NI 5441 Specifications
NI PXI-5441 16-Bit 100 MS/s Arbitrary Waveform Generator
with Onboard Signal Processing (OSP)
Unless otherwise noted, the following conditions were used for each
specification:
•
•
Analog Filter enabled.
DAC Interpolation set to maximum allowed factor for a given sample
rate.
•
•
Signals terminated with 50 Ω.
Direct Path set to 1 Vpk-pk, Low-Gain Amplifier Path set to 2 Vpk-pk
,
and High-Gain Amplifier Path set to 12 Vpk-pk
.
•
Sample clock set to 100 MS/s.
Typical values are representative of an average unit operating at room
temperature (25 °C 3 °C). Specifications are subject to change without
notice. For the most recent NI 5441 specifications, visit
ni.com/manuals.
To access all the NI 5441 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5441 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.
Hot Surface If the NI 5441 has been in use, it may exceed safe handling temperatures and
Phase-Locked Loop (PLL) Reference Clock.......................................... 17
CLK IN ................................................................................................... 18
PFI 0 and PFI 1 ....................................................................................... 19
DIGITAL DATA & CONTROL (DDC) ................................................ 20
Start Trigger ............................................................................................ 22
Markers ................................................................................................... 24
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Specification
Value
Comments
Amplitude and Offset
Amplitude
Range
Path
Amplitude (Vpk-pk
)
1. Amplitude
values assume
the full scale
of the DAC is
utilized. If an
amplitude
Load
50 Ω
1 kΩ
Minimum Value
0.707
Maximum Value
Direct
1.00
1.91
1.35
smaller than
the minimum
value is
desired, then
waveforms
less than full
scale of the
DAC can be
used.
Open
50 Ω
1 kΩ
Open
50 Ω
1 kΩ
Open
1.41
2.00
2.00
3.81
4.00
12.0
22.9
24.0
Low-
Gain
Amplifier
0.00564
0.0107
0.0113
0.0338
0.0644
0.0676
High-
Gain
Amplifier
2. NI-FGEN
compensates
for user-
specified
Amplitude
Resolution
3 digits
—
Offset
Range
Span of 25% of Amplitude Range with increments
<0.0014% of Amplitude Range.
Not available on
the Direct Path.
Maximum Output Voltage
Maximum
Output
Voltage
Path
Load
Maximum Output Voltage (Vpk-pk
)
The Maximum
Output Voltage
of the NI 5441 is
determined by
the Amplitude
Range and the
Offset Range.
Direct
50 Ω
1 kΩ
Open
50 Ω
1 kΩ
Open
50 Ω
1 kΩ
Open
0.500
0.953
1.000
1.000
1.905
2.000
6.000
11.43
12.00
Low-
Gain
Amplifier
High-
Gain
Amplifier
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Specification
Accuracy
Value
Comments
DC Accuracy
For the Low-Gain or High-Gain Amplifier Path:
All paths are
calibrated for
amplitude and
gain errors. The
Low-Gain and
High-Gain
0.2% of Amplitude 0.05% of Offset 500 µV
(within 10 °C of self-calibration temperature)
0.4% of Amplitude 0.05% of Offset 1 mV
(0 °C to 55 °C)
Amplifier Paths
also are
For the Direct Path:
calibrated for
offset errors.
Gain Accuracy: 0.2% (within 10 °C of self-calibration
temperature)
Gain Accuracy: 0.4% (0 °C to 55 °C)
DC Error: 30 mV (0 °C to 55 °C)
AC Amplitude
Accuracy
1.0% of Amplitude 1 mV
50 kHz sine
wave.
Output Characteristics
Output
Impedance
50 Ω nominal or 75 Ω nominal, software-selectable.
—
—
Load
Impedance
Compensation
Output amplitude is compensated for user-specified load
impedances.
Output
Coupling
DC
—
—
Output
Enable
Software-selectable. When disabled, CH 0 out is terminated
with a 1 W resistor with a value equal to the selected output
impedance.
Maximum
Output
Overload
The CH 0 output can be connected to a 50 Ω, 12 V
( 8 V for the Direct Path) source without sustaining any
damage. No damage occurs if the CH 0 output is shorted to
ground indefinitely.
—
—
Waveform
Summing
The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5441
signal generators can be connected together.
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Specification
Value
Comments
Frequency and Transient Response
Bandwidth
43 MHz
Measured at
–3 dB.
DAC Digital
Interpolation
Filter
Software-selectable Finite Impulse Response (FIR) filter.
Available interpolation factors are 2, 4, or 8.
Refer to the
Onboard Signal
Processing
section for OSP
Interpolation.
Analog
Filter
Software-selectable 7-pole elliptical filter for image
suppression.
Available only
on Low-Gain
Amplifier and
High-Gain
Amplifier Paths.
Passband
Flatness
Path
—
Direct
Low-Gain
Amplifiers
High-Gain
Amplifiers
+0.6 dB to –0.4 dB +0.5 dB to –1.0 dB +0.5 dB to –1.2 dB
100 Hz to 40 MHz 100 Hz to 20 MHz 100 Hz to 20 MHz
Pulse
Response
Path
Analog Filter
and DAC
Interpolation
Filter disabled.
Low-Gain
Amplifier
High-Gain
Amplifier
Direct
Rise/Fall Time
Aberration
<5 ns
<10%
<8 ns
<5%
<10 ns
<5%
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2.0
1.0
+0.6 dB
–0.4 dB
+0.4 dB
–0.4 dB
+0.3 dB
–0.4 dB
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
Guaranteed Specification
Typical
–10.0
1.0M
10.0M
48.0M
Frequency (Hz)
Figure 1. Normalized Passband Flatness, Direct Path
2.0
1.6
1.2
0.8
0.4
0.0
–0.4
–0.8
–1.2
–1.6
–2.0
0.0
20.0n
40.0n
60.0n
80.0n
100.0n
Time (s)
Figure 2. Pulse Response, Low-Gain Amplifier Path 50 Ω Load
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5.0
2.5
0.0
–2.5
–5.0
–7.5
–10.0
–12.5
–15.0
–17.5
–20.0
–22.5
–25.0
–27.5
–30.0
0.0
20.0M
40.0M
60.0M
80.0M 100.0M 120.0M 140.0M 160.0M 180.0M 200.0M
Frequency (Hz)
Figure 3. Frequency Response of Direct Path, 100 MS/s, 1x DAC Interpolation
Note Above 50 MHz, the response is the image response.
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Specification
Value
Comments
Suggested Maximum Frequencies for Common Functions
Function
Path
Disable the
Analog Filter
and the DAC
Interpolation
Filter for Square,
Ramp, and
Low-Gain
Amplifier
High-Gain
Amplifier
Direct
Sine
43 MHz
43 MHz
25 MHz
5 MHz
5 MHz
43 MHz
12.5 MHz
5 MHz
Square Not recommended*
Ramp Not recommended*
Triangle Not recommended*
Triangle.
* Direct Path is
optimizedforthe
frequency
5 MHz
domain.
Spectral Characteristics
Signal to
Noise and
Distortion
Path
Amplitude
–1 dBFS.
Low-Gain
Amplifier
High-Gain
Amplifier
Measured from
DC to 50 MHz.
SINAD at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
(SINAD)
Direct
64 dB
61 dB
57 dB
60 dB
60 dB
58 dB
1 MHz
66 dB
60 dB
56 dB
62 dB
62 dB
60 dB
63 dB
47 dB
42 dB
62 dB
62 dB
55 dB
10 MHz
20 MHz
30 MHz
40 MHz
43 MHz
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Specification
Value
Comments
Amplitude
Spurious-Free
Dynamic
Path
–1 dBFS.
Range
(SFDR) with
Harmonics
Measured from
DC to 50 MHz.
Also called
Low-Gain
Amplifier
High-Gain
Amplifier
Direct
harmonic
distortion.
SFDR with
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
1 MHz
10 MHz
20 MHz
30 MHz
40 MHz
43 MHz
–76 dBc
–68 dBc
–60 dBc
–73 dBc
–76 dBc
–78 dBc
–71 dBc
–64 dBc
–57 dBc
–73 dBc
–73 dBc
–75 dBc
–58 dBc
–47 dBc
–42 dBc
–74 dBc
–74 dBc
–59 dBc
typical and
include aliased
harmonics.
SFDR without
Harmonics
Path
Amplitude
–1 dBFS.
Low-Gain
Amplifier
High-Gain
Amplifier
Measured from
DC to 50 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
Direct
1 MHz
10 MHz
20 MHz
30 MHz
40 MHz
43 MHz
–88 dBFS
–87 dBFS
–80 dBFS
–73 dBFS
–76 dBFS
–78 dBFS
–91 dBFS
–89 dBFS
–89 dBFS
–73 dBFS
–73 dBFS
–75 dBFS
–91 dBFS
–91 dBFS
–89 dBFS
–74 dBFS
–74 dBFS
–60 dBFS
typical and
include aliased
harmonics.
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Specification
Value
Comments
Amplitude
0 ºC to 40 ºC
Total
Harmonic
Distortion
(THD)
Path
–1 dBFS.
Includes the 2nd
through the 6th
harmonic.
Low-Gain
Amplifier
High-Gain
Amplifier
Direct
–77 dBc
(typical)
20 kHz
–77 dBc (typical)
–77 dBc (typical)
–70 dBc
(typical)
1 MHz
5 MHz
–75 dBc (typical)
–68 dBc
–62 dBc (typical)
–55 dBc
–68 dBc
–61 dBc
–53 dBc
–48 dBc
–46 dBc
–45 dBc
Path
10 MHz
20 MHz
30 MHz
40 MHz
43 MHz
–65 dBc
–46 dBc
–55 dBc
–40 dBc
–50 dBc
–38 dBc
–48 dBc
–34 dBc
–47 dBc
–33 dBc
0 ºC to 55 ºC
Amplitude
THD
–1 dBFS.
Low-Gain
Amplifier
High-Gain
Amplifier
Includes the 2nd
through the 6th
harmonic.
Direct
–76 dBc
(typical)
20 kHz
–76 dBc (typical)
–76 dBc (typical)
–69 dBc
(typical)
1 MHz
5 MHz
–74 dBc (typical)
–67 dBc
–61 dBc (typical)
–54 dBc
–67 dBc
–60 dBc
–52 dBc
–46 dBc
–41 dBc
–41 dBc
10 MHz
20 MHz
30 MHz
40 MHz
43 MHz
–63 dBc
–45 dBc
–54 dBc
–39 dBc
–48 dBc
–36 dBc
–46 dBc
–32 dBc
–45 dBc
–31 dBc
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Specification
Value
Comments
Spectral Characteristics (Continued)
AverageNoise
Density
Amplitude
Range
Average
Noise Density
Average Noise
Density at small
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
nV
dBFS/
Hz
----------
Path
Vpk-pk
dBm
Hz
18
9
dBm/Hz
–142
–148
–148
–145
–142
–136
–130
–120
Direct
1
0.06
0.1
0.4
1
4.0
–20.4
–16.0
–4.0
4.0
–146.0
–127.6
–132.0
–141.0
–146.0
–146.0
–146.0
–145.6
Low Gain
Low Gain
Low Gain
Low Gain
Low Gain
High Gain
High Gain
9
13
18
35
71
213
2
10.0
16.0
25.6
4
12
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10.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
25.0M
50.0M
75.0M
100.0M
125.0M
158.0M
175.0M
200.0M
Frequency (Hz)
Figure 4. 10 MHz Single-Tone Spectrum, Direct Path, 100 MS/s, DAC Interpolation Factor Set to 4
Note The noise floor in Figure 4 is limited by the measurement device. Refer to the
Average Noise Density specifications.
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20.0
10.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
25.0M
50.0M
75.0M
100.0M
125.0M
150.0M
175.0M
200.0M
Figure 5. 10 MHz Single-Tone Spectrum, Low-Gain Amplifier Path, 100 MS/s, DAC Interpolation Factor Set to 4
Note The noise floor in Figure 5 is limited by the measurement device. Refer to the
Average Noise Density specifications.
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10.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
25.0M
50.0M
75.0M
100.0M
125.0M
150.0M
175.0M
200.0M
Frequency (Hz)
Figure 6. Direct Path, 2-Tone Spectrum (Typical)
Note The noise floor in Figure 6 is limited by the measurement device. Refer to the
Average Noise Density specifications.
Sample Clock
Specification
Value
Comments
Sources
1. Internal, Divide-by-N (N ≥ 1)
Refer to the
Onboard Clock
section for more
information
2. Internal, DDS-based, High-Resolution
3. External, CLK IN (SMB front panel connector)
4. External, DDC CLK IN (DIGITAL DATA &
CONTROL front panel connector)
about internal
clock sources.
5. External, PXI Star trigger (backplane connector)
6. External, PXI_Trig<0..7> (backplane connector)
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Specification
Value
Comments
Sample Rate Range and Resolution
Sample Clock
—
Source
Sample Rate Range
Sample Rate Resolution
Divide-by-N
23.84 S/s to 100 MS/s
10 S/s to 100 MS/s
Settable to (100 MS/s) / N
(1 ≤ N ≤ 4,194,304)
High
1.06 µHz
Resolution
CLK IN
200 kS/s to 105 MS/s
10 S/s to 105 MS/s
10 S/s to 105 MS/s
Resolution determined by
external clock source.
DDC CLK IN
External Sample Clock duty
cycle tolerance 40% to 60%.
PXI Star
Trigger
PXI_Trig<0..7>
10 S/s to 20 MS/s
DAC Effective Sample Rate
Sample Rate
DAC
Interpolation
Factor
Effective Sample DAC Effective
(MS/s)
Rate
Sample Rate =
(DAC
Interpolation
Factor) ×
(Sample Rate)
10 S/s to
105 MS/s
1 (Off)
10 S/s to
105 MS/s
12.5 MS/s to
105 MS/s
2
4
8
25 MS/s to
210 MS/s
Refer to the
Onboard Signal
Processing
section for OSP
Interpolation.
10 MS/s to
100 MS/s
40 MS/s to
400 MS/s
10 MS/s to
50 MS/s
80 MS/s to
400 MS/s
Sample Clock Delay Range and Resolution
Sample Clock
Source
Delay Adjustment
Resolution
—
Delay Adjustment Range
1 sample clock period
1 sample clock period
Divide-by-N
<10 ps
High-
Resolution
Sample Clock
Period/16,384
External (all)
0 ns to 7.6 ns
<15 ps
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Specification
Value
Comments
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
System Phase Noise
Density
(dBc/Hz) Offset
1. High-
Resolution
System Output Jitter
(Integrated from
100 Hz to 100 kHz)
specifications
increase as the
SampleRateis
decreased.
100 Hz 1 kHz 10 kHz
Divide-by-N
–110
–114
–131
–126
–137
–126
<1.0 ps rms
<4.0 ps rms
2. PXI Star
High-
Resolution1
trigger
specification
is valid when
the Sample
Clock Source
is locked to
PXI_CLK10.
CLK IN
–113
–115
–132
–118
–135
–130
<1.1 ps rms
<3.0 ps rms
PXI Star
Trigger2
External
Cycle-Cycle Jitter 300 ps
Period Jitter 1 ns
—
Sample Clock
Input Jitter
Tolerance
Sample Clock Exporting
Exported
Sample Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
Exported Sample
Clocks can be
dividedbyinteger
K (1 ≤ K ≤
2. DDC CLK OUT (DIGITAL DATA & CONTROL front
panel connector)
3. PXI_Trig<0..7> (backplane connector)
4,194,304).
Exported
—
Sample Clock
Destinations
Maximum
Frequency
105 MHz
Jitter (Typical)
PFI 0: 6 ps rms
PFI 1: 12 ps rms
40 ps rms
Duty Cycle
25% to 65%
PFI<0..1>
DDC CLK
OUT
105 MHz
20 MHz
40% to 60%
—
PXI_Trig<0..7>
—
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Onboard Clock
(Internal VCXO)
Specification
Value
Comments
Clock Source
Internal sample clocks can either be locked to a Reference
Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.
—
Frequency
Accuracy
25 ppm
—
Phase-Locked Loop (PLL) Reference Clock
Specification
Value
Comments
Sources
1. PXI_CLK10 (backplane connector)
2. CLK IN (SMB front panel connector)
The PLL
Reference Clock
provides the
reference
frequency for the
PLL.
Frequency
Accuracy
When using the PLL, the Frequency Accuracy of the
NI 5441 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.
—
Lock Time
Typical: 70 ms.
Maximum: 200 ms.
—
—
Frequency
Range
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate
to 50 ppm.
Duty Cycle
Range
40% to 60%
—
—
Exported PLL
Reference
Clock
1. PFI<0..1> (SMB front panel connectors)
2. PXI_Trig<0..7> (backplane connector)
Destinations
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CLK IN
(Sample Clock and Reference Clock Input, Front Panel Connector)
Specification
Connector
Value
Comments
SMB (jack)
Input
—
—
—
Direction
Destinations
1. Sample Clock
2. PLL Reference Clock
Frequency
Range
1 MHz to 105 MHz (Sample Clock destination and
sine waves)
—
200 kHz to 105 MHz (Sample Clock destination and
square waves)
5 MHz to 20 MHz (PLL Reference Clock destination)
Input Voltage
Range
Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk into 50 Ω
(0 dBm to +13 dBm)
—
Square wave: 0.2 Vpk-pk to 2.8 Vpk-pk into 50 Ω
Maximum
Input Overload
10 V
—
—
—
Input
Impedance
50 Ω
Input Coupling AC
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PFI 0 and PFI 1
(Programmable Function Interface, Front Panel Connectors)
Specification
Connectors
Direction
Value
Comments
Two SMB (jacks)
Bidirectional
—
—
—
Frequency
Range
DC to 105 MHz
As an Input (Trigger)
Destinations
Start Trigger
—
—
Maximum
–2 V to +7 V
Input Overload
VIH
VIL
2.0 V
0.8 V
1 kΩ
—
—
—
Input
Impedance
As an Output (Event)
Sources
1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)
—
2. Sample Clock Timebase (100 MHz) divided by integer
M (2 ≤ M ≤ 4,194,304)
3. PLL Reference Clock
4. Marker
5. Exported Start Trigger (Out Start Trigger)
Output
Impedance
50 Ω
—
—
Maximum
Output
–2 V to +7 V
Overload
VOH
VOL
Minimum: 2.9 V (open load), 1.4 V (50 Ω load)
Outputdriversare
+3.3 V TTL
compatible.
Maximum: 0.2 V (open load), 0.2 V (50 Ω load)
Measured with a
1 m cable.
Rise/Fall Time ≤2.0 ns
Load of 10 pF.
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DIGITAL DATA & CONTROL (DDC)
Optional Front Panel Connector
Specification
Value
Comments
Connector
Type
68-pin VHDCI female receptacle
—
Number of
Data Output
Signals
16
—
—
Control
Signals
1. DDC CLK OUT (clock output)
2. DDC CLK IN (clock input)
3. PFI 2 (input)
4. PFI 3 (input)
5. PFI 4 (output)
6. PFI 5 (output)
Ground
23 pins
—
Output Signal Characteristics (Includes Data Outputs, DDC CLK OUT, and PFI<4..5>)
Signal Type
LVDS (Low-Voltage Differential Signal)
—
Signal
Characteristics
1. Tested with
100 Ω
Minimum
Typical
1.3 V
1.0 V
—
Maximum
differential
load.
VOH
VOL
—
1.7 V
—
0.8 V
0.25 V
2. Measured at
the front
Differential
Output Voltage
0.45 V
panel.
3. Load
Output
Common-Mode
Voltage
1.125 V
—
—
—
1.375 V
0.6 ns
capacitance
<15 pF.
4. Driver and
receiver
Differential
Pulse Skew
(skew within
a differential
pair)
comply with
ANSI/TIA/
EIA-644.
Rise/Fall Time
—
0.5 ns
1.6 ns
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Specification
Value
Comments
Output Signal Characteristics (Continued)
Output Skew
Output
Typical: 1 ns, maximum 2 ns. Skew between any
two outputs on the DIGITAL DATA & CONTROL
front panel connector.
—
Controlled through the software on all Data Output Signals
—
—
Enable/Disable and Control Signals collectively. When disabled, the outputs
go to a high-impedance state.
Maximum
Output
–0.3 V to +3.9 V
Overload
Input Signal Characteristics (Includes DDC CLK IN and PFI<2..3>)
Signal Type
LVDS (Low-Voltage Differential Signal)
—
—
Input
100 Ω
Differential
Impedance
Maximum
Output
Overload
–0.3 V to +3.9 V
—
—
Signal
Characteristics
Minimum
0.1 V
Maximum
Differential
0.5 V
Input Voltage
Input Common
Mode Voltage
0.2 V
2.2 V
DDC CLK OUT
Clocking
Format
Data outputs and markers change on the falling edge of
DDC CLK OUT.
—
—
Frequency
Range
Refer to the Sample Clock section for more information.
Duty Cycle
Jitter
40% to 60%
40 ps rms
—
—
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Specification
DDC CLK IN
Value
Comments
Clocking
Format
DDC Data Output signals change on the rising edge of
DDC CLK IN.
—
—
—
Frequency
Range
10 Hz to 105 MHz
Input Duty
Cycle
40% to 60%
Tolerance
Input Jitter
Tolerances
300 ps pk-pk of Cycle-Cycle Jitter, and 1 ns rms of
Period Jitter.
—
Start Trigger
Specification
Value
Comments
Sources
1. PFI<0..1> (SMB front panel connectors)
—
2. PFI<2..3> (DIGITAL DATA & CONTROL front panel
connector)
3. PXI_Trig<0..7> (backplane connector)
4. PXI Star trigger (backplane connector)
5. Software (use function call)
6. Immediate (does not wait for a trigger). Default.
Modes
1. Single
—
2. Continuous
3. Stepped
4. Burst
Edge Detection Rising
—
—
Minimum
25 ns. Refer to the ts1 documentation in the NI Signal
Pulse Width
Generators Help by navigating to NI Signal Generators
Help»Devices»NI 5441»Triggering»Trigger Timing.
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Specification
Value
Comments
Delay from
DAC Interpolation Factor
Typical Delay
Refer to the ts2
documentation in
the NI Signal
Generators Help
by navigating to
NI Signal
Generators
Help»Devices»
NI 5441»
Start Trigger to
CH 0 Analog
Output with
Digital Interpolation Filter
disabled.
44 Sample Clock
Periods + 110 ns
OSP Disabled.
2
4
8
58 Sample Clock
Periods + 110 ns
64 Sample Clock
Periods + 110 ns
Triggering»
Trigger Timing.
65 Sample Clock
Periods + 110 ns
Delay from
40 Sample Clock periods + 110 ns.
—
Start Trigger to
Digital Data
Output with
OSP Disabled.
Additional
Delay for
Function
Generator
Mode.
Add 33 Sample Clock Periods
—
(Applicable to Delay from Start Trigger to CH0 Analog
Output and Delay from Start Trigger to Digital Data
Output.)
Additional
Delay with
OSP Enabled.
Add 70 Sample Clock Periods for Real data processing
mode
FIR and CIC
filters enabled.
Add 73 Sample Clock Periods for Complex data processing
mode.
Output.)
Trigger Exporting
Exported
Trigger
Destinations
A signal used as a trigger can be routed out to any
destination listed in the Destinations specification of the
Markers section.
—
—
Exported
Trigger Delay
65 ns (typical). Refer to the ts3 documentation in the
NI Signal Generators Help by navigating to NI Signal
Generators Help»Devices»NI 5441»Triggering»Trigger
Timing.
Exported
Trigger Pulse
Width
>150 ns. Refer to the ts4 documentation in the NI Signal
Generators Help by navigating to NI Signal Generators
Help»Devices»NI 5441»Triggering»Trigger Timing.
—
© National Instruments Corporation
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Markers
Specification
Value
Comments
Destinations
1. PFI<0..1> (SMB front panel connectors)
—
2. PFI<4..5> (DIGITAL DATA & CONTROL front panel
connector)
3. PXI_Trig<0..6> (backplane connector)
One Marker per Segment.
Quantity
Quantum
—
—
Marker position must be placed at an integer multiple of
four samples (two samples for Complex (IQ) data).
Width
>150 ns. Refer to the tm2 documentation in the NI Signal
Generators Help by navigating to NI Signal Generators
Help»Devices»NI 5441»Waveform Generation»Marker
Events.
—
Skew
With Respect to
Digital Data
Output
Refer to the tm1
documentation in
the NI Signal
Generators Help
by navigating to
NI Signal
With Respect to
Analog Output
Destination
PFI<0..1>
2 Sample Clock
Periods
N/A
Generators
Help»Devices»
NI 5441»
PFI<4..5>
N/A
<2 ns
N/A
PXI_Trig<0..6>
2 Sample Clock
Periods
Waveform
Generation»
Marker Events.
Jitter
20 ps rms
—
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Arbitrary Waveform Generation Mode
Specification
Value
Comments
For more
information,
refer to the
Memory Usage The NI 5441 uses the Synchronization and Memory Core
(SMC) technology in which waveforms and instructions
share onboard memory. Parameters, such as number of
segments in sequence list, maximum number of waveforms NI Signal
in memory, and number of samples available for waveform Generators Help
storage, are flexible and user defined.
by navigating to
NI Signal
Generators
Help»
Programming»
NI-TClk
Synchronization
Help.
Onboard
32 MB option:
256 MB option:
512 MB option:
—
Memory Size
33,554,432 bytes 268,435,456 bytes 536,870,912 bytes
Output Modes
Arbitrary Waveform mode and Arbitrary Sequence mode
—
—
Arbitrary
Waveform
Mode
In Arbitrary Waveform mode, a single waveform is selected
from the set of waveforms stored in onboard memory and
generated.
Arbitrary
Sequence
Mode
In Arbitrary Sequence mode, a sequence directs the NI 5441
to generate a set of waveforms in a specific order. Elements
of the sequence are referred to as segments. Each segment is
associated with a set of instructions. The instructions
identify which waveform is selected from the set of
waveforms in memory, how many loops (iterations) of the
waveform are generated, and at which sample in the
waveform a marker output signal is sent.
—
© National Instruments Corporation
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Specification
Value
Comments
Minimum
WaveformSize
(Samples)
Arbitrary
Waveform Mode
Arbitrary
Sequence Mode
The Minimum
Waveform Size
is sample rate
dependent in
Arbitrary
Trigger Mode
Single
16
16
16
Continuous
96 @ >50 MS/s
32 @ ≤50 MS/s
96 @ >50 MS/s
32 @ ≤50 MS/s
512 @ >50 MS/s
256 @ ≤50 MS/s
Sequence mode.
ForComplex(IQ)
data Minimum
Waveform Size is
halved.
Stepped
Burst
32
16
Loop Count
Quantum
1 to 16,777,215.
Burst trigger: Unlimited
—
—
Waveform size must be an integer multiple of four samples
(two samples for Complex (IQ) data).
Memory Limits
32 MB Option
256 MB Option
512 MB Option
All trigger modes
except where
noted.
Arbitrary
Waveform
Mode,
Maximum
Waveform
Memory
16,777,088
Samples
134,217,600
Samples
268,435,328
Samples
For Complex
(IQ) data
Maximum
Waveform
Memory is
halved.
Arbitrary
Sequence
Mode,
16,777,008
Samples
134,217,520
Samples
268,435,200
Samples
Condition: One
or two segments
in a sequence.
Maximum
Waveform
Memory
For Complex
(IQ) data
Maximum
Waveform
Memory is
halved.
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Specification
Value
Comments
Memory Limits (Continued)
Arbitrary
Sequence
Mode,
Maximum
Waveforms
262,000
2,097,000
4,194,000
Condition: One
or two segments
in a sequence.
Burst trigger:
32,000
Burst trigger:
262,000
Burst trigger:
524,000
Arbitrary
Sequence
Mode,
Maximum
Segments in a
Sequence
418,000
3,354,000
6,708,000
Condition:
Waveform
memory is
<4,000 samples.
(<2,000 samples
for Complex (IQ)
Data.)
Burst trigger:
262,000
Burst trigger:
2,090,000
Burst trigger:
4,180,000
Waveform Play Times
32 MB
256 MB
512 MB
MaximumPlay
Time, Sample
Rate = 100
MS/s, OSP
Disabled
0.16 seconds
1.34 seconds
2.68 seconds
Single Trigger
Mode.
Play Times can
be significantly
extendedbyusing
Continuous,
Stepped, or Burst
Trigger Modes.
MaximumPlay
Time, IQ Rate
= 1 MS/s,
16 seconds
2 m i n u t e s a n d
14 seconds
4 m i n u t e s a n d
28 seconds
Real Mode,
OSP Enabled
ForComplex(IQ)
Mode the Play
Times are halved.
MaximumPlay
Time, IQ Rate
= 100 kS/s,
2 m i n u t e s a n d
47 seconds
2 2 m i n u t e s a n d
22 seconds
4 4 m i n u t e s a n d
43 seconds
Real Mode,
OSP Enabled
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Function Generation Mode
Specification
Value
Comments
Standard
Waveform
Sine
Maximum Frequency
43 MHz
25 MHz
5 MHz
—
Waveforms
and Maximum
Frequencies
Square
Triangle
Ramp Up
5 MHz
Ramp Down
DC
5 MHz
—
Noise (Pseudo-Random)
User Defined
5 MHz
43 MHz
Memory Size
65,536 Samples for 1/4 symmetric waveforms
(Example: Sine)
16-bit samples.
User Defined
Waveforms must
be exactly 16,384
samples.
16, 384 Samples for non-1/4 symmetric waveforms
(Example: Ramp)
Frequency
Resolution
355 nHz
0.0055º
—
Phase
—
Resolution
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Onboard Signal Processing
Onboard Signal Processing
Pre-Filter
Gain I
Pre-Filter
Offset I
I FIR
I CIC
X
Digital
Gain
DAC
Interpolation
Waveform
Memory
Output
Engine
IQ
Rate
–
DAC
Pre-Filter
Gain Q
Pre-Filter
Offset Q
Q FIR
Q CIC
X
Iφ
Qφ
NCO
IQ Rate
Rate Change
Sample Rate
Rate Change
Effective
(OSP Interpolation)
Sample Rate
Figure 7. Onboard Signal Processing Block Diagram
Specification
IQ Rate
Value
Comments
OSP
12 to 512 (Multiples of 2)
Total
Interpolation
Range
512 to 1,024 (Multiples of 4)
1,024 to 2,048 (Multiples of 8)
NI PXI-5441
Interpolation =
OSP
Interpolation ×
DAC
(OSP Interpolation = FIR Interpolation × CIC Interpolation)
Interpolation.
IQ Rate
Sample Rate/OSP Interpolation
Example:Fora
(Lower IQ Rates are possible by either lowering the sample rate Sample Rate
or doing software interpolation)
of 100 MS/s,
IQ Rate Range
= 48.8 kS/s to
8.3 MS/s
Data
Processing
Modes
1. Real (I path only)
2. Complex (IQ)
—
Pre-Filter Gain and Offset
Pre-FilterGain 18 Bits
and Offset
—
Resolution
Pre-FilterGain –2.0 to +2.0
Unitless
Range
(Values < |1| attenuate User Data)
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Specification
Value
Comments
Pre-Filter
–1.0 to +1.0
Applied after
Offset Range
Pre-Filter Gain
Output
Output = (User Data × Pre-Filter Gain) + Pre-Filter Offset
(–1 ≤ Output ≤ +1)
Pre-Filter
Output
FIR (Finite Impulse Response) Filter
Filter Length
95 Taps
The FIR Filter
is used to pulse
shape the IQ
Coefficient
Width
17 bits (–1 to +1)
compensate
for the CIC
Filter roll-off.
Filter
Symmetry
Symmetric
2, 4, or 8
Interpolation
Range
Coefficients
Automatically generated by NI-FGEN (refer to FIR Filter
Types) or Custom Coefficients provided by the user
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Specification
FIR Filter Types
Filter Type
Value
Comments
Parameter
—
Minimum
—
Maximum
—
—
Custom
Coefficients
are provided
by the user.
Flat
Passband
0.1
0.43
Lowpass Filter
that minimizes
ripple to:
IQ Rate ×
Passband.
Gaussian
BT
0.1
0.1
0.1
0.9
0.9
0.9
—
Raised Cosine
Alpha
Alpha
Root Raised
Cosine
CIC (Cascaded Integrator-Comb) Filter
Size
6 Stages
6 ≤ Interpolation ≤ 256 (integers)
The CIC Filter
does the
majority of the
interpolation
in the OSP.
Interpolation
Range
NCO (Numerically Controlled Oscillator)
Frequency
Range
1 mHz to (0.43 × Sample Rate)
—
Frequency
Resolution
Sample Rate / 248
Example:
355 nHzwitha
Sample Rate
of 100 MS/s
I and Q Phase
Resolution
0.0055º
16 bits
—
Phase
Quantization
Look-Up
Table Address
Width
Tuning Speed
1 ms
—
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Specification
Value
Comments
Modulation Performance (Typical)
Modulation
Configuration
Measurement Type
FIR Interpolation
4
—
2
8
GSM Physical MER
46 dB
47 dB
42 dB
Direct Path
( 4 d B m P e a k ) ,
25 MHz
Layer1
(Modulation Error Ratio)
EVM
<0.5 % <0.5 % <0.8 %
rms
Carrier
(Error Vector Magnitude)
rms
rms
W-CDMA
Physical
Layer2
MER
46 dB
39 dB
—
Direct Path
( 4 d B m P e a k ) ,
25 MHz
Carrier, ACPR
Measurement
BW = 4 MHz
& Channel
Spacing =
(Modulation Error Ratio)
EVM
<0.5 % <1.0 %
rms rms
—
—
(Error Vector Magnitude)
ACPR
65 dBc 68 dBc
(Adjacent Channel Power
Ratio)
(External Sample Clock)
5 MHz
ACPR
61 dBc 61 dBc
—
(Adjacent Channel Power
Ratio)
(High-Resolution Sample
Clock)
DVB Physical
Layer3
MER
43 dB
—
—
—
—
—
—
Direct Path
( 4 d B m P e a k ) ,
25 MHz
Carrier, ACPR
Measurement
BW =
(Modulation Error Ratio)
EVM
<0.6 %
rms
(Error Vector Magnitude)
ACPR
48 dBc
(Adjacent Channel Power
Ratio)
7.96 MHz &
Channel
(External Sample Clock)
Spacing =
8 MHz
ACPR
47 dBc
—
—
(Adjacent Channel Power
Ratio)
(High-Resolution Sample
Clock)
1 OSP Enabled. IQ Rate = 1.083 MS/s, 4 Samples/Symbol. FIR Filter Type = Flat, Passband = 0.4. MSK modulation:
Software Pulse Shaping and Phase Accumulation, 270.833 kS/s, Gaussian, BT = 0.3. PN Sequence Order = 14.
2 OSP Enabled. IQ Rate = 3.84 MS/s, 1 Sample/Symbol. FIR Filter Type = Root Raised Cosine, Alpha = 0.22. QPSK.
PN Sequence Order = 15.
3 OSP Enabled. IQ Rate = 6.92 MS/s, 1 Sample/Symbol. FIR Filter Type = Root Raised Cosine, Alpha = 0.15. 32 QAM
Modulation. PN Sequence Order = 15.
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Specification
Value
Comments
Digital Performance
Maximum
NCO Spur
< –90 dBc
Full-Scale Output
—
FIR
Interpolation
IQ Rate Range
(with 100 MS/s
Sample Clock
Rate)
OSP Out of Band
Suppression
OSP Passband
Ripple
2
4
8
195 kS/s to
8.33 MS/s
63 dB
74 dB
40 dB
0 to –0.08 dB
0 to –0.08 dB
0 to –0.8 dB
FIR Filter Type =
Flat. Passband =
0.4. Ripple
Measurement to
0.4 × IQ Rate.
Stop Band
97.6 kS/s to
4.16 MS/s
48.8 kS/s to
2.08 MS/s
Suppression from
0.6 × IQ Rate.
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Figure 8. GSM Physical Layer1
External Sample Clocking = 99.665 MHz
Figure 9. GSM Physical Layer1
Internal (High Resolution) Sample Clocking = 99.665 MHz
Additional artifacts are due to High Resolution Clock spurs.
1
OSP Enabled. Direct Path (4 dBm Peak). 25 MHz Carrier. IQ Rate = 1.083 MS/s, 4 Samples/Symbol. FIR Filter Type = Flat,
Passband = 0.4. Software MSK modulation: 270.833 kS/s, Gaussian, BT = 0.3. PN Sequence Order = 14.
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Figure 10. CDMA 2000 Physical Layer1
External Sample Clocking = 98.304 MHz
Figure 11. CDMA 2000 Physical Layer1
Internal (High Resolution) Sample Clocking = 98.304 MHz
Additional artifacts are due to High Resolution Clock spurs.
1
OSP Enabled. Direct Path (4 dBm Peak). 25 MHz Carrier. IQ Rate = 1.2288 MS/s, 1 Sample/Symbol. FIR Filter Type =
Custom Flat Filter with Passband = 0.48. QPSK. PN Sequence Order = 15.
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Figure 12. W-CDMA Physical Layer1
External Sample Clocking = 92.16 MHz
Figure 13. W-CDMA Physical Layer1
Internal (High Resolution) Sample Clocking = 92.16 MHz
Additional artifacts are due to High Resolution Clock spurs.
1
OSP Enabled. Direct Path (4 dBm Peak). 25 MHz Carrier. IQ Rate = 3.84 MS/s, 1 Sample/Symbol. FIR Filter Type = Root
Raised Cosine, Alpha = 0.22. QPSK. PN Sequence Order = 15.
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Figure 14. DVB Physical Layer1
External Sample Clocking = 96.88 MHz
Artifacts at 15 and 35 MHz are due to 2x FIR Interpolation aliasing.
Figure 15. DVB Physical Layer1
Internal (High Resolution) Sample Clocking = 96.88 MHz
Artifact at 10 MHz is due to CLK IN feed-through.
Additional artifacts are due to High Resolution Clock spurs.
1
OSP Enabled. Direct Path (4 dBm Peak). 25 MHz Carrier. IQ Rate = 6.92 MS/s, 1 Sample/Symbol. FIR Filter Type = Root
Raised Cosine, Alpha = 0.15. 32 QAM Modulation. PN Sequence Order = 15.
© National Instruments Corporation
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Calibration
Specification
Value
Comments
Self-Calibration An onboard, 24-bit ADC and precision voltage reference are
used to calibrate the DC gain and offset. The self-calibration
is initiated by the user through the software and takes
approximately 75 seconds to complete.
—
External
Calibration
The External Calibration calibrates the VCXO, voltage
reference, output impedance, DC gain, and offset.
Appropriate constants are stored in nonvolatile memory.
—
Calibration
Interval
Specifications valid within 2 years of External Calibration.
—
—
Warm-up Time 15 minutes
Power
Specification
+3.3 VDC
+5 VDC
Typical Operation
Overload Operation
Comments
1.9 A
2.2 A
2.7 A
2.4 A
Typical.
Overload
operation occurs
when CH 0 is
shorted to
+12 VDC
0.46 A
0.01 A
22.9 W
0.5 A
–12 VDC
0.01 A
27.0 W
ground.
Total Power
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Software
Specification
Value
Comments
Driver
Software
NI-FGEN 2.3 or later version. NI-FGEN is an
IVI-compliant driver that allows you to configure, control,
and calibrate the NI 5441. NI-FGEN provides application
programming interfaces for many development
environments.
—
Application
Software
NI-FGEN provides programming interfaces for the
following application development environments:
—
•
•
•
•
•
•
LabVIEW
LabWindows™/CVI™
Measurement Studio
Microsoft Visual C++ .NET
Microsoft Visual C/C++
Microsoft Visual Basic
Interactive
Control and
Configuration
Software
NI provides several options for interactively controlling and
configuring the NI 5441:
—
•
•
•
NI Signal Express
FGEN Soft Front panel
NI Measurement & Automation Explorer (MAX)
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Environment
NI PXI-5441 Environment
Note To ensure that the NI PXI-5441 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5441 kit. The NI PXI-5441
is intended for indoor use only.
Specifications
Value
Comments
Operating
0 ºC to +55 ºC in all NI PXI chassis except the following:
—
Temperature
0 ºC to +45 ºC when installed in an NI PXI-101x or
NI PXI-1000B chassis.
Meets IEC-60068-2-1 and IEC-60068-2-2.
Storage
Temperature
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.
—
—
Operating
Relative
10% to 90%, noncondensing. Meets IEC-60068-2-56.
Humidity
Storage
5% to 95%, noncondensing. Meets IEC-60068-2-56.
—
Relative
Humidity
Operating
Shock
30 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
Spectral and jitter
specifications
could degrade.
Storage Shock
50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
—
Operating
Vibration
5 Hz to 500 Hz, 0.31 grms. Meets IEC-60068-2-64.
Spectral and jitter
specifications
could degrade.
Storage
Vibration
5 Hz to 500 Hz, 2.46 grms. Meets IEC-60068-2-64. Test
profile exceeds requirements of MIL-PRF-28800F, Class B.
—
Altitude
2,000 meter maximum (at 25 °C ambient temperature)
2
—
—
Pollution
Degree
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Safety, Electromagnetic Compatibility, and
CE Compliance
Specification
Safety
Value
Comments
The NI 5441 meets the requirements of the
following standards of safety for electrical
equipment for measurement, control, and
laboratory use:
For UL and other
safety certifications,
refer to the product
label or visit
ni.com/
•
•
•
IEC 61010-1, EN 61010-1
UL 61010-1
certification.
CAN/CSA-C22.2 No. 61010-1
Emissions
EN 55011 Class A at 10 m
FCC Part 15A above 1 GHz
—
Immunity
EMC/EMI
EN 61326:1997 + A2:2001, Table 1
—
—
CE, C-Tick, and FCC Part 15 (Class A) Compliant.
For EMC compliance, operate this device with
shielded cabling.
This product meets the essential requirements of applicable European Directives, as amended
for CE marking, as follows:
Low-Voltage
73/23/EEC
—
Directive (safety)
Electromagnetic
Compatibility
89/336/EEC
—
Directive (EMC)
Note: Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory
compliance information. To obtain the DoC for this product, visit ni.com/certification,
search by model number or product line, and click the appropriate link in the Certification column.
© National Instruments Corporation
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Physical
Specification
Value
Comments
Dimensions
3U, One Slot, PXI/cPCI Module
—
2.0 × 13.0 × 21.6 cm (0.8 × 5.1 × 8.5 in)
Weight
345 g (12.1 oz)
—
—
Front Panel Connectors
Label
Function(s)
Analog Output
Connector Type
SMB (jack)
CH 0
CLK IN
Sample clock input and PLL SMB (jack)
reference clock input.
PFI 0
PFI 1
Markeroutput, triggerinput, SMB (jack)
sample clock output,
exported trigger output, and
PLL reference clock output.
Markeroutput, triggerinput, SMB (jack)
sample clock output,
exported trigger output, and
PLL reference clock output.
DIGITAL
DATA &
CONTROL
Digital data output, trigger
input, exported trigger
output, markers, external
sample clock input, and
sample clock output.
68-pin VHDCI female
receptacle
Front Panel LED Indicators
Label
Function
For more
information, refer
to the NI Signal
Generators Help.
ACCESS LED The ACCESS LED indicates the status of the PCI bus and
the interface from the NI 5441 to the controller.
ACTIVE LED The ACTIVE LED indicates the status of the onboard
generation hardware of the NI 5441.
Included Cable
1 (NI part number 763541-01), 50 Ω, BNC Male to SMB
Plug, RG223/U, Double Shielded, 1 m cable.
—
NI 5441 Specifications
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Technical Support Resources
NI Web Support
National Instruments Web support is your first stop for help in solving
installation, configuration, and application problems and questions. Online
problem-solving and diagnostic resources include frequently asked
questions, knowledge bases, product-specific troubleshooting wizards,
manuals, drivers, software updates, and more. Web support is available
through the Technical Support section of ni.com.
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NI 5441 Specifications
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