CBT3126
Quad FET bus switch
Rev. 02 — 23 October 2008
Product data sheet
1. General description
The CBT3126 is a quadruple FET bus switch features independent line switches. Each
switch is disabled when the associated Output Enable (OE) input is LOW.
The CBT3126 is characterized for operation from −40 °C to +85 °C.
2. Features
I Standard ’126-type pinout
I Multiple package options
I 5 Ω switch connection between two ports
I TTL-compatible input levels
I Minimal propagation delay through the switch
I Latch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Specified from −40 °C to +85 °C
3. Ordering information
Table 1.
Ordering information
Type number
Temperature range Package
Name
Description
Version
CBT3126D
−40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
CBT3126DB
−40 °C to +85 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
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Quad FET bus switch
5. Pinning information
5.1 Pinning
CBT3126
CBT3126
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
n.c.
1OE
1A
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
1A
V
CC
4OE
4A
4OE
4A
1B
1B
4B
2OE
2A
4B
2OE
2A
3OE
3A
3OE
3A
2B
2B
3B
GND
8
3B
GND
n.c.
001aaj025
001aaj026
Fig 3. Pin configuration SOT108-1 (SO14), SOT337-4
(SSOP14) and SOT402-1 (TSSOP14)
Fig 4. Pin configuration SOT519-1 (SSOP16)
5.2 Pin description
Table 2.
Symbol
Pin description
Pin SOT108-1 SOT337-4
Pin SOT519-1
Description
and SOT402-1
1OE to 4OE
1A to 4A,
1B to 4B
GND
1, 4, 10, 13
2, 5, 12, 15
3, 6, 11, 14
4, 7, 10, 13
8
output enable input
A input/output
2, 5, 9, 12
3, 6, 8, 11
B output/input
7
ground (0 V)
VCC
14
-
16
positive supply voltage
not connected
n.c.
1, 9
6. Functional description
Table 3.
Function selection
H = HIGH voltage level; L = LOW voltage level.
Inputs
nOE
L
Switch
nA to nB disconnected
nA to nB connected
H
CBT3126_2
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7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
−0.5
−0.5
-
Max
+7.0
+7.0
128
-
Unit
V
VCC
VI
supply voltage
input voltage
V
ICC
IIK
supply current
continuous current through each VCC or GND pin
VI < 0 V
mA
mA
°C
input clamping current
storage temperature
total power dissipation
−50
−65
Tstg
Ptot
+150
Tamb = −40 °C to +125 °C
SO14 package
-
-
-
500
500
500
mW
mW
mW
SSOP14 and SSOP16 package
TSSOP14 package
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The package thermal impedance is calculated from JESD51-7.
[3] For SO14 package; Ptot derates linearly with 8 mW/K above 70 °C.
[4] For SSOP14, SSOP16 and TSSOP14 packages; Ptot derates linearly with 5.5 mW/K above 70 °C.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
Symbol
VCC
Parameter
Conditions
Min
4.5
2.0
-
Max
5.5
-
Unit
supply voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
ambient temperature
V
VIL
0.8
+85
V
Tamb
operating in free-air
−40
°C
9. Static characteristics
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C.
Symbol
VIK
Parameter
Conditions
Min
Unit
V
input clamping voltage
pass voltage
VCC = 4.5 V; II = −18 mA
-
-
-
-
-
−1.2
-
Vpass
II
VI = VCC = 5.0 V; IO = −100 µA
VCC = 5.5 V; VI = GND or 5.5 V
3.8
V
input leakage current
supply current
-
-
±1
3
µA
µA
ICC
VCC = 5.5 V; IO = 0 mA;
VI = VCC or GND
∆ICC
additional supply current
control pins; per input;
-
-
2.5
mA
VCC = 5.5 V; one input at 3.4 V,
other inputs at VCC or GND
CI
input capacitance
control pins; VI = 3 V or 0 V
-
-
1.7
3.4
-
-
pF
pF
Cio(off)
off-state input/output capacitance VO = 3 V or 0 V; OE = VCC
CBT3126_2
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Product data sheet
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Table 6.
Static characteristics …continued
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
Min
Typ[1] Max
Unit
RON
ON resistance
VCC = 4.0 V
VI = 2.4 V; II = 15 mA
VCC = 4.5 V
-
16
22
Ω
VI = 0 V; II = 64 mA
VI = 0 V; II = 30 mA
VI = 2.4 V; II = 15 mA
-
-
-
5
7
Ω
Ω
Ω
5
7
10
15
[1] All typical values are measured at VCC = 5 V; Tamb = 25 °C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Symbol
tpd
Parameter
Conditions
Min
-
Max
0.25
4.5
Unit
propagation delay
enable time
nA to nB or nB to nA; see Figure 5
OE to nA or nB; see Figure 6
OE to nA or nB; see Figure 6
ns
ns
ns
ten
1.6
1.0
tdis
disable time
5.4
[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2] tPLH and tPHL are the same as tpd
;
tPZL and tPZH are the same as ten
;
tPLZ and tPHZ are the same as tdis
.
11. AC waveforms
V
I
V
V
M
input
0 V
M
t
t
PLH
PHL
V
OH
V
V
M
output
M
V
OL
001aai367
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. The input (nA, nB) to output (nB, nA) propagation delay times
CBT3126_2
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Quad FET bus switch
V
I
nOE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
disabled
switch
enabled
001aaj027
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
Table 8.
Input
VM
Measurement points
Output
VM
VX
VY
VOH − 0.3 V
1.5 V
1.5 V
VOL + 0.3 V
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12. Test information
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
7.0 V
tPHZ, tPZH
4.5 V to 5.5 V
GND to 3.0 V
≤ 2.5 ns
50 pF
500 Ω
open
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Product data sheet
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Quad FET bus switch
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 8. Package outline SOT109-1 (SO16)
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Quad FET bus switch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 9. Package outline SOT338-1 (SSOP16)
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Quad FET bus switch
SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm
SOT519-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
A
2
A
(A )
3
A
1
θ
L
p
L
8
1
detail X
w M
e
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.25
0.10
1.55
1.40
0.31
0.20
0.25
0.18
5.0
4.8
4.0
3.8
6.2
5.8
0.89
0.41
0.18
0.05
mm
1.73
0.25
0.635
1
0.2
0.18
0.09
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-05-04
03-02-18
SOT519-1
Fig 10. Package outline SOT519-1 (SSOP16)
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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 11. Package outline SOT403-1 (TSSOP16)
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DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 12. Package outline SOT763-1 (DHVQFN16)
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14. Abbreviations
Table 10. Abbreviations
Acronym
CDM
ESD
Description
Charged Device Model
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
CBT3126_2
Release date
20081023
Data sheet status
Change notice
Supersedes
Product data sheet
-
CBT3126_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
CBT3126_1
20011212
Product data sheet
-
-
CBT3126_2
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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18. Contents
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For sales office addresses, please send an email to: [email protected]
Date of release: 23 October 2008
Document identifier: CBT3126_2
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