Celeron™ Processor
Development Kit Manual
July 1999
Order Number: 273246-002
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Contents
1
About This Manual..................................................................................................1-1
1.1
1.2
1.3
Content Overview...............................................................................................1-1
Text Conventions ...............................................................................................1-1
Technical Support ..............................................................................................1-2
1.3.1
Electronic Support Systems ..............................................................1-2
1.3.1.1
1.3.1.2
Online Documents ...............................................................1-2
Intel Product Forums ...........................................................1-3
1.3.2
Telephone Technical Support ...........................................................1-3
1.4
1.5
Product Literature...............................................................................................1-3
Related Documents............................................................................................1-4
2
Getting Started.........................................................................................................2-1
2.1
Overview ............................................................................................................2-1
2.1.1
2.1.2
Processor Assembly Features ..........................................................2-1
Baseboard Features..........................................................................2-2
2.2
2.3
Included Hardware .............................................................................................2-2
Software Key Features.......................................................................................2-3
2.3.1
2.3.2
General Software, Inc........................................................................2-3
QNX Software Systems, Ltd..............................................................2-4
2.4
2.5
2.6
Before You Begin ...............................................................................................2-4
Setting up the Evaluation Board.........................................................................2-5
Configuring the BIOS .........................................................................................2-7
3
Theory of Operation...............................................................................................3-1
3.1
3.2
Block Diagram....................................................................................................3-1
System Operation...............................................................................................3-2
3.2.1
3.2.2
Celeron Processor.............................................................................3-2
82443BX Host Bridge/Controller .......................................................3-2
3.2.2.1
3.2.2.2
3.2.2.3
System Bus Interface...........................................................3-3
Accelerated Graphics Port (AGP) Interface.........................3-3
System Clocking..................................................................3-3
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
ITP.....................................................................................................3-3
82371EB PCI to ISA/IDE Xcelerator (PIIX4E)...................................3-4
DRAM................................................................................................3-4
Power ................................................................................................3-4
Boot ROM..........................................................................................3-4
RTC/NVRAM.....................................................................................3-4
Legacy I/O.........................................................................................3-4
IDE Support.......................................................................................3-5
Floppy Disk Support..........................................................................3-5
Keyboard/Mouse ...............................................................................3-5
USB...................................................................................................3-5
RS232 Ports......................................................................................3-5
IEEE 1284 Parallel Port.....................................................................3-5
PCI Connectors.................................................................................3-5
ISA Connectors .................................................................................3-5
AGP Connector .................................................................................3-5
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3.2.19
3.2.20
3.2.21
3.2.22
Post Code Debugger.........................................................................3-6
Clock Generation...............................................................................3-6
Interrupt Map.....................................................................................3-6
Memory Map .....................................................................................3-7
4
Hardware Reference ..............................................................................................4-1
4.1
Processor Assembly ..........................................................................................4-1
4.1.1
4.1.2
Thermal Management .......................................................................4-1
ITP Debugger Port ............................................................................4-1
4.2
4.3
4.4
4.5
Post Code Debugger..........................................................................................4-1
ISA and PCI Expansion Slots.............................................................................4-2
PCI Device Mapping ..........................................................................................4-2
Connector Pinouts..............................................................................................4-3
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
ATX Power Connector.......................................................................4-3
ITP Debugger Connector ..................................................................4-4
Stacked USB.....................................................................................4-4
Mouse and Keyboard Connectors.....................................................4-5
Parallel Port.......................................................................................4-5
Serial Ports........................................................................................4-6
IDE Connector...................................................................................4-6
Floppy Drive Connector.....................................................................4-7
PCI Slot Connector............................................................................4-8
ISA Slot Connector............................................................................4-9
4.6
4.7
AGP Connector................................................................................................4-10
Jumpers ...........................................................................................................4-11
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.7.8
Enable Spread Spectrum Clocking (J14) ........................................4-11
Clock Frequency Selection (J15) ....................................................4-11
On/Off (J20).....................................................................................4-11
Flash BIOS VPP Select (J21)..........................................................4-12
Flash BIOS Boot Block Control (J22)..............................................4-12
SMI# Source Control (J23)..............................................................4-12
CMOS RAM Clear (J24)..................................................................4-12
Push Button Switches .....................................................................4-12
4.8
In-Circuit BIOS Update.....................................................................................4-13
5
BIOS Quick Reference ..........................................................................................5-1
5.1
5.2
5.3
BIOS and Pre-Boot Features .............................................................................5-1
Power-On Self-Test (POST) ..............................................................................5-1
Setup Screen System ........................................................................................5-3
5.3.1
5.3.2
Basic CMOS Configuration Screen...................................................5-3
Configuring Drive Assignments.........................................................5-4
5.3.2.1
Configuring Floppy Drive Types ..........................................5-4
5.3.3
Configuring IDE Drive Types.............................................................5-5
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Configuring Boot Actions....................................................................................5-6
Custom Configuration Setup Screen..................................................................5-6
Shadow Configuration Setup Screen.................................................................5-7
Standard Diagnostics Routines Setup Screen...................................................5-8
Start System BIOS Debugger Setup Screen .....................................................5-8
Start RS232 Manufacturing Link Setup Screen .................................................5-9
Manufacturing Mode ..........................................................................................5-9
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5.10.1
5.10.2
5.10.3
Console Redirection ..........................................................................5-9
CE-Ready Windows CE Loader......................................................5-10
Integrated BIOS Debugger..............................................................5-10
5.11
5.12
Embedded BIOS POST Codes ........................................................................5-12
Embedded BIOS Beep Codes..........................................................................5-15
A
PLD Code Listing ................................................................................................... A-1
Bill of Materials ....................................................................................................... B-1
Schematics ............................................................................................................... C-1
.................................................................................................................................Index-1
B
C
Index
Figures
2-1
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
Evaluation Board Jumpers and Connectors.......................................................2-5
Evaluation Board Block Diagram........................................................................3-1
BIOS POST Pre-Boot Environment....................................................................5-2
Embedded BIOS Setup Screen Menu................................................................5-3
Embedded BIOS Basic Setup Screen................................................................5-4
Embedded BIOS Custom Setup Screen ............................................................5-7
Embedded BIOS Shadow Setup Screen............................................................5-7
Standard Diagnostic Routines Setup Screen.....................................................5-8
Start RS232 Manufacturing Link Setup Screen..................................................5-9
CE-Ready Boot Feature...................................................................................5-10
Integrated BIOS Debugger Running Over a Remote Terminal........................5-11
Tables
1-1
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
5-1
B-1
B-2
Related Documents............................................................................................1-4
Interrupts ............................................................................................................3-6
Memory Map ......................................................................................................3-7
PCI Device Mapping...........................................................................................4-2
Primary Power Connector (J11).........................................................................4-3
ITP Connector Pin Assignment (J2 on the Processor Assembly) ......................4-4
USB Connector Pinout (J2)................................................................................4-4
Keyboard and Mouse Connector Pinouts (J1 on the Baseboard)......................4-5
DB25 Parallel Port Connector Pinout (J3)..........................................................4-5
Serial Port Connector Pinout (J4).......................................................................4-6
PCI IDE1 (JP3) and IDE2 (JP4) Connector........................................................4-6
Diskette Drive Header Connector (JP1).............................................................4-7
PCI Slots (J7, J8, J9)..........................................................................................4-8
ISA Slots (J5, J6)................................................................................................4-9
AGP Slot (J13) .................................................................................................4-10
Default Jumper Settings...................................................................................4-11
IDE0-IDE3 Drive Assignments ...........................................................................5-5
Baseboard Bill of Materials................................................................................ B-1
Celeron™ Processor Assembly Bill of Materials............................................... B-5
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About This Manual
1
This manual tells you how to set up and use the evaluation board and processor assembly included
in your Celeron™ Processor Development Kit.
1.1
Content Overview
Chapter 1, “About This Manual” - This chapter contains a description of conventions used in this
manual. The last few sections tell you how to obtain literature and contact customer support.
Chapter 2, “Getting Started” - Provides complete instructions on how to configure the evaluation
board and processor assembly by setting jumpers, connecting peripherals, providing power, and
configuring the BIOS.
Chapter 3, “Theory of Operation” - This chapter provides information on the system design.
Chapter 4, “Hardware Reference” - This chapter provides a description of jumper settings and
functions, and pinout information for each connector.
Chapter 5, “BIOS Quick Reference” - This chapter describes how to configure the BIOS for your
system configuration. A summary of all BIOS menu options is provided.
Appendix A, “PLD Code Listing” - This appendix includes a sample code listing for the Post Code
Debugger.
Appendix B, “Bill of Materials” - This appendix contains the bill of materials for the evaluation
board.
Appendix C, “Schematics” - This appendix contains schematics for selected connectors and
subsystems for the evaluation board.
1.2
Text Conventions
The following notations may be used throughout this manual.
#
The pound symbol (#) appended to a signal name indicates that the
signal is active low.
Variables
Instructions
Variables are shown in italics. Variables must be replaced with correct
values.
Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
upper- or lowercase.
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About This Manual
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that
begin with A through F. (For example, FF is shown as 0FFH.) Decimal
and binary numbers are represented by their customary notations. (That
is, 255 is a decimal number and 1111 1111 is a binary number. In some
cases, the letter B is added for clarity.)
Units of Measure
The following abbreviations are used to represent units of measure:
A
amps, amperes
gigabytes
kilobytes
kilo-ohms
milliamps, milliamperes
megabytes
megahertz
milliseconds
milliwatts
Gbyte
Kbyte
KΩ
mA
Mbyte
MHz
ms
mW
ns
nanoseconds
pF
picofarads
W
watts
V
volts
µA
microamps, microamperes
microfarads
microseconds
microwatts
µF
µs
µW
Signal Names
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals
are named CS0#, CS1#, CS2#, and so on; they are collectively called
CSn#. A pound symbol (#) appended to a signal name identifies an
active-low signal. Port pins are represented by the port abbreviation, a
period, and the pin number (e.g., P1.0).
1.3
Technical Support
1.3.1
Electronic Support Systems
Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical
information and product support. This information is available 24 hours per day, 7 days per week,
providing technical information whenever you need it.
1.3.1.1
Online Documents
Product documentation is provided online in a variety of web-friendly formats at:
http://developer.intel.com/design/litcentr/index.htm
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About This Manual
1.3.1.2
Intel Product Forums
Intel provides technical expertise through electronic messaging. With publicly accessible forums,
you have all of the benefits of email technical support, with the added benefit of the option of
viewing previous messages written by other participants, and providing suggestions and tips that
can help others.
Each of Intel’s technical support forums is based on a single product or product family. Questions
and replies are limited to the topic of the particular forum. Intel also provides several non-technical
support related forums.
Complete information on Intel forums is available at:
http://support.intel.com/newsgroups/index.htm
1.3.2
Telephone Technical Support
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S.
and Canada, please contact your local distributor.
1-800-628-8686
916-356-7599
U.S. and Canada
U.S. and Canada
U.S. and Canada
916-356-6100 (fax)
1.4
Product Literature
You can order product literature from the following Intel literature centers.
1-800-548-4725
708-296-9333
U.S. and Canada
U.S. (from overseas)
Europe (U.K.)
Germany
44(0)1793-431155
44(0)1793-421333
44(0)1793-421777
81(0)120-47-88-32
France
Japan (fax only)
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About This Manual
1.5
Related Documents
Table 1-1. Related Documents
Document Title
Order Number
®
Intel Celeron™ Processor datasheet
243658
243748
244001
®
Intel Celeron™ Processor Specification Update
P6 Family of Processors Hardware Developer’s Manual
Intel Architecture Software Developer’s Manual,
Volume 1: Basic Architecture
243190
243191
243192
Intel Architecture Software Developer’s Manual,
Volume 2: Instruction Set Reference
Intel Architecture Software Developer’s Manual,
Volume 3: System Programming Guide
®
Intel 440BX AGPset: 82443BX Host Bridge/Controller datasheet
290633
290639
273218
290562
290635
273135
®
Intel 440BX AGPset: 82443BX Host Bridge/Controller Specification Update
®
Intel 440BX AGPset: 82443BX Host Bridge/Controller Timing Specification
82371AB (PIIX4) and 82371EB (PIIX4E) PCI-TO-ISA/IDE Xcelerator datasheet
Intel 82371EB (PIIX4E) Specification Update
Intel 82371AB PCI ISA IDE Xcelerator (PIIX4) Timing Specification
1-4
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Getting Started
2
This chapter identifies the Development Kit’s key components, features and specifications, and
tells you how to set up the board for operation.
2.1
Overview
The evaluation board consists of a baseboard and a processor assembly.
• The processor assembly contains an Intel® Celeron™ Processor and an 82443BX Host
Bridge/Controller.
• The baseboard contains the 82371EB PCI ISA IDE Xcelerator (PIIX4E) and other system
board components and peripheral connectors.
Warning: The processor assembly is attached to the baseboard at the factory. Do not remove the processor
assembly from the baseboard. Intel will not support the processor assembly or the baseboard if any
portion of the assembly is removed by the customer.
2.1.1
Processor Assembly Features
The processor assembly features are summarized below.
• Celeron Processor in a PPGA package (Socket-370) with 66-MHz system bus frequencies
• Intel 440BX AGPset: 82443BX Host Bridge/Controller
• 66 MHz memory interface: A wide range of DRAM support including:
— 64-bit memory data interface plus 8 ECC bits and hardware scrubbing
— 60 ns EDO DRAM and 66 MHz SDRAM support
— 16 Mbit and 64 Mbit DRAM technologies
• Five PCI masters
— PCI Specification Rev 2.1 Compliant
• Accelerated Graphics Port (AGP) Support:
— AGP Interface Specification Revision 1.0 compliant
— AGP - 66/133 MHz, 3.3-V device support
• Integrated System Power Management support
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Getting Started
2.1.2
Baseboard Features
The baseboard has these features:
• Flash system BIOS ROM
— General Software system BIOS
— In-circuit BIOS upgradability
• Two SDRAM DIMM connectors
• 32-Mbyte SDRAM DIMM included
— 4 Mbyte x64, 3.3 V, 66 MHz with a CAS latency of 2
• User-accessible on-board connectors include:
— Two serial RS-232 ports; COM1, COM2
— One EPP/ECP parallel port
— PS/2 keyboard and PS/2 mouse (6-pin mini-DIN connectors)
— Two USB ports
— Two IDE bus connectors
— One floppy connector
— Three PCI expansion slots and two ISA expansion slots. There are no shared slots; all
slots are usable.
— One AGP connector
— Standard ATX power supply connector
• Miscellaneous features include:
— On board post-code debugger (Port 80)
— Reset push button
— Stand-off feet for table-top operation
2.2
Included Hardware
• Evaluation board (baseboard and processor assembly combination)
• 3.2-Gbyte hard disk drive pre-loaded with the QNX Real Time Operating System*
• 32-Mbyte SDRAM DIMM
• Attached heatsink and fan
• PCI video graphics adapter using the CHIPS* 69000 HiQVideo* Accelerator
• Mounting hardware
• IDE cable for the hard disk drive
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Getting Started
2.3
Software Key Features
The software in the kit was chosen to facilitate development of real-time applications based on the
components used in the evaluation board. The software tools included in your kit are described in
this section.
Note: Software in the kit is provided free by the vendor and is only licensed for evaluation purposes.
Customers using the tools that work with Microsoft products must have licensed those products.
Any targets created by those tools should also have appropriate licenses. Software included in the
kit is subject to change.
2.3.1
General Software, Inc.
Embedded BIOS is a full-featured BIOS for x86-based handheld, embedded, and volume
consumer electronics applications. This product offers a winning combination of superior OEM
configurability and superior embedded features.
Embedded BIOS leads the industry with all the on-target embedded features that OEMs making
embedded, handheld, mobile, and consumer electronics demand:
• CE Ready*, the Windows CE* launcher
• Integrated BIOS-aware debugger
• Resident Flash Disk disk emulator
• ROM disk and RAM disk emulators
• Manufacturing Mode for in-field diagnosis and software upgrades
• Power management that can operate in an APM or stand-alone environment
• PCI resource management
• Matrix keyboard support
• LCD panel drivers
• Console redirection over RS232 ports
• Flexibility to boot from many disk servers
• OEM-configurable setup screen system
• Embedded DOS*-ROM (adaptation kit and license)
• Total compatibility with industry standards
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Getting Started
2.3.2
QNX Software Systems, Ltd.
QNX Real Time Operating System for Intel Architecture.
• Small memory footprint of the QNX operating system with microGUI
• QNX microGUI is a full featured graphical user interface (GUI) and windowing system
• Photon Application Builder
• QNX Development kit provides the basic utilities to build and program Intel Flash
• Watcom C/C++ Development Suite: is a full featured development suite
• Includes compiler, assembler and debugger with full support for the QNX microGUI function
library
• Makes development of the QNX executables fast, easy and optimized
Caution: Use the shutdown button to exit from QNX. Improper shutdown may result in the loss of the file
system.
2.4
Before You Begin
Before you set up and configure your evaluation board, you may want to gather some additional
hardware and software.
VGA Monitor
You can use any standard VGA or multi-resolution monitor. The setup
instructions in this chapter assume that you are using a standard VGA
monitor.
Power Supply
Keyboard
You must use an ATX-type PC power supply.
You need a keyboard with a PS/2 style connector or adapter.
Optional. You can use a mouse with a PS/2 style connector or adapter.
Mouse
Additional Drives
You can connect up to four IDE drives and a floppy drive to the
evaluation board. Two devices (master and slave) can be attached to
each IDE connector. You will need to provide the cables for these
drives.
You may have all these storage devices attached to the board at the
same time.
Video Adapter
You can use the Chips and Technologies video adapter supplied with
your kit, or you can use a different adapter. The evaluation board
supports AGP, PCI and ISA video cards. It is up to you to install the
correct drivers for video adapters other than the one provided.
Other Devices
and Adapters
The evaluation board behaves much like a standard desktop computer
motherboard. Most PC compatible peripherals can be attached and
configured to work with the evaluation board. For example, you may
want to install a sound card or network adapter.
2-4
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Getting Started
2.5
Setting up the Evaluation Board
Once you have gathered the hardware described in the last section, follow the steps below to set up
your evaluation board. This manual assumes you are familiar with basic concepts involved with
installing and configuring hardware for a personal computer system. Refer to Figure 2-1 for
locations of connectors, jumpers, etc.
1. Make sure you are in a static-free environment before removing any components from their
anti-static packaging. The evaluation board is susceptible to electro-static discharge damage;
such damage may cause product failure or unpredictable operation.
2. Inspect the contents of your kit. Check for damage that may have occurred during shipment.
Contact your sales representative if any items are missing or damaged.
Caution: Connecting the wrong cable or reversing the cable can damage the evaluation board and may
damage the device being connected. Since the board is not in a protective chassis, use caution when
connecting cables to this product.
Figure 2-1. Evaluation Board Jumpers and Connectors
PCI
AGP Connector
USB
Keyboard (Top) COM1 (Top)/
Connectors
/Mouse
COM2
Parallel Port
LEDs
ISA
Connectors
J2
J3
J1
D1
D2
J4
J5
J6
ATX Power
Connector
J7
J8
J9
J12
J14
J15
J13
J14 J15
Floppy
J11
Connector
J17
J18
Processor
Assembly
J20
J20
J21
J22
J21 J22
U12 U13
ITP
U11
J23
Debugger
Port
Post
Code
Debugger
J2
JP2
JP2
IDE2
JP3
IDE1
J24
Battery
JP2
J24 J23
IDE Connectors
SDRAM
DIMM Slots
Special Mounting Holes
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Getting Started
3. Make sure the board’s jumpers are set to the following default locations.
• J14 - Not installed
• J15 - Installed
• J20 - Jumper pins 2-3
• J21 - Jumper pins 2-3
• J22 - Jumper pins 2-3
• J23 - Jumper pins 2-3
• J24 - Jumper pins 1-2
4. Mount the hardware:
•
Table-top operation: The evaluation board is shipped with standoff “feet” for use in a
table-top environment. These feet are installed on the evaluation board to raise it off the
table surface.Your kit contains two bags of mounting hardware. One bag contains eight
standoff feet, eight mounting screws, and eight washers. Another bag has three shorter
feet that must be attached slightly differently.
— To mount the eight standard feet, insert a washer onto a screw, then push the screw
through the top of the board. From below the board, thread one of the longer feet
onto the screw.
— To mount the three special feet, screw the three shorter feet onto the existing
screws. See Figure 2-1 for the location of the three special holes.
Warning: Do not remove the nuts from these three holes! This will detach the processor assembly from the
baseboard, and Intel will no longer support the evaluation board.
•
The evaluation board is not ATX compatible.
5. Connect desired storage devices to the evaluation board:
The evaluation board supports Primary and Secondary IDE interfaces that can each host one or
two devices (master/slave). When you are using multiple devices, such as a hard disk and a
CD-ROM drive, make sure the hard disk drive has a jumper in the master position and the CD-
ROM has a jumper in the slave position. When you are using a single IDE device with the
evaluation board, be sure that the jumpers set correctly for single master operation. For jumper
settings for other configurations, consult the drive’s documentation.
Note: The evaluation board BIOS only supports hard drives of 16 Gbytes or less.
•
Installing the IDE hard disk drive included in your kit:
— Connect the hard drive’s IDE connector to the JP4 connector on the evaluation
board. Be sure to align Pin 1 of the cable connector with pin 1 of JP4.
— Connect the other end to the hard disk drive.
Caution: Make sure the tracer on the ribbon cable is aligned with pin 1 on both the hard disk and the IDE
connector header. Connecting the cable backwards can damage the evaluation board or the hard
disk.
— Connect the hard drive to the power supply.
Note: The hard disk is already formatted and is pre-loaded with the QNX Real-Time Operating System
for Intel Architecture.
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Getting Started
— You may have to make changes to the system BIOS to enable this hard disk. See
Chapter 5, “BIOS Quick Reference” for more information.
•
Floppy drive: A floppy disk drive connected to the evaluation board is the most direct
method for loading software.
— Insert floppy cable into JP1 (be sure to orient Pin 1 correctly).
— Connect the other end of the ribbon cable to the floppy drive.
— Connect a power cable to the floppy drive.
— You must make changes to the system BIOS to enable this floppy disk. See
Chapter 5, “BIOS Quick Reference” for more information.
6. Make sure the SDRAM DIMM is installed in the socket labeled J18.
7. Connect a PS/2 mouse and keyboard (see Figure 2-1 for connector locations).
Note: J1 (on the baseboard) is a stacked PS/2 connector. The bottom connector is for the mouse and the
top is for the keyboard.
8. Install the Chips and Technologies PCI video adapter into one of the available PCI slots.
Connect the monitor cable to the VGA port on the card.
9. Connect the power supply:
You’ll need a standard ATX PC power supply. Make sure the power supply is unplugged (or
turned off), then connect the power supply cable to the power header (J11).
Note: Some ATX power supplies do not have an on/off switch. In this case remove jumper J20 before
plugging in the ATX power connector. J20 controls an internal power supply on/off switch. When
you are ready to apply power, insert the jumper on pins 2-3. You may want to wire this header up to
a toggle switch for convenience.
Turn on the power to the monitor and evaluation board. When the power is on you should see two
power-indicator LEDs light up (located next to the ATX power connector in the upper right corner
of the board; see Figure 2-1). Check to see that the fan on the processor is operating.
2.6
Configuring the BIOS
General Software’s BIOS software is pre-loaded on the evaluation board. You will have to make
changes to the BIOS to enable hard disks, floppy disks and other supported features You can use
the Setup program to modify BIOS settings and control the special features of the system. Setup
options are configured through a menu-driven user interface. Chapter 5, “BIOS Quick Reference”
contains a description of BIOS options.
BIOS updates may periodically be posted to Intel’s Developers’ web site at
http://developer.intel.com/.
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Theory of Operation
3
3.1
Block Diagram
Figure 3-1. Evaluation Board Block Diagram
Processor Assembly
ITP
Celeron™ Processor
Thermal
Sensor
with 128 Kbyte
Integrated L2 Cache
VCCcore
Voltage
Regulator
SMBus
Processor
Side Bus
82443BX
Host Bridge/Controller
DRAM Bus
AGP Bus
Clock Generator
AGP Connector
PCI Connectors
PCI Bus
USB
PIIX4E
Bus Master IDE
I/O APIC
XD Bus
ISA Bus
Boot
Flash
ISA Connectors
PS/2 Mouse
IEEE 1284 Parallel Port
SMC FDC37B78X
SuperI/O*
PS/2 Keyboard
Floppy Drive
COM1
COM2
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Theory of Operation
3.2
System Operation
The Celeron™ processor evaluation board is a full-featured system board and processor assembly.
The processor assembly includes either a 366-MHz or a 433-MHz Celeron processor (based on the
development kit purchased) with 128 Kbytes of integrated L2 cache and the Intel 82443 BX Host
Bridge/Controller. The evaluation board contains the Intel 82371EB PCI-to-ISA/IDE Xcelerator
(PIIX4E) and other system and I/O peripherals.
The evaluation board and processor assembly support 300-MHz, 366-MHz, and 433 MHz Celeron
processors with 128 Kbytes of integrated L2 cache. The customer may remove the Celeron
processor from the processor socket and replace it with another supported version. Do not remove
the processor assembly. The evaluation board automatically detects which processor is installed in
the socket.
3.2.1
3.2.2
Celeron Processor
The Celeron processor for applied computing is offered at 366 MHz and 433 MHz with a processor
system bus speed of 66 MHz. The Celeron processor consists of a Pentium® II processor core with
an integrated second level cache and a 64-bit high-performance host bus. The processor has a
private second level cache bus that allows a high-performance 64-bit wide cache subsystem to be
integrated on the same die as the processor. The processor can cache up to 4 Gbytes of memory
using 128 Kbytes of L2 cache, 16 Kbytes of L1 data cache and 16 Kbytes of L2 code cache. The
private first and second level cache operate at the same frequency and voltage as the processor core
to improve performance and reduce total system power consumption.
82443BX Host Bridge/Controller
The Intel® 440BX AGPset supports the Pentium II processor architecture. It interfaces with the
Celeron processor system bus at 66 MHz. Along with its Host-to-PCI bridge interface, the
82443BX Host Bridge/Controller has been optimized with a 66 MHz SDRAM memory controller
and data path unit. The 82443BX also features the Accelerated Graphics Port (AGP) interface. The
82443BX component includes the following functions and capabilities:
• 64-bit GTL+ based system data bus interface
• 32-bit system address bus support
• 64/72-bit main memory interface with optimized support for SDRAM
• 32-bit PCI bus interface with integrated PCI arbiter
• AGP interface with up to 133 MHz data transfer capability
• Extensive data buffering between all interfaces for high throughput and concurrent operations
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Theory of Operation
3.2.2.1
System Bus Interface
The 82443BX supports a maximum of 4 Gbytes of memory address space from the processor
perspective. The largest address size is 32 bits. The 82443BX provides bus control signals and
address paths for transfers between the processor bus, PCI bus, Accelerated Graphics Port and
main memory. The 82443BX supports a 4-deep-in-order queue, which provides support for
pipelining of up to four outstanding transaction requests on the system bus.
For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the
PCI bus, depending on the PCI address space being accessed. When the access is to a PCI
configuration space, the processor I/O cycle is mapped to a PCI configuration space cycle. When
the access is to a PCI I/O or memory space, the processor address is passed without modification to
the PCI bus. Certain memory address ranges are dedicated for a graphics memory address space.
When this space or a portion of it is mapped to main DRAM, the address is translated by the AGP
address remapping mechanism and the request is forwarded to the DRAM subsystem. A portion of
the graphics aperture can be mapped on the AGP, and the corresponding system bus cycles
accessing that range are forwarded to the AGP without any translation. The AGP address map
defines other system bus cycles that are forwarded to the AGP.
3.2.2.2
3.2.2.3
Accelerated Graphics Port (AGP) Interface
The 82443BX supports an AGP interface. The AGP interface has a maximum theoretical transfer
rate of ~532 Mbytes/s.
System Clocking
The 82443BX operates the system bus interface at 66 MHz, the PCI bus at 33 MHz and the AGP at
a transfer rate of 66/133 MHz. The 82443BX clocking scheme uses an external clock synthesizer
that produces reference clocks for the system bus and PCI interfaces. The 82443BX generates the
AGP and DRAM clock signals. Please refer to the CK97 Clock Synthesizer/Driver Specification
(order number 243867).
3.2.3
ITP
The evaluation board is populated with a 2.5 V ITP debugger port. The ITP port provides a path for
debugger tools like emulators, in-target probes, and logic analyzers to gain access to the Celeron
processor registers and signals without affecting high speed operation. This allows the system to
operate at full speed with the debugger attached.
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Theory of Operation
3.2.4
82371EB PCI to ISA/IDE Xcelerator (PIIX4E)
The 82443BX is designed to support the PIIX4E I/O bridge. The PIIX4E is a highly-integrated
multifunctional component that supports the following:
• PCI Revision 2.1 compliant PCI-to-ISA bridge with support for 33 MHz PCI operations
• ACPI Power Management support
• Enhanced DMA controller, interrupt controller and timer functions
• Integrated IDE controller with Ultra DMA/33 support
• USB host interface with support for two USB ports
• System Management Bus (SMB) with support for DIMM Serial Presence Detect
3.2.5
3.2.6
DRAM
The evaluation board provides two 168-pin DIMM module connectors. The DRAM interface is a
64-bit data path that supports Synchronous DRAM (SDRAM). The DRAM interface supports
4 Mbytes to 256 Mbytes of 4-Mbit, 16-Mbit and 64-Mbit DRAM and SRAM technology (both
symmetrical and asymmetrical). Parity is not supported. One 32-Mbyte SDRAM DIMM is
included in the kit.
Power
The evaluation board uses an industry standard ATX-style power supply with a 20-pin connector. A
230-watt (minimum) supply is recommended. Note that the ATX power connector is keyed to
prevent incorrect insertion. See “ATX Power Connector” on page 4-3 for a detailed description of
the power connector.
Make sure that the ATX power supply is not plugged into the wall when connecting or
disconnecting it from the evaluation board.
3.2.7
Boot ROM
The system boot ROM installed at U11 is a 2-Mbit 28F002BC flash device. The system is set up
for in-circuit reprogramming of the BIOS, but the flash device is also socketed. This device is
addressable on the XD bus extension of the ISA bus.
3.2.8
3.2.9
RTC/NVRAM
The RTC and NVRAM are contained within the 82371EB PIIX4E device. CMOS NVRAM
backup is provided by a 3-V lithium-ion battery.
Legacy I/O
Support for legacy I/O functions is provided by the Intel 82371EB PIIX4E and the SMC
FDC37B78X SuperI/O* device.
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Theory of Operation
3.2.10
3.2.11
3.2.12
IDE Support
The evaluation board supports both a primary and secondary IDE interface via two 40-pin IDE
connectors. The connector labeled IDE1 is the primary interface. IDE2 is the secondary interface.
Floppy Disk Support
Floppy disk support is provided by the SMC FDC37B78X SuperI/O device. One 34-pin floppy
connector is provided on the evaluation board.
Keyboard/Mouse
Keyboard and mouse support are provided by the SMC FDC37B8X SuperI/O device. The
keyboard and mouse connectors (J1) are PS/2 style, 6-pin stacked miniature DIN connectors. The
top connector is for the keyboard and the bottom connector is for the mouse.
3.2.13
3.2.14
USB
USB support is provided through the PIIX4E and can be used through connector J2.
RS232 Ports
Two serial I/O ports provided by the SMC FDC37B78X SuperI/O device. Two 9-pin RS232
connectors are provided on a single stacked connector (J4).
3.2.15
3.2.16
IEEE 1284 Parallel Port
One 25-pin IEEE 1284 parallel port connector controlled by the SMC FDC37B78X SuperI/O
device is provided (J3).
PCI Connectors
Three industry standard 32-bit, 5-V PCI connectors are provided on the evaluation board. The
connectors are designed to handle either a 5-V only card or a universal card. 3.3-V cards are not
supported.
3.2.17
3.2.18
ISA Connectors
Two 16-bit ISA connectors are provided on the evaluation board.
AGP Connector
AGP support is provided through the 82443BX Host Bridge/Controller. One industry standard
AGP connector (J13) is provided on the evaluation board.
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Theory of Operation
3.2.19
3.2.20
Post Code Debugger
The evaluation board has an on-board Post Code Debugger. Data from any program that does an
I/O write to 0080H is latched and displayed on the two LEDs (U12 and U13). During BIOS startup,
codes are posted to these LEDs to indicate what the BIOS is doing. Application programs can post
their own data to these LEDs by writing to I/O address 0080H.
Clock Generation
There are three devices on the baseboard which generate and distribute the clocks used by the
entire system. These are the CY2280 clock synthesizer, CY2318NZ clock buffer and the CY23009
zero delay buffer. Not all of these devices are used on this version of the evaluation board.
The CY2280 generates the clocks for the Celeron processor, Host Bridge/Controller, cache, PCI,
USB and ISA bus. The processor clock runs at 66 MHz. The PCI clocks run at 33 MHz. This
device is capable of spread spectrum clocking. If spread spectrum clocking is enabled, a 0.5%
down spread will be introduced in the processor and PCI clocks.
The CY2318NZ clock buffer is used to buffer the clock signals sent to the SDRAM DIMMS. The
SDRAM interface operates at 66 MHz.
The CY2309 Zero Delay Buffer is not used by the evaluation board.
3.2.21
Interrupt Map
Table 3-1. Interrupts
IRQ
System Resources
I/O Channel Check
NMI
0
Reserved, Interval Timer
Reserved, Keyboard buffer full
Reserved, Cascade interrupt from slave PIC
Serial Port 2
1
2
3
4
Serial Port 1
5
Parallel Port (PNP0 option)
Floppy
6
7
Parallel Port 1
8
Real Time Clock
9
IRQ2 Redirect
10
11
12
13
14
15
Reserved. Not supported.
Reserved. Not supported.
Onboard Mouse Port if present, else user available
Reserved, Math coprocessor
Primary IDE if present, else user available
Reserved. Not supported.
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Theory of Operation
3.2.22
Memory Map
Table 3-2. Memory Map
Address Range
(Hex)
Size
Description
100000-8000000
E0000-FFFFF
C8000-DFFFF
A0000-C7FFF
9FC00-9FFFF
80000-9FBFF
00000-7FFFF
127.25M
128K
Extended Memory
BIOS
Available expansion BIOS area (Flash disk memory window)
Off-board video memory and BIOS
Extended BIOS Data (movable by QEMM, 386MAX)
Extended conventional
1K
127K
512K
Conventional
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Hardware Reference
4
This section provides reference information on the system design. Included in this section is
connector pinout information, jumper settings, and other system design information.
4.1
Processor Assembly
The processor assembly contains the Celeron™ processor, the 82443BX Host Bridge/Controller, a
voltage regulator and an ITP debugger connector. The assembly connects to the baseboard via a
400-pin connector.
Warning: The processor assembly is attached to the baseboard at the factory. Do not remove the processor
assembly from the baseboard. Intel will not support the processor assembly or the baseboard if any
portion of the assembly is removed by the customer.
4.1.1
Thermal Management
The objective of thermal management is to ensure that the temperature of each component is
maintained within specified functional limits. The functional temperature limit is the range within
which the electrical circuits can be expected to meet their specified performance requirements.
Operation outside the functional limit can degrade system performance and cause reliability
problems.
Important: The evaluation kit contains a heatsink and fan attached to the top of the Celeron processor. This
thermal solution has been tested in an open air environment at room temperature and is sufficient
for evaluation purposes only. It is up to the designer to provide adequate thermal management for
any designs derived from the schematics provided in your kit.
4.1.2
ITP Debugger Port
The evaluation platform is populated with a 2.5 V ITP debugger port. The ITP port provides a path
for debugger tools like emulators, in-target probes, and logic analyzers to gain access to the
Celeron processor’s registers and signals without affecting high speed operation. This allows the
system to operate at full speed with the debugger attached.
4.2
Post Code Debugger
The evaluation board has an on-board Post Code Debugger. Data from any code that does an I/O
write to 80H is latched on the two led displays (U12/U13). During BIOS startup, code is posted to
these LEDs to indicate what the BIOS is doing. Application code can post its own data to these
LEDs by doing an I/O write to address 80H. The 22V10 PLD code used to implement this function
is included in Appendix A, “PLD Code Listing.”
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Hardware Reference
4.3
4.4
ISA and PCI Expansion Slots
The evaluation platform has three PCI expansion slots and two ISA slots.
PCI Device Mapping
On the evaluation platform the PCI devices are mapped to PCI device numbers by connecting an
address line to the IDSEL signal of each PCI device. Table 4-1 shows the mapping of PCI devices.
Table 4-1. PCI Device Mapping
Device
Address Line
PCI Device Number
PIIX4E
AD18
AD28
AD29
AD30
7
PCI Slot 0 (J7)
PCI Slot 1 (J8)
PCI Slot 2 (J9)
17
18
19
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Hardware Reference
4.5
Connector Pinouts
4.5.1
ATX Power Connector
Table 4-2 shows the signals assigned to the ATX style power connector.
Table 4-2. Primary Power Connector (J11)
Pin
Name
Function
1
2
3.3 V
3.3 V
GND
+5V
3.3 V
3.3 V
3
Ground
+5 V VCC
Ground
+5 V VCC
Ground
Power Good
Standby 5 V
+12 V
4
5
GND
+5V
6
7
GND
PWRGD
5VSB
+12 V
3.3 V
–12 V
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
3.3 V
–12 V
Ground
PS_ON#
GND
Soft-off control
Ground
GND
Ground
GND
Ground
–5 V
–5 Volts
+5 V
+5 V VCC
+5 V VCC
+5 V
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4.5.2
ITP Debugger Connector
Table 4-3. ITP Connector Pin Assignment (J2 on the Processor Assembly)
Pin
Signal
Pin
Signal
1
2
RESET#
GND
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PREQ0#
GND
3
DBRESET#
GND
PRDY0#
GND
4
5
TCK
PREQ1#
GND
6
GND
7
TMS
PRDY1#
GND
8
TDI
9
POWERON
TDO
PREQ2#
GND
10
11
12
13
14
15
DBINST#
TRST#
GND
PRDY2#
GND
PREQ3#
BCLK
BSEN#
GND
PRDY3#
4.5.3
Stacked USB
P0 is the bottom connector. P1 is on top.
Table 4-4. USB Connector Pinout (J2)
Pin
P0 Signals
P1 Signals
1
2
3
4
VCC0
D0-
VCC1
D1-
D0+
D1+
GND0
GND1
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4.5.4
Mouse and Keyboard Connectors
The keyboard port is on top. The mouse port is on the bottom.
Table 4-5. Keyboard and Mouse Connector Pinouts (J1 on the Baseboard)
Pin
Signal Name
1
2
3
4
5
6
Data
No Connect
Ground
+5 V (fused)
Clock
No Connect
4.5.5
Parallel Port
Table 4-6. DB25 Parallel Port Connector Pinout (J3)
Signal
Name
Signal
Name
Pin
Pin
1
2
Strobe#
14
15
16
17
18
19
20
21
22
23
24
25
Auto Feed#
Fault#
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
ACK#
3
INIT#
4
SLCT IN#
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
5
6
7
8
9
10
11
12
13
Busy
Paper end
SLCT
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4.5.6
Serial Ports
COM1 is the top connector. COM2 is the bottom connector.
Table 4-7. Serial Port Connector Pinout (J4)
Pin
Signal Name
1
2
3
4
5
6
7
8
9
DCD
Serial In (SIN)
Serial Out (SOUT)
DTR
GND
DSR
RTS
CTS
RI
4.5.7
IDE Connector
Table 4-8. PCI IDE1 (JP3) and IDE2 (JP4) Connector
Pin
Signal Name
Reset IDE
Pin
Signal Name
Ground
1
2
3
Host Data 7
Host Data 6
Host Data 5
Host Data 4
Host Data 3
Host Data 2
Host Data 1
Host Data 0
Ground
4
Host Data 8
Host Data 9
Host Data 10
Host Data 11
Host Data 12
Host Data 13
Host Data 14
Host Data 15
Key
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DRQ3
Ground
I/O Write#
I/O Read#
IOCHRDY
DACK3#
Ground
Ground
BALE
Ground
IRQ14
IOCS16#
Ground
Addr 1
Addr 0
Addr 2
Chip Select 0#
Activity
Chip Select 1#
Ground
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4.5.8
Floppy Drive Connector
Table 4-9. Diskette Drive Header Connector (JP1)
Pin
Signal Name
Ground
Pin
Signal Name
FDHDIN
1
2
3
Ground
Key
4
Reserved
5
6
FDEDIN
7
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
8
Index
9
10
12
14
16
18
20
22
24
26
28
30
32
34
Motor Enable A#
Drive Select B#
Drive Select A#
Motor Enable B#
DIR#
11
13
15
17
19
21
23
25
27
29
31
33
STEP#
Write Data#
Write Gate#
Track 00#
Write Protect#
Read Data#
Side 1 Select#
Diskette Change#
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4.5.9
PCI Slot Connector
Table 4-10. PCI Slots (J7, J8, J9)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
VCC
B1
B2
- 12V
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
AD16
3.3V
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD17
CBE2#
GND
+ 12V
VCC
GND
A3
B3
GND
FRAME#
GND
A4
VCC
B4
No Connect
VCC
IRDY#
3.3 V
DEVSEL#
GND
A5
VCC
B5
TRDY#
GND
A6
PIRQ1#
PIRQ3#
VCC
B6
VCC
A7
B7
PIRQ2#
PIRQ0
PRSNT1B#
No Connect
PRSNT2B#
GND
STOP#
3.3 V
SDONE
SBO#
GND
A8
B8
LOCK#
PERR#
3.3 V
SERR#
3.3V
A9
No Connect
VCC
B9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
No Connect
GND
PAR
GND
GND
AD15
3.3V
CBE1#
AD14
GND
No Connect
RST#
VCC
No Connect
GND
AD13
AD11
GND
PCLK3
GND
AD12
AD10
GND
GNT1#
GND
REQ#
VCC
AD9
Reserved
AD30
KEY
KEY
AD31
KEY
KEY
3.3V
AD29
CBEO#
3.3 V
AD6
AD8
AD28
GND
AD7
AD26
AD27
3.3 V
AD5
GND
AD25
AD4
AD24
3.3 V
GND
AD3
IDSEL
3.3V
CBE3#
AD23
AD2
GND
AD0
AD1
AD22
GND
VCC
VCC
AD20
AD21
REQ64#
VCC
ACK64#
VCC
GND
AD19
AD18
3.3 V
VCC
VCC
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4.5.10
ISA Slot Connector
Table 4-11. ISA Slots (J5, J6)
Pin
A1
Signal Name
IOCHK#
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
B1
B2
GND
RSTSLOT
VCC
A26
A27
A28
A29
A30
A31
C1
SA5
SA4
B26
B27
B28
B29
B30
B31
D1
DACK2#
TC
A2
A3
SD7
SD6
B3
SA3
BALE
A4
SD5
B4
IRQB9
SA2
VCC
A5
SD4
B5
–5V
SA1
OSC
A6
SD3
B6
DREQ2
–12V
SA0
GND
A7
SD2
B7
SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR#
MEMW#
SD8
MEMCS16#
IOCS16#
IRQB10
IRQB11
IRQB11
IRQ15
A8
SD1
B8
ZEROWS#
+12V
C2
D2
A9
SD0
B9
C3
D3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
IOCHRDY
AEN
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
GND
C4
D4
SMEMW#
SMEMR#
IOW#
C5
D5
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
C6
D6
C7
D7
IRQ14
IOR#
C8
D8
DACK0
DREQ0
DACK5
DREQ5
DACK6#
DREQ6
DACK7#
DREQ7#
VCC
DACK3#
DREQ3
DACK1#
DREQ1
REFRESH#
SYSCLK
IRQA7
C9
D9
C10
C11
C12
C13
C14
C15
C16
C17
C18
D10
D11
D12
D13
D14
D15
D16
D17
D18
SD9
SD10
SD11
SD12
SD13
SD14
SD15
IRQA6
SA8
IRQA5
MASTER#
GND
SA7
IRQA4
SA6
IRQA3
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4.6
AGP Connector
Table 4-12. AGP Slot (J13)
Pin#
B
A
Pin#
B
A
1
2
OVRCNT#
5.0V
12V
TYPEDET#
Reserved
USB-
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Vddq3.3
AD21
Vddq3.3
AD22
3
5.0V
AD19
AD20
4
USB+
GND
GND
GND
5
GND
AD17
AD18
6
INTB#
CLK
INTA#
RST#
C/BE2#
Vddq3.3
IRDY#
3.3Vaux
GND
AD16
7
Vddq3.3
FRAME#
Reserved
GND
8
REQ#
VCC3.3
ST0
GNT#
VCC3.3
ST1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NOTES:
ST2
Reserved
PIPE#
GND
Reserved
VCC3.3
DEVSEL#
Vddq3.3
PERR#
GND
Reserved
VCC3.3
TRDY#
STOP#
PME#
GND
RBF#
GND
Reserved
SBA0
VCC3.3
SBA2
SB_STB
GND
Reserved
SBA1
VCC3.3
SBA3
SERR#
C/BE1#
Vddq3.3
AD14
PAR
Reserved
GND
AD15
Vddq3.3
AD13
SBA4
SBA6
KEY
SBA5
SBA7
AD12
AD11
KEY
GND
GND
KEY
KEY
AD10
AD9
KEY
KEY
AD8
C/BE0#
Vddq3.3
Reserved
AD6
KEY
KEY
Vddq3.3
AD_STB0
AD7
AD31
AD29
VCC3.3
AD27
AD25
GND
AD30
AD28
VCC3.3
AD26
GND
GND
AD5
AD4
AD24
AD3
AD2
GND
Vddq3.3
AD1
Vddq3.3
AD0
AD_STB1
AD23
Reserved
C/BE3#
Reserved
Reserved
1. Reserved pins are only for future use by the AGP interface specification.
2. IDSEL# is not a pin on the AGP connector. AGP graphics components should connect the AD16 signal to
the 3. 3 volt IDSEL# function internal to the component.
3. All 3.3 volt cards leave the TYPEDET signal open. All 1.5 volt cards tie this signal hard to ground.
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4.7
Jumpers
Table 4-13 shows default Jumper settings.
Table 4-13. Default Jumper Settings
Jumper
Function
Settings
In – Enable Spread Spectrum
J14
Enable Spread Spectrum Clocking
Out – Disable Spread Spectrum (Default)
In – 66 MHz Processor Clock (Default)
Out – Reserved
J15
Clock Frequency Selection
1–2 Reserved
J20
On/Off
2–3 On (Default)
No Jumper Installed – Off
1–2 12 V
J21
J22
J23
J24
Flash BIOS VPP Select
Flash BIOS boot block control
SMI# Source
2–3 5 V (Default)
1–2 12 V
2–3 5 V (Default)
1–2 SMI# controlled by IOAPIC
2–3 SMI# controlled by PIIX4E (Default)
1–2 Normal Operation (Default)
2–3 Clear CMOS RAM
CMOS RAM Clear
4.7.1
4.7.2
Enable Spread Spectrum Clocking (J14)
This jumper is used to enable or disable spread spectrum clocking on the clock synthesizer. When
this jumper is in, a 0.5% down spread will be introduced into the PCI and processor clocks. The
default setting is no jumper installed, which disables spread spectrum clocking.
Clock Frequency Selection (J15)
This jumper controls the frequency of the processor clock. When the jumper is in, 66 MHz
operation is supported. This is the only setting supported by this evaluation kit.
Caution: Leave this jumper installed. When the jumper is out, 100 MHz processor clocks will be generated.
This position is not supported and may cause damage to the processor.
4.7.3
On/Off (J20)
This jumper is used to control the state of the ATX power supply. When this jumper is removed, the
power supply will be turned off. Placing the jumper in the 2-3 position will turn the power supply
on.
The 1-2 position is reserved and should not be used.
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4.7.4
Flash BIOS VPP Select (J21)
This jumper controls the voltage presented to the flash BIOS VPP pin. The 2-3 position supplies
5 V and is the default for normal operation. This position inhibits programming or erasing the flash
BIOS.
The 1-2 position supplies 12 V and should only be used if directed to do so by a utility that is used
to reprogram the BIOS.
4.7.5
Flash BIOS Boot Block Control (J22)
This jumper controls the Boot Block protection of the flash BIOS. When this jumper is in the 2-3
position, the boot block is locked and cannot be programmed. This is the default position of this
jumper.
The 1-2 position unlocks the boot block so that it can be erased and reprogrammed. This position
should only be used under the direction of a utility that is designed to reprogram the boot block of
the flash device.
4.7.6
4.7.7
SMI# Source Control (J23)
This jumper selects the source of the SMI# interrupt to the processor. Only the 2-3 position which
selects the PIIX4E is supported. The 1-2 position is reserved for future use.
CMOS RAM Clear (J24)
This jumper controls power to the battery backed-up CMOS RAM. This RAM is used to store
information about the system configuration that is required by the BIOS. The 1-2 position is for
normal operation. The 2-3 position allows for the RAM to be cleared.
To clear the RAM perform the following steps:
1. Remove power from the evaluation platform by removing jumper J20
2. Move J24 to the 2-3.
3. Disconnect the power supply (J11).
4. Install J24 in the 1-2 position.
5. Reconnect the power supply (J11).
6. Reboot the system and enter the BIOS setup screen to configure the system.
4.7.8
Push Button Switches
There are two push button switches on the evaluation board labeled S1 and S2.
• S1 is non-functional and reserved for future use.
• S2 is the reset button. Press S2 to force a hardware reset of the system.
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4.8
In-Circuit BIOS Update
The BIOS can be upgraded in-circuit. BIOS updates may periodically be posted to Intel’s
Developers’ site at http://www.intel.com/design/.
To reprogram the BIOS:
1. Set Jumper J21 and Jumper J22 to the 1-2 position on the evaluation platform.
2. Download the new BIOS upgrade file from Intel’s Developers’ web site.
3. Extract the BIOS upgrade zip file onto a bootable floppy.
4. Insert the floppy disk into the floppy drive attached to the evaluation board.
5. Reboot the evaluation board so that it boots from the floppy.
6. Follow the on-screen instructions.
7. When the BIOS update program is finished, power down the board and reset the jumpers at
J21 and J22 to the 2-3 position.
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5
The Celeron processor evaluation board is licensed with a single copy of Embedded BIOS and
Embedded DOS software from General Software, Inc.1 This software is provided for
demonstration purposes only and must be licensed directly from General Software, Inc. for
integration with new designs. General Software may be reached at (800) 850-5755, on the web at
http://www.gensw.com, or via email at sales@gensw.com.
BIOS updates may periodically be posted to the Intel Developers’ web site at
http://developer.intel.com/.
5.1
BIOS and Pre-Boot Features
The system’s pre-boot environment is managed with an adaptation of Embedded BIOS from
General Software. The pre-boot environment includes POST, Setup Screen System, Manufacturing
Mode, Console Redirection, Windows CE Loader (CE Ready), and Integrated BIOS Debugger. A
REFLASH tool is also available to update the BIOS image with new builds of Embedded BIOS
that may be obtained from General Software.
Before using the system, please read the following to properly configure CMOS settings, and learn
how to use the embedded features of the pre-boot firmware, Embedded BIOS.
The last two sections of this chapter provide the BIOS POST Codes and Beep codes.
5.2
Power-On Self-Test (POST)
When the system is powered on, Embedded BIOS tests and initializes the hardware and programs
the chipset and other peripheral components. During this time, POST progress codes are written by
the system BIOS to I/O port 80H, allowing the user to monitor the progress with a special monitor.
“Embedded BIOS POST Codes” on page 5-12 lists the POST codes and their meanings.
During early POST, no video is available to display error messages should a critical error be
encountered; therefore, POST uses beeps on the speaker to indicate the failure of a critical system
component during this time. Consult “Embedded BIOS Beep Codes” on page 5-15 for a list of
Beep codes used by the system’s BIOS.
POST displays its progress on the system video device, which may be the video screen if a VGA
card is used, or on a terminal emulation program’s screen if output is redirected over a serial port.
1. General Software™, the GS Logo, Embedded BIOS™, BIOStart™, CE-Ready™, and Embedded DOS™ are trademarks or registered
trademarks of General Software, Inc.
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Figure 5-1. BIOS POST Pre-Boot Environment
When the system is powered on for the first time, you’ll need to configure the system through the
Setup Screen System (described later) before peripherals, such as disk drives, are recognized by the
BIOS. The information is written to battery-backed CMOS RAM on the board’s Real Time Clock.
Should the board’s battery fail, this information will be lost and the board will need to be
reconfigured.
OEMs can modify the look-and-feel of POST with the Embedded BIOS adaptation kit. While the
demonstration BIOS looks and feels like a desktop PC, it is possible to eliminate messages, sounds,
delays, to make the POST effectively invisible.
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5.3
Setup Screen System
The system is configured from within the Setup Screen System, which is a series of menus that can
be invoked from POST by pressing the <DEL> key if the main keyboard is being used, or by
pressing ^C if the console is being redirected to a terminal program.
Figure 5-2. Embedded BIOS Setup Screen Menu
Once in the Setup Screen System (Figure 5-2), the user can navigate with the UP and DOWN
arrow keys from the main console, or use the ^E and ^X keys from the remote terminal program to
accomplish the same thing. TAB and ENTER are used to advance to the next field, and ‘+’ and ‘-’
keys cycle through values, such as those in the Basic Setup Screen, or the Diagnostics Setup
Screen.
5.3.1
Basic CMOS Configuration Screen
The system’s drive types, boot activities, and POST optimizations are configured from the Basic
Setup Screen (Figure 5-3). In order to use disk drives with your system, you must select
appropriate assignments of drive types in the left-hand column. Then, if you are using true floppy
and IDE drives (not memory disks that emulate these drives), you need to configure the drive types
themselves in the Floppy Drive Types and IDE Drive Geometry sections. Finally, you’ll need to
configure the boot sequence in the middle of the screen. Once these selections have been made,
your system is ready to use.
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Figure 5-3. Embedded BIOS Basic Setup Screen
5.3.2
Configuring Drive Assignments
Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS
allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and
Ide3), and memory disks when configured (Flash0, ROM0, RAM0, etc.) Figure 5-3 shows how the
first floppy drive (Floppy0) is assigned to drive A: in the system, and then how the first IDE drive
(Ide0) is assigned to drive C: in the system.
To switch two floppy disks around or two hard disks around, just map Floppy0 to B: and Floppy1
to A:, and for hard disks map Ide0 to D: and Ide1 to C:.
Caution: Take care to not skip drive A: when making floppy disk assignments, as well as drive C: when
making hard disk assignments. The first floppy should be A:, and the first hard drive should be C:.
Also, do not assign the same file system to more than one drive letter. Thus, Floppy0 should not be
used for both A: and B:. The BIOS permits this to allow embedded devices to alias drives, but
desktop operating systems may not be able to maintain cache coherency with such a mapping in
place.
A special field in this section entitled “Boot Method: (Windows CE/Boot Sector)” is used to
configure the CE Ready feature of the BIOS. For normal booting (DOS, Windows NT, etc.), select
“Boot Sector” or “Unused”.
5.3.2.1
Configuring Floppy Drive Types
If true floppy drive file systems (and not their emulators, such as ROM, RAM, or flash disks) are
mapped to drive letters, then the floppy drives themselves must be configured in this section.
Floppy0 refers to the first floppy disk drive on the drive ribbon cable (normally drive A:), and
Floppy1 refers to the second drive (drive B:).
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5.3.3
Configuring IDE Drive Types
If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are
mapped to drive letters, then the IDE drives themselves must be configured in this section. The
following table shows the drive assignments for Ide0-Ide3:
Table 5-1. IDE0-IDE3 Drive Assignments
File System Name
Controller
Master/Slave
Ide0
Ide1
Ide2
Ide3
Primary (1f0h)
Primary (1f0h)
Master
Slave
Secondary (170h)
Secondary (170h)
Master
Slave
To use the primary master IDE drive in your system (the typical case), just configure Ide0 in this
section, and map Ide0 to drive C: in the Configuring Drive Assignments section.
The IDE Drive Types section lets you select the type for each of the four IDE drives: None, User,
Physical, LBA, or CHS.
User
This type allows the user to select the maximum cylinders, heads, and sectors
per track associated with the IDE drive. This method is now rarely used since
LBA is now in common use.
Physical
This type instructs the BIOS to query the drive’s geometry from the controller
on each POST. No translation on the drive’s geometry is performed, so this type
is limited to drives of 512 Mbytes or less. Commonly, this is used with
embedded ATA PC Cards.
LBA
CHS
This type instructs the BIOS to query the drive’s geometry from the controller
on each POST, but then translate the geometry according to the industry-
standard LBA convention. This supports up to 16-Gbyte drives. Use this method
for all new drives.
This type instructs the BIOS to query the drive’s geometry from the controller
on each POST, but then translate the geometry according to the Phoenix CHS
convention. Using this type on a drive previously formatted with LBA or
Physical geometry might show data as being missing or corrupted.
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5.4
Configuring Boot Actions
Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the
entire system has been initialized, POST executes these steps in order until an operating system
successfully loads. In addition, other pre-boot features can be run before, after, or between
operating system load attempts. The following actions can be used:
Drive A: - K:
Boot operating system from specified drive. If “Loader” is set to “BootRecord”
or “Unused”, then the standard boot record will be invoked, causing DOS,
Windows95/98, Windows NT, or other industry-standard operating systems to
load. If “Boot Method” is set to “Windows CE”, then the boot drive’s boot
record will not be used, and instead the BIOS will attempt to load and execute
the Windows CE Kernel file, NK.BIN, from the root directory of each boot
device.
Debugger
Launch the Integrated BIOS Debugger. To return to the boot process from the
debugger environment, type “G” at the debugger prompt and press ENTER.
MFGMODE
WindowsCE
DOS in ROM
Initiate Manufacturing Mode, allowing the system to be configured remotely
via an RS232 connect to a host computer.
Execute a ROM-resident copy of Windows CE, if available. This feature is not
applicable unless properly configured by the OEM in the BIOS adaptation.
Execute a ROM-resident copy of DOS, if available. This feature is not
applicable unless an XIP copy of DOS, such as Embedded DOS-ROM, has been
stored in the BIOS boot ROM. Copies of Embedded DOS-ROM may be
obtained from General Software.
None
No action; POST proceeds to the next activity in the sequence.
5.5
Custom Configuration Setup Screen
The system’s hardware-specific features are configured with the Custom Setup Screen
(Figure 5-4). All features are straightforward except for the Redirect Debugger I/O option, which is
an extra embedded feature that allows the user to select whether the Integrated BIOS Debugger
should use standard keyboard and video or RS232 console redirection for interaction with the user.
If no video is available, the debugger is always redirected.
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Figure 5-4. Embedded BIOS Custom Setup Screen
5.6
Shadow Configuration Setup Screen
The system’s Shadow Configuration Setup Screen (Figure 5-5) allows the selective enabling and
disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM,
which is shadowed as a unit. Normally, shadowing should be enabled at C000/C400 (to enhance
VGA ROM BIOS performance), and then E000-F000 should be shadowed to maximize system
ROM BIOS performance.
Figure 5-5. Embedded BIOS Shadow Setup Screen
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5.7
Standard Diagnostics Routines Setup Screen
Embedded systems may require automated burn-in testing in the development cycle. This facility is
provided directly in the system’s system BIOS through the Standard Diagnostics Routines Setup
Screen (Figure 5-6). To use the system, selectively enable or disable features to be tested, and then
enable the “Tests Begin on ESC?” option to cause the system test suite to be invoked. To repeat the
system test battery continuously, you should also enable the “Continuous Testing” option. When
continuous testing is started, the system will continue until an error is encountered.
Caution: The disk I/O diagnostics perform write operations on those drives; therefore, only spare drives
should be used which do not contain data that could be harmed by the test.
Caution: The keyboard test may fail when in fact the hardware is operating within reasonable limits. This is
because although the device may produce occasional errors, the BIOS retries operations when
failures occur during normal operation of the system.
Figure 5-6. Standard Diagnostic Routines Setup Screen
5.8
Start System BIOS Debugger Setup Screen
The Embedded BIOS Integrated Debugger may be invoked from the Setup Screen main menu, as
well as a boot activity. Once invoked, the debugger will display the debugger prompt:
EB42DBG:
and await debugger commands. To resume back to the Setup Screen main menu, type the following
command, which instructs the debugger to “go”:
EB42DBG: G <ENTER>
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5.9
Start RS232 Manufacturing Link Setup Screen
The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as
well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the
console of the system (Figure 5-7). The host can resume operation of the system and give control
back to the system Setup Screen system with special control software.
Figure 5-7. Start RS232 Manufacturing Link Setup Screen
5.10
Manufacturing Mode
The system’s BIOS provides a special mode, called Manufacturing Mode, that allows the target to
be controlled by a host computer such as a laptop or desktop PC. Running special software
supplied by General Software, the host can access the target’s drives and manage the file systems
on the target, reprogram flash memories, and test target hardware.
A full discussion of the uses of Manufacturing Mode is beyond the scope of this chapter. Complete
documentation and host-side software is available directly from General Software. For more
information, visit the General Software web site at http://www.gensw.com.
5.10.1
Console Redirection
The system can operate either with a standard PC/AT or PS/2 keyboard and VGA video monitor, or
with a special emulation of a console over an RS232 cable connected to a host computer running a
terminal program. To see an example session with HYPERTERMINAL, see the debugger section’s
screen display (Figure 5-9).
To use the Console Redirection feature, simply remove the video display card from the system so
that no video ROM is available for the BIOS to detect. In the absence of any video support, the
BIOS automatically switches its keyboard and screen functions to serial I/O over COM1 on the
board. The hardware connection to the host computer requires a null modem cable.
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The software on the target can be any terminal emulation program that supports ANSI terminal
mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during
BIOS adaptation.) The program must be set to not use flow control, or the console may seem to
stall or not accept input.
Caution: HYPERTERMINAL’s default setting is to use flow control, which will render the console
inoperative. To change this, create a new session, change the flow control setting to “none”, save
the session, and exit HYPERTERMINAL. Then reinvoke HYPERTERMINAL with the session
and it will operate with the new flow control setting.
5.10.2
CE-Ready Windows CE Loader
Your system’s BIOS is “CE-Ready” and can directly boot Windows CE* without loading an
intermediate operating system such as DOS and LOADCEPC. Instead, the NK.BIN file can be
placed on a disk drive or drive emulator, and then the BIOS can be configured through the Basic
CMOS Configuration Setup Screen to boot the NK.BIN file from the boot drives instead of the
boot records on those drives.
To configure your system to boot Windows CE natively from a disk drive, set the “Boot Method”
field to “Windows CE” in the Basic CMOS Configuration Setup Screen. Then, place a copy of
NK.BIN suitable for execution by LOADCEPC in the root directory of your normal boot drive,
such as drive C:. Then, reboot the system. The configuration box should be displayed (Figure 5-8),
and immediately following should be the message “Loading Windows CE…” followed by a series
of dots, indicating that the loading process is continuing. Once fully loaded, Windows CE takes
over the system and runs using the standard PC keyboard, screen, and PS/2 mouse.
Figure 5-8. CE-Ready Boot Feature
5.10.3
Integrated BIOS Debugger
The system’s BIOS contains a built-in debugger that can be a valuable tool to aid the board bring-
up process on new designs similar to the evaluation board. It supports a DOS SYMDEB-style
command line interface, and can be used on the main console’s keyboard and screen, or over a
redirected connection to a terminal program (see “Console Redirection” on page 5-9).
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To activate the debugger at any time from the main console, press the left shift and the control keys
together. A display similar to the one in the HYPERTERMINAL session below (Figure 5-9) will
appear, containing the title, “Embedded BIOS Debugger Breakpoint Trap” and a snapshot of the
processor general registers.
Figure 5-9. Integrated BIOS Debugger Running Over a Remote Terminal
To leave the debugger and resume the interrupted activity (whether POST, BIOS, DOS, Windows,
or an application program), enter the “G” command (short for “go”) and press ENTER. If you were
at a DOS prompt when you entered the debugger, then DOS will still be waiting for its command,
and will not prompt again until you press ENTER again.
The debugger can also be entered from the Setup Screen System, and as a boot activity (see “Basic
CMOS Configuration Screen” on page 5-3), as a last ditch effort during board bring-up and
development if no bootable device is available.
If your version of DOS, an application, or any OEM-supplied BIOS extensions have debugging
code (i.e., “INT 3” instructions) remaining, then these will invoke the debugger automatically,
although this is not an error. To continue, use the “G” command. When Embedded BIOS is adapted
by the OEM, the debugger can be removed from the final production BIOS, and superfluous
debugging code in the application will not cause the debugger to be invoked.
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BIOS Quick Reference
A complete discussion of the debugger is beyond the scope of this chapter; however, complete
documentation is available from General Software via the web at http://www.gensw.com.
5.11
Embedded BIOS POST Codes
Embedded BIOS writes progress codes, also known as POST codes, to I/O port 80H during POST,
in order to provide information to OEM developers about system faults. These POST codes may be
monitored on the on-board Post Code Debugger located at U12 and U13. They are not displayed on
the screen. For more information about POST codes, contact General Software.
Mnemonic Code
Code System Progress Report
POST_STATUS_START
POST_STATUS_CPUTEST
POST_STATUS_DELAY
00h Start POST (BIOS is executing).
01h Start CPU register test.
02h Start power-on delay.
POST_STATUS_DELAYDONE
POST_STATUS_KBDBATRDY
POST_STATUS_DISABSHADOW
POST_STATUS_CALCCKSUM
POST_STATUS_CKSUMGOOD
POST_STATUS_BATVRFY
POST_STATUS_KBDCMD
03h Power-on delay finished.
04h Keyboard BAT finished.
05h Disable shadowing & cache.
06h Compute ROM CRC, wait for KBC.
07h CRC okay, KBC ready.
08h Verifying BAT command to KB.
09h Start KBC command.
POST_STATUS_KBDDATA
POST_STATUS_BLKUNBLK
POST_STATUS_KBDNOP
0ah Start KBC data.
0bh Start pin 23,24 blocking & unblocking.
0ch Start KBC NOP command.
POST_STATUS_SHUTTEST
POST_STATUS_CMOSDIAG
POST_STATUS_CMOSINIT
POST_STATUS_CMOSSTATUS
POST_STATUS_DISABDMAINT
POST_STATUS_DISABPORTB
POST_STATUS_BOARD
0dh Test CMOS RAM shutdown register.
0eh Check CMOS checksum.
0fh Initialize CMOS contents.
10h Initialize CMOS status for date/time.
11h Disable DMA, PICs.
12h Disable Port B, video display.
13h Initialize board, start memory bank detection.
14h Start timer tests.
POST_STATUS_TESTTIMER
POST_STATUS_TESTTIMER2
POST_STATUS_TESTTIMER1
POST_STATUS_TESTTIMER0
POST_STATUS_MEMREFRESH
POST_STATUS_TESTREFRESH
POST_STATUS_TEST15US
POST_STATUS_TEST64KB
POST_STATUS_TESTDATA
POST_STATUS_TESTADDR
POST_STATUS_TESTPARITY
POST_STATUS_TESTMEMRDWR
POST_STATUS_SYSINIT
POST_STATUS_INITVECTORS
POST_STATUS_8042TURBO
POST_STATUS_POSTTURBO
POST_STATUS_POSTVECTORS
POST_STATUS_MONOMODE
POST_STATUS_COLORMODE
POST_STATUS_TOGGLEPARITY
15h Test 8254 T2, for speaker, port B.
16h Test 8254 T1, for refresh.
17h Test 8254 T0, for 18.2Hz.
18h Start memory refresh.
19h Test memory refresh.
1ah Test 15usec refresh ON/OFF time.
1bh Test base 64KB memory.
1ch Test data lines.
20h Test address lines.
21h Test parity (toggling).
22h Test Base 64KB memory.
23h Prepare system for IVT initialization.
24h Initialize vector table.
25h Read 8042 for turbo switch setting.
26h Initialize turbo data.
27h Modification of IVT.
28h Video in monochrome mode verified.
29h Video in color mode verified.
2ah Toggle parity before video ROM test.
POST_STATUS_INITBEFOREVIDEO 2bh Initialize before video ROM check.
5-12
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BIOS Quick Reference
POST_STATUS_VIDEOROM
POST_STATUS_POSTVIDEO
POST_STATUS_CHECKEGAVGA
2ch Passing control to video ROM.
2dh Control returned from video ROM.
2eh Check for EGA/VGA adapter.
POST_STATUS_TESTVIDEOMEMORY 2fh No EGA/VGA found, test video memory.
POST_STATUS_RETRACE
30h Scan for video retrace signal.
31h Primary retrace failed.
POST_STATUS_ALTDISPLAY
POST_STATUS_ALTRETRACE
POST_STATUS_VRFYSWADAPTER
POST_STATUS_SETDISPMODE
POST_STATUS_CHECKSEG40A
POST_STATUS_SETCURSOR
POST_STATUS_PWRONDISPLAY
POST_STATUS_SAVECURSOR
POST_STATUS_BIOSIDENT
POST_STATUS_HITDEL
32h Alternate found.
33h Verify video switches.
34h Establish display mode.
35h Initialize ROM BIOS data area.
36h Set cursor for power-on msg.
37h Display power-on message.
38h Save cursor position.
39h Display BIOS identification string.
3ah Display "Hit <DEL> to ..." message.
40h Prepare protected mode test.
41h Prepare descriptor tables.
42h Enter virtual mode for memory test.
43h Enable interrupts for diagnostics mode.
44h Initialize data for memory wrap test.
45h Test for wrap, find total memory size.
46h Write extended memory test patterns.
47h Write conventional memory test patterns.
48h Find low memory size from patterns.
49h Find high memory size from patterns.
4ah Verify ROM BIOS data area again.
4bh Check for <DEL> pressed.
POST_STATUS_VIRTUAL
POST_STATUS_DESCR
POST_STATUS_ENTERVM
POST_STATUS_ENABINT
POST_STATUS_CHECKWRAP1
POST_STATUS_CHECKWRAP2
POST_STATUS_HIGHPATTERNS
POST_STATUS_LOWPATTERNS
POST_STATUS_FINDLOWMEM
POST_STATUS_FINDHIMEM
POST_STATUS_CHECKSEG40B
POST_STATUS_CHECKDEL
POST_STATUS_CLREXTMEM
POST_STATUS_SAVEMEMSIZE
POST_STATUS_COLD64TEST
POST_STATUS_COLDLOWTEST
POST_STATUS_ADJUSTLOW
POST_STATUS_COLDHITEST
POST_STATUS_REALMODETEST
POST_STATUS_ENTERREAL
POST_STATUS_SHUTDOWN
POST_STATUS_DISABA20
POST_STATUS_CHECKSEG40C
POST_STATUS_CHECKSEG40D
POST_STATUS_CLRHITDEL
POST_STATUS_TESTDMAPAGE
POST_STATUS_VRFYDISPMEM
POST_STATUS_TESTDMA0BASE
POST_STATUS_TESTDMA1BASE
POST_STATUS_CHECKSEG40E
POST_STATUS_CHECKSEG40F
POST_STATUS_PROGDMA
4ch Clear extended memory for soft reset.
4dh Save memory size.
4eh Cold boot: Display 1st 64KB memtest.
4fh Cold boot: Test all of low memory.
50h Adjust memory size for EBDA usage.
51h Cold boot: Test high memory.
52h Prepare for shutdown to real mode.
53h Return to real mode.
54h Shutdown successful.
55h Disable A20 line.
56h Check ROM BIOS data area again.
57h Check ROM BIOS data area again.
58h Clear "Hit <DEL>" message.
59h Test DMA page register file.
60h Verify from display memory.
61h Test DMA0 base register.
62h Test DMA1 base register.
63h Checking ROM BIOS data area again.
64h Checking ROM BIOS data area again.
65h Program DMA controllers.
POST_STATUS_INITINTCTRL
POST_STATUS_STARTKBDTEST
POST_STATUS_KBDRESET
POST_STATUS_CHECKSTUCKKEYS
POST_STATUS_INITCIRCBUFFER
66h Initialize PICs.
67h Start keyboard test.
80h Issue KB reset command.
81h Check for stuck keys.
82h Initialize circular buffer.
POST_STATUS_CHECKLOCKEDKEYS 83h Check for locked keys.
POST_STATUS_MEMSIZEMISMATCH 84h Check for memory size mismatch.
POST_STATUS_PASSWORD
85h Check for password or bypass setup.
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BIOS Quick Reference
POST_STATUS_BEFORESETUP
86h Password accepted.
POST_STATUS_CALLSETUP
POST_STATUS_POSTSETUP
POST_STATUS_DISPPWRON
POST_STATUS_DISPWAIT
POST_STATUS_ENABSHADOW
POST_STATUS_STDCMOSSETUP
POST_STATUS_MOUSE
87h Entering setup system.
88h Setup system exited.
89h Display power-on screen message.
8ah Display "Wait..." message.
8bh Shadow system & video BIOS.
8ch Load standard setup values from CMOS.
8dh Test and initialize mouse.
8eh Test floppy disks.
POST_STATUS_FLOPPY
POST_STATUS_CONFIGFLOPPY
POST_STATUS_IDE
8fh Configure floppy drives.
90h Test hard disks.
POST_STATUS_CONFIGIDE
POST_STATUS_CHECKSEG40G
POST_STATUS_CHECKSEG40H
POST_STATUS_SETMEMSIZE
POST_STATUS_SIZEADJUST
POST_STATUS_INITC8000
POST_STATUS_CALLC8000
POST_STATUS_POSTC8000
POST_STATUS_TIMERPRNBASE
POST_STATUS_SERIALBASE
POST_STATUS_INITBEFORENPX
POST_STATUS_INITNPX
91h Configure IDE drives.
92h Checking ROM BIOS data area.
93h Checking ROM BIOS data area.
94h Set base & extended memory sizes.
95h Adjust low memory size for EBDA.
96h Initialize before calling C800h ROM.
97h Call ROM BIOS extension at C800h.
98h ROM C800h extension returned.
99h Configure timer/printer data.
9ah Configure serial port base addresses.
9bh Prepare to initialize coprocessor.
9ch Initialize numeric coprocessor.
9dh Numeric coprocessor initialized.
9eh Check KB settings.
POST_STATUS_POSTNPX
POST_STATUS_CHECKLOCKS
POST_STATUS_ISSUEKBDID
POST_STATUS_RESETID
9fh Issue keyboard ID command.
0a0h KB ID flag reset.
POST_STATUS_TESTCACHE
POST_STATUS_DISPSOFTERR
POST_STATUS_TYPEMATIC
POST_STATUS_MEMWAIT
0a1h Test cache memory.
0a2h Display soft errors.
0a3h Set keyboard typematic rate.
0a4h Program memory wait states.
0a5h Clear screen.
POST_STATUS_CLRSCR
POST_STATUS_ENABPTYNMI
POST_STATUS_INITE000
POST_STATUS_CALLE000
POST_STATUS_POSTE000
POST_STATUS_DISPCONFIG
POST_STATUS_INT19BOOT
POST_STATUS_LOWMEMEXH
POST_STATUS_EXTMEMEXH
POST_STATUS_PCIENUM
0a6h Enable parity and NMIs.
0a7h Initialize before calling ROM at E000h.
0a8h Call ROM BIOS extension at E000h.
0a9h ROM extension returned.
0b0h Display system configuration box.
00h Call INT 19h bootstrap loader.
0b1h Test low memory exhaustively.
0b2h Test extended memory exhaustively.
0b3h Enumerate PCI busses.
5-14
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BIOS Quick Reference
5.12
Embedded BIOS Beep Codes
Embedded BIOS tests much of the system hardware early in POST before messages can be
displayed on the screen. When system failures are encountered at these early stages, POST uses
beep codes (a sequence of tones on the speaker) to identify the source of the error.
The following is a comprehensive list of POST beep codes for the system BIOS. BIOS extensions,
such as VGA ROMs and SCSI adapter ROMs, may use their own beep codes, including short/long
sequences, or possibly beep codes that sound like the ones below. When diagnosing a system
failure, remove these adapters if possible before making a final determination of the actual POST
test that failed.
Mnemonic Code
Beep CountDescription of Problem
POST_BEEP_REFRESH
POST_BEEP_PARITY
POST_BEEP_BASE64KB
POST_BEEP_TIMER
POST_BEEP_CPU
1
Memory refresh is not working.
Parity error found in 1st 64KB of memory.
Memory test of 1st 64KB failed.
T1 timer test failed.
2
3
4
5
CPU test failed.
POST_BEEP_GATEA20
POST_BEEP_DMA
6
7
Gate A20 test failed.
DMA page/base register test failed.
Video controller test failed.
Keyboard test failed.
CMOS shutdown register test failed.
External cache test failed.
POST_BEEP_VIDEO
POST_BEEP_KEYBOARD
POST_BEEP_SHUTDOWN
POST_BEEP_CACHE
POST_BEEP_BOARD
POST_BEEP_LOWMEM
POST_BEEP_EXTMEM
POST_BEEP_CMOS
POST_BEEP_ADDRESS_LINE
POST_BEEP_DATA_LINE
POST_BEEP_INTERRUPT
POST_BEEP_PASSWORD
8
9
10
11
12
13
14
15
16
17
18
1
General board initialization failed.
Exhaustive low memory test failed.
Exhaustive extended memory test failed.
CMOS restart byte test failed.
Address line test failed.
Data line test failed.
Interrupt controller test failed.
Incorrect password used to access SETUP.
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PLD Code Listing
A
The code listing below is for the 22V10 PLD.
TITLE
22V10 PORT 80 ADDRESS DECODER / FLASH DECODE
PATTERN
REVISION
AUTHOR
COMPANY
DATE
1
B
CHRIS BANYAI
INTEL CORPORATION
10/1/97
OPTIONS
SECURITY = OFF
; ( part was 22V10FN before conversion )
CHIP P80B iPLD22V10N
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
19
3
IOWR_BAR
AEN
[6:7]
[9:13]
16
SA[0:1]
SA[2:6]
SA7
[5:4]
[26:23]
[21:20]
2
SA[8:9]
SA[19:16]
SA[15:14]
SEL
PIN
PIN
PIN
18
17
27
/CS_BAR
/CS_DOC
OX
EQUATIONS
CS_BAR = /IOWR_BAR * /AEN * /SA0 * /SA1 * /SA2 * /SA3 * /SA4 * /SA5 * /SA6
* SA7 * /SA8 * /SA9
CS_BAR.TRST = VCC
CS_DOC = /SEL * /AEN * SA19 * SA18 * /SA17 * /SA16 * SA15 * /SA14
+ SEL * /AEN * SA19 * SA18 * /SA17 * SA16 * /SA15 * /SA14
CS_DOC.TRST = VCC
OX = /IOWR_BAR
OX.TRST = VCC
SIMULATION
SETF /AEN /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 IOWR_BAR
SETF SA7 IOWR_BAR
SETF /IOWR_BAR
SETF IOWR_BAR
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PLD Code Listing
SETF AEN /IOWR_BAR
SETF /AEN
SETF IOWR_BAR
SETF SA0 /IOWR_BAR
SETF /SA0 /IOWR_BAR
SETF IOWR_BAR
SETF /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9
SETF /SA19 /SA18 /SA17 /SA16 /SA15 /SA14
SETF /SEL
SETF SA19 SA18 /SA17 /SA16 SA15 /SA14
SETF /SEL
SETF /AEN
SETF /SA19
SETF SA19
SETF /SA18
SETF SA18
SETF SA17
SETF /SA17
SETF SA16
SETF /SA16
SETF /SA15
SETF SA15
SETF SA14
SETF /SA14
SETF /SEL
SETF SA19 SA18 /SA17 SA16 /SA15 /SA14
SETF /SEL
SETF /AEN
SETF SEL
SETF /SA19
SETF SA19
SETF /SA18
SETF SA18
SETF SA17
SETF /SA17
SETF /SA16
SETF SA16
SETF SA15
SETF /SA15
SETF SA14
SETF /SA14
SETF /SEL
A-2
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Bill of Materials
B
Table B-1 is the bill of materials for the baseboard. Table B-2 is the bill of materials for the
Processor Assembly.
Table B-1. Baseboard Bill of Materials (Sheet 1 of 4)
Reference
Description
Manufacturer
3M
Manufacturer P/N
929647-09-02
Notes
Conn,Jumper2,1X2 25-mil sq/
100-mil space,HDR2
J14,J15
J20-24
JP2
Conn,Jumper3,1X3 25-mil sq/
100-mil space,HDR3
3M
3M
929647-09-03
929647-09-04
Conn,Speaker,1X4 25-mil sq/
100-mil space,HDR4
DO NOT
POPULATE
J10
NOT POPULATED
J12
Conn,Fan
AMP
AMP
173981-3
822271-1
XU9
PLCC, Socket 28
Conn,CPU,400 Pin Array
(BGA),BGA40X10-400R
J19
U6
Berg
74219-002
IC,Clock
Generator,CK100,SSOP300-
48(PIN)
Cypress
CY2280PVC-11S
IC,Clock Buffer,Zero Delay
U26
3.3V,16PIN,150MIL,TSSOP,PSS Cypress
OP16
CY2309ZC-1H
IC,Clock Buffer,18 Output low
Cypress
U16
Y2
CY2318ANZPVC-1
MC-405
skew,SSOP300-48(PIN)
Crystal,32.768KHz,XTAL/MC-
Epson
405
DO NOT
POPULATE
J16
Conn,SDRAM DIMM,168 Pin
Recept
J17,J18
FOXCONN
AT08403-K8
J4
J3
Conn, Serial Stack,DB9MX2
Conn, DB25,DB25FM1
FOXCONN
FOXCONN
DM10156-73
DT11323-R5T
Conn,PCI Edge Recept,145154-
120
J7,J8,J9
FOXCONN
EH06001-PC-W
J5,J6
JP1
Conn,ISA Edge Recept.,isa-98
Conn,Floppy,17X2 Header
Conn, IDE,20X2 Header
FOXCONN
FOXCONN
FOXCONN
FOXCONN
EQ04901-S6
HL07173-P4
HL07206-D2
HM20100-P2
JP3,JP4
J11
Conn,Power,5566DP-20/ATX
Conn,PS2 Keyboard / Mouse
Connector
J1
FOXCONN
MH11067-D2
Conn,AGP Edge Recept., 120
pins,AGP-124
J13
J2
FOXCONN
FOXCONN
PC1243K-10
UB1112C-D3
2 USB Stack Connectors
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Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 2 of 4)
Reference
Description
Manufacturer
INTEL
Manufacturer P/N
28F002BC
Notes
BIOS FLASH
Memory,TSOP12X20/40S
U11
U8
VLSI,PIIX4,PCI to IDE &ISA
Bridge,324 mBGA,BGA20x20-
324
Intel
FW82371EB
IC,Interrupt Controller,
82093AA,QFP16x22-64
DO NOT
POPULATE
U14
INTEL
Kemet
S82093AA
C99,C100,C132,C133,C2
09,C214
Chip Capacitor,10pF,
50V,CC0603
C0603C100J5GAC
C: 22,42-43,48-49,54,59-
65,70-71,73,75-76,85-
87,90-92,96-97, 102,106-
108,111-112,114,116-118,
126-127,129-
131,142,147,157,159-162,
174-176,181-183, 187-
200,205-206,208,226-228
DO NOT
POPULATE
C143,
C146,C203,
C210, C215
Chip Capacitor,0.1uF,
16V,CC0603
Kemet
C0603C104K4RAC
C27-C41,C44-C47,C50-
C53
Chip Capacitor,470pF,
50V,CC0603
Kemet
C0603C471K5RAC
T491C106K016AS
C3-5,C8,C55-57,
C94,C119-121,
Cap,Tant,10uF,15V,C Case,6032 Kemet
C134,C138,C145, C153
C93,C103-105,
C128,C152, C154-156
Cap,Tant,47uF, 20V,D
Kemet
T491D476M020AS
T495D107M010AS
Case,7343
C2,C6,C58,C72,
C84,C88,C89,C95, C109
Cap,Tant,100uF, 10V,D
Kemet
Case,7343
C1,C7,C23,C66-
C68,C74,C77-C82,
C101,C113,C115,
C141,C158,C163-
173,C177-180, C184-
186,C201-
Chip Capacitor,0.01uF
Kemet
C0603C103J5RAC
50V,CC0603
202,C204,C207, C211-
213,C216-217,C220-C225
U9
IC,PLD,PLCC28,Socket28
LATTICE
GAL22V10B-7LJ
LT1117-3.3cst
IC,Linear Voltage
Regulator,SOT-223
U23
Linear Tech.
Linear Tech.
Meritec
IC,Linear Voltage
Regulator,SOT-223
U5
LT1117CST
40TSOP BIOS
Socket,TSOP12X20/40S
XU11
980020-40-01
XU12,XU13
U25
TIL311 SOCKET,DIP14
MILLMAX
Motorola
Murata
110-99-314-41-001
MC74ACT05DR
BLM41A800S
IC,Logic,74ACT05,SO14
Ferrite Bead,SM1806,Z-Bead
IC,Logic,74ALS00,SOIC14
FB1-FB9
U22
National
DM74ALS00M
IC,Tranciever,8-Bit Bidirectional
Buffer,SOIC20,SO20W
U7
National
DM74ALS245AWM
ECE-A1EU221
Cap,Electrolitic,220uF,
25v,6.3mmx11.2mm,PCAPR200 Panasonic
-300
C69,C83,C98,C110
B-2
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Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 3 of 4)
Reference
Description
Manufacturer
Manufacturer P/N
Notes
DO NOT
POPULATE
R33, R35,
R37
R33,R35,R37,R48,R52,R9
8-R100, R106,R108-
R116,R118-R122
Chip Resistor,0 Ohm
Shunt,5%,CR0805
Panasonic
ERJ6GEY0R00V
DO NOT
POPULATE
R6, R51
R6,R25,R42,R45,R49-
R51,R63,R101,R102
Chip Resistor,1K,5%,CR0805
Chip Resistor,10K,5%,CR0805
Panasonic
Panasonic
ERJ6GEYJ102V
ERJ6GEYJ103V
R2,R4,R5,R11,R40,R41,R
43,R53-
R56,R97,R105,R117,R123
-124,R127
R1,R3,R88,R89.R90,R91
R9
Chip Resistor,15K,5%,CR0805
Chip Resistor,22,5%,CR0805
Panasonic
Panasonic
ERJ6GEYJ153V
ERJ6GEYJ220V
R10,R12,R13,R14,R39,R5
8,R70
Chip Resistor,220,5%,CR0805
Panasonic
ERJ6GEYJ221V
R92-R95
Chip Resistor,27,5%,CR0805
Chip Resistor,2.7K,5%,CR0805
Panasonic
Panasonic
ERJ6GEYJ270V
ERJ6GEYJ272V
R20,R44,R57,R71
R17-R19,R21-R24,R26-
R32,R34,R36,R38
Chip Resistor,33,5%,CR0805
Chip Resistor,470,5%,CR0805
Chip Resistor,4.7k,5%,CR0805
Chip Resistor,8.2K,5%,CR0805
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ6GEYJ330V
ERJ6GEYJ471V
ERJ6GEYJ472V
ERJ6GEYJ822V
EVQ-PHP03T
R103,R104
R7,R64-R69,
R125,R126,R128
R72-R87,R96,R107
S1,S2
Switch-Push Button,PBSW/
PNASNC2
RP2,RP3,RP41-
RP47,RP54-RP56,
RP58,RP60,RP61
Res,Array,SMT,33,5%,EXB-V
Res,Array,SMT,1K,5%,EXB-V
Panasonic
Panasonic
EXB33V330JV
EXB38V102JV
RP10,RP18,RP23
RP8-9,RP11,RP13-
17,RP19-RP22,
RP24,RP26-33, RP35-36,
RP39, RP51-52,RP59
Res,Array,SMT,10K,5%,EXB-V
Panasonic
EXB38V103JV
RP1,RP4,RP48
Res,Array,SMT,22,5%,EXB-V
Res,Array,SMT,2.7K,5%,EXB-V
Panasonic
Panasonic
EXB38V220JV
EXB38V272JV
RP25,RP37,RP38,RP40,R
P49,RP50,RP53
RP57
Res,Array,SMT,47,5%,EXB-V
Res,Array,SMT,4.7K,5%,EXB-V
Res,Array,SMT,5.6k,5%,EXB-V
Panasonic
Panasonic
Panasonic
EXB38V470JV
EXB38V472JV
RP5,RP6,RP7
RP12,RP34
IC,Logic,Inverter, Schmitt
Trigger,SOIC14
U24
U10
Philips
74HCT14D
QS3384SO
IC,Logic,10 Bit Bus
Switch,QSOP,SO24W
Quality Semi
Crystal,14.318MHz,XTAL,FOX-
HC495D
Y1
Raltron
AS-14.31818-20
SMD250-2
F1-F3
Fuse,Drawing,SM250
RayChem
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Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 4 of 4)
Reference
Description
Manufacturer
Renata
Manufacturer P/N
HU-2032-1
Notes
XBT1
BT1
Battery Holder Socket
Battery
Reneta
Siemens
SMSC
CR2032
D1,D2,D5
U1
Diode,LED,SOT23-A
VLSI,Super I/O,QFP128
LGS260-DO
FDC37B78X
DO NOT
POPULATE
C229
C122-C125,C229
Chip Capacitor,47pF,CC0603
TDK
C1608C0G1H470JT$
C9-C21,C24-C26
Chip Capacitor,220pF,CC0603
IC,Logic,3 state buffer,SOP-14
IC,Logic,SOP-14
TDK
TI
C1608X7R1H221KT009A
74LVC125A
U15
U21
TI
74LVC14A
IC,RS232 Transceiver,
SOIC20,SO20W
U3,U4
U2
TI
TI
GD75232DW
SN7407D
IC,Logic,Open Drain Buffer,SOP-
14
U12,U13
7 Segment LED display,DIP14
Schottky Diode,SOT23-E
TI
TIL311
BAT54
D3-D4,D6-D7
R8,R15,R16,R46,R47
ZETEX
Chip Resistor,124,1%,CR0805
Micron
32 MB SDRAM DIMMS
Semiconductor
Prdcts
MT4LSDT464AG-662B2
B-4
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Bill of Materials
Table B-2. Celeron™ Processor Assembly Bill of Materials (Sheet 1 of 2)
Reference
Descriptions
Manufacturer
Manufacturer P/N
C1
CAP
CAP
CAP
20 pF
25V
50V
10V
CC0603
CC0603
CC0603
Panasonic
Panasonic
Panasonic
ECU-V1H200JCM
ECJ-1VB1H472K
ECJ-1VB1C103K
C117
4700pF
0.01uF
C84-C85, C94-C98
C2-9, C48,C50-83,C86-
93,C100-
103,C106,C110,C113,C115,C
116,C128-C129,C131-
C132,C137-C138, C140-
C142,C145-C146
CAP
0.1uF
16V
CC0603
Panasonic
ECJ-1VB1C104K
C10-C24,C30-C34,C40-
C44,C112,C114,C126,C133-
136
CAP
CAP
1uF
10V
10V
CC0805
CC1206
Panasonic
Panasonic
ECJ-2YB1A105K
ECJ-3YF1C475Z
C25-C29,C35-C39,C45-
C47,C139
4.7uF
C122-C125
C49
CAP
CAP
10uF
33uF
16V
16V
CC1210
3528
Panasonic
Kernet
Do Not Populate
T491B226M010AS
PCAPR20
0-300
C104-C105,C127,C130,
CAP
CAP
470uF
16V
16V
Panasonic
Panasonic
EEU-FC1C471L
EEU-FC1C222
PCAPR20
0-500
C107-C109,C111,C118-C121
2200uF
D1
Diode
BAT54
22 uH
4.7uH
SOT23
Zetex
BAT54CT-ND
L1
Inductor
Inductor
CR0805
IND1855
Murata
LQG21C220N00T1
L2,L3
Bi Technologies HM00-98637A
NPN
Transistor
Q1
MMBT3904
SOT23
Fairchild
MMBT3904
RP1-RP2
Resistor Pac 1K
EXB-V
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
EXB-V8V102JV
EXB-V8V560JV
EXB-V8V331JV
ERJ-6GEY0R00V
ERX-1SJ1R1
RP33-RP62
Resistor Pac 56 ohm
Resistor Pac 330
EXB-V
RP63
EXB-V
R9,R12,R54,R66,R78,R79
R14
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0
CR0805
CR0805
CR1206
CR0805
CR0805
CR0805
1.1
2.2
10
22
51
R68,R71,R72
R65,R63
ERJ-6RQJ2R2V
ERJ-6GEYJ100V
ERJ-6GEYJ220V
ERJ-6GEYJ510V
R19,R26-R27
R4,R41,R48,R50,R51,R77
R1,R7,R8,R31,R46,R47,R49,
R52
Resistor
Resistor
Resistor
Resistor
Resistor
270
330
1K
CR0805
CR0805
CR0805
CR0805
CR0805
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-6GEYJ271V
ERJ-6GEYJ331V
ERJ-6GEYJ102V
ERJ-6GEYJ332V
ERJ-6GEYJ102V
R10
R2-R3, R15,R32-R39,R42-
R43,R45,R53,R64,R67,R80
R11,R13,R40,R44
3.3K
10K
R16-R18,R20-R25,R28-
R30,R70
Celeron™ Processor Development Kit Manual
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Bill of Materials
Table B-2. Celeron™ Processor Assembly Bill of Materials (Sheet 2 of 2)
Reference
Descriptions
47K
Manufacturer
Manufacturer P/N
R75,R73
R55,R56
R60
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
CR0805
CR0805
CR0805
CR0805
CR0805
CR0805
CR0805
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-6GEYJ472V
ERJ-6ENF0750V
ERJ-6ENF1000V
ERJ-6ENF1100V
ERJ-6ENF1500V
ERJ-6ENF1001V
ERJ-6ENF2321V
75 1%
100 1%
110 1%
150 1%
1.00K 1%
2.32K 1%
R6,R5
R57-R59
R61
R62
3 milliOhm
5%
R69,R74,R76
Resistor
CR2512
SO14
Dale/Vishay
WSL-2512 0.003 5%
Texas
Instruments
U2,U3
U4
Logic
74LVC07A
443BX_10
SN74LVC07AD
FW82443BX
74220-001
BGA Chip
Intel
BGA
Connector
BGA40X1
0-400
U5
Berg
U6
U7
Temp Sensor MAX1617
QSOP16
SO16
Maxim
MAX1617MEE
QS3257
Logic
Logic
Logic
FET
QS3257
74LVQ00
SC1185
Quickswitch
National
Semiconductor
U8
SO14
74LVQ00
U9
SO24W
TO252
TO252
Semtech
Siliconix
Motorola
SC1185
SUD50N03-
07
U10,U11
U12,U13
SUD50N03-07-T4
FET
MTD3055V
MTD3055V
Processor, 370-pin, 37x37 PPGA, 366 MHz
OR (depends on kit purchased)
FV80524RX366128
U1
Intel
Processor, 370-pin, 37x37 PPGA, 433 MHz
FV80524RX433128
916783-2
Socket
Socket
Header
Socket370
Socket370
ITP
AMP
XU1
Foxconn
AMP
PZ37047S1T-S-001
104068-3
J2
J1
J3
104068-3
173981-3
644518-4
Fan
Connector
Connector
Connector
AMP
AMP
173981-3
644518-4
4 Pin PWR
B-6
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Schematics
C
The most current schematics, including “flat” schematics (without the 400-pin connector), are
located on Intel’s Developer Web site at: http://www.intel.com/design/intarch/schems/.
Schematics are provided for the following items:
Baseboard:
• Block Diagram
• Mini-PCI Connector (Not Populated)
• Processor Assembly Connector
• DIMM0
• DIMM1
• DIMM2 (Not Populated)
• Clocks
• ISA/PCI Pullups
• PCI Slots 0 & 1
• PCI Slot 2
• AGP Connector
• PIIX4 Part 1
• PIIX4 Part 2
• IDE Connectors
• Super I/O
• USB Connectors
• ISA Connectors
• COMx, DB25, Floppy
• BIOS/ Port 80
• ATX Power Connector
• Unused Gates
Processor Assembly:
• Socket 370A Host Interface
• Socket 370B Power Supply
• GTL+ Termination Resistors - Bridge System/Controller
• GTL+ Termination Resistors - Processor
• 82443BX - Bus Interface
• 82443BX - Memory Interface
• Connector Hardware
• ITP/Bus Ratio/Thermal Sensor
• Voltage Regulator
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T P
1
T P
1
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T P
1
V D D A P I C
V D D C P U
V D D C P U
4 6
4 1
3 7
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
4 3
3 8
3 4
3 2
2 4
2 0
1 8
1 2
6
A V D D
A V D D
V D D R E F
V D D U S B
V D D P C I
V D D P C I
3 3
1 9
4 8
2 1
9
1 5
3
5
6
7
8
4
3
2
1
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
4 6
4 2
3 7
3 3
2 9
2 3
2 0
1 6
1 2
7
4 3
3 9
3 4
3 0
2 7
2 6
2 2
1 9
1 5
1 0
6
1
1
2
2
5
6
7
8
4
3
2
1
3
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1
3
G N D
G N D
G N D
5 2
3 3
1
V C C
V C C
V C C
5 1
1 9
6 4
1
3
1
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T P
1
T P
1
2
T P
1
1
T P
1
T P
T P
1
V C C S U S
V C C S U S
V C C S U S B
R 1 6
N 1 6
K 5
V S S U S B
J 5
V S S
M 1 2
V C C P
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
V S S
E 9
M 1 1
M 1 0
M 9
V C C P
V C C P
V C C P
V C C P
V C C P
V C C P
V C C P
V C C P
E 1 2
E 1 6
F 5
F 1 4
G 6
R 7
P 1 5
T 6
L 1 2
L 1 1
L 1 0
L 9
K 1 2
K 1 1
K 1 0
K 9
V C C
F 6
V C C
V C C
V C C
V C C
E 1 1
F 1 5
R 6
J 1 2
J 1 1
J 1 0
J 9
R 1 5
E 1 3
E 7
D 1 0
2
1
1
3
3
1
2
1
2
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I N
2
1
O U T
3
N C
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2
1
2
1
S M D 2 5 0 - 0 0 2
P M E # / I R Q 9
B U T T O N _ I N
P O W E R O N
2 1
2 0
1 9
V S S
V S S
V S S
V S S
A V S S
1 0 4
7 4
4 8
7
V B A T
V T R
V C C
V C C
V C C
6 5
6 9
1 2 1
9 3
6 2
6 7
5
6
7
8
4
3
2
1
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2
2
1
1
2
2
1
1
1
2
1
2
1
2
1
2
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2 7
2 6
5
6
7
8
4
3
2
1
5
6
7
8
4
3
2
1
5
6
7
8
4
3
2
1
1
2
3
4
8
7
6
5
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2
T P
T P
T P
T P
1
1
1
1
2
T P
T P
T P
T P
1
1
1
1
T P
1
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I N
2
1
O U T
3
N C
I N
2
1
O U T
3
N C
T P
1
2
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4
1 0
1 3
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5
6
7
8
4
3
2
1
5
6
7
8
4
3
2
1
C
V C
D
G N
C
V C
D
G N
1 4
7
1 4
7
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E C A R E F I N T
A G P
PCI ARB & PWR
MGT
PCI
INTERFACE
3
1
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A 4 V I
A 3 V I
A 2 V I
A 1 V I
4
3
2
1
A 4 V I
A 3 V I
A 2 V I
A 1 V I
4
3
2
1
A 4 V I
A 3 V I
A 2 V I
A 1 V I
4
3
2
1
A 4 V I
A 3 V I
A 2 V I
A 1 V I
4
3
2
1
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2
1
2
2
1
1
2
1
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
1
1
2
2
2
1
2
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3
2
3
2
3
2
3
2
1
2
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Index
#, defined 1-1
440BX AGPset 3-2
82371EB PCI ISA IDE Xcelerator (PIIX4E) 2-1, 3-4
82443BX Host Bridge/Controller 2-1
D
DIMM
installing 2-7
Documents online 1-2
DRAM 3-4
Drive assignments 5-4
A
Address size 3-3
AGP connector 3-5, 4-10
AGP support 2-1, 3-2, 3-3
ATX power connector 4-3
E
Embedded BIOS 2-3, 5-1
Embedded BIOS Integrated Debugger 5-8
Embedded BIOS Manufacturing Mode 5-9
Evaluation board 2-1
B
Expansion slots 4-2
Baseboard 2-1
Beep codes 5-1, 5-15
BIOS 2-7
F
Basic Setup Screen 5-3
configuring 2-7
Floppy connector 4-7
Floppy drive 2-4, 3-5
installing 2-7
Configuring floppy drives 5-4
Configuring IDE drives 5-5
console redirection 5-9
Custom Setup Screen 5-6
Drive assignments 5-4
Integrated BIOS debugger 5-10
Setup Screen System 5-2
Shadow Configuration Setup Screen 5-7
Standard Diagnostics Routines Setup Screen 5-
8
G
General Software, Inc. 2-3
H
Hard disk
BIOS updates 4-13
Block diagram 3-1
installing 2-6
Boot ROM 3-4
I
I/O, legacy support 3-4
IDE connectors (JP3, JP4) 4-6
IDE interface 3-5
C
CD-ROM drive 2-4
Celeron™ Processor 2-1
Clock synthesizer 3-6
Clocking 3-3
Installation 2-5
Instructions, notational conventions 1-1
Intel® Celeron™ Processor 2-1
ISA connectors 3-5
ITP Debugger connector 4-4
ITP debugger port 3-3
Connectors
J1, keyboard and mouse 4-5
J11, power connector 4-3
J13, AGP connector 4-10
J2, ITP connector 4-4
J2, USB connector 4-4
J3, parallel port 4-5
J4, serial ports 4-6
JP1, floppy connector 4-7
JP4/JP3, IDE connector 4-6
J
Jumpers
default settings 4-11
J14, enable spread spectrum clocking 4-11
Celeron™ Processor Development Kit Manual
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J15, clock frequency selection 4-11
J20, on/off 4-11
J21, flash BIOS VPP select 4-12
J22, flash BIOS boot block control 4-12
J23, SMI# source control 4-12
J24, CMOS RAM clear 4-12
R
RTC 3-4
S
Serial ports 3-5, 4-6
Setup instructions 2-5
Signals, notational conventions 1-2
Software Key Features 2-3
K
Keyboard 2-4, 3-5, 4-5
Kit contents 2-2
T
Technical support 1-2
M
Measurements, defined 1-2
Memory address space 3-3
Memory interface 2-1
Memory Map 3-7
U
Units of measure, defined 1-2
USB connector 4-4
Mouse 2-4, 3-5, 4-5
USB support 3-5
N
V
Notational conventions 1-1
NVRAM 3-4
Video Adapter 2-4
O
W
Online help 1-2
Windows CE 5-10
World Wide Web 1-2
www.intel.com 1-2
P
Parallel port 3-5, 4-5
PCI connectors 3-5
PLD A-1
Post Code Debugger 3-6, 4-1
POST codes 5-1, 5-12
Power connector 4-3
Power LEDs 2-7
Power supply 2-4, 3-4
connecting 2-7
Power-on Self Test (POST) 5-1
Processor assembly 2-1
Product literature, ordering 1-3
Q
QNX Real-Time Operating System 2-6
QNX Software Systems, Ltd. 2-4
Index-2
Celeron™ Processor Development Kit Manual
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