Intel Computer Hardware IXD1110 User Manual

®
Intel IXD1110 Demo Board  
Development Kit Manual  
June 2003  
Document Number: 250807  
Revision Number: 003  
Revision Date: June 27, 2003  
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Contents  
Contents  
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Contents  
Figures  
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Intel IXD1110 Demo Board (Top View)...............................................................9  
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Intel IXF1110 CPU Daughter Card....................................................................13  
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Intel IXD1110 Demo Board Power (Revision A1) .............................................25  
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Intel IXD1110 Digital Power ..............................................................................26  
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Intel IXD1110 Analog Power.............................................................................27  
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Intel IXD1110 Control........................................................................................28  
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Intel IXD1110 SerDes GBIC Ports 0-2..............................................................29  
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Intel IXD1110 SerDes GBIC Ports 3-5..............................................................30  
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Intel IXD1110 SerDes GBIC Ports 6-8..............................................................31  
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Intel IXD1110 SerDes GBIC Port 9...................................................................32  
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Intel IXD1110 SPI4-2 ........................................................................................33  
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Intel IXD1110 LEDs...........................................................................................34  
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Intel IXD1110 CPU Interface Control ................................................................35  
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Intel IXD1110 CPU Connectors ........................................................................36  
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Intel IXD1110 CPU Logic Probe Connectors ....................................................37  
Tables  
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Intel IXD1110 Demo Board Principal Components.............................................9  
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Intel IXF1110 Reset Test Points .......................................................................20  
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Intel IXF1110 Differential Input Clock Test Points.............................................20  
8
Mictor Connector Test Points..............................................................................21  
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Intel IXD1110 Demo Board Bill of Materials (Rev. A1)......................................38  
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Revision History  
Revision 003  
Rev. Date: June 27, 2003  
Page #  
Description  
Added second bullet under Section 2.0, “Quick Start”.  
Modified Figure 3, “Intel® IXF1110 CPU Daughter Card”.  
Modified pin 8 description in Table 3, “JTAG Test Signals (JP1)”.  
Revision Number: 002  
Revision Date: July 31, 2002  
Page Number Description  
Revision Number: 001  
Revision Date: May 31, 2002  
Page Number Description  
Initial release.  
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Contents  
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Document Number: 250807  
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IXD1110 Demo Board  
1.0  
Introduction  
This document describes all the necessary requirements, settings, and procedures for evaluating the  
®
Intel IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (MAC) using the  
®
Intel IXD1110 demo board. For immediate operation, refer to Section 2.0, “Quick Start” on  
The IXD1110 demo board kit includes a CPU daughter card that attaches to the underside of the  
®
board. Through the CPU daughter card, the Intel IXF1010/IXF1110 10-Port 100/1000 Ethernet  
MAC Demonstration Software (included on the CD) provides access to all IXF1110 registers and  
RMON statistics.  
Additional sections include information about LEDs, test points, board schematics, and a bill of  
materials.  
Note: For comprehensive information in evaluating the IXF1110 using the IXD1110 demo board, use the  
IXF1110 Demonstration Software Help File and the IXF1110 Datasheet (document number  
250210) in conjunction with this document.  
1.1  
1.2  
About This Kit  
The IXD1110 demo board kit includes the following:  
IXD1110 demo board with CPU daughter card  
IXF1110 Demonstration Software CD (includes a software help file)  
SPI4-2 loopback connector  
IXD1110 Demo Board Development Kit Manual  
Additional Equipment Required  
The following additional equipment is required for board setup:  
Packet Generator with 1000BASE-SX capabilities  
3.3 V DC power supply with 6A current capability  
2.5 V DC power supply with 6A current capability  
1.8 V DC power supply with 6A current capability  
One to ten fiber cables (for data transmission)  
Two CAT5-UTP cables (for IXF1110 software)  
DB-9–to–RJ-45 converter [optional] (for IXF1110 software)  
PC (for IXF1110 software) (see Section 5.1, “PC Requirements” on page 15)  
GBIC SFP modules [up to 10] (Agilent* HFBR-5710L)  
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IXD1110 Demo Board  
1.3  
About The IXD1110 Demo Board  
The IXD1110 demo board provides a working platform for the evaluation of the IXF1110 in  
1000 Mbps fiber optic applications. All ten network ports provide a 1000BASE-SX connection  
through the GBIC Small Form Factor Pluggable (SFP) modules (not included).  
The IXD1110 demo board contains one IXF1110 device, one SPI4-2 interface connector, ten GBIC  
SFP connectors, and one plug-in CPU daughter card. The SPI4-2 interface connector allows for  
loopback connection.  
Note: In loopback mode, the board cannot be tested or used with other devices or equipment.  
Connection can be made to an alternate SPI4-2 device or to another IXD1010 or IXD1110 demo  
board utilizing a SPI4-2 connector board. In these modes, the SPI4-2 interface can be tested for  
lengths greater than that in loopback mode.  
The attached CPU daughter card uses the IXF1110 CPU interface to access all registers and RMON  
statistics through the supplied IXF1110 software.  
1.3.1  
Features  
The following is a list of IXD1110 demo board features and evaluation capabilities:  
Ten IEEE 802.3 compliant 1000BASE-SX MAC ports  
SPI4-2 interface  
— Capable of data transfers up to 12.8 Gbps  
— Supports SPI4-2 loopback mode (default)  
— Can be connected to another SPI4-2 device (optional)  
For example, a SPI4-2 enabled daughter card (FPGAs, bridges, etc.)  
SerDes interface with GBIC SFP modules not included  
Motorola* MCP860 32-bit CPU  
— Mounted on the daughter card, which is attached to the bottom side of the demo board  
(see Figure 2)  
Access to all supported registers for full evaluation  
Access to all RMON statistics registers  
Broadcast, multicast, and unicast address filtering capability  
Independent port enable/disable  
Programmable option to filter packets with errors  
Compliance with IEEE 802.3x flow control standard  
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IXD1110 Demo Board  
1.3.2  
Component Location and Description  
Figure 1 illustrates the top view of the IXD1110 demo board.  
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Figure 1. Intel IXD1110 Demo Board (Top View)  
GBIC SFP  
Connectors  
GND  
1.8VIXF  
2.5 V IXF  
3.3 V  
2.5 V  
Port 0  
Port 1  
Port 2  
Port 3  
Port 4  
EPROM  
SMB Connectors  
Mictor Connector  
Probe D  
FPGA  
JP1  
J
T
A
G
Intel®  
IXF1110  
SPI4-2  
Connector  
Mictor Connector  
Probe C  
Port 5  
Port 6  
Port 7  
Port 8  
Port 9  
Mictor Connector  
Probe A  
Reset  
S1  
JP2  
Intel® IXF1110  
LEDs  
Table 1 provides a list of the various principal components found on the IXD1110 demo board.  
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Table 1. Intel IXD1110 Demo Board Principal Components  
Component  
IXF1110  
Description  
10-port Gigabit MAC that supports IEEE 802.3 1000 Mbps applications. Refer to the  
IXF1110 Datasheet for additional information.  
The IXF1110 uses a serial interface consisting of three signals to provide LED data to  
an external driver. This interface provides the data for 30 separate direct drive LEDs  
and allows three LEDs per MAC port. Refer to Section 7.0, “LEDs” on page 19.  
IXF1110 LEDs  
This jumper provides access to the JTAG test signals. Refer to Section 6.2, “JTAG  
JP1  
JP2  
This reset jumper is required for proper board operation. Refer to Section 6.1, “Reset  
Jumper JP2” on page 18 for more information.  
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.  
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IXD1110 Demo Board  
®
Table 1. Intel IXD1110 Demo Board Principal Components (Continued)  
Component  
Description  
S1  
Reset Switch: This switch resets the entire board when pressed.  
SPI4-2 Interface  
Connector  
Allows a loopback connection when the loopback module is installed. This connector  
can also interface with alternate SPI4-2 connections.  
Mictor Connectors A, Provide access to selected IXF1110 signals. Refer to Section 8.4, “Mictor Connectors”  
C, and D1  
on page 21 for more information.  
GBIC Connectors  
These connectors allow for SFP modules (Agilent* HFBR-5710L).  
Converts the IXF11110 asynchronous CPU signals into a synchronous format. Refer  
to Section 4.1, “CPU FPGA” on page 14 for more information.  
FPGA  
EPROM  
EPROM is used to program the FPGA.  
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.  
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IXD1110 Demo Board  
2.0  
Quick Start  
The quick-start procedure allows for IXF1110 1000 Mbps SerDes data transfer evaluation in the  
following interfaces:  
IXF1110 SPI4-2 loopback data transfer  
2
I C signals  
CPU interface  
2.1  
Setup  
The following quick-start procedure uses the IXIA* 1600T packet generator to evaluate the  
IXD1110 demo board. All ports on the IXF1110 are set to a default setting of 1000 Mbps  
1. Set reset jumper JP2 to the HRESET position.  
2. Jumper pins 6 and 8 of JP1.  
3. Install optic modules on all ten ports.  
4. Connect the IXF1110 optic modules to the external ports on the IXIA* 1600T LM1000SX  
cards.  
5. Verify that the CPU daughter card is installed on the bottom of the board.  
6. Verify that the SPI4-2 loopback module is connected to the SPI4-2 connector.  
7. Connect the 1.8 V DC power supply to BN1 (“1.8 V IXF”).  
8. Connect the 2.5 V DC power supply to BN4 (“2.5 V IXF”) and BN5 (“2.5 V”).  
9. Connect the 3.3 V DC power supply to BN6 (“3.3 V”).  
10. Connect all power supply return lines to ground BN3 (“GND”).  
11. With the board properly configured, proceed in the following order:  
a. Apply +1.8 V DC power  
b. Apply +2.5 V DC power  
c. Apply+3.3 V, DC power  
d. Press reset switch S1  
12. Once the CPU Daughter Card has completed autoboot, the board is ready for evaluation of  
standard packets (64 - 1518 bytes) at 1000 Mbps full-duplex on all ports.  
13. To access registers and RMON statistics, install the IXF1110 software. Instructions are  
change the default settings of the IXF1110 and configure the device for other modes of  
operation.  
14. Proceed with evaluation as desired.  
Note: The IXF1110 software modifies some of the IXF1110 registers on power-up. For a complete list of  
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IXD1110 Demo Board  
3.0  
Typical Test Setup  
Figure 2 shows a typical test setup for standard operation of the IXF1110 (see Section 2.0, “Quick  
Start” on page 11 for step-by-step details). The IXD1110 demo board can be connected to an  
IXIA* 1600T packet generator with LM1000SX cards for evaluation of the board. Each port can be  
connected to the IXIA* box with fiber cables. For IXF1110 software use, connect CAT5-UTP  
cables to the ports shown on the CPU daughter card. One of the cables connects to the COM port  
on the IXIA* box by using a DB-9–to–RJ-45 connector. The other cable connects to the network  
page 16 for proper installation.  
Note: The IXF1110 evaluation software can be run from the IXIA or an added PC connected to the CPU  
daughter card.  
Figure 2. Typical Test Setup  
Connect to  
COM port  
Demo Software  
IXIA* 1600T  
Advanced Multi-port Performance Tester  
DB-9-to-RJ-45  
Connector  
Fiber Connectors  
Power  
Supplies  
Monitor  
for IXIA  
Connect To  
Network Port  
LM1000SX  
Cards  
GBIC SFP  
Modules  
Fiber  
Cables  
Intel®  
SPI4-2  
SPI4-2  
Loop-back  
IXF1110  
Connector  
CPU Daughter  
Card  
Intel® IXD1110  
Demo Board  
TCP/IP connection  
UTP to Serial Connection  
CAT5 UTP  
B1895  
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IXD1110 Demo Board  
4.0  
CPU Daughter Card  
The IXD1110 demo board uses the Embedded Planet* RPX Classic LF (CLLF_BW31), a single-  
board computer that uses the Motorola* MPC860 CPU. This card attaches to the underside of the  
board and is used to interface with the IXF1110 CPU interface. Figure 3 provides a top-level view  
of the CPU daughter card.  
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Figure 3. Intel IXF1110 CPU Daughter Card  
CPU Daughter  
Card  
IP Address located on  
the side of the connector  
RJ-45 #1 10Mbps  
Ethernet Connection  
Not Used  
RJ-45 #2 Serial  
Connection  
The IXF1110 software requires the proper connections to the daughter card as follows:  
Note: For full operation of the IXF1110 software, RJ-45 #1 and #2 (see Figure 3) must be connected to a  
PC.  
RJ-45 #1 (10 Mbps Ethernet): Requires the following connection (this connection gives access  
to the GUI):  
— CAT5-UTP cable (connected to the CPU daughter card)  
— Network port on a PC (connected to the CAT5-UTP cable), installed with IXF1110  
software  
RJ-45 #2 (Serial): Requires a connection that gives access to the HyperTerminal interface of  
complete setup information).  
Table 2 provides the DB-9–to–RJ-45 connector pinout for connection to a PC COM port.  
Only three pins are used for the DB-9–to–RJ-45 connector.  
Table 2. Pinout for DB-9–to–RJ-45 Connector  
RJ-45 Pin Number  
DB-9 Pin Number  
4
5
6
5
3
2
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IXD1110 Demo Board  
For more information on the HyperTerminal and GUI interfaces, please refer to the IXF1110  
Software Help File.  
4.1  
4.2  
CPU FPGA  
The IXD1110 demo board has a Field Programmable Gate Array (FPGA) that allows the  
Motorola* CPU, which requires a synchronous interface, to interoperate with the asynchronous  
IXF1110 CPU interface.  
For additional information regarding the IXF1110 CPU interface, refer to the IXF1110 Datasheet.  
IXF1110 Register Modifications on Startup  
The Motorola* CPU automatically modifies some of the IXF1110 registers on startup to put the  
board in a 1000 Mbps evaluation mode. The following registers are modified from default settings  
on startup:  
TX FIFO Highwater Mark Ports 0-9 are set to 0x00000BB8  
RX FIFO Errored Frame Drop Enable is set to 0x000003FF  
MAC Transfer Threshold Ports 0-9 are set to 0x000003E8  
Diverse Config Ports 0-9 are set to 0x0000112D  
LED Control is set to 0x00000003  
For additional information on these registers, please refer to the IXF1110 Datasheet.  
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IXD1110 Demo Board  
5.0  
IXF1110 Software  
The IXF1110 software allows access to the following register blocks through the Graphical User  
Interface (GUI) or the Serial Monitor (HyperTerminal) interface:  
MAC Control  
MAC RX Statistics  
MAC TX Statistics  
Global Status and Configuration  
RX Block  
TX Block  
SPI4-2 Block  
SerDes Block  
GBIC Block  
For additional information on all of the registers, please refer to the IXF1110 Datasheet or On-Line  
Help.  
Note: For help on using IXF1110 software, refer to the On-Line Help included in the software provided  
with the IXD1110 demo board.  
5.1  
PC Requirements  
The following is a list of the minimum PC requirements for installation of the IXF1110 software:  
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®
Intel Pentium II 400 MHz or equivalent  
128 MB RAM  
16 MB Video Card  
Serial port  
Microsoft* Windows 98, 2000 operating system  
Note: Microsoft* Windows 95, ME, NT, and XP have not been tested.  
Microsoft* Windows HyperTerminal  
1024 x 768 minimum viewing resolution  
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IXD1110 Demo Board  
5.2  
Installing the IXF1110 Software  
For proper installation of the IXF1110 software, follow these steps:  
1. Verify that the CAT5-UTP cable is connected between the PC and the IXF1110 CPU daughter  
card. This allows access to the GUI interface. Refer to Section 4.0, “CPU Daughter Card” on  
page 13 for detailed installation instructions.  
2. (Optional) The following connection is required to access the HyperTerminal interface:  
— CAT5-UTP cable (connected to a CPU daughter card)  
— DB-9–to–RJ-45 connector (connected to a CAT5-UTP cable)  
— DB-9–to–RJ-45 connector (connected to a COM port on a PC installed with IXF1110  
software)  
For more information, refer to Section 4.0, “CPU Daughter Card” on page 13 for detailed  
instructions.  
3. Insert the CD into the PC.  
4. If your system supports Autorun, follow the on-screen instructions.  
5. If your system does not support Autorun, select Run... from the Start menu. The Run dialog  
opens.  
6. Select setup.exe from the CD in the Open: window (click Browse... to find setup.exe if not  
already in the window).  
7. Click OK.  
8. Follow the on-screen instructions.  
9. Locate the IXD1110 demo board IP address that is located on the CPU daughter card. The IP  
address is required each time the GUI is opened.  
10. Start the IXF1110 software GUI by double clicking the desktop icon.  
Note: The IXF1110 software includes online documentation that describes how to run the GUI and  
HyperTerminal interfaces. Refer to the quick-start section of the IXF1110 Demonstration Software  
Help File for additional instructions on use of these interfaces.  
5.3  
Changing the IP Address of the CPU Daughter Card  
(Optional)  
The CPU daughter card comes with a default IP address, which is listed on a sticker attached to the  
daughter card. The GUI uses this IP address to locate the IXD1110 demo board. The IP address  
may need to be changed depending on the PC or network to which the board is attached. Use the  
following procedure to permanently change the IP Address of the CPU daughter card:  
1. Ensure the IXD1110 demo board has been set up correctly (see Section 2.0, “Quick Start” on  
page 11).  
2. Open the HyperTerminal on the PC to which the CPU daughter card serial port is attached, and  
configure the relevant COM port with the following settings:  
Speed: 9600 Baud  
Databits: 8  
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IXD1110 Demo Board  
Parity: None  
Stops bits: 1  
Flow Control: None  
3. Press the reset button switch SW1. The following message appears on the HyperTerminal:  
MPC8xx PlanetCore Boot Loader v2.00  
Copyright 2001 Embedded Planet. All rights reserved.  
DRAM available size = 16 MB  
wvCV  
DRAM OK  
Autoboot in 2 seconds.  
ESC to abort, SPACE or ENTER to go.  
4. Press the ESC key to stop the Autoboot. The following message appears on the  
HyperTerminal:  
Autoboot aborted.  
>
5. Type the following at the > prompt:  
> set ip 10.254.21.34 (Changes the IP address to the value entered)  
> store (Permanently changes the IP address)  
> reset (Restarts the IXD1110 demo board)  
Once the Autoboot is complete, the GUI can access the IXD1110 demo board using the newly  
programmed IP address.  
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IXD1110 Demo Board  
6.0  
Optional Configurations  
6.1  
Reset Jumper JP2  
6.1.1  
Standard Operation  
The Reset Jumper JP2 is required for standard operation of the IXD1110 demo board. Use the  
HRESET position for standard operation.  
The POR position is not recommended for standard operation of the IXD1110 demo board. This  
configuration only affects the CPU operation, and does not affect IXF1110 operation. The only  
difference between HRESET and POR is that POR also resets the CPU PLLs and state machines.  
This difference is seen when reset is asserted by pressing switch S1. For more information on the  
POR position of JP2, refer to Table 12 (MPC860 Reset Responses) of the Motorola* MPC860 CPU  
Datasheet.  
6.2  
JTAG Test Signals  
The boundary scan test port for the IXF1110 is accessed using JP1 for board-level testing. Table 3  
describes JTAG test signals.  
Note: For normal IXD1110 demo board operation, connect TRST_N pin 8 on JP1 to ground by  
jumpering pins 6 and 8 of JP1.  
Table 3. JTAG Test Signals (JP1)  
Pin  
Number  
IXF1110 Ball  
Designator  
Jumper  
Symbol  
Description  
1
TDI  
TDO  
TMS  
TCLK  
TRST  
GND  
AC18  
Y24  
T16  
AA29  
N18  
Test Data Input  
3
5
Test Data Output  
Test Mode Select  
JP1  
7
Test Clock  
8
Test Reset (jumper pins 6 and 8)  
Connect to system ground  
2,4,6  
18  
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IXD1110 Demo Board  
7.0  
LEDs  
Table 4 describes the behavior of the Link LED - Amber, Link LED - Green, and Activity LED for  
the IXF1110.  
Table 4. IXF1110 LED Behavior  
Type  
Status  
Description  
Synchronization has occurred but no packets are being  
received and the Link LED Enable Register (Addr:  
0x502) is not set.  
Off  
RX Synchronization has not occurred or no optical  
signal exists.  
Amber On  
Port has remote fault and the LED Fault Disable  
Register (Addr: 0x50B) is not set. Based on remote  
fault bit setting received in Rx_Config word.  
RxLED  
Amber Blinking  
RX Synchronization has occurred and the Link LED  
Enable Register (Addr: 0x502) bit is set.  
Green On  
RX Synchronization has occurred and port is receiving  
data.  
Green Blinking  
Off  
Port is not transmitting data or the Link LED Enable  
Register (Addr: 0x502)” is not set.  
TxLED  
Port is transmitting data and the Link LED Enable  
Register (Addr: 0x502)” bit is set.  
Green Blinking  
NOTES:  
1. The LED behavior table assumes the port is enabled in the Port Enable Register (Addr: 0x500) and the  
LEDs are enabled in the LED Control Register (Addr: 0x509). If a port is not enabled, all the LEDs for that  
port will be off. If the LEDs are not enabled, all of the LEDs will be off.  
2. For a detailed description of the LED interface and register information, refer to the IXF1110 Datasheet.  
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IXD1110 Demo Board  
8.0  
Test Points  
8.1  
Reset Test Points  
Two test points allow evaluation of the IXF1110 reset signals. TP21 allows IXF1110 Sys_Res  
signal monitoring. DTP3 allows board reset signal monitoring. The board Sys_Res can be  
monitored on both test points if it is asserted by Switch S1 or the CPU. The reset is seen at TP21 if  
an IXF1110 reset is issued by the software interface.  
®
Table 5. Intel IXF1110 Reset Test Points  
IXF1110 Ball  
Designator  
Test Point  
Symbol  
Description  
TP21  
DTP3  
Sys_Res  
Sys_Res  
Y4  
System reset for IXF1110  
Board reset  
NOTE: DTP = Differential Test Point, TP = Test Point  
8.2  
IXF1110 Input Clock Test Points  
The IXF1110 requires input clocks of 50 and 125 MHz. There are two test points that allow the  
user to monitor those signals (see Table 6).  
®
Table 6. Intel IXF1110 Differential Input Clock Test Points  
IXF1110 Ball  
Designator  
Test Point  
Symbol  
Description  
DTP1  
DTP2  
CLK125  
CLK50  
AA5  
C21  
125 MHz input clock for IXF1110  
50 MHz input clock for IXF1110  
NOTE: DTP = Differential Test Point  
8.3  
GBIC Test Points  
2
Table 7 lists GBIC test points that allow evaluation of the I C clock, which is connected to all of  
2
2
the GBIC modules, and the I C Data pins for each of the ten ports. For more information on the I C  
interface, refer to the IXF1110 Datasheet.  
Table 7. GBIC Test Points (Sheet 1 of 2)  
IXF1110 Ball  
Designator  
Test Point  
Symbol  
Description  
DTP6  
DTP7  
DTP8  
DTP9  
DTP10  
I2C_CLK  
L19  
G22  
G23  
J24  
I2C_CLK for IXF1110  
I2C_DATA_0  
I2C_DATA_1  
I2C_DATA_2  
I2C_DATA_3  
I2C_DATA_0 for IXF1110  
I2C_DATA_1 for IXF1110  
I2C_DATA_2 for IXF1110  
I2C_DATA_3 for IXF1110  
F22  
NOTE: DTP = Differential Test Point  
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Table 7. GBIC Test Points (Sheet 2 of 2)  
IXF1110 Ball  
Designator  
Test Point  
Symbol  
Description  
DTP11  
DTP12  
DTP13  
DTP14  
DTP15  
DTP16  
I2C_DATA_4  
I2C_DATA_5  
I2C_DATA_6  
I2C_DATA_7  
I2C_DATA_8  
I2C_DATA_9  
E23  
H24  
G20  
E22  
G24  
F24  
I2C_DATA_4 for IXF1110  
I2C_DATA_5 for IXF1110  
I2C_DATA_6 for IXF1110  
I2C_DATA_7 for IXF1110  
I2C_DATA_8 for IXF1110  
I2C_DATA_9 for IXF1110  
NOTE: DTP = Differential Test Point  
8.4  
Mictor Connectors  
Table 8 provides a detailed list of the Mictor Connector test points that are available using Mictor  
Connectors and that are designed for easy use with the Tektronix* P6434 Mass Termination Probe.  
Using these connectors with a Tektronix* logic analyzer allows the probing of the signals in  
Table 8. Mictor Connector Test Points (Sheet 1 of 2)  
IXF1110  
Ball  
Designator  
Address  
Bus and  
Other  
IXF1110  
Ball  
Designator  
Pause I/F  
andReset  
Signals  
IXF1110  
Ball  
Designator  
Probe  
A
CPU Data  
Bus  
Probe  
C
Probe  
D
A0(0) uPx_Data0  
A0(1) uPx_Data1  
A0(2) uPx_Data2  
A0(3) uPx_Data3  
A0(4) uPx_Data4  
A0(5) uPx_Data5  
B3  
A4  
C0(0)  
C0(1)  
C0(2)  
C0(3)  
C0(4)  
C0(5)  
C0(6)  
C0(7)  
C1(0)  
C1(1)  
C1(2)  
C1(3)  
C1(4)  
C1(5)  
C1(6)  
C1(7)  
C2(0)  
C2(1)  
C2(2)  
TA  
Start_XFER  
RD/~WR  
Gen_PCsN  
D0(0)  
D0(1)  
D0(2)  
D0(3)  
D0(4)  
D0(5)  
D0(6)  
D0(7)  
D1(0)  
D1(1)  
D1(2)  
D1(3)  
D1(4)  
D1(5)  
B9  
A7  
C12  
E11  
C13  
A8  
CsN  
A06)  
uPx_Data6  
Bus_request  
Bus_Busy  
Bus_Grant  
A0(7) uPx_Data7  
A1(0) uPx_Data8  
A1(1) uPx_Data9  
A1(2) uPx_Data10  
A1(3) uPx_Data11  
A1(4) uPx_Data12  
A1(5) uPx_Data13  
A1(6) uPx_Data14  
A1(7) uPx_Data15  
A2(0) uPx_Data16  
A2(1) uPx_Data17  
A2(2) uPx_Data18  
A10  
A9  
E12  
A11  
G12  
E10  
F11  
D7  
uPx_RdyN  
C22  
uPx_CsN  
uPx_WrN  
uPx_RdN  
F20  
A18  
H14  
D1(6) POR  
D1(7) HRESET  
D14  
C14  
F14  
uPx_Add0  
uPx_Add1  
uPx_Add2  
J1  
G4  
F3  
D2(0)  
D2(1)  
D2(2)  
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.  
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Table 8. Mictor Connector Test Points (Sheet 2 of 2)  
IXF1110  
Ball  
Designator  
Address  
Bus and  
Other  
IXF1110  
Ball  
Designator  
Pause I/F  
andReset  
Signals  
IXF1110  
Ball  
Designator  
Probe  
A
CPU Data  
Bus  
Probe  
C
Probe  
D
A2(3) uPx_Data19  
A2(4) uPx_Data20  
A2(5) uPx_Data21  
A2(6) uPx_Data22  
A2(7) uPx_Data23  
A3(0) uPx_Data24  
A3(1) uPx_Data25  
A3(2) uPx_Data26  
A12  
A15  
G13  
B16  
E15  
G14  
A16  
C17  
C2(3)  
C2(4)  
C2(5)  
C2(6)  
C2(7)  
C3(0)  
C3(1)  
C3(2)  
uPx_Add3  
uPx_Add4  
uPx_Add5  
uPx_Add6  
uPx_Add7  
uPx_Add8  
uPx_Add9  
uPx_Add10  
H1  
E3  
E2  
G1  
C3  
F5  
F1  
C2  
D2(3)  
D2(4)  
D2(5)  
D2(6)  
D2(7)  
D3(0)  
D3(1)  
D3(2)  
TxPause  
Add3  
A3(3) uPx_Data27  
A3(4) uPx_Data28  
A3(5) uPx_Data29  
A3(6) uPx_Data30  
A3(7) uPx_Data31  
A17  
B18  
A21  
B22  
C23  
C3(3)  
C3(4)  
C3(5)  
C3(6)  
C3(7)  
D3(3)  
D3(4)  
D3(5)  
D3(6)  
D3(7)  
Q0  
K1  
J2  
G2  
G3  
J7  
TxPause  
Add2  
TxPause  
Add1  
TxPause  
Add0  
TxPause  
Fr  
IRQ  
CLK_  
Bus_CLK  
0
CLK_  
3
CLK_  
1
CLK_  
2
Q1  
1. For evaluation of the signals provided by the Mictor connector, use the corresponding logic analyzer probe.  
8.5  
Power and Ground Test Points  
Table 9 provides the power and ground test points that allow the monitoring of voltages at various  
points on the board.  
Table 9. Power Test Points (Sheet 1 of 2)  
Test Point  
Symbol  
Description  
TP2  
TP3  
TP4  
TP5  
TP6  
TP8  
TP9  
TP19  
Vdd_1P8_IXF  
Vdd_2P5_IXF  
TxA25_A  
1.8 V for IXF1110  
2.5 V for IXF1110  
SerDes Tx Block A 2.5 V  
1.8 V for PLL1  
PLL1_aVdd  
PLL2_aVdd  
PLL3_aVdd  
TxA25_C  
1.8 V for PLL2  
2.5V for PLL3  
SerDes Tx Block C 2.5 V  
2.5 V rest of the board  
Vdd_2P5  
NOTE: TP = Test Point  
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Table 9. Power Test Points (Sheet 2 of 2)  
Test Point  
Symbol  
Vdd_3P3  
Description  
TP20  
TP22  
TP23  
TP24  
TP25  
TP26  
TP27  
TP28  
TP29  
TP30  
TP31  
3.3 V rest of the board  
TxAVTT_A  
TxAVTT_B  
RxAVTT_C  
RxA25_A  
RxAVTT_A  
TxA25_B  
SerDes Tx Block A 1.8 V  
SerDes Tx Block B 1.8 V  
SerDes Rx Block C 1.8 V  
SerDes Rx Block A 2.5 V  
SerDes Rx Block A 1.8 V  
SerDes Tx Block B 2.5 V  
SerDes Rx Block B 2.5 V  
SerDes Rx Block B 1.8 V  
SerDes Tx Block C 1.8 V  
SerDes Rx Block C 2.5 V  
RxA25_B  
RxAVTT_B  
TxAVTT_C  
RxA25_C  
NOTE: TP = Test Point  
Table 10 lists the various ground test points provided on the IXD1110 demo board.  
Table 10. Ground Test Points  
Test Point  
Symbol  
Description  
TP10  
TP11  
TP12  
TP13  
TP14  
TP15  
TP16  
TP17  
GND  
Ground Test Points  
NOTE: TP = Test Point  
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8.6  
Unused Test Points  
The unused test points are for internal testing only and are not designed for evaluation of the  
IXF1110 device. Table 11 provides a list of the unused test points.  
Table 11. Unused Test Points  
Test Points  
Description  
J29  
J30  
J31  
J32  
J33  
J34  
TP1  
J29, J30, 31, J32, J33, J34, and TP1 are not  
designated for IXF1110 evaluation  
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9.0  
Board Schematics  
®
Figure 4. Intel IXD1110 Demo Board Power (Revision A1)  
1
1
1
1
1
1
1
1
1
1
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Figure 5. Intel IXD1110 Digital Power  
1
1
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IXD1110 Demo Board  
®
Figure 6. Intel IXD1110 Analog Power  
1
1
1
1
PLL Power - 1.8 V  
Serdes Power - 2.5V  
Block B  
Block A  
Block C  
1
1
1
1
1
1
1
1
1
1
1
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®
Figure 7. Intel IXD1110 Control  
4 2  
R 8  
X
R 1 1  
4 2  
R 1  
X
R 2  
1
+
|
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Figure 8. Intel IXD1110 SerDes GBIC Ports 0-2  
P o r t 0  
S e r D e s / G B I C -  
P o r t 1  
S e r D e s / G B I C -  
P o r t 2  
S e r D e s / G B I C -  
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Figure 9. Intel IXD1110 SerDes GBIC Ports 3-5  
P o r t 3  
S e r D e s / G B I C -  
P o r t 4  
S e r D e s / G B I C -  
P o r t 5  
S e r D e s / G B I C -  
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Figure 10. Intel IXD1110 SerDes GBIC Ports 6-8  
P o r t 6  
S e r D e s / G B I C -  
P o r t 7  
S e r D e s / G B I C -  
P o r t 8  
S e r D e s / G B I C -  
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Figure 11. Intel IXD1110 SerDes GBIC Port 9  
P o r t 9  
S e r D e s / G B I C -  
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IXD1110 Demo Board  
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Figure 12. Intel IXD1110 SPI4-2  
SPI-4 Phase 2 - TX  
X
R - 2  
P h a s e S P I - 4  
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Figure 13. Intel IXD1110 LEDs  
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IXD1110 Demo Board  
®
Figure 14. Intel IXD1110 CPU Interface Control  
C
C
V C  
V C  
8
7
G N D  
5
CPU Bus Interface  
IXF1110 Interface  
1
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Figure 15. Intel IXD1110 CPU Connectors  
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Figure 16. Intel IXD1110 CPU Logic Probe Connectors  
G N D  
4 3  
G N D  
4 2  
G N D  
4 1  
G N D  
4 0  
G N D  
3 9  
G N D  
4 3  
G N D  
4 2  
G N D  
4 1  
G N D  
4 0  
G N D  
3 9  
G N D  
4 3  
G N D  
4 2  
G N D  
4 1  
G N D  
4 0  
G N D  
3 9  
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IXD1110 Demo Board  
10.0  
Bill of Materials  
®
Table 12. Intel IXD1110 Demo Board Bill of Materials (Rev. A1)  
Reference Designator  
BN1, 3-6  
Description  
Manufacturer1  
Part Number  
108-0740-001  
CONN BANANA  
NUT SILVER  
EF Johnson  
C1-2, 122-132, 134, 136-138, 140-145,  
147-148, 150-153, 155-157, 162-166,  
168-194, 300-319  
CAP .01UF 16V  
CER 10% X7R  
(0603)  
Panasonic  
Vishay  
ECJ-1VB1C103K  
293D106X9016B  
CAP 10UF 16V  
TANT SIZE B  
(CASEB)  
C3, 7-8, 12-13, 17-18, 22-23, 27-28, 32-  
33, 37-38, 42-43, 47-48, 52-53  
C6, 9-11, 14-16, 19-21, 24-26, 29-31, 34-  
36, 39-41, 44-46, 49-51, 54-55, 133, 135,  
139, 265, 275, 277, 282  
CAP 0.1UF 16V  
X7R (0603)  
Panasonic  
Panasonic  
Panasonic  
ECJ-1VB1C104K  
ECS-H1VY224R  
ECU-V1E223KBV  
CAP 0.22UF 35V  
TANT (CASEA)  
C106-109, 114-117  
C110-113, 118-121  
CAP .022UF 25V  
10% CER (0603)  
SMD  
CAP 10UF 16V  
TANT (CASEC)  
C259, 269, 272, 279  
C260, 270, 273, 280  
C261, 271, 274, 281  
C266, 276, 278, 283  
Kemet  
T491C106K016AS  
EEU-FC1E101S  
ECS-T1EY105R  
ECJ-1VB1H102K  
CAP 100UF 25V  
ELEC FC RADIAL  
Panasonic  
Panasonic  
Panasonic  
CAP 1.0UF 25V  
TANT (CASEA)  
CAP 1000PF 50V  
X7R (0603)  
CAP 10PF +/-  
0.5PF 50V NPO  
(0603) SMD  
C292-299  
Panasonic  
ECJ-1VC1H100D  
DIODE GREEN  
LED SS TYPE  
LOW CUR SMD  
D1, 3-4, 6-7, 9-10, 12-13, 15-16, 18-19,  
21-22, 24-25, 27-28, 30-31  
Panasonic  
Diodes, Inc.  
Panasonic  
LNJ308G8LRA  
LL4148  
DIODE LL4148  
SMD ( )  
D2  
DIODE AMBER  
LED SS TYPE  
LOW CUR SMD  
D5, 8, 11, 14, 17, 20, 23, 26, 29, 32  
LNJ408K8ZRA  
DTP1-3, 6-16  
FB1-2  
HEADER 2X1  
FBEAD  
Berg  
68000-240-2  
2961666671  
Fair-Rite  
RES 1.0 OHM 1/  
8W 1% (0805) SMD  
FB3, 8-18  
FB4, 5, 7  
J1-10  
Panasonic  
Panasonic  
AMP  
ERJ-6RQF1R0V  
ERJ-6RQF5R6V  
1367073-1  
RES 5.6 OHM 1/  
8W 1% (0805) SMD  
HOST CONN FOR  
HFBR-5701L  
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Table 12. Intel IXD1110 Demo Board Bill of Materials (Rev. A1) (Continued)  
Reference Designator  
Description  
Manufacturer1  
Part Number  
MISC BOTTOM  
EMI CAGE FOR  
HFBR-5710L  
J1-10  
AMP  
1367034-1  
MISC TOP EMI  
J1-10  
J1-10  
J25-26  
J28  
CAGE FOR HFBR- AMP  
5710L  
1367035-1  
IC FIBER MODULE  
HFBR-5710  
Agilent  
HFBR-5710L  
131-3711-201  
1469002-1  
CONN SMB  
STRAIGHT JACK  
RECPT  
Johnson  
Components  
HEADER 40 DIFF  
PAIR 120 PIN  
AMP  
JP1  
JP2  
HEADER 4X2  
HEADER 3X1  
Berg  
Berg  
C9192-280-4  
68000-240-3  
INDUCTOR 1UH  
SMD (1206)  
MLF3216A1R0KT00  
0
L1-20  
P1-2  
TDK  
AMP  
CONN PLUG  
ASSY 120 POS  
.8MM FHBB  
179031-5  
RES 42.2 OHM 1/  
16W 1% (0603)  
R1, 8  
Panasonic  
NOT INSTALLED  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
ERJ-3EKF42R2V  
R2, 11, 34-35, 40-41, 46-47, 52-53, 58-  
59, 64-65, 70-71, 76-77, 82-83, 88-89  
R3, 30-33, 36-39, 42-45, 48-51, 54-57,  
RES 4.75K 1/16W  
60-63, 66-69, 72-75, 78-81, 84-87, 1266 1% (0603)  
ERJ-3EKF4751V  
ERJ-3EKF1002V  
ERJ-3EKF49R9V  
ERJ-3EKF2210V  
ERJ-3GEY0R00V  
R4-7, 13-14, 220, 236-237, 360, 377,  
379-389, 1139, 1141, 1271, 1273  
RES 10K 1/16W  
1% (0603)  
R9, 116, 222-224, 226-230, 238, 240,  
243, 245, 358, 378, 390  
RES 49.9 OHM 1/  
16W 1% (0603)  
RES 221 OHM 1/  
16W 1% (0603)  
R15  
RES 0 OHM 1/16W  
5% (0603) SMD  
R16, 150-152, 1267, 1269, 1277  
RES 84.5 OHM 1/  
16W 1% (0603)  
SMD  
R156-185  
Panasonic  
ERJ-3EKF84R5V  
RES 1.00K 1/16W  
1% (0603)  
R216-219, 1264, 1265  
R361-368  
Panasonic  
Panasonic  
ERJ-3EKF1001V  
ERJ-3EKF22R1V  
RES 22.1 OHM 1/  
16W 1% (0603)  
SWITCH SPST  
S1  
MOM KEY J-LEAD C&K Components  
SMD  
KT11P2JM  
TP1  
HEADER 1X1  
Berg  
68000-240-1  
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®
Table 12. Intel IXD1110 Demo Board Bill of Materials (Rev. A1) (Continued)  
Reference Designator  
Description  
Manufacturer1  
Part Number  
TESTPOINT  
SILVER LOOP  
(SMD)  
Components Corp.  
(Lab stock-reel)  
TP2-17, 19-21  
TP-108-02  
IC MAC IXF1110 10  
PORT  
U1  
U3  
U4  
Intel  
IXF1110  
OSC 125 MHZ 3.3V  
4 PIN SMD  
Pletronics  
Pletronics  
SM7744DSV-125.0M  
SM7744HSV-50.0M  
OSC 50.0 MHZ  
3.3V 4 PIN SMD  
IC LOGIC 74HC05  
U5  
U8  
HEX INVERTER W/ Texas Instruments  
OD 14 PIN SOP  
SN74HC05D  
IC FPGA  
Altera  
EP1K30TC144-1  
EP1K30TC144-1  
IC LOGIC  
74HC595 8 BIT  
SHIFT REGISTER  
16 PIN SOIC  
Fairchild  
Semiconductor  
U10-13  
MM74HC595M  
SOCKET 8 PIN DIP MILL--Max  
SOCKET FOR U18  
U18  
110-93-308-41-001  
EPC1PC8  
GOLD  
Manufacturing Corp  
IC MEM PROM  
EPC1PC8 ALTERA Altera  
8 PIN DIP (DIP8)  
CONN 38 PIN  
U19-21  
MICTOR PLUG  
AMP  
2-767004-2  
CONNECTOR ( )  
MISC LATCH  
HOUSING FOR  
MICTOR RECPT  
Precision  
Interconnect  
LATCH HOUSING FOR U19-21  
105-1089-00  
IC LOGIC  
NC7SZ125  
SINGLE TRISTATE Semiconductor  
BUFFER SOT23  
Fairchild  
U22  
U23  
NC7SZ125M5  
SN74LV08AD  
IC LOGIC 74LV08  
QUAD 2-INPUT  
Texas Instruments  
AND GATE 14 SOP  
1. Third-party brands and names are the property of their respective owners.  
40  
Development Kit Manual  
Document Number: 250807  
Revision Number: 003  
Revision Date: June 27, 2003  
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