IBM Network Card PD78081 User Manual

µPD78083 SUBSERIES

8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78081 µPD78081(A)

µPD78082 µPD78082(A)

µPD78P083 µPD78P083(A)

µPD78P081(A2)

Document No. U12176EJ2V0UM00 (2nd edition)

(O. D. No. IEU-886)

Date Published May 1997 N

Printed in Japan

1994

1992

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FIP, IEBus, and QTOP are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.

HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Sun OS is a trademark of Sun Microsystems, Inc.

Ethernet is a trademark of XEROX Corporation.

NEWS and NEWS-OS are trademarks of SONY Corporation.

OSF/Motif is a trademark of Open Software Foundation, Inc.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from a

country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

License not needed: µPD78P083DU

The customer must judge the need for license:

µPD78081CU-×××, 78081GB-×××-3B4, 78081GB-×××-3BS-MTX

µPD78081GB(A)-×××-3B4, 78081GB(A2)-×××-3B4

µPD78082CU-×××, 78082GB-×××-3B4, 78082GB-×××-3BS-MTX

µPD78082GB(A)-×××-3B4

µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX

µPD78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX

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The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated “quality assurance program“ for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M7 96.5

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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 800-729-9288

Fax: 2886-9022/9044

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 0211-65 03 490

Fax: 01-30-67 58 99

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Fax: 01908-670-290

Fax: 250-3583

Tel: 01-504-2787

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Fax: 02-66 75 42 99

Fax: 02-719-5951

Tel: 08-63 80 820

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

Fax: 08-63 80 388

J96. 8

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Major Revision in This Edition

Page

Description

Throughout

The following products have been already developed

µPD78081CU-×××, 78081GB-×××-3B4, 78082CU-×××, 78082GB-×××-3B4, 78P083CU, 78P083DU,

78P083GB-3B4

The following products have been added

µPD78081GB-×××-3BS-MTX, 78082GB-×××-3BS-MTX, 78P083GB-3BS-MTX, 78081GB(A)-×××-3B4,

78082GB(A)-×××-3B4, 78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX, 78081GB(A2)-×××-3B4

Changes supply voltage to VDD = 1.8 to 5.5V.

p. 9

1.6 78K/0 Series Development has been changed.

p. 13

1.9 Differences between the µPD78081, 78082, and 78P083, the µPD78081(A), 78082(A), and

78P083(A), and the µPD78081(A2) has been added.

p. 19

p. 72

Cautions regarding the use of functions in common with 2.2.5 (2) (d) ASCK has been added.

Cautions concerning the Write to OSMS Command has been added to 5.3 (2) Oscillation mode select

p. 73

Cautions concerning external clock input in 5.4.1 Main system clock oscillator has been changed.

Figure 7-3. Watchdog Timer Mode Register Format, notes and cautions have been added.

Description of 7.4.2 Interval timer operation has been changed.

p. 108

p. 110

p. 113

Cautions with regard to rewriting TCL0 to other than same data has been added to 8.3 (1) Timer clock

select register 0 (TCL0).

p. 120

The HSC bit has been added to the A/D Converter Mode

p. 122, 193

p. 137

10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby function, and Cautions have been added.

Figure 11-1. Serial Interface Channel 2 Block Diagram has been corrected.

p. 146, 155

11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/receive clock by means of main system

clock have been added.

76800 bps has been added to baud rate generated from the main system clock.

p. 161

p. 165

p. 168

p. 206

p. 205

Figure 11-10. Receive Error Timing has been corrected.

11.4.3 (1) (c) Baud rate generator control register (BRGC) has been added.

11.4.3 (3) MSB/LSB switching as start bit has been added.

15.1 Memory Size Switching Register has been changed from W to R/W.

Items and cautions have been added to Table 15-1. Differences between the µPD78P083 and Mask ROM

Versions.

p. 214

A description of the QTOP microcontroller has been added to 15.5 Screening of One-Time PROM

Versions.

p. 232

p. 231

Figure A-1. Development Tool Configuration has been changed.

APPENDIX A DEVELOPMENT TOOLS

The following Development Tools have been added:

IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0

p. 239

p. 240

p. 244

p. 249

A.4 OS for IBM PC has been added.

Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added.

B.1 Real-time OS has been added.

APPENDIX D REVISION HISTORY has been added.

The mark

shows major revised points.

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PREFACE

Readers

This manual has been prepared for user engineers who want to understand the

functions of the µPD78083 subseries and design and develop its application

systems and programs.

Caution

In the µPD78083 Subseries, the µPD78P083DU is not designed to maintain the

reliability required for use in customers’ mass-produced equipment.

Please use this device only for experimentation or for evaluation of functions.

Purpose

This manual is intended for users to understand the functions described in the

Organization below.

Organization

The µPD78083 subseries manual is separated into two parts: this manual and the

instruction edition (common to the 78K/0 Series).

µPD78083 Subseries

User’s Manual

78K/0 Series

User’s Manual

Instruction

(This Manual)

Pin functions

CPU functions

Internal block functions

Interrupt

Instruction set

Explanation of each instruction

Other on-chip peripheral functions

How to Read This Manual

Before reading this manual, you should have general knowledge of electric and logic

circuits and microcontrollers.

For those who will be using this as a manual for the µPD78081(A), 78082(A),

78P083(A) and 78081(A2):

→ The µPD78081, 78082, 78P083 are explained as being representative de-

vices.

In case this is used as a manual for the µPD78081(A), 78082(A), 78P083(A),

or 78081(A2), please reread the product names as follows.

µPD78081 → µPD78081(A) or µPD78081(A2)

µPD78082 → µPD78082(A)

µPD78P083 → µPD78P083(A)

When you want to understand the functions in general:

→ Read this manual in the order of the contents.

To know the µPD78083 Subseries instruction function in detail:

→ Refer to the 78K/0 Series User's Manual: Instructions (IEU-1372)

How to interpret the register format:

→

For the circled bit number, the bit name is defined as a reserved word in

RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.

To learn the function of a register whose register name is known:

→ Refer to Appendix C Register Index.

To know the electrical specifications of the µPD78083 Subseries:

→ Refer to separately available Data Sheet.

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ToknowapplicationexamplesofthefunctionsprovidedintheµPD78083Subseries:

→ Refer to Application Note separately provided.

Legend

Data representation weight

Active low representations

Note

High digits on the left and low digits on the right

××× (line over the pin and signal names)

Description of note in the text.

Information requiring particular attention

Additional explanatory material

Binary ... ×××× or ××××B

Caution

Remarks

Numeral representations

Decimal ... ××××

Hexadecimal ... ××××H

Examples of use in this manual are prepared for “Standard” quality level devices for general electronic

equipment. In the case of examples of use in this manual for devices which meet “Special” quality level

requirements, please use each device only after studying each part that is actuall to be used, the circuitry

and the quality level of each component before use.

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Other Documents

Document No.

Document name

Japanese

C10943X

English

IC PACKAGE MANUAL

Semiconductor Device Mounting Technology Manual

Quality Grade on NEC Semiconductor Devices

Reliability Quality Control on NEC Semiconductor Devices

Electric Static Discharge (ESD) Test

C10535J

C11531J

C10983J

MEM-539

C11893J

U11416J

C10535E

C11531E

C10983E

—

Semiconductor Devices Quality Assurance Guide

Microcontroller Related Product Guide—Third Party Manufacturers

C11893E

—

Caution: The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

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CONTENTS

CHAPTER 1 OUTLINE.....................................................................................................................

1.1 Features .............................................................................................................................

1.2 Applications ......................................................................................................................

1.3 Ordering Information ........................................................................................................

1.4 Quality Grade ....................................................................................................................

1.5 Pin Configuration (Top View) ...........................................................................................

1.6 78K/0 Series Development ...............................................................................................

1.7 Block Diagram...................................................................................................................

1.8 Outline of Function ...........................................................................................................

1.9 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A)

and 78P083(A), and the µPD78081(A2) ...........................................................................

CHAPTER 2 PIN FUNCTION ...........................................................................................................

2.1 Pin Function List ...............................................................................................................

2.1.1

2.1.2

Normal operating mode pins ...............................................................................................

PROM programming mode pins (µPD78P083 only)............................................................

2.2 Description of Pin Functions ...........................................................................................

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

P00 to P03 (Port 0) ..............................................................................................................

P10 to P17 (Port 1) ..............................................................................................................

P30 to P37 (Port 3) ..............................................................................................................

P50 to P57 (Port 5) ..............................................................................................................

P70 to P72 (Port 7) ..............................................................................................................

P100 to P101 (Port 10) ........................................................................................................

AV^REF..................................................................................................................................

AV^DD....................................................................................................................................

AV^SS....................................................................................................................................

2.2.10 RESET .................................................................................................................................

2.2.11 X1 and X2 ............................................................................................................................

2.2.12 V^DD......................................................................................................................................

2.2.13 V^SS......................................................................................................................................

2.2.14 V^PP(µPD78P083 only) .........................................................................................................

2.2.15 IC (Mask ROM version only)................................................................................................

2.2.16 NC (44-pin plastic QFP versions only).................................................................................

2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ...............

CHAPTER 3 CPU ARCHITECTURE................................................................................................

3.1 Memory Spaces.................................................................................................................

3.1.1

3.1.2

3.1.3

3.1.4

Internal program memory space..........................................................................................

Internal data memory space ................................................................................................

Special Function Register (SFR) area .................................................................................

Data memory addressing ....................................................................................................

3.2 Processor Registers .........................................................................................................

3.2.1

3.2.2

Control registers ..................................................................................................................

General registers .................................................................................................................

– i –

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3.2.3

Special Function Register (SFR) .........................................................................................

3.3 Instruction Address Addressing .....................................................................................

3.3.1

3.3.2

3.3.3

3.3.4

Relative Addressing .............................................................................................................

Immediate addressing .........................................................................................................

Table indirect addressing .....................................................................................................

Register addressing.............................................................................................................

3.4 Operand Address Addressing .........................................................................................

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

3.4.9

Implied addressing ..............................................................................................................

Register addressing.............................................................................................................

Direct addressing.................................................................................................................

Short direct addressing........................................................................................................

Special-Function Register (SFR) addressing ......................................................................

Register indirect addressing ................................................................................................

Based addressing ................................................................................................................

Based indexed addressing ..................................................................................................

Stack addressing .................................................................................................................

CHAPTER 4 PORT FUNCTIONS ....................................................................................................

4.1 Port Functions...................................................................................................................

4.2 Port Configuration ............................................................................................................

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

Port 0 ...................................................................................................................................

Port 1 ...................................................................................................................................

Port 3 ...................................................................................................................................

Port 5 ...................................................................................................................................

Port 7 ...................................................................................................................................

Port 10 .................................................................................................................................

4.3 Port Function Control Registers .....................................................................................

4.4 Port Function Operations.................................................................................................

4.4.1

4.4.2

4.4.3

Writing to input/output port...................................................................................................

Reading from input/output port ............................................................................................

Operations on input/output port ...........................................................................................

CHAPTER 5 CLOCK GENERATOR ................................................................................................

5.1 Clock Generator Functions..............................................................................................

5.2 Clock Generator Configuration .......................................................................................

5.3 Clock Generator Control Register...................................................................................

5.4 System Clock Oscillator...................................................................................................

5.4.1

5.4.2

Main system clock oscillator ................................................................................................

Scaler...................................................................................................................................

5.5 Clock Generator Operations ............................................................................................

5.6 Changing CPU Clock Settings .........................................................................................

5.6.1

5.6.2

Time required for CPU clock switchover..............................................................................

CPU clock switching procedure ...........................................................................................

CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 ..............................................................

6.1 8-Bit Timer/Event Counters 5 and 6 Functions ..............................................................

6.2 8-Bit Timer/Event Counters 5 and 6 Configurations......................................................

6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers .................................................

– ii –

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6.4 8-Bit Timer/Event Counters 5 and 6 Operations ............................................................

6.4.1

6.4.2

6.4.3

6.4.4

Interval timer operations ......................................................................................................

External event counter operation.........................................................................................

Square-wave output ............................................................................................................

PWM output operations .......................................................................................................

6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 ..........................................................

100

CHAPTER 7 WATCHDOG TIMER ...................................................................................................

7.1 Watchdog Timer Functions ..............................................................................................

7.2 Watchdog Timer Configuration .......................................................................................

7.3 Watchdog Timer Control Registers .................................................................................

7.4 Watchdog Timer Operations ............................................................................................

103

105

106

109

110

7.4.1

7.4.2

Watchdog timer operation....................................................................................................

Interval timer operation ........................................................................................................

CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT .....................................................................

8.1 Clock Output Control Circuit Functions .........................................................................

8.2 Clock Output Control Circuit Configuration...................................................................

8.3 Clock Output Function Control Registers ......................................................................

111

112

113

CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................

9.1 Buzzer Output Control Circuit Functions .......................................................................

9.2 Buzzer Output Control Circuit Configuration.................................................................

9.3 Buzzer Output Function Control Registers ....................................................................

115

116

CHAPTER 10 A/D CONVERTER.......................................................................................................

10.1 A/D Converter Functions..................................................................................................

10.2 A/D Converter Configuration ...........................................................................................

10.3 A/D Converter Control Registers.....................................................................................

10.4 A/D Converter Operations ................................................................................................

10.4.1 Basic operations of A/D converter .......................................................................................

10.4.2 Input voltage and conversion results ...................................................................................

10.4.3 A/D converter operating mode.............................................................................................

10.5 A/D Converter Cautions ...................................................................................................

119

122

126

128

129

131

CHAPTER 11 SERIAL INTERFACE CHANNEL 2 ............................................................................

11.1 Serial Interface Channel 2 Functions ..............................................................................

11.2 Serial Interface Channel 2 Configuration .......................................................................

11.3 Serial Interface Channel 2 Control Registers.................................................................

11.4 Serial Interface Channel 2 Operation ..............................................................................

11.4.1 Operation stop mode ...........................................................................................................

11.4.2 Asynchronous serial interface (UART) mode ......................................................................

11.4.3 3-wire serial I/O mode .........................................................................................................

135

136

140

148

150

163

CHAPTER 12 INTERRUPT FUNCTION ............................................................................................

12.1 Interrupt Function Types ..................................................................................................

12.2 Interrupt Sources and Configuration ..............................................................................

12.3 Interrupt Function Control Registers ..............................................................................

171

172

175

– iii –

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12.4 Interrupt Servicing Operations ........................................................................................

12.4.1 Non-maskable interrupt request acknowledge operation ....................................................

12.4.2 Maskable interrupt request acknowledge operation ............................................................

12.4.3 Software interrupt request acknowledge operation .............................................................

12.4.4 Multiple interrupt servicing ...................................................................................................

12.4.5 Interrupt request reserve .....................................................................................................

181

184

187

191

CHAPTER 13 STANDBY FUNCTION................................................................................................

13.1 Standby Function and Configuration..............................................................................

13.1.1 Standby function ..................................................................................................................

13.1.2 Standby function control register .........................................................................................

13.2 Standby Function Operations..........................................................................................

13.2.1 HALT mode ..........................................................................................................................

13.2.2 STOP mode .........................................................................................................................

193

194

195

198

CHAPTER 14 RESET FUNCTION .....................................................................................................

14.1 Reset Function ..................................................................................................................

201

CHAPTER 15 µPD78P083 .................................................................................................................

15.1 Memory Size Switching Register.....................................................................................

15.2 PROM Programming .........................................................................................................

15.2.1 Operating modes .................................................................................................................

15.2.2 PROM write procedure ........................................................................................................

15.2.3 PROM reading procedure....................................................................................................

15.3 Erasure Procedure (µPD78P083DU Only).......................................................................

15.4 Opaque Film Masking the Window (µPD78P083DU Only).............................................

15.5 Screening of One-Time PROM Versions .........................................................................

205

206

207

209

213

214

CHAPTER 16 INSTRUCTION SET ....................................................................................................

16.1 Legends Used in Operation List......................................................................................

16.1.1 Operand identifiers and description methods ......................................................................

16.1.2 Description of “operation” column........................................................................................

16.1.3 Description of “flag operation” column .................................................................................

16.2 Operation List....................................................................................................................

16.3 Instructions Listed by Addressing Type .........................................................................

215

216

217

218

226

APPENDIX A DEVELOPMENT TOOLS............................................................................................

A.1 Language Processing Software ......................................................................................

A.2 PROM Programming Tools ..............................................................................................

231

233

234

A.2.1

A.2.2

Hardware .............................................................................................................................

Software...............................................................................................................................

A.3 Debugging Tools ............................................................................................................... 235

A.3.1

A.3.2

Hardware .............................................................................................................................

Software (1/3) ......................................................................................................................

Software (2/3) ......................................................................................................................

Software (3/3) ......................................................................................................................

235

236

237

238

239

A.4 OS for IBM PC ...................................................................................................................

– iv –

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A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series

In-Circuit Emulator............................................................................................................

APPENDIX B EMBEDDED SOFTWARE ..........................................................................................

240

243

B.1 Real-time OS...................................................................................................................... 244

B.2 Fuzzy Inference Development Support System............................................................. 245

APPENDIX C REGISTER INDEX ...................................................................................................... 247

C.1 Register Index .....................................................................................................................

247

APPENDIX D REVISION HISTORY ..................................................................................................

249

– v –

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FIGURE (1/4)

Fig. No.

2-1

Title

Page

Pin Input/Output Circuit of List............................................................................................

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

3-11

3-12

Memory Map (µPD78081) ..................................................................................................

Memory Map (µPD78082) ..................................................................................................

Memory Map (µPD78P083)................................................................................................

Data Memory Addressing (µPD78081)...............................................................................

Data Memory Addressing (µPD78082)...............................................................................

Data Memory Addressing (µPD78P083) ............................................................................

Program Counter Configuration .........................................................................................

Program Status Word Configuration...................................................................................

Stack Pointer Configuration................................................................................................

Data to be Saved to Stack Memory....................................................................................

Data to be Reset from Stack Memory ................................................................................

General Register Configuration ..........................................................................................

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

Port Types ..........................................................................................................................

P00 Block Diagram.............................................................................................................

P01 to P03 Block Diagram .................................................................................................

P10 to P17 Block Diagram .................................................................................................

P30 to P37 Block Diagram .................................................................................................

P50 to P57 Block Diagram .................................................................................................

P70 Block Diagram.............................................................................................................

P71 and P72 Block Diagram ..............................................................................................

P100 to P101 Block Diagram .............................................................................................

Port Mode Register Format ................................................................................................

Pull-Up Resistor Option Register Format ...........................................................................

5-1

5-2

5-3

5-4

5-5

5-6

5-7

Block Diagram of Clock Generator .....................................................................................

Processor Clock Control Register Format ..........................................................................

Oscillation Mode Selection Register Format ......................................................................

Main System Clock Waveform due to Writing to OSMS.....................................................

External Circuit of Main System Clock Oscillator ...............................................................

Examples of Oscillator with Bad Connection (1/2) .............................................................

CPU Clock Switching .........................................................................................................

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

8-Bit Timer/Event Counters 5 and 6 Block Diagram ...........................................................

Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ...................

Timer Clock Select Register 5 Format................................................................................

Timer Clock Select Register 6 Format................................................................................

8-Bit Timer Mode Control Register 5 Format......................................................................

8-Bit Timer Mode Control Register 6 Format......................................................................

Port Mode Register 10 Format ...........................................................................................

8-Bit Timer Mode Control Register Settings for Interval Timer Operation ..........................

Interval Timer Operation Timings .......................................................................................

– vi –

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FIGURE (2/4)

Fig. No.

Title

Page

6-10

6-11

6-12

6-13

6-14

6-15

6-16

6-17

6-18

6-19

6-20

8-Bit Timer Mode Control Register Setting for External Event Counter Operation.............

External Event Counter Operation Timings (with Rising Edge Specification) ....................

8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..............

8-Bit Timer Mode Control Register Settings for PWM Output Operation ...........................

PWM Output Operation Timing (Active high setting) ..........................................................

PWM Output Operation Timings (CRn0 = 00H, active high setting)...................................

PWM Output Operation Timings (CRn0 = FFH, active high setting) ..................................

PWM Output Operation Timings (CRn0 changing, active high setting)..............................

8-Bit Timer Registers 5 and 6 Start Timing .........................................................................

External Event Counter Operation Timing ..........................................................................

Timing after Compare Register Change during Timer Count Operation ............................

100

101

7-1

7-2

7-3

Watchdog Timer Block Diagram .........................................................................................

Timer Clock Select Register 2 Format................................................................................

Watchdog Timer Mode Register Format.............................................................................

105

107

108

8-1

8-2

8-3

8-4

Remote Controlled Output Application Example ................................................................

Clock Output Control Circuit Block Diagram.......................................................................

Timer Clock Select Register 0 Format................................................................................

Port Mode Register 3 Format .............................................................................................

111

112

113

114

9-1

9-2

9-3

Buzzer Output Control Circuit Block Diagram ....................................................................

Timer Clock Select Register 2 Format................................................................................

Port Mode Register 3 Format .............................................................................................

115

117

118

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

A/D Converter Block Diagram ............................................................................................

A/D Converter Mode Register Format ................................................................................

A/D Converter Input Select Register Format ......................................................................

External Interrupt Mode Register 1 Format ........................................................................

A/D Converter Basic Operation ..........................................................................................

Relations between Analog Input Voltage and A/D Conversion Result................................

A/D Conversion by Hardware Start ....................................................................................

A/D Conversion by Software Start......................................................................................

Example of Method of Reducing Current Dissipation in Standby Mode.............................

Analog Input Pin Disposition ..............................................................................................

A/D Conversion End Interrupt Request Generation ...........................................................

Handling of AVDD Pin.........................................................................................................

120

123

124

125

127

128

129

130

131

132

133

11-1

11-2

11-3

11-4

11-5

11-6

Serial Interface Channel 2 Block Diagram .........................................................................

Baud Rate Generator Block Diagram .................................................................................

Serial Operating Mode Register 2 Format..........................................................................

Asynchronous Serial Interface Mode Register Format.......................................................

Asynchronous Serial Interface Status Register Format .....................................................

Baud Rate Generator Control Register Format (1/2) .........................................................

137

138

140

141

143

144

– vii –

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FIGURE (3/4)

Fig. No.

Title

Page

145

11-6

11-7

11-8

11-9

11-10

11-11

Baud Rate Generator Control Register Format (2/2) .........................................................

Asynchronous Serial Interface Transmit/Receive Data Format..........................................

Asynchronous Serial Interface Transmission Completion Interrupt Request Timing ..........

Asynchronous Serial Interface Reception Completion Interrupt Request Timing ...............

Receive Error Timing ..........................................................................................................

State of the Receive Buffer Register (RXB) when Reception is Interrupted, and

157

159

160

161

Generation/Non Generation of an Interrupt Request (INTSR) ...........................................

3-Wire serial I/O Mode Timing ............................................................................................

Circuit of Switching in Transfer Bit Order ...........................................................................

162

168

169

11-12

11-13

12-1

Basic Configuration of Interrupt Function (1/2)...................................................................

Basic Configuration of Interrupt Function (2/2)...................................................................

Interrupt Request Flag Register Format .............................................................................

Interrupt Mask Flag Register Format..................................................................................

Priority Specify Flag Register Format.................................................................................

External Interrupt Mode Register 0 Format ........................................................................

External Interrupt Mode Register 1 Format ........................................................................

Program Status Word Configuration...................................................................................

Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment............

Non-Maskable Interrupt Request Acknowledge Timing ......................................................

Non-Maskable Interrupt Request Acknowledge Operation ................................................

Interrupt Request Acknowledge Processing Algorithm.......................................................

Interrupt Request Acknowledge Timing (Minimum Time) ...................................................

Interrupt Request Acknowledge Timing (Maximum Time) ..................................................

Example of Multiple Interrupt (1/2) .....................................................................................

Example of Multiple Interrupt (2/2) .....................................................................................

Interrupt Request Hold .......................................................................................................

173

174

176

177

178

179

180

182

183

185

186

189

190

192

12-1

12-2

12-3

12-4

12-5

12-6

12-7

12-8

12-9

12-10

12-11

12-12

12-13

12-14

12-15

13-1

13-2

13-3

13-4

13-5

Oscillation Stabilization Time Select Register Format ........................................................

HALT Mode Clear upon Interrupt Generation .....................................................................

HALT Mode Release by RESET Input................................................................................

STOP Mode Release by Interrupt Generation....................................................................

Release by STOP Mode RESET Input ...............................................................................

194

196

197

199

200

14-1

14-2

14-3

14-4

Block Diagram of Reset Function .......................................................................................

Timing of Reset Input by RESET Input...............................................................................

Timing of Reset due to Watchdog Timer Overflow .............................................................

Timing of Reset Input in STOP Mode by RESET Input ......................................................

201

202

15-1

15-2

15-3

15-4

15-5

Memory Size Switching Register Format ...........................................................................

Page Program Mode Flowchart..........................................................................................

Page Program Mode Timing ...............................................................................................

Byte Program Mode Flowchart ...........................................................................................

Byte Program Mode Timing ................................................................................................

206

209

210

211

212

– viii –

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FIGURE (4/4)

Fig. No.

15-6

Title

Page

213

PROM Read Timing ...........................................................................................................

A-1

A-2

A-3

Development Tool Configuration ........................................................................................

EV-9200G-44 Drawing (For Reference Only).....................................................................

EV-9200G-44 Footprint (For Reference Only)....................................................................

232

241

242

– ix –

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TABLE (1/2)

Table. No.

1-1

Title

Page

Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A)

and 78P083(A), and the µPD78081(A2) ............................................................................

2-1

Type of Input/Output Circuit of Each Pin ............................................................................

3-1

3-2

Vector Table........................................................................................................................

Special-Function Register List (1/2) ..................................................................................

Special-Function Register List (2/2) ...................................................................................

4-1

4-2

4-3

Port Functions ....................................................................................................................

Port Configuration ..............................................................................................................

Port Mode Register and Output Latch Settings when Using Dual-Fucntions .....................

5-1

5-2

Clock Generator Configuration ...........................................................................................

Maximum Time Required for CPU Clock Switchover .........................................................

6-1

6-2

6-3

6-4

6-5

6-6

Timer/Event Counter Types and Functions ........................................................................

8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................

8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................

8-Bit Timer/Event Counters 5 and 6 Configurations ...........................................................

8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................

8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................

7-1

7-2

7-3

7-4

7-5

Watchdog Timer Overrun Detection Times .........................................................................

Interval Times .....................................................................................................................

Watchdog Timer Configuration ...........................................................................................

Watchdog Timer Overrun Detection Time ..........................................................................

Interval Timer Interval Time ................................................................................................

103

104

105

109

110

8-1

Clock Output Control Circuit Configuration ........................................................................

Buzzer Output Control Circuit Configuration ......................................................................

A/D Converter Configuration ..............................................................................................

112

115

119

9-1

10-1

11-1

11-2

11-3

11-4

11-5

11-6

11-7

Serial Interface Channel 2 Configuration ...........................................................................

Serial Interface Channel 2 Operating Mode Settings .........................................................

Relation between Main System Clock and Baud Rate .......................................................

Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

Relation between Main System Clock and Baud Rate .......................................................

Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

Receive Error Causes ........................................................................................................

136

142

146

147

155

156

161

– x –

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TABLE (2/2)

Table. No.

Title

Page

172

12-1

12-2

12-3

12-4

Interrupt Source List ...........................................................................................................

Various Flags Corresponding to Interrupt Request Sources ..............................................

Times from Maskable Interrupt Request Generation to Interrupt Service ..........................

Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing .......................

175

184

188

13-1

13-2

13-3

13-4

HALT Mode Operating Status.............................................................................................

Operation after HALT Mode Release .................................................................................

STOP Mode Operating Status ............................................................................................

Operation after STOP Mode Release.................................................................................

195

197

198

200

14-1

Hardware Status after Reset (1/2)......................................................................................

Hardware Status after Reset (2/2)......................................................................................

203

204

15-1

15-2

15-3

Differences between the µPD78P083 and Mask ROM Versions .......................................

Examples of Memory Size Switching Register Settings .....................................................

PROM Programming Operating Modes .............................................................................

205

206

207

16-1

Operand Identifiers and Description Methods ....................................................................

216

A-1

A-2

System-Up Method from Other In-Circuit Emulator to IE-78000-R ....................................

System-Up Method from Other In-Circuit Emulator to IE-78000-R-A.................................

240

– xi –

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[MEMO]

– xii –

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CHAPTER 1 OUTLINE

1.1 Features

On-chip ROM and RAM

Type

Part Number

Data Memory

Program Memory

(ROM)

(Internal High-Speed RAM)

µPD78081

µPD78082

µPD78P083

8 Kbytes

256 bytes

384 bytes

16 Kbytes

24 Kbytes (Note)

512 bytes (Note)

Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory

size switching register (IMS).

Instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation) to low

speed (12.8 µs: In main system clock 5.0 MHz operation)

Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions

33 I/O ports

8-bit resolution A/D converter: 8 channels

Serial interface: 1 channel

• 3-wire serial I/O/UART mode: 1 channel

Timer: 3 channels

• 8-bit timer/event counter : 2 channels

• Watchdog timer : 1 channel

Vectored Interrupt Source : 13

Supply voltage: VDD = 1.8 to 5.5 V

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CHAPTER 1 OUTLINE

1.2 Applications

µPD78081, 78082, 78P083:

Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc.

µPD78081(A), 78082(A), 78P083(A), 78081(A2):

Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc.

1.3 Ordering Information

Part number

Package

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

42-pin ceramic shrink DIP (with window) (600 mil)

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 × 10 mm)

Internal ROM

Mask ROM

µPD78081CU-×××

µPD78081GB-×××-3B4

µPD78081GB-×××-3BS-MTX

µPD78082CU-×××

Mask ROM

µPD78082GB-×××-3B4

µPD78082GB-×××-3BS-MTX

µPD78P083CU

Mask ROM

One-Time PROM

EPROM

µPD78P083DU

µPD78P083GB-3B4

One-Time PROM

Mask ROM

µPD78P083GB-3BS-MTX

µPD78081GB(A)-×××-3B4

µPD78082GB(A)-×××-3B4

µPD78P083CU(A)

Mask ROM

One-Time PROM

Mask ROM

µPD78P083GB(A)-3B4

µPD78P083GB(A)-3BS-MTX

µPD78081GB(A2)-×××-3B4

Note

Note Under development

Remark ××× indicates ROM code suffix.

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CHAPTER 1 OUTLINE

1.4 Quality Grade

Part number

Package

Quality grade

µPD78081CU-×××

42-pin plastic shrink DIP (600 mil)

Standard

µPD78081GB-×××-3B4

µPD78081GB-×××-3BS-MTX

µPD78082CU-×××

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

42-pin ceramic shrink DIP (with window) (600 mil)

Standard

µPD78082GB-×××-3B4

µPD78082GB-×××-3BS-MTX

µPD78P083CU

Standard

µPD78P083DU

Not applicable

µPD78P083GB-3B4

44-pin plastic QFP (10 × 10 mm)

Standard

µPD78P083GB-3BS-MTX

µPD78081GB(A)-×××-3B4

µPD78082GB(A)-×××-3B4

µPD78P083CU(A)

44-pin plastic QFP (10 × 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 × 10 mm)

Special

µPD78P083GB(A)-3B4

µPD78P083GB(A)-3BS-MTX

µPD78081GB(A)-×××-3B4

Note

Note Under planning

Remark ××× indicates ROM code suffix.

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

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CHAPTER 1 OUTLINE

1.5 Pin Configuration (Top View)

(1) Normal operating mode

42-pin plastic shrink DIP (600 mil)

µPD78081CU-×××, 78082CU-×××, 78P083CU, 78P083CU(A)

42-pin ceramic shrink DIP (with window) (600 mil)

µPD78P083DU

P55

P56

V^SS

P54

P57

P53

P30

P52

P31

P51

P32

P50

P33

P100/TI5/TO5

P101/TI6/TO6

P70/R^XD/SI2

P71/T^XD/SO2

P72/ASCK/SCK2

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

AV^SS

P34

P35/PCL

P36/BUZ

P37

P00

P01/INTP1

P02/INTP2

P03/INTP3

RESET

IC (V^PP)

V^DD

AVDD

AVREF

Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.

2. Connect AV^DDpin to VDD.

3. Connect AV^SSpin to VSS.

Remark Pin connection in parentheses is intended for the µPD78P083.

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CHAPTER 1 OUTLINE

•

44-pin plastic QFP (10 × 10 mm)

µPD78081GB-×××-3B4, 78081GB-×××-3BS-MTX

µPD78082GB-×××-3B4, 78082GB-×××-3BS-MTX

µPD78P083GB-3B4, 78P083GB-3BS-MTX

µPD78081GB(A)-×××-3B4, 78082GB(A)-×××-3B4

Note

µPD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX

µPD78P081GB(A2)-×××-3B4

44 43 42 41 40 39 38 37 36 35 34

P12/ANI2

P13/ANI3

P03/INTP3

P02/INTP2

P01/INTP1

P00

P14/ANI4

P15/ANI5

P16/ANI6

P37

P17/ANI7

P36/BUZ

P35/PCL

P34

P72/ASCK/SCK2

P71/TxD/SO2

P70/RxD/SI2

P101/TI6/TO6

P100/TI5/TO6

P33

P32

12 13 14 15 16 17 18 19 20 21 22

Note Under development

Cautions 1. Be sure to connect IC (Internally Connected) pin to V^SSdirectly.

2. Connect AV^DDpin to VDD.

3. Connect AV^SSpin to VSS.

4. Connect NC pin to V^SSfor noise protection (It can be left open).

Remark Pin connection in parenthesis is intended for the µPD78P083.

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CHAPTER 1 OUTLINE

Pin Identifications

ANI0 to ANI7

ASCK

Analog Input

P100, P101

Port 10

Asynchronous Serial Clock

Analog Power Supply

Analog Reference Voltage

Analog Ground

Buzzer Clock

PCL

Programmable Clock

Reset

AV^DD

RESET

RxD

AV^REF

Receive Data

Serial Clock

AV^SS

SCK2

SI2

BUZ

Serial Input

Internally Connected

Interrupt from Peripherals

Non-connection

Port 0

SO2

Serial Output

Timer Input

INTP1 to INTP3

TI5, TI6

TO5 to TO6

TxD

Timer Output

Transmit Data

Power Supply

Programming Power Supply

Ground

P00 to P03

P10 to P17

P30 to P37

P50 to P57

P70 to P72

Port 1

V^DD

Port 3

V^PP

Port 5

V^SS

Port 7

X1, X2

Crystal (Main System Clock)

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CHAPTER 1 OUTLINE

(2) PROM programming mode

•

42-pin plastic shrink DIP (600 mil)

µPD78P083CU, 78P083CU(A)

42-pin ceramic shrink DIP (with window) (600 mil)

µPD78P083DU

V^SS

PGM

A10

A11

A12

A13

A14

(L)

RESET

V^PP

Open

(L)

V^DD

V^SS

VSS

VDD

Cautions 1. (L)

2. V^SS

: Individually connect to V^SSvia a pull-down resistor.

: Connect to the ground.

3. RESET: Set to the low level.

4. Open : Do not connect anything.

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CHAPTER 1 OUTLINE

•

44-pin plastic QFP (10 × 10 mm)

µPD78P083GB-3B4, 78P083GB-3BS-MTX

µPD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX

Note

44 43 42 41 40 39 38 37 36 35 34

(L)

A14

A13

A12

A11

A10

PGM

(L)

12 13 14 15 16 17 18 19 20 21 22

Note Under development

Cautions 1. (L)

2. V^SS

: Connect individually to V^SSvia a pull-down resistor.

: Connect to the ground.

3. RESET : Set to the low level.

4. Open : Do not connect anything.

A0 to A14

: Address Bus

: Chip Enable

: Data Bus

RESET

: Reset

V^DD

V^PP

V^SS

: Power Supply

: Programming Power Supply

: Ground

D0 to D7

: Output Enable

: Program

PGM

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CHAPTER 1 OUTLINE

1.6 78K/0 Series Development

The following shows the 78K/0 Series products development. Subseries names are shown inside frames.

Mass-produced products

Products under development

Y Subseries supports the I²C bus specifications.

Control

100-pin

80-pin

64-pin

42/44-pin

Low EMI noise version of the µPD78078

µPD78075B

µPD78078

µPD78070A

µPD78075BY

µPD78078Y

µPD78070AY

Timer is added to the µPD78054 and its external interface is enhanced.

ROM-less versions of the µPD78078

µPD780018^NoteµPD780018Y^Note

Serial I/O of the µPD78078 is enhanced and only selected functions are provided.

Serial I/O-enhanced versions of the µPD78054; Low EMI noise version

Low EMI noise version of the µPD78054

µPD780058

µPD78058F

µPD78054

µPD780034

µPD780024

µPD78014H

µPD78018F

µPD78014

µPD780001

µPD78002

µPD78083

µPD780058Y^Note

µPD78058FY

µPD78054Y

UART and D/A converter are added to the µPD78014 and I/O is enhanced

A/D-enhanced version of the µPD780024

µPD780034Y

µPD780024Y

Serial I/O-enhanced versions of the µPD78018F; Low EMI noise version

Low EMI noise version of the µPD78018F

Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities available.

A/D converter and 16-bit timer are added to the µPD78002.

A/D converter is added to the µPD78002.

µPD78018FY

µPD78014Y

Basic subseries for control applications

µPD78002Y

On-chip UART, and operable at low voltage (1.8 V).

Inverter control

64-pin

A/D-enhanced version of the µPD780924

µPD780964

µPD780924

On-chip inverter control circuit and UART incorporated; Low EMI noise version

FIP® driving

100-pin

80-pin

µPD780208

µPD780228

µPD78044H

µPD78044F

I/O and FIP C/D of the µPD78044F are enhanced. Total display outputs : 53 pins

I/O and FIP C/D of the µPD78044H are enhanced. Total display outputs : 48 pins

N-ch open-drain I/O is added to the µPD78044F. Total display outputs : 34 pins

Basic subseries for FIP driving. Total display outputs: 34 pins

78K/0

series

80-pin

LCD driving

100-pin

SIO of the µPD78064 is enhanced, and ROM and RAM are expanded.

Low EMI noise version of the µPD78064

µPD780308

µPD78064B

µPD78064

µPD780308Y

µPD78064Y

Basic subseries for driving LCDs and with on-chip UART.

IEBus^TMsupported

80-pin

64-pin

µPD78098

IEBus controller is added to the µPD78054.

PWM output, LV digital code decoder and Hsync counter are incorporated.

µPD78P0914

Note Under planning

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CHAPTER 1 OUTLINE

The following table shows the differences among subseries functions.

VDD

MIN.

value

Function

Subseries name

ROM

Timer

8-bit 10-bit 8-bit

External

Serial interface I/O

capacity

8-bit 16-bit Watch WDT A/D A/D D/A

expansion

Control

µPD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch

—

2 ch 3 ch (UART: 1 ch) 88

1.8 V Available

2.7 V

µPD78078

48K to 60K

—

µPD78070A

µPD780018 48K to 60K

µPD780058 24K to 60K 2 ch

µPD78058F 48K to 60K

—

2 ch (Time division 88

3-wire: 1 ch)

2 ch 3 ch (Time division 68

UART: 1 ch)

1.8 V

3 ch (UART: 1 ch) 69

2.7 V

2.0 V

1.8 V

µPD78054

16K to 60K

µPD780034 8K to 32K

µPD780024

—

8 ch

—

3 ch (UART: 1 ch, Time 51

division 3-wire: 1 ch)

8 ch

µPD78014H

2 ch

µPD78018F 8K to 60K

µPD78014

8K to 32K

2.7 V

µPD780001 8K

—

1 ch

—

1 ch

—

µPD78002

µPD78083

8K to 16K

—

8 ch

—

Available

1 ch (UART: 1 ch) 33

2 ch (UART: 2 ch) 47

1.8 V

2.7 V

—

Inverter

control

µPD780964 8K to 32K 3 ch Note

µPD780924

—

1 ch

8 ch

—

Available

8 ch

FIP driving µPD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch

µPD780228 48K to 60K 3 ch

—

2 ch

1 ch

2.7 V

4.5 V

2.7 V

—

µPD78044H 32K to 48K 2 ch 1 ch 1 ch

µPD78044F 16K to 40K

2 ch

LCD

µPD780308 48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch

—

3 ch (Time division

UART: 1 ch)

2.0 V

driving

µPD78064B 32K

2 ch (UART: 1 ch)

µPD78064

µPD78098

16K to 32K

IEBus

32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch

—

2 ch 3 ch (UART: 1 ch) 69

2.7 V Available

4.5 V Available

supported

µPD78P0914 32K

6 ch

—

1 ch 8 ch

—

2 ch

Note 10 bits timer: 1 channel

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CHAPTER 1 OUTLINE

1.7 Block Diagram

P100/TI5/TO5

P00

8-bit TIMER/

EVENT COUNTER 5

PORT 0

PORT 1

PORT 3

PORT 5

P01-P03

8-bit TIMER/

EVENT COUNTER 6

P101/TI6/TO6

P10-P17

P30-P37

78K/0

CPU

CORE

WATCHDOG

TIMER

ROM

SI2/R^XD/P70

SO2/T^XD/P71

SERIAL

INTERFACE 2

P50-P57

P70-P72

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

A/D

CONVERTER

AV^DD

AVSS

PORT 7

AVREF

RAM

INTP1/P01-

INTP3/P03

PORT 10

P100, P101

INTERRUPT

CONTROL

BUZZER OUTPUT

BUZ/P36

PCL/P35

RESET

SYSTEM

CONTROL

CLOCK OUTPUT

CONTROL

VDD VSS IC

(V^PP)

Remarks 1. The internal ROM and high-speed RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the µPD78P083.

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CHAPTER 1 OUTLINE

1.8 Outline of Function

Part Number

Item

µPD78081

µPD78082

µPD78083

Internal memory

ROM

Mask ROM

PROM

8 Kbytes

256 bytes

64 Kbytes

16 Kbytes

384 bytes

24 Kbytes^Note

512 bytes^Note

High-speed RAM

Memory space

General register

Instruction cycle

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Instruction execution time variable function is integrated.

0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock)

• 16-bit operation

Instruction set

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

I/O ports

Total

• CMOS input

• CMOS input/output

A/D converter

Serial interface

Timer

• 8-bit resolution × 8 channels

• 3-wire serial I/O/UART mode selectable: 1 channel

• 8-bit timer/event counter: 2 channels

• Watchdog timer: 1 channel

Timer output

Clock output

2 pins (8-bit PWM output enable)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

and 5.0 MHz (@ 5.0-MHz operation with main system clock)

1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz

(@ 5.0-MHz operation with main system clock)

Internal : 8 external : 3

Buzzer output

Vectored

interrupt

source

Maskable

Non-maskable

Software

Internal : 1

Supply voltage

V^DD= 1.8 to 5.5 V

Operating ambient temperature

Package

T^A= –40 to +85°C

• 42-pin plastic shrink DIP (600 mil)

• 44-pin plastic QFP (10 × 10 mm)

• 42-pin ceramic shrink DIP (with window) (600 mil) (µPD78P083 only)

Note

Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size

switching register (IMS).

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CHAPTER 1 OUTLINE

1.9 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A) and

78P083(A), and the µPD78081(A2)

Table 1-1 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A) and

78P083(A), and the µPD78081(A2)

Part Number

µPD78081

µPD78082

µPD78P083

µPD78081(A)

µPD78082(A)

µPD78P083(A)

µPD78081(A2)

Item

Quality grade

Standard

VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Special

Supply voltage

VDD = 4.5 to 5.5 V

TA = –40 to +125°C

Electrical specifications

Please refer to the individual data sheets.

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CHAPTER 1 OUTLINE

[MEMO]

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CHAPTER 2 PIN FUNCTION

2.1 Pin Function List

2.1.1 Normal operating mode pins

(1) Port pins

Pin Name

P00

Input/Output

Input

Function

After Reset

Input

Alternate Function

—

Port 0

Input only

P01

P02

P03

Input/output

4-bit input/output port

Input/output is specifiable

bit-wise. When used as the

input port, it is possible to

connect a pull-up resistor by

software.

Input

INTP1

INTP2

INTP3

P10-P17

Port 1

Input

ANI0-ANI7

8-bit input/output port

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect

Note

a pull-up resistor by software.

P30-P34

P35

Port 3

—

PCL

BUZ

—

8-bit input/output port

P36

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect

a pull-up resistor by software.

Port 5

P37

P50-P57

—

8-bit input/output port

A maximum of 7 out of 8 ports can drive LEDs directly.

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect

a pull-up resistor by software.

Port 7

P70

P71

P72

Input/output

Input

SI2/RxD

3-bit input/output port

SO2/TxD

SCK2/ASCK

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect

a pull-up resistor by software.

Port 10

P100

P101

TI5/TO5

TI6/TO6

2-bit input/output port

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect

a pull-up resistor by software.

Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to

the input mode. The on-chip pull-up resistor is automatically disabled.

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CHAPTER 2 PIN FUNCTION

(2) Pins other than port pins

Pin Name

INTP1

Input/Output

Input

Function

After Reset

Alternate Function

External interrupt request input by which the active edge Input

(rising edge, falling edge, or both rising and falling edges)

can be specified.

P01

INTP2

INTP3

SI2

P02

P03

Input

Serial interface serial data input.

Input

P70/RxD

SO2

SCK2

RxD

Output

Input/output

Input

Serial interface serial data output.

P71/TxD

Serial interface serial clock input/output.

Asynchronous serial interface serial data input.

Asynchronous serial interface serial data output.

Asynchronous serial interface serial clock input.

External count clock input to 8-bit timer (TM5).

External count clock input to 8-bit timer (TM6).

8-bit timer output. (also used for 8-bit PWM output)

P72/ASCK

P70/SI2

TxD

Output

Input

P71/SO2

ASCK

TI5

P72/SCK2

Input

P100/TO5

TI6

P101/TO6

TO5

Output

Input

P100/TI5

TO6

P101/TI6

PCL

Output

Input

–

Clock output. (for main system clock trimming)

Buzzer output.

Input

P35

BUZ

ANI0-ANI7

AV^REF

AV^DD

AV^SS

RESET

P36

A/D converter analog input.

P10-P17

A/D converter reference voltage input.

A/D converter analog power supply. Connected to VDD.

A/D converter ground potential. Connected to VSS.

System reset input.

–

Input

–

Main system clock oscillation crystal connection.

V^DD

–

Positive power supply.

V^PP

–

High-voltage applied during program write/verification.

Connected directly to V^SSin normal operating mode.

Ground potential.

V^SS

–

Internal connection. Connect directly to V^SS.

Does not internally connected. Connect to V^SS.

(It can be left open)

2.1.2 PROM programming mode pins (µPD78P083 only)

Pin Name

RESET

Input/Output

Input

Function

PROM programming mode setting.

When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the

RESET pin, the PROM programming mode is set.

VPP

Input

Input/output

Input

—

High-voltage application for PROM programming mode setting and program write/verify.

A0 to A14

D0 to D7

Address bus

Data bus

PROM enable input/program pulse input

Read strobe input to PROM

Program/program inhibit input in PROM programming mode

Positive power supply

PGM

VDD

VSS

—

Ground potential

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CHAPTER 2 PIN FUNCTION

2.2 Description of Pin Functions

2.2.1 P00 to P03 (Port 0)

These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt

request input.

The following operating modes can be specified bit-wise.

(1) Port mode

P00 functions as input-only port and P01 to P03 function as input/output ports.

P01 to P03 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they

are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor option

(2) Control mode

INTP1 to INTP3 function as external interrupt request input pins which are capable of specifying the valid edges

(rising edge, falling edge, and both rising and falling edges).

2.2.2 P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports.

They can be specified bit-wise as input or output ports with a port mode register 1 (PM1). If used as input

ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L

(PUOL).

(2) Control mode

These ports function as A/D converter analog input pins (ANI0-ANI7). The on-chip pull-up resistor is

automatically disabled when the pins specified for analog input.

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CHAPTER 2 PIN FUNCTION

2.2.3 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock output and buzzer

output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with

port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used by

defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as clock output, and buzzer output.

(a) PCL

Clock output pin.

(b) BUZ

Buzzer output pin.

2.2.4 P50 to P57 (Port 5)

These are 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register

5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor

option register L (PUOL). A maximum of 7 out of 8 ports can drive LEDs directly.

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CHAPTER 2 PIN FUNCTION

2.2.5 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/

output and clock input/output functions.

The following operating modes can be specified bit-wise.

(1) Port mode

Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible

by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used

by defining the pull-up resistor option register L (PUOL).

(2) Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a) SI2, SO2

Serial interface serial data input/output pins

(b) SCK2

Serial interface serial clock input/output pin.

Asynchronous serial interface serial data input/output pins.

(d) ASCK

Asynchronous serial interface serial clock input pin.

Caution When this port is used as a serial interface, the I/O and output latches must be set according

to the function the user requires.

For the setting, see the operation mode setting list in Table 11-2 “Serial Interface Channel

2 Operating Mode Settings”

2.2.6 P100 to P101 (Port 10)

These are 2-bit input/output ports. Besides serving as input/output ports, they function as timer input/output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 2-bit input/output ports. They can be specified bit-wise as input or output ports with

port mode register 10 (PM10). When they are used as input ports, on-chip pull-up resistors can be used by

defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports function as timer input/output.

(a) TI5, TI6

Pin for external clock input to the 8-bit timer/event counter 5 and 6.

(b) TO5, TO6

Timer output pins.

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CHAPTER 2 PIN FUNCTION

2.2.7 AVREF

A/D converter reference voltage input pin.

When A/D converter is not used, connect this pin to V^SS.

2.2.8 AV^DD

Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D

converter is not used.

2.2.9 AVSS

This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/

D converter is not used.

2.2.10 RESET

This is a low-level active system reset input pin.

2.2.11 X1 and X2

Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its

inverted signal to X2.

2.2.12 V^DD

Positive power supply pin

2.2.13 V^SS

Ground potential pin

2.2.14 V^PP(µPD78P083 only)

High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V^SS

in normal operating mode.

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CHAPTER 2 PIN FUNCTION

2.2.15 IC (Mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the µPD78083 Subseries at delivery.

Connect it directly to the V^SSwith the shortest possible wire in the normal operating mode.

When a voltage difference is produced between the IC pin and V^SSpin because the wiring between those two pins

is too long or an external noise is input to the IC pin, the user's program may not run normally.

Connect IC pins to VSS pins directly.

VSS IC

As short as possible

2.2.16 NC (44-pin plastic QFP versions only)

Not internally connected. Please connect to Vss (open is also possible)

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CHAPTER 2 PIN FUNCTION

2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins

Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1.

For the configuration of each type of input/output circuit, see Figure 2-1.

Table 2-1. Type of Input/Output Circuit of Each Pin

Pin Name

Input/Output

Circuit Type

Input/Output

Recommended Connection for Unused Pins

P00

Input

Connect to V^SS.

P01/INTP1

P02/INTP2

P03/INTP3

P10/ANI0-P17/ANI7

P30-P32

8-A

Input/Output

Independently connect to VSS via a resistor.

Input/Output

Independently connect to V^DDor VSS via

a resistor.

5-A

8-A

5-A

P33, P34

P35/PCL

P36/BUZ

P37

P50-P57

5-A

8-A

5-A

8-A

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P100/TI5/TO5

P101/TI6/TO6

RESET

Input

–

Connect to VSS.

AV^REF

–

AVDD

Connect to VDD.

AV^SS

Connect to VSS.

VPP (µPD78P083)

NC (44-pin plastic QFP

version)

Connect directly to VSS.

Connect to V^SS(can also leave open)

IC (Mask ROM version)

Connect directly to V^SS.

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CHAPTER 2 PIN FUNCTION

Figure 2-1. Pin Input/Output Circuit of List

Type 2

Type 8-A

VDD

pull-up

enable

P-ch

VDD

data

P-ch

IN/OUT

Schmitt-Triggered Input with

Hysteresis Characteristics

output

disable

N-ch

Type 11

Type 5-A

V^DD

VDD

pull-up

enable

P-ch

pull-up

enable

P-ch

VDD

data

P-ch

VDD

IN/OUT

data

P-ch

output

disable

N-ch

P-ch

N-ch

IN/OUT

comparator

output

disable

–

N-ch

V^REF(Threshold voltage)

input

enable

input

enable

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CHAPTER 2 PIN FUNCTION

[MEMO]

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Spaces

Figures 3-1 to 3-3 shows memory maps.

Figure 3-1. Memory Map (µPD78081)

FFFFH

Special Function

Registers (SFRs)

256 × 8 bits

FF00H

FEFFH

General Registers

32 × 8 bits

FEE0H

FEDFH

Internal High-speed RAM

1FFFH

256 × 8 bits

Program Area

CALLF Entry Area

Program Area

1000H

0FFFH

FE00H

FDFFH

Data memory

space

0800H

07FFH

Unusable

0080H

007FH

2000H

1FFFH

CALLT Table Area

Vector Table Area

Program

memory

space

0040H

003FH

Internal ROM

8192 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD78082)

FFFFH

Special Function

Registers (SFRs)

256 × 8 bits

FF00H

FEFFH

General Registers

32 × 8 bits

FEE0H

FEDFH

3FFFH

Internal High-speed RAM

384 × 8 bits

Program Area

CALLF Entry Area

Program Area

1000H

0FFFH

FD80H

FD7FH

Data memory

space

0800H

07FFH

Unusable

0080H

007FH

4000H

3FFFH

CALLT Table Area

Vector Table Area

Program

memory

space

0040H

003FH

Internal ROM

16384 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-3. Memory Map (µPD78P083)

FFFFH

Special Function

Registers (SFRs)

256 × 8 bits

FF00H

FEFFH

General Registers

32 × 8 bits

FEE0H

FEDFH

5FFFH

Internal High-speed RAM

512 × 8 bits

Program Area

CALLF Entry Area

Program Area

1000H

0FFFH

FD00H

FCFFH

Data memory

space

0800H

07FFH

Unusable

0080H

007FH

6000H

5FFFH

CALLT Table Area

Vector Table Area

Program

memory

space

0040H

003FH

Internal PROM

24576 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory is mask ROM with a 8192 × 8-bit configuration in the µPD78081, and a 16384 ×

8-bit configuration in the µPD78082, and PROM with a 24576 × 8-bit configuration in the µPD78P083.

The internal program memory spacestores programs and table data. Normally, they are addressed with a program

counter (PC).

The internal program memory is divided into the following three areas.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start

addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the

16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

Table 3-1. Vector Table

Vector Table Address

0000H

Interrupt Request

RESET input

INTWDT

INTP1

0004H

0008H

000AH

INTP2

000CH

INTP3

0018H

INTSER

INTSR/INTCSI2

INTST

001AH

001CH

0028H

INTAD

002AH

INTTM5

002CH

INTTM6

003EH

BRK

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory space

The internal high speed RAM configuration is 256 × 8-bit in the µPD78081, 384 × 8-bit in the µPD78082 and 512

× 8-bit in the µPD8P083. In this area, four banks of general registers, each bank consisting of eight 8-bit registers,

are allocated in the 32-byte area FEE0H to FEFFH.

The internal high-speed RAM can also be used as a stack memory area.

3.1.3 Special Function Register (SFR) area

An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer

to Table 3-2. Special-Function Register List in 3.2.3 Special Function Register (SFR)).

Caution Do not access addresses where the SFR is not assigned.

3.1.4 Data memory addressing

The method to specify the address of the instruction to be executed next, or the address of a register or memory

to be manipulated when an instruction is executed is called addressing.

The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to

3.3 Instruction Address Addressing).

To address the memory that is manipulated when an instruction is executed, the µPD78083 Subseries is provided

with many addressing modes with a high operability. Especially at addresses corresponding to data memory area,

particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general

registers. This area is between FE00H and FFFFH for the µPD78081, FD80H and FFFFH for the µPD78082, and

between FD00H and FFFFH for the µPD78P083. The data memory space is the entire 64K-byte space (0000H to

FFFFH). Figure 3-4 to 3-6 show the data memory addressing modes. For details of each addressing, refer to 3.4

Operand Address Addressing.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Data Memory Addressing (µPD78081)

FFFFH

Special Function

Registers (SFRs)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

General Registers

32 × 8 bits

FEE0H

FEDFH

Short Direct

Addressing

Internal High-speed RAM

Direct Addressing

256 × 8 bits

FE20H

FE1FH

Addressing

FE00H

FDFFH

Based Addressing

Based Indexed

Addressing

Unusable

2000H

1FFFH

Internal ROM

8192 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Data Memory Addressing (µPD78082)

FFFFH

Special Function

Registers (SFRs)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

General Registers

32 × 8 bits

FEE0H

FEDFH

Short Direct

Addressing

Internal High-speed RAM

Direct Addressing

384 × 8 bits

FE20H

FE1FH

Addressing

FD80H

FD7FH

Based Addressing

Based Indexed

Addressing

Unusable

4000H

3FFFH

Internal ROM

16384 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Data Memory Addressing (µPD78P083)

FFFFH

Special Function

Registers (SFRs)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

General Registers

32 × 8 bits

Short Direct

Addressing

FEE0H

FEDFH

Internal High-speed RAM

Direct Addressing

512 × 8 bits

FE20H

FE1FH

Addressing

FD00H

FCFFH

Based Addressing

Based Indexed

Addressing

Unusable

6000H

5FFFH

Internal PROM

24576 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

The µPD78083 subseries units incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist

of a program counter, a program status word and a stack pointer.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data and register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Program Counter Configuration

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-8. Program Status Word Configuration

RBS1

RBS0

ISP

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.

When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status).

When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled

with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority

specify flag.

The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request

is acknowledged, and set to 1 when the EI instruction is executed.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags to select one of the four register banks.

In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction

execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all

other cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the

vectored interrupt request whose priority is specified by the priority specify flag registers (PR0L, PR0H,

and PR1L) (Refer to 12.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is

disabled. Whether the interrupt request is actually acknowledged is controlled by the status of the interrupt

enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out

value upon rotate instruction execution and functions as a bit accumulator during bit manipulation

instruction execution.

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CHAPTER 3 CPU ARCHITECTURE

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM

area (FE00H-FEFFH for the µPD78081, FD80H-FEFFH for the µPD78082, and FD00H-FEFFH for the

µPD78P083) can be set as the stack area.

Figure 3-9. Stack Pointer Configuration

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from

the stack memory.

Each stack operation saves/resets data as shown in Figures 3-10 and 3-11.

Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before

instruction execution.

Figure 3-10. Data to be Saved to Stack Memory

Interrupt and

BRK Instruction

PUSH rp Instruction

CALL, CALLF, and

CALLT Instruction

SP SP

PC7-PC0

PC15-PC8

PSW

PC7-PC0

PC15-PC8

Figure 3-11. Data to be Reset from Stack Memory

RETI and RETB

Instruction

POP rp Instruction

RET Instruction

SP + 1

PC7-PC0

PC15-PC8

PSW

SP + 1

SP + 2

PC15-PC8

SP SP + 2

SP SP + 3

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General registers

A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks,

each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).

Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register

(AX, BC, DE and HL).

They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names

(R0 to R7 and RP0 to RP3).

of the 4-register bank configuration, an efficient program can be created by switching between a register for normal

processing and a register for interruption request for each bank.

Figure 3-12. General Register Configuration

(a) Absolute Name

16-Bit Processing

RP3

8-Bit Processing

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

RP2

RP1

RP0

FEF0H

FEE8H

FEE0H

(b) Function Name

16-Bit Processing

8-Bit Processing

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

FEF0H

FEE8H

FEE0H

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special Function Register (SFR)

Unlike a general register, each special-function register has special functions.

It is allocated in the FF00H to FFFFH area.

The special-function register can be manipulated like the general register, with the operation, transfer and bit

manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can also be specified with an address.

• 8-bit manipulation

Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can also be specified with an address.

• 16-bit manipulation

Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).

When addressing an address, describe an even address.

Table 3-2 gives a list of special-function registers. The meaning of items in the table is as follows.

• Symbol

Symbols indicating the addresses of special function register. These symbols are reserved words for the RA78K/

0 and defined by header file sfrbit.h for the CC78K/0, and can be used as the operands of instructions when

the RA78K/0, ID78K0, and SD78K/0 are used.

• R/W

Indicates whether the corresponding special-function register can be read or written.

R/W : Read/write enable

: Read only

: Write only

• Manipulatable bit units

√ indicates bit units (1, 8 or 16 bits) in which the register can be manipulated. — indicates that the register cannot

be manipulated in the indicated bit units.

• After reset

Indicates each register status upon RESET input.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-2. Special-Function Register List (1/2)

Manipulatable Bit Unit

Address

Special-Function Register (SFR) Name

Symbol

R/W

After Reset

00H

1 bit

8 bits

16 bits

FF00H

FF01H

FF03H

FF05H

FF07H

FF0AH

FF1FH

FF20H

FF21H

FF23H

FF25H

FF27H

FF2AH

FF40H

FF42H

FF50H

FF51H

FF52H

FF53H

FF54H

FF55H

FF56H

FF57H

Port0

√

—

√

—

√

—

Port1

Port3

Port5

Port7

Port10

P10

A/D conversion result register

Port mode register 0

Port mode register 1

Port mode register 3

Port mode register 5

Port mode register 7

Port mode register 10

Timer clock select register 0

Timer clock select register 2

Compare Register 50

8-bit timer register 5

Timer clock select register 5

8-bit timer mode control register 5

Compare Register 60

8-bit timer register 6

Timer clock select register 6

8-bit timer mode control register 6

ADCR

PM0

PM1

PM3

PM5

PM7

PM10

TCL0

TCL2

CR50

TM5

TCL5

TMC5

CR60

TM6

TCL6

TMC6

Undefined

FFH

R/W

00H

R/W

FF70H

FF71H

FF72H

FF73H

Asynchronous serial interface mode register

Asynchronous serial interface status register

Serial operating mode register 2

ASIM

ASIS

√

—

CSIM2

BRGC

R/W

√

Baud rate generator control register

—

FF74H

Transmit shift register

TXS SIO2

RXB

—

√

—

FFH

Receive buffer register

FF80H

FF84H

FFE0H

FFE1H

FFE2H

FFE4H

FFE5H

FFE6H

FFE8H

FFE9H

A/D converter mode register

A/D converter input select register

Interrupt request flag register 0L

Interrupt request flag register 0H

Interrupt request flag register 1L

Interrupt mask flag register 0L

Interrupt mask flag register 0H

Interrupt mask flag register 1L

Priority order specify flag register 0L

Priority order specify flag register 0H

ADM

R/W

√

—

√

—

√

01H

00H

ADIS

IF0

IF0L

IF0H

IF1L

—

MK0 MK0L

MK0H

√

FFH

MK1L

—

PR0

PR0L

PR0H

√

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CHAPTER 3 CPU ARCHITECTURE

Table 3-2. Special-Function Register List (2/2)

Manipulatable Bit Unit

Address

Special-Function Register (SFR) Name

Symbol

R/W

After Reset

1 bit

8 bits

16 bits

FFEAH

FFECH

FFEDH

FFF0H

FFF2H

FFF3H

FFF7H

FFF9H

FFFAH

FFFBH

Priority order specify flag register 1L

External interrupt mode register 0

External interrupt mode register 1

Memory size switching register

Oscillation mode selection register

Pull-up resistor option register H

Pull-up resistor option register L

Watchdog timer mode register

PR1L

INTM0

INTM1

IMS

√

—

√

—

FFH

00H

(Note)

OSMS

PUOH

PUOL

WDTM

OSTS

PCC

00H

R/W

√

Oscillation stabilization time select register

Processor clock control register

—

√

04H

Note The value after reset depends on products.

µPD78081 : 82H, µPD78082 : 64H, µPD78P083 : 46H.

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. The contents of PC are normally

incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each

time another instruction is executed. When a branch instruction is executed, the branch destination information is

set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 USER'S MANUAL:

Instruction (IEU-1372).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit.

In the relative addressing modes, execution branches in a relative range of –128 to +127 from the first address

of the next instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

PC indicates the start address

of the instruction

after the BR instruction.

...

jdisp8

When S = 0, all bits of α are 0.

When S = 1, all bits of α are 1.

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.

The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11

instruction branches to an area of addresses 0800H through 0FFFH.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

CALL or BR

Low Addr.

High Addr.

8 7

In the case of CALLF !addr11 instruction

fa^10–8

CALLF

fa^7–0

11 10

8 7

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CHAPTER 3 CPU ARCHITECTURE

3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the

immediate data of an operation code are transferred to the program counter (PC) and branched.

Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction

references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire

memory space.

[Illustration]

Operation Code

ta4–0

Effective Address

Memory (Table)

Low Addr.

High Addr.

Effective Address+1

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CHAPTER 3 CPU ARCHITECTURE

3.3.4 Register addressing

[Function]

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) which undergo

manipulation during instruction execution.

3.4.1 Implied addressing

[Function]

The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly)

addressed.

Of the µPD78083 Subseries instruction words, the following instructions employ implied addressing.

Instruction

MULU

A register for multiplicand and AX register for product storage

AX register for dividend and quotient storage

DIVUW

ADJBA/ADJBS

ROR4/ROL4

A register for storage of numeric values which become decimal correction targets

A register for storage of digit data which undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format is

necessary.

[Description example]

In the case of MULU X

With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,

the A and AX registers are specified by implied addressing.

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Register addressing

[Function]

This addressing accesses a general register as an operand. The general register accessed is specified by the

8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier

Description

X, A, C, B, E, D, L, H

AX, BC, DE, HL

'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute

names (R0 to R7 and RP0 to RP3).

[Description example]

MOV A, C; when selecting C register as r

Operation code

1 1 0 0 0 1

INCW DE; when selecting DE register pair as rp

Operation code 0 0 0 0 1 0

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Direct addressing

[Function]

This addressing directly addresses the memory indicated by the immediate data in an instruction word.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code

0 0 0 1 1 1

0 0 0 0 0 0

1 1 1 1 1 1

OP code

00H

FEH

[Illustration]

OP code

saddr16 (low)

saddr16 (high)

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An

internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to

FF1FH, respectively.

The SFR area (FF00H through FF1FH) to which short direct addressing is applied is a part of the entire SFR

area. To this area, ports frequently accessed by the program, and the compare registers and capture registers

of timer/event counters are mapped. These SFRs can be manipulated with a short byte length and a few clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. Refer to [Illustration] on next page.

[Operand format]

Identifier

saddr

Description

Label of FE20H to FF1FH immediate data

saddrp

Label of FE20H to FF1FH immediate data (even address only)

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CHAPTER 3 CPU ARCHITECTURE

[Description example]

MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H

Operation code

0 0 1 0 0 0

0 1 1 0 0 0

1 0 1 0 0 0

OP code

30H (saddr-offset)

50H (immediate data)

[Illustration]

OP code

saddr-offset

Short Direct Memory

Effective Address

When 8-bit immediate data is 20H to FFH, α = 0

When 8-bit immediate data is 00H to 1FH, α = 1

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CHAPTER 3 CPU ARCHITECTURE

3.4.5 Special-Function Register (SFR) addressing

[Function]

The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special-function register name

16-bit manipulatable special-function register name (even address only)

sfrp

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code

1 1 1 0 1 1

0 1 0 0 0 0

OP code

20H (sfr-offset)

[Illustration]

OP code

sfr-offset

SFR

Effective Address

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Register indirect addressing

[Function]

This addressing addresses the memory with the contents of a register pair specified as an operand. The register

pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code

in an instruction code. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

—

Description

[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

Operation code 0 0 0 0 1 0

[Illustration]

Memory address specified

by register pair DE

Memory

Contents of addressed

memory are transferred.

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CHAPTER 3 CPU ARCHITECTURE

3.4.7 Based addressing

[Function]

This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair

which is used as a base register and by using the result of the addition. The HL register pair to be accessed

is in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by

expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing

can be carried out for all the memory spaces.

[Operand format]

Identifier

—

Description

[HL + byte]

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

Operation code

0 1 0 1 1 1

0 0 1 0 0 0

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CHAPTER 3 CPU ARCHITECTURE

3.4.8 Based indexed addressing

[Function]

This addressing addresses the memory by adding the contents of the HL register, which is used as a base register,

to the contents of the B or C register specified in the instruction word, and by using the result of the addition.

The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select

flags (RBS0 and RBS1). The addition is performed by extending the contents of the B or C register to 16 bits

as a positive number. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory

spaces.

[Operand format]

Identifier

—

Description

[HL + B], [HL + C]

[Description example]

In the case of MOV A, [HL + B]

Operation code

0 1 0 1 0 1

3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN

instructions are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing enables to address the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Operation code

0 1 1 0 1 0

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

The µPD78083 Subseries units incorporate an input port and thirty-two input/output ports. Figure 4-1 shows the

port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control

operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.

Figure 4-1. Port Types

P50

P00

Port 0

Port 1

P03

P10

Port 5

P57

P70

Port 7

P72

P17

P30

P100

Port 10

P101

Port 3

P37

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CHAPTER 4 PORT FUNCTIONS

Table 4-1. Port Functions

Pin Name

P00

Input/Output

Input

Function

Dual-Function Pin

Port 0

Input only

—

P01

Input/output 4-bit input/output port Input/output is specifiable bit-wise. When

INTP1

P02

used as the input port, it is possible to connect INTP2

P03

a pull-up resistor by software.

INTP3

P10-P17

Input/output Port 1

8-bit input/output port

ANI0-ANI7

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect a pull-up resistor

by software.

P30-P34

P35

Input/output Port 3

—

PCL

8-bit input/output port

P36

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect a pull-up resistor

by software.

BUZ

P37

—

P50-P57

Input/output Port 5

—

8-bit input/output port

A maximum of 7 out of 8 ports can drive LEDs directly.

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect a pull-up resistor

by software.

P70

P71

P72

Input/output Port 7

SI2/RxD

3-bit input/output port

SO2/TxD

SCK2/ASCK

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect a pull-up resistor

by software.

P100

P101

Input/output Port 10

TI5/TO5

TI6/TO6

2-bit input/output port

Input/output is specifiable bit-wise.

When used as the input port, it is possible to connect a pull-up resistor

by software.

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CHAPTER 4 PORT FUNCTIONS

4.2 Port Configuration

A port consists of the following hardware:

Table 4-2. Port Configuration

Item

Configuration

Control register

Port mode register (PMm: m = 0, 1, 3, 5, 7, 10)

Pull-up resistor option register (PUOH, PUOL)

Total: 33 ports (1 input, 32 inputs/outputs)

Total: 32 (software specifiable)

Port

Pull-up resistor

4.2.1 Port 0

Port 0 is an 4-bit input/output port with output latch. P01 to P03 pins can specify the input mode/output mode in

1-bit units with the port mode register 0 (PM0). P00 pin is input-only port. When P01 to P03 pins are used as input

ports, an on-chip pull-up resistor can be used to them in 3-bit units with a pull-up resistor option register L (PUOL).

Dual-functions include external interrupt request input.

RESET input sets port 0 to input mode.

Figures 4-2 and 4-3 show block diagrams of port0.

Caution Because port 0 also serves for external interrupt request input, when the port function output

mode is specified and the output level is changed, the interrupt request flag is set. Thus, when

the output mode is used, set the interrupt mask flag to 1.

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CHAPTER 4 PORT FUNCTIONS

Figure 4-2. P00 Block Diagram

P00

Figure 4-3. P01 to P03 Block Diagram

VDD

WR^PUO

PUO0

P-ch

Selector

WRPORT

P01/INTP1

P03/INTP3

Output Latch

(P01 to P03)

WRPM

PM01-PM03

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 0 read signal

WR : Port 0 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with

a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used

to them in 8-bit units with a pull-up resistor option register L (PUOL).

Dual-functions include an A/D converter analog input.

RESET input sets port 1 to input mode.

Figure 4-4 shows a block diagram of port 1.

Caution A pull-up resistor cannot be used for pins used as A/D converter analog input.

Figure 4-4. P10 to P17 Block Diagram

VDD

WR^PUO

PUO1

P-ch

Selector

WRPORT

P10/ANI0

Output Latch

(P10 to P17)

P17/ANI7

WRPM

PM10-PM17

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 1 read signal

WR : Port 1 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 3

Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in

1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up

resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

Dual-functions include clock output and buzzer output.

RESET input sets port 3 to input mode.

Figure 4-5 shows a block diagram of port 3.

Figure 4-5. P30 to P37 Block Diagram

VDD

WR^PUO

PUO3

P-ch

Selector

WRPORT

P30

Output Latch

(P30 to P37)

P34,

P35/PCL,

P36/BUZ,

P37

WRPM

PM30-PM37

Alternate Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 3 read signal

WR : Port 3 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 5

Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in

1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up

resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

A maximum of 7 out of 8 ports can drive LEDs directly.

RESET input sets port 5 to input mode.

Figure 4-6 shows a block diagram of port 5.

Figure 4-6. P50 to P57 Block Diagram

VDD

WR^PUO

PUO5

P-ch

Selector

WRPORT

Output Latch

(P50 to P57)

P50-P57

WRPM

PM50-PM57

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 5 read signal

WR : Port 5 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.5 Port 7

This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means

of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can

be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).

Dual-functions include serial interface channel 2 data input/output and clock input/output.

RESET input sets the input mode.

Port 7 block diagrams are shown in Figures 4-7 and 4-8.

Caution When used as a serial interface, set the input/output and output latch according to its functions.

For the setting method, refer to Table 11-2 Serial Interface Channel 2 Operating Mode Settings.

Figure 4-7. P70 Block Diagram

VDD

WR^PUO

PUO7

P-ch

Selector

WRPORT

Output Latch

P70/SI2/RxD

(P70)

WRPM

PM70

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 7 read signal

WR : Port 7 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-8. P71 and P72 Block Diagram

VDD

WR^PUO

PUO7

P-ch

Selector

WRPORT

Output Latch

(P71 and P72)

P71/SO2/TxD,

P72/SCK2/ASCK

WRPM

PM71, PM72

Alternate Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 7 read signal

WR : Port 7 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.6 Port 10

This is an 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means

of port mode register 10 (PM10). When pins P100 to P101 are used as input port pins, an on-chip pull-up resistor

can be used as an 2-bit unit by means of pull-up resistor option register H (PUOH).

These pins are dual function pins and serve as timer inputs/outputs.

RESET input sets the input mode.

The port 10 block diagram is shown in Figure 4-9.

Figure 4-9. P100 to P101 Block Diagram

VDD

WR^PUO

PUO10

P-ch

Selector

WRPORT

Output Latch

P100/TI5/TO5,

(P100 to P101)

P101/TI6/TO6

WRPM

PM100 to PM101

Alternate

Functions

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 10 read signal

WR : Port 10 write signal

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CHAPTER 4 PORT FUNCTIONS

4.3 Port Function Control Registers

The following two types of registers control the ports.

• Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10)

• Pull-up resistor option register (PUOH, PUOL)

(1) Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10)

These registers are used to set port input/output in 1-bit units.

PM0, PM1, PM3, PM5, PM7, PM10 are independently set with a 1-bit or 8-bit memory manipulation instruction

RESET input sets registers to FFH.

When port pins are used as the dual-function pins, set the port mode register and output latch according to

Table 4-3.

Cautions 1. P00 pin is input-only pin.

2. As port 0 has a dual function as external interrupt request input, when the port function

output mode is specified and the output level is changed, the interrupt request flag is

set. When the output mode is used, therefore, the interrupt mask flag should be set to

1 beforehand.

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CHAPTER 4 PORT FUNCTIONS

Table 4-3. Port Mode Register and Output Latch Settings when Using Dual-Functions

Dual-functions

PM××

P××

Pin Name

Name

Input/Output

P01 to P03

INTP1 to INTP3

Input

P10 to P17^Note

ANI0 to ANI7

PCL

Input

P35

Output

Input

P36

BUZ

P100

TI5

TO5

Output

Input

P101

TI6

TO6

Output

Note If a read instruction is performed to these pins when they are used as an alternate function, read data is

to be undefined.

Caution When port 7 is used for serial interface, the I/O latch or output latch must be set according to

its function. For the setting methods, see Table 11-2 “Serial Interface Channel 2 Operating Mode

Settings.”

Remarks

: don’t care

PM×× : port mode register

P×× : port output latch

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CHAPTER 4 PORT FUNCTIONS

Figure 4-10. Port Mode Register Format

After

Reset

Symbol

PM0

Address

FF20H

R/W

PM03 PM02 PM01

FFH

PM1

FF21H

FF23H

FF25H

FF27H

FF2AH

R/W

PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10

PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30

PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50

R/W

PM7

PM72 PM71 PM70

PM10

PM101 PM100

Pmn Pin Input/Output Mode Selection

(m = 0, 1, 3, 5, 7, 10 : n = 0 to 7)

PMmn

Output mode (output buffer ON)

Input mode (output buffer OFF)

Caution Set 1 to the bits 0, 4 to 7 of PM0, bits 3 to 7 of PM7 and bits 2 to 7 of PM10.

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CHAPTER 4 PORT FUNCTIONS

(2) Pull-up resistor option register (PUOH, PUOL)

This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor

is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been

specified with PUOH, PUOL. No on-chip pull-up resistors can be used to the bits set to the output mode or

to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.

PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Cautions 1. P00 pin does not incorporate a pull-up resistor.

2. When port 1 is used as dual-function pin, an on-chip pull-up resistor cannot be used even

if 1 is set in PUOL bit 1 (PUO1).

Figure 4-11. Pull-Up Resistor Option Register Format

After

Reset

Symbol

PUOH

Address

FFF3H

R/W

PUO10

00H

PUOL PUO7

PUO5

PUO3

PUO1 PUO0

FFF7H

00H

R/W

Pm Internal Pull-up Resistor Selection

(m = 0, 1, 3, 5, 7, 10)

PUOm

Internal pull-up resistor not used

Internal pull-up resistor used

Caution Set 0 to the bits 0, 1, 3 to 7 of PUOH and bits 2, 4, 6 of PUOL.

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CHAPTER 4 PORT FUNCTIONS

4.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

4.4.1 Writing to input/output port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from

the pin.

Once data is written to the output latch, it is retained until data is written to the output latch again.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status

does not change.

Once data is written to the output latch, it is retained until data is written to the output latch again.

Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated

the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output

pins, the output latch contents for pins specified as input are undefined except for the

manipulated bit.

4.4.2 Reading from input/output port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

4.4.3 Operations on input/output port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output

latch contents are output from the pins.

Once data is written to the output latch, it is retained until data is written to the output latch again.

(2) Input mode

The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.

Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated

the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output

pins, the output latch contents for pins specified as input are undefined, even for bits other

than the manipulated bit.

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CHAPTER 4 PORT FUNCTIONS

[MEMO]

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CHAPTER 5 CLOCK GENERATOR

5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type

of system clock oscillator is available.

Main system clock oscillator

This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction.

5.2 Clock Generator Configuration

The clock generator consists of the following hardware.

Table 5-1. Clock Generator Configuration

Item

Configuration

Control register

Processor clock control register (PCC)

Oscillation mode selection register (OSMS)

Main system clock oscillator

Oscillator

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CHAPTER 5 CLOCK GENERATOR

Figure 5-1. Block Diagram of Clock Generator

Prescaler

Clock to

Peripheral

Hardware

Main

System

Clock

Prescaler

Scaler

f^XX

Oscillator

f^X

fXX

2⁴

Standby

Control

Circuit

2³

fXX

CPU Clock

(f^CPU)

2²

f^XX

STOP

MCS

PCC2

PCC0

PCC1

Oscillation Mode

Selection Register

Processor Clock Control Register

Internal Bus

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CHAPTER 5 CLOCK GENERATOR

5.3 Clock Generator Control Register

The clock generator is controlled by the following two registers:

• Processor clock control register (PCC)

• Oscillation mode selection register (OSMS)

(1) Processor clock control register (PCC)

The PCC sets whether to use CPU clock selection and the ratio of division.

The PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the PCC to 04H.

Figure 5-2. Processor Clock Control Register Format

After

Symbol

PCC

Address

FFFBH

Reset

R/W

PCC2 PCC1 PCC0

04H

CPU CIock Selection (f^CPU)

MCS=1

PCC2 PCC1 PCC0

MCS=0

fXX

(0.4

/2 (0.8

x/2²(1.6µs)

fXX/2

f^XX/2²

fXX/2³

fXX/2⁴

x/2 (0.8

x/2 (1.6 s)

x/2³(3.2

x/2⁴(6.4

x/2³(3.2

x/2⁴(6.4

x/2⁵(12.8

Other than above

Setting prohibited

Caution Set 0 to the bits 3 to 7.

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X: Main system clock oscillator frequency

3. MCS : Bit 0 of oscillation mode selection register (OSMS)

4. Figures in parentheses indicate minimum instruction execution time : 2f^CPUwhen operating

at f^X= 5.0 MHz.

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CHAPTER 5 CLOCK GENERATOR

(2) Oscillation mode selection register (OSMS)

This register specifies whether the clock output from the main system clock oscillator without passing through

the scaler is used as the main system clock, or the clock output via the scaler is used as the main system

clock.

OSMS is set with 8-bit memory manipulation instruction.

RESET input sets OSMS to 00H.

Figure 5-3. Oscillation Mode Selection Register Format

After

Symbol

OSMS

Reset

Address

FFF2H

R/W

MCS

00H

Main System Clock Scaler Control

Scaler used

MCS

Scaler not used

Cautions 1. Writing to OSMS should be performed only immediately after reset signal release and before

peripheral hardware operation starts. As shown in Figure 5-4 below, writing data (including

same data as previous) to OSMS cause delay of main system clock cycle up to 2/f^xduring

the write operation. Therefore, if this register is written during the operation, in peripheral

hardware which operates with the main system clock, a temporary error occurs in the count

clock cycle of timer, etc. In addition, because the oscillation mode is changed by this register,

the clocks for peripheral hardware as well as that for the CPU are switched.

Figure 5-4. Main System Clock Waveform due to Writing to OSMS

Write to OSMS

(MCS

Max. 2/fX

fXX

Operating at fXX = fX/2 (MCS = 0)

2. When writing “1” to MCS, V^DDmust be 2.7 V or higher before the write execution.

Remarks f^xx: Main system clock frequency (fx or fx/2)

f^x: Main system clock oscillation frequency

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CHAPTER 5 CLOCK GENERATOR

5.4 System Clock Oscillator

5.4.1 Main system clock oscillator

The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz)

connected to the X1 and X2 pins.

External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin

and an antiphase clock signal to the X2 pin.

Figure 5-5 shows an external circuit of the main system clock oscillator.

Figure 5-5. External Circuit of Main System Clock Oscillator

(a) Crystal and ceramic oscillation

(b) External clock

External

Clock

PD74HCU04

Crystal

Ceramic Resonator

Cautions 1. Do not execute the STOP instruction if an external clock is used. This is because the X2 pin

is connected to V^DDvia a pull-up register.

2. When using a main system clock oscillator, carry out wiring in the broken line area in Figure

5-5 to prevent any effects from wiring capacities.

● Minimize the wiring length.

● Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come

near changing high current.

● Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do

not ground to any ground pattern where high current is present.

● Do not fetch signals from the oscillator.

Figure 5-6 shows examples of oscillator having bad connection.

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CHAPTER 5 CLOCK GENERATOR

Figure 5-6. Examples of Oscillator with Bad Connection (1/2)

(a) Wiring of connection circuits

(b) Signal conductors intersect

with each other

is too long

PORTn

(n = 0, 1, 3, 5, 7, 10)

signal conductor

(d) Current flows through the grounding line

of the ocsillator (potential at points A, B,

and C fluctuate)

V^DD

Pnm

High

Current

High

Current

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CHAPTER 5 CLOCK GENERATOR

Figure 5-6. Examples of Oscillator with Bad Connection (2/2)

5.4.2 Scaler

The scaler divides the main system clock oscillator output (f^XX) and generates various clocks.

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CHAPTER 5 CLOCK GENERATOR

5.5 Clock Generator Operations

The clock generator generates the following various types of clocks and controls the CPU operating mode

including the standby mode.

• Main system clock

• CPU clock

fXX

fCPU

• Clock to peripheral hardware

The following clock generator functions and operations are determined with the processor clock control register

(PCC) and the oscillation mode selection register (OSMS).

(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (12.8 µs when operated

at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is

applied to RESET pin.

(b) The six types of CPU clocks (0.4 µs. 0.8 µs, 1.6 µs, 3.2 µs, 6.4µs, 12.8 µs : 5.0 MHz) can be selected by setting

the PCC and OSMS.

(d) The main system clock is divided and supplied to the peripheral hardware. Thus, the peripheral hardware

also stops if the main system clock is stopped. (Except external input clock operation)

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CHAPTER 5 CLOCK GENERATOR

5.6 Changing CPU Clock Settings

5.6.1 Time required for CPU clock switchover

The CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) of the processor clock control register

(PCC).

The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the

pre-switchover clock for several instructions (see Table 5-2).

Table 5-2. Maximum Time Required for CPU Clock Switchover

Set Values before

Switchover

Set Values After Switchover

PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0

PCC2 PCC1 PCC0

16 instructions

8 instructions

16 instructions

8 instructions

16 instructions

8 instructions

4 instructions

2 instructions

1 instruction

2 instructions

1 instruction

2 instructions

1 instruction

Remark One instruction is the minimum instruction execution time with the pre-switchover CPU clock.

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CHAPTER 5 CLOCK GENERATOR

5.6.2 CPU clock switching procedure

This section describes CPU clock switching procedure.

Figure 5-7. CPU Clock Switching

VDD

RESET

CPU Clock

Minimum Maximum Speed

Speed

Operation

Wait (26.2 ms : 5.0 MHz)

Internal Reset Operation

(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released

by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation

stabilization time (2 /fX) is secured automatically.

After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 µs when

operated at 5.0 MHz).

(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds,

the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and

the maximum-speed operation is carried out.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

The timers incorporated into the µPD78083 subseries are outlined below.

(1) 8-bit timers/event counters 5 and 6 (TM5 and TM6)

This can be used to serve as an interval timer, an external event counter, square wave output with any selected

frequency PWM, etc. It cannot be used as a 16-bit timer/event counter (SeeCHAPTER 6 8-BIT TIMER/EVENT

COUNTERS 5 AND 6).

(2) Watchdog timer (WDTM)

WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable

interrupt requests and RESET at the preset time intervals (See CHAPTER 7 WATCHDOG TIMER).

(3) Clock output control circuit

This circuit supplies a clock obtained by dividing the main system clock, to other devices (See CHAPTER 8

CLOCK OUTPUT CONTROL CIRCUIT).

(4) Buzzer output control circuit

This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 9

BUZZER OUTPUT CONTROL CIRCUIT).

Table 6-1 Timer/Event Counter Types and Functions

8-bit Timer/Event Counters 5 and 6

Watchdog Timer

Note

Type

Interval timer

2 channels

1 channel

External event counter

Timer output

√

—

√

Function

PWM output

Square-wave output

Interrupt request

Note Watchdog timer can perform either the watchdog timer function or the interval timer function.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.1 8-Bit Timer/Event Counters 5 and 6 Functions

The 8-bit timer/event counters 5 and 6 (TM5 and TM6) have the following functions.

• Interval timer

• External event counter

• Square-wave output

• PWM output

(1) 8-bit interval timer

Interrupt requests are generated at the preset time intervals.

Table 6-2. 8-Bit Timer/Event Counters 5 and 6 Interval Times

Minimum Interval Time

Maximum Interval Time

Resolution

MCS = 0

MCS = 1

—

MCS = 0

MCS = 1

—

MCS = 0

MCS = 1

—

1/f^X

2 × 1/fX

1/f^X

(200 ns)

(51.2 µs)

(200 ns)

1/fX

2 × 1/fX

1/fX

2 × 1/fX

(200 ns)

(400 ns)

(51.2 µs)

(102.4 µs)

(200 ns)

(400 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(400 ns)

(800 ns)

(102.4 µs)

(204.8 µs)

(400 ns)

(800 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(800 ns)

(1.6 µs)

(204.8 µs)

(409.6 µs)

(800 ns)

(1.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(1.6 µs)

(3.2 µs)

(409.6 µs)

(819.2 µs)

(1.6 µs)

(3.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(3.2 µs)

(6.4 µs)

(819.2 µs)

(1.64 ms)

(3.2 µs)

(6.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(6.4 µs)

(12.8 µs)

(1.64 ms)

(3.28 ms)

(6.4 µs)

(12.8 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(12.8 µs)

(25.6 µs)

(3.28 ms)

(6.55 ms)

(12.8 µs)

(25.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(25.6 µs)

(51.2 µs)

(6.55 ms)

(13.1 ms)

(25.6 µs)

(51.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(51.2 µs)

(102.4 µs)

(13.1 ms)

(26.2 ms)

(51.2 µs)

(102.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

× 1/fX

(102.4 µs)

(204.8 µs)

(26.2 ms)

(52.4 ms)

(102.4 µs)

(204.8 µs)

× 1/fX

(409.6 µs)

(819.2 µs)

(104.9 ms)

(209.7 ms)

(409.6 µs)

(819.2 µs)

Remarks 1. f^X

: Main system clock oscillation frequency

2. MCS : Oscillation mode selection register (OSMS) bit 0

3. Values in parentheses when operated at f^X= 5.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(2) External event counter

The number of pulses of an externally input signal can be measured.

(3) Square-wave output

A square wave with any selected frequency can be output.

Table 6-3. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges

Minimum pulse width

MCS = 1 MCS = 0

Maximum pulse width

MCS = 1 MCS = 0

Resolution

MCS = 0

MCS = 1

—

1/f^X

2 × 1/fX

(51.2 µs)

1/f^X

—

(200 ns)

1/fX

2 × 1/fX

(400 ns)

2 × 1/fX

(51.2 µs)

2 × 1/fX

1/fX

2 × 1/fX

(400 ns)

(200 ns)

(102.4 µs)

(200 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(400 ns)

(800 ns)

(102.4 µs)

(204.8 µs)

(400 ns)

(800 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(800 ns)

(1.6 µs)

(204.8 µs)

(409.6 µs)

(800 ns)

(1.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(1.6 µs)

(3.2 µs)

(409.6 µs)

(819.2 µs)

(1.6 µs)

(3.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(3.2 µs)

(6.4 µs)

(819.2 µs)

(1.64 ms)

(3.2 µs)

(6.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(6.4 µs)

(12.8 µs)

(1.64 ms)

(3.28 ms)

(6.4 µs)

(12.8 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(12.8 µs)

(25.6 µs)

(3.28 ms)

(6.55 ms)

(12.8 µs)

(25.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(25.6 µs)

(51.2 µs)

(6.55 ms)

(13.1 ms)

(25.6 µs)

(51.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(51.2 µs)

(102.4 µs)

(13.1 ms)

(26.2 ms)

(51.2 µs)

(102.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

× 1/fX

(102.4 µs)

(204.8 µs)

(26.2 ms)

(52.4 ms)

(102.4 µs)

(204.8 µs)

× 1/fX

(409.6 µs)

(819.2 µs)

(104.9 ms)

(209.7 ms)

(409.6 µs)

(819.2 µs)

Remarks 1. f^X

: Main system clock oscillation frequency

2. MCS : Oscillation mode selection register (OSMS) bit 0

3. Values in parentheses when operated at f^X= 5.0 MHz.

(4) PWM Output

TM5 and TM6 can generate 8-bit resolution PWM output.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.2 8-Bit Timer/Event Counters 5 and 6 Configurations

The 8-bit timer/event counters 5 and 6 consist of the following hardware.

Table 6-4. 8-Bit Timer/Event Counters 5 and 6 Configurations

Item

Timer register

Configuration

8 bits × 2 (TM5, TM6)

Compare register: 8 bits × 2 (CR50, CR60)

Timer output

Control register

2 (TO5, TO6)

Timer clock select register 5 and 6 (TCL5, TCL6)

8-bit timer mode control register 5 and 6 (TMC5, TMC6)

Port mode register 10 (PM10)

Figure 6-1. 8-Bit Timer/Event Counters 5 and 6 Block Diagram

Internal Bus

8-Bit Compare Register

(CRn0)

Match

INTTMn

2f^xx-fxx/2⁹

Output Control

Circuit^Note

TO5/P100/TI5,

TO6/P101/TI6

8-Bit Timer Register n

(TMn)

OVF

fxx/2¹¹

TI5/P100/TO5,

TI6/P101/TO6

Clear

Selector

TMC

TCL TCL TCL TCL

TCEn

LVSn LVRn

TOEn

Timer Clock

Select Register n

8-Bit Timer Mode

Control Register n

Internal Bus

Note Refer to Figures 6-2 for details of configurations of 8-bit timer/event counters 5 and 6 output control circuits.

Remark n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit

TMCn1

TMCn6

RESET

LVRn

LVSn

TO5/P100/TI5,

TO6/P101/TI6

TMCn1

INV

PM100,

PM101^Note

P100, P101

Output Latch

TMCn6

INTTMn

PWM Output Circuit

Timer Output F/F2

TCEn

INTTMn

OVFn

Level

Invert

TOEn

Note PM100 : Bit 0 of port mode register 10 (PM10)

PM101 : Bit 1 of PM10

Remarks 1. The section in the broken line is an output control circuit.

2. n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(1) Compare registers 50 and 60 (CR50, CR60)

These are 8-bit registers to compare the value set to CR50 to the 8-bit timer register 5 (TM5) count value,

and the value set to CR60 to the 8-bit timer register 6 (TM6) count value, and, if they match, generate an

interrupt request (INTTM5 and INTTM6, respectively).

CR50 and CR60 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit

memory manipulation instruction. The 00H to FFH values can be set.

RESET input sets CR50 and CR60 to 00H.

Caution When using the PWM mode, please set the CRn0 value before setting TMCn (n=5, 6) to the

PWM mode.

(2) 8-bit timer registers 5 and 6 (TM5, TM6)

These are 8-bit registers to count count pulses.

TM5 and TM6 are read with an 8-bit memory manipulation instruction.

RESET input sets TM5 and TM6 to 00H.

6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers

The following three types of registers are used to control the 8-bit timer/event counter 5 and 6.

• Timer clock select register 5 and 6 (TCL5, TCL6)

• 8-bit timer mode control register 5 and 6 (TMC5, TMC6)

• Port mode register 10 (PM10)

(1) Timer clock select register 5 (TCL5)

This register sets count clocks of 8-bit timer register 5.

TCL5 is set with an 8-bit memory manipulation instruction.

RESET input sets TCL5 to 00H.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Figure 6-3. Timer Clock Select Register 5 Format

Address

FF52H

After Reset

00H

R/W

Symbol

TCL5

TCL53 TCL52 TCL51 TCL50

8-Bit Timer Register 5 Count Clock Selection

MCS=1

TCL53 TCL52 TCL51 TCL50

MCS=0

TI5 falling edge^Note

TI5 rising edge^Note

2f^XX

Setting prohibited

(5.0 MHz)

f^XX

fX/2

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

(4.9 kHz)

(1.2 kHz)

f^XX/2

fX/2 (2.5 MHz)

fX/2²(1.25 MHz)

fX/2³(625 kHz)

fX/2⁴(313 kHz)

fX/2⁵(156 kHz)

fX/2⁶(78.1 kHz)

fX/2⁷(39.1 kHz)

fX/2⁸(19.5 kHz)

fX/2⁹(9.8 kHz)

fX/2¹¹(2.4 kHz)

fX/2²

fX/2³

fX/2⁴

fX/2⁵

fX/2⁶

fX/2⁷

fX/2⁸

fX/2⁹

fX/2¹⁰

fX/2¹²

f^XX/2²

f^XX/2³

f^XX/2⁴

f^XX/2⁵

f^XX/2⁶

f^XX/2⁷

f^XX/2⁸

fXX/2⁹

f^XX/2¹¹

Other than above

Setting prohibited

Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external

source.

Caution When rewriting TCL5 to other data, stop the timer operation beforehand.

Remarks 1. f^XX

2. f^X

: Main system clock frequency (fX or fX/2)

: Main system clock oscillation frequency

3. TI5 : 8-bit timer register 5 input pin

4. MCS : Oscillation mode selection register (OSMS) bit 0

5. Values in parentheses when operated at f^X= 5.0 MHz

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(2) Timer clock select register 6 (TCL6)

This register sets count clocks of 8-bit timer register 6.

TCL6 is set with an 8-bit memory manipulation instruction.

RESET input sets TCL6 to 00H.

Figure 6-4. Timer Clock Select Register 6 Format

Address

FF56H

After Reset

00H

Symbol

TCL6

TCL63 TCL62 TCL61 TCL60

8-bit Timer Register 6 Count Clock Selection

MCS=1

TCL63 TCL62 TCL61 TCL60

MCS=0

TI6 falling edge^Note

TI6 rising edge^Note

2f^XX

Setting prohibited

(5.0 MHz)

(2.5 MHz)

fXX

(5.0 MHz)

fX/2 (2.5 MHz)

fX/2²(1.25 MHz)

fX/2³(625 kHz)

fX/2⁴(313 kHz)

fX/2⁵(156 kHz)

fX/2⁶(78.1 kHz)

fX/2⁷(39.1 kHz)

fX/2⁸(19.5 kHz)

fX/2⁹(9.8 kHz)

fX/2¹¹(2.4 kHz)

fX/2

f^XX/2

fXX/2²

fXX/2³

f^XX/2⁴

f^XX/2⁵

fXX/2⁶

fXX/2⁷

fX/2²

fX/2³

fX/2⁴

fX/2⁵

fX/2⁶

fX/2⁷

fX/2⁸

fX/2⁹

fX/2¹⁰

fX/2¹²

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

(4.9 kHz)

(1.2 kHz)

f^XX/2⁸

fXX/2⁹

fXX/2¹¹

Other than above

Setting prohibited

Note When clock is input from the external, timer output (PWM output) cannot be used.

Caution When rewriting TCL6 to other data, stop the timer operation beforehand.

Remarks 1. f^XX

2. f^X

: Main system clock frequency (fX or fX/2)

: Main system clock oscillation frequency

3. TI6 : 8-bit timer register 6 input pin

4. MCS : Oscillation mode selection register (OSMS) bit 0

5. Values in parentheses when operated at f^X= 5.0 MHz

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(3) 8-bit timer mode control register 5 (TMC5)

This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register

5 and controls operation of 8-bit timer/event counter 5 output control circuit.

It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion

enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/

disabling.

TMC5 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC5 to 00H.

Figure 6-5. 8-Bit Timer Mode Control Register 5 Format

Address

FF53H

After Reset

00H

R/W

Symbol

TMC5

TCE5 TMC56

LVS5 LVR5 TMC51 TOE5

TOE5

8-Bit Timer/Event Counter 5 Output Control

Output disabled (Port mode)

Output enabled

In PWM Mode

In Other Modes

TMC51

Active level selection Timer output F/F1 control

Active high

Active low

Inversion operation disabled

Inversion operation enabled

8-Bit Timer/Event Counter 5 Timer

Output F/F1 Status Setting

LVS5 LVR5

No change

Timer output F/F1 reset (0)

Timer output F/F1 set (1)

Setting prohibited

TMC56 8-Bit Timer/Event Counter 5 Operating Mode Selection

Clear & start mode on match of TM5 and CR50

PWM mode (free-running)

TCE5

8-Bit Timer Register 5 Operation Control

Operation stop (TM5 clear to 0)

Operation enable

Cautions 1. Timer operation must be stopped before setting TMC5.

2. If LVS5 and LVR5 are read after data are set, they will be 0.

3. Set 0 to the bits 4 and 5.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(4) 8-bit timer mode control register 6 (TMC6)

This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register

6 and controls operation of 8-bit timer/event counter 6 output control circuit.

It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/

disabling in modes other than PWM mode and 8-bit timer/event counter 6 timer output enabling/disabling.

TMC6 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TMC6 to 00H.

Figure 6-6. 8-Bit Timer Mode Control Register 6 Format

Address

FF57H

After Reset

00H

R/W

Symbol

TMC6

TCE6 TMC66

LVS6 LVR6 TMC61 TOE6

TOE6

8-Bit Timer/Event Counter 6 Output Control

Output disabled (Port mode)

Output enabled

In PWM Mode

In Other Modes

TMC61

Active level selection Timer output F/F1 control

Active high

Active low

Inversion operation disabled

Inversion operation enabled

8-Bit Timer/Event Counter 6 Timer

Output F/F1 Status Setting

LVS6 LVR6

No change

Timer output F/F1 reset (0)

Timer output F/F1 set (1)

Setting prohibited

TMC66 8-Bit Timer/Event Counter 6 Operating Mode Selection

Clear & start mode on match of TM6 and CR60

PWM mode (free-running)

TCE6

8-Bit Timer Register 6 Operation Control

Operation Stop (TM6 clear to 0)

Operation Enable

Cautions 1. Timer operation must be stopped before setting TMC6.

2. If LVS6 and LVR6 are read after data are set, they will be 0.

3. Set 0 to the bits 4 and 5.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(5) Port mode register 10 (PM10)

This register sets port 10 input/output in 1-bit units.

When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101, and output latches

of P100 and P101 to 0.

PM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM10 to FFH.

Figure 6-7. Port Mode Register 10 Format

Address

FF2AH

After Reset

FFH

R/W

Symbol

PM10

PM101 PM100

PM10n P10n Pin Input/Output Mode Selection (n = 0, 1)

Output mode (output buffer ON)

Input mode (output buffer OFF)

Caution Set 1 to the bits 2 to 7.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.4 8-Bit Timer/Event Counters 5 and 6 Operations

6.4.1 Interval timer operations

By setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-8, it can be

operated as an interval timer. The 8-bit timer/event counters 5 and 6 operate as interval timers which generate interrupt

requests repeatedly at intervals of the count value preset to 8-bit compare registers 50 and 60 (CR50 and CR60).

When the count values of the 8-bit timer registers 5 and 6 (TM5 and TM6) match the values set to CR50 and CR60,

counting continues with the TM5 and TM6 values cleared to 0 and the interrupt request signals (INTTM5 and INTTM6)

are generated.

Count clock of TM5 can be selected with the timer clock select register 5 (TCL5). Count clock of TM6 can be

selected with the timer clock select register 6 (TCL6).

Figure 6-8. 8-Bit Timer Mode Control Register Settings for Interval Timer Operation

TCEn TMCn6

LVSn LVRn TMCn1 TOEn

0/1 0/1 0/1 0/1

TMCn

Clear and start on match of TMn and CRn0

TMn operation enable

Remarks 1. 0/1 : Setting 0 or 1 allows another function to be used simultaneously with the interval timer.

See 6.3 (3), (4) for details.

2. n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Figure 6-9. Interval Timer Operation Timings

Count Clock

TMn Count Value

Clear

CRn0

TCEn

Count start

INTTMn

TOn

Interrupt Request

Acknowledge

Interrupt Request

Acknowledge

Interval Time

Remarks 1. Interval time = (N + 1) × t : N = 00H to FFH

2. n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Table 6-5. 8-Bit Timer/Event Counters 5 and 6 Interval Times

Minimum Interval Time

MCS = 1 MCS = 0

TIn input cycle

Maximum Interval Time

Resolution

MCS = 1 MCS = 0

TCLn3 TCLn2 TCLn1 TCLn0

MCS = 1

MCS = 0

2 × TIn input cycle

TIn input edge cycle

2 × TIn input cycle

Setting

1/fX

Setting

2 × 1/fX

(51.2 µs)

Setting

1/fX

prohibited

(200 ns)

prohibited

(200 ns)

1/fX

2 × 1/fX

(400 ns)

2 × 1/fX

1/fX

2 × 1/fX

(400 ns)

(200 ns)

(51.2 µs)

(102.4 µs)

(200 ns)

2 × 1/fX

(400 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(400 ns)

2 × 1/fX

(800 ns)

(102.4 µs)

(204.8 µs)

(800 ns)

2 × 1/fX

(800 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(800 ns)

2 × 1/fX

(1.6 µs)

(204.8 µs)

(409.6 µs)

(1.6 µs)

2 × 1/fX

(1.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(1.6 µs)

2 × 1/fX

(3.2 µs)

(409.6 µs)

(819.2 µs)

(3.2 µs)

2 × 1/fX

(3.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(3.2 µs)

2 × 1/fX

(6.4 µs)

(819.2 µs)

(1.64 ms)

(6.4 µs)

2 × 1/fX

(6.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(6.4 µs)

2 × 1/fX

(12.8 µs)

(1.64 ms)

(3.28 ms)

(12.8 µs)

2 × 1/fX

(12.8 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(12.8 µs)

2 × 1/fX

(25.6 µs)

(3.28 ms)

(6.55 ms)

(25.6 µs)

2 × 1/fX

(25.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(25.6 µs)

2 × 1/fX

(51.2 µs)

(6.55 ms)

(13.1 ms)

(51.2 µs)

2 × 1/fX

(51.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(51.2 µs)

2 × 1/fX

(102.4 µs)

(13.1 ms)

(26.2 ms)

(102.4 µs)

2 × 1/fX

(102.4 µs)

× 1/fX

2 × 1/fX

(102.4 µs)

× 1/fX

(204.8 µs)

(26.2 ms)

(52.4 ms)

(204.8 µs)

× 1/fX

(409.6 µs)

(819.2 µs)

(104.9 ms)

(209.7 ms)

(409.6 µs)

(819.2 µs)

Other than above

Setting prohibited

Remarks 1. f^X

: Main system clock oscillation frequency

2. MCS : Oscillation mode selection register (OSMS) bit 0

3. Values in parentheses when operated at f^X= 5.0 MHz.

4. n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.4.2 External event counter operation

The external event counter counts the number of external clock pulses to be input to the TI5/PI00/TO5 and TI6/

P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6).

TM5 and TM6 are incremented each time the valid edge specified with the timer clock select register 5 and 6 (TCL5

and TCL6) is input. Either the rising or falling edge can be selected.

When the TM5 and TM6 counted values match the values of 8-bit compare registers 50 and 60 (CR50 and CR60),

TM5 and TM6 are cleared to 0 and the interrupt request signals (INTTM5 and INTTM6) are generated.

Figure 6-10. 8-Bit Timer Mode Control Register Setting for External Event Counter Operation

TCEn TMCn6

LVSn LVRn TMCn1 TOEn

TMCn

TOn output disable

Clear and start mode on match of TMn and CRn0

TMn operation enable

Remarks 1. n = 5, 6

2. × : don’t care

Figure 6-11. External Event Counter Operation Timings (with Rising Edge Specification)

Count Clock

TMn Count Value

CRn0

N-1

TCEn

INTTMn

Remarks 1. N = 00H to FFH

2. n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.4.3 Square-wave output

This makes the value set in advance in the 8-bit conveyor register 50, 60 (CR50, CR60) to be the interval. It operates

as a square wave output at the desired frequency.

The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR50

or CR60 by setting bit 1 (TMC51) and bit 0 (TOE5) of 8-bit timer output control register 5 (TMC5), or bit 1 (TMC61)

and bit 0 (TOE6) of 8-bit timer mode control register 6 (TMC6) to 1.

This enables a square wave of any selected frequency to be output.

Figure 6-12. 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation

TCEn TMCn6

LVSn LVRn TMCn1 TOEn

0/1 0/1

TMCn

TOn output enable

Inversion of output on match of TMn and CRn0

Specifies timer output F/F1 initial value

Clear and start mode on match of TMn and CRn0

TMn operation enable

Caution When TI5/P100/TO5 or TI6/P101/TO6 pin is used as the timer output, set 0 to port mode register

(PM100 or PM101) and output latch (P100 or P101).

Remark n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges

Minimum Pulse Width

MCS = 1 MCS = 0

1/f^X

Maximum Pulse Width

Resolution

MCS = 1

—

MCS = 0

MCS = 1

MCS = 0

—

2 × 1/fX

—

1/fX

(200 ns)

(51.2 µs)

(200 ns)

1/fX

2 × 1/fX

1/fX

2 × 1/fX

(200 ns)

(400 ns)

(51.2 µs)

(102.4 µs)

(200 ns)

(400 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(400 ns)

(800 ns)

(102.4 µs)

(204.8 µs)

(400 ns)

(800 ns)

2 × 1/fX

× 1/fX

2 × 1/fX

(800 ns)

(1.6 µs)

(204.8 µs)

(409.6 µs)

(800 ns)

(1.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(1.6 µs)

(3.2 µs)

(409.6 µs)

(819.2 µs)

(1.6 µs)

(3.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(3.2 µs)

(6.4 µs)

(819.2 µs)

(1.64 ms)

(3.2 µs)

(6.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(6.4 µs)

(12.8 µs)

(1.64 ms)

(3.28 ms)

(6.4 µs)

(12.8 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(12.8 µs)

(25.6 µs)

(3.28 ms)

(6.55 ms)

(12.8 µs)

(25.6 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(25.6 µs)

(51.2 µs)

(6.55 ms)

(13.1 ms)

(25.6 µs)

(51.2 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

(51.2 µs)

(102.4 µs)

(13.1 ms)

(26.2 ms)

(51.2 µs)

(102.4 µs)

2 × 1/fX

× 1/fX

2 × 1/fX

× 1/fX

(102.4 µs)

(204.8 µs)

(26.2 ms)

(52.4 ms)

(102.4 µs)

(204.8 µs)

× 1/fX

(409.6 µs)

(819.2 µs)

(104.9 ms)

(209.7 ms)

(409.6 µs)

(819.2 µs)

Remarks 1. f^X

: Main system clock oscillation frequency

2. MCS : Oscillation mode selection register (OSMS) bit 0

3. Values in parentheses when operated at f^X= 5.0 MHz.

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.4.4 PWM output operations

Setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-13 allows operation

as PWM output. Pulses with the duty ratio determined by the values preset in the 8-bit compare registers 50 and

60 (CR50 and CR60) output from the TO5/P100/TI5 or TO6/P101/TI6 pin.

Select the active level of PWM pulse with bit 1 (TMC51) of 8-bit timer mode control register 5 (TMC5) or bit 1

(TMC61) of 8-bit timer mode control register 6 (TMC6).

This PWM pulse has an 8-bit resolution. The pulse can be converted into an analog voltage by integrating it with

an external low-pass filter (LPF). Count clock of 8-bit timer register 5 (TM5) can be selected with timer clock select

(TCL6).

PWM output enable/disable can be selected with bit 0 (TOE5) of TMC5 or bit 0 (TOE6) of TMC6.

Figure 6-13. 8-Bit Timer Mode Control Register Settings for PWM Output Operation

TCEn TMCn6

LVSn LVRn TMCn1 TOEn

0/1

TMCn

TOn output enable

Sets active level

PWM mode

TMn operation enable

Remarks 1. n = 5, 6

2. × : don’t care

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Figure 6-14. PWM Output Operation Timing (Active high setting)

CRn0 Changing

(M→N)

Count Clock

N+1

N+2 N+3 00

TMn Count Value

CRn0

TCEn

INTTMn

OVFn

TOn

Inactive Level

Active Level

Inactive Level

Remark n = 5, 6

Figure 6-15. PWM Output Operation Timings (CRn0 = 00H, active high setting)

CRn0 Changing

(M→00)

Count Clock

TMn Count Value

CRn0

TCEn

INTTMn

OVFn

TOn

Inactive Level

Remark n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting)

Count Clock

TMn Count Value

CRn0

TCEn

INTTMn

OVFn

TOn

Inactive Level

Active Level

Inactive Level

Active Level

Remark n = 5, 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6

(1) Timer start errors

An error with a maximum of one clock may occur concerning the time required for a match signal to be gener-

ated after timer start. This is because 8-bit timer registers 5 and 6 (TM5 and TM6) are started asynchronously

with the count pulse.

Figure 6-18. 8-Bit Timer Registers 5 and 6 Start Timing

Count Pulse

TM5, TM6 Count Value

00H

01H

02H

03H

04H

Timer Start

(2) 8-bit compare register 50 and 60 setting

The 8-bit compare registers 50 and 60 (CR50 and CR60) can be set to 00H.

Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be

carried out.

Figure 6-19. External Event Counter Operation Timing

TI5, TI6, Input

CR50, CR60

00H

TM5, TM6 Count Value

TO5, TO6

00H

Interrupt Request Flag

100

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

(3) Operation after compare register change during timer count operation

If the values after the 8-bit compare registers 50 and 60 (CR50 and CR60) are changed are smaller than those

of 8-bit timer registers 5 and 6 (TM5 and TM6), TM5 and TM6 continue counting, overflow and then restart

counting from 0. Thus, if the value (M) after CR50 and CR60 change is smaller than value (N) before the

change, it is necessary to restart the timer after changing CR50 and CR60.

Figure 6-20. Timing after Compare Register Change during Timer Count Operation

Count Pulse

CR50, CR60

TM5, TM6 Count Value

X-1

FFH

00H

01H

02H

Remark N > X > M

101

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6

[MEMO]

102

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CHAPTER 7 WATCHDOG TIMER

7.1 Watchdog Timer Functions

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register

(WDTM) (The watchdog timer and interval timer cannot be used at the same time).

(1) Watchdog timer mode

An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable

interrupt request or RESET can be generated.

Table 7-1. Watchdog Timer Overrun Detection Times

Runaway Detection Time

MCS = 1

MCS = 0

× 1/fXX

× 1/fX (410 µs)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (104.9 ms)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (52.4 ms)

× 1/fX (209.7 ms)

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz.

103

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CHAPTER 7 WATCHDOG TIMER

(2) Interval timer mode

Interrupt requests are generated at the preset time intervals.

Table 7-2. Interval Times

Interval Time

MCS = 1

CS = 0

× 1/fXX

× 1/fX (410 µs)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (104.9 ms)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (52.4 ms)

× 1/fX (209.7 ms)

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz.

104

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CHAPTER 7 WATCHDOG TIMER

7.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Table 7-3. Watchdog Timer Configuration

Item

Configuration

Timer clock select register 2 (TCL2)

Watchdog timer mode register (WDTM)

Control register

Figure 7-1. Watchdog Timer Block Diagram

Internal Bus

XX/2³

Prescaler

TMMK4

fXX fXX fXX fXX fXX fXX

RUN

2⁴2⁵2⁶2⁷2⁸2⁹2¹¹

INTWDT

Maskable

Interrupt

Request

TMIF4

8-Bit Counter

Control

Circuit

RESET

INTWDT

Non-Maskable

Interrupt

Request

TCL22 TCL21

WDTM3

WDTM4

TCL20

Timer Clock Select Register 2

Watchdog Timer Mode Register

Internal Bus

105

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CHAPTER 7 WATCHDOG TIMER

7.3 Watchdog Timer Control Registers

The following two types of registers are used to control the watchdog timer.

• Timer clock select register 2 (TCL2)

• Watchdog timer mode register (WDTM)

(1) Timer clock select register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set with 8-bit memory manipulation instruction.

RESET input sets TCL2 to 00H.

Remark Besides setting the watchdog timer count clock, TCL2 sets the buzzer output frequency.

106

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CHAPTER 7 WATCHDOG TIMER

Figure 7-2. Timer Clock Select Register 2 Format

After

Reset

Address

FF42H

R/W

Symbol

TCL2

TCL27 TCL26 TCL25

TCL22 TCL21 TCL20

00H

Watchdog Timer Count Clock Selection

MCS=1

TCL22 TCL21 TCL20

MCS=0

f^XX/2³

fXX/2⁴

fXX/2⁵

fXX/2⁶

fXX/2⁷

fXX/2⁸

fXX/2⁹

fXX/2¹¹

f^X/2³(625 kHz)

fX /2⁴(313 kHz)

f^X/2⁵(156 kHz)

f^X/2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^X/2⁸(19.5 kHz)

f^X/2⁹(9.8 kHz)

fX /2¹¹(2.4 kHz)

f^X/2⁴(313 kHz)

fX /2⁵(156 kHz)

fX /2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^X/2⁸(19.5 kHz)

fX /2⁹(9.8 kHz)

f^X/2¹⁰(4.9 kHz)

fX /2¹²(1.2 kHz)

Buzzer Output Frequency Selection

MCS=1

TCL27 TCL26 TCL25

MCS=0

Buzzer output disable

f^XX/2⁹

f^X/2⁹(9.8 kHz)

f^X/2¹⁰(4.9 kHz)

f^X/2¹¹(2.4 kHz)

fX /2¹⁰(4.9 kHz)

f^X/2¹¹(2.4 kHz)

f^X/2¹²(1.2 kHz)

fXX/2¹⁰

fXX/2¹¹

Setting prohibited

Caution 1. When rewriting TCL2 to other data, stop the timer operation beforehand.

2. Set 0 to the bits 3 and 4.

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X

3. ×

: Main system clock oscillation frequency

: Don’t care

4. MCS : Oscillation mode selection register (OSMS) bit 0

5. Values in parentheses when operated at f^X= 5.0 MHz.

107

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CHAPTER 7 WATCHDOG TIMER

(2) Watchdog timer mode register (WDTM)

This register sets the watchdog timer operating mode and enables/disables counting.

WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets WDTM to 00H.

Figure 7-3. Watchdog Timer Mode Register Format

After

Reset

Address

FFF9H

R/W

Symbol

WDTM

RUM

WDTM4 WDTM3

00H

Watchdog Timer Operation Mode

Selection^{Note 1}

WDTM4 WDTM3

Interval timer mode^{Note 2}

(Maskable interrupt occurs upon

generation of an overflow.)

Watchdog timer mode 1

(Non-maskable interrupt occurs upon

generation of an overflow.)

Watchdog timer mode 2

(Reset operation is activated upon

generation of an overflow.)

RUN Watchdog Timer Operation Mode Selection^{Note 3}

Count stop

Counter is cleared and counting starts.

Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.

2. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.

3. Once set to 1, RUN cannot be cleared to 0 by software.

Thus, once counting starts, it can only be stopped by RESET input.

Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is

up to 0.5 % shorter than the time set by timer clock select register 2.

2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (TMIF4)

is 0, and then set WDTM4 to 1.

If WDTM4 is set to 1 when TMIF4 is 1, the non-maskable interrupt request occurs,

regardless of the contents of WDTM3.

Remark ×: Don’t care

108

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CHAPTER 7 WATCHDOG TIMER

7.4 Watchdog Timer Operations

7.4.1 Watchdog timer operation

When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated

to detect any inadvertent program loop.

The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to

2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1

within the set overrun detection time interval. The watchdog timer can be cleared and counting is started by setting

RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable

interrupt request is generated according to the WDTM bit 3 (WDTM3) value.

By setting RUN to 1, the watchdog timer can be cleared.

The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1

before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.

Caution The actual overrun detection time may be shorter than the set time by a maximum of

0.5 %.

Table 7-4. Watchdog Timer Overrun Detection Time

TCL22 TCL21 TCL20 Runaway Detection Time

MCS = 1

MCS = 0

× 1/fXX

× 1/fX (410 µs)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (104.9 ms)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (52.4 ms)

× 1/fX (209.7 ms)

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz.

109

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CHAPTER 7 WATCHDOG TIMER

7.4.2 Interval timer operation

The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of

the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.

A count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL22) of the timer clock select register

2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer.

When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag

(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt

requests, the INTWDT default has the highest priority.

The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) of

WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval

timer mode is not set unless RESET input is applied.

2. The interval time just after setting with WDTM may be shorter than the set time by a maximum

of 0.5 %.

Table 7-5. Interval Timer Interval Time

TCL22 TCL21 TCL20

Interval Time

MCS = 1

MCS = 0

× 1/fXX

× 1/fX (410 µs)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (104.9 ms)

× 1/fX (819 µs)

× 1/fX (1.64 ms)

× 1/fX (3.28 ms)

× 1/fX (6.55 ms)

× 1/fX (13.1 ms)

× 1/fX (26.2 ms)

× 1/fX (52.4 ms)

× 1/fX (209.7 ms)

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz.

110

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CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT

8.1 Clock Output Control Circuit Functions

The clock output control circuit is intended for carrier output during remote controlled transmission and clock output

for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/

P35 pin.

Follow the procedure below to output clock pulses.

(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03)

of TCL0.

(2) Set the P35 output latch to 0.

(3) Set bit 5 (PM35) of port mode register 3 to 0 (set to output mode).

(4) Set bit 7 (CLOE) of timer clock select register 0 to 1.

Caution Clock output cannot be used when setting P35 output latch to 1.

Remark When clock output enable/disable is switched, the clock output control circuit does not output pulses

with small widths (See the portions marked with * in Figure 8-1).

Figure 8-1. Remote Controlled Output Application Example

CLOE

PCL/P35 Pin Output

111

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CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT

8.2 Clock Output Control Circuit Configuration

The clock output control circuit consists of the following hardware.

Table 8-1. Clock Output Control Circuit Configuration

Item

Configuration

Timer clock select register 0 (TCL0)

Port mode register 3 (PM3)

Control register

Figure 8-2. Clock Output Control Circuit Block Diagram

f^XX

fXX /2

f^XX/2²

fXX /2³

fXX /2⁴

fXX /2⁵

fXX /2⁶

fXX /2⁷

Synchronizing

Circuit

PCL/P35

P35

Output Latch

CLOE TCL03 TCL02 TCL01 TCL00

PM35

Port Mode Register 3

Timer Clock Select Register 0

Internal Bus

112

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CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT

8.3 Clock Output Function Control Registers

The following two types of registers are used to control the clock output function.

• Timer clock select register 0 (TCL0)

• Port mode register 3 (PM3)

(1) Timer clock select register 0 (TCL0)

This register sets PCL output clock.

TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets TCL0 to 00H.

Figure 8-3. Timer Clock Select Register 0 Format

After

Reset

Address

FF40H

R/W

Symbol

TCL0

CLOE

TCL03 TCL02 TCL01 TCL00

00H

PCL Output Clock Selection

MCS=1

TCL03 TCL02 TCL01 TCL00

MCS=0

f^XX

f^X

(5.0 MHz)

f^X/2 (2.5 MHz)

f^X/2²(1.25 MHz)

f^X/2³(625 kHz)

f^X/2⁴(313 kHz)

f^X/2⁵(156 kHz)

f^X/2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^X/2⁸(19.5 kHz)

fXX/2

f^X/2 (2.5 MHz)

f^X/2²(1.25 MHz)

f^X/2³(625 kHz)

f^X/2⁴(313 kHz)

f^X/2⁵(156 kHz)

f^X/2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^XX/2²

fXX/2³

fXX/2⁴

fXX/2⁵

fXX/2⁶

fXX/2⁷

Other than above

Setting prohibited

CLOE PCL Output Control

Output disable

Output enable

Cautions 1. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory

manipulation instruction.

2. When rewriting TCL0 to other data, stop the clock operation beforehand.

3. Set 0 to bits 4 to 6.

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X

: Main system clock oscillation frequency

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz.

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CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT

(2) Port mode register 3 (PM3)

This register set port 3 input/output in 1-bit units.

When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0.

PM3 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM3 to FFH.

Figure 8-4. Port Mode Register 3 Format

After

Reset

Address

FF23H

R/W

Symbol

PM3

PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30

FFH

PM3n P3n Pin Input/Output Mode Selection (n=0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

114

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CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT

9.1 Buzzer Output Control Circuit Functions

The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer

frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.

Follow the procedure below to output the buzzer frequency.

(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.

(2) Set the P36 output latch to 0.

(3) Set bit 6 (PM36) of port mode register 3 to 0 (Set to output mode).

Caution Buzzer output cannot be used when setting P36 output latch to 1.

9.2 Buzzer Output Control Circuit Configuration

The buzzer output control circuit consists of the following hardware.

Table 9-1. Buzzer Output Control Circuit Configuration

Item

Configuration

Timer clock select register 2 (TCL2)

Port mode register 3 (PM3)

Control register

Figure 9-1. Buzzer Output Control Circuit Block Diagram

f^XX/2⁹

fXX /2¹⁰

fXX /2¹¹

BUZ/P36

P36

Output Latch

TCL27 TCL26 TCL25

PM36

Port Mode Register 3

Timer Clock Select Register 2

Internal Bus

115

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CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT

9.3 Buzzer Output Function Control Registers

The following two types of registers are used to control the buzzer output function.

• Timer clock select register 2 (TCL2)

• Port mode register 3 (PM3)

(1) Timer clock select register 2 (TCL2)

This register sets the buzzer output frequency.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input sets TCL2 to 00H.

Remark Besides setting the buzzer output frequency, TCL2 sets the watchdog timer count clock.

116

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CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT

Figure 9-2. Timer Clock Select Register 2 Format

After

Reset

Address

FF42H

R/W

Symbol

TCL2

TCL27 TCL26 TCL25

TCL22 TCL21 TCL20

00H

Watchdog Timer Count Clock Selection

MCS=1

TCL22 TCL21 TCL20

MCS=0

f^XX/2³

fXX/2⁴

fXX/2⁵

fXX/2⁶

fXX/2⁷

fXX/2⁸

fXX/2⁹

fXX/2¹¹

f^X/2³(625 kHz)

fX /2⁴(313 kHz)

f^X/2⁵(156 kHz)

f^X/2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^X/2⁸(19.5 kHz)

f^X/2⁹(9.8 kHz)

fX /2¹¹(2.4 kHz)

f^X/2⁴(313 kHz)

fX /2⁵(156 kHz)

fX /2⁶(78.1 kHz)

f^X/2⁷(39.1 kHz)

f^X/2⁸(19.5 kHz)

fX /2⁹(9.8 kHz)

f^X/2¹⁰(4.9 kHz)

fX /2¹²(1.2 kHz)

Buzzer Output Frequency Selection

MCS=1

TCL27 TCL26 TCL25

MCS=0

Buzzer output disable

f^XX/2⁹

f^X/2⁹(9.8 kHz)

f^X/2¹⁰(4.9 kHz)

f^X/2¹¹(2.4 kHz)

fX /2¹⁰(4.9 kHz)

f^X/2¹¹(2.4 kHz)

f^X/2¹²(1.2 kHz)

fXX/2¹⁰

fXX/2¹¹

Setting prohibited

Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand.

2. Set 0 to bits 3 and 4.

Remarks 1. f^XX: Main system clock frequency (fX or fX/2)

2. f^X

3. ×

: Main system clock oscillation frequency

: don’t care

4. MCS : Oscillation mode selection register (OSMS) bit 0

5. Values in parentheses when operated at f^X= 5.0 MHz

117

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CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT

(2) Port mode register 3 (PM3)

This register sets port 3 input/output in 1-bit units.

When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0.

PM3 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM3 to FFH.

Figure 9-3. Port Mode Register 3 Format

After

Reset

Address

FF23H

R/W

Symbol

PM3

PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30

FFH

PM3n P3n Pin Input/Output Mode Selection (n=0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

118

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CHAPTER 10 A/D CONVERTER

10.1 A/D Converter Functions

The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an

8-bit resolution.

The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D

conversion result register (ADCR).

The following two ways are available to start A/D conversion.

(1) Hardware start

Conversion is started by trigger input (INTP3).

(2) Software start

Conversion is started by setting the A/D converter mode register.

Select 1 channel of analog input from ANI0 to ANI7 and perform A/D conversion. As for A/D conversion operations,

when the hardware is started up, the A/D conversion operation stops when A/D conversion is completed, and an

interrupt request (INTAD) is generated. In the case of software start, the A/D conversion operation is repeated. Each

time an A/D conversion operation ends, an interrupt request (INTAD) is generated.

10.2 A/D Converter Configuration

The A/D converter consists of the following hardware.

Table 10-1. A/D Converter Configuration

Item

Configuration

Analog input

Control register

8 Channels (ANI0 to ANI7)

A/D converter mode register (ADM)

A/D converter input select register (ADIS)

External interrupt mode register 1 (INTM1)

Successive approximation register (SAR)

A/D conversion result register (ADCR)

119

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CHAPTER 10 A/D CONVERTER

Figure 10-1. A/D Converter Block Diagram

Internal Bus

A/D Converter Input Select Register

ADIS3

ADIS2

ADIS0

ADIS1

Series Resistor String

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

AV^DD

Sample & Hold Circuit

Note 1

Note 2

Voltage

Comparator

AV^REF

Successive

Approximation

AVSS

Edge

Detector

Control

Circuit

INTP3/P03

INTAD

INTP3

ES40, ES41^{Note 3}

Trigger Enable

A/D Conversion

Result Register

(ADCR)

CS TRG FR1

ADM3 ADM2 ADM1 HSC

FR0

A/D Converter Mode Register

Internal Bus

Notes 1. Selector to select the number of channels to be used for analog input.

2. Selector to select the channel for A/D conversion.

3. External interrupt mode register 1 (INTM1) bits 0 and 1.

120

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CHAPTER 10 A/D CONVERTER

(1) Successive approximation register (SAR)

This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from

the series resistor string and holds the result from the most significant bit (MSB).

When held to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR are transferred

to the A/D conversion results register.

(2) A/D conversion result register (ADCR)

This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result

is loaded from the successive approximation register.

ADCR is read with an 8-bit memory manipulation instruction.

RESET input makes ADCR undefined.

(3) Sample & hold circuit

The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and

sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D

conversion.

(4) Voltage comparator

The voltage comparator compares the analog input to the series resistor string output voltage.

(5) Series resistor string

The series resistor string is connected within AV^REFto AVSS and generates a voltage for comparison with the

analog input.

(6) ANI0 to ANI7 pins

These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter.

Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used

as input/output ports.

Caution Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AV^REF

or lower than AVSS is applied (even if within the absolute maximum ratings), the converted

value of the corresponding channel becomes indeterminate and may adversely affect the

converted values of other channels.

(7) AV^REFpin

This pin inputs the A/D converter reference voltage.

It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV^REF

and AVSS.

The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV^REF

pin to AVSS level in standby mode.

(8) AV^SSpin

This is a GND potential pin of the A/D converter. Keep it at the same potential as the V^SSpin when not using

the A/D converter.

(9) AV^DDpin

This is an A/D converter analog power supply pin. Keep it at the same potential as the V^SSpin when not using

the A/D converter.

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CHAPTER 10 A/D CONVERTER

10.3 A/D Converter Control Registers

The following three types of registers are used to control the A/D converter.

• A/D converter mode register (ADM)

• A/D converter input select register (ADIS)

• External interrupt mode register 1 (INTM1)

(1) A/D converter mode register (ADM)

This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and

external trigger.

ADM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADM to 01H.

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CHAPTER 10 A/D CONVERTER

Figure 10-2. A/D Converter Mode Register Format

After

Reset

Address

FF80H

R/W

Symbol

ADM

CS TRG FR1 FR0 ADM3 ADM2 ADM1 HSC

01H

ADM3 ADM2 ADM1 Analog Input Channel Selection

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

A/D Conversion Time Selection^{Note 1}

FR1 FR0 HSC fX =5.0 MHz Operation

MCS=1

f^X=4.19 MHz Operation

MCS=1

MCS=0

80/f^X(Setting prohibited^{Note 2}

40/fX (Setting prohibited^{Note 2}

50/fX (Setting prohibited^{Note 2}

)

160/f^X(32.0 s)

80/f^X(19.1 s)

160/f^X(38.1 s)

Note 2

80/f^X(Setting prohibited

)

40/f^X(Setting prohibited

)

80/f^X(19.1 s)

Note 2

100/f^X(20.0 s)

50/f^X(Setting prohibited

100/f^X(23.8 s)

100/fX (20.0 s)

200/f^X(40.0 s)

100/f^X(23.8 s)

200/f^X(47.7 s)

Other than above Setting prohibited

TRG External Trigger Selection

No external trigger (software starts)

Conversion started by external trigger (hardware starts)

A/D Conversion Operation Control

Operation stop

Operation start

Notes 1. Set so that the A/D conversion time is 19.1 µs or more.

2. Setting prohibited because A/D conversion time is less than 19.1 µs.

Cautions 1. The following sequence is recommended for power consumption reduction of A/D

converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the

A/D conversion operation, and then execute the HALT or STOP instruction.

2. When restarting the stopped A/D conversion operation, start the A/D conversion

operation after clearing the interrupt request flag (ADIF) to 0.

Remarks 1. f^X

: Main system clock oscillation frequency

2. MCS : Oscillation mode selection register (OSMS) bit 0

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CHAPTER 10 A/D CONVERTER

(2) A/D converter input select register (ADIS)

This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels

or ports. Pins other than those selected as analog input can be used as input/output ports.

ADIS is set with an 8-bit memory manipulation instruction.

RESET input sets ADIS to 00H.

Cautions 1. Set the analog input channel in the following order.

(1) Set the number of analog input channels with ADIS.

(2) Using A/D converter mode register (ADM), select one channel to undergo A/D

conversion from among the channels set for analog input with ADIS.

2. No internal pull-up resistor can be used to the channels set for analog input with ADIS,

irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register L (PUOL).

Figure 10-3. A/D Converter Input Select Register Format

After

Reset

Address

FF84H

R/W

Symbol

ADIS

ADIS3 ADIS2 ADIS1 ADIS0

00H

ADIS3 ADIS2 ADIS1 ADIS0 Number of Analog Input Channel Selection

No analog input channel (P10-P17)

1 channel (ANI0, P11-P17)

2 channel (ANI0, ANI1, P12-P17)

3 channel (ANI0-ANI2, P13-P17)

4 channel (ANI0-ANI3, P14-P17)

5 channel (ANI0-ANI4, P15-P17)

6 channel (ANI0-ANI5, P16, P17)

7 channel (ANI0-ANI6, P17)

8 channel (ANI0-ANI7)

Other than above

Setting prohibited

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CHAPTER 10 A/D CONVERTER

(3) External interrupt mode register 1 (INTM1)

This register sets the valid edge for INTP3.

INTM1 is set with an 8-bit memory manipulation instruction.

RESET input sets INTM1 to 00H.

Figure 10-4. External Interrupt Mode Register 1 Format

After

Reset

Address

FFEDH

R/W

Symbol

INTM1

ES41 ES40

00H

ES41 ES40 INTP3 Valid Edge Selection

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

Caution Set 0 to the bits 2 to 7.

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CHAPTER 10 A/D CONVERTER

10.4 A/D Converter Operations

10.4.1 Basic operations of A/D converter

(1) Set the number of analog input channels with A/D converter input select register (ADIS).

(2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter

mode register (ADM).

(3) Sample the voltage input to the selected analog input channel with the sample & hold circuit.

(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit

holds the input analog voltage until termination of A/D conversion.

(5) Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set at

(1/2) AV^REFby the tap selector.

(6) The voltage difference between the series resistor string voltage tap and the analog input is compared by the

voltage comparater. If the analog input is larger than (1/2) AV^REF, the MSB of the SAR remains set. If it is

smaller than (1/2) AV^REF, the MSB is reset.

(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the

series resistor string voltage tap is selected according to the preset value of bit 7 as described below.

• Bit 7 = 1 : (3/4) AV^REF

• Bit 7 = 0 : (1/4) AVREF

The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as

follows.

• Analog input voltage ≥ Voltage tap : Bit 6 = 1

• Analog input voltage ≤ Voltage tap : Bit 6 = 0

(8) Comparison of this sort continues up to bit 0 of SAR.

(9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the

resultant value is transferred to and latched in the A/D conversion result register (ADCR).

At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.

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CHAPTER 10 A/D CONVERTER

Figure 10-5. A/D Converter Basic Operation

Conversion

Time

Sampling Time

Sampling

A/D Converter

Operation

A/D Conversion

C0H

40H

Conversion

Result

Undefined

80H

SAR

Conversion

Result

ADCR

INTAD

A/D conversion operations are performed continuously until bit 7 (CS) of A/D converter mode register (ADM) is

reset (0) by software.

If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and

if the CS bit is set (1), conversion starts again from the beginning.

After RESET input, the value of ADCR is undefined.

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CHAPTER 10 A/D CONVERTER

10.4.2 Input voltage and conversion results

The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion

result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.

V^IN

AVREF

ADCR = INT (

× 256 + 0.5)

AVREF

256

AVREF

256

(ADCR – 0.5) ×

≤ V^IN< (ADCR + 0.5) ×

Where, INT( ) : Function which returns integer parts of value in parentheses.

V^IN: Analog input voltage

AV^REF: AVREF pin voltage

ADCR : Value of A/D conversion result register (ADCR)

Figure 10-6 shows the relation between the analog input voltage and the A/D conversion result.

Figure 10-6. Relations between Analog Input Voltage and A/D Conversion Result

255

254

A/D Conversion

Results

(ADCR)

253

507 254 509 255 511

512 256 512 256 512

512 256 512 256 512 256

Input Voltage/AV^REF

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CHAPTER 10 A/D CONVERTER

10.4.3 A/D converter operating mode

Using the A/D converter input select register (ADIS) and the A/D converter mode register (ADM), select one

channel for the analog input from ANI0 to ANI7 and start A/D conversion.

The following two ways are available to start A/D conversion.

• Hardware start: Conversion is started by trigger input (INTP3).

• Software start: Conversion is started by setting ADM.

The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal

(INTAD) is simultaneously generated.

(1) A/D conversion by hardware start

When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby

state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied

to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.

Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register

(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started

and terminated, another operation is not started until a new external trigger signal is input.

If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D

conversion operation and waits for a new external trigger signal to be input. When the external trigger input

signal is reinput, A/D conversion is carried out from the beginning.

If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops

immediately.

Figure 10-7. A/D Conversion by Hardware Start

INTP3

ADM Rewrite

CS=1, TRG=1

ADM Rewrite

CS=1, TRG=1

Standby

State

Standby

State

Standby

State

A/D Conversion

ANIn

ANIm

ADCR

INTAD

ANIn

Remarks 1. n = 0, 1, ... , 7

2. m = 0, 1, ... , 7

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CHAPTER 10 A/D CONVERTER

(2) A/D conversion operation in software start

When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the

A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to

ADM3) of ADM.

Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register

(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started

and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation con-

tinues repeatedly until new data is written to ADM.

If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D

conversion operation and starts A/D conversion on the newly written data.

If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops im-

mediately.

Figure 10-8. A/D Conversion by Software Start

Conversion Start

CS=1, TRG=0

ADM Rewrite

CS=1, TRG=0

ADM Rewrite

CS=0, TRG=0

A/D Conversion

ANIn

ANIm

Conversion suspended

Conversion results are

not stored

Stop

ADCR

INTAD

ANIn

ANIm

Remarks 1. n = 0, 1, ... , 7

2. m = 0, 1, ... , 7

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CHAPTER 10 A/D CONVERTER

10.5 A/D Converter Cautions

(1) Power consumption in standby mode

The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode. As a

current still flows in the AV^REFpin at this time, this current must be cut in order to minimize the overall system

power dissipation. In Figure 10-9, the power dissipation can be reduced by outputting a low-level signal to

the output port in standby mode. However, there is no precision to the actual AV^REFvoltage, and therefore

the conversion values themselves lack precision and can only be used for relative comparison.

Figure 10-9. Example of Method of Reducing Current Dissipation in Standby Mode

VDD

Output Port

µ PD78082

AVREF

AVREF = VDD

Series Resistor String

AVSS

(2) Input range of ANI0 to ANI7

The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above

AV^REFor below AVSS is input (even if within the absolute maximum rating range), the conversion value for that

channel will be indeterminate. The conversion values of the other channels may also be affected.

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CHAPTER 10 A/D CONVERTER

(3) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid to noise on pins AV^REFand ANI0 to ANI7. Since

the effect increases in proportion to the output impedance of the analog input source, it is recommended that

a capacitor be connected externally as shown in Figure 10-10 in order to reduce noise.

Figure 10-10. Analog Input Pin Disposition

If there is possibility that noise whose

level is AV^REFor higher or AVSS or lower may enter,

clamp with a diode with a small VF (0.3 V or less).

Reference

AVREF

Voltage Input

ANI0-ANI7

V^DD

C=100-1000 pF

VDD

AVDD

AVSS

VSS

(4) Pins ANI0/P10 to ANI7/P17

The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. When A/D conversion

is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while

conversion is in progress, as this may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected

A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins

adjacent to the pin undergoing A/D conversion.

(5) AV^REFpin input impedance

A series resistor string of approximately 10 kΩ is connected between the AV^REFpin and the AVSS pin.

Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection

to the series resistor string between the AV^REFpin and the AVSS pin, and there will be a large reference voltage

error.

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CHAPTER 10 A/D CONVERTER

(6) Interrupt request flag (ADIF)

The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.

Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the

A/D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite, and

when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion

for the post-change analog input has not ended.

When the A/D conversion is stopped and then resumed, clear the ADIF before it is resumed.

Figure 10-11. A/D Conversion End Interrupt Request Generation Timing

ADM Rewrite

ADIF is set but ANIm

(Start of ANIm Conversion)

conversion has not ended

ADM Rewrite

(Start of ANIn Conversion)

A/D Conversion

ANIn

ANIm

ANIn

ANIm

ADCR

INTAD

ANIn

ANIm

(7) AV^DDpin

The AV^DDpin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to

ANI7/P17.

Therefore, be sure to apply the same voltage as V^DDto this pin shown in the following figure even when the

application circuit is designed so as to switch to a backup battery.

Figure 10-12. Handling of AV^DDPin

AV^REF

VDD

AVDD

Main

power

supply

Capacitor

for back-up

AVSS

VSS

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CHAPTER 10 A/D CONVERTER

[MEMO]

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.1 Serial Interface Channel 2 Functions

Serial interface channel 2 has the following three modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

• 3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial transfer is not carried out to reduce power consumption.

(2) Asynchronous serial interface (UART) mode

In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is

possible.

A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud

rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.

The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.

(3) 3-wire serial I/O mode (MSB-first/LSB-first switchable)

In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines

(SI2, SO2).

In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer

processing speed.

Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection

to devices using either as the start bit.

The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which

incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K

series, etc.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.2 Serial Interface Channel 2 Configuration

Serial interface channel 2 consists of the following hardware.

Table 11-1. Serial Interface Channel 2 Configuration

Item

Configuration

Transmit shift register (TXS)

Receive shift register (RXS)

Receive buffer register (RXB)

Control register

Serial operating mode register 2 (CSIM2)

Asynchronous serial interface mode register (ASIM)

Asynchronous serial interface status register (ASIS)

Baud rate generator control register (BRGC)

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

Figure 11-1. Serial Interface Channel 2 Block Diagram

★

Internal Bus

Asynchronous

Serial Interface

Mode Register

Asynchronous

Serial Interface

Status Register

Direction

Control Circuit

Receive Buffer

PE FE OVE

TXE RXE PS1 PS0 CL

SL ISRM SCK

(RXB/SIO2)

Transmit Shift

(TXS/SIO2)

Direction

Control Circuit

Receive Shift

RxD/SI2/

P70

TxD/SO2/

P71

PM71

SCK Output

Control Circuit

INTSER

Reception

Control

Circuit

Transmission

Control

Circuit

INTSR/INTCSI2

ISRM

INTST

PM72

ASCK/

SCK2/P72

Baud Rate Generator^Note

fxx-fxx/2¹⁰

SCK

CSIE2

CSCK

TXE

RXE

CSIM

CSIE2

CSCK

MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0

Serial Operating

Mode Register 2

Baud Rate Generator

Control Register

Internal Bus

Note See Figure 11-2 for the baud rate generator configuration.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

Figure 11-2. Baud Rate Generator Block Diagram

CSIE2

TXE

Start Bit

Sampling Clock

5-Bit

Counter

ASCK/SCK2/P72

fxx-fxx/2¹⁰

Transmit

Clock

1/2

Selector

Match

TPS0-TPS3

SCK

MDL0-MDL3

CSCK

Decoder

Receive

Clock

Match

1/2

5-Bit

Counter

RXE

Start Bit Detection

TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

Baud Rate Generator

Control Register

Internal Bus

138

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(1) Transmit shift register (TXS)

This register is used to set the transmit data. The data written in TXS is transmitted as serial data.

If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.

Writing data to TXS starts the transmit operation.

TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.

TXS value is FFH after RESET input.

Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register

(RXB) are allocated to the same address, and when a read is performed, the value of RXB

is read.

(2) Receive shift register (RXS)

This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is

received, the receive data is transferred to the receive buffer register (RXB).

RXS cannot be directly manipulated by a program.

(3) Receive buffer register (RXB)

This register holds receive data. Each time one byte of data is received, new receive data is transferred from

the receive shift register (RXS).

If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of

RXB is always set to 0.

RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.

RXB value is FFH after RESET input.

Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write

is performed, the value is written to TXS.

(4) Transmission control circuit

This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data

written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial

interface mode register (ASIM).

(5) Reception control circuit

This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface

mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an

error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with

the error contents.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.3 Serial Interface Channel 2 Control Registers

Serial interface channel 2 is controlled by the following four registers.

• Serial Operating Mode Register 2 (CSIM2)

• Asynchronous Serial Interface Mode Register (ASIM)

• Asynchronous Serial Interface Status Register (ASIS)

• Baud Rate Generator Control Register (BRGC)

(1) Serial operating mode register 2 (CSIM2)

This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.

CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM2 to 00H.

Figure 11-3. Serial Operating Mode Register 2 Format

Symbol

Address After Reset R/W

FF72H 00H R/W

CSIM

CSIM2 CSIE2

CSCK

CSCK Clock Selection in 3-wire Serial I/O Mode

Input clock from off-chip to SCK2 pin

Dedicated baud rate generator output

CSIM22 First Bit Specification

MSB

LSB

CSIE2 Operation Control in 3-wire Serial I/O Mode

Operation stopped

Operation enabled

Cautions 1. Set 0 to the bits 0 and 3 to 6.

2. When UART mode is selected, CSIM2 should be set to 00H.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(2) Asynchronous serial interface mode register (ASIM)

This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.

ASIM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIM to 00H.

Figure 11-4. Asynchronous Serial Interface Mode Register Format

Symbol

Address After Reset R/W

FF70H 00H R/W

ASIM TXE RXE PS1 PS0

SL ISRM SCK

SCK Clock Selection in Asynchronous Serial Interface

Mode

Input clock from off-chip to ASCK pin

Dedicated baud rate generator output^Note

ISRM Control of Reception Completion Interrupt in Case

of Error Generation

Reception completion interrupt generated in case

of error generation

Reception completion interrupt not generated in

case of error generation

Transmit Data Stop Bit Length Specification

1 bit

2 bits

Character Length Specification

7 bits

8 bits

PS1

PS0 Parity Bit Specification

No Parity

0 parity always added in transmission

No parity test in reception (parity error not

generated)

Odd parity

Even parity

RXE Receive Operation Control

Receive operation stopped

Receive operation enabled

TXE Transmit Operation Control

Transmit operation stopped

Transmit operation enabled

Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as

an input/output port.

Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.

2. The serial transmit/receive operation must be stopped before changing the operating

mode.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

Table 11-2. Serial Interface Channel 2 Operating Mode Settings

(1) Operation Stop Mode

ASIM

CSIM2

P71 PM72

PM70 P70 PM71 P72 Start Shift

P72/SCK2

/ASCK Pin

Functions

P70/SI2

/RxD Pin /TxD Pin

Functions Functions

P71/SO2

Bit

Clock

TXE RXE SCK CSIE2

CSCK

CSIM22

x^Note1x^Note1x^Note1

x^Note1

x^Note1x^Note1

—

P70

P71

P72

Other than above

Setting prohibited

(2) 3-wire Serial I/O Mode

ASIM

CSIM2

P71 PM72

PM70 P70 PM71

P72 Start Shift

Bit Clock

P72/SCK2

/ASCK Pin

Functions

P70/SI2

/RxD Pin /TxD Pin

Functions Functions

P71/SO2

TXE RXE SCK CSIE2

CSCK

CSIM22

1^Note2x^Note2

MSB External SI2^Note2

clock

SO2

(CMOS

output)

SCK2 input

SCK2 output

SCK2 input

SCK2 output

Internal

clock

LSB External

clock

Internal

clock

Other than above

Setting prohibited

(3) Asynchronous Serial Interface Mode

ASIM

CSIM2

P71 PM72

PM70 P70 PM71 P72 Start Shift

P72/SCK2

/ASCK Pin

Functions

P70/SI2

/RxD Pin /TxD Pin

Functions Functions

P71/SO2

Bit

Clock

TXE RXE SCK CSIE2

CSCK

CSIM22

x^Note1x^Note1

LSB External

clock

TxD

P70

ASCK input

(CMOS

output)

x ^Note1

x ^Note

Internal

clock

P72

x^Note1x ^Note

RxD

P71

External

clock

ASCK input

P72

x ^Notex ^Note

Internal

clock

TxD

(CMOS

output)

External

clock

ASCK input

P72

x ^Note

Internal

clock

Other than above

Setting prohibited

Notes 1. Can be used freely as port function.

2. Can be used as P70 (CMOS input/output) when only transmitter is used.

Remark

: Don’t care

PM×× : Port mode register

P×× : Port output latch

142

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(3) Asynchronous serial interface status register (ASIS)

This is a register which displays the type of error when a reception error is generated in the asynchronous

serial interface mode.

ASIS is read with a 1-bit or 8-bit memory manipulation instruction.

In 3-wire serial I/O mode, the contents of the ASIS are undefined.

RESET input sets ASIS to 00H.

Figure 11-5. Asynchronous Serial Interface Status Register Format

Symbol

ASIS

Address After Reset R/W

FF71H 00H

OVE

OVE Overrun Error Flag

Overrun error not generated

Overrun error generated^{Note 1}

(When next receive operation is completed before

data from receive buffer register is read)

Framing Error Flag

Framing error not generated

Framing error generated^{Note 2}

(When stop bit is not detected)

Parity Error Flag

Parity error not generated

Parity error generated (When transmit data parity

does not match)

Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors

will continue to be generated until RXB is read.

2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface

mode register (ASIM), only single stop bit detection is performed during reception.

143

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(4) Baud rate generator control register (BRGC)

This register sets the serial clock for serial interface channel 2.

BRGC is set with an 8-bit memory manipulation instruction.

RESET input sets BRGC to 00H.

Figure 11-6. Baud Rate Generator Control Register Format (1/2)

Symbol

Address After Reset R/W

FF73H 00H R/W

BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection

f^SCK/16

f^SCK/17

f^SCK/18

f^SCK/19

f^SCK/20

f^SCK/21

f^SCK/22

f^SCK/23

f^SCK/24

f^SCK/25

f^SCK/26

f^SCK/27

f^SCK/28

f^SCK/29

f^SCK/30

—

Note

f^SCK

Note Can only be used in 3-wire serial I/O mode.

Remarks 1. f^SCK: 5-bit counter source clock

2. k

: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

Figure 11-6. Baud Rate Generator Control Register Format (2/2)

5-Bit Counter Source Clock Selection

TPS3 TPS2 TPS1 TPS0

MCS=1

MCS=0

fXX/2

fXX

fXX/2

(4.9 kHz)

(5.0 MHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

fX/2

(2.4 kHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

(4.9 kHz)

fX/2

fXX/2

fX/2

Other than above

Setting prohibited

Caution When a write is performed to BRGC during a communication operation, baud rate generator

output is disrupted and communication cannot be performed normally. Therefore, BRGC

must not be written to during a communication operation.

Remarks 1. f^X

2. f^XX

Main system clock oscillation frequency

Main system clock frequency (fX or fX/2)

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. n Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

5. Values in parentheses when operated at f^X=5.0 MHz

145

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal

scaled from the clock input from the ASCK pin.

(a) Generation of baud rate transmit/receive clock by means of main system clock

The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from

the main system clock is found from the following expression.

fXX

[Baud rate] =

where,

[Hz]

2 × (k+16)

f^X

f^XX

: Main system clock oscillation frequency

: Main system clock frequency (fx or fx/2)

: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

Table 11-3. Relation between Main System Clock and Baud Rate

fx=5.0 MHz

fx=4.19 MHz

Baud

Rate

(bps)

MCS=1

MCS=0

MCS=1

MCS=0

BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)

–

00H

E6H

E0H

D0H

C0H

B0H

A0H

90H

80H

70H

64H

60H

50H

1.73

0.88

1.73

0BH

03H

EBH

DBH

CBH

BBH

ABH

9BH

8BH

7BH

71H

6BH

5BH

1.14

–2.01

1.14

–1.31

1.14

EBH

E3H

DBH

CBH

BBH

ABH

9BH

8BH

7BH

6BH

61H

5BH

—

1.14

–2.01

1.14

–1.31

1.14

—

110

06H

00H

E0H

D0H

C0H

B0H

A0H

90H

80H

74H

70H

60H

0.88

1.73

150

300

600

1200

2400

4800

9600

19200

31250

38400

76800

1.73

★

Remark MCS: Oscillation mode selection register (OSMS) bit 0

146

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin

The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate

generated from the clock input from the ASCK pin is obtained with the following expression.

fASCK

[Baud rate] =

where,

[Hz]

2 × (k+16)

f^ASCK

Frequency of clock input to ASCK pin

Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

Table 11-4. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

Baud Rate (bps)

ASCK Pin Input Frequency

2.4 kHz

110

3.52 kHz

150

4.8 kHz

300

9.6 kHz

600

19.2 kHz

1200

38.4 kHz

2400

76.8 kHz

4800

153.6 kHz

307.2 kHz

614.4 kHz

1000.0 kHz

1228.8 kHz

9600

19200

31250

38400

147

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.4 Serial Interface Channel 2 Operation

Serial interface channel 2 has the following three modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

• 3-wire serial I/O mode

11.4.1 Operation stop mode

In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.

In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal

input/output ports.

(1) Register setting

Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the

asynchronous serial interface mode register (ASIM).

(a) Serial operating mode register 2 (CSIM2)

CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM2 to 00H.

Symbol

Address After Reset R/W

FF72H 00H R/W

CSIM

CSIM2 CSIE2

CSCK

CSIE2 Operation Control in 3-wire Serial I/O Mode

Operation stopped

Operation enabled

Caution Set 0 to the bits 0 and 3 to 6.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(b) Asynchronous serial interface mode register (ASIM)

ASIM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIM to 00H.

Symbol

ASIM TXE RXE PS1 PS0

Address After Reset R/W

FF70H 00H R/W

SL ISRM SCK

RXE Receive Operation Control

Receive operation stopped

Receive operation enabled

TXE Transmit Operation Control

Transmit operation stopped

Transmit operation enabled

149

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.4.2 Asynchronous serial interface (UART) mode

In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.

A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.

In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.

The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.

(1) Register setting

UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial

interface mode register (ASIM), the asynchronous serial interface status register (ASIS), and the baud rate

generator control register (BRGC).

(a) Serial operating mode register 2 (CSIM2)

CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM2 to 00H.

When the UART mode is selected, 00H should be set in CSIM2.

Symbol

Address After Reset R/W

FF72H 00H R/W

CSIM

CSIM2 CSIE2

CSCK

CSCK Clock Selection in 3-wire Serial I/O Mode

Input clock from off-chip to SCK2 pin

Dedicated baud rate generator output

CSIM22 First Bit Specification

MSB

LSB

CSIE2 Operation Control in 3-wire Serial I/O Mode

Operation stopped

Operation enabled

Caution Set 0 to the bits 0 and 3 to 6.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(b) Asynchronous serial interface mode register (ASIM)

ASIM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIM to 00H.

Symbol

Address After Reset R/W

FF70H 00H R/W

ASIM TXE RXE PS1 PS0

SL ISRM SCK

SCK Clock Selection in Asynchronous Serial Interface

Mode

Input clock from off-chip to ASCK pin

Dedicated baud rate generator output^Note

ISRM Control of Reception Completion Interrupt in Case

of Error Generation

Reception completion interrupt request generated

in case of error generation

Reception completion interrupt request not

generated in case of error generation

Transmit Data Stop Bit Length Specification

1 bit

2 bits

Character Length Specification

7 bits

8 bits

PS1

PS0 Parity Bit Specification

No Parity

0 parity always added in transmission

No parity test in reception (parity error not

generated)

Odd parity

Even parity

RXE Receive Operation Control

Receive operation stopped

Receive operation enabled

TXE Transmit Operation Control

Transmit operation stopped

Transmit operation enabled

Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used

as an input/output port.

Caution The serial transmit/receive operation must be stopped before changing the operating

mode.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

ASIS is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIS to 00H.

Symbol

ASIS

Address After Reset R/W

FF71H 00H

OVE

OVE Overrun Error Flag

Overrun error not generated

Overrun error generated^{Note 1}

(When next receive operation is completed before

data from receive buffer register is read)

Framing Error Flag

Framing error not generated

Framing error generated^{Note 2}

(When stop bit is not detected)

Parity Error Flag

Parity error not generated

Parity error generated (When transmit data parity

does not match)

Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun

errors will continue to be generated until RXB is read.

2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial

interface mode register (ASIM), only single stop bit detection is performed during reception.

152

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(d) Baud rate generator control register (BRGC)

BRGC is set with an 8-bit memory manipulation instruction.

RESET input sets BRGC to 00H.

Symbol

BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

Address After Reset R/W

FF73H 00H R/W

MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection

f^SCK/16

f^SCK/17

f^SCK/18

f^SCK/19

f^SCK/20

f^SCK/21

f^SCK/22

f^SCK/23

f^SCK/24

f^SCK/25

f^SCK/26

f^SCK/27

f^SCK/28

f^SCK/29

f^SCK/30

(continued)

Remark

fSCK : 5-bit counter source clock

Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

5-Bit Counter Source Clock Selection

TPS3 TPS2 TPS1 TPS0

MCS=1

MCS=0

fXX/2

fXX

fX/2

(4.9 kHz)

(5.0 MHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

fX/2

(2.4 kHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

(4.9 kHz)

fX/2

fXX/2

fX/2

Other than above

Setting prohibited

Caution When a write is performed to BRGC during a communication operation, baud rate

generator output is disrupted and communication cannot be performed normally.

Therefore, BRGC must not be written to during a communication operation.

Remarks 1. f^X

2. f^XX

Main system clock oscillation frequency

Main system clock frequency (fX or fX/2)

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. n Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

5. Values in parentheses when operated at f^X= 5.0 MHz.

154

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or

a signal scaled from the clock input from the ASCK pin.

(i) Generation of baud rate transmit/receive clock by means of main system clock

The transmit/receive clock is generated by scaling the main system clock. The baud rate generated

from the main system clock is obtained with the following expression.

fXX

[Baud rate] =

where,

[Hz]

2 × (k+16)

f^X

f^XX

: Main system clock oscillation frequency

: Main system clock frequency (fx or fx/2)

: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

Table 11-5. Relation between Main System Clock and Baud Rate

fx=5.0 MHz

fx=4.19 MHz

Baud

Rate

(bps)

MCS=1

MCS=0

MCS=1

MCS=0

BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)

–

00H

E6H

E0H

D0H

C0H

B0H

A0H

90H

80H

70H

64H

60H

50H

1.73

0.88

1.73

0BH

03H

EBH

DBH

CBH

BBH

ABH

9BH

8BH

7BH

71H

6BH

5BH

1.14

–2.01

1.14

–1.31

1.14

EBH

E3H

DBH

CBH

BBH

ABH

9BH

8BH

7BH

6BH

61H

5BH

—

1.14

–2.01

1.14

–1.31

1.14

—

110

06H

00H

E0H

D0H

C0H

B0H

A0H

90H

80H

74H

70H

60H

0.88

1.73

150

300

600

1200

2400

4800

9600

19200

31250

38400

76800

1.73

★

Remark MCS: Oscillation mode selection register (OSMS) bit 0

155

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin

The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate

generated from the clock input from the ASCK pin is obtained with the following expression.

f^ASCK

[Baud rate] =

[Hz]

2 × (k+16)

where,

f^ASCK

Frequency of clock input to ASCK pin

Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

Table 11-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

Baud Rate (bps)

ASCK Pin Input Frequency

2.4 kHz

110

3.52 kHz

150

4.8 kHz

300

9.6 kHz

600

19.2 kHz

1200

38.4 kHz

2400

76.8 kHz

4800

153.6 kHz

307.2 kHz

614.4 kHz

1000.0 kHz

1228.8 kHz

9600

19200

31250

38400

156

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(2) Communication operation

(a) Data format

The transmit/receive data format is as shown in Figure 11-7.

Figure 11-7. Asynchronous Serial Interface Transmit/Receive Data Format

One Data Frame

Start

Bit

Parity

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Character Bit

Stop Bit

1 Data frame is configured from the following bits.

• Start bits.................. 1 bit

• Character bits ......... 7 bits/8 bits

• Parity bits ................ Even parity/odd parity/0 parity/no parity

• Stop bit(s) ............... 1 bit/2 bits

The specification of character bit length, parity selection, and specification of stop bit length for each data

frame is carried out with asynchronous serial interface mode register (ASIM).

When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in

transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is

always “0”.

The serial transfer rate is selected by means of the ASIM and the baud rate generator control register

(BRGC).

If a serial data receive error is generated, the receive error contents can be determined by reading the

status of the asynchronous serial interface status register (ASIS).

157

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(b) Parity types and operation

The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity

bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd

number) error can be detected. With 0 parity and no parity, an error cannot be detected.

(i) Even parity

• Transmission

The number of bits with a value of “1”, including the parity bit, in the transmit data is controlled to

be even.

The value of the parity bit is as follows:

Number of bits with a value of “1” in transmit data is odd: 1

Number of bits with a value of “1” in transmit data is even: 0

• Reception

The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If

it is odd, a parity error occurs.

(ii) Odd parity

• Transmission

Conversely to the situation with even parity, the number of bits with a value of “1”, including the

parity bit, in the transmit data is controlled to be odd. The value of the parity bit is as follows:

Number of bits with a value of “1” in transmit data is odd: 0

Number of bits with a value of “1” in transmit data is even: 1

• Reception

The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If

it is even, a parity error occurs.

(iii) 0 Parity

When transmitting, the parity bit is set to "0" irrespective of the transmit data.

At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective

of whether the parity bit is set to "0" or "1".

(iv) No parity

A parity bit is not added to the transmit data. At reception, data is received assuming that there is

no parity bit. Since there is no parity bit, a parity error is not generated.

158

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit,

parity bit and stop bit(s) are added automatically.

When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when

the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is

generated.

Figure 11-8. Asynchronous Serial Interface Transmission Completion Interrupt Request Timing

(a) Stop bit length: 1

STOP

TxD (Output)

INTST

Parity

START

(b) Stop bit length: 2

TxD (Output)

INTST

Parity

STOP

START

Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be

performed during a transmit operation. If rewriting of the ASIM register is performed

during transmission, subsequent transmit operations may not be possible (the normal

state is restored by RESET input).

It is possible to determine whether transmission is in progress by software by using a

transmission completion interrupt request (INTST) or the interrupt request flag (STIF)

set by the INTST.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(d) Reception

When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation

is enabled and sampling of the RxD pin input is performed.

RxD pin input sampling is performed using the serial clock specified by ASIM.

When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (see Figure 11-2)

starts counting, and at the time when the half time determined by specified baud rate has passed, the

data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start

timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and

data sampling is performed. When character data, a parity bit and one stop bit are detected after the

start bit, reception of one frame of data ends.

When one frame of data has been received, the receive data in the shift register is transferred to the receive

buffer register (RXB), and a reception completion interrupt request (INTSR) is generated.

If an error is generated, the receive data in which the error was generated is still transferred to RXB, and

INTSR is generated.

If the RXE bit is reset (0) during the receive operation, the receive operation is stopped immediately. In

this case, the contents of RXB and ASIS are not changed, and INTSR and INTSER are not generated.

Figure 11-9. Asynchronous Serial Interface Reception Completion Interrupt Request Timing

STOP

RxD (Input)

INTSR

Parity

START

Caution The receive buffer register (RXB) must be read even if a receive error is generated. If

RXB is not read, an overrun error will be generated when the next data is received, and

the receive error state will continue indefinitely.

160

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(e) Receive errors

Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.

When a data reception results error flag is set in the asynchronous serial interface register (ASIS), a

reception error interrupt request (INTSER) is generated.

★

The reception error interrupt request is generated first before the reception completed interrupt request

(INTSR). Receive error causes are shown in Table 11-7.

It is possible to determine what kind of error was generated during reception by reading the contents of

the asynchronous serial interface status register (ASIS) in the reception error interrupt servicing (INTSER)

(see Figures 11-9 and 11-10).

The contents of ASIS are reset (0) by reading the receive buffer register (RXB) or receiving the next data

(if there is an error in the next data, the corresponding error flag is set).

Table 11-7. Receive Error Causes

Receive Errors

Cause

Parity error

Transmission-time parity specification and reception data parity do not match

Stop bit not detected

Framing error

Overrun error

Reception of next data is completed before data is read from receive register buffer

Figure 11-10. Receive Error Timing

★

STOP

RxD (Input)

Parity

START

INTSR

INTSER

Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset (0)

by reading the receive buffer register (RXB) or receiving the next data. To ascertain

the error contents, ASIS must be read before reading RXB.

2. The receive buffer register (RXB) must be read even if a receive error is generated.

If RXB is not read, an overrun error will be generated when the next data is received,

and the receive error state will continue indefinitely.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(3) UART mode cautions

(a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) has been cleared

and a transmit operation has been terminated during transmission, be sure to set 1 in TXE after setting

FFH in the transmit shift register (TXS) before executing the next transmission.

(b) In cases where bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) has been cleared

(0) and a receive operation terminated during reception, enable/disable will differ depending on the timing,

the condition of the receive buffer register (RXB), and generation of the reception completed interrupt

request (INTSR) . The timing is displayed in Figure 11-11.

Figure 11-11 State of the Receive Buffer Register (RXB) when Reception is Interrupted, and Generation/

Non Generation of an Interrupt Request (INTSR)

RxD Pin

Parity

RXB

INTSR

<1>

<3>

<2>

When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.

When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.

When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

11.4.3 3-wire serial I/O mode

The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate

a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc.

Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).

(1) Register setting

3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchro-

nous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).

(a) Serial operating mode register 2 (CSIM2)

CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets CSIM2 to 00H.

Symbol

Address After Reset R/W

FF72H 00H R/W

CSIM

CSIM2 CSIE2

CSCK

CSCK Clock Selection in 3-wire Serial I/O Mode

Input clock from off-chip to SCK2 pin

Dedicated baud rate generator output

CSIM22 First Bit Specification

MSB

LSB

CSIE2 Operation Control in 3-wire Serial I/O Mode

Operation stopped

Operation enabled

Caution Set 0 to the bits 0 and 3 to 6.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(b) Asynchronous serial interface mode register (ASIM)

ASIM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ASIM to 00H.

When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.

Symbol

ASIM TXE RXE PS1 PS0

Address After Reset R/W

FF70H 00H R/W

SL ISRM SCK

SCK Clock Selection in Asynchronous Serial Interface

Mode

Input clock from off-chip to ASCK pin

Dedicated baud rate generator output

ISRM Control of Reception Completion Interrupt in Case

of Error Generation

Reception completion interrupt request generated

in case of error generation

Reception completion interrupt request not

generated in case of error generation

Transmit Data Stop Bit Length Specification

1 bit

2 bits

Character Length Specification

7 bits

8 bits

PS1

PS0 Parity Bit Specification

No Parity

0 parity always added in transmission

No parity test in reception (parity error not

generated)

Odd parity

Even parity

RXE Receive Operation Control

Receive operation stopped

Receive operation enabled

TXE Transmit Operation Control

Transmit operation stopped

Transmit operation enabled

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

★

BRGC is set with an 8-bit memory manipulation instruction.

RESET input sets BRGC to 00H.

Symbol

BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

Address After Reset R/W

FF73H 00H R/W

MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection

f^SCK/16

f^SCK/17

f^SCK/18

f^SCK/19

f^SCK/20

f^SCK/21

f^SCK/22

f^SCK/23

f^SCK/24

f^SCK/25

f^SCK/26

f^SCK/27

f^SCK/28

f^SCK/29

f^SCK/30

f^SCK

—

(continued)

Remark

f^SCK: 5-bit counter source clock

Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

5-Bit Counter Source Clock Selection

TPS3 TPS2 TPS1 TPS0

MCS=1

MCS=0

fXX/2

fXX

fX/2

(4.9 kHz)

(5.0 MHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

fX/2

(2.4 kHz)

(2.5 MHz)

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz)

(4.9 kHz)

fX/2

fXX/2

fX/2

Other than above

Setting prohibited

Caution When a write is performed to BRGC during a communication operation, baud rate

generator output is disrupted and communication cannot be performed normally.

Therefore, BRGC must not be written to during a communication operation.

Remarks 1. f^X

2. f^XX

Main system clock oscillation frequency

Main system clock frequency (fX or fX/2)

3. MCS : Oscillation mode selection register (OSMS) bit 0

4. n Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

5. Values in parentheses when operated at f^X= 5.0 MHz.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below.

BRGC Setting is not required if an external serial clock is used.

(i) When the baud rate generator is not used:

Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.

The serial clock frequency becomes the same as the source clock frequency for the 5-bit counter.

(ii) When the baud rate generator is used:

Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.

The serial clock frequency is calculated by the following formula:

f^XX

Serial clock frequency=

[H^z]

2 x (k + 16)

Remarks 1. f^X

2. f^XX

Main system clock oscillation frequency

Main system clock frequency (fX or fX/2)

Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)

Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)

3. n

4. k

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

(2) Communication operation

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/

received bit by bit in synchronization with the serial clock.

Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in

synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output

from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2)

on the rise of SCK2.

At the end of an 8-bit transfer, the operation of the TXS/SIO2 or RXS stops automatically, and the interrupt

request flag (SRIF) is set.

Figure 11-12. 3-Wire Serial I/O Mode Timing

SCK2

SI2

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SO2

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SRIF

End of Transfer

Transfer Start at the Falling Edge of SCK2

(3) MSB/LSB switching as the start bit

The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.

★

Figure 11-13 shows the configuration of the transmission shift register (TXS/SIO2) and internal bus. As shown

in the figure, MSB/LSB can be read/written in reverse form.

MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register

2 (CSIM2).

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

Figure 11-13. Circuit of Switching in Transfer Bit Order

★

Internal Bus

LSB-first

MSB-first

Read/Write Gate

SO0 Latch

SI2

Transmission Shift Register (TXS/SIO02)

SO2

SCK2

Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains

unchanged.

Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.

(4) Transfer start

Serial transfer is started by setting transfer data to the transmission shift register (TXS/SIO2) when the

following two conditions are satisfied.

•

Serial interface channel 2 operation control bit (CSIE2) =1

Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.

Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start.

Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is

set.

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CHAPTER 11 SERIAL INTERFACE CHANNEL 2

[MEMO]

170

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CHAPTER 12 INTERRUPT FUNCTION

12.1 Interrupt Function Types

The following three types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo

interrupt priority control and is given top priority over all other interrupt requests.

It generates a standby release signal.

One of the non-maskable interrupts is the interrupt request from the Watchdog Timer.

(2) Maskable interrupts

These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group

and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, PR1L).

Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same

priority are simultaneously generated, each interrupts has a predetermined priority (see Table 12-1).

A standby release signal is generated.

Maskable interrupts include three external interrupt requests and eight internal interrupt requests.

(3) Software interrupt

This is a vectored interrupt that occurs when the BRK instruction is executed. It is acknowledged even in a

disabled state. The software interrupt does not undergo interrupt priority control.

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CHAPTER 12 INTERRUPT FUNCTION

12.2 Interrupt Sources and Configuration

There are a total of 13 interrupts, combining non-maskable interrupts, maskable interrupts and software interrupts

(see Table 12-1).

Table 12-1. Interrupt Source List

Note 2

Note 1

Default

Priority

Vector

Table

Address

Basic

Interrupt Source

Trigger

Interrupt

Type

Internal/

External

Configuration

Type

Name

Non-

—

INTWDT

Watchdog timer overflow (with

Internal

0004H

(A)

(B)

(C)

maskable

Maskable

watchdog timer mode 1 selected)

INTWDT

Watchdog timer overflow (with

interval timer mode selected)

INTP1

INTP2

INTP3

INTSER

Pin input edge detection

External

0008H

000AH

000CH

0018H

Serial interface channel 2 UART reception Internal

error generation

(B)

INTSR

INTCSI2

INTST

End of serial interface channel 2

UART reception

001AH

End of serial interface channel 2

3-wire transfer

End of serial interface channel 2

UART transfer

001CH

INTAD

End of A/D converter conversion

0028H

002AH

INTTM5

Generation of 8-bit timer/event

counter 5 match signal

INTTM6

BRK

Generation of 8 bit timer/event

counter 6 match signal

002CH

003EH

Software

—

BRK instruction execution

—

(D)

Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupts. 0 is the

highest priority and 9 is the lowest priority.

2. Basic configuration types (A) to (D) correspond to (A) to (D) of Figure 12-1.

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-1. Basic Configuration of Interrupt Function (1/2)

(A) Internal non-maskable interrupt

Internal Bus

Vector Table

Priority Control

Circuit

Interrupt

Request

Address

Generator

Standby

Release Signal

(B) Internal maskable interrupt

Internal Bus

ISP

Vector Table

Priority Control

Circuit

Address

Interrupt

Request

Generator

Standby

Release Signal

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-1. Basic Configuration of Interrupt Function (2/2)

Internal Bus

External Interrupt

Mode Register

(INTM0, INTM1)

ISP

Vector Table

Address

Generator

Priority Control

Circuit

Interrupt

Request

Edge

Detector

Standby

Release Signal

(D) Software interrupt

Internal Bus

Vector Table

Address

Generator

Interrupt

Request

Priority Control

Circuit

Remark

Interrupt request flag

Interrupt enable flag

ISP : Inservice priority flag

MK : Interrupt mask flag

Priority specify flag

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CHAPTER 12 INTERRUPT FUNCTION

12.3 Interrupt Function Control Registers

The following five types of registers are used to control the interrupt functions.

• Interrupt request flag register (IF0L, IF0H, IF1L)

• Interrupt mask flag register (MK0L, MK0H, MK1L)

• Priority specify flag register (PR0L, PR0H, PR1L)

• External interrupt mode register (INTM0, INTM1)

• Program status word (PSW)

Table 12-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding

to interrupt request sources.

Table 12-2. Various Flags Corresponding to Interrupt Request Sources

Interrupt Source

Interrupt Request Flag

Interrupt Mask Flag

Priority Specify Flag

INTWDT

TMIF4

IF0L

TMMK4

PMK1

MK0L

TMPR4

PPR1

PR0L

INTP1

PIF1

INTP2

PIF2

PMK2

PPR2

INTP3

PIF3

PMK3

PPR3

INTSER

INTSR/INTCSI2

INTST

SERIF

SRIF

STIF

IF0H

IF1L

SERMK

SRMK

STMK

MK0H

MK1L

SERPR

SRPR

STPR

PR0H

PR1L

INTAD

ADIF

TMIF5

TMIF6

ADMK

TMMK5

TMMK6

ADPR

TMPR5

TMPR6

INTTM5

INTTM6

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CHAPTER 12 INTERRUPT FUNCTION

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)

The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction

is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request

or upon application of RESET input.

IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used

as a 16-bit register IF0 use a 16-bit memory manipulation instruction for the setting.

RESET input sets these registers to 00H.

Figure 12-2. Interrupt Request Flag Register Format

After

Reset

Address

FFE0H

R/W

Symbol

IF0L

00H

PIF3 PIF2 PIF1

TMIF4

FFE1H

FFE2H

00H

R/W

IF0H

IF1L

STIF SRIF SERIF

TMIF6 TMIF5 ADIF

× × IF×

Interrupt Request Flag

No interrupt request signal

Interrupt request signal is generated;

Interrupt request state

Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If

a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.

2. Set 0 to the bits 1, 5 to 7 of IF0L and bits 0, 1, 5 to 7 of IF0H and IF1L.

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CHAPTER 12 INTERRUPT FUNCTION

(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)

The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set

standby clear enable/disable.

MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H

are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.

RESET input sets these registers to FFH.

Figure 12-3. Interrupt Mask Flag Register Format

After

Reset

Address

FFE4H

R/W

Symbol

MK0L

FFH

PMK3 PMK2 PMK

TMMK4

FFE5H

FFE6H

FFH

R/W

MK0H

MK1L

STMK SRMK SERMK

TMMK6 TMMK5 ADMK

× × MK

Interrupt Servicing Control

Interrupt servicing enabled

Interrupt servicing disabled

Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value

becomes undefined.

2. Because port 0 has a dual function as the external interrupt request input, when the

output level is changed by specifying the output mode of the port function, an interrupt

request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the

output mode.

3. Set 1 to the bits 1, 5 to 7 of MK0L and bits 0, 1, 5 to 7 of MK0H and MK1L.

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CHAPTER 12 INTERRUPT FUNCTION

(3) Priority specify flag registers (PR0L, PR0H, and PR1L)

The priority specify flag is used to set the corresponding maskable interrupt priority orders.

PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are

used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.

RESET input sets these registers to FFH.

Figure 12-4. Priority Specify Flag Register Format

After

Reset

Address

FFE8H

R/W

Symbol

PR0L

FFH

PPR3 PPR2 PPR1

TMPR4

FFE9H

FFEAH

FFH

R/W

PR0H

PR1L

STPR SRPR SERPR

TMPR6 TMPR5 ADPR

× × PR

Priority Level Selection

High priority level

Low priority level

Cautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1.

2. Set 1 to the bits 1, 5 to 7 of PR0L and bits 0, 1, 5 to 7 of PR0H and PR1L.

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CHAPTER 12 INTERRUPT FUNCTION

(4) External interrupt mode register (INTM0, INTM1)

These registers set the valid edge for INTP1 to INTP3.

INTM0 and INTM1 are set by 8-bit memory manipulation instructions.

RESET input sets these registers to 00H.

Figure 12-5. External Interrupt Mode Register 0 Format

After

Reset

Address

FFECH

R/W

Symbol

INTM0 ES31 ES30 ES21 ES20

00H

ES21 ES20

INTP1 Valid Edge Selection

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES31 ES30

INTP2 Valid Edge Selection

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

Caution Set 0 to the bits 0 to 3.

Figure 12-6. External Interrupt Mode Register 1 Format

After

Reset

Address

FFEDH

R/W

Symbol

INTM1

ES41 ES40

00H

ES41 ES40

INTP3 Valid Edge Selection

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

Caution Set 0 to the bits 2 to 7.

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CHAPTER 12 INTERRUPT FUNCTION

(5) Program status word (PSW)

The program status word is a register to hold the instruction execution result and the current status for interrupt

request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt

processing are mapped.

Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and

dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK

instruction is executed, the contents of PSW is automatically saved to the stack and the IE flag is reset to 0.

If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged

interrupt are transferred to the ISP flag. The contents of PSW are also saved to the stack by the PUSH PSW

instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.

RESET input sets PSW to 02H.

Figure 12-7. Program Status Word Configuration

State after

Reset

02H

PSW

RBS1 AC RBS0

ISP

Used when normal instruction is executed

ISP

Priority of Interrupt Currently Being Received

High-priority interrupt servicing

(low-priority interrupt disable)

Interrupt not acknowledged or low-priority

interrupt request servicing

(all-maskable interrupts enable)

Interrupt Request Acknowledge Enable/Disable

Disable

Enable

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CHAPTER 12 INTERRUPT FUNCTION

12.4 Interrupt Servicing Operations

12.4.1 Non-maskable interrupt request acknowledge operation

A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge

disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.

If a non-maskable interrupt request is acknowledged, the contents of program status word (PSW) and program

counter (PC), in that order, are saved to the stack, the IE flag and ISP flag are reset (0), and the contents of the vector

table are loaded in the PC and branched.

A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program

is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following

RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request

is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt

request is acknowledged after termination of the non-maskable interrupt service program execution.

The flowchart showing the flow from non-maskable interrupt request generation to acknowledgment is shown in

Figure 12-8, the non-maskable interrupt request acknowledge timing is shown in Figure 12-9, and acknowledge

operation in the case where multiple non-maskable interrupt requests are generated, is shown in Figure 12-10.

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-8. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment

Start

WDTM4=1

(with watchdog timer

mode selected)?

Interval timer

Yes

Overflow in WDT?

Yes

WDTM3=0

(with non-maskable

interrupt selected)?

Reset processing

Yes

Interrupt request generation

WDT interrupt servicing?

Interrupt request

held pending

Yes

Interrupt control

Yes

Interrupt

service start

WDTM : Watchdog timer mode register

WDT : Watchdog timer

Figure 12-9. Non-Maskable Interrupt Request Acknowledge Timing

PSW and PC Save, Jump Interrupt Sevicing

to Interrupt Servicing

Program

CPU Instruction

TMIF4

Instruction

Interrupt requests which generate within this space are acknowledged with ↑ timing.

TMIF4 : Watchdog timer interrupt request flag

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation

(a) If a new non-maskable interrupt request is generated during

non-maskable interrupt servicing program execution

Main Routine

NMI Request ➀Execute

NMI Request ➁ Reserve

NMI Request ➀

NMI Request ➁

1 Instruction

Execution

Reserved NMI Request Processing

(b) If two non-maskable interrupt requests are generated during

non-maskable interrupt servicing program execution

Main Routine

NMI Request ➀Execute

NMI

Request ➁

NMI Request ➁Reserve

NMI Request ➂ Reserve

NMI Request ➀

NMI

Request ➂

1 Instruction

Execution

Reserved NMI Request ➁

Processing

Cannot acknowledge NMI Request ➂

(Although multiple NMI requests may

be generated twice or more, they

can only be acknowledged once.)

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CHAPTER 12 INTERRUPT FUNCTION

12.4.2 Maskable interrupt request acknowledge operation

A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt

mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE

flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with

ISP flag reset to 0).

The waiting time from the point when a maskable interrupt request is generated until interrupt processing is

executed is as shown in Table 12-3.

Please refer to Figures 12-12 and 12-13 concerning interrupt request acknowledgement timing.

Table 12-3. Times from Maskable Interrupt Request Generation to Interrupt Service

Note

Minimum Time

7 clocks

Maximum Time

32 clocks

When ××PR=0

When ××PR=1

8 clocks

33 clocks

Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.

Remark

1 clock :

(f^CPU: CPU clock)

fCPU

If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority

with the priority specify flag is acknowledged first. Also, when the same priority is specified with the priority specify

flag, the interrupt request with the higher default priority is acknowledged first.

Any reserved interrupt requests are acknowledged when they become acknowledgeable.

Figure 12-11 shows interrupt request acknowledge algorithms.

If a maskable interrupt request is acknowledged, the contents are saved to the stack in the order of first, program

status word (PSW), then, program counter (PC), then the IE flag is reset (0) and the contents of the acknowledged

interrupt request priority specification flag are transferred to the ISP flag.

Further, the data in the vector table which has been determined with each interrupt request, are loaded into the

PC and branched.

Return from the interrupt is possible with the RETI instruction.

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-11. Interrupt Request Acknowledge Processing Algorithm

Start

× × IF=1?

Yes (Interrupt Request

Generation)

× × MK=0?

Yes

Interrupt request

reserve

Yes (High priority)

× × PR=0?

No (Low Priority)

Do any

of the simultaneously

Any

Simultaneously

Yes

generated ××PR=0 interrupt

requests have a high

priority?

Yes

generated ××PR=0 interrupt

requests?

Interrupt request

reserve

Interrupt request

reserve

Any

Simultaneously

IE=1?

Yes

generated high-priority

interrupt requests?

Yes

Interrupt request

reserve

Interrupt request

reserve

Vectored interrupt

servicing

IE=1?

Interrupt request

reserve

Yes

ISP=1?

Yes

Interrupt request

reserve

Vectored interrupt

servicing

××IF : Interrupt request flag

××MK : Interrupt mask flag

××PR : Priority specify flag

: Flag which controls maskable interrupt request acknowledgment (1 = enable, 0 = disable)

: Flag which indicates the priority of the interrupt currently being processed. (0 = high priority

interrupt being processed, 1= interrupt request not acknowledged, or low priority interrupt

being processed.)

ISP

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time)

6 Clocks

PSW and PC Save,

Jump to Interrupt

Servicing

Interrupt

Servicing

Program

CPU Processing

Instruction

× × IF

(× × PR=1)

8 Clocks

× × IF

(× × PR=0)

7 Clocks

f^CPU

Remark 1 clock :

(f^CPU: CPU clock)

Figure 12-13. Interrupt Request Acknowledge Timing (Maximum Time)

25 Clocks

6 Clocks

PSW and PC Save,

Jump to Interrupt

Servicing

Interrupt

Servicing

Program

CPU Processing

Instruction

Divide Instruction

× × IF

(× × PR=1)

33 Clocks

× × IF

(× × PR=0)

32 Clocks

fCPU

Remark 1 clock :

(f^CPU: CPU clock)

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CHAPTER 12 INTERRUPT FUNCTION

12.4.3 Software interrupt request acknowledge operation

A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.

If a software interrupt request is acknowledged, the contents are saved to the stack in the order of first, program

status word (PSW), then the program counter (PC), then the IE flag is reset (0) and the contents of the vector tables

(003EH, 003FH) are loaded into the PC and branched.

Return from the software interrupt is possible with the RETB instruction.

Caution Do not use the RETI instruction for returning from the software interrupt.

12.4.4 Multiple interrupt servicing

When another interrupt is acknowledged while an interrupt is being processed, this is called multiple interrupt.

Multiple interrupts are not generated unless interrupt request acknowledge is enabled (IE = 1) (non-maskable

interrupts excepted). Also, at the point when an interrupt request is acknowledged, acknowledgment of other interrupt

requests is disabled (IE = 0).Therefore, in order to enable multiple interrupts, it is necessary during interrupt processing

to set the IE flag (1) using the IE instruction, and enable interrupts.

There are cases where multiple requests are not enabled even though interrupts are enabled. However, this is

controlled by the priority of the interrupt. There are two interrupt priorities, the default priority and the programmable

priority. Multiple interrupt control is handled by programmable priority control.

In interrupt enabled condition, when an interrupt request is generated which is the same level, or which has a higher

priority than the interrupt currently being processed, it is acknowledged as a multiple interrupt. When an interrupt

request is generated which has a lower priority than the interrupt currently being processed, it is not acknowledged

as a multiple interrupt.

Interrupt requests which have not been permitted as multiple interrupts because of low priority or because of the

interrupt being disabled, are reserved, and after the current interrupt processing has been completed, they are

acknowledged after executing one of the main processing instructions.

Multiple interrupts are not permitted during non-maskable interrupt processing.

Multiple interrupt enabled interrupt requests are shown in Table 12-4, and an example of multiple interrupts is given

in Figure 12-14 .

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CHAPTER 12 INTERRUPT FUNCTION

Table 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing

Multiple Interrupt

Request

Maskable Interrupt Request

PR=0 PR=1

Non-maskable

Interrupt

Request

IE=1

IE=0

IE=1

IE=0

during processing

Non-maskable interrupt

Maskable interrupt

ISP=0

ISP=1

Software interrupt

Remarks 1. E : Multiple interrupt enable

2. D : Multiple interrupt disable

3. ISP and IE are the flags contained in PSW

ISP=0 : An interrupt with higher priority is being serviced

ISP=1 : An interrupt request is not accepted or an interrupt with lower priority is being

serviced

IE=0 : Interrupt request acknowledge is disabled

IE=1 : Interrupt request acknowledge is enabled

4. PR is a flag contained in PR0L, PR0H, and PR1L

PR=0

PR=1

Higher priority level

Lower priority level

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-14. Multiple Interrupt Example (1/2)

Example 1. Example of when a multiple interrupt is generated twice.

Main Processing

INTxx

INTyy

INTzz

Servicing

IE=0

INTxx

(PR=1)

INTyy

(PR=0)

INTzz

(PR=0)

RETI

Two interrupt requests, INTyy and INTzz, are acknowledged during processing of interrupt INTxx,

and a multiple interrupt is generated. Before each interrupt request is acknowledged, the EI

instruction is always executed and interrupt request acknowledgment enabled.

Example 2. Example of when a multiple interrupt is not generated because of priority control.

Main Processing

INTxx

INTyy

Servicing

IE=0

INTyy

(PR=1)

INTxx

(PR=0)

RETI

1 Instruction

Execution

IE=0

RETI

Interrupt request INTyy, which has been generated during processing of interrupt INTxx, and which

has an interrupt priority that is lower than that of INTxx, is not acknowledged, and a multiple interrupt

is not generated. Interrupt request INTyy is reserved and is acknowledged after execution of one

main processing instructions.

PR = 0 : High priority level

PR = 1 : Low priority level

IE = 0 : Interrupt request acknowledge disabled

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CHAPTER 12 INTERRUPT FUNCTION

Figure 12-14 Multiple Interrupt Example (2/2)

Example 3. Example of when a multiple interrupt is not generated because interrupts are not enabled.

Main Processing

INTxx

Servicing

INTyy

Servicing

IE=0

INTyy

(PR=0)

INTxx

(PR=0)

RETI

IE=0

1 Instruction

Execution

RETI

Because interrupts are not enabled (the EI instruction is not executed) during processing of interrupt

INTxx , interrupt request INTyy is not acknowledged and a multiple interrupt is not generated. Interrupt

request INTyy is reserved and acknowledged after one main processing instruction is implemented.

PR = 0 : High priority level

IE = 0 : Interrupt request acknowledge disabled.

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CHAPTER 12 INTERRUPT FUNCTION

12.4.5 Interrupt request reserve

There are some instructions which, though an interrupt request may be generated while they are being executed,

will reserve the acknowledgment of the request until after execution of the next instruction. These instructions (interrupt

request reserve instructions) are shown below.

• MOV

PSW, #byte

• MOV A, PSW

• MOV

PSW, A

• MOV1 PSW.bit, CY

• MOV1 CY, PSW.bit

• AND1 CY, PSW.bit

• OR1

CY, PSW.bit

• XOR1 CY, PSW.bit

• SET1 PSW.bit

• CLR1 PSW.bit

• RETB

• RETI

• PUSH PSW

• POP

• BT

PSW

PSW.bit, $addr16

• BF

• BTCLR PSW.bit, $addr16

• EI

• DI

• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers

Caution The BRK instruction is not one of the above interrupt request reserve instructions. However in

the case of software interrupts, which are activated by execution of the BRK instruction, the IE

flag is cleared to 0. Therefore, even if a maskable interrupt request is generated during BRK

instruction execution, the interrupt request will not be acknowledged. However, non-maskable

interrupt requests will be acknowledged.

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CHAPTER 12 INTERRUPT FUNCTION

The interrupt request reserve timing is shown in Figure 12-15.

Figure 12-15. Interrupt Request Hold

Save PSW and PC,

Jump to interrupt service

Interrupt service

program

CPU processing

Instruction N

Instruction M

× × IF

Remarks 1. Instruction N: Instruction that holds interrupts requests

2. Instruction M: Instructions other than instruction N

3. The operation of ××IF (interrupt request) is not affected by ××PR (priority level) values.

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CHAPTER 13 STANDBY FUNCTION

13.1 Standby Function and Configuration

13.1.1 Standby function

The standby function is designed to decrease power consumption of the system. The following two modes are

available.

(1) HALT mode

HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.

System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in

the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out

intermittent operations.

(2) STOP mode

STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops

and the whole system stops. CPU current consumption can be considerably decreased.

Data memory low-voltage hold (down to V^DD= 1.8 V) is possible. Thus, the STOP mode is effective to hold

data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt

request, it enables intermittent operations to be carried out.

However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode

is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request.

In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The

input/output port output latch and output buffer statuses are also held.

Cautions 1. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and

execute the STOP instruction.

2. The following sequence is recommended for power consumption reduction of the A/D

converter when the standby function is used: first clear bit 7 (CS) of A/D converter mode

instruction.

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CHAPTER 13 STANDBY FUNCTION

13.1.2 Standby function control register

A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with

the oscillation stabilization time select register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, it takes 2 /fX, not 2 /fX, until the STOP mode is cleared by RESET

input.

Figure 13-1. Oscillation Stabilization Time Select Register Format

After

Reset

Symbol

OSTS

Address

FFFAH

R/W

OSTS2 OSTS1 OSTS0

04H

Selection of Oscillation Stabilization

Time when STOP Mode is Released

OSTS2OSTS1OSTS0

MCS = 1

MCS = 0

2¹²/fxx 2¹²/fx(819ms)

2¹³/fx(1.64 ms)

2¹⁴/fxx 2¹⁴/fx(3.28 ms) 2¹⁵/fx(6.55 ms)

2¹⁵/fxx 2¹⁵/fx(6.55 ms) 2¹⁶/fx(13.1 ms)

2¹⁶/fxx 2¹⁶/fx(13.1 ms) 2¹⁷/fx(26.2 ms)

2¹⁷/fxx 2¹⁷/fx(26.2 ms) 2¹⁸/fx(52.4 ms)

Other than above Setting prohibited

Caution The wait time after STOP mode clear does not include the time (see "a" in the illustration below)

from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by

interrupt generation.

STOP Mode Clear

X1 Pin

Voltage

Waveform

V^SS

Remarks 1. f^XX

2. f^X

:Main system clock frequency (fX or fX/2)

:Main system clock oscillation frequency

3. MCS :Oscillation mode select register (OSMS) bit 0

4. Values in parentheses when operated at f^X= 5.0 MHz

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CHAPTER 13 STANDBY FUNCTION

13.2 Standby Function Operations

13.2.1 HALT mode

(1) HALT mode set and operating status

The HALT mode is set by executing the HALT instruction.

The operating status in the HALT mode is described below.

Table 13-1. HALT Mode Operating Status

Item

HALT Mode Operating Status

Can be oscillated. Supply to the CPU clock is stopped.

Operation stops.

Clock generator

CPU

Port

Status before HALT mode setting is held.

Operable.

8-bit timer/event counter 5, 6

Watchdog timer

A/D converter

Serial interface

External interrupt request

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CHAPTER 13 STANDBY FUNCTION

(2) HALT mode clear

The HALT mode can be cleared with the following three types of sources.

(a) Clear upon unmasked interrupt request

An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled,

vectored interrupt service is carried out. If disabled, the next address instruction is executed.

Figure 13-2. HALT Mode Clear upon Interrupt Generation

HALT

Instruction

Wait

Standby

Release Signal

Operating

Mode

HALT Mode

Operating Mode

Oscillation

Clock

Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby

status is acknowledged.

2. Wait time will be as follows:

• When vectored interrupt service is carried out:

8 to 9 clocks

• When vectored interrupt service is not carried out: 2 to 3 clocks

(b) Clear upon non-maskable interrupt request

The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge

is enabled or disabled.

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CHAPTER 13 STANDBY FUNCTION

As is the case with normal reset operation, a program is executed after branch to the reset vector address.

Figure 13-3. HALT Mode Release by RESET Input

Wait

(2¹⁷/fx : 26.2 ms)

HALT

Instruction

RESET

Signal

Oscillation

Operating

Mode

Reset

Period

Stabilization

Wait Status

Operating

Mode

HALT Mode

Oscillation

stop

Oscillation

Clock

Remarks 1. f^X: main system clock oscillation frequency

2. Values in parentheses when operated at f^x= 5.0 MHz

Table 13-2. Operation after HALT Mode Release

Release Source

Maskable interrupt

request

MK××

PR××

ISP

Operation

–

Next address instruction execution

Interrupt service execution

Next address instruction execution

Interrupt service execution

HALT mode hold

Non-maskable interrupt

request

Interrupt service execution

RESET input

–

Reset processing

Remark ×: Don’t care

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CHAPTER 13 STANDBY FUNCTION

13.2.2 STOP mode

(1) STOP mode set and operating status

The STOP mode is set by executing the STOP instruction.

Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V^DDvia a pull-up resistor

to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode

in a system where an external clock is used for the main system clock.

2. Because the interrupt request signal is used to clear the standby mode, if there is an

interrupt source with the interrupt request flag set and the interrupt mask flag reset, the

standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT

mode immediately after execution of the STOP instruction. After the wait set using the

oscillation stabilization time select register (OSTS), the operating mode is set.

The operating status in the STOP mode is described below.

Table 13-3. STOP Mode Operating Status

Item

STOP Mode Operating Status

Oscillation stops.

Clock generator

CPU

Port

Operation stops.

Status before STOP mode setting is held.

Operable when TI5 and TI6 are selected for the count clock.

Operation stops.

8-bit timer/event counter 5, 6

Watchdog timer

A/D converter

Serial interface

Three-wire serial I/O is operable when the externally input

clock is selected as the serial clock. UART operation stops.

External interrupt request

Operable.

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CHAPTER 13 STANDBY FUNCTION

(2) STOP mode release

The STOP mode can be cleared with the following two types of sources.

(a) Release by unmasked interrupt request

An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled

after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt

acknowledge is disabled, the next address instruction is executed.

Figure 13-4. STOP Mode Release by Interrupt Generation

Wait

STOP

Instruction

(Time set by OSTS)

Standby

Release Signal

Operationg

Mode

Oscillation Stabilization

Wait Status

Operating

Mode

STOP Mode

Oscillation

Oscillation Stop

Oscillation

Clock

Remark The broken line indicates the case when the interrupt request which has cleared the standby

status is acknowledged.

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CHAPTER 13 STANDBY FUNCTION

(b) Release by RESET input

The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried

out.

Figure 13-5. Release by STOP Mode RESET Input

Wait

(2¹⁷/fx : 26.2 ms)

STOP

Instruction

RESET

Signal

Oscillation

Operating

Mode

Reset

Period

Stabilization

Wait Status

Operating

Mode

STOP Mode

Oscillation

Oscillation Stop

Oscillation

Clock

Remarks 1. f^X: main system clock oscillation frequency

2. Values in parentheses when operated at f^X= 5.0 MHz

Table 13-4. Operation after STOP Mode Release

Release Source

MK××

PR××

ISP

Operation

Maskable interrupt request

–

Next address instruction execution

Interrupt service execution

Next address instruction execution

Interrupt service execution

STOP mode hold

RESET input

Reset processing

Remark ×: Don’t care

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CHAPTER 14 RESET FUNCTION

14.1 Reset Function

The following two operations are available to generate the reset signal.

(1) External reset input with RESET pin

(2) Internal reset by watchdog timer overrun time detection

External reset and internal reset have no functional differences. In both cases, program execution starts at the

address at 0000H and 0001H by RESET input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware

is set to the status as shown in Table 14-1. Each pin has high impedance during reset input or during oscillation

stabilization time just after reset clear.

When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse

of oscillation stabilization time (2 /fX). The reset applied by watchdog timer overflow is automatically cleared after

a reset and program execution starts after the lapse of oscillation stabilization time (2 /fX) (see Figure 14-2 to 14-

4).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. Main system clock oscillation stops during reset input.

3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.

However, the port pin becomes high-impedance.

Figure 14-1. Block Diagram of Reset Function

Reset

Signal

RESET

Reset Control Circuit

Over-

flow

Interrupt

Function

Watchdog Timer

Stop

Count Clock

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CHAPTER 14 RESET FUNCTION

Figure 14-2. Timing of Reset Input by RESET Input

Oscillation

Stabilization

Time Wait

Reset Period

(Oscillation

Stop)

Normal Operation

(Reset Processing)

Normal Operation

RESET

Internal

Reset Signal

Delay

Hi-Z

Port Pin

Figure 14-3. Timing of Reset due to Watchdog Timer Overflow

Reset Period

(Oscillation

Stop)

Oscillation

Stabilization

Time Wait

Normal Operation

(Reset Processing)

Normal Operation

Watchdog

Timer

Overflow

Internal

Reset Signal

Hi-Z

Port Pin

Figure 14-4. Timing of Reset Input in STOP Mode by RESET Input

STOP Instruction Execution

Stop Status

(Oscillation

Stop)

Reset Period

(Oscillation

Stop)

Oscillation

Stabilization

Time Wait

Normal Operation

(Reset Processing)

Normal Operation

RESET

Internal

Reset Signal

Delay

Hi-Z

Port Pin

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CHAPTER 14 RESET FUNCTION

Table 14-1. Hardware Status after Reset (1/2)

Hardware

Status after Reset

Note1

Program counter (PC)

Stack pointer (SP)

The contents of reset vector

tables (0000H and 0001H)

are set.

Undefined

02H

Program status word (PSW)

RAM

Note2

Data memory

Undefined

Note2

General register

Undefined

Port 0, Port 1, Port 3, Port 5, Port 7,

Port 10 (P0, P1, P3, P5, P7, P10)

00H

Port (Output latch)

Port mode register (PM0, PM1, PM3, PM5, PM7, PM10)

Pull-up resistor option register (PUOH, PUOL)

Processor clock control register (PCC)

FFH

00H

04H

Oscillation mode selection register (OSMS)

Memory size switching register (IMS)

00H

Note3

Oscillation stabilization time select register (OSTS)

Timer clock selection register 0 (TCL0)

04H

00H

8-bit timer/event counter

5 and 6

Timer register (TM5, TM6)

Compare registers (CR50, CR60)

Clock select register (TCL5, TCL6)

Mode control registers (TMC5, TMC6)

Watchdog timer

Serial Interface

Clock select register (TCL2)

00H

FFH

Mode register (WDTM)

Mode register (CSIM2)

Asynchronous serial interface mode register (ASIM)

Asynchronous serial interface status register (ASIS)

Baud rate generator control register (BRGC)

Transmit shift register (TXS)

Receive buffer register (RXB)

Mode register (ADM)

A/D converter

01H

Undefined

00H

Conversion result register (ADCR)

Input select register (ADIS)

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CHAPTER 14 RESET FUNCTION

Table 14-1. Hardware Status after Reset (2/2)

Hardware

Status after Reset

Interrupt

Request flag register (IF0L, IF0H, IF1L)

Mask flag register (MK0L, MK0H, MK1L)

Priority specify flag register (PR0L, PR0H, PR1L)

External interrupt mode register (INTM0, INTM1)

00H

FFH

00H

Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware

statuses become undefined. All other hardware statuses remains unchanged after reset.

2. The post-reset status is held in the standby mode.

3. The values after reset depend on the product.

µPD78081 : 82H, µPD78082 : 64H, µPD78P083 : 46H

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CHAPTER 15 µPD78P083

The µPD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which

has program write, erasure and rewrite capability.

Differences between the µPD78P083 and mask ROM versions are shown in Table 15-1.

Table 15-1. Differences between the µPD78P083 and Mask ROM Versions

Parameter

Internal ROM type

µPD78P083

One-time PROM/EPROM

24 Kbytes

Mask ROM Versions

Mask ROM

Internal ROM capacity

µPD78081 : 8 Kbytes

µPD78082 : 16 Kbytes

µPD78081 : 256 bytes

µPD78082 : 384 bytes

Disable

Internal high-speed RAM capacity

512 bytes

Note

Internal ROM and internal high-speed

RAM capacity change by internal

memory size switching register (IMS)

IC pin

Enable

Not available

Available

VPP pin

Available

Not available

Electrical specifications

Refer to a data sheet of each product

Note The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512 bytes by the RESET

input.

Caution Noise resistance and noise radiation differs between PROM versions and Mask ROM versions.

If studying the replacement of PROM versions with mask ROM versions in the process of

prototype to volume production, do a thorough evaluation with mask ROM versions with CS

versions (not ES versions).

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CHAPTER 15 µPD78P083

15.1 Memory Size Switching Register

It is possible to specify the internal memory of the µPD78P083 by means of the memory size switching register

(IMS). By setting the IMS, memory mapping can be made to match the memory mapping of the µPD78081 and 78082,

which have different internal memory.

IMS is set with an 8-bit memory manipulation instruction.

RESET input sets IMS to 46H.

Figure 15-1. Memory Size Switching Register Format

After

Reset

Address

FFF0H

R/W

Symbol

46H

IMS RAM2 RAM1 RAM0

ROM3 ROM2 ROM1 ROM0

ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection

8 Kbytes

16 Kbytes

24 Kbytes

Other than above

Setting prohibited

RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selection

512 bytes

384 bytes

256 bytes

Other than above

Setting prohibited

Caution If using mask ROM versions, do not specify any values in the IMS other than when resetting.

The IMS settings to give the same memory map as mask ROM versions are shown in Table 15-2.

Table 15-2. Examples of Memory Size Switching Register Settings

Relevant Mask ROM Version

µPD78081

IMS Setting

82H

µPD78082

64H

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CHAPTER 15 µPD78P083

15.2 PROM Programming

The µPD78P083 incorporate a 24-Kbyte PROM as program memory, respectively. To write a program into

the µPD78P083 PROM, make the device enter the PROM programming mode by setting the levels of the VPP

and RESET pins as specified. For the connection of unused pins, see paragraph (2) “PROM programming

mode” in section 1.5 Pin Configuration (Top View).

Caution Perform program writing only in the 0000H to 5FFFH address range (specify the last address

as 5FFFH.)

The program cannot be correctly written by a PROM programmer which does not have a write

address specification function.

15.2.1 Operating modes

When +5 V or +12.5 V is applied to the V^PPpin and a low-level signal is applied to the RESET pin, the µPD78P083

are set to the PROM programming mode. This is one of the operating modes shown in Table 15-3 below according

to the setting of the CE, OE, and PGM pins.

The PROM contents can be read by setting the read mode.

Table 15-3. PROM Programming Operating Modes

RESET

VPP

VDD

OE PGM

D0-D7

Operating mode

Page data latch

Page write

+12.5 V +6.5 V

Data input

High impedance

Data input

Byte write

Program verify

Program inhibit

Data output

High impedance

Read

+5 V

+5V

Data output

Output disabled

Standby

High impedance

Remark ×: L or H

(1) Read mode

Read mode is set by setting CE to L and OE to L.

(2) Output disable mode

If OE is set to H, data output becomes high impedance and the output disable mode is set.

Therefore, if multiple µPD78P083s are connected to the data bus, data can be read from any one device by

controlling the OE pin.

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CHAPTER 15 µPD78P083

(3) Standby mode

Setting CE to H sets the standby mode.

In this mode, data output becomes high impedance irrespective of the status of OE.

(4) Page data latch mode

Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.

In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.

(5) Page write mode

After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed

by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=H and OE=H. After this, program

verification can be performed by setting CE to L and OE to L.

If programming is not performed by one program pulse, repeated write and verify operations are executed

X times (X ≤ 10).

(6) Byte write mode

A byte write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=L and OE=H.

After this, program verification can be performed by setting OE to L.

If programming is not performed by one program pulse, repeated write and verify operations are executed

X times (X ≤ 10).

(7) Program verify mode

Setting CE to L, PGM to H, and OE to L sets the program verify mode.

After writing is performed, this mode should be used to check whether the data was written correctly.

(8) Program inhibit mode

The program inhibit mode is used when the OE pins, V^PPpins and pins D0 to D7 of multiple µPD78P083s

are connected in parallel and any one of these devices must be written to.

The page write mode or byte write mode described above is used to perform a write. At this time, the write

is not performed on the device which has the PGM pin driven high.

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CHAPTER 15 µPD78P083

15.2.2 PROM write procedure

Figure 15-2. Page Program Mode Flowchart

Start

Address = G

V^DD= 6.5 V, VPP= 12.5 V

Remark:

G = Start address

N = Last address of program

X = 0

Latch

Address = Address + 1

Latch

Address = Address + 1

Latch

Address = Address + 1

Latch

Address = Address + 1

X = X + 1

Yes

X = 10?

0.1-ms program pulse

Fail

Verify 4 Bytes

Pass

Address = N?

Yes

V^DD= 4.5 to 5.5 V, VPP= VDD

Fail

Pass

All bytes verified?

All Pass

End of write

Defective product

209

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CHAPTER 15 µPD78P083

Figure 15-3. Page Program Mode Timing

Page

Program

Page Data Latch

Program Verify

A2-A14

A0, A1

D0-D7

Data Input

Data Output

V^PP

VPP

VDD

VDD+1.5

VDD

V^DD

VIH

VIL

VIH

VIL

VIH

PGM

VIL

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CHAPTER 15 µPD78P083

Figure 15-4. Byte Program Mode Flowchart

Start

Remark:

Address = G

G = Start address

N = Last address of program

V^DD= 6.5 V, VPP= 12.5 V

X = 0

X = X + 1

X = 10?

Yes

0.1-ms program pulse

Address = Address + 1

Fail

Verify

Pass

Address = N?

Yes

V^DD= 4.5 to 5.5 V, VPP= VDD

Pass

Fail

All bytes verified?

All Pass

End of write

Defective product

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CHAPTER 15 µPD78P083

Figure 15-5. Byte Program Mode Timing

Program

Program Verify

A0-A14

D0-D7

Data Input

Data Output

V^PP

VPP

VDD

VDD+1.5

VDD

VIH

PGM

VIL

VIH

VIL

VIH

VIL

Cautions 1. Be sure to apply V^DDbefore applying VPP, and remove it after removing VPP.

2. V^PPmust not exceed +13.5 V including overshoot voltage.

3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied

to the V^PPpin may have an adverse affect on device reliability.

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CHAPTER 15 µPD78P083

15.2.3 PROM reading procedure

PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.

(1) Fix the RESET pin low, and supply +5 V to the V^PPpin. Unused pins are handled as shown in paragraph,

(2) “PROM programming mode” in section 1.5 Pin Configuration (Top View).

(2) Supply +5 V to the V^DDand VPP pins.

(3) Input the address of data to be read to pins A0 through A14.

(4) Read mode is entered.

(5) Data is output to pins D0 through D7.

The timing for steps (2) through (5) above is shown in Figure 15-6.

Figure 15-6. PROM Read Timing

A0-A14

Address Input

CE (Input)

OE (Input)

D0-D7

Hi-Z

Data Output

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CHAPTER 15 µPD78P083

15.3 Erasure Procedure (µPD78P083DU Only)

With the µPD78P083DU, it is possible to erase ( or set all contents to FFH) the data contents written in the program

memory, and rewrite the memory.

The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter.

Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written

data is shown below.

• UV intensity × exposure time: 30 W s/cm or more

• Exposure time: 40 minutes or more (using a 12 mW/cm ultraviolet lamp. A longer exposure time may be

required in case of deterioration of the ultraviolet lamp or dirt on the package window).

When erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube.

15.4 Opaque Film Masking the Window (µPD78P083DU Only)

To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction

due to light coming in through the erasure window, mask the window with opaque film after writing the EPROM.

15.5 Screening of One-Time PROM Versions

One-time PROM versions (µPD78P083CU, 78P083GB-3B4, 78P083GB-3-MTX) cannot be fully tested by NEC

before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM,

screening should be implemented by user: that is, store devices at high temperature for one day as specified below,

and verify their contents after the devices have returned to room temperature.

Storage Temperature

Storage Time

24 hours

125°C

For users who do not wish to implement screening by themselves, NEC provides such users with a charged

service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying

their contents for users by request. The PROM version devices which provide this service are called QTOP

microcontrollers. As regards the µPD78P083, preparations are underway. For details, please consult an NEC sales

representative.

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CHAPTER 16 INSTRUCTION SET

This chapter describes each instruction set of the µPD78083 subseries as list table. For details of its operation

and operation code, refer to the separate document “78K/0 series USER’S MANUAL—Instruction (IEU-1372).”

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CHAPTER 16 INSTRUCTION SET

16.1 Legends Used in Operation List

16.1.1 Operand identifiers and description methods

Operands are described in “Operand” column of each instruction in accordance with the description method of

the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more

description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and

must be described as they are. Each symbol has the following meaning.

• # : Immediate data specification

• ! : Absolute address specification

• $ : Relative address specification

• [ ] : Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #, !, $, and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 16-1. Operand Identifiers and Description Methods

Identifier

Description Method

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Note

sfr

sfrp

Special-function register symbol

Note

Special-function register symbol (16-bit manipulatable register even addresses only)

saddr

FE20H-FF1FH Immediate data or labels

saddrp

FE20H-FF1FH Immediate data or labels (even address only)

addr16

0000H-FFFFH Immediate data or labels

(Only even addresses for 16-bit data transfer instructions)

0800H-0FFFH Immediate data or labels

addr11

addr5

0040H-007FH Immediate data or labels (even address only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

RBn

RB0 to RB3

Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.

Remark For special-function register symbols, refer to Table 3-2 Special-Function Register List.

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CHAPTER 16 INSTRUCTION SET

16.1.2 Description of “operation” column

: A register; 8-bit accumulator

: X register

: B register

: C register

: D register

: E register

: H register

: L register

: AX register pair; 16-bit accumulator

: BC register pair

: DE register pair

: HL register pair

: Program counter

: Stack pointer

PSW : Program status word

: Carry flag

: Auxiliary carry flag

: Zero flag

RBS : Register bank select flag

IE : Interrupt request enable flag

NMIS : Non-maskable interrupt servicing flag

( )

: Memory contents indicated by address or register contents in parentheses

: Higher 8 bits and lower 8 bits of 16-bit register

: Logical product (AND)

H, ×

: Logical sum (OR)

: Exclusive logical sum (exclusive OR)

—— : Inverted data

addr16 : 16-bit immediate data or label

jdisp8 : Signed 8-bit data (displacement value)

16.1.3 Description of “flag operation” column

(Blank) : Nt affected

: Cleared to 0

: Set to 1

: Set/cleared according to the result

: Previously saved value is restored

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CHAPTER 16 INSTRUCTION SET

16.2 Operation List

Clock

Flag

Instruction

Mnemonic

Group

Operands

r, #byte

Byte

Operation

Note 1 Note 2

AC CY

–

r ← byte

saddr, #byte

sfr, #byte

A, r

(saddr) ← byte

sfr ← byte

A ← r

Note 3

r, A

r ← A

A, saddr

saddr, A

A, sfr

A ← (saddr)

(saddr) ← A

A ← sfr

sfr, A

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

(HL) ← A

PSW, A

MOV

A, [DE]

8-bit data

transfer

[DE], A

A, [HL]

[HL], A

A, [HL + byte]

[HL + byte], A

A, [HL + B]

[HL + B], A

A, [HL + C]

[HL + C], A

A, r

A ← (HL + byte)

(HL + byte) ← A

A ← (HL + B)

(HL + B) ← A

A ← (HL + C)

(HL + C) ← A

A ↔ r

Note 3

A, saddr

A, sfr

A ↔ (saddr)

A ↔ sfr

A, !addr16

A, [DE]

A ↔ (addr16)

A ↔ (DE)

XCH

A, [HL]

A ↔ (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A ↔ (HL + byte)

A ↔ (HL + B)

A ↔ (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed.

3. Except “r = A”

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

rp, #word

Byte

Operation

Note 1 Note 2

AC CY

–

rp ← word

saddrp, #word

sfrp, #word

AX, saddrp

saddrp, AX

AX, sfrp

(saddrp) ← word

sfrp ← word

AX ← (saddrp)

(saddrp) ← AX

16-bit

data

MOVW

AX ← sfrp

sfrp, AX

sfrp ← AX

transfer

Note 3

AX, rp

–

AX ← rp

rp, AX

–

rp ← AX

AX, !addr16

!addr16, AX

AX, rp

–

AX ← (addr16)

(addr16) ← AX

Note 3

Note 4

XCHW

AX ↔ rp

A, #byte

–

A, CY ← A + byte

(saddr), CY ← (saddr) + byte

A, CY ← A + r

saddr, #byte

A, r

–

r, A

–

r, CY ← r + A

A, saddr

A, !addr16

A, [HL]

A, CY ← A + (saddr)

A, CY ← A + (addr16)

A, CY ← A + (HL)

A, CY ← A + (HL + byte)

A, CY ← A + (HL + B)

A, CY ← A + (HL + C)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

r, CY ← r + A + CY

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A + (HL + B) + CY

A, CY ← A + (HL + C) + CY

ADD

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

8-bit

operation

–

saddr, #byte

A, r

Note 4

–

r, A

–

A, saddr

A, !addr16

A, [HL]

ADDC

A, [HL + byte]

A, [HL + B]

A, [HL + C]

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Only when rp = BC, DE or HL

4. Except “r = A”

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Byte

Operation

A, CY ← A – byte

Note 1 Note 2

AC CY

–

saddr, #byte

A, r

(saddr), CY ← (saddr) – byte

A, CY ← A – r

Note 3

r, A

r, CY ← r – A

A, saddr

A, !addr16

A, [HL]

A, CY ← A – (saddr)

SUB

A, CY ← A – (addr16)

A, CY ← A – (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

A, CY ← A – (HL + byte)

A, CY ← A – (HL + B)

A, CY ← A – (HL + C)

A, CY ← A – byte – CY

(saddr), CY ← (saddr) – byte – CY

A, CY ← A – r – CY

r, A

r, CY ← r – A – CY

A, saddr

A, !addr16

A, [HL]

A, CY ← A – (saddr) – CY

A, CY ← A – (addr16) – CY

A, CY ← A – (HL) – CY

A, CY ← A – (HL + byte) – CY

A, CY ← A – (HL + B) – CY

A, CY ← A – (HL + C) – CY

A ← A byte

8-bit

SUBC

operation

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

(saddr) ← (saddr) byte

A ← A

r ← r

r, A

A, saddr

A, !addr16

A, [HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

AND

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A ← A (HL + byte)

A ← A (HL + B)

A ← A (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Byte

Operation

Note 1 Note 2

AC CY

–

A ← A byte

(saddr) ← (saddr) byte

saddr, #byte

A, r

Note 3

A ← A

r ← r

r, A

A, saddr

A, !addr16

A, [HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

A ← A (HL + byte)

A ← A (HL + B)

A ← A (HL + C)

A ← A byte

(saddr) ← (saddr) byte

A ← A

r ← r

r, A

A, saddr

A, !addr16

A, [HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

A ← A (HL + byte)

A ← A (HL + B)

A ← A (HL + C)

A – byte

8-bit

XOR

operation

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

(saddr) – byte

A – r

r, A

r – A

A, saddr

A, !addr16

A, [HL]

A – (saddr)

CMP

A – (addr16)

A – (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A – (HL + byte)

A – (HL + B)

A – (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

221

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

AX, #word

Byte

Operation

AX, CY ← AX + word

Note 1 Note 2

AC CY

ADDW

SUBW

CMPW

MULU

DIVUW

–

16-bit

AX, #word

AX, CY ← AX – word

AX – word

operation

AX, #word

AX ← A × X

Multiply/

divide

AX (Quotient), C (Remainder) ← AX ÷ C

r ← r + 1

INC

saddr

(saddr) ← (saddr) + 1

r ← r – 1

Increment/

decrement

DEC

saddr

(saddr) ← (saddr) – 1

rp ← rp + 1

INCW

DECW

ROR

rp ← rp – 1

A, 1

(CY, A7 ← A0, Am – 1 ← Am) × 1 time

(CY, A0 ← A7, Am + 1 ← Am) × 1 time

(CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time

(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time

ROL

RORC

ROLC

Rotate

A3 – 0 ← (HL)3 – 0, (HL)7 – 4 ← A3 – 0,

(HL)3 – 0 ← (HL)7 – 4

ROR4

[HL]

–

A3 – 0 ← (HL)7 – 4, (HL)3 – 0 ← A3 – 0,

(HL)7 – 4 ← (HL)3 – 0

ROL4

Decimal Adjust Accumulator after

Addition

ADJBA

ADJBS

BCD

adjust

Decimal Adjust Accumulator after

Subtract

–

CY, saddr.bit

CY, sfr.bit

–

CY ← (saddr.bit)

CY ← sfr.bit

CY, A.bit

CY ← A.bit

CY, PSW.bit

CY, [HL].bit

saddr.bit, CY

sfr.bit, CY

CY ← PSW.bit

CY ← (HL).bit

(saddr.bit) ← CY

sfr.bit ← CY

Bit

MOV1

manipu-

late

A.bit, CY

A.bit ← CY

PSW.bit, CY

[HL].bit, CY

PSW.bit ← CY

(HL).bit ← CY

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

CY, saddr.bit

Byte

Operation

CY ← CY (saddr.bit)

Note 1 Note 2

AC CY

–

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW. bit

CY, [HL].bit

saddr.bit

sfr.bit

CY ← CY sfr.bit

CY ← CY A.bit

CY ← CY PSW.bit

CY ← CY (HL).bit

CY ← CY (saddr.bit)

CY ← CY sfr.bit

CY ← CY A.bit

CY ← CY PSW.bit

CY ← CY (HL).bit

CY ← CY (saddr.bit)

CY ← CY sfr.bit

CY ← CY A.bit

CY ← CY PSW.bit

CY ← CY (HL).bit

(saddr.bit) ← 1

sfr.bit ← 1

AND1

OR1

XOR1

SET1

CLR1

Bit

manipu-

late

A.bit

A.bit ← 1

PSW.bit

[HL].bit

PSW.bit ← 1

(HL).bit ← 1

saddr.bit

sfr.bit

–

(saddr.bit) ← 0

sfr.bit ← 0

A.bit

A.bit ← 0

PSW.bit

[HL].bit

PSW.bit ← 0

(HL).bit ← 0

SET1

CLR1

NOT1

–

CY ← 1

CY ← 0

CY ← CY

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

Byte

Operation

Note 1 Note 2

AC CY

(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,

PC ← addr16, SP ← SP – 2

CALL

!addr16

!addr11

–

(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,

PC15 – 11 ← 00001, PC10 – 0 ← addr11,

SP ← SP – 2

CALLF

CALLT

(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,

PCH ← (00000000, addr5 + 1),

PCL ← (00000000, addr5),

SP ← SP – 2

[addr5]

–

Call/return

(SP – 1) ← PSW, (SP – 2) ← (PC + 1)H,

(SP – 3) ← (PC + 1)L, PCH ← (003FH),

PCL ← (003EH), SP ← SP – 3, IE ← 0

BRK

RET

–

PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0

RETI

RETB

PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3

–

PSW

(SP – 1) ← PSW, SP ← SP – 1

PUSH

POP

(SP – 1) ← rpH, (SP – 2) ← rpL,

SP ← SP – 2

PSW

PSW ← (SP), SP ← SP + 1

Stack

manipu-

late

rpH ← (SP + 1), rpL ← (SP),

SP ← SP + 2

SP, #word

SP, AX

AX, SP

!addr16

$addr16

–

SP ← word

MOVW

SP ← AX

AX ← SP

–

PC ← addr16

Uncondi-

tional

–

PC ← PC + 2 + jdisp8

PCH ← A, PCL ← X

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

branch

–

$addr16

–

BNC

–

Conditional

branch

–

BNZ

–

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

224

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CHAPTER 16 INSTRUCTION SET

Clock

Flag

Instruction

Group

Mnemonic

Operands

Byte

Operation

Note 1 Note 2

AC CY

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

–

PC ← PC + 3 + jdisp8 if(saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 3 + jdisp8 if PSW.bit = 1

PC ← PC + 3 + jdisp8 if (HL).bit = 1

PC ← PC + 4 + jdisp8 if(saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW. bit = 0

PC ← PC + 3 + jdisp8 if (HL).bit = 0

PSW.bit, $addr16

[HL].bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

–

PSW.bit, $addr16

[HL].bit, $addr16

–

PC ← PC + 4 + jdisp8

if(saddr.bit) = 1

Condi-

tional

saddr.bit, $addr16

then reset(saddr.bit)

branch

PC ← PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

[HL].bit, $addr16

B, $addr16

–

BTCLR

PC ← PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

PC ← PC + 4 + jdisp8 if PSW.bit = 1

then reset PSW.bit

–

PC ← PC + 3 + jdisp8 if (HL).bit = 1

then reset (HL).bit

B ← B – 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C ← C –1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

DBNZ

C, $addr16

–

(saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if(saddr) ≠ 0

saddr. $addr16

RBn

SEL

NOP

–

RBS1, 0 ← n

No Operation

IE ← 1(Enable Interrupt)

IE ← 0(Disable Interrupt)

Set HALT Mode

CPU

control

HALT

STOP

Set STOP Mode

Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remark One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the PCC register.

225

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CHAPTER 16 INSTRUCTION SET

16.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

226

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CHAPTER 16 INSTRUCTION SET

Second Operand

[HL + byte]

Note

#byte

sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16

None

First Operand

[HL + C]

ADD

ADDC

SUB

SUBC

AND

MOV MOV MOV MOV MOV MOV MOV MOV

ROR

XCH XCH XCH XCH

XCH XCH XCH

ADD ADD

ROL

ADD

ADDC

SUB

SUBC

AND

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

RORC

ROLC

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

XOR

CMP

XOR

CMP

XOR XOR

CMP CMP

XOR XOR

CMP CMP

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

XOR

CMP

B, C

sfr

DBNZ

MOV MOV

saddr

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

XOR

CMP

!addr16

PSW

MOV

MOV MOV

PUSH

POP

[DE]

[HL]

MOV

ROR4

ROL4

[HL + byte]

[HL + B]

MOV

[HL + C]

MULU

DIVUW

Note Except r = A

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CHAPTER 16 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second Operand

Note

#word

sfrp

saddrp

MOVW

!addr16

MOVW

None

First Operand

ADDW

SUBW

CMPW

MOVW

XCHW

MOVW

Note

MOVW

INCW

DECW

PUSH

POP

sfrp

MOVW

saddrp

!addr16

MOVW

Note Only when rp = BC, DE, HL

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

$addr16

None

First Operand

A.bit

MOV1

SET1

CLR1

BTCLR

sfr.bit

MOV1

SET1

CLR1

BTCLR

saddr.bit

PSW.bit

[HL].bit

SET1

CLR1

BTCLR

SET1

CLR1

BTCLR

SET1

CLR1

BTCLR

MOV1

AND1

OR1

MOV1

AND1

OR1

MOV1

AND1

OR1

MOV1

SET1

CLR1

NOT1

AND1

OR1

AND1

OR1

XOR1

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CHAPTER 16 INSTRUCTION SET

(4) Call/instructions/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second Operand

!addr16

!addr11

CALLF

[addr5]

CALLT

$addr16

First Operand

Basic instruction

CALL

BNC

BNZ

Compound

instruction

BTCLR

DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

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CHAPTER 16 INSTRUCTION SET

[MEMO]

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems which employ the µPD78083

subseries.

Figure A-1 shows the configuration of the development tools.

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration

Embedded software

PROM programmer control software

• PG-1500 controller

• Real-time OS, OS

• Fuzzy inference development

support system

Language processing software

• Assembler package

• C compiler package

• C library source file

• System simulator

• Screen debugger or

integrated debugger

• Device file

Host machine (PC or EWS)

Interface adapter (only when

integrated debugger is used)

PROM writing

environments

In-circuit emulator

Interface adapter (only when

PROM programmer

integrated debugger is used)

Emulation board

Programmer

adapter

PROM containing

version

Emulation probe

Conversion socket

Target system

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APPENDIX A DEVELOPMENT TOOLS

A.1 Language Processing Software

RA78K/0

This assembler converts a program written in mnemonics into an object code executable with a

microprocontroller.

Assembler Package

Further, this assembler is provided with functions capable of automatically creating symbol tables

and branch instruction optimization.

Used in combination with optional device file (DF78083).

Part Number: µS××××RA78K/0

CC78K/0

This compiler converts a program written in C Language into an object code executable with an

microcontroller.

C Compiler Package

Used in combination with optional assembler package (RA78K/0) and device file (DF78083).

Part Number: µS××××CC78K/0

Note

DF78083

This is a file containing information inherent to the device.

Device File

Used in combination with optional RA78K/0, CC78K/0, SM78K0, ID78K0, or SD78K/0.

Part Number: µS××××DF78083

CC78K/0-L

This is a function source program configurating object library included in CC78K/0 C compiler.

Necessary for changing object library included in CC78K/0 in according to customer’s

specifications.

C Library Source File

Part Number: µS××××CC78K0-L

Note The DF78083 can be used commonly with all the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0.

Remark ×××× of the part number differs depending on the host machine and OS used. Refer to the table below.

µS××××RA78K0

µS××××CC78K0

µS××××DF78083

µS××××CC78K0-L

××××

5A13

5A10

7B13

7B10

3H15

3P16

3K15

3M15

Host Machine

PC-9800 Series

Medium

3.5-inch 2HD

MS-DOS

Note

(Ver. 3.30 to 6.2

)

5-inch 2HD

IBM PC/AT and their

compatible machines

HP9000 series 300™

HP9000 series 700™

SPARCstation™

Refer to A.4

3.5-inch 2HC

5-inch 2HC

HP-UX™ (rel. 7.05B)

HP-UX (rel. 9.01)

Cartridge tape (QIC-24)

Digital audio tape (DAT)

Cartridge tape (QIC-24)

SunOS™ (rel. 4.1.1)

EWS-UX/V (rel. 4.0)

EWS-4800 series (RISC)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

233

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APPENDIX A DEVELOPMENT TOOLS

A.2 PROM Programming Tools

A.2.1 Hardware

PG-1500

This is a PROM programmer capable of programming the single-chip microcontroller with on-chip

PROM by manipulating from the stand-alone or host machine through connection of the

separately available programmer adapter and the attached board. It can also program separate

PROM ICs with a capacity from 256 Kbits to 4 Mbits.

PROM programmer

PA-78P083CU

PA-78P083GB

PROM programmer

adapter

This is a PROM programmer adapter for the µPD78P083, and is used connected to the PG-1500.

PA-78P083CU: 42-pin plastic shrink DIP (600 mil)

42-pin ceramic shrink DIP (with window) (600 mil)

PA-78P083GB: 44-pin plastic QFP (10 × 10 mm)

A.2.2 Software

PG-1500 controller

This program controls the PG-1500 from the host machine through serial and/or parallel interface

cable(s).

Part Number: µS××××PG1500

Remark ×××× of the part number differs depending on the host machine and OS used. Refer to the table below.

µS××××PG1500

××××

5A13

5A10

7B13

7B10

Host Machine

PC-9800 Series

Medium

MS-DOS

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Note

(Ver. 3.30 to 6.2

)

IBM PC/AT and their

compatible machines

Refer to A.4

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

234

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APPENDIX A DEVELOPMENT TOOLS

A.3 Debugging Tools

A.3.1 Hardware

IE-78000-R-A

This in-circuit emulator helps users in debugging hardware and software of an application system

that includes a 78K/0 series device. This in-circuit emulator supports integrated debugger

(ID78K0). It is used with emulation probe and interface adapter that connects host machine.

In-circuit emulator

(supporting integrated

debugger)

IE-70000-98-IF-B

Interface adapter

This is an adapter necessary when using the PC-9800 series (except notebook type) as a host

machine for the IE-78000-R-A.

IE-70000-98N-IF

Interface adapter

This is an adapter and cable necessary when using notebook type PC-9800 series as a host

machine for the IE-78000-R-A.

IE-70000-PC-IF-B

Interface adapter

This is an adapter necessary when using IBM PC/AT as a host machine for the IE-78000-R-A.

IE-78000-R-SV3

Interface adapter

This is an adapter and cable necessary when using EWS as a host machine for the IE-78000-R-

As Ethernet™, 10Base-5 is supported. With other mode, commercially available conversion

adapter is necessary.

IE-78000-R

This is in-circuit emulator that debugs hardware and software when application system using

78K/0 series is developed. It supports screen debugger (SD78K/0), and is used with emulation

probe. This emulator is connected to host machine or PROM programmer for efficient

debugging.

In-circuit emulator

(supporting screen

debugger)

IE-78078-R-EM

Emulation board

IEP-78083CU-R

Emulation probe

This board is used to emulate device-specific peripheral hardware (3.0 to 5.5 V), and is used with

in-circuit emulator.

This is a probe to connect an in-circuit emulator to target sytem.

This probe is designed for 42-pin plastic shrink DIP (CU type) and 42-pin ceramic shrink DIP

(DU type).

EP-78083GB-R

Emulation probe

This is a probe to connect an in-circuit emulator to target system.

This probe is designed for 44-pin plastic QFP (GB-3B4, GB-3BS-MTX types).

This probe set includes a 44-pin conversion socket EV-9200G-44 for easier development of

target systems

EV-9200G-44

This adapter connects the EP-78083GB-R to the target system board designed for 44-pin plastic

Conversion socket QFP (GB-3B4, GB-3BS-MTX types).

Remark EV-9200G-44s are sold in sets of five units.

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software (1/3)

SM78K0

This simulator can debug target system at C source level or assembler level while simulating

operation of target system on host machine.

System simulator

SM78K0 runs on Windows.

By using SM78K0, logic and performance of application can be verified without in-circuit emulator

independently of hardware development, so that development efficiency and software quality can

be improved.

This simulator is used with optional device file (DF78083).

Part Number: µS××××SM78K0

Remark ×××× of the part number differs depending on the host machine and OS used. Refer to the table below.

µS××××SM78K0

××××

Host Machine

PC-9800 Series

Medium

3.5-inch 2HD

AA13

MS-DOS

Note

(Ver. 3.30 to 6.2

)

Windows (Ver. 3.0 to 3.1)

AB13

BB13

IBM PC/AT and their

compatible machines

(Windows in Japanese)

Refer to A.4

3.5-inch 2HC

IBM PC/AT and their

compatible machines

(Windows in English)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

236

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software (2/3)

ID78K0

This is control program that debugs 78K/0 series.

Integrated debugger

This program employs Windows on personal computer and OSF/Motif™ on EWS as graphical

user interface, and provides appearance and operability conforming to interface. In addition

debugging functions supporting C language are reinforced. Trace result can be displayed at C

level by using window integration function that associates source program, disassemble display,

and memory display with trace result. Moreover, debugging efficiency of program using real-time

OS can be enhanced by using function expansion modules such as task debugger and system

performance analyzer.

This program is used in combination with optional device file (DF78083).

Part Number: µS××××ID78K0

Remark ×××× of the part number differs depending on the host machine and OS used. Refer to the table below.

µS××××ID78K0

××××

Host Machine

PC-9800 Series

Medium

3.5-inch 2HD

AA13

MS-DOS

Note

(Ver. 3.30 to 6.2

)

Windows (Ver. 3.1)

AB13

BB13

IBM PC/AT and their

Refer to A.4

3.5-inch 2HC

compatible machines

(Windows in Japanese)

IBM PC/AT and their

compatible machines

(Windows in English)

3P16

3K15

3K13

3R16

3R13

3M15

HP9000 series 700

SPARCstation

HP-UX (rel. 9.01)

SunOS (rel. 4.1.1)

Digital audio tape (DAT)

Cartridge tape (QIC-24)

3.5-inch 2HC

NEWS™ (RISC)

NEWS-OS™ (6.1x)

EWS-UX/V (rel. 4.0)

1/4-inch CGMT

3.5-inch 2HC

EWS4800 series (RISC)

Cartridge tape (QIC-24)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

237

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software (3/3)

SD78K/0

This program controls IE-78000-R on host machine with IE-78000-R and host machine

connected with serial interface (RS-232-C).

Screen debugger

It is used with optional device file (DF78083).

Part Number: µS××××SD78K0

Note

DF78083

File containing device-specific information.

Device file

It is used with optional RA78K/0, CC78K/0, SM78K0, ID78K0, or SD78K/0.

Part Number: µS××××DF78083

Note This device file can be used for any of the RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0 devices.

Remark ×××× of the part number differs depending on the host machine and OS used. Refer to the table below.

µS××××SD78K0

µS××××DF78083

××××

5A13

5A10

7B13

7B10

Host Machine

PC-9800 Series

Medium

3.5-inch 2HD

MS-DOS

Note

(Ver. 3.30 to 6.2

)

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

IBM PC/AT and their

Refer to A.4

compatible machines

(Windows in Japanese)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

238

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APPENDIX A DEVELOPMENT TOOLS

A.4 OS for IBM PC

As the OS for IBM PC, the following is supported.

To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuzzy Inference Development Support System), Windows

(Ver. 3.0 to Ver. 3.1) is necessary.

PC DOS

Version

Ver. 5.02 to 6.3

Note

J6.1/V

to J6.3/V

Note

IBM DOS™

MS-DOS

J5.02/V

Ver. 5.0 to 6.22

Note

5.0/V

to 6.2/V

Note Only English mode is supported.

Caution The task swap function is not available with this software through the function is provided in

MS-DOS version 5.0 or later.

239

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APPENDIX A DEVELOPMENT TOOLS

A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator

If you already have an in-circuit emulator for the 78K series or the 75X/XL series, you can use that in-circuit emulator

as the equivalent of the 78K/0 series in-circuit emulator IE-78000-R or IE-78000-R-A by replacing the internal break

board with the IE-78000-R-BK.

Table A-1. System-Up Method from Other In-Circuit Emulator to IE-78000-R

Series Name

75X/XL series

In-Circuit Emulator Owned

Board to be Purchased

IE-78000-R-BK

Note

IE-75000-R

, IE-75001-R

78K/I series

78K/II series

IE-78130-R, IE-78140-R

Note

IE-78230-R

IE-78240-R

, IE-78230-R-A,

, IE-78240-R-A

Note

78K/III seires

IE-78320-R

, IE-78327-R,

IE-78330-R, IE-78350-R

Note Maintenance product

Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A

Series Name

75X/XL series

In-Circuit Emulator Owned

Board to be Purchased

Note 1

Note 2

IE-75000-R

, IE-75001-R

IE-78000-R-BK

78K/I series

78K/II series

IE-78130-R, IE-78140-R

Note 1

IE-78230-R

IE-78240-R

, IE-78230-R-A,

, IE-78240-R-A

Note 1

78K/III seires

78K/0 series

IE-78320-R

, IE-78327-R,

IE-78330-R, IE-78350-R

IE-78000-R

Note 2

—

Notes 1. Maintenance product

2. Partial remodeling of the frame of the in-circuit emulator and replacement of the control/

trace board with a supervisor board must be done by NEC.

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APPENDIX A DEVELOPMENT TOOLS

Drawing and Footprint for Conversion Socket (EV-9200G-44)

Figure A-2. EV-9200G-44 Drawing (For Reference Only)

Based on EV-9200G-44

(1) Package drawing (in mm)

EV-9200G-44

No.1 pin index

EV-9200G-44-G0E

ITEM

MILLIMETERS

15.0

10.3

15.0

4-C 3.0

0.8

INCHES

0.591

0.406

0.591

4-C 0.118

0.031

0.197

0.472

0.579

0.197

0.472

0.579

0.315

0.307

0.079

5.0

12.0

14.7

5.0

12.0

14.7

8.0

7.8

2.0

1.35

0.053

+0.004

0.35 0.1

0.014

–0.005

1.5

0.059

241

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APPENDIX A DEVELOPMENT TOOLS

Figure A-3. EV-9200G-44 Footprint (For Reference Only)

Based on EV-9200G-44

(2) Pad draw ing (in m m )

EV-9200G-44-P1E

ITEM

MILLIMETERS

INCHES

0.618

15.7

11.0

0.433

+0.002

–0.002

0.8 0.02 × 10=8.0 0.05 0.031_–0.001

^+0.002× 0.394=0.315

+0.002

–0.002

0.8 0.02 × 10=8.0 0.05 0.031_–0.001

11.0

15.7

0.433

0.618

0.197

+0.003

–0.004

5.00 0.08

+0.003

–0.004

5.00 0.08

+0.001

0.5 0.02

0.02

–0.002

+0.001

1.57 0.03

0.062

–0.002

+0.004

–0.005

2.2 0.1

0.087

0.062

+0.001

–0.002

1.57 0.03

Dimensions of mount pad for EV-9200 and that for target

device (QFP) may be different in some parts. For the

recommended mount pad dimensions for QFP, refer to

"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY

MANUAL" (C10535E).

Caution

242

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APPENDIX B EMBEDDED SOFTWARE

This section describes the embedded software which are provided for the µPD78083 subseries to allow users to

develop and maintain the application program for these subseries.

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APPENDIX B EMBEDDED SOFTWARE

B.1 Real-time OS

MX78K0

µITRON-specification subset OS. Nucleus of MX78K0 is supplied.

This OS performs task management, event management, and time management. It controls the task

execution sequence for task management and selects the task to be executed next.

Part Number: µS××××MX78K0-∆∆∆

Remark ×××× and ∆∆∆ of the part number differs depending on the host machine and operating system used.

Refer to the table below.

µS××××MX78K0-∆∆∆

∆∆∆

001

Product outline

Evaluation object

Note

Use for experimental production.

Use for mass production.

××

Mass-production object

Source program

S01

Can be purchased only when object for mass

production has been purchased.

××××

5A13

5A10

7B13

7B10

3H15

3P16

3K15

3M15

Host Machine

Medium

3.5-inch 2HD

PC-9800 Series

MS-DOS

Note

(Ver. 3.30 to 6.2

)

5-inch 2HD

IBM PC/AT and their

compatible machines

HP9000 series 300

HP9000 series 700

SPARCstation

Refer to A.4

3.5-inch 2HC

5-inch 2HC

HP-UX (rel. 7.05B)

HP-UX (rel. 9.01)

SunOS (rel. 4.1.1)

EWS-UX/V (rel. 4.0)

Cartridge tape (QIC-24)

Digital audio tape (DAT)

Cartridge tape (QIC-24)

EWS4800 series (RISC)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

244

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APPENDIX B EMBEDDED SOFTWARE

B.2 Fuzzy Inference Development Support System

FE9000/FE9200

This program supports input of fuzzy knowledge data (fuzzy rule and membership function),

Fuzzy Knowledge Data editing (edit), and evaluation (simulation)

Creation Tool

FE9200 operations on Windows.

Part Number: µS××××FE9000 (PC-9800 series)

µS××××FE9200 (IBM PC/AT and their compatible machines)

FT9080/FT9085

Translator

This program converts fuzzy knowledge data obtained by using fuzzy knowledge data preparation

tool to RA78K/0 assembler source program.

Part Number: µS××××FT9080 (PC-9800 series)

µS××××FT9085 (IBM PC/AT and their compatible machines)

FI78K0

This program executes fuzzy inference by linking fuzzy knowledge data converted by translator.

Fuzzy Inference Module Part Number: µS××××FI78K0 (PC-9800 series, IBM PC/AT and their compatible machines)

FD78K0

This software supports evaluating and adjusting fuzzy knowledge data at hardware level by using

in-circuit emulator.

Fuzzy Inference

Debugger

Part Number: µS××××FD78K0 (PC-9800 series, IBM PC/AT and their compatible machines)

Remark ×××× of the part number differs depending on the host machine and operating system used. Refer to

the table below.

µS××××FE9000

µS××××FT9080

µS××××FI78K0

µS××××FD78K0

××××

5A13

5A10

Host Machine

PC-9800 Series

Medium

3.5-inch 2HD

5-inch 2HD

MS-DOS

(Ver. 3.30 to 6.2

Note2

)

Note The task swap function is not available with this software through the function is

provided in MS-DOS version 5.0 or later.

µS××××FE9200

µS××××FT9085

µS××××FI78K0

µS××××FD78K0

××××

7B13

7B10

Host Machine

IBM PC/AT and their

compatible machines

Refer to A.4

Medium

3.5-inch 2HC

5-inch 2HC

245

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APPENDIX B EMBEDDED SOFTWARE

[MEMO]

246

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APPENDIX C REGISTER INDEX

C.1 Register Index

8-bit timer mode control register (TMC5)............................................................................................................ 87

8-bit timer register 5 (TM5) ........................................................................................................................... 79, 84

8-bit timer register 6 (TM6) ........................................................................................................................... 79, 84

[A]

ADCR:

ADIS:

ADM:

ASIM:

ASIS:

A/D conversion result register ........................................................................................................ 121

A/D converter input select register................................................................................................. 124

A/D converter mode register .......................................................................................................... 122

Asynchronous serial interface mode register ............................................................... 141, 149, 151

Asynchronous serial interface status register .............................................................. 143, 152, 164

[B]

BRGC:

Baud rate generator control register ............................................................................. 144, 153, 165

[C]

CR50:

CR60:

CSIM2:

Compare registers 50 ....................................................................................................................... 84

Compare registers 60 ....................................................................................................................... 84

Serial operating mode register 2 ...........................................................................140, 148, 150, 163

[E]

External interrupt mode register (INTM0) ......................................................................................................... 179

External interrupt mode register (INTM1) ................................................................................................ 125, 179

[I]

IF0H:

IF0L:

Interrupt request flag register 0H .......................................................................................... 175, 176

Interrupt request flag register 0L........................................................................................... 175, 176

Interrupt request flag register 1L........................................................................................... 175, 176

Memory size switching register ...................................................................................................... 206

External interrupt mode register 0 ........................................................................................ 175, 179

External interrupt mode register 1 ................................................................................ 125, 175, 179

IF1L:

IMS:

INTM0:

INTM1:

Interrupt mask flag register 0H (MK0H) ................................................................................................... 175, 177

Interrupt mask flag register 0L (MK0L) .................................................................................................... 175, 177

Interrupt mask flag register 1L (MK1L) .................................................................................................... 175, 177

[M]

MK0H:

MK0L:

MK1L:

Interrupt mask flag register 0H.............................................................................................. 175, 177

Interrupt mask flag register 0L .............................................................................................. 175, 177

Interrupt mask flag register 1L .............................................................................................. 175, 177

Memory size switching register (IMS) ............................................................................................................... 206

[O]

OSMS:

OSTS:

Oscillation mode selection register ..................................................................................... 71, 72, 76

Oscillation stabilization time select register................................................................................... 194

247

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APPENDIX C REGISTER INDEX

[P]

P0:

Port0 ........................................................................................................................................... 17, 55

Port1 ........................................................................................................................................... 17, 57

Port3 ........................................................................................................................................... 18, 58

Port5 ........................................................................................................................................... 18, 59

Port7 ........................................................................................................................................... 19, 60

Port10 ......................................................................................................................................... 19, 62

Processor clock control register .......................................................................................... 71, 76, 77

Port mode register 0 ......................................................................................................................... 63

Port mode register 1 ......................................................................................................................... 63

Port mode register 3 ........................................................................................................ 63, 114, 118

Port mode register 5 ......................................................................................................................... 63

Port mode register 7 ......................................................................................................................... 63

Port mode register 10 ................................................................................................................ 63, 89

Priority specify flag register 0H ............................................................................................. 175, 178

Priority specify flag register 0L.............................................................................................. 175, 178

Priority specify flag register 1L.............................................................................................. 175, 178

Program status word........................................................................................................ 33, 175, 180

Pull-up resistor option register H ..................................................................................................... 66

Pull-up resistor option register L ...................................................................................................... 66

P1:

P3:

P5:

P7:

P10:

PCC:

PM0:

PM1:

PM3:

PM5:

PM7:

PM10:

PR0H:

PR0L:

PR1L:

PSW:

PUOH:

PUOL:

[R]

RXB:

Receive buffer register ................................................................................................................... 139

[S]

SAR:

SFR:

Successive approximation register ................................................................................................ 121

Special-function register ...................................................................................................... 29, 37, 49

Serial operating mode register 2 (CSIM2) ...............................................................................140, 148, 150, 163

[T]

TCL0:

TCL2:

TCL5:

TCL6:

TM5:

Timer clock select register 0 .......................................................................................................... 113

Timer clock select register 2 ................................................................................................. 106, 116

Timer clock select register 5 ............................................................................................................ 84

Timer clock select register 6 ............................................................................................................ 86

8-bit timer register 5................................................................................................................... 79, 84

8-bit timer register 6................................................................................................................... 79, 84

8-bit timer mode control register 5 ................................................................................................... 87

8-bit timer mode control register 6 ................................................................................................... 88

Transmit shift register ..................................................................................................................... 139

TM6:

TMC5:

TMC6:

TXS:

[W]

WDTM:

Watchdog timer mode register ........................................................................................ 79, 103, 108

248

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APPENDIX D REVISION HISTORY

Major revisions by edition and revised chapters are shown below.

Edition

2nd

Major revisions from previous version

Revised Chapter

The following products have been already developed

µPD78081CU-×××, 78081GB-×××-3B4, 78082CU-×××,

78082GB-×××-3B4, 78P083CU, 78P083DU, 78P083GB-3B4

Throughout

The following products have been added

µPD78081GB-×××-3BS-MTX, 78082GB-×××-3B4-MTX,

780P083GB-3BS-MTX, 78081GB(A)-×××-3B4,78082GB(A)-×××-3B4,

78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX,

78081GB(A2)-×××-3B4

Power voltage changed to VDD = 1.8 to 5.5V.

1.6 78K/0 Series Development has been changed.

CHAPTER 1 OUTLINE

1.9 Differences between the µPD78081, 78082, and 78P083,

the µPD78081(A), 78082(A), and 78P083(A), and

the µPD78081(A2) has been added.

Cautions regarding the use of functions in common with 2.2.5

(2) (d) ASCK has been added.

CHAPTER 2 PIN FUNCTION

Cautions concerning the Write to OSMS Command has been

CHAPTER 5 CLOCK GENERATOR

added to 5.3 (2) Oscillation mode select register (OSMS).

Cautions concerning external clock input in 5.4.1 Main system

clock oscillation has been changed.

Figure 7-3. Watchdog Timer Mode Register Format, notes and CHAPTER 7 WATCHDOG TIMER

cautions have been added.

Description of 7.4.2 Interval timer operation has been changed.

Cautions with regard to rewriting TCL0 to other than same data

CHAPTER 8 CLOCK OUTPUT CONTROL

CIRCUIT

has been added to 8.3 (1) Timer clock select register 0 (TCL0).

The HSC bit has been added to the A/D Converter Mode

CHAPTER 10 A/D CONVERTER

10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby

function, and Cautions have been added.

Figure 11-1. Serial Interface Channel 2 Block Diagram has

CHAPTER 11 SERIAL INTERFACE

CHANNEL 2

been corrected.

11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/

receive clock by means of main system clock have been added.

76800 bps has been added to baud rate generated from the main

system clock.

Figure 11-10. Receive Error Timing has been corrected.

11.4.3 (c) Baud rate generator control register (BRGC) has

been added.

15.1 Memory Size Switching Register has been changed from

CHAPTER 15 µPD78P083

W to R/W.

Items and cautions have been added to Table 15-1. Differences

between the µPD78P083 and Mask ROM Versions.

A description of the QTOP icon has been added to 15.5 Screening

of One-Time PROM Versions.

249

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APPENDIX D REVISION HISTORY

Edition

2nd

Major revisions from previous version

Revised Chapter

Figure A-1. Development Tool Configuration has been changed. APPENDIX A DEVELOPMENT TOOLS

APPENDIX A DEVELOPMENT TOOLS

The following Development Tools have been added:

IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98-N-IF,

IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0

A.4 OS for IBM PC has been added.

Table A-2. System-Up Method from Other In-Circuit Emulator

to IE-78000-R-A has been added.

B.1 Real-time OS has been added.

APPENDIX B EMBEDDED SOFTWARE

250

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