Fujitsu Power Supply MB39A104 User Manual

FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS04-27231-3E  
ASSP For Power Management Applications  
(General Purpose DC/DC Converter)  
2-ch DC/DC Converter IC  
with Overcurrent Protection  
MB39A104  
DESCRIPTION  
The MB39A104 is a 2-channel DC/DC converter IC using pulse width modulation (PWM), incorporating an  
overcurrent protection circuit (requiring no current sense resistor). This IC is ideal for down conversion.  
Operating at high frequency reduces the value of coil.  
This is ideal for built-in power supply such as LCD monitors and ADSL.  
This product is covered by US Patent Number 6,147,477.  
FEATURES  
• Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)  
• Power supply voltage range : 7 V to 19 V  
• Reference voltage : 5.0 V ± 1 %  
• Error amplifier threshold voltage : 1.24 V ± 1 %  
• High-frequency operation capability : 1.5 MHz (Max)  
• Built-in standby function: 0 µA (Typ)  
• Built-in soft-start circuit independent of loads  
• Built-in totem-pole type output for Pch MOS FET  
PACKAGE  
24-pin plastic SSOP  
(FPT-24P-M03)  
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MB39A104  
PIN DESCRIPTION  
Pin No.  
Symbol  
VCCO  
VH  
I/O  
Descriptions  
1
2
3
4
Output circuit power supply terminal (Connect to same potential as VCC pin.)  
Power supply terminal for FET drive circuit (VH = VCC 5 V)  
External Pch MOS FET gate drive terminal  
O
O
I
OUT1  
VS1  
Overcurrent protection circuit input terminal  
Overcurrent protection circuit detection resistor connection terminal. Set  
overcurrent detection reference voltage depending on external resistor and  
internal current resource (110 µA at RT = 24 k)  
5
ILIM1  
I
I
PWM comparator block (PWM) input terminal. Compares the lowest voltage  
among FB1 and DTC terminals with triangular wave and controls output.  
6
7
DTC1  
VCC  
Power supply terminal for reference power supply and control circuit  
(Connect to same potential as the VCCO terminal)  
8
CSCP  
FB1  
Timer-latch short-circuit protection capacitor connection terminal  
Error amplifier (Error Amp 1) output terminal  
9
O
I
10  
11  
12  
13  
14  
15  
16  
17  
INE1  
CS1  
RT  
Error amplifier (Error Amp 1) inverted input terminal  
Soft-start capacitor connection terminal  
Triangular wave oscillation frequency setting resistor connection terminal  
Triangular wave oscillation frequency setting capacitor connection terminal  
Soft-start capacitor connection terminal  
CT  
CS2  
INE2  
FB2  
I
Error amplifier (Error Amp 2) inverted input terminal  
Error amplifier (Error Amp 2) output terminal  
O
O
VREF  
Reference voltage output terminal  
Output circuit ground terminal (Connect to same potential as GNDO  
terminal.)  
18  
19  
GND  
PWM comparator block (PWM) input terminal. Compares the lowest voltage  
among FB2 and DTC terminals with triangular wave and controls output.  
DTC2  
I
I
Overcurrent protection circit detection resistor connection terminal. Set  
overcurrent detection reference voltage depending on external resistor and  
internal current resource (110 µA at RT = 24 k)  
20  
ILIM2  
21  
22  
23  
VS2  
I
Overcurrent protection circuit input terminal  
OUT2  
GNDO  
O
External Pch MOS FET gate drive terminal  
Output circuit ground terminal (Connect to same potential as GND terminal.)  
Power supply control terminal. Setting the CTL terminal at “L” level places IC  
in the standby mode.  
24  
CTL  
I
3
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MB39A104  
BLOCK DIAGRAM  
INE1 10  
1
3
VCCO  
OUT1  
CH1  
L priority  
VREF  
1.24 V  
Error  
PWM  
Comp.1  
Amp1  
10 µA  
CS1 11  
+
+
Drive1  
Pch  
+
+
L priority  
FB1  
9
IO = 200 mA  
at VCCO = 12 V  
+
4
5
VS1  
Current  
Protection  
Logic  
ILIM1  
DTC1  
6
INE2 15  
CH2  
L priority  
VREF  
1.24 V  
Error  
PWM  
Comp.2  
Amp2  
10 µA  
CS2 14  
+
+
+
+
Drive2  
Pch  
22 OUT2  
L priority  
FB2 16  
IO = 200 mA  
at VCCO = 12 V  
DTC2 19  
+
21 VS2  
Current  
Protection  
Logic  
H priority  
H: at SCP  
20 ILIM2  
SCP  
Comp.  
+
+
(3.1 V)  
H: at OCP  
VH  
VCC 5 V  
2
VH  
Bias  
Voltage  
SCP  
Logic  
CSCP  
8
23 GNDO  
2.5 V  
1.5 V  
Error Amp Power Supply  
Error Amp Reference  
UVLO  
7
VCC  
H:UVLO  
release  
1.24 V  
Power  
bias  
24 CTL  
OSC  
ON/OFF  
CTL  
VREF  
VR1  
Accuracy  
±1%  
5.0 V  
12 13  
RT CT  
17  
18  
VREF  
GND  
4
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MB39A104  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Max  
Min  
Power supply voltage  
Output current  
VCC  
IO  
VCC, VCCO terminal  
OUT1, OUT2 terminal  
Duty 5% (t = 1/fOSC×Duty)  
Ta +25 °C  
20  
60  
V
mA  
mA  
mW  
°C  
Output peak current  
Power dissipation  
Storage temperature  
IOP  
700  
740*  
+125  
PD  
TSTG  
55  
* : The packages are mounted on the epoxy board (10 cm × 10 cm).  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
RECOMMENDED OPERATING CONDITIONS  
Value  
Parameter  
Symbol  
Condition  
Unit  
Min  
7
Typ  
Max  
19  
Power supply voltage  
VCC  
IREF  
IVH  
VCC, VCCO terminal  
VREF terminal  
12  
V
mA  
mA  
V
Reference voltage output current  
VH output current  
1  
0
0
VH terminal  
30  
VINE  
VDTC  
VCTL  
IO  
INE1, INE2 terminal  
DTC1, DTC2 terminal  
CTL terminal  
0
VCC 0.9  
VCC 0.9  
19  
Input voltage  
0
V
Control input voltage  
Output current  
0
V
OUT1, OUT2 terminal  
Duty 5% (t = 1/fOSC×Duty)  
45  
450  
+45  
+450  
mA  
mA  
Output Peak current  
IOP  
Overcurrent detection  
by ON resistance of FET  
100  
500  
1000  
kHz  
Oscillation frequency  
fOSC  
*
100  
39  
500  
100  
24  
1500  
560  
130  
1.0  
kHz  
pF  
Timing capacitor  
CT  
RT  
Timing resistor  
11  
kΩ  
µF  
µF  
µF  
VH terminal capacitor  
Soft-start capacitor  
Short-circuit detection capacitor  
CVH  
CS  
VH terminal  
0.1  
0.1  
0.1  
CS1, CS2 terminal  
CSCP terminal  
1.0  
CSCP  
1.0  
Reference voltage output  
capacitor  
CREF  
Ta  
VREF terminal  
0.1  
1.0  
µF  
°C  
Operating ambient temperature  
30  
+25  
+85  
* : See“ SETTING THE TRIANGULAR OSCILLATION FREQUENCY”.  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All of the device’s electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
5
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MB39A104  
ELECTRICAL CHARACTERISTICS  
(VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C)  
Value  
Symbol  
Parameter  
Output voltage  
Pin No  
Conditions  
Ta = +25 °C  
Unit  
Min  
Typ  
Max  
VREF  
17  
4.95 5.00 5.05  
V
Output voltage  
temperature  
variation  
VREF/  
VREF  
17  
Ta = 0 °C to +85 °C  
0.5*  
%
Input stability  
Load stability  
Line  
17  
17  
VCC = 7 V to 19 V  
3
1
10  
10  
mV  
mV  
Load  
VREF = 0 mA to 1 mA  
Short-cuircuit  
output current  
IOS  
VTLH  
VTHL  
VH  
17  
17  
17  
17  
8
VREF = 1 V  
VREF =  
50  
2.6  
2.4  
25  
2.8  
12  
3.0  
2.8  
mA  
V
Threshold  
voltage  
VREF =  
2.6  
V
Hysteresis  
width  
0.2 *  
V
Threshold  
voltage  
VTH  
0.68 0.73 0.78  
V
Input source  
current  
ICSCP  
VRST  
8
1.4 1.0 0.6  
µA  
Reset voltage  
17  
VREF =  
2.4  
2.6  
2.8  
V
Threshold  
voltage  
VTH  
8
2.8  
3.1  
3.4  
V
Oscillation  
frequency  
fOSC  
13  
13  
CT = 100 pF, RT = 24 k450  
Ta = 0 °C to +85 °C  
500  
1*  
550 kHz  
Frequency  
temperature  
variation  
fOSC/  
fOSC  
%
Charge current  
ICS  
11, 14  
CS1 = CS2 = 0 V  
14  
10  
6  
µA  
Threshold  
voltage  
VTH  
IB  
9, 16  
10, 15  
9, 16  
FB1 = FB2 = 2 V  
INE1 = INE2 = 0 V  
DC  
1.227 1.240 1.253  
120 30  
100*  
V
Input bias  
current  
nA  
dB  
Voltage gain  
AV  
(Continued)  
6
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MB39A104  
(Continued)  
(VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C)  
Value  
Parameter  
Symbol  
Pin No.  
Conditions  
AV = 0 dB  
Unit  
Min Typ Max  
Frequency  
bandwidth  
BW  
9, 16  
1.6*  
MHz  
VOH  
9, 16  
9, 16  
4.7  
4.9  
40  
V
Output voltage  
VOL  
200 mV  
Output source  
current  
ISOURCE  
ISINK  
9, 16  
9, 16  
6, 19  
FB1 = FB2 = 2 V  
FB1 = FB2 = 2 V  
Duty cycle = 0 %  
2  
1  
mA  
µA  
V
Output sink current  
150 200  
VT0  
1.4  
1.5  
2.5  
Threshold voltage  
VT100  
IDTC  
ILIM  
6, 19  
6, 19  
5, 20  
Duty cycle = Dtr  
2.6  
V
Input current  
DTC1 = DTC2 = 0.4 V  
2.0 0.6  
µA  
ILIM terminal input  
current  
RT = 24 k, CT = 100 pF 99  
110 121 µA  
Offset voltage  
Output voltage  
VIO  
5, 20  
1 *  
mV  
VCCVCCVCC−  
VCC = VCCO = 7 V to 19 V  
VH = 0 mA to 30 mA  
VH  
ISOURCE  
ISINK  
2
V
5.5  
5.0  
4.5  
OUT1 to OUT4 = 7 V,  
Duty 5 %  
(t = 1/fOSC×Duty)  
Output source  
current  
3, 22  
3, 22  
300  
mA  
mA  
OUT1 to OUT4 = 12 V,  
Duty 5 %  
(t = 1/fOSC×Duty)  
Output sink current  
350  
ROH  
ROL  
VIH  
3, 22  
3, 22  
24  
OUT1 = OUT2 = 45 mA  
OUT1 = OUT2 = 45 mA  
IC Active mode  
8.0 12.0  
V
V
Output ON  
resistor  
6.5  
50  
9.7  
19  
2
0
CTL input voltage  
VIL  
24  
IC Standby mode  
CTL = 5 V  
0.8  
ICTLH  
24  
100 µA  
Input current  
ICTLL  
24  
CTL = 0 V  
CTL = 0 V  
1
µA  
µA  
Standby current  
ICCS  
1, 17  
0
10  
Power supply  
current  
ICC  
1, 17  
CTL = 5 V  
4.0  
6.0 mA  
*: Standard design value.  
7
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MB39A104  
TYPICAL CHARACTERISTICS  
Power Supply Current vs. Power Supply Voltage  
Reference Voltage vs. Power Supply Voltage  
10  
10  
Ta = +25 °C  
Ta = +25 °C  
CTL = 5 V  
CTL = 5 V  
VREF = 0 mA  
8
8
6
4
2
0
6
4
2
0
0
5
10  
15  
20  
0
5
10  
15  
20  
Power supply voltage VCC (V)  
Power supply voltage VCC (V)  
Reference Voltage vs. Ambient Temperature  
Reference Voltage vs. Ambient Temperature  
2.0  
10  
VCC = 12 V  
Ta = +25 °C  
CTL = 5 V  
1.5  
1.0  
VCC = 12 V  
VREF = 0 mA  
CTL = 5 V  
8
6
4
2
0
0.5  
0.0  
0.5  
1.0  
1.5  
2.0  
40  
20  
0
20  
40  
60  
80  
100  
0
5
10  
15  
20  
25  
30  
35  
Ambient temperature Ta (°C)  
Ambient temperature Ta (°C)  
CTL terminal Current vs. CTL terminal Voltage  
500  
400  
300  
200  
100  
0
10  
9
8
7
6
5
4
3
2
1
0
Ta = +25 °C  
VCC = 12 V  
VREF = 0 mA  
VREF  
ICTL  
0
5
10  
15  
20  
CTL terminal voltage VCTL (V)  
(Continued)  
8
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MB39A104  
Triangular Wave Oscillation Frequency  
vs. Timing Capacitor  
Triangular Wave Oscillation Frequency  
vs. Timing Resistor  
10000  
10000  
Ta = +25 °C  
Ta = +25 °C  
VCC = 12 V  
CTL = 5 V  
VCC = 12 V  
CTL = 5 V  
1000  
1000  
100  
10  
RT = 11 kΩ  
CT = 39 pF  
RT = 24 kΩ  
100  
CT = 560 pF  
RT = 130 kΩ  
RT = 68 kΩ  
CT = 220 pF  
CT = 100 pF  
10  
10  
100  
1000  
10000  
1
10  
100  
1000  
Timing resistor RT (k)  
Timing capacitor CT (pF)  
Triangular Wave Upper and Lower Limit Voltage  
vs. Ambient Temperature  
Triangular Wave Upper and Lower Limit Voltage  
vs. Triangular Wave Oscillation Frequency  
3.2  
3.2  
VCC = 12 V  
Ta = +25 °C  
3.0  
3.0  
2.8  
2.6  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
CTL = 5 V  
VCC = 12 V  
CTL = 5 V  
RT = 24 kΩ  
2.8  
CT = 100 pF  
RT = 47 kΩ  
Upper  
Upper  
2.6  
2.4  
2.2  
2.0  
1.8  
Lower  
1.6  
Lower  
1.4  
1.2  
40 20  
0
20  
40  
60  
80  
100  
0
200 400 600 800 1000 1200 1400 1600  
Ambient temperature Ta ( °C)  
Triangular wave oscillation frequency fOSC (kHz)  
Triangular Wave Oscillation Frequency  
vs. Ambient Temperature  
Triangular Wave Oscillation Frequency  
vs. Power supply voltage  
560  
560  
VCC = 12 V  
CTL = 5 V  
Ta = +25 °C  
CTL = 5 V  
540  
520  
500  
480  
460  
440  
RT = 24 kΩ  
CT = 100 pF  
540  
520  
500  
480  
460  
440  
RT = 24 kΩ  
CT = 100 pF  
40 20  
0
20  
40  
60  
80  
100  
0
5
10  
15  
20  
Ambient temperature Ta ( °C)  
Power supply voltage VCC (V)  
(Continued)  
9
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MB39A104  
(Continued)  
Error Amplifier, Gain, Phase vs. Frequency  
Ta = +25 °C  
VCC = 12 V  
40  
30  
180  
240 kΩ  
AV  
ϕ
20  
90  
10 kΩ  
(15)  
10  
1 µF  
10  
+
0
0
2.4 kΩ  
IN  
9
+
+
11  
(14)  
10  
20  
30  
40  
(16)  
10 kΩ  
OUT  
Error Amp1  
(Error Amp2)  
90  
180  
1.24 V  
100  
1 k  
10 k 100 k  
1 M  
10 M  
Frequency f (Hz)  
Power Dissipation vs. Ambient Temperature  
1000  
800  
740  
600  
400  
200  
0
40  
20  
0
20  
40  
60  
80  
100  
Ambient temperature Ta ( °C)  
10  
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MB39A104  
FUNCTIONS  
1. DC/DC Converter Functions  
(1) Reference voltage block (REF)  
The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) from the  
voltage supplied from the power supply terminal (pin 7). The voltage is used as the reference voltage for the  
IC’s internal circuitry.  
The reference voltage can supply a load current of up to 1 mA to an external device through the VREF terminal  
(pin 17).  
(2) Triangular-wave oscillator block (OSC)  
The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to  
the CT terminal (pin 13) and RT terminal (pin 12) to generate triangular oscillation waveform amplitude of 1.5 V  
to 2.5 V.  
The triangular waveforms are input to the PWM comparator in the IC.  
(3) Error amplifier block (Error Amp1, Error Amp2)  
The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition,  
an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to  
inverted input terminal of the error amplifier, enabling stable phase compensation to the system.  
Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the  
CS1 terminal (pin 11) and CS2 terminal (pin 14) which are the non-inverted input terminal for Error Amp. The  
use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that  
is independent of the output load on the DC/DC converter.  
(4) PWM comparator block (PWM Comp.)  
The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/  
output voltage.  
The comparator keeps output transistor on while the error amplifier output voltage remain higher than the  
triangular wave voltage.  
(5) Output block  
The output block is in the totem pole configuration, capable of driving an external P-channel MOS FET.  
(6) Bias voltage block (VH)  
This bias voltage circuit outputs VCC 5 V(Typ) as minimum potential of the output circuit. In standby mode, this  
circuit outputs the potential equal to VCC.  
11  
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MB39A104  
2. Control Function  
When CTL terminal (pin 24) is “L” level, IC becomes the standby mode. The power supply current is 10 µA (Max)  
at the standby mode.  
On/Off Setting Conditions  
CTL  
L
Power  
OFF (Standby)  
ON (Operating)  
H
3. Protective Functions  
(1) Timer-latch overcurrent protection circuit block (OCP)  
The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an  
overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the  
external FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP con-nected to the  
CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, latch is set  
and OUT terminlas (pin 3,22) of each channel are fixed at “H” level. And the circuit sets the latch to turn off the  
external FET. The detection current value can be set by resistor RLIM1 connected between the FET’s drain and  
the ILIM1 terminal (pin 5) and resistor RLIM2 connected between the drain and the ILIM2 terminal (pin 20).  
Changing connection enables to detect overcurrent at current sense resistor.  
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal  
(pin 6) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “1. Setting Timer-  
Latch Overcurrent Protection Detection Current” in “ABOUT TIMER-LATCH PROTECTION CIRCUIT”.)  
(2) Timer-latch short-circuit protection circuit (SCP Logic, SCP Comp.)  
The short-circuit detection comparator (SCP Comp.) detects the output voltage level of Error Amp, and if the  
error amp output voltage of any channel falls below the short-circuit detection voltage (3.1 V Typ), the timer  
circuits are actuated to start charging the external capacitor CSCP connected to the CSCP terminal (pin 8).  
When the capacitor voltage reaches about 0.73 V, the circuit is turned off the output transistor and sets the dead  
time to 100 %.  
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal  
(pin 24) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (See “2. Setting Time  
Constant for Timer-Latch Short-Circuit Protection Circuit” in “ABOUT TIMER-LATCH PROTECTION CIR-  
CUIT”.)  
(3) Under voltage lockout protection circuit (UVLO)  
The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned  
on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent such  
malfunctions, undervoltagelockoutprotectioncircuitdetectsadecreaseininternalreferencevoltagewithrespect  
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the  
CSCP terminal (pin 8) at the “L” level.  
The circuit restores the output transistor to normal when the supply voltage reaches the threshold voltage of the  
undervoltage lockout protection circuit.  
(4) Protection circuit operating function table  
This table refers to output condition when protection circuit is operating.  
Operating circuit  
Overcurrent protection circuit  
Short-circuit protection circuit  
Under-voltage lockout  
CS1  
CS2  
OUT1  
OUT2  
L
L
L
L
L
L
H
H
H
H
H
H
12  
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MB39A104  
SETTING THE OUTPUT VOLTAGE  
• Output Voltage Setting Circuit  
VO  
R1  
(INE2)  
INE1  
15  
10  
Error Amp  
+
+
1.24  
R2  
VO (V) =  
(R1 + R2)  
R2  
1.24 V  
(CS2)  
CS1  
14  
11  
SETTING THE TRIANGULAR OSCILLATION FREQUENCY  
The triangular oscillation frequency is determined by the timing capacitor (CT) connected to the CT terminal (pin  
13), and the timing resistor (RT) connected to the RT terminal (pin 12).  
Moreover, it shifts more greatly than the caluculated values according to the constant of timing resistor (RT) when  
the triangular wave oscillation frequency exceeds 1 MHz. Therefore, set it referring to “Triangular Wave Oscillation  
Frequency vs. Timing Resistor” and “Triangular Wave Oscillation Frequency vs. Timing Capacitor” in “TYPICAL  
CHARACTERISTICS”.  
Triangular oscillation frequency : fOSC  
1200000  
fOSC (kHz) =:  
CT (pF) RT (k)  
13  
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MB39A104  
SETTING THE SOFT-START AND DISCHARGE TIMES  
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors  
(CS1 and CS2) to the CS1 terminal (pin 11) for channel 1 and the CS2 terminal (pin 14) for channel 2, respectively.  
When CTL terminal (pin 24) goes to “H” level and IC starts (VCC UVLO threshold voltage), the external soft-  
start capacitors (CS1 and CS2) connected to CS1 and CS2 terminals are charged at 10 µA. The error amplifier  
output (FB1 (pin 9) , FB2 (pin 16) ) is determined by comparison between the lower one of the potentials at two  
non-inverted input terminals (1.24 V, CS1 terminal voltages) and the inverted input terminal voltage (INE1 (pin  
10) voltage, INE2 (pin 15) voltage).  
The FB1 (FB2) terminal voltage is decided for the soft-start period by the comparison between 1.24 V in an  
internal reference voltage and the voltages of the CS1 (CS2) terminal. The DC/DC converter output voltage  
rises in proportion to the CS1 (CS2) terminal voltage as the soft-start capacitor connected to the CS1 (CS2)  
terminal is charged.  
The soft-start time is obtained from the following formula:  
Soft-start time: ts (time to output 100%)  
ts (s)=: 0.124 × CS (µF)  
CS1 (CS2) terminal voltage  
=: 5 V  
Error Amp block INE1 (INE2) voltage  
=: 1.24 V  
=: 0 V  
t
Soft-start time (ts)  
14  
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MB39A104  
• Soft-Start Circuit  
VREF  
V
O
R1  
R2  
10 µA  
INE1  
10  
15  
(INE2)  
L priority  
Error Amp  
CH ON/OFF signal  
L : ON, H : OFF  
+
+
11  
14  
CS1  
(CS2)  
CS1  
1.24 V  
(CS2)  
FB1  
9
16  
(FB2)  
UVLO  
15  
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MB39A104  
TREATMENT WITHOUT USING CS TERMINAL  
When not using the soft-start function, open the CS1 terminal (pin 11) and the CS2 terminal (pin 14) .  
Without Setting Soft-Start Time  
“OPEN”  
“OPEN”  
14  
CS2  
11  
CS1  
16  
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MB39A104  
ABOUT TIMER-LATCH PROTECTION CIRCUIT  
1. Setting Timer-Latch Overcurrent Protection Detection Current  
The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent  
flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET  
ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP  
terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the  
latch to fix OUT terminals (pin 3, 22) at “H” level and turn off the external FET. The detection current value can  
be set by the resistors (RLIM1 and RLIM2) connected between the FET’s drain and the ILIM1 terminal (pin 5) and  
between the drain and the ILIM2 terminal (pin 20), respectively.  
The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 12).  
Time until activating timer circuit and setting latch is equal to short-circuit detection time in "2. Setting Time  
Constant for Timer-Latch Short-Circuit Protection Circuit".  
Internal current value: ILIM  
2700  
ILIM (µA) =:  
RT (k)  
Detection current value: IOCP  
ILIM(A) × RLIM()  
RON ()  
(VIN(V) VO(V)) × VO(V)  
2 × VIN(V) × fOSC(Hz) × L(H)  
IOCP (A) =:  
RLIM : Overcurrent detection resistor  
RON : External FET ON resistor  
VIN : Input voltage  
VO : DC/DC converter output voltage  
fOSC : Oscillation frequency  
L
: Coil inductance  
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal  
(pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less.  
• Overcurrent detection circuit  
VIN  
Q1  
L
(VS2)  
VS1  
21  
4
VO  
(ILIM2)  
+
Current  
Protection  
Logic  
20  
ILIM1  
(RLIM)  
5
(1 µA)  
Each  
Channel  
Drive  
CSCP  
8
VREF  
UVLO  
S
Latch  
R
17  
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MB39A104  
Overcurrent Protection Circuit: Range of Operation  
When an overcurrent flow occurs, if the increased voltage between the drain and source of the FET is detected  
by means of the external FET (Q1) resistor, operational stability is lost when the external FET (Q1) ON interval  
determined by the oscillation frequency, input voltage, and output voltage falls below 450 ns.  
Therefore, the circuit should be used within a range that ensures that the ON interval does not fall below 450ns,  
according to the following formula.  
VO (V)  
ON interval 450 (ns) ≥  
VIN (V) × fOSC (Hz)  
If the ON interval of the external FET (Q1) is below 450ns, we recommend the use of an overcurrent detection  
resistor RS to detect overcurrent, as shown below.  
This example shows the range of operation of the overcurrent detection function with a setting of Vo = 3.3V.  
Method to detect by current when external FET(Q1) is turned on  
Overcurrent Detection Function Operating Range  
1600  
VIN  
(Rs)  
ErrAmp  
Q1  
1400  
VO = set to 3.3 V  
(VS2)  
1200  
1000  
800  
400  
200  
0
21  
4
VS1  
Operation Range  
(ILIM2)  
20  
+
ILIM1  
ConnecttoRS  
when  
5
using RS  
6
8
10  
12  
14  
16  
18  
20  
VCC (V)  
Method to detect by mean current  
Overcurrent Detection Function Operating Range  
VIN  
ErrAmp  
1600  
RS  
Q1  
1400  
VO = set to 3.3 V  
(VS2)  
21  
1200  
VS1  
4
1000  
800  
Operation Range  
600  
400  
200  
0
(ILIM2)  
+
20  
ILIM1  
5
6
8
10  
12  
14  
16  
18  
20  
VCC (V)  
18  
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MB39A104  
2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit  
Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifiers  
output level to the reference voltage (3.1 V Typ).  
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output  
remains at “L” level, and the CSCP terminal (pin 8) is held at “L” level.  
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage  
to drop, the output of the short-circuit detection comparator goes to “H” level. This causes the external short-  
circuit protection capacitor CSCP connected to the CSCP terminal to be charged at 1 µA.  
Short-circuit detection time (tSCP)  
tSCP (s) =: 0.73 × CSCP (µF)  
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.73 V), the latch is set and the external  
FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal is  
held at “L” level. If a short-circuit is detected on either of the two channels, both channels are shut off.  
When the power supply is turned on back or VREF terminal (pin 17) voltage is less than 2.4 V (Min) by setting  
CTL terminal (pin 24) to “L” level, the latch is released.  
Timer-latch short-circuit protection circuit  
(FB2)  
16  
9
VO  
FB1  
R1  
R2  
(INE2)  
INE1  
15  
10  
Error  
Amp  
+
(1.24 V)  
SCP  
Comp.  
+
+
(3.1 V)  
(1 µA)  
To each channel  
Drive  
CSCP  
8
VREF  
UVLO  
S
R
Latch  
19  
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MB39A104  
TREATMENT WITHOUT USING CSCP TERMINAL  
When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 8) to GND with  
the shortest distance.  
Treatment without using CSCP  
18  
GND  
8
CSCP  
RESETTING THE LATCH OF EACH PROTECTION CIRCUIT  
When the overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch to fix the output  
at the "L" level.  
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal  
(pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less.  
20  
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MB39A104  
I/O EQUIVALENT CIRCUIT  
⟨⟨Reference voltage block⟩⟩  
⟨⟨Control block⟩⟩  
⟨⟨Soft-start block⟩⟩  
VREF  
(5.0 V)  
VCC  
CSX  
7
VCC  
24  
CTL  
+
1.24 V  
72  
kΩ  
VREF  
17  
77.8  
kΩ  
104  
kΩ  
24.8  
kΩ  
GND  
GND  
18  
GND  
⟨⟨Triangular wave oscillator  
block (RT) ⟩⟩  
⟨⟨Triangular wave oscillator  
(CT) block⟩⟩  
⟨⟨Short-circuit detection block⟩⟩  
VCC  
VREF  
(5.0 V)  
(3.1 V)  
(3.1 V)  
2 kΩ  
+
1.35 V  
CT  
13  
CSCP  
8
RT  
12  
GND  
VCC  
GND  
GND  
⟨⟨Overcurrent protection circuit block⟩⟩  
⟨⟨Error amplifier block (CH1, CH2) ⟩⟩  
VCCO  
VCC  
ILIMX  
VSX  
VREF  
(5.0 V)  
INEX  
CSX  
1.24 V  
FBX  
GND  
GND  
GNDO  
⟨⟨PWM comparator  
block (CH1, CH2) ⟩⟩  
⟨⟨Bias voltage block⟩⟩  
⟨⟨Output block (CH1, CH2) ⟩⟩  
VCC  
VCC  
VCCO  
VCCO  
1
O
FBX  
CT  
VH  
DTCX  
2
VH  
23  
GNDO  
GND  
GND  
GNDO  
X : Each channel No.  
21  
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MB39A104  
APPLICATION EXAMPLE  
22  
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MB39A104  
PARTS LIST  
COMPONENT  
Q1, Q2  
ITEM  
Pch FET  
Diode  
SPECIFICATION  
VDS = 30 V, ID = 6 A  
VENDOR  
TOSHIBA  
ROHM  
PARTS No.  
TPC8102  
D1, D2  
VF = 0.42 V (Max) , at IF = 3 A  
RB0530L-30  
CDRH104R-150  
L1, L2  
Inductor  
15 µH  
3.6 A, 50 mΩ  
SUMIDA  
C1  
Ceramics Condenser  
OS-CONTM  
100 pF  
10 µF  
10 µF  
50 V  
20 V  
25 V  
6.3 V  
50 V  
50 V  
50 V  
TDK  
SANYO  
TDK  
C1608CH1H101J  
20SVP10M  
C2, C6  
C3, C7  
C4, C8  
Ceramics Condenser  
OS-CONTM  
C3225JF1E106Z  
6SVP82M  
82 µF  
SANYO  
TDK  
C10, C11, C20 Ceramics Condenser  
C12, C14, C21 Ceramics Condenser  
0.1 µF  
1000 pF  
0.1 µF  
C1608JB1H104K  
C1608JB1H102K  
C1608JB1H104K  
TDK  
C16, C17  
Ceramics Condenser  
TDK  
R1  
R4, R5  
R8, R13  
R9, R14  
R10  
Resistor  
Resistor  
Resistor  
Resistor  
Resistor  
Resistor  
Resistor  
Resistor  
24 kΩ  
2.7 kΩ  
220 kΩ  
68 kΩ  
150 kΩ  
56 kΩ  
0.5 %  
0.5 %  
0.5 %  
0.5 %  
0.5 %  
0.5 %  
0.5 %  
0.5 %  
ssm  
ssm  
ssm  
ssm  
ssm  
ssm  
ssm  
ssm  
RR0816P-243-D  
RR0816P-272-D  
RR0816P-224-D  
RR0816P-683-D  
RR0816P-154-D  
RR0816P-563-D  
RR0816P-104-D  
RR0816P-133-D  
R11  
R15  
100 kΩ  
13 kΩ  
R16  
Note : TOSHIBA : TOSHIBA Corporation  
ROHM : ROHM Co., Ltd  
SANYO : SANYO Electric Co., Ltd.  
TDK  
SUMIDA : SUMIDA Electric Co., Ltd.  
ssm : SUSUMU Co., Ltd.  
: TDK Corporation  
23  
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MB39A104  
SELECTION OF COMPONENTS  
• Pch MOS FET  
The P-ch MOSFET for switching use should be rated for at least 20% more than the maximum input voltage. To  
minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and  
high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered.  
In this application, the Toshiba TPC8102 is used. Continuity loss, on/off switching loss, and total loss are deter-  
mined by the following formulas. The selection must ensure that peak drain current does not exceed rated values,  
and also must be in accordance with overcurrent detection levels.  
Continuity loss : PC  
2
PC = ID × RDS (ON) × Duty  
On-cycle switching loss : PS (ON)  
VD (Max) × ID × tr × fOSC  
PS (ON) =  
6
Off-cycle switching loss : PS (OFF)  
VD (Max) × ID (Max) × tf × fOSC  
PS (OFF) =  
6
Total loss : PT  
PT = PC + PS (ON) + PS (OFF)  
Example: Using the Toshiba TPC8102  
CH1  
Input voltage VIN (Max) = 19 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz,  
L = 15 µH, drain-source on resistance RDS (ON) =: 50 m, tr = tf=: 100 ns.  
Drain current (Max) : ID (Max)  
VIN VO  
ID (Max) = IO +  
ton  
2L  
19 5  
1
= 3 +  
×
×
× 0.263  
2 × 15 × 106  
500 × 103  
=: 3.25 (A)  
Drain current (Min) : ID (Min)  
VIN VO  
ID (Min) = IO −  
ton  
2L  
19 5  
2 × 15 × 106  
1
= 3 −  
× 0.263  
500 × 103  
=: 2.75 (A)  
24  
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MB39A104  
2
PC = ID × RDS (ON) × Duty  
= 3 2 × 0.05 × 0.263  
=: 0.118 W  
VD (Max) × ID × tr × fOSC  
PS (ON)  
=
=
6
19 × 3 × 100 × 109 × 500 × 103  
6
=: 0.475 W  
VD (Max) × ID (Max) × tf × fOSC  
PS (OFF)  
=
6
19 × 3.25 × 100 × 109 × 500 × 103  
=
6
=: 0.515 W  
PT  
= PC + PS (ON) + PS (OFF)  
=: 0.118 + 0.475 + 0.515  
=: 1.108 W  
The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) .  
CH2  
Input voltage VIN (Max) = 19 V output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency  
fOSC = 500 kHz, L = 15 µH, drain-source on resistance RDS (ON) =: 50 m, tr = tf=: 100 ns.  
Drain current (Max) : ID (Max)  
VIN VO  
ID (Max) = IO +  
ton  
2L  
19 3.3  
1
= 3 +  
×
×
× 0.174  
2 × 15 × 106  
500 × 103  
=: 3.18 (A)  
Drain current (Min) : ID (Min)  
VIN VO  
ID (Min) = IO −  
ton  
2L  
19 3.3  
1
= 3 −  
× 0.174  
2 × 15 × 106  
500 × 103  
=: 2.82 (A)  
25  
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MB39A104  
2
PC = ID × RDS (ON) × Duty  
=
3 2 × 0.05 × 0.174  
=: 0.078 W  
VD (Max) × ID × tr × fOSC  
PS (ON)  
=
=
6
19 × 3 × 100 × 109 × 500 × 103  
6
=: 0.475 W  
VD (Max) × ID (Max) × tf × fOSC  
PS (OFF)  
=
=
6
19 × 3.18 × 100 × 109 × 500 × 103  
6
=: 0.504 W  
PT = PC + PS (ON) + PS (OFF)  
=: 0.078 + 0.475 + 0.504  
=: 1.057 W  
The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) .  
• Inductors  
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor,  
but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous  
operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value,  
which will enable continuous operation under light loads. Note that if the inductance value is too high, however,  
direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at  
the point where efficiency is greatest.  
Note also that the DC superimposition characteristics become worse as the load current value approaches the  
rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing  
loss of efficiency. The selection of rated current value and inductance value will vary depending on where the  
point of peak efficiency lies with respect to load current.  
Inductance values are determined by the following formulas.  
The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the  
load current or less.  
Inductance value : L  
2 (VIN VO)  
L ≥  
ton  
IO  
26  
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MB39A104  
Example:  
CH1  
2 (VIN VO)  
L ≥  
ton  
IO  
2 × (19 5)  
1
×
× 0.263  
IO  
500 × 103  
4.91 µH  
CH2  
2 (VIN VO)  
L ≥  
ton  
IO  
2 × (19 3.3)  
1
×
× 0.174  
IO  
500 × 103  
3.64 µH  
Inductance values derived from the above formulas are values that provide sufficient margin for continuous  
operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore  
necessary to determine the load level at which continuous operation becomes possible. In this application, the  
Sumida CDRH104R-150 is used. At 15 µH, the load current value under continuous operating conditions is  
determined by the following formula.  
Load current value under continuous operating conditions : IO  
VO  
2L  
IO ≥  
toff  
Example: Using the CDRH104R-150  
15 µH (allowable tolerance ±30%) , rated current = 3.6 A  
CH1  
VO  
2L  
IO ≥  
toff  
5
1
×
× (1 0.263)  
2 × 15 × 106  
500 × 103  
245.7 mA  
CH2  
VO  
toff  
2L  
IO  
3.3  
1
× (1 0.174)  
2 × 15 × 106 × 500 × 103  
181.7 mA  
27  
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MB39A104  
To determine whether the current through the inductor is within rated values, it is necessary to determine the  
peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output  
ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following  
formulas.  
Peak value : IL  
VIN VO  
IL IO +  
ton  
2L  
Peak-to-peak value : IL  
VIN VO  
IL =  
ton  
L
Example: Using the CDRH104R-150  
15 µH (allowable tolerance ±30%) , rated current = 3.6 A  
Peak value:  
CH1  
VIN VO  
ton  
IL IO +  
2L  
19 5  
1
× 0.263  
3 +  
2 × 15 × 106 × 500 × 103  
3.25 A  
CH2  
VIN VO  
IL IO +  
ton  
2L  
19 3.3  
1
3 +  
×
× 0.174  
2 × 15 × 106  
500 × 103  
3.18 A  
Peak-to-peak value:  
CH1  
VIN VO  
IL =  
ton  
L
19 5  
1
=
× 0.263  
15 × 106 × 500 × 103  
= 0.491 A  
CH2  
VIN VO  
IL =  
ton  
L
19 3.3  
1
=
×
× 0.174  
15 × 106  
500 × 103  
= 0.364 A  
28  
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MB39A104  
• Flyback diode  
The flyback diode is generally used as a Shottky barrier diode (SBD) when the reverse voltage to the diode is  
less than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and  
lower forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently  
higher than the input voltage, the average current flowing through the diode is within the average output current  
level, and peak current is within peak surge current limits, there is no problem. In this application the Rohm  
RB053L-30 is used. The diode average current and diode peak current can be calculated by the following  
formulas.  
Diode mean current : IDi  
VO  
VIN  
IDi IO × (1 −  
)
Diode peak current : IDip  
VO  
IDip (IO +  
toff)  
2L  
Example: Using the Rohm RB053L-30  
VR (DC reverse voltage) = 30 V, average output voltage = 3.0 A, peak surge current = 70 A,  
VF (forward voltage) = 0.42 V, IF = 3.0 A  
CH1  
IDi IO × (1 −  
VO  
VIN  
)
3 × (1 0.263)  
2.21 A  
CH2  
IDi IO × (1 −  
VO  
VIN  
)
3 × (1 0.174)  
2.48 A  
CH1  
VO  
2L  
IDip (IO +  
toff)  
toff)  
3.24 A  
CH2  
VO  
2L  
IDip (IO +  
3.18 A  
29  
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MB39A104  
• Smoothing Capacitor  
The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smooth-  
ing capacitor it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher  
ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low  
ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics,  
and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient  
margin for allowable ripple current. This application uses the (OS-CON TM) 6SVP82M made by Sanyo. The ESR,  
capacitance value, and ripple current can be calculated from the following formulas.  
Equivalent Series Resistance : ESR  
VO  
IL  
1
ESR ≤  
2πfCL  
Capacitance value : CL  
IL  
CL  
2πf (VO IL × ESR)  
Ripple current : ICLrms  
(VIN VO) ton  
ICLrms ≥  
23L  
Example: Using the 6SVP82M  
Rated voltage = 6.3 V, ESR = 50 m, maximum allowable ripple current = 1570 mArms  
Equivalent series resistance  
CH1  
VO  
IL  
1
ESR ≤  
2πfCL  
0.050  
0.491  
1
2π × 500 × 103 × 82 × 106  
98.0 mΩ  
30  
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MB39A104  
CH2  
ESR  
VO  
IL  
0.033  
0.364  
1
2πfCL  
1
2π × 500 × 103 × 82 × 106  
86.8 mΩ  
Capacitance value  
CH1  
IL  
CL  
2πf (VO IL × ESR)  
0.491  
2π × 500 × 103 × (0.050 0.491 × 0.05)  
6.14 µF  
CH2  
IL  
CL ≥  
2πf (VO IL × ESR)  
0.364  
2π × 500 × 103 × (0.033 0.364 × 0.05)  
7.83 µF  
Ripple current  
CH1  
(VIN VO) ton  
23L  
(19 5) × 0.263  
23 × 15 × 106 × 500 × 103  
ICLrms ≥  
141.7 mArms  
CH2  
(VIN VO) ton  
ICLrms ≥  
23L  
(19 3.3) × 0.174  
23 × 15 × 106 × 500 × 103  
105.1 mArms  
31  
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MB39A104  
REFERENCE DATA  
TOTAL Efficiency vs. Input Voltage  
100  
90  
80  
70  
60  
50  
40  
Vin = 7 V  
Vin = 10 V  
Vin = 12 V  
Vin = 19 V  
Ta = +25 °C  
5 V Output  
SW1 = OFF  
SW2 = ON  
30  
10 m  
100 m  
1
10  
Input voltage VIN (V)  
Each CH Efficiency vs. Input Voltage  
100  
90  
80  
70  
60  
50  
40  
Vin = 7 V  
Vin = 10 V  
Vin = 12 V  
Vin = 19 V  
Ta = +25 °C  
3.3 V Output  
SW1 = ON  
SW2 = OFF  
30  
10 m  
100 m  
1
10  
Input voltage VIN (V)  
(Continued)  
32  
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MB39A104  
(Continued)  
Switching Wave Form (CH1)  
VG (V)  
Ta = +25 °C  
VIN = 12 V  
CTL = 5 V  
VO = 5 V  
15  
10  
5
RL = 1.67 Ω  
0
VS (V)  
15  
10  
5
0
0
1
2
3
4
5
6
7
8
9
10  
t (µs)  
Switching Wave Form (CH2)  
VG (V)  
Ta = +25 °C  
VIN = 12 V  
CTL = 5 V  
VO = 3.3 V  
RL = 1.1 Ω  
15  
10  
5
0
VS (V)  
15  
10  
5
0
0
1
2
3
4
5
6
7
8
9
10  
t (µs)  
33  
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MB39A104  
USAGE PRECAUTION  
Printed circuit board ground lines should be set up with consideration for common impedance.  
Take appropriate static electricity measures.  
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.  
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.  
• Work platforms, tools, and instruments should be properly grounded.  
• Working personnel should be grounded with resistance of 250 kto 1 Mbetween body and ground.  
Do not apply negative voltages.  
The use of negative voltages below –0.3 V may create parasitic transistors on LSI lines, which can cause  
abnormal operation.  
ORDERING INFORMATION  
Part number  
Package  
Remarks  
24-pin plastic SSOP  
(FPT-24P-M03)  
MB39A104PFV  
34  
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MB39A104  
PACKAGE DIMENSIONS  
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) MAX) .  
Note 2) *2 : These dimensions do not include resin protrusion.  
Note 3) Pins width and pins thickness include plating thickness.  
Note 4) Pins width do not include tie bar cutting remainder.  
24-pin plastic SSOP  
(FPT-24P-M03)  
1
0.17±0.03  
(.007±.001)  
*
7.75±0.10(.305±.004)  
24  
13  
*25.60±0.10 7.60±0.20  
(.220±.004) (.299±.008)  
INDEX  
Details of "A" part  
1.25 +0.20  
–0.10  
–.004  
(Mounting height)  
.049 +.008  
0.25(.010)  
0~8˚  
"A"  
1
12  
0.24 +0.08  
.009 +.003  
–0.07  
0.65(.026)  
M
0.13(.005)  
–.003  
0.50±0.20  
0.10±0.10  
(.020±.008)  
(.004±.004)  
(Stand off)  
0.60±0.15  
(.024±.006)  
0.10(.004)  
C
2003 FUJITSU LIMITED F24018S-c-4-5  
Dimensions in mm (inches)  
Note : The values in parentheses are reference values.  
35  
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MB39A104  
FUJITSU LIMITED  
All Rights Reserved.  
The contents of this document are subject to change without notice.  
Customers are advised to consult with FUJITSU sales  
representatives before ordering.  
The information, such as descriptions of function and application  
circuit examples, in this document are presented solely for the  
purpose of reference to show examples of operations and uses of  
Fujitsu semiconductor device; Fujitsu does not warrant proper  
operation of the device with respect to use based on such  
information. When you develop equipment incorporating the  
device based on such information, you must assume any  
responsibility arising out of such use of the information. Fujitsu  
assumes no liability for any damages whatsoever arising out of  
the use of the information.  
Any information in this document, including descriptions of  
function and schematic diagrams, shall not be construed as license  
of the use or exercise of any intellectual property right, such as  
patent right or copyright, or any other right of Fujitsu or any third  
party or does Fujitsu warrant non-infringement of any third-party’s  
intellectual property right or other right by using such information.  
Fujitsu assumes no liability for any infringement of the intellectual  
property rights or other rights of third parties which would result  
from the use of information contained herein.  
The products described in this document are designed, developed  
and manufactured as contemplated for general use, including  
without limitation, ordinary industrial use, general office use,  
personal use, and household use, but are not designed, developed  
and manufactured as contemplated (1) for use accompanying fatal  
risks or dangers that, unless extremely high safety is secured, could  
have a serious effect to the public, and could lead directly to death,  
personal injury, severe physical damage or other loss (i.e., nuclear  
reaction control in nuclear facility, aircraft flight control, air traffic  
control, mass transport control, medical life support system, missile  
launch control in weapon system), or (2) for use requiring  
extremely high reliability (i.e., submersible repeater and artificial  
satellite).  
Please note that Fujitsu will not be liable against you and/or any  
third party for any claims or damages arising in connection with  
above-mentioned uses of the products.  
Any semiconductor devices have an inherent chance of failure. You  
must protect against injury, damage or loss from such failures by  
incorporating safety design measures into your facility and  
equipment such as redundancy, fire protection, and prevention of  
over-current levels and other abnormal operating conditions.  
If any products described in this document represent goods or  
technologies subject to certain restrictions on export under the  
Foreign Exchange and Foreign Trade Law of Japan, the prior  
authorization by Japanese government will be required for export  
of those products from Japan.  
F0308  
FUJITSU LIMITED Printed in Japan  
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