STK11C88
256 Kbit (32K x 8) SoftStore nvSRAM
Features
Functional Description
■
■
■
■
■
■
■
■
■
■
■
■
25 ns and 45 ns access times
The Cypress STK11C88 is a 256 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap™ technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under Software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
Pin compatible with industry standard SRAMs
Software initiated STORE and RECALL
Automatic RECALL to SRAM on power up
Unlimited Read and Write endurance
Unlimited RECALL cycles
1,000,000 STORE cycles
100 year data retention
Single 5V+10% power supply
Commercial and Industrial Temperatures
28-pin (300 mil and 330 mil) SOIC packages
RoHS compliance
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-50591 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 29, 2009
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STK11C88
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
Device Operation
The STK11C88 is a versatile memory chip that provides several
modes of operation. The STK11C88 can operate as a standard
32K x 8 SRAM. A 32K x 8 array of nonvolatile storage elements
shadow the SRAM. SRAM data can be copied from nonvolatile
memory or nonvolatile data can be recalled to the SRAM.
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
tSTORE cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
SRAM Read
The STK11C88 performs a READ cycle whenever CE and OE
are LOW, while WE is HIGH. The address specified on pins
A0–14 determines the 32,768 data bytes accessed. When the
READ is initiated by an address transition, the outputs are valid
after a delay of tAA (READ cycle 1). If the READ is initiated by
CE or OE, the outputs are valid at tACE or at tDOE, whichever is
later (READ cycle 2). The data outputs repeatedly respond to
address changes within the tAA access time without the need for
transitions on any control input pins, and remain valid until
another address change or until CE or OE is brought HIGH.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common IO pins DQ0–7
are written into the memory if it has valid tSD, before the end of
a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C88 software STORE
cycle is initiated by executing sequential CE controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC<VRESET),
an internal RECALL request is latched. When VCC once again
exceeds the sense voltage of VSWITCH, a RECALL cycle is
automatically initiated and takes tHRECALL to complete.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
If the STK11C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
To initiate the software STORE cycle, the following READ
sequence is performed:
and system VCC or between CE and system VCC
.
Document Number: 001-50591 Rev. **
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STK11C88
Figure 3. Icc (max) Writes
Hardware Protect
The STK11C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage
conditions. When VCC<VSWITCH
,
all externally initiated
STORE operations and SRAM WRITEs are inhibited.
Noise Considerations
The STK11C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals help prevent
noise problems.
Low Average Active Power
CMOS technology provides the STK11C88 the benefit of
drawing significantly less current when it is cycled at times
between ICC and READ or WRITE cycle time. Worst case
current consumption is shown for both CMOS and TTL input
levels (commercial temperature range, VCC = 5.5V, 100
percent duty cycle on chip enable). Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the STK11C88 depends on the following items:
Best Practices
nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, the experience gained working with hundreds of appli-
cations has resulted in the following suggestions as best
practices:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The VCC level
■
The nonvolatile cells in a nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that a NV
array is in a set programmed state. Routines that check
memory content values to determine first time system config-
uration and cold or warm boot status, should always program
a unique NV pattern (for example, a complex 4-byte pattern
of 46 E6 49 53 hex or more random bytes) as part of the final
system manufacturing test to ensure these system routines
work consistently.
7. IO loading
Figure 2. Icc (max) Reads
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the nvSRAM
into the desired state as a safeguard against events that
might flip the bit inadvertently (program bugs or incoming
inspection routines).
Document Number: 001-50591 Rev. **
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STK11C88
Table 2. Software STORE/RECALL Mode Selection
A13 – A0
Mode
IO
Notes
CE
L
WE
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Nonvolatile STORE
L
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Nonvolatile RECALL
Notes
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
2. While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
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STK11C88
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V
Power Dissipation ......................................................... 1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Temperature under bias..............................–55°C to +125°C
Supply Voltage on VCC Relative to GND.......... –0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to VCC + 0.5V
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
4.5V to 5.5V
4.5V to 5.5V
-40°C to +85°C
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
Parameter
ICC1
Description
Test Conditions
Min
Max Unit
Average VCC Current tRC = 25 ns
Commercial
Industrial
97
70
mA
mA
t
RC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
100
70
mA
mA
I
OUT = 0 mA.
Average VCC Current All Inputs Do Not Care, VCC = Max
during STORE Average current for duration tSTORE
Average VCC Current WE > (VCC – 0.2V). All other inputs cycling.
ICC2
ICC3
3
mA
mA
10
at tRC= 200 ns, 5V,
25°C Typical
Dependent on output loading and cycle rate. Values obtained
without output loads.
[3]
ISB1
Average VCC Current tRC=25ns, CE > VIH
Commercial
30
22
mA
mA
μA
(Standby, Cycling
TTL Input Levels)
tRC=45ns, CE > VIH
Industrial
31
23
[3]
ISB2
VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
(Standby, Stable
750
CMOS Input Levels)
IIX
Input Leakage
Current
VCC = Max, VSS < VIN < VCC
-1
-5
+1
+5
μA
μA
V
IOZ
VIH
VIL
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
Input HIGH Voltage
2.2
VCC
0.5
+
Input LOW Voltage
VSS
0.5
–
0.8
V
VOH
VOL
Output HIGH Voltage IOUT = –4 mA
Output LOW Voltage IOUT = 8 mA
2.4
V
V
0.4
Data Retention and Endurance
Parameter
DATAR
Description
Min
100
Unit
Data Retention
Years
K
NVC
Nonvolatile STORE Operations
1,000
Note
3. CE > V will not produce standby current levels until any nonvolatile cycle in progress has timed out.
IH
Document Number: 001-50591 Rev. **
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STK11C88
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0 V
Max
5
Unit
pF
CIN
V
COUT
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[4]
28-SOIC
(300 mil)
28-SOIC
(330 mil)
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Figure 4. AC Test Loads
R1 480Ω
5.0V
Output
R2
30 pF
255Ω
AC Test Conditions
Input Pulse Levels..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
4. These parameters are guaranteed by design and are not tested.
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STK11C88
AC Switching Characteristics
SRAM Read Cycle
Parameter
25 ns
45 ns
Description
Unit
Cypress
Alt
Min
Max
Min
Max
Parameter
tACE
tELQV
tAVAV, ELEH
tAVQV
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
t
25
45
[6]
tAA
tDOE
Address Access Time
25
10
45
20
tGLQV
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
[6]
tOHA
tAXQX
5
5
5
5
[7]
[7]
[7]
[7]
tLZCE
tHZCE
tLZOE
tHZOE
tELQX
tEHQZ
10
10
25
15
15
45
tGLQX
0
0
0
0
tGHQZ
[4]
tPU
tELICCH
tEHICCL
[4]
tPD
Switching Waveforms
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W2+$
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'$7$ꢌ9$/,'
W5&
$''5(66
&(
W$&(
W3'
W+=&(
W/=&(
2(
W+=2(
W'2(
W/=2(
'4ꢌꢊ'$7$ꢌ287ꢋ
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W38
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,&&
Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < V and WE > V ; device is continuously selected.
IL
IH
7. Measured ±200 mV from steady state output voltage.
Document Number: 001-50591 Rev. **
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STK11C88
SRAM Write Cycle
Parameter
25 ns
45 ns
Description
Write Cycle Time
Unit
Cypress
Alt
Min
Max
Min
Max
Parameter
tWC
tAVAV
tWLWH, WLEH
tELWH, ELEH
tDVWH, DVEH
tWHDX, EHDX
tAVWH, AVEH
tAVWL, AVEL
tWHAX, EHAX
tWLQZ
tWHQX
25
20
20
10
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWE
tSCE
tSD
t
Write Pulse Width
t
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
t
tHD
tAW
tSA
tHA
t
t
20
0
30
0
t
t
0
0
tHZWE
tLZWE
10
15
5
5
Switching Waveforms
tWC
ADDRESS
CE
tHA
tSCE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
tWC
ADDRESS
tHA
tSCE
tSA
CE
WE
tAW
tPWE
tSD
tHD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9.
CE or WE must be greater than V during address transitions.
IH
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STK11C88
STORE INHIBIT or Power Up RECALL
STK11C88
Parameter
Alt
Description
Unit
Min
Max
[10]
tHRECALL
tRESTORE
tHLHZ
Power up RECALL Duration
STORE Cycle Duration
550
10
μs
ms
V
[6]
tSTORE
VRESET
Low Voltage Reset Level
Low Voltage Trigger Level
3.6
4.5
VSWITCH
4.0
V
Switching Waveforms
Figure 9. STORE INHIBIT/Power Up RECALL
VCC
5V
VSWITCH
VRESET
STORE INHIBIT
POWER-UP RECALL
t
HRECALL
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
RESET
RESET
SWITCH
Notes
10. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
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STK11C88
Software Controlled STORE/RECALL Cycle
25 ns
45 ns
Parameter
tRC
Alt
Description
Unit
Min
25
0
Max
Min
45
0
Max
tAVAV
tAVEL
tELEH
tELAX
STORE/RECALL Initiation Cycle Time
Address Setup Time
ns
ns
ns
ns
μs
[11]
tSA
tCW
Clock Pulse Width
20
20
30
20
[11]
tHACE
Address Hold Time
tRECALL
RECALL Duration
20
20
Switching Waveforms
tRC
tRC
ADDRESS # 1
ADDRESS # 6
ADDRESS
CE
tSA
tSCE
tHACE
OE
t
STORE / tRECALL
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA)
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50591 Rev. **
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STK11C88
Part Numbering Nomenclature
STK11C88 - N F 25 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
Blank - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Speed:
25 - 25 ns
45 - 45 ns
Lead Finish
F = 100% Sn (Matte Tin)
Package:
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 330 mil SOIC
Ordering Information
Speed
Operating
Range
Ordering Code
(ns)
Package Diagram
Package Type
25
STK11C88-NF25TR
STK11C88-NF25
51-85026
51-85026
51-85058
51-85058
51-85026
51-85026
51-85058
51-85058
51-85026
51-85026
51-85058
51-85058
51-85026
51-85026
51-85058
51-85058
28-Pin SOIC (300 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (300 mil)
28-Pin SOIC (330 mil)
28-Pin SOIC (330 mil)
Commercial
STK11C88-SF25TR
STK11C88-SF25
STK11C88-NF25ITR
STK11C88-NF25I
STK11C88-SF25ITR
STK11C88-SF25I
STK11C88-NF45TR
STK11C88-NF45
Industrial
45
Commercial
Industrial
STK11C88-SF45TR
STK11C88-SF45
STK11C88-NF45ITR
STK11C88-NF45I
STK11C88-SF45ITR
STK11C88-SF45I
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Document Number: 001-50591 Rev. **
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STK11C88
Package Diagrams
Figure 11. 28-Pin (300 mil) SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
14
1
MIN.
3. DIMENSIONS IN INCHES
MAX.
0.291[7.39]
0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01]
0.419[10.64]
PART #
15
28
0.026[0.66]
0.032[0.81]
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
*
0.004[0.10]
0.0091[0.23]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
*
0.004[0.10]
0.0125[3.17]
0.050[1.27]
TYP.
0.0118[0.30]
51-85026-*D
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STK11C88
Package Diagrams (continued)
Figure 12. 28-Pin (330 mil) SOIC (51-85058)
51-85058-*A
Document Number: 001-50591 Rev. **
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STK11C88
Document History Page
Document Title: STK11C88 256 Kbit (32K x 8) SoftStore nvSRAM
Document Number: 001-50591
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
2625096
GVCH/PYRS
12/19/08
New data sheet
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50591 Rev. **
Revised January 29, 2009
Page 15 of 15
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holders.
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