CYS25G0101DX-ATC Evaluation Board
User’s Guide
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 19, 2002
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CYS25G0101DX-ATC Evaluation Board User’s Guide
List of Figures(continued)
Figure 23. Reference Clock Block Schematic Diagram ................................................................... 31
Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing ....................................... 33
Figure 25. CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen .................................... 34
Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout ........................................... 35
Figure 27. CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask .................................. 36
Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout ....................................... 37
Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout ..................................... 38
Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen ........................................ 39
Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout ..................................... 40
Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask ....................................... 41
List of Tables
Table 1. Functional Description of the Connectors ............................................................................ 6
Table 2. Pin Assignment of J1 Header and Description of J10 Header ............................................ 7
Table 3. Pin Assignment of J2 Header and Description of J9 Header .............................................. 8
Table 4. Functional Description of DIP Switch 1 (SW1) ..................................................................... 9
Table 5. Functional Description of J4 Connector ............................................................................. 10
Table 6. Description of LED Indicators .............................................................................................. 10
Table 7. Operation Specification of CYS25G0101DX Evaluation Board ......................................... 23
Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4 ........................................ 43
Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4 ........................................ 44
Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4 ..................................... 45
Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4 ..................................... 46
Table 12. CYS25G0101DX Evaluation Board HSTL BOM - Page 1 of 4 .......................................... 48
Table 13. CYS25G0101DX Evaluation Board HSTL BOM - Page 2 of 4 .......................................... 49
Table 14. CYS25G0101DX Evaluation Board HSTL BOM - Page 3 of 4 .......................................... 50
Table 15. CYS25G0101DX Evaluation Board HSTL BOM - Page 4 of 4 .......................................... 51
3
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CYS25G0101DX-ATC Evaluation Board User’s Guide
1. Introduction
Cypress'sCYS25G0101DXSONETOC-48Transceiverisacommunicationsbuildingblockforhigh-speedSONETdatacommunica-
tions.Itprovidescompleteparallel-to-serialandserial-to-parallelconversions,clockgeneration,andclockanddatarecoveryopera-
tionsinasinglechip,optimizedforfullSONET/SDHcompliance.TheCYS25G0101DXEvaluationBoardisdesignedforevaluatingas
well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The CYS25G0101DX SONET/SDH
TransceiverEvaluationBoardprovidesthefollowingadvantages.
2. Features
• Flexibleandeasytooperate
• On-boardCypress120-pinTQFPCYS25G0101DXSONET/SDHTransceiver
• SupportsLVPECLandHSTLinterfaces
• Dipswitchforselectingdifferentdiagnosticmodes
• Fourdiagnosticmodes–DiagnosticLoopbackmode,LineLoopbackmode,AnalogLineLoopbackmode,andfactoryTEST0
(ParallelLineLoopback)mode
• LFIandFIFO_ERRLEDs
• OnboardoscillatorfortheREFCLK
• SupportsexternalclocksourcefortheREFCLK
• 16-bitRxD,16-bitTxDbus,RXCLK,TXCLKI,TXCLKOinterface
• SMAconnectorsforCMLinputandoutputbuffers
• SeparateBananaJacksforallvoltagesourcesformeasuringcurrentindividually
3. Kit Contents
• CYS25G0101DXEvaluationBoard
• CertificateofCompliance
• CYS25G0101DXEvaluationKitCD
—
—
—
UsersGuide
ApplicationNotes
DataSheet
4. Functional Description
This board can be used to test the CYS25G0101DX in various modes, such as TEST0 (parallel line loopback mode), LINELOOP,
LOOPA and LOOPTIME. The REFCLK of the CYS25G0101DX is connected to the onboard 155.52-MHz oscillator. The on-board
REFCLK can be replaced by connecting the external reference clock source to J17 and J18. To use the external reference clock
source,theC400andC401(0.01-µFcap)havetoberemovedandplacedonC402andC403positions.Also,theP2,CLKVCC,hasto
bedisconnectedfromthepowersupply(orpowerdown).TheCYS25G0101DXEvaluationBoardprovidesanoptionalopticalmodule
interfaceforconnectingtoanopticalmoduledaughtercard.
The block diagram of the CYS25G0101DX is shown in Figure 1. The detailed functional description can be found in the
CYS25G0101DX data sheet. Figure 2 shows the picture of the CYS25G0101DX Evaluation Board and the location of the jumpers.
Table 1isthedescriptionofalljumpersandconnectors.Thebusconnectors,J1andJ2,areusedtoconnecttothe16-bitRxDandTxD
busesfortransferringandreceivingtheparalleldata.Table 2andTable 3 arethepindefinitionsofJ1andJ2.Amulti-functioneight-po-
sitionDipswitchprovidestheselectionofthedifferentdiagnosticmodesaswellasthecontrolfunctions. Table 4 isthefunctionalde-
scription of the Dip switch SW1. The TEST0 jumper, J6, when closed, is used to enable the factory TEST0 (Parallel Line Loop Back)
mode.Inthe“ParallelLineLoopBack”mode,paralleloutputbuffersareinternallyjumpedtotheparallelinputbuffers.Thereisnoneed
touseexternaljumpersfortheheaders.J13,J14,J15,J16andJ4areDifferentialCMLinputandoutputandpowersupplyfortheoption-
alopticalmoduledaughtercard. Table 5 idescribestheopticalmoduleinterfaceand Table 6idescribestheLED. Figure 3showsthe
jumperorientationsoftheCYS25G0101DXEvaluationBoard.
4
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CYS25G0101DX-ATC Evaluation Board User’s Guide
(155.52MHz)
FIFO_RST TXCLKI
(155.52MHz)
REFCLK
(155.52MHz)
RXCLKOUT
FIFO_ERR
TXCLKO
TXD
15:0
RXD
15:0
Output
Register
Input
Register
TX PLL
x16
/16
Recovered
Bit-Clock
FIFO
SHIFTER
/16
(5byte)
RX CDR
PLL
SHIFTER
Retimed
Data
Tx Bit-Clock
Lock-to-Ref
LOOPTIME
DIAGLOOP
LINELOOP
LOOPA
Lock-to-Data /
Clock Control
Logic
IN±
OUT±
PWRDN LOCKREF SD LFI RESET
Figure 1. The Block Diagram of the CYS25G0101DX
5
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CYS25G0101DX-ATC Evaluation Board User’s Guide
SMA13
SMA14
SMA16
SMA15
J4
P4
SW1
J6
J5
SMA17
P2
J7
D2
D1
SMA18
P3
J8
J3
SMA12
P5
SMA11
SMA10
J2
J1
P1
P5
Figure 2. The CYS25G0101DX Evaluation Board
Table 1. Functional Description of the Connectors
Jumpers and
Connectors
Name
RxDBUS
Description
J1
16-bitRxDDataBusinterfaceheader(seeTable 2fordetails).Figure 3showstheorienta-
tionofthisheader
J2
J3
J4
TxDBUS
16-bitTxDDataBusinterfaceheader(seeTable 3 fordetails).Figure 3showstheorienta-
tionofthisheader
TxCLKO_H
OPTICPOWER
HeaderforCYS25G0101DX’sTXCLKO(pin79)andGND.Figure 3showstheorientation
ofthisjumper
Powersupplyforexternalopticalmodule(seeTable 5fordetails)
6
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CYS25G0101DX-ATC Evaluation Board User’s Guide
Table 1. Functional Description of the Connectors(continued)
Jumpers and
Connectors
Name
Description
J5
SD
ThisjumperisusedtosettheSDsignal.Whenopen(default),SDsignalwillbedrivenbythe
opticalmodule.When1-2areshorted,SDisforcedtoHIGH.When2-3areshorted,SDis
forcedtoLOW.Figure 3showstheorientationofthisjumper
J6
TEST0
LFI
Thisjumper,whenshorted,istoenabletheParallelLineLoopbackmode.
J7
TestTapforCYS25G0101DX’sLFI(pin1).Figure 3showstheorientationofthisjumper
TestTapforCYS25G0101DX’sLIFO(pin51).Figure 3showstheorientationofthisjumper
J8
FIFO_ERR
TXCLKI
SMA10
OptionalSMAconnectorforCYS25G0101DX’sTXCLKI(pin57).R37 need to be popu-
lated, if this connector is used
SMA11
SMA12
RXCLK
OptionalSMAconnectorforCYS25G0101DX’sRXCLK(pin24).C118, R118, R138 and
R158 need to be populated and C116, R116, and R136 need to be unpopulated, if
this connector is used
TXCLKO
OptionalSMAconnectorforCYS25G0101DX’sTXCLKO(pin79).C119, R119, R139 and
R159 need to be populated and C117, R117, and R137 need to be unpopulated, if
this connector is used
SMA13
SMA14
SMA15
SMA16
SMA17
IN+
SMAconnectorforCYS25G0101DX’sIN+(pin109).Thisconnectorisalsofortheoptional
opticalmoduleinterface
IN-
SMAconnectorforCYS25G0101DX’sIN–(pin108).Thisconnectorisalsofortheoptional
opticalmoduleinterface
OUT-
OUT+
REFCLKP
SMAconnectorforCYS25G0101DX’sOUT–(pin104).Thisconnectorisalsofortheoption-
alopticalmoduleinterface
SMAconnectorforCYS25G0101DX’sOUT+(pin103).Thisconnectorisalsofortheoption-
alopticalmoduleinterface
OptionalSMAconnectorforCYS25G0101DX’sREFCLK+(pin87).Thisconnectorisforus-
ingtheexternalreferenceclockinsteadofusingthe“on-board”oscillator(155.52MHz).To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
SMA18
REFCLKN
OptionalSMAconnectorforCYS25G0101DX’sREFCLK+(pin87).Thisconnectorisforus-
ingtheexternalreferenceclockinsteadofusingthe“on-board”oscillator(155.52MHz).To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
P1
P2
P3
P4
P5
P6
GND
PowerGround.Forexternalpowersupply
CLKVCC
VDDQ
Powersupply-+3.3Vfortheclockoscillator
Powersupply-+3.3VforLVPECLoutput.+1.5VforHSTLoutputs
Powersupply-+3.3Vfortheoptionalopticalmodule
Powersupply-+3.3Vfordigitalandlow-speedI/Ofunction
Powersupply-+3.3VforLVPECLoutput.+1.5VforHSTLoutputs
VCC_OPTIC
VCC
V_Par
Table 2. Pin Assignment of J1 Header and Description of J10 Header
Pin Number
Name
RXD15
I/O Characteristics
Description
1
HSTLoutput
ParallelreceivedataoutputRXD15.Theoutputschangefollowing
RXCLK↓
3
RXD14
HSTLoutput
ParallelreceivedataoutputRXD14.Theoutputschangefollowing
RXCLK↓
7
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Table 2. Pin Assignment of J1 Header and Description of J10 Header(continued)
Pin Number
Name
RXD13
I/O Characteristics
Description
5
HSTLoutput
ParallelreceivedataoutputRXD13.Theoutputschangefollowing
RXCLK↓
7
RXD12
RXD11
RXD10
RXD9
RXD8
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
GND
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
HSTLoutput
Ground
ParallelreceivedataoutputRXD12.Theoutputschangefollowing
RXCLK↓
9
ParallelreceivedataoutputRXD11.Theoutputschangefollowing
RXCLK↓
11
13
15
17
19
21
23
25
27
29
31
ParallelreceivedataoutputRXD10.Theoutputschangefollowing
RXCLK↓
ParallelreceivedataoutputRXD9.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD8.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD7.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD6.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD5.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD4.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD3.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD2.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD1.TheoutputschangefollowingRX-
CLK↓
ParallelreceivedataoutputRXD0.TheoutputschangefollowingRX-
CLK↓
2,4,6,8,10,
12,14,16,18,
20,22,24,26,
28,30,32
Ground
J10
RXCLK
HSTLoutput
Receiveclockoutput.Thisclockisdividedby16ofthebit-rateclock
extractedfromthereceivedserialstream
Table 3. Pin Assignment of J2 Header and Description of J9 Header
Pin Number
Name
I/O Characteristics
Description
1,3,5,7,9,11, GND
13,15,17,19,
21,23,25,27,
29,31
Ground
Ground
2
4
6
TXD15
TXD14
TXD13
HSTLoutput
HSTLinput
HSTLinput
ParalleltransmitdatainputTXD15.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD14.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD13.TheinputdataissampledbyTX-
CLKI↑
8
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Table 3. Pin Assignment of J2 Header and Description of J9 Header (continued)
Pin Number
Name
TXD12
I/O Characteristics
Description
8
HSTLinput
ParalleltransmitdatainputTXD12.TheinputdataissampledbyTX-
CLKI↑
10
12
14
16
18
20
22
24
26
28
30
32
J9
TXD11
TXD10
TXD9
TXD8
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
TXCLKI
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
HSTLinput
ParalleltransmitdatainputTXD10.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD9.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD8.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD8.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD7.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD6.TheinputdataissampledbyTX-
CLKI↑
Paralleltransmitdata‘inputTXD5.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD4.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD3.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD2.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD1.TheinputdataissampledbyTX-
CLKI↑
ParalleltransmitdatainputTXD0.TheinputdataissampledbyTX-
CLKI↑
Paralleltransmitdatainputclock
Table 4. Functional Description of DIP Switch 1 (SW1)
Position
Name
State
ON*
OFF
ON
Description
1
RESET
DisableReset-Normaloperation
ResetforalllogicfunctionsexceptthetransmitFIFO
2
DIAGLOOP
Transmitdata(fromTXD[15:0])isroutedthroughthereceiveclock
anddatarecoveryandpresentedatRXD[15:0]output
OFF*
Receivedserialdata(fromIN±)isroutedthroughthereceiveclockand
datarecoveryandpresentedatRXD[15:0]output
3,4
LINELOOP,
LOOPA
ON
ON
ON
Invalidsetting
OFF
Receivedserialdataisloopedbackfromreceiveinput(IN±)totrans-
mitoutput(OUT±)after being reclocked by the recovered clock
OFF
ON
Receivedserialdataisloopedbackfromreceiveinput(IN±)totrans-
mitoutput(OUT±),but is not routed through the clock and data
recovery PLL
OFF*
OFF*
Disableserialdataloopback.
9
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Table 4. Functional Description of DIP Switch 1 (SW1) (continued)
Position
Name
State
Description
5
LOOPTIME
ON
Thetransmissionwillbeusingtheextractedreceivebit-clockforthe
transmittedbitclock
OFF*
ThetransmissionwillbeusingtheREFCLKinput(155.52MHz),which
ismultipliedby16,togeneratethetransmittedbitclock
6
7
LOCKREF
PWRDN
ON*
OFF
ON*
OFF
ThereceivePLLlockstoserialdatastream
ThereceivePLLlockstotheREFCLK
DisablePowerDown-NormalOperation
EnableDevicePowerDownmode.Allthelogicanddriversaredis-
abledandplacedintoastandbyconditionwhereonlyminimalpoweris
dissipated
8
FIFO_RST
ON*
OFF
DisableFIFOreset-NormalOperation
ResetthetransmitFIFOpointers.Theinandoutpointersofthetrans-
mitFIFOareresettothemaximumseparation
Table 5. Functional Description of J4 Connector
Pin
Name
Description
Powersupplyforopticalmodule
Powerground
1A,1B,3A,3B
VCC_OPTIC
2A,2B,4A,4B
GND
NC
5A
5B
NoConnection
SD
SDsignalfromopticalmodule
Table 6. Description of LED Indicators
LED
Name
LED Status
Description
D1
FIFO_ERR
ON
ThetransmitFIFOhaseitherunderoroverflowed.TheFIFO
mustberesettocleartheerror(byswitchingtheDIPswitch
SW1-8toOFFandthenON.SeeTable 4fordetails)
OFF
ON
IndicatestheFIFOhasneitherunderoroverflowed
D2
LFI
IndicatesnoLineFault.ItwillappeartobeONevenwhenLFIis
toggling.InsuchacaseobserveLFIusingascopeonJ7
OFF
Indicatestheselectedreceivedatastreamhasbeendetectedan
invalideitherLOWinputonSDorbythereceiveVCObeingoper-
atedoutsideitsspecifiedlimits
10
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5A
1A
1B
5B
J5
3
2
1
J7
LFI
GND
FIFO_ERR
GND
J8
TXCLKO
GND
RXCLK
GND
J2
TXCLKI
GND
J1
Pin 1
Pin 1
Figure 3. The Jumper Orientations of the CYS25G0101DX
11
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5. Diagnostic Modes
The CYS25G0101DX Evaluation Board provides four different diagnostic modes—Diagnostic Loopback mode, Line Loopback
mode,AnalogLoopbackmodeand“ParallelLineLoopback”mode.Figure 4toFigure 7illustratethesediagnosticmodesandFigure
8toFigure 10illustratethetestingequipmentset-upfortestingthecharacteristicsoftheCYS25G0101DX.
5.1 Diagnostic Loopback Mode
IntheDiagnosticLoopbackmode,paralleldatawillloopthroughtheinputbuffer,serializer,CDRblock,deserializerandtheoutputbuff-
er.Figure 4showsthedatapath(boldline)oftheDiagnosticLoopbackmode.ToselecttheDiagnosticLoopbackmode:
1. SW1-2(DIAGLOOP)mustbeinONposition,SW1-3(LINELOOP)
2. AllotherdipswitchesmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8toFigure 10
TXCLKIN
TXCLK
REFCLK RXCLKOUT
TXD
15:0
RXD
15:0
Input
Output
Register
Register
TX PLL
x16
/16
FIFO
(5byte)
SHIFTER
/16
RX CDR
PLL
SHIFTER
DIAGLOOP
(SW1-2) = ON
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
Figure 4. Diagnostic Loopback Mode Data Path
12
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5.2 Line Loopback
In the Line Loopback mode, serial data (from IN±) will loop through the serial input buffer and CDR block to the serial output buffer
(OUT±).Figure 5showsthedatapath(boldline)oftheLineLoopbackmode.ToselecttheLineLoopbackmode:
1. SW1-3(LINELOOP)mustbeinONposition
2. AllotherdipswitchsettingsmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8toFigure 10
TXCLKIN
TXCLK
REFCLK RXCLKOUT
TXD
15:0
RXD
15:0
Input
Output
Register
Register
TX PLL
x16
/16
FIFO
(5byte)
SHIFTER
/16
RX CDR
PLL
SHIFTER
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = ON
LOOPA
SW1-4 = OFF
IN±
OUT±
Figure 5. Line Loopback Mode Data Path
13
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CYS25G0101DX-ATC Evaluation Board User’s Guide
5.3 Analog Line Loopback
In the Analog Line Loopback mode, serial data (from IN±) will loop through directly from serial input buffer to the serial output buffer
(OUT±).Figure 6showsthedatapath(boldline)oftheAnalogLineLoopbackmode.ToselecttheAnalogLineLoopbackmode:
1. SW1-4(LOOPA)mustbeinONpositionandSW1-3(LINELOOP)mustbeinOFFposition.
2. AllotherdipswitchesmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8toFigure 10
TXCLKIN
TXCLK
REFCLK RXCLKOUT
TXD
15:0
RXD
15:0
Input
Output
Register
Register
TX PLL
x16
/16
FIFO
(5byte)
SHIFTER
/16
RX CDR
PLL
SHIFTER
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = ON
IN±
OUT±
Figure 6. Analog Line Loopback Mode Data Path
14
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5.4 “Parallel Line Loopback” (TEST0) Mode
In Parallel Line Loopback mode, the parallel output buffers are internally linked to the parallel input buffers. Figure 7 shows the data
path(boldline)oftheParallelLineLoopbackmode. Inthistestmode, theinternalRX CDRPLLandTXPLLcanbetestedbydifferent
configurations.
5.4.1 Test the Internal RX CDR PLL Only
1. TEST0,jumperJ6mustbeshorted
2. SW1-5(LOOPTIME)mustbeinONposition
3. Allotherdipswitchesmustbeintheirdefaultpositions(seeTable 4)
4. ApplytheTestingHookupillustratedinFigure 8toFigure 10forthemeasurement
5.4.2 Test the Internal RX CDR PLL and TX PLL
1. TEST0,jumperJ6mustbeshorted
2. Alldipswitchesmustbeintheirdefaultpositions(seeTable 4)
3. DisconnectCLKVCC(P2),removethe155.52-MHzoscillator,placeC400onC402andC401onC403positions(seeTable
1,jumpersJ17andJ18fordetails)
4. ApplytheTestingHookupillustratedinFigure 11forthemeasurement
TXCLKIN
TXCLK
REFCLK RXCLKOUT
TXD
15
RXD
15:0
Input
Output
Register
Register
TX PLL
x16
/16
FIFO
(5byte)
SHIFTER
/16
RX CDR
PLL
SHIFTER
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
JUMPER J6 (TEST0) = CLOSED
IN±
OUT±
Figure 7. Parallel Loopback (TEST0) Mode Data Path
15
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6. Testing Hookup
6.1 Set-up for BERT Test
Figure 8illustratestheset-upfortheBERTtest.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. ErrorDetector–TektronixD3286ErrorDetector
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Tektronix D3286
Pattern Analyzer
Tektronix D3186
Pattern Generator
Ω
50 Terminator
CLK2
For OUT-
IN+ IN-
OUT+
OUT-
Cypress CYS25G0101DX
Evaluation Board
HP E3631A
Power Supply
Figure 8. Equipment Set-up for BERT Test
16
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6.2 Set-up for Eye Diagram Test
Figure 9illustratestheset-upfortestingtheEyeDiagram.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. Oscilloscope–AgilentInfiniiumDCA86100Awith83484ADual-Channel50GHzModule
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Tektronix D3186 Pattern Generator
Agilent Infinium DAC 86100A Oscilloscope
with 8348A Dual-Channel 50GHz Module
Trigger Out
Trigger
IN+ IN-
OUT+
OUT-
Cypress CYS25G0101DX
Evaluation Board
HP E3631A
Power Supply
Figure 9. Equipment Set-up For Eye Diagram Test
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6.3 SONET Jitter Transfer and Jitter Tolerance Test
Figure 10illustratestheset-upfortestingthejitter.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. SONETTester–Agilent(HP)OmniBER718CommunicationPerformanceAnalyzer
3. OpticalConverters-Agilent(HP)83446AReceiverand83430ATransmitter
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
HP OmniBER 718
Communications
Performance Analyzer
Optical to Analog
Converter
(i.e. HP’s 83446A)
Analog to Optical
Converter (i.e. HP’s 83430A)
Cypress CYS25G0101DX
Evaluation Board
HP E3631A
Power Supply
Figure 10. Equipment Set-up For Jitter Test
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6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode
Figure 11illustratestheset-upfortestingtheTXPLLinParallelLineLoopbackMode.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. ErrorDetector–TektronixD3286ErrorDetector
4. PulseGenerator-HP8133APulseGenerator
5. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Tektronix D3286
Pattern Analyzer
HP 8133A Pulse Generator
(configure to Output = Input Clock divided by 16)
Tektronix D3186
Pattern Generator
External
Input
CLK2
CLK1
Ω
50 Terminator For OUT-
IN+ IN-
OUT+
OUT-
1. Disconnect CLKVCC
2. Remove the OSC
3. Place C400 on C402 and
C401 on C403 positions
Cypress CYS25G0101DX
Evaluation Board
HP E3631A
Power Supply
Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode
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7. Eye Diagram Testing Result
Figure 12 is the Eye Diagram measurement from CYS25G0101DX Evaluation Board by using the test set-up as in Figure 9. In this
measurement,theevaluationboardisconfiguredtoparallelloopbackmode(Figure 7)andwithnoSONETfilterattheoscilloscope.
Figure 12. CYS25G0101DX Evaluation Board Eye Diagram
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8. Jitter Transfer Testing Result
Figure 13andFigure 14showtheJitterTransfermeasurementbyusingthetestset-upasinFigure 10.Figure 13isthemeasurement
resultoftheGR-253(Bellcore)standardandFigure 14isthemeasurementresultoftheG958(ITU)standard.Inthismeasurement,the
CYS25G0101DXevaluationboardisconfiguredtoparallelloopbackmode(Figure 7).
Figure 13. CYS25G0101DX Evaluation Board GR-253 Jitter Transfer Testing Result
Figure 14. CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result
21
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9. Jitter Tolerance Testing Result
Figure 15andFigure 16showtheJitterTolerancemeasurementbyusingthetestset-upasinFigure 10.Figure 15isthemeasurement
resultoftheGR-253(Bellcore)standardandFigure 16isthemeasurementresultoftheG825(ITU)standard.Inthismeasurement,the
CYS25G0101DXevaluationboardisconfiguredtoparallelloopbackmode(Figure 7).
Figure 15. CYS25G0101DX Evaluation Board GR-253 JitterTolerance Testing Result
Figure 16. CYS25G0101DX Evaluation Board G825 Jitter Tolerance Testing Result
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10. Schematic Diagram, PCB Layout and BOM (Bill of Material)
Figure 17toFigure 23inAppendix AshowstheschematicdiagramoftheCYS25G0101DXevaluationboard.Figure 17isthetoplevel
diagramfortheschematicdiagramsforFigure 18toFigure 23.Figure 24toFigure 32inAppendix BshowthePCBlayoutofeachlayer
oftheCYS25G0101DXevaluationboard.TheBillofMaterial(BOM)oftheevaluationboardislistedinAppendix C(forLVPECLTable
8toTable 11)andAppendix D(forHSTLTable 12toTable 15)respectively.
Table 7. Operation Specification of CYS25G0101DX Evaluation Board
Description
Min.
Max.
Unit
Notes
PowerSupplyVCC
CurrentI
3.135
280
3.465
320
V
1
2
mA
V
VCC
ClockPowerSupplyCLKVCC
3.135
75
3.465
90
CurrentI
mA
3
CLKVCC
Notes:
1. The operation voltage VCC for the device at the power supply nodes.
2. The operation current drawn by supply VCC at room temperature.
3. Assumes onboard clock option. If external clock (SMA option) is used the current drawn will depend on the termination resistors required for
the external clock.
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Appendix A: Schematic Diagrams of the
CYS25G0101DX Evaluation Board
24
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Figure 17. Top Level of CYS25G0101DX Evaluation Board Schematic Diagram
25
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Figure 18. Parallel Output Block Schematic Diagram
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Figure 19. Parallel Input Block Schematic Diagram
27
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Figure 20. Signals Block Schematic Diagram
28
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Figure 21. Power Supply Block Schematic Diagram
29
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Figure 22. Control Block Schematic Diagram
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Figure 23. Reference Clock Block Schematic Diagram
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Appendix B: PCB Layout Diagrams of the
CYS25G0101DX Evaluation Board
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Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing
33
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Figure 25. CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen
34
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Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout
35
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Figure 27. CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask
36
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Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout
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Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout
38
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Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen
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Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout
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Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask
41
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Appendix C: CYS25G0101DX Evaluation
Board LVPECL BOM (Bill of Material)
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Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4
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Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4
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Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4
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Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4
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Appendix D: CYS25G0101DX Evaluation
Board HSTL BOM (Bill of Material)
47
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Table 12. CYS25G0101DX Evaluation Board HSTL BOM - Page 1 of 4
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Table 13. CYS25G0101DX Evaluation Board HSTL BOM - Page 2 of 4
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Table 14. CYS25G0101DX Evaluation Board HSTL BOM - Page 3 of 4
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Table 15. CYS25G0101DX Evaluation Board HSTL BOM - Page 4 of 4
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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