CY7C1020BN
32K x 16 Static RAM
Features
Functional Description
• High speed
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
— t = 12, 15 ns
AA
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
— 825 mW (max.)
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
1
8
• Low CMOS standby power (L version only)
— 2.75 mW (max.)
written into the location specified on the address pins (A
0
through A ). If Byte High Enable (BHE) is LOW, then data
15
from I/O pins (I/O through I/O ) is written into the location
9
16
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
specified on the address pins (A through A ).
0
15
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O to I/O . If Byte High Enable (BHE) is
1
8
LOW, then data from memory will appear on I/O to I/O . See
9
16
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O through I/O ) are placed in a
1
16
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
1
NC
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
A7
A6
A5
A4
A3
A2
OE
A
1
BHE
BLE
I/O
I/O
I/O
A
0
32K x 16
CE
I/O1–I/O8
RAM Array
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
2
3
15
14
13
I/O9–I/O16
9
A1
A0
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
31
30
29
28
27
I/O
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
NC
18
A
A
8
15
BHE
19
26
25
A
A
14
9
WE
CE
OE
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
BLE
Cypress Semiconductor Corporation
Document #: 001-06443 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
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CY7C1020BN
AC Test Loads and Waveforms
R 481Ω
R 481Ω
ALL INPUT PULSES
5V
5V
OUTPUT
3.0V
90%
10%
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
GND
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time: 1 V/ns
Fall Time: 1 V/ns
1.73V
(b)
(a)
167
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
30 pF
Switching Characteristics[5] Over the Operating Range
7C1020BN-12
7C1020BN-15
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
12
15
AA
Data Hold from Address Change
CE LOW to Data Valid
3
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
12
6
15
7
OE LOW to Data Valid
[6]
OE LOW to Low Z
0
3
0
0
3
0
[6, 7]
OE HIGH to High Z
6
6
7
7
[6]
CE LOW to Low Z
[6, 7]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
6
15
7
PD
DBE
LZBE
HZBE
0
0
6
7
[8]
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
0
HA
0
0
SA
8
10
8
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
6
0
0
HD
[6]
WE HIGH to Low Z
3
3
LZWE
HZWE
BW
[6, 7]
WE LOW to High Z
6
7
Byte Enable to End of Write
8
9
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 30-pF load capacitance.
I
OL OH
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state
HZOE HZBE HZCE
HZWE
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document #: 001-06443 Rev. **
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CY7C1020BN
Switching Waveforms
[9, 10]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[10, 11]
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V .
IL
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06443 Rev. **
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CY7C1020BN
Switching Waveforms (continued)
[12, 13]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06443 Rev. **
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CY7C1020BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O –I/O
I/O –I/O
16
Mode
Power
1
8
9
H
L
X
L
X
H
X
L
X
L
High Z
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
Power-Down
Read – All bits
Standby (I
)
SB
Data Out
Data Out
High Z
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
)
)
)
CC
CC
CC
CC
CC
CC
CC
CC
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
H
L
L
X
L
L
Data In
Data In
High Z
L
H
L
Write – Lower bits only
Write – Upper bits only
H
X
H
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
High Z
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C1020BN-12VC
Package Type
12
51-85082
51-85082
51-85087
51-85087
51-85087
51-85087
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C1020BN-12VXC
CY7C1020BN-12ZC
CY7C1020BN-12ZXC
CY7C1020BN-15ZC
CY7C1020BN-15ZXC
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II
15
44-pin TSOP Type II (Pb-free)
Please contact local sales representative regarding availability of these parts.
Document #: 001-06443 Rev. **
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CY7C1020BN
Package Diagrams
44-Lead (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-Pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06443 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.
CY7C1020BN
Document History Page
Document Title: CY7C1020BN 32K x 16 Static RAM
Document #: 001-06443
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
426812
See ECN
NXR
New Data Sheet
Document #: 001-06443 Rev. **
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