CY62167EV18 MoBL®
16 Mbit (1M x 16) Static RAM
by 99 percent when addresses are not toggling. Place the device
Features
into standby mode when deselected (CE HIGH or CE LOW or
1
2
both BHE and BLE are HIGH). The input and output pins (I/O
■ Very high speed: 55 ns
0
through I/O ) are placed in a high impedance state when: the
15
■ Wide voltage range: 1.65V to 2.25V
device is deselected (CE HIGH or CE LOW); outputs are
1
2
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); and a write operation is
■ Ultra low standby power
❐ Typical standby current: 1.5 μA
❐ Maximum standby current: 12 μA
in progress (CE LOW, CE HIGH and WE LOW).
1
2
To write to the device, take Chip Enables (CE LOW and CE
1
2
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O through I/O ) is
0
7
written into the location specified on the address pins (A through
0
■ Easy memory expansion with CE , CE , and OE features
1
2
A
). If Byte High Enable (BHE) is LOW, then data from I/O pins
19
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 48-ball VFBGA packages
(I/O through I/O ) is written into the location specified on the
8
15
address pins (A through A ).
0
19
To read from the device, take Chip Enables (CE LOW and CE
1
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
Functional Description
on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from
0
7
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL ) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
8
15
®
For best practice recommendations, refer to the Cypress
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
10
9
8
7
6
1M × 16
RAM ARRAY
5
4
3
2
1
0
IO –IO
0
7
IO –IO
A
8
15
A
A
A
COLUMN DECODER
BHE
WE
CE2
CE2
CE
1
PowerDown
Circuit
CE
1
OE
BHE
BLE
BLE
Cypress Semiconductor Corporation
Document #: 38-05447 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 13, 2009
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CY62167EV18 MoBL®
DC Input Voltage
....... –0.2V to 2.45V (V (max) + 0.2V)
Maximum Ratings
CC
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch up Current...................................................... >200 mA
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .......................... –0.2V to 2.45V (V (max) + 0.2V)
Ambient
Temperature
Device
Range
V
CC
CC
CY62167EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
in High Z State
........... –0.2V to 2.45V (V (max) + 0.2V)
CC
Electrical Characteristics
Over the Operating Range
55 ns
Parameter
Description
Test Conditions
Unit
Min
Typ
Max
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
I
I
= –0.1 mA
= 0.1 mA
1.4
V
V
OH
OL
IH
OH
V
V
V
I
0.2
OL
V
= 1.65V to 2.25V
= 1.65V to 2.25V
1.4
–0.2
–1
V
+ 0.2V
CC
V
CC
CC
V
0.4
+1
+1
30
V
IL
Input Leakage Current
Output Leakage Current
GND < V < V
CC
μA
μA
mA
mA
IX
I
I
I
GND < V < V , Output Disabled
–1
OZ
O
CC
V
Operating Supply
f = f
= 1/t
V
= V (max)
25
CC
CC
max
RC
CC
CC
Current
I
= 0 mA
OUT
f = 1 MHz
2.2
4.0
CMOS levels
I
I
Automatic CE Power Down
Current – CMOS Inputs
CE > V – 0.2V or CE < 0.2V
1.5
12
μA
SB1
1
CC
2
V
> V – 0.2V, V < 0.2V)
CC IN
IN
f = f
(Address and Data Only),
max
f = 0 (OE, WE, BHE and BLE),
= V (max)
V
CC
CC
Automatic CE Power Down
Current – CMOS Inputs
CE > V – 0.2V or CE < 0.2V,
CC
1.5
12
μA
1
2
SB2
V
> V – 0.2V or V < 0.2V,
CC IN
IN
f = 0, V = V
CC
CC(max)
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Input Capacitance T = 25°C, f = 1 MHz,
Output Capacitance
Max
10
Unit
pF
C
IN
A
V
= V
CC(typ)
CC
C
10
pF
OUT
Notes
6. V (min) = –2.0V for pulse durations less than 20 ns.
IL
7.
V
(max) = V + 0.75V for pulse durations less than 20 ns.
IH CC
8. Full Device AC operation is based on a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
CC
CC
9. Only chip enables (CE and CE ), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
VFBGA
VFBGA
Parameter
Description
Test Conditions
Unit
(6 x 7 x 1mm) (6 x 8 x 1mm)
Θ
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
27.74
9.84
55
16
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
°C/W
JC
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
V
CC
V
CC
OUTPUT
90%
10%
GND
R2
30 pF
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
1.8V
13500
10800
6000
0.80
Unit
Ω
R1
R2
Ω
R
Ω
TH
V
V
TH
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
= 1.0V, CE > V – 0.2V, CE < 0.2V,
Min
Typ
Max
Unit
V
V
V
for Data Retention
1.0
DR
CC
I
Data Retention Current
V
V
10
μA
CCDR
CC
1
CC
2
> V – 0.2V or V < 0.2V
IN
CC
IN
CDR
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
Operation Recovery Time
t
RC
R
Figure 3. Data Retention Waveform
DATA RETENTION MODE
V
(min)
> 1.0 V
V
t
(min)
V
CC
V
CC
DR
CC
t
CDR
R
CE or
1
BHE.BLE
CE
2
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V ramp from V to V (min) > 100 μs or stable at V (min) > 100 μs.
CC
DR
CC
CC
12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Switching Characteristics
Over the Operating Range
55 ns
Parameter
Description
Unit
Min
55
Max
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
RC
Address to Data Valid
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Data Hold from Address Change
CE LOW and CE HIGH to Data Valid
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
25
1
2
OE LOW to Data Valid
OE LOW to Low-Z
5
10
0
OE HIGH to High-Z
CE LOW and CE HIGH to Low-Z
18
18
1
2
CE HIGH and CE LOW to High-Z
1
2
CE LOW and CE HIGH to Power Up
1
2
CE HIGH and CE LOW to Power Down
55
55
PD
1
2
BLE/BHE LOW to Data Valid
DBE
LZBE
HZBE
BLE/BHE LOW to Low-Z
10
BLE/BHE HIGH to High-Z
Write Cycle Time
18
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW and CE HIGH to Write End
SCE
AW
1
2
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
HA
0
SA
40
40
25
0
PWE
BW
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
SD
HD
WE LOW to High-Z
20
HZWE
LZWE
WE HIGH to Low-Z
10
Notes
13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of V
/2, input pulse levels
CC(typ)
of 0 to V
CC(typ)
OL OH
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
device.
16. t
, t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZOE HZCE HZBE
HZWE
17. The internal memory write time is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a write and
1
IL
IL
2
IH
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Switching Waveforms
Figure 4 shows address transition controlled read cycle waveforms.
Figure 4. Read Cycle No. 1
t
RC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Figure 5 shows OE controlled read cycle waveforms.
Figure 5. Read Cycle No. 2
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
18. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .
IH
1
IL
IL
2
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Switching Waveforms (continued)
Figure 6 shows WE controlled write cycle waveforms.
Figure 6. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
VALID DATA
tHZOE
Notes
21. Data IO is high impedance if OE = V
.
IH
22. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
23. During this period the IOs are in output state. Do not apply input signals.
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Switching Waveforms (continued)
1
2
Figure 7. Write Cycle No. 2
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
VALID DATA
tHZOE
Figure 8 shows WE controlled, OE LOW write cycle waveforms.
Figure 8. Write Cycle No. 3
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
DATA I/O
VALID DATA
tLZWE
t
HZWE
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Switching Waveforms (continued)
Figure 9 shows BHE/BLE controlled, OE LOW write cycle waveforms.
Figure 9. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
VALID DATA
tHD
NOTE 23
DATA IO
Truth Table
CE
H
X
CE
X
WE OE BHE BLE
Inputs/Outputs
Mode
Power
1
2
X
X
X
H
H
X
X
X
L
X
X
H
L
X
X
H
L
High Z
High Z
High Z
Deselect / Power Down
Deselect / Power Down
Deselect / Power Down
Read
Standby (I
Standby (I
Standby (I
)
SB
L
)
SB
X
X
)
SB
L
H
H
Data Out (I/O –I/O
)
Active (I
Active (I
)
CC
0
15
L
L
H
L
Data Out (I/O –I/O );
Read
)
CC
0
7
High Z (I/O –I/O
)
8
15
L
H
H
L
L
H
High Z (I/O –I/O );
Read
Active (I
)
CC
0
7
Data Out (I/O –I/O
)
8
15
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
)
CC
)
CC
L
Data In (I/O –I/O
)
)
CC
0
15
L
H
Data In (I/O –I/O );
High Z (I/O –I/O
Write
)
CC
0
7
)
8
15
L
H
L
X
L
H
High Z (I/O –I/O );
Write
Active (I
)
CC
0
7
Data In (I/O –I/O
)
8
15
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62167EV18LL-55BAXI
CY62167EV18LL-55BVI
CY62167EV18LL-55BVXI
55
001-13297 48-ball VFBGA (6 × 7 × 1 mm) (Pb-free)
51-85150 48-ball VFBGA (6 × 8 × 1 mm)
48-ball VFBGA (6 × 8 × 1 mm) (Pb-free)
Industrial
CY62167EV30LL-45BVI
51-85150 48-ball VFBGA (6 × 8 × 1 mm)
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297
NOTES:
1. ALL DIMENSION ARE IN MM [MAX/MIN]
2. JEDEC REFERENCE : MO-216
3. PACKAGE WEIGHT : 0.03g
001-13297-*A
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Package Diagram
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85150-*D
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Document History Page
®
Document Title: CY62167EV18 MoBL 16 Mbit (1M x 16) Static RAM
Document Number: 38-05447
Orig. of
Change
Submission
date
REV.
ECN NO.
Description of Change
**
202600
463674
AJU
01/23/2004 New Data Sheet
*A
NXR
See ECN
Converted from Advance Information to Preliminary
Changed V from 2.20V to 2.25V
CC(max)
Removed ‘L’ bin and 35 ns speed bin from product offering
Changed ball E3 from DNU to NC
Removed redundant foot note on DNU
Changed the I
Changed the I
value from 1.3 μA to 1.5 μA
value from 40 mA to 25 mA
SB2(typ)
CC(max)
Changed the AC Test Load Capacitance value from 50 pF to 30 pF
Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns
Changed the I
Value from 8 μA to 5 μA
CCDR
Changed t
Changed t
Changed t
Changed t
, t
, t
, and t
from 6 ns to 10 ns
OHA LZCE LZBE
LZWE
from 3 ns to 5 ns
LZOE
, t
, t
, and t
from 15 ns to 18 ns
HZOE HZCE HZBE
HZWE
, t , and t from 40 ns to 35 ns
SCE AW
BW
Changed t from 30 ns to 35 ns
PE
Changed t from 20 ns to 25 ns
SD
Updated 48 ball FBGA Package Information
Updated the Ordering Information table
*B
*C
*D
469182
619122
1130323
NSI
NXR
VKN
See ECN
See ECN
See ECN
Minor Change: Moved to external web
Replaced 45 ns speed bin with 55 ns speed bin
Converted from preliminary to final
Added footnote# 8 related I
and I
SB2
CCDR
Changed I
Changed I
and I
spec from 10 μA to 12 μA
SB1
SB2
spec from 8 μA to 10 μA
CCDR
Added footnote# 13 related AC timing parameters
Changed t
Changed t
Changed t
spec from 45 ns to 55 ns
WC
, t , t
, t
spec from 35 ns to 40 ns
SCE AW PWE BW
spec from 18 ns to 20 ns
HZWE
*E
1388287
VKN
See ECN
See ECN
Added 48-Ball VFBGA (6 x 7 x 1mm) package
Added footnote# 1 related to FBGA package
Updated Ordering Information table
*F
1664843
2675375
VKN/AESA
VKN/PYRS
Added CY62167EV30LL-45BVI part in the Ordering Information table
Added footnote# 5 related to CY62167EV30LL-45BVI part
*G
03/17/2009 Added CY62167EV18LL-55BVI part in the Ordering Information table
Document #: 38-05447 Rev. *G
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CY62167EV18 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05447 Rev. *G
Revised March 13, 2009
Page 13 of 13
MoBL is aregisteredtrademark andMore Battery Lifeis atrademark of Cypress Semiconductor. All product andcompany names mentioned in this document are the trademarks of their respective holders.
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