CY62146DV30
4-Mbit (256K x 16) Static RAM
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
Features
• Very high speed: 45 ns
deselected (CE HIGH). The input/output pins (I/O through
0
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62146CV30
• Ultra-low active power
I/O ) are placed in a high-impedance state when: deselected
15
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
— Typical active current: 1.5 mA @ f = 1 MHz
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
— Typical active current: 8 mA @ f = f
• Ultra low standby power
max
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
0
7
written into the location specified on the address pins (A
0
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
through A ). If Byte High Enable (BHE) is LOW, then data
17
from I/O pins (I/O through I/O ) is written into the location
8
15
specified on the address pins (A through A ).
0
17
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-free packages
Functional Description[1]
pins will appear on I/O to I/O . If Byte High Enable (BHE) is
0
7
LOW, then data from memory will appear on I/O to I/O . See
8
15
The CY62146DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146DV30 is available in a 48-ball VFBGA, 44-pin
TSOPII packages.
is ideal for providing More Battery Life™ (MoBL ) in portable
applications such as cellular telephones. The device also has
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
Cypress Semiconductor Corporation
Document #: 38-05339 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 2, 2005
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CY62146DV30
DC Input Voltage
.....................–0.3V to V
+ 0.3V
Maximum Ratings
CC(MAX)
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Ambient Tem-
Potential......................................–0.3V to + V
+ 0.3V
+ 0.3V
CC(MAX)
.........................–0.3V to V
CC(MAX)
Device
Range perature (T )
V
CC
A
CY62146DV30L Industrial –40°C to +85°C 2.20V to 3.60V
CY62146DV30LL
in High-Z State
Electrical Characteristics Over the Operating Range
CY62146DV30-45
CY62146DV30-55
CY62146DV30-70
Parameter Description
Test Conditions
Min. Typ.
2.0
Max. Min. Typ.
Max. Min. Typ.
Max. Unit
V
V
V
Output HIGH I = –0.1 mA V = 2.20V
Voltage
2.0
2.4
2.0
2.4
V
V
V
V
V
OH
OL
IH
OH
CC
I
= –1.0 mA V = 2.70V
2.4
OH
CC
Output LOW I = 0.1 mA V = 2.20V
Voltage
0.4
0.4
0.4
0.4
0.4
0.4
OL
CC
I
= 2.1 mA V = 2.70V
CC
OL
Input HIGH
Voltage
V
= 2.2V to 2.7V
1.8
2.2
V
0.3V
+
1.8
2.2
V
0.3V
+
1.8
2.2
V
CC
0.3V
+
CC
CC
CC
V
= 2.7V to 3.6V
V
+
V
+
V
+
V
CC
CC
CC
CC
0.3V
0.3V
0.3V
V
I
Input LOW
Voltage
V
V
= 2.2V to 2.7V
= 2.7V to 3.6V
–0.3
–0.3
–1
0.6
0.8
+1
–0.3
–0.3
–1
0.6
0.8
+1
–0.3
–0.3
–1
0.6
0.8
+1
V
V
IL
CC
CC
InputLeakage GND < V < V
Current
µA
IX
I
CC
I
I
Output
Leakage
Current
GND < V < V , Output
Disabled
–1
+1
–1
+1
–1
+1
µA
OZ
O
CC
V
f = f
=
V
= V
CCmax
= 0 mA
10
20
3
8
15
3
8
15
3
mA
CC
CC
MAX
CC
Operating
Supply
Current
1/t
I
RC
OUT
CMOS levels
f = 1 MHz
1.5
2
1.5
2
1.5
2
mA
I
I
Automatic
CE
Power-down f = f
Current —
CMOS
Inputs
CE > V −0.2V,
L
12
8
12
8
12
8
µA
SB1
CC
V >V –0.2V, V <0.2V)
IN
CC
IN
LL
(Address and Data
MAX
Only),
f = 0 (OE, WE, BHE and
BLE), V = 3.60V
CC
Automatic
CE
Power-down 0.2V,
CE > V – 0.2V,
L
2
12
8
2
12
8
2
12
8
µA
SB2
CC
V
> V – 0.2V or V
<
IN
CC
IN
LL
Current —
f = 0, V = 3.60V
CC
CMOS Inputs
Notes:
6. V
7. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
8. Full device AC operation assumes a 100-µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
Document #: 38-05339 Rev. *A
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CY62146DV30
Capacitance (for all packages)
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
10
Unit
pF
C
C
Input Capacitance
Output Capacitance
IN
A
V
= V
CC
CC(typ)
10
pF
OUT
Parameter
Description
Test Conditions
BGA
TSOP II
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
72
75.13
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
8.86
8.95
°C/W
JC
AC Test Loads and Waveforms[10]
R1
ALL INPUT PULSES
V
V
CC
CC
90%
10%
90%
OUTPUT
10%
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
R2
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
Ω
R
Ω
TH
TH
V
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min. Typ.
Max. Unit
V
V
for Data Retention
1.5
V
DR
CC
I
Data Retention Current
V
= 1.5V
L
9
6
µA
CCDR
CC
CE > V – 0.2V,
CC
LL
V
> V – 0.2V or V < 0.2V
CC IN
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
t
R
RC
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
V
V
CC(min)
CC(min)
V
V
CC
DR
t
t
R
CDR
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Test condition for the 45 ns part is a load capacitance of 30 pF.
11. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05339 Rev. *A
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CY62146DV30
Switching Characteristics Over the Operating Range
45 ns
55 ns
70 ns
Parameter
Description
Min.
Max.
Min.
55
Max.
Min.
70
Max.
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
55
70
AA
Data Hold from Address Change
CE LOW to Data Valid
10
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
25
55
25
70
35
OE LOW to Data Valid
OE LOW to LOW Z
5
10
0
5
10
0
5
10
0
OE HIGH to High Z
15
20
20
20
25
25
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
45
25
55
25
70
35
PD
DBE
LZBE
HZBE
BLE/BHE LOW to Low Z
10
10
10
BLE/BHE HIGH to HIGH Z
15
20
25
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
HA
0
0
0
SA
35
40
25
0
40
40
25
0
45
60
30
0
PWE
BW
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
SD
HD
WE LOW to High-Z
15
20
25
HZWE
LZWE
WE HIGH to Low-Z
10
10
10
Notes:
12. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2,
CC(typ)
input pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
given device.
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedence state.
HZOE HZCE HZBE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05339 Rev. *A
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CY62146DV30
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .
IL
IL
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05339 Rev. *A
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CY62146DV30
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATAIN
DATA I/O
NOTE 21
t
HZOE
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 21
t
HZOE
Notes:
19. Data I/O is high impedance if OE = V
.
IH
20. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.
IH
21. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05339 Rev. *A
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CY62146DV30
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATAI/O
DATAIN
t
HZWE
t
LZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
t
SA
tPWE
WE
tHZWE
tHD
t
SD
DATA I/O
DATAIN
NOTE 21
tLZWE
Document #: 38-05339 Rev. *A
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CY62146DV30
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
High Z
Data Out (I/O –I/O
Mode
Deselect/Power-Down
Output Disabled
Read
Power
Standby (I
)
SB
X
X
H
H
Active (I
Active (I
Active (I
)
CC
L
H
L
L
L
)
)
CC
O
15
L
H
L
H
L
Data Out (I/O –I/O );
Read
)
CC
O
7
I/O –I/O in High Z
8
15
L
H
L
L
H
Data Out (I/O –I/O );
Read
Active (I
)
8
15
CC
I/O –I/O in High Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
High Z
High Z
)
CC
)
CC
L
Data In (I/O –I/O
)
)
CC
O
15
L
H
Data In (I/O –I/O );
Write
)
CC
O
7
I/O –I/O in High Z
8
15
L
L
X
L
H
Data In (I/O –I/O );
Write
Active (I
)
8
15
CC
I/O –I/O in High Z
0
7
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
45
CY62146DV30LL-45BVI
CY62146DV30LL-45BVXI
CY62146DV30LL-45ZSXI
CY62146DV30L-55BVI
CY62146DV30L-55BVXI
BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free)
44-pin TSOP II (Pb-free)
ZS-44
55
BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30LL-55BVI
CY62146DV30LL-55BVXI
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30L-55ZSXI
CY62146DV30LL-55ZSXI
CY62146DV30L-70BVI
CY62146DV30L-70BVXI
ZS-44
44-pin TSOP II (Pb-free)
70
BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
Industrial
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30LL-70BVI
CY62146DV30LL-70BVXI
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62146DV30L-70ZSXI
CY62146DV30LL-70ZSXI
ZS-44
44-pin TSOP II (Pb-free)
Document #: 38-05339 Rev. *A
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CY62146DV30
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-Pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05339 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.
CY62146DV30
Document History Page
®
Document Title:CY62146DV30 MoBL 4-Mbit (256K x 16) Static RAM
Document Number: 38-05339
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
213251
316039
See ECN
See ECN
AJU
PCI
New Data Sheet
*A
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #10 on page #4
Added Pb-free package ordering information on page # 9
Changed 44-lead TSOP-II package name on page 10 from Z44 to ZS44
Standardized Icc values across ‘L’ and ‘LL’ bins
Document #: 38-05339 Rev. *A
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