MoBL® CY62128E
1-Mbit (128K x 8) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL ) in portable
■ Temperature ranges
®
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH or CE LOW). The
■ Voltage range: 4.5V to 5.5V
■ Pin compatible with CY62128B
1
2
eight input and output pins (IO through IO ) are placed in a high
0
7
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA (Industrial)
impedance state when the device is deselected (CE HIGH or
1
CE LOW), the outputs are disabled (OE HIGH), or a write
2
operation is in progress (CE LOW and CE HIGH and WE LOW)
1
2
To write to the device, take Chip Enable (CE LOW and CE
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
1
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins (IO through IO ) is then written into the location specified
0
7
■ Easy memory expansion with CE , CE and OE features
on the address pins (A through A ).
1
2,
0
16
■ Automatic power down when deselected
■ CMOS for optimum speed and power
To read from the device, take Chip Enable (CE LOW and CE
2
1
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the IO pins.
■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin TSOP I packages
Logic Block Diagram
IO
0
INPUT BUFFER
A
0
A
1
IO
1
A
2
A
3
IO
2
A
4
A
A
A
A
A
A
A
128K x 8
ARRAY
IO
3
5
6
IO
IO
IO
IO
7
4
5
6
7
8
9
10
11
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 4, 2008
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MoBL® CY62128E
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up Current.....................................................> 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Ambient
[7]
V
CC
Device
Range
Supply Voltage to Ground
Potential............................... –0.5V to 6.0V (V
Temperature
+ 0.5V)
CC(max)
CY62128ELL Ind’l/Auto-A
Auto-E
–40°C to +85°C 4.5V to 5.5V
–40°C to +125°C
in High-Z State
.............. –0.5V to 6.0V (V
+ 0.5V)
+ 0.5V)
CC(max)
........... –0.5V to 6.0V (V
CC(max)
DC Input Voltage
Electrical Characteristics (Over the Operating Range)
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Description
Test Conditions
= –1 mA
Unit
[3]
Min Typ
Max
Min Typ
2.4
Max
V
Output HIGH
Voltage
I
I
2.4
V
V
OH
OH
V
Output LOW
Voltage
= 2.1 mA
0.4
0.4
OL
OL
V
V
I
Input HIGH Voltage V = 4.5V to 5.5V
2.2
–0.5
–1
V
+ 0.5 2.2
V + 0.5
CC
V
V
IH
CC
CC
Input LOW voltage V = 4.5V to 5.5V
0.8
+1
–0.5
–4
0.8
+4
IL
CC
Input Leakage
Current
GND < V < V
CC
μA
IX
I
I
I
Output Leakage
Current
GND <V <V , Output Disabled –1
+1
–4
+4
μA
OZ
O
CC
V
Operating
f = f
= 1/t
V
= V
CC(max)
= 0 mA
11
16
2
11
35
4
mA
CC
CC
max
RC CC
Supply Current
I
OUT
f = 1 MHz
1.3
1.3
CMOS levels
I
Automatic CE
Power down
Current—CMOS
Inputs
CE > V – 0.2V or CE < 0.2V,
1
4
1
30
μA
SB2
1
CC
2
V
> V – 0.2V or V < 0.2V,
IN
CC IN
f = 0, V = V
CC
CC(max)
[9]
Capacitance (For all Packages)
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max
10
Unit
C
C
Input Capacitance
Output Capacitance
pF
pF
IN
A
V
= V
CC
CC(typ)
10
OUT
Notes
5.
6.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
CC
CC
8. Only chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
SOIC
Package
STSOP
Package
TSOP
Unit
Parameter
Description
Test Conditions
Package
Θ
Thermal Resistance
(Junction to Ambient) two-layer printed circuit board
Still Air, soldered on a 3 × 4.5 inch,
48.67
25.86
32.56
3.59
33.01
°C/W
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
3.42
JC
AC Test Loads and Waveform
R1
ALL INPUT PULSES
90%
V
CC
3.0V
GND
OUTPUT
90%
10%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
Value
1800
990
Unit
Ω
R1
R2
Ω
R
639
Ω
TH
V
1.77
V
TH
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min Typ
Max Unit
V
V
for Data Retention
2
V
DR
CC
I
Data Retention Current
V
V
=V , CE > V − 0.2V or CE < 0.2V, Ind’l/Auto-A
4
μA
μA
ns
CCDR
CC
IN
DR
1
CC
2
> V - 0.2V or V < 0.2V
CC
IN
Auto-E
30
t
t
Chip Deselect to Data
Retention Time
0
CDR
Operation Recovery
Time
t
ns
R
RC
Data Retention Waveform[11]
DATA RETENTION MODE
> 2.0V
V
V
CC(min)
V
CC(min)
VCC
DR
t
t
R
CDR
CE
Notes
10. Full device AC operation requires linear V ramp from V to V
> 100 μs or stable at V
2
> 100 μs.
CC
DR
CC(min)
CC(min)
11. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
1
2
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Switching Characteristics (Over the Operating Range)
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Read Cycle
Description
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
55
AA
Data Hold from Address Change
CE LOW and CE HIGH to Data Valid
10
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
55
25
1
2
OE LOW to Data Valid
OE LOW to Low-Z
5
10
0
5
10
0
OE HIGH to High-Z
18
18
45
20
20
55
CE LOW and CE HIGH to Low-Z
1
2
CE HIGH or CE LOW to High-Z
1
2
CE LOW and CE HIGH to Power Up
1
2
CE HIGH or CE LOW to Power Down
PD
1
2
Write Cycle
t
t
t
Write Cycle Time
45
35
35
55
ns
ns
ns
WC
SCE
AW
CE LOW and CE HIGH to Write End
40
40
1
2
Address Setup to Write End
t
t
t
t
t
t
t
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
0
0
ns
ns
ns
ns
ns
ns
ns
0
0
HA
SA
35
25
0
40
25
0
PWE
SD
Data Setup to Write End
Data Hold from Write End
HD
WE LOW to High-Z
18
20
HZWE
LZWE
WE HIGH to Low-Z
10
10
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
14. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Switching Waveforms
Figure 1. Read Cycle 1 (Address Transition Controlled)
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
]
Figure 2. Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Figure 3. Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA IO
NOTE
DATA VALID
t
HZOE
Notes:
16. The device is continuously selected. OE, CE = V , CE = V .
1
IL
2
IH
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Switching Waveforms (continued)
Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE
DATA VALID
DATA IO
t
t
LZWE
HZWE
Truth Table
CE
H
X
CE
X
WE
X
OE
X
Inputs/Outputs
High-Z
Mode
Power
1
2
Deselect/Power down
Deselect/Power down
Read
Standby (I
Standby (I
)
SB
SB
L
X
X
High-Z
)
L
H
H
L
Data Out
Data In
High-Z
Active (I
Active (I
Active (I
)
)
)
CC
CC
CC
L
H
L
X
Write
L
H
H
H
Selected, Outputs Disabled
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62128ELL-45SXI
CY62128ELL-45ZAXI
CY62128ELL-45ZXI
CY62128ELL-45SXA
CY62128ELL-45ZXA
CY62128ELL-55SXE
CY62128ELL-55ZAXE
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85094 32-pin STSOP (Pb-free)
Industrial
51-85056 32-pin TSOP Type I (Pb-free)
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85056 32-pin TSOP Type I (Pb-free)
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85094 32-pin STSOP (Pb-free)
45
55
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 6. 32-pin (450 Mil) Molded SOIC (51-85081)
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Figure 7. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm) (51-85094)
51-85094-*D
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Figure 8. 32-pin Thin Small Outline Package Type I (8 x 20 mm) (51-85056)
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Document History Page
®
Document Title: CY62128E MoBL 1-Mbit (128K x 8) Static RAM
Document Number: 38-05485
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
**
203120
299472
See ECN
See ECN
AJU New data sheet
*A
SYT Converted from Advance Information to Preliminary
Changed t
Changed t
Changed t
from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
from 15 ns to 18 ns for 35 ns speed bin
OHA
DOE
, t
from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
HZOE HZWE
speed bins, respectively
Changed t from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed
HZCE
bins, respectively
Changed t from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed
SCE
bins, respectively
Changed t from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
SD
respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of I
, I
and I
from 1.0 μA to 1.5 μA
SB1 SB2
CCDR
*B
461631
See ECN
NXR Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed I
from 8 mA to 11 mA and I
from 12 mA to 16 mA for f
CC (Typ)
CC (max)
= f
max
Changed I
Removed I
Changed I
Changed I
Changed I
from 1.5 mA to 2.0 mA for f = 1 MHz
DC Specs from Electrical characteristics table
from 1.5 μA to 4 μA
CC (max)
SB1
SB2 (max)
SB2 (Typ)
from 0.5 μA to 1 μA
from 1.5 μA to 4 μA
CCDR (max)
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed t
Changed t
Changed t
Changed t
from 3 to 5 ns
from 6 to 10 ns
from 22 to 18 ns
from 30 to 35 ns
LZOE
LZCE
HZCE
PWE
Changed t from 22 to 25 ns
SD
Changed t
from 6 to 10 ns
LZWE
Updated the Ordering Information Table
NXR Updated the Block Diagram on page # 1
AJU Added footnote 4 on page 2
*C
*D
*E
464721
563144
1024520
See ECN
See ECN
See ECN
VKN Added Automotive-A information
Converted Automotive-E specs to final
Added footnote #9 related to I
and I
SB2
CCDR
Updated Ordering Information table
*F
2548575
08/05/08
NXR Corrected typo error in Ordering Information table
Document #: 38-05485 Rev. *F
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MoBL® CY62128E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
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wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05485 Rev. *F
Revised August 4, 2008
Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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