CYV15G0404DXB
Independent Clock Quad HOTLink II™
Transceiver with Reclocker
■ Synchronous LVTTL parallel interface
■ JTAG boundary scan
Features
■ Quad channel transceiver for 195 to 1500 MBaud serial
signaling rate
■ Built In Self Test (BIST) for at-speed link testing
❐ Aggregate throughput of up to 12 Gbits/second
■ Link quality indicator by channel
❐ Analog signal detect
®
■ Second-generation HOTLink technology
❐ Digital signal detect
■ Compliant to multiple standards
❐ SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES-
■ Low power 3W at 3.3V typical
■ Single 3.3V supply
CON, and Gigabit Ethernet (IEEE802.3z)
❐ 10 bit uncoded data or 8B/10B coded data
■ 256 ball thermally enhanced BGA
■ 0.25μ BiCMOS technology
■ JTAG device ID ‘0C811069’x
■ Truly independent channels
❐ Each channel is able to:
• Perform reclocker function
• Operate at a different signaling rate
• Transport a different data format
Functional Description
■ Internal phase-locked loops (PLLs) with no external PLL
components
The CYV15G0404DXB Independent Clock Quad HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communica-
tions building block enabling the transfer of data over a variety of
high speed serial links including SMPTE 292, SMPTE 259, and
DVB-ASI video applications. The signaling rate can be anywhere
in the range of 195 to 1500 MBaud for each serial link. Each
channel operates independently with its own reference clock
allowing different rates. Each transmit channel accepts parallel
characters in an input register, encodes each character for
transport, and then converts it to serial data. Each receive
channel accepts serial data and converts it to parallel data,
decodes the data into characters, and presents these characters
to an output register. The received serial data can also be
reclocked and retransmitted through the serial outputs. Figure 1
illustrates typical connections between independent video
coprocessors and corresponding CYV15G0404DXB chips.
■ Selectable differential PECL compatible serial inputs per
channel
❐ Internal DC restoration
■ Redundant differential PECL compatible serial outputs per
channel
❐ No external bias resistors required
❐ Signaling rate controlled edge rates
❐ Source matched for 50Ω transmission lines
■ MultiFrame™ Receive Framer provides alignment options
❐ Comma or full K28.5 detect
❐ Single or multibyte Framer for byte alignment
❐ Low latency option
■ Selectable input and output clocking options
Figure 1. HOTLink II™ System Connections
10
10
Serial Links
10
10
10
Independent
Channel
CYV15G0404DXB
10
10
Serial Links
Serial Links
10
10
Independent
Channel
CYV15G0404DXB
10
10
Reclocker
10
10
Reclocker
10
Serial Links
10
10
Cable
Connections
Cypress Semiconductor Corporation
Document #: 38-02097 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 14, 2007
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CYV15G0404DXB
RECLCK[A..D] are Internal Reclocker Signals
TXLB[A..D] are Internal Serial Loopback Signals
Transmit Path Block Diagram
REFCLKA+
Bit-Rate Clock
OEA[2..1]
REFCLKA–
TXRATEA
= Internal Signal
TransmitPLL
ClockMultiplierA
Character-Rate Clock A
PABRSTA
SPDSELA
TXCLKOA
ENCBYPA
RECLCKA
OEA[2..1]
TXERRA
TXCLKA
A
TXBIST
0
1
TXCKSELA
8
OUTA1+
OUTA1–
TXDA[7:0]
10
10
10
10
2
OUTA2+
OUTA2–
TXCTA[1:0]
TXLBA
REFCLKB+
REFCLKB–
Bit-Rate Clock
OEB[2..1]
Transmit PLL
Clock Multiplier B
TXRATEB
SPDSELB
TXCLKOB
ENCBYPB
RECLCKB
Character-Rate Clock B
PABRSTB
TXERRB
TXCLKB
B
TXBIST
OEB[2..1]
0
1
TXCKSELB
OUTB1+
OUTB1–
8
10
10
10
10
TXDB[7:0]
OUTB2+
OUTB2–
2
TXCTB[1:0]
TXLBB
REFCLKC+
REFCLKC–
Bit-Rate Clock
OEC[2..1]
Transmit PLL
Clock Multiplier C
TXRATEC
SPDSELC
TXCLKOC
RECLCKC
OEC[2..1]
ENCBYPC
Character-Rate Clock C
PABRSTC
TXERRC
TXCLKC
C
TXBIST
0
1
TXCKSELC
8
OUTC1+
OUTC1–
TXDC[7:0]
10
10
10
10
2
OUTC2+
OUTC2–
TXCTC[1:0]
TXLBC
REFCLKD+
REFCLKD–
Bit-Rate Clock
OED[2..1]
Transmit PLL
Clock Multiplier D
RECLCKD
OED[2..1]
TXRATED
SPDSELD
TXCLKOD
TXERRD
ENCBYPD
Character-Rate Clock D
PABRSTD
TXBISTD
TXCLKD
0
1
TXCKSELD
OUTD1+
OUTD1–
10
8
10
10
10
TXDD[7:0]
OUTD2+
OUTD2–
2
TXCTD[1:0]
TXLBD
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
RECLCK[A..D] are Internal Reclocker Signals
TXLB[A..D] are Internal Serial Loopback Signals
Receive Path Block
= Internal Signal
RESET
TRST
JTAG
Boundary
Scan
TMS
TCLK
TDI
SPDSELA
RXPLLPDA
RCLKENA
RECLCKA
Controller
TDO
LFIA
Receive
Signal
LPENA
INSELA
Monitor
INA1+
INA1–
8
RXDA[7:0]
INA2+
INA2–
TXLBA
Clock &
Data
Recovery
PLL
3
RXSTA[2:0]
ULCA
SPDSELB
RXPLLPDB
RCLKENB
RXCLKA+
RXCLKA–
Clock
÷2
RECLCKB
Select
Receive
Signal
Monitor
LPENB
INSELB
LFIB
INB1+
INB1–
8
RXDB[7:0]
Clock &
Data
Recovery
PLL
INB2+
INB2–
TXLBB
3
RXSTB[2:0]
ULCB
SPDSELC
RXPLLPDC
RCLKENC
Clock
÷2
RXCLKB+
RXCLKB–
RECLCKC
Select
LPENC
INSELC
Receive
Signal
Monitor
LFIC
INC1+
INC1–
8
RXDC[7:0]
INC2+
INC2–
TXLBC
Clock &
Data
Recovery
PLL
3
RXSTC[2:0]
ULCC
SPDSELD
RXPLLPDD
Clock
÷2
RXCLKC+
RXCLKC–
RECLCKD
RCLKEND
Select
LPEND
INSELD
Receive
Signal
Monitor
LFID
IND1+
IND1–
8
RXDD[7:0]
IND2+
IND2–
TXLBD
Clock &
Data
Recovery
PLL
3
RXSTD[2:0]
ULCD
SDASEL[A..D][1:0]
LDTDEN
Clock
÷2
RXCLKD+
RXCLKD–
Select
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Device Configuration and Control Block
= Internal Signal
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
TXRATE[A..D]
TXCKSEL[A..D]
PABRST[A..D]
TXBIST[A..D]
WREN
Device Configura-
tion and Control
ADDR[3:0]
DATA[7:0]
Interface
OE[A..D][2..1]
ENCBYP[A..D]
GLEN[11..0]
FLEN[2..0]
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
IN
C1–
OUT
C1–
IN
C2–
OUT
C2–
IN
D1–
OUT
D1–
IN
D2–
OUT
D2–
IN
A1–
OUT
A1–
IN
A2–
OUT
A2–
IN
B1–
OUT
B1–
IN
B2–
OUT
B2–
V
GND
GND
V
CC
CC
CC
CC
CC
CC
CC
CC
IN
C1+
OUT
C1+
IN
C2+
OUT
C2+
IN
D1+
OUT
D1+
IN
D2+
OUT
D2+
IN
A1+
OUT
A1+
IN
A2+
OUT
A2+
IN
B1+
OUT
B1+
IN
B2+
OUT
B2+
V
V
V
GND
GND
GND
GND
GND
GND
V
V
V
TDI
TMS INSELC INSELB
INSELD INSELA
ULCD ULCC
DATA
[7]
DATA
[5]
DATA
[3]
DATA
[1]
RCLK
ENB
SPD
SELD
LDTD TRST LPEND TDO
EN
TCLK
ULCA
SPD
SELC
DATA
[6]
DATA
[4]
DATA
[2]
DATA
[0]
LPENB ULCB
LPENA VCC
SCAN TMEN3
EN2
E
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
F
G
H
RX
RX
TX
RCLK
END
RCLK
RX
TX
RX
DC[6] DC[7] DC[0]
ENA STB[1] CLKOB STB[0]
TX
DC[7]
WREN
TX
TX
SPD
SELB
LP
ENC
SPD
SELA DB[1]
RX
DC[4] DC[1]
GND GND GND GND
GND GND GND GND
J
K
L
TX
TX
TX
TX
RX
RX
RX
DB[5]
RX
DB[2]
CTC[1] DC[5] DC[2] DC[3]
STB[2] DB[0]
RX
REF
TX
TX
RX
DB[3]
RX
DB[4]
RX
DB[7]
LFIB
DC[2] CLKC– CTC[0] CLKC
RX
REF
LFIC
TX
RX
RX
RX
TX
DC[3] CLKC+
DC[6]
DB[6] CLKB+ CLKB– DB[6]
M
N
RX
RX
RCLK
ENC
TX
ERRC
REF REF TX TX
DC[4] DC[5]
CLKB+ CLKB– ERRB CLKB
GND GND GND GND
GND GND GND GND
P
R
T
RX
RX
RX
RX
TX
DB[5]
TX
DB[4]
TX
DB[3]
TX
DB[2]
DC[1] DC[0] STC[0] STC[1]
RX
TX
RX
RX
TX
DB[1]
TX
TX
TX
STC[2] CLKOC CLKC+ CLKC–
DB[0] CTB[1] DB[7]
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
U
V
TX
TX
TX
TX
RX
RX
TX
CTA[1]
ADDR
[0] CLKD– DA[1]
REF
TX
TX
TX
RX
TX
RX
RX
V
V
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
DD[0] DD[1] DD[2] CTD[1]
DD[2] DD[1]
DA[4] CTA[0]
DA[2] CTB[0] STA[2] STA[1]
TX
TX
TX
RX
RX
RX
RX
STD[2]
ADDR
[2]
REF
CLKD+ CLKOA
TX
TX
DA[3]
TX
DA[7]
RX
DA[7]
RX
DA[3]
RX
RX
DD[3] DD[4] CTD[0] DD[6]
DD[3] STD[0]
DA[0] STA[0]
W
Y
TX
TX
LFID
RX
RX
CLKD–
RX
RX
ADDR ADDR
[3]
RX
TX
TX
DA[2]
TX
DA[6]
LFIA
REF
CLKA+ DA[4]
RX
RX
DA[1]
DD[5] DD[7]
DD[4] STD[1]
[1]
CLKA+ ERRA
[1]
TX
TX
RX
RX
RX
TX
CLKOD
NC
TX
RX
TX
DA[0]
TX
DA[5]
TX
REF RX
RX
DA[5]
DD[6] CLKD DD[7] CLKD+
DD[5] DD[0]
CLKA CLKA–
ERRD CLKA– DA[6]
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Configuration (Bottom View)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUT
B2–
IN
B2–
OUT
B1–
IN
B1–
OUT
A2–
IN
A2–
OUT
A1–
IN
A1–
OUT
D2–
IN
D2–
OUT
D1–
IN
D1–
OUT
C2–
IN
C2–
OUT
C1–
IN
C1–
V
GND
GND
V
CC
CC
CC
CC
CC
CC
CC
CC
A
B
C
D
E
F
OUT
B2+
IN
B2+
OUT
B1+
IN
B1+
OUT
A2+
IN
A2+
OUT
A1+
IN
A1+
OUT
D2+
IN
D2+
OUT
D1+
IN
D1+
OUT
C2+
IN
2+
OUT
C1+
IN
C1+
V
V
V
GND
GND
GND
GND
GND
GND
V
V
V
TDO
LP
END
TRST LDTD
EN
SPD
SELD
RCLK
ENB
DATA
[1]
DATA
[3]
DATA
[5]
DATA
[7]
ULCC ULCD
IN
IN
TMS
TDI
SELB SELC
TMEN3 SCAN
EN2
VCC
LP
ENA
ULCB
LP
ENB
DATA
[0]
DATA
[2]
DATA
[4]
DATA
[6]
SPD
SELC
ULCA
IN
IN
RESET TCLK
SELA SELD
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
RX
TX
RX
RCLK
RCLK
END
TX
RX
Rx
STB[0] CLKOB STB[1] ENA
DC[0] DC[7] DC[6]
RX
SPD
LP
ENC
SPD
SELB
TX
TX
WREN
TX
DC[7]
G
H
J
DB[1] SELA
DC[1] DC[4]
GND GND GND GND
GND GND GND GND
RX
DB[2]
RX
DB[5]
RX
RX
TX
TX
TX
TX
DB[0] STB[2]
DC[3] DC[2] DC[5] CTC[1]
LFIB
RX
DB[7]
RX
DB[4]
RX
DB[3]
TX
TX
REF
RX
K
L
CLKC CTC[0] CLKC– DC[2]
TX
RX
RX
RX
TX
DC[6]
LFIC
REF
CLKC+ DC[3]
RX
DB[6] CLKB– CLKB+ DB[6]
TX
TX
REF
REF
TX
ERRC
RCLK
ENC
RX
RX
M
N
P
R
T
CLKB ERRB CLKB– CLKB+
DC[5] DC[4]
GND GND GND GND
GND GND GND GND
TX
DB[2]
TX
DB[3]
TX
DB[4]
TX
DB[5]
RX
RX
RX
RX
STC[1] STC[0] DC[0] DC[1]
TX
TX
TX
TX
DB[1]
RX
RX
TX
RX
DB[7] CTB[1] DB[0]
CLKC– CLKC+ CLKOC STC[2]
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
RX
RX
TX
RX
TX
TX
TX
REF
ADDR
[0]
TXC
TA[1]
RX
RX
TX
TX
TX
TX
V
V
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
U
V
W
STA[1] STA[2] CTB[0] DA[2]
CTA[0] DA[4]
DA[1] CLKD–
DD[1] DD[2]
CTD[1] DD[2] DD[1] DD[0]
RX
RX
RX
DA[3]
RX
DA[7]
TX
DA[7]
TX
DA[3]
TX
REF
ADDR
[2]
RX
STD[2]
RX
RX
RX
TX
TX
TX
STA[0] DA[0]
CLKOA CLKD+
STD[0] DD[3]
DD[6] CTD[0] DD[4] DD[3]
RX
DA[1]
RX
REF
LFIA
TX
DA[6]
TX
DA[2]
TX
RX
ADDR ADDR
[1]
RX
RX
RX
CLKD–
LFID
TX
TX
DA[4] CLKA+
ERRA CLKA+
[3]
STD[1] DD[4]
DD[7] DD[5]
[1]
RX
DA[5]
RX
REF
TX
TX
DA[5]
TX
DA[0]
RX
TX
NC
TX
CLKOD
RX
RX
RX
RX
TX
TX
Y
DA[6] CLKA– ERRD
CLKA– CLKA
DD[0] DD[5]
CLKD+ DD[7] CLKD DD[6]
Note
1. NC=Do Not Connect
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Definitions
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
Transmit Path Data and Status Signals
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
LVTTL Input,
synchronous,
sampled by the
associated
Transmit Data Inputs. TXDx[7:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface, and passed to the encoder or Transmit
Shifter. When the Encoder is enabled, TXDx[7:0] specifies the specific data or
command character sent.
REFCLKx↑
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
LVTTL Input,
synchronous,
sampled by the
associated
Transmit Control. TXCTx[1:0] inputs are captured on the rising edge of the transmit
interface clock. The transmit interface clock is selected by the TXCKSELx latch
through the device configuration interface, and passed to the encoder or transmit
shifter. The TXCTA[1:0] inputs identify how the associated TXDx[7:0] characters are
interpreted. When the encoder is bypassed, these inputs are interpreted as data bits.
When the encoder is enabled, these inputs determine if the TXDx[7:0] character is
encoded as data, a special character code, or replaced with other special character
REFCLKx↑
TXERRA
TXERRB
TXERRC
TXERRD
LVTTL Output,
Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit
phase align buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until either a word sync sequence is transmitted on that channel, or the transmit
phase align buffer is recentered with the PABRSTx latch through the device configu-
ration interface. When TXBISTx = 0, the BIST progress is presented on the
associated TXERRx output. The TXERRx signal pulses HIGH for one transmit
character clock period to indicate a pass through the BIST sequence once every 511
or 527 (depending on RXCKSELx) character times. If RXCKSELx = 1, a one
character pulse occurs every 527 character times. If RXCKSELx = 0, a one character
synchronous to
REFCLKx↑
,
synchronous to
RXCLKx when
selected as
REFCLKx,
asynchronous to
transmit channel
enable/disable,
asynchronous to loss pulse occurs every 511 character times.
or return of
TXERRx is also asserted HIGH, when any of these conditions is true:
REFCLKx±
■ The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are simultaneous disabled by setting OE2x = 0 and
OE1x = 0.
■ The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
REFCLKC±
REFCLKD±
Differential LVPECL Reference Clock. REFCLKx± clock inputs are used as the timing references for the
or single ended
transmit and receive PLLs. These input clocks may also be selected to clock the
transmit and receive parallel interfaces. When driven by a single ended LVCMOS or
LVTTL clock source, connect the clock source to either the true or complement
REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven
by an LVPECL clock source, the clock must be a differential clock, using both inputs.
LVTTL input clock
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal pull down
Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the
associated TXCLKx input is selected as the character-rate input clock for the
TXDx[7:0] and TXCTx[1:0] inputs. In this mode, the TXCLKx input must be
frequency-coherent to its associated TXCLKOx output clock, but may be offset in
phase by any amount. Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity
of the phase align buffer, TXERRx is asserted to indicate the loss of data, and remains
asserted until the phase align buffer is initialized. The phase of the TXCLKx input
clock relative to its associated REFCLKx± is initialized when the configuration latch
PABRSTx is written as 0. When the associated TXERRx is deasserted, the phase
align buffer is initialized and input characters are correctly captured.
Notes
2. When REFCLKx± is configured for half rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
LVTTL Output
Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATE = 0), or at
twice the frequency of REFCLKx± (TXRATE = 1). The transmit clock outputs have no
fixed phase relationship to REFCLKx±.
Receive Path Data and Status Signals
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
LVTTL Output,
synchronous to the
selected RXCLK±
Parallel Data Output. RXDx[7:0] parallel data outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full rate clock, the RXCLKx± clock outputs are complementary clocks
output or REFCLKx± operating at the character rate. The RXDx[7:0] outputs for the associated receive
input
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXDx[7:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
LVTTL Output,
synchronous to the
selected RXCLK±
Parallel Status Output. RXSTA[2:0] status outputs change relative to the receive
interface clock. The receive interface clock is selected by the RXCKSELx latch. If
RXCLKx± is a full rate clock, the RXCLKx± clock outputs are complementary clocks
output or REFCLKx± operating at the character rate. The RXSTAx[2:0] outputs for the associated receive
input
channels follow rising edge of RXCLKx+ or falling edge of RXCLKx–. If RXCLKx± is
a half rate clock, the RXCLKx± clock outputs are complementary clocks operating at
half the character rate. The RXSTAx[2:0] outputs for the associated receive channels
follow both the falling and rising edges of the associated RXCLKx± clock outputs.
When the decoder is bypassed, RXSTx[1:0] become the two low-order bits of the
10-bit received character. RXSTx[2] = HIGH indicates the presence of a Comma
character in the Output Register. When the decoder is enabled, RXSTx[2:0] provide
Receive Path Clock Signals
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control timing
of the RXDx[7:0] and RXSTA[2:0] parallel outputs. The source of the RXCLKx±
outputs is selected by the RXCKSELx latch via the device configuration interface.
These true and complement clocks are used to control timing of data output transfers.
th
These clocks are output continuously at either the dual-character rate (1/20 the
th
serial bit-rate) or character rate (1/10 the serial bit-rate) of the data being received,
as selected by RXRATEx. When configured such that the output data path is clocked
by the REFCLKx± instead of a recovered clock, the RXCLKx± output drivers present
a buffered or divided form (depending on RXRATEx) of the associated REFCLKx±
that are delayed in phase to align with the data. This phase difference allows the user
to select the optimal clock (REFCLKx± or RXCLK±) for setup or hold timing for their
specific system.
When REFCLKx± is a full rate clock, the RXCLKx± rate depends on the value of
RXRATEx.
When REFCLKx± is a half rate clock and RXCKSELx = 0, the RXCLKx± rate depends
on the value of RXRATEx.
When REFCLKx± is a half rate clock and RXCKSELx=1, the RXCLKx± rate does not
depend on the value of RXRATEx and operates at the same rate as REFCLKx±.
Device Control Signals
RESET LVTTL Input,
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters,
and configuration latches are at an initial state. As per the JTAG specifications, the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
ration latches.
asynchronous,
internal pull up
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
LDTDEN
LVTTL Input,
internal pull up
Level Detect Transition Density Enable. When LDTDEN is HIGH, the signal level
detector, range controller, and transition density detector are all enabled to determine
if the RXPLL tracks REFCLKx± or the selected input serial data stream. If the signal
level detector, range controller, or transition density detector are out of their
respective limits while LDTDEN is HIGH, the RXPLL locks to REFCLK± until such a
time they become valid. The (SDASEL[A..D][1:0]) configure the trip level of the signal
level detector. The transition density detector limit is one transition in every 60
consecutive bits. When LDTDEN is LOW, only the range controller determines if the
RXPLL tracks REFCLKx± or the selected input serial data stream. For the cases
when RXCKSELx = 0 (recovered clock), it is recommended to set LDTDEN = HIGH.
RCLKENA
RCLKENB
RCLKENC
RCLKEND
LVTTL Input,
internal pull down
Reclocker Enable. When RCLKENx is HIGH, the RXPLL performs clock and data
recovery functions on the input serial data stream and routes the deserialized data
to the RXDx[7:0] and RXSTA[2:0] parallel data outputs as configured by DECBYPx.
It also presents the reclocked serial data to the enabled differential serial outputs.
When RCLKENx is LOW, the receive reclocker is disabled and the TXDx[7:0] parallel
data inputs and TXCTx[1:0] inputs are interpreted (as configured by ENCBYPx) to
generate appropriate 10-bit characters that are presented to the differential serial
outputs.
The reclocker feature is optimized to be used for SMPTE video applications.
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull up
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from REFCLKx±.
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select
Serial Rate Select. The SPDSELx inputs specify the operating signaling rate range
of each channel’s transmit and receive PLL.
static control input
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
Receive Input Selector. The INSELx input determines which external serial bit
stream is passed to the receiver’s clock and data recovery circuit. When INSELx is
HIGH, the primary differential serial data input, INx1±, is selected for the associated
receive channel. When INSELx is LOW, the secondary differential serial data input,
INx2±, is selected for the associated receive channel.
LPENA
LPENB
LPENC
LPEND
LVTTL Input,
asynchronous,
internal pull down
Loop Back Enable. The LPENx input enables the internal serial loop back for the
associated channel. When LPENx is HIGH, the transmit serial data from the
associated channel is internally routed to the associated receive Clock and Data
Recovery (CDR) circuit. All enabled serial drivers on the channel are forced to differ-
ential logic-1, and the serial data inputs are ignored. When LPENx is LOW, the
internal serial loop back function is disabled.
Notes
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually
SS
CC
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of five internal conditions. LFIx is asserted LOW when any of these condi-
tions are true:
■ Received serial data rate outside expected range
■ Analog amplitude below expected levels
■ Transition density lower than expected
■ Receive channel disabled
■ ULCx is LOW
■ No REFCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
the latch specified by the address location on the ADDR[3:0] bus.
[5]
internal pull up
ADDR[3:0]
LVTTL input
asynchronous,
internal pull up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configuration latches within the device, and the initialization value of the latches upon
DATA[7:0]
LVTTL input
asynchronous,
internal pull up
Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
latches within the device, and the initialization value of the latches upon the assertion
Internal Device Configuration Latches
RFMODE[A..D][1:0] Internal Latch
Reframe Mode Select.
FRAMCHAR[A..D] Internal Latch
Framing Character Select.
Receiver Decoder Mode Select.
Receiver Decoder Bypass.
Receive Clock Select.
DECMODE[A..D] Internal Latch
DECBYP[A..D]
RXCKSEL[A..D]
RXRATE[A..D]
Internal Latch
Internal Latch
Internal Latch
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Encoder Bypass.
Transmit Clock Select.
SDASEL[A..D][1:0] Internal Latch
ENCBYP[A..D]
TXCKSEL[A..D]
TXRATE[A..D]
RFEN[A..D]
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Transmit PLL Clock Rate Select.
Reframe Enable.
RXPLLPD[A..D]
RXBIST[A..D]
TXBIST[A..D]
OE2[A..D]
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Global Latch Enable.
OE1[A..D]
PABRST[A..D]
GLEN[11..0]
FGLEN[2..0]
Force Global Latch Enable.
Note
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
Factory Test Modes
SCANEN2
LVTTL input,
internal pull down
Factory Test 2. SCANEN2 input is for factory testing only. Leave this input as a NO
CONNECT or GND only.
TMEN3
LVTTL input,
internal pull down
Factory Test 3. TMEN3 input is for factory testing only. Leave this input as a NO
CONNECT or GND only.
Analog I/O
OUTA1±
OUTB1±
OUTC1±
OUTD1±
CML Differential
Output
Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC coupled for PECL
compatible connections.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
CML Differential
Output
Secondary Differential Serial Data Output. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber
optic transmitter modules, and must be AC coupled for PECL compatible connections.
INA1±
INB1±
INC1±
IND1±
Differential Input
Differential Input
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization and decoding. The INx1± serial stream is passed to the
receive CDR circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
Secondary Differential Serial Data Input. The INx2± input accepts the serial data
stream for deserialization and decoding. The INx2± serial stream is passed to the
receiver CDR circuit to extract the data content when INSELx = LOW.
JTAG Interface
TMS
LVTTL Input,
internal pull up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull down
JTAG Test Clock.
TDO
TDI
3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.
LVTTL Input,
Test Data In. JTAG data input port.
internal pull up
TRST
LVTTL Input,
internal pull up
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V
+3.3V Power.
CC
GND
Signal and Power Ground for all internal circuits.
When the encoder is bypassed, the control bits are part of the
preencoded 10-bit character.
CYV15G0404DXB HOTLink II Operation
The CYV15G0404DXB is a highly configurable, independent
clocking, quad-channel transceiver designed to support reliable
transfer of large quantities of data, using high speed serial links
from multiple sources to multiple destinations. This device
supports four single byte channels.
When the encoder is enabled, the TXCTx[1:0] bits are inter-
preted along with the associated TXDx[7:0] character to
generate a specific 10-bit transmission character.
Phase Align Buffer
Data from each input register is passed to the associated phase
align buffer, when the TXDx[7:0] and TXCTx[1:0] input registers
are clocked using TXCLKx¦ (TXCKSELx = 0 and TXRATEx = 0).
When the TXDx[7:0] and TXCTx[1:0] input registers are clocked
using REFCLKx± (TXCKSELx = 1) and REFCLKx± is a full rate
clock, the associated phase alignment buffer in the transmit path
is bypassed. These buffers are used to absorb clock phase
differences between the TXCLKx input clock and the internal
character clock for that channel.
CYV15G0404DXB Transmit Data Path
Input Register
The bits in the Input Register for each channel support different
assignments, based on if the input data is encoded or
When the ENCODER is enabled, each input register captures
eight data bits and two control bits on each input clock cycle.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Once initialized, TXCLKx is allowed to drift in phase as much as
±180 degrees. If the input phase of TXCLKx drifts beyond the
handling capacity of the phase align buffer, TXERRx is asserted
to indicate the loss of data, and remains asserted until the phase
align buffer is initialized. The phase of the TXCLKx relative to its
associated internal character rate clock is initialized when the
configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the phase align buffer is
initialized and input characters are correctly captured.
Depending on the operational mode, the generated transmission
character may be
■ The 10-bit preencoded character accepted in the input register.
■ The 10-bit equivalent of the 8-bit Data character accepted in
the input register
■ The 10-bit equivalent of the 8-bit Special Character code
accepted in the input register
Table 1. Input Register Bit Assignments
■ The 10-bit equivalent of the C0.7 violation character if a phase
align buffer overflow or underflow error is present
Signal Name
TXDx[0] (LSB)
TXDx[1]
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
Encoded
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
■ A character that is part of the 511-character BIST sequence
■ A K28.5 character generated as an individual character or as
part of the 16-character Word Sync Sequence
TXDx[2]
Data Encoding
TXDx[3]
Raw data, as received directly from the transmit input register, is
seldom in a form suitable for transmission across a serial link.
The characters must usually be processed or transformed to
guarantee
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
■ aminimumtransitiondensity(toallowthereceivePLLtoextract
a clock from the serial data stream)
TXCTx[0]
TXCTx[1] (MSB)
■ A DC-balance in the signaling (to prevent baseline wander)
Note
7. LSB shifted out first.
■ Run length limits in the serial data (to limit the bandwidth
requirements of the serial link)
■ the remote receiver a way of determining the correct character
boundaries (framing)
If the phase offset between the initialized location of the input
clock and REFCLKx exceeds the skew handling capabilities of
the phase align buffer, an error is reported on that channel’s
TXERRx output. This output indicates an error continuously until
the phase align buffer for that channel is reset. While the error
remains active, the transmitter for that channel outputs a
continuous C0.7 character to indicate to the remote receiver that
an error condition is present in the link.
When the encoder is enabled (ENCBYPx = 1), the characters
transmitted are converted from data or special character codes
to 10-bit transmission characters, using an integrated 8B/10B
encoder. When directed to encode the character as a special
character code, the encoder uses the special character encoding
as a data character, it is encoded using the data character
Each phase align buffer may be individually reset with minimal
disruption of the serial data stream. When a phase align buffer
error is present, the transmission of a word sync sequence
recenters the phase align buffer and clears the error indication.
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit Ethernet,
®
®
the IBM ESCON and FICON™ channels, ETSI DVB-ASI, and
ATM Forum standards for data transport.
Note. K28.5 characters may be added or removed from the data
stream during the phase align buffer reset operation. When used
with non-Cypress devices that require a complete 16-character
word sync sequence for proper receive elasticity buffer
operation, follow the phase alignment buffer reset by a word sync
sequence to ensure proper operation.
generated by more than one input character. The
CYV15G0404DXB is designed to support two independent (but
non-overlapping) special character code tables. This allows the
CYV15G0404DXB to operate in mixed environments with other
Cypress HOTLink devices using the enhanced Cypress
command code set, and the reduced command sets of other
non-Cypress devices. Even when used in an environment that
normally uses non-Cypress Special Character codes, the
selective use of Cypress command codes can permit operation
where running disparity and error handling must be managed.
Encoder
Each character received from the Input register or phase align
buffer is passed to the encoder logic. This block interprets each
character and any associated control bits, and outputs a 10-bit
transmission character.
Following conversion of each input character from eight bits to a
10-bit transmission character, it is passed to the transmit shifter
and is shifted out LSB first, as required by ANSI and IEEE
standards for 8B/10B coded serial data streams.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
sequence. At the end of this sequence, if the TXCTx[1:0] = 11
condition is sampled again, the sequence restarts and remains
uninterruptible for the following 15 character clocks.
Transmit Modes
Encoder Bypass
When the Encoder is bypassed, the character captured from the
TXDx[7:0] and TXCTx[1:0] input register is passed directly to the
transmit shifter without modification. With the encoder bypassed,
the TXCTx[1:0] inputs are considered part of the data character
and do not perform a control function that would otherwise
modify the interpretation of the TXDx[7:0] bits. The bit usage and
mapping of these control bits when the Encoder is bypassed is
Transmit BIST
Each transmit channel contains an internal pattern generator that
can be used to validate both the link and device operation. These
generators are enabled by the associated TXBISTx latch
through the device configuration interface. When enabled, a
register in the associated transmit channel becomes a signature
pattern generator by logically converting to a Linear Feedback
Shift Register (LFSR). This LFSR generates a 511-character (or
526-character) sequence that includes all data and special
character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can be
matched to an identical LFSR in the attached Receiver(s).
Table 2. Encoder Bypass Mode
Signal Name
TXDx[0] (LSB)
TXDx[1]
Bus Weight
10B Name
0
[7]
2
a
1
2
b
c
d
e
i
2
TXDx[2]
2
A device reset (RESET sampled LOW) presets the BIST enable
latches to disable BIST on all channels.
3
TXDx[3]
2
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured for
reference clock operation, each pass is preceded by a
16-character word sync sequence to allow elasticity buffer
alignment and management of clock frequency variations.
4
TXDx[4]
2
5
TXDx[5]
2
6
TXDx[6]
2
f
7
TXDx[7]
2
g
h
j
8
TXCTx[0]
TXCTx[1] (MSB)
2
Transmit PLL Clock Multiplier
9
2
Each Transmit PLL Clock Multiplier accepts a character rate or
half character-rate external clock at the associated REFCLKx±
input, and that clock is multiplied by 10 or 20 (as selected by
TXRATEx) to generate a bit rate clock for use by the transmit
shifter. It also provides a character rate clock used by the
transmit paths, and outputs this character rate clock as
TXCLKOx.
When the encoder is enabled, the TXCTx[1:0] data control bits
control the interpretation of the TXDx[7:0] bits and the characters
generated by them. These bits are interpreted as listed in
Table 3. Transmit Modes
Each clock multiplier PLL is able to accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0404DXB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
TXCTx[1] TXCTx[0]
Characters Generated
Encoded data character
K28.5 fill character
0
0
1
1
0
1
0
1
Special character code
[4]
SPDSELx are 3-level select inputs that select one of three
16-character Word Sync Sequence
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling rate and
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a word sync sequence, is generated on the
associated channel. This sequence of K28.5 characters may
start with either a positive or negative disparity K28.5 (as deter-
mined by the current running disparity and the 8B/10B coding
rules). The disparity of the second and third K28.5 characters in
this sequence are reversed from what normal 8B/10B coding
rules would generate. The remaining K28.5 characters in the
sequence follow all 8B/10B coding rules. The disparity of the
generated K28.5 characters in this sequence follow a pattern of
either ++––+–+–+–+–+–+– or ––++–+–+–+–+–+–+.
Table 4. Operating Speed Settings
REFCLKx±
Signaling
SPDSELx
TXRATE
Frequency
(MHz)
Rate (MBaud)
LOW
1
0
1
0
1
0
reserved
19.5 – 40
20 – 40
195 – 400
MID (Open)
HIGH
400 – 800
40 – 80
40 – 75
800 – 1500
The generation of this sequence, once started, cannot be
stopped until all 16 characters have been sent. The content of
the associated input registers are ignored for the duration of this
80 – 150
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CYV15G0404DXB
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected to
a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL, or
LVCMOS clock source, connect the clock source to either the
true or complement REFCLKx input, and leave the alternate
REFCLKx input open (floating).
The local internal loopback (LPENx) allows the serial transmit
data outputs to be routed internally back to the clock and data
recovery circuit associated with each channel. When configured
for local loopback, the associated transmit serial driver outputs
are forced to output a differential logic-1. This prevents local
diagnostic patterns from being broadcast to attached remote
receivers.
Signal Detect/Link Fault
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This can
either be a differential LVPECL clock that is DC- or AC-coupled
or a differential LVTTL or LVCMOS clock.
Each selected line receiver (that is routed to the clock and data
recovery PLL) is simultaneously monitored for:
■ Analog amplitude above amplitude level selected by SDASELx
■ Transition density above the specified limit
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so,
ensure that the input differential crossing point remains within the
parametric range supported by the input.
■ Range controls report the received data stream inside normal
frequency range (±1500 ppm)
■ Receive channel enabled
■ The presence of a reference clock
■ ULCx is not asserted.
Serial Output Drivers
The serial output interface drivers use differential Current Mode
Logic (CML) drivers to provide source matched drivers for trans-
mission lines. These drivers accept data from the transmit
shifters. They have signal swings equivalent to that of standard
PECL drivers, and are capable of driving AC-coupled optical
modules or transmission lines. When configured for local
loopback (LPENx = HIGH), all enabled serial drivers are
configured to drive a static differential logic 1.
All of these conditions must be valid for the signal detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the selected
receive interface clock.
Analog Amplitude
Transmit Channels Enabled
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow operation
with highly attenuated signals, or in high noise environments.
The analog amplitude level detection is set by the SDASELx
latch via device configuration interface. The SDASELx latch sets
the trip point for the detection of a valid signal at one of three
monitors for all receive channels.
Each driver can be enabled or disabled separately using the
device configuration interface.
When a driver is disabled through the configuration interface, it
is internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Table 5. Analog Amplitude Detect Valid Signal Levels
CYV15G0404DXB Receive Data Path
SDASEL Typical Signal with Peak Amplitudes Above
00
01
10
11
Analog Signal Detector is disabled
140 mV p-p differential
Serial Line Receivers
Two differential line receivers, INx1± and INx2±, are available on
each channel for accepting serial data streams. The active serial
line receiver on a channel is selected using the associated
INSELx input. The serial line receiver inputs are differential, and
can accommodate wire interconnect and filtering losses or trans-
mission line attenuation greater than 16 dB. For normal
280 mV p-p differential
420 mV p-p differential
The analog signal detect monitors are active for the line receiver
as selected by the associated INSELx input. When configured
for local loopback, no input receivers are selected, and the LFIx
output for each channel reports only the receive VCO frequency
out-of-range and transition density status of the associated
transmit signal. When local loopback is active, the associated
analog signal detect monitor is disabled.
operation, these inputs should receive a signal of at least VI
>
DIFF
100 mV, or 200 mV peak-to-peak differential. Each Line Receiver
can be DC- or AC-coupled to +3.3V powered fiber optic interface
modules (any ECL/PECL family, not limited to 100K PECL) or
AC-coupled to +5V powered optical modules. The common
mode tolerance of these line receivers accommodates a wide
range of signal termination voltages. Each receiver provides
internal DC-restoration, to the center of the receiver’s common
mode range, for AC-coupled signals.
Notes
8. When a disabled transmit channel (i.e., both outputs disabled) is re-enabled, the data on the serial outputs may not meet all timing specifications for up to 250 ms.
9. The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals may
have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values
in the table above by approximately 100 mV.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Transition Density
Each CDR accepts
a
character rate (bit-rate ÷ 10) or
half-character rate (bit-rate ÷ 20) reference clock from the
The transition detection logic checks for the absence of transi-
tions spanning greater than six transmission characters (60 bits).
If no transitions are present in the data received, the detection
logic for that channel asserts LFIx.
associated REFCLKx± input. This REFCLKx± input is used to
■ EnsurethattheVCO(withintheCDR)isoperatingatthecorrect
frequency (rather than a harmonic of the bit-rate)
Range Controls
■ Reduce PLL acquisition time
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO operates
at, or near the rate of the incoming data stream for two primary
cases:
■ Limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected serial line receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks REFCLKx± instead of the data
stream. Once the CDR output (RXCLK±) frequency returns close
to REFCLKx± frequency, the CDR input is switched back to the
input data stream. If no data is present at the selected line
receiver, this switching behavior may result in brief RXCLK±
frequency excursions from REFCLKx±. However, the validity of
the input data stream is indicated by the LFIx output. The
frequency of REFCLKx± is required to be within ±1500 ppm of
the frequency of the clock that drives the REFCLKx± input of the
remote transmitter to ensure a lock to the incoming data stream.
■ When the incoming data stream resumes after a time in which
it has been “missing.”
■ When the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the REFCLKx± input.
If the VCO is running at a frequency beyond ±1500 ppm, as
defined by the REFCLKx± frequency, it is periodically forced to
the correct frequency (as defined by REFCLKx±, SPDSELx, and
TXRATEx) and then released in an attempt to lock to the input
data stream.
For systems using multiple or redundant connections, the LFIx
can be output to select an alternate data stream. When an LFIx
indication is detected, external logic can toggle selection of the
associated INx1± and INx2± input through the associated
INSELx input. When a port switch takes place, it is necessary for
the receive PLL for that channel to reacquire the new serial
stream and frame to the incoming character boundaries.
The sampling and relock period of the range control is calculated
in
the
following
manner:
RANGE_CONTROL_
SAMPLING_PERIOD = (RECOVERED BYTE CLOCK PERIOD)
* (4096).
During the time that the range control forces the RXPLL VCO to
track REFCLKx±, the LFIx output is asserted LOW. After a valid
serial data stream is applied, it may take up to one RANGE
CONTROL SAMPLING PERIOD before the PLL locks to the
input data stream, after which LFIx should be HIGH.
Reclocker
The CYV15G0404DXB contains a reclocker mode on each
receive channel that can be independently enabled and
disabled. When the reclocker mode is enabled by RCLKENx, the
received serial data is reclocked and transmitted through the
enabled differential serial outputs of the selected channel. In the
reclocker mode, the RXPLL performs clock and data recovery
functions on the input serial data stream and the reclocked serial
data is routed to the enabled differential serial outputs. The serial
data is also routed to the deserializer and the deserialized data
is presented to the RXDx[7:0] and RXSTA[2:0] parallel data
outputs as configured by DECBYPx. When the reclocker is
enabled, the data on the TXDx[7:0] and TXCT[1:0] is ignored and
not transmitted through the enabled serial outputs.
Receive Channel Enabled
The CYV15G0404DXB contains four receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface. When
the RXPLLPDx latch = 0, the associated PLL and analog circuitry
of the channel is disabled. Any disabled channel indicates a
constant link fault condition on the LFIx output. When
RXPLLPDx = 1, the associated PLL and receive channel is
enabled to receive and decode a serial stream.
Deserializer/Framer
Note. When a disabled receive channel is reenabled, the status
of the associated LFIx output and data on the parallel outputs for
the associated channel may be indeterminate for up to 2 ms.
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the shifter/framer at the bit clock
rate. When enabled, the framer examines the data stream
looking for one or more COMMA or K28.5 characters at all
possible bit positions. The location of this character in the data
stream determines the character boundaries of all following
characters.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of the
transitions in the incoming bit stream and align the phase of the
internal bit rate clock to the transitions in the selected serial data
stream.
Framing Character
The CYV15G0404DXB allows selection of different framing
characters on each channel. Two combinations of framing
characters are supported to meet the requirements of different
interfaces. The selection of the framing character is made
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CYV15G0404DXB
through the FRAMCHARx latches through the configuration
interface.
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted.
The specific bit combinations of these framing characters are
selected framing character is detected by the framer, the bound-
aries of the characters present in the received data stream are
known.
10B/8B Decoder Block
The decoder logic block performs two primary functions:
■ Decoding the received transmission characters to data and
special character codes
Table 6. Framing Character Selector
■ Comparing generated BIST patterns with received characters
Bits Detected in Framer
FRAMCHARx
to permit at-speed link and device testing
Character Name
Bits Detected
The framed parallel output of each deserializer shifter is passed
to its associated 10B/8B Decoder where, if the decoder is
enabled, the input data is transformed from a 10-bit transmission
character back to the original data or special character code.
combination on the associated RXSTx[2:0] status bits, and
special character codes are indicated by a 001b bit combination
of these status outputs. Framing characters, invalid patterns,
disparity errors, and synchronization status are presented as
alternate combinations of these status bits.
0
1
COMMA+
COMMA–
00111110XX
or 11000001XX
–K28.5
+K28.5
0011111010 or
1100000101
Framer
The framer on each channel operates in one of three different
modes. Each framer is enabled or disabled using the RFENx
latches using the configuration interface. When the framer is
disabled (RFENx = 0), no combination of received bits alters the
frame information.
When DECBYPx = 0, the 10B/8B decoder is bypassed through
the configuration interface. When bypassed, raw 10-bit
characters are passed through the receiver and presented at the
RXDx[7:0] and the RXSTA[1:0] outputs as 10-bit wide
characters.
When the low latency framer is selected (RFMODEx[1:0] = 00),
the framer operates by stretching the recovered character clock
until it aligns with the received character boundaries. In this
mode the framer starts its alignment process on the first
detection of the selected framing character. To reduce the impact
on external circuits that use the recovered clock, the clock period
is not stretched by more than two bit periods in any one clock
cycle. When operated with a character rate output clock, the
output of properly framed characters may be delayed by up to
nine character clock cycles from the detection of the selected
framing character. When operated with a half character rate
output clock, the output of properly framed characters may be
delayed by up to 14 character clock cycles from the detection of
the framing character.
When the decoder is enabled by setting DECBYPx = 1 through
the configuration interface, the 10-bit transmission characters
device configuration interface. When DECMODEx = 0 the
ALTERNATE table is used and when DECMODEx = 1 the
CYPRESS table is used.
Receive BIST Operation
The receiver channel contains an internal pattern checker that
can be used to validate both device and link operation. These
pattern checkers are enabled by the associated RXBISTx latch
using the device configuration interface. When enabled, a
register in the associated receive channel becomes a signature
pattern generator and checker by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a
511-character or 526-character sequence that includes all data
and special character codes, including the explicit violation
symbols. This provides a predictable yet pseudo random
sequence that can be matched to an identical LFSR in the
attached transmitters. When synchronized with the received
data stream, the associated Receiver checks each character in
the Decoder with each character generated by the LFSR and
indicates compare errors and BIST status at the RXSTx[2:0] bits
of the Output Register.
When RFMODEx[1:0] = 10, the Cypress-Mode Multi-Byte framer
is selected. The required detection of multiple framing characters
makes the associated link much more robust to incorrect framing
due to aliased SYNC characters in the data stream. In this mode,
the framer does not adjust the character clock boundary, but
instead aligns the character to the already recovered character
clock. This ensures that the recovered clock does not contain
any significant phase changes or hops during normal operation
or framing, and allows the recovered clock to be replicated and
distributed to other external circuits or components using
PLL-based clock distribution elements. In this framing mode the
character boundaries are only adjusted if the selected framing
character is detected at least twice within a span of 50 bits, with
both instances on identical 10-bit character boundaries.
When RFMODEx[1:0] = 01, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the data stream
must contain a minimum of four of the selected framing
When BIST is first recognized as being enabled in the Receiver,
the LFSR is preset to the BIST-loop start code of D0.0. This code
D0.0 is sent only once per BIST loop. The status of the BIST
progress and any character mismatches are presented on the
RXSTx[2:0] status outputs.
Note
10. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Code rule violations or running disparity errors that occur as part
of the BIST loop do not cause an error indication. RXSTx[2:0]
indicates 010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress. These same status values are presented when
the decoder is bypassed and BIST is enabled on a receive
channel.
RXRATEx) and delayed form of REFCLKx±. In this mode, the
receive elasticity buffers are enabled. For REFCLKx± clocking,
the elasticity buffers must be able to insert K28.5 characters and
delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel. However, the actual timing of
these insertions and deletions is controlled in part by how the
transmitter sends its data. Insertion of a K28.5 character can only
occur when the receiver has a framing character in the elasticity
buffer. Likewise, to delete a framing character, one must also be
in the elasticity buffer. To prevent a buffer overflow or underflow
on a receive channel, a minimum density of framing characters
must be present in the received data streams.
The specific status reported by the BIST state machine are listed
status outputs.
The specific patterns checked by each receiver are described in
detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the CYV15G0404DXB is
identical to that in the CY7B933, CY7C924DX, and
CYP(V)15G0401DXB, allowing interoperable systems to be built
when used at compatible serial signaling rates.
When the receive channel output register is clocked by a
recovered clock, no characters are added or deleted and the
receiver elasticity buffer is bypassed.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
Power Control
The CYV15G0404DXB supports user control of the powered up
or down state of each transmit and receive channel. The receive
channels are controlled by the RXPLLPDx latch through the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the OE1x and the OE2x
latches through the device configuration interface. When a driver
is disabled through the configuration interface, it is internally
powered down to reduce device power. If both serial drivers for
a channel are in this disabled state, the associated internal logic
for that channel is powered down as well.
When Receive BIST is enabled on a channel, do not enable the
low latency framer. The BIST sequence contains an aliased
K28.5 framing character, which causes the receiver to update its
character boundaries incorrectly.
The receive BIST state machine requires the characters to be
correctly framed for it to detect the BIST sequence. If the low
latency framer is enabled, the framer misaligns to an aliased
SYNC character within the BIST sequence. If the alternate
multi-byte framer is enabled and the receiver outputs are clocked
relative to a recovered clock, it is generally necessary to frame
the receiver before BIST is enabled. If the receive outputs are
clocked relative to REFCLKx±, the transmitter precedes every
Device Reset State
When the CYV15G0404DXB is reset by assertion of RESET, all
state machines, counters, and configuration latches in the device
are initialized to a reset state, and the elasticity buffer pointers
are set to a nominal offset. Additionally, the JTAG controller must
also be reset to ensure valid operation (even if JTAG testing is
configuration latches.
sequence.
A device reset (RESET sampled LOW) presets the BIST enable
latches to disable BIST on all channels.
Receive Elasticity Buffer
Each receive channel contains an elasticity buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using a clock that is asynchronous in both
frequency and phase from the elasticity buffer write clock, or to
be read using a clock that is frequency coherent but with uncon-
trolled phase relative to the elasticity buffer write clock.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This is done by
interface.
Output Bus
If the chip is configured for operation with a recovered clock, the
elasticity buffer is bypassed.
Each receive channel presents an 11-signal output bus
consisting of
Each elasticity buffer is 10 characters deep, and supports and an
11 bit wide data path. It is capable of supporting a decoded
character and three status bits for each character present in the
buffer. The write clock for these buffers is always the recovered
clock for the associated read channel.
■ An 8-bit data bus
■ A 3-bit status bus.
The signals present on this output bus are modified by the
present operating mode of the CYV15G0404DXB as selected by
the DECBYPx configuration latch. This mapping is shown in
Receive Modes
When the receive channel is clocked by REFCLKx±, the
RXCLKx± outputs present a buffered or divided (depending on
Note
11. When the receive paths are configured for REFCLKx± operation, each pass must be preceded by a 16-character Word Sync Sequence to allow management
of clock frequency variations.
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CYV15G0404DXB
This adjustment only occurs when the framer is enabled. When
the framer is disabled, the clock boundaries are not adjusted,
and COMDETx may be asserted during the rising edge of
RXCLKx– (if an odd number of characters were received
following the initial framing).
Table 7. Output Register Bit Assignments
BYPASS ACTIVE
Signal Name
DECODER
(DECBYPx = 0)
COMDETx
DOUTx[0]
DOUTx[1]
DOUTx[2]
DOUTx[3]
DOUTx[4]
DOUTx[5]
DOUTx[6]
DOUTx[7]
DOUTx[8]
DOUTx[9]
(DECBYP = 1)
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXSTx[2] (LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
Receive Status Bits
When the 10B/8B decoder is enabled, each character presented
at the output register includes three associated status bits.
These bits are used to identify
RXDx[1]
RXDx[1]
■ If the contents of the data bus are valid
■ The type of character present
■ The state of receive BIST operations
■ Character violations
RXDx[2]
RXDx[2]
RXDx[3]
RXDx[3]
RXDx[4]
RXDx[4]
RXDx[5]
RXDx[5]
RXDx[6]
RXDx[6]
These conditions often overlap; for example, a valid data
character received with incorrect running disparity is not reported
as a valid data character. It is instead reported as a decoder
violation of some specific type. This implies a hierarchy or priority
level to the various status bit combinations. The hierarchy and
RXDx[7] (MSB)
RXDx[7]
When the 10B/8B decoder is bypassed, the framed 10-bit value
is presented to the associated output register, along with a status
output signal indicating if the character in the output register is
one of the selected framing characters. The bit usage and
mapping of the external signals to the raw 10B transmission
receive channel is configured for BIST operation. This status is
used to report receive BIST status and progress.
Table 8. Decoder Bypass Mode
BIST Status State Machine
Signal Name
RXSTx[2] (LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
Bus Weight
10 Bit Name
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0] bits
identify the present state of the BIST compare operation.
COMDETx
0
2
a
b
c
d
e
i
The BIST state machine has multiple states, as shown in
out-of-lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state machine.
If the number of detected errors ever exceeds the number of
valid matches by greater than 16, the state machine is forced to
the WAIT_FOR_BIST state where it monitors the receive path for
the first character of the next BIST sequence (D0.0). Also, if the
Elasticity Buffer ever hits an overflow/underflow condition, the
status is forced to the BIST_START until the buffer is re-centered
(approximately nine character periods).
1
2
2
2
3
RXDx[1]
2
4
RXDx[2]
2
5
RXDx[3]
2
6
RXDx[4]
2
f
7
RXDx[5]
2
g
h
j
8
RXDx[6]
2
To ensure compatibility between the source and destination
systems when operating in BIST modes, the sending and
receiving ends of the link must use the same receive clock
configuration.
9
RXDx[7] (MSB)
2
The COMDETx status output operates the same regardless of
the bit combination selected for character framing by the
FRAMCHARx latch. COMDETx is HIGH when the character in
the output register contains the selected framing character at the
proper character boundary, and LOW for all other bit combina-
tions.
Device Configuration and Control Interface
The CYP(V)15G0404DX is highly configurable through the
configuration interface. The configuration interface allows the
device to be configured globally or allows each channel to be
within the device including the initialization value of the latches
8-bit latch bank. There are 16 such write-only latch banks. When
WREN = 0, the logic value in the DATA[7:0] is latched to the latch
bank specified by the values in ADDR[3:0]. The second column
sponding latch bank. For example, the first three latch banks (0,1
and 2) consist of configuration bits for channel A. The latch banks
When the low-latency framer and half rate receive port clocking
are also enabled, the framer stretches the recovered clock to the
nearest 20-bit boundary such that the rising edge of RXCLKx+
occurs when COMDETx is present on the associated output bus.
When the Cypress or alternate mode framer is enabled and half
rate receive port clocking is also enabled, the output clock is not
modified when framing is detected, but a single pipeline stage
may be added or subtracted from the data stream by the framer
logic such that the rising edge of RXCLKx+ occurs when
COMDETx is present on the associated output bus.
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CYV15G0404DXB
12, 13, and 14 consist of global configuration bits and the last
latch bank (15) is the mask latch bank that can be configured to
perform bit-by-bit configuration.
basis. A logic 1 in a bit location allows for the update of that same
location of the target latch bank(s), whereas a logic 0 disables it.
The reset value of this latch bank is FFh, thereby making its use
optional by default. The mask latch bank is not maskable. The
FGLEN functionality is not affected by the bit 0 value of the mask
latch bank.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that is used to reduce the number of write operations
needed to setup the latch banks. This function is beneficial in
systems that use a common configuration in multiple channels.
The GLENx bit is present in bit 0 of latch banks 0 through 11 only.
Its default value (1) enables the global update of the latch bank's
contents. Setting the GLENx bit to 0 disables this functionality.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by two static and one dynamic latch
bank. The S type contain those settings that normally do not
change for a given application, while the D type controls the
settings that could change dynamically during the application's
lifetime.The first row of latches for each channel (address
numbers 0, 3, 7, and 10) are the static receiver control latches.
The second row of latches for each channel (address numbers
1, 4, 8, and 11) are the static transmitter control latches. The third
row of latches for each channel (address numbers 2, 5, 9, and
12) are the dynamic control latches that are associated with
enabling dynamic functions within the device.
Latch Banks 12, 13, and 14 load values in the related latch banks
in a global manner. A write operation to latch bank 12 could do
a global write to latch banks 0, 3, 6, and 9 depending on the value
of GLENx in these latch banks; latch bank 13 could do a global
write to latch banks 1, 4, 7, and 10; and latch banks 14 could do
a global write to latch banks 2, 5, 8, and 11. The GLENx bit
cannot be modified by a global write operation.
Force Global Enable Function
Latch Bank 14 is also useful for those users that do not need the
latch-based programmable feature of the device. This latch bank
could be used in those applications that do not need to modify
the default value of the static latch banks, and that can afford a
global (that is, not independent) control of the dynamic signals.
In this case, this feature becomes available when ADDR[3:0] is
left unchanged with a value of “1110” and WREN is left asserted.
The signals present in DATA[7:0] effectively become global
control pins, and for the latch banks 2, 5, 8, and 11.
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx = 1
for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector to
control the update of the configuration latch banks on a bit-by-bit
Table 9. Device Configuration and Control Latch Descriptions
Name
Signal Description
RFMODEA[1:0] Reframe Mode Select. The initialization value of the RFMODEx [1:0] latches = 10. RFMODEx is used to select
RFMODEB[1:0] the operating mode of the framer. When RFMODEx[1:0] = 00, the low-latency framer is selected. This frames
RFMODEC[1:0] on each occurrence of the selected framing character(s) in the received data stream. This mode of framing
RFMODED[1:0] stretches the recovered clock for one or multiple cycles to align that clock with the recovered data. When
RFMODEx[1:0] = 01, the alternate mode Multi-Byte parallel framer is selected. This requires detection of the
selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four directly
adjacent characters. The recovered character clock remains in the same phasing regardless of character
offset. When RFMODEx[1:0] =10, the Cypress-mode Multi-Byte parallel framer is selected. This requires a
pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits, before the
character boundaries are adjusted. The recovered character clock remains in the same phasing regardless of
character offset. RFMODEx[1:0] = 11 is reserved for test.
FRAMCHARA
FRAMCHARB
Framing Character Select. The initialization value of the FRAMCHARx latch = 1. FRAMCHARx is used to
select the character or portion of a character used for framing of each channel’s received data stream. When
FRAMCHARC FRAMCHARx = 1, the framer looks for either disparity of the K28.5 character. When FRAMCHARx = 0, the
FRAMCHARD framer looks for either disparity of the 8-bit Comma characters. The specific bit combinations of these framing
DECMODEA
DECMODEB
DECMODEC
DECMODED
Receiver Decoder Mode Select. The initialization value of the DECMODEx latch = 1. DECMODEx selects
the Decoder Mode used for the associated channel. When DECMODEx = 1 and decoder is enabled, the
Cypress Decoding Mode is used. When DECMODEx = 0 and decoder is enabled, the Alternate Decoding
mode is used. When the decoder is enabled (DECBYPx = 1), the 10-bit transmission characters are decoded
using Table 14 and Table 15. The column used in the Special Characters Table 15 is determined by the
DECMODEx latch.
DECBYPA
DECBYPB
DECBYPC
DECBYPD
Receiver Decoder Bypass. The initialization value of the DECBYPx latch = 1. DECBYPx selects if the
Receiver Decoder is enabled or bypassed. When DECBYPx = 1, the decoder is enabled and the Decoder
Mode is selected by DECMODEx. When DECBYPx = 0, the decoder is bypassed and raw 10-bit characters
are passed through the receiver.
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CYV15G0404DXB
Table 9. Device Configuration and Control Latch Descriptions (continued)
Name
Signal Description
RXCKSELA
RXCKSELB
RXCKSELC
RXCKSELD
Receive Clock Select. The initialization value of the RXCKSELx latch = 1. RXCKSELx selects the receive
clock source used to transfer data to the Output Registers and the clock source for the RXCLK± output. When
RXCKSELx = 1, the associated Output Registers, are clocked by REFCLKx± at the associated RXCLKx±
output buffer. When RXCKSELx = 0, the associated Output Registers, are clocked by the Recovered Byte
clock at the associated RXCLKx± output buffer. These output clocks may operate at the character-rate or half
the character-rate as selected by RXRATEx.
RXRATEA
RXRATEB
RXRATEC
RXRATED
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select the
rate of the RXCLKx± clock output.
When RXRATEx = 1 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at half the character rate. Data for the associated receive channels should be
latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at the character rate. Data for the associated receive channels should be latched
on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at half the character rate. Data for the
associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 with RXCKSELx = 1 and REFCLKx± is a full rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at the character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXCKSELx = 1 and REFCLKx± is a half rate clock, the value of RXRATEx is not interpreted and the
RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half the
character rate. Data for the associated receive channels should be latched alternately on the rising edge of
RXCLKx+ and RXCLKx–.
SDASEL1A[1:0] Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0]
SDASEL1B[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1± Primary
SDASEL1C[1:0] Differential Serial Data Inputs.
SDASEL1D[1:0] When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
SDASEL2A[1:0] Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2B[1:0] SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2±
SDASEL2C[1:0] Secondary Differential Serial Data Inputs.
SDASEL2D[1:0] When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
ENCBYPA
ENCBYPB
ENCBYPC
ENCBYPD
Transmit Encoder Bypassed. The initialization value of the ENCBYPx latch = 1. ENCBYPx selects if the
Transmit Encoder is enabled or bypassed. When ENCBYPx = 1, the Transmit encoder is enabled. When
ENCBYPx = 0, the Transmit Encoder is bypassed and raw 10-bit characters are transmitted.
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register,
TXDx[7:0] and TXCTx[1:0], is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit
path is bypassed. When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input registers,
TXDx[7:0] and TXCTx[1:0].
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Table 9. Device Configuration and Control Latch Descriptions (continued)
Name
Signal Description
TXRATEA
TXRATEB
TXRATEC
TXRATED
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select
the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated
REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx output clocks
are full rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input. When
TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the serial
bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the REFCLKx±
input. When TXCKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both the rising
and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx is LOW, is an invalid state and this combination
is reserved.
RFENA
RFENB
RFENC
RFEND
Reframe Enable. The initialization value of the RFENx latch = 1. RFENx selects if the receiver framer is
enabled or disabled. When RFENx = 1, the associated channel’s framer is enabled to frame per the presently
enabled framing mode and selected framing character. When RFENx = 0, the associated channel’s framer is
disabled, and no received bits alters the frame offset.
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated PLL and
analog circuitry is powered-down. When RXPLLPDx = 1, the associated PLL and analog circuitry is enabled.
RXBISTA
RXBISTB
RXBISTC
RXBISTD
Receive Bist Disabled. The initialization value of the RXBISTx latch = 1. RXBISTx selects if receive BIST is
disabled or enabled. When RXBISTx = 1, the receiver BIST function is disabled. When RXBISTx = 0, the
receive BIST function is enabled.
TXBISTA
TXBISTB
TXBISTC
TXBISTD
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit BIST
is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0, the
transmit BIST function is enabled.
OE2A
OE2B
OE2C
OE2D
Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch = 0.
OE2x selects if the OUT2± secondary differential output drivers are enabled or disabled. When OE2x = 1, the
associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When
OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration
interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this
disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET
sampled LOW) disables all output drivers.
OE1A
OE1B
OE1C
OE1D
Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0. OE1x
selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1, the associated
serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0,
the associated serial data output driver is disabled. When a driver is disabled via the configuration interface,
it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled
state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled
LOW) disables all output drivers.
PABRSTA
PABRSTB
PABRSTC
PABRSTD
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized. PABRST
is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal clock domain.
PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization of
the Phase Alignment Buffer.
GLEN[11..0]
FGLEN[2..0]
Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx
= 0 for a given address, that address is disabled from participating in a global configuration.
Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal
ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel,
FGLEN forces the global update of the target latch banks.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Device Configuration Strategy
4. Set the dynamic bank of latches for the target channel. Enable
the Receive PLLs and transmit channels. May be performed
using a global operation, if the application permits it.
[Required step.]
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power up. This operation
resets all four channels. Initialize the JTAG state machine to
5. Reset the Phase Alignment Buffer for the target channel. May
be performed using a global operation, if the application
permits it. [Optional if phase align buffer is bypassed.]
2. Set the static receiver latch bank for the target channel. May
be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
When a receive channel is configured with the decoder
bypassed and the receive clock selected as recovered clock in
half rate mode (DECBYPx = 0, RXRATEx = 0, RXCKSELx = 0),
the channel cannot be dynamically reconfigured to enable the
decoder with RXCLKx selected as the REFCLKx (DECBYPx =
1, RXCKSELx = 1). If such a change is desired, a global reset
should be performed and all channels should be reconfigured to
the desired settings.
3. Set the static transmitter latch bank for the target channel.
May be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
Table 10. Device Control Latch Configuration Table
Reset
ADDR Channel Type
DATA7
RFMODEA[1] RFMODEA[0] FRAMCHARA
SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0] ENCBYPA TXCKSELA TXRATEA
RFENA RXPLLPDA RXBISTA TXBISTA OE2A OE1A PABRSTA
RFMODEB[1] RFMODEB[0] FRAMCHARB DECMODEB DECBYPB RXCKSELB RXRATEB
SDASEL2B[1] SDASEL2B[0] SDASEL1B[1] SDASEL1B[0] ENCBYPB TXCKSELB TXRATEB
RFENB RXPLLPDB RXBISTB TXBISTB OE2B OE1B PABRSTB
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Value
0
A
S
S
D
S
S
D
S
S
D
S
S
D
S
S
D
D
DECMODEA DECBYPA RXCKSELA RXRATEA
GLEN0
10111111
(0000b)
1
A
GLEN1
GLEN2
GLEN3
GLEN4
GLEN5
GLEN6
GLEN7
GLEN8
10101101
10110011
10111111
10101101
10110011
10111111
10101101
10110011
10111111
10101101
10110011
N/A
(0001b)
2
A
(0010b)
3
B
(0011b)
4
B
(0100b)
5
B
(0101b)
6
C
RFMODEC[1] RFMODEC[0] FRAMCHARC DECMODEC DECBYPC RXCKSELC RXRATEC
SDASEL2C[1] SDASEL2C[0] SDASEL1C[1] SDASEL1C[0] ENCBYPC TXCKSELC TXRATEC
(0110b)
7
C
(0111b)
8
C
D
RFENC
RXPLLPDC
RXBISTC
TXBISTC
OE2C
OE1C
PABRSTC
(1000b)
9
RFMODED[1] RFMODED[0] FRAMCHARD DECMODED DECBYPD RXCKSELD RXRATE D GLEN9
SDASEL2D[1] SDASEL2D[0] SDASEL1D[1] SDASEL1D[0] ENCBYPD TXCKSELD TXRATED GLEN10
(1001b)
10
(1010b)
D
11
(1011b)
D
RFEND
RXPLLPDD
RXBISTD
TXBISTD
OE2D
OE1D
PABRSTD GLEN11
12
GLOBAL
GLOBAL
GLOBAL
MASK
RFMODEGL[1]
RFMODE
GL[0]
FRAMCHARGL DECMODEGL DECBYPGL RXCKSELGL RXRATEG FGLEN0
L
(1100b)
13
(1101b)
SDASEL2GL[1] SDASEL2GL[ SDASEL1GL[1] SDASEL1GL[0 ENCBPGL TXCKSELGL TXRATEG FGLEN1
N/A
0]
]
L
14
(1110b)
RFENGL
D7
RXPLLPDGL
RXBISTGL
D5
TXBISTGL
OE2GL
D3
OE1GL
D2
PABRSTG FGLEN2
L
N/A
15
(1111b)
D6
D4
D1
D0
11111111
JTAG Support
reset (using RESET). The JTAG state machine is initialized using
TRST (asserting it LOW and de-asserting it or leaving it
asserted), or by asserting TMS HIGH for at least five consecutive
TCLK cycles. This is necessary to ensure that the JTAG
controller does not enter any of the test modes after device
power up. In this JTAG reset state, the rest of the device is in
normal operation.
The CYV15G0404DXB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
Note. The order of device reset (using RESET) and JTAG initial-
ization does not matter.
To ensure valid device operation after power up (including
non-JTAG operation), the JTAG state machine must also be
initialized to a reset state. This is done in addition to the device
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan register.
These bits report the LOW, MID, and HIGH state of the
associated input as 00, 10, and 11 respectively.
JTAG ID
The JTAG device ID for the CYV15G0404DXB is ‘0C811069’x
.
Receive Character Status Bits
Description
RXSTx[2:0] Priority
Normal Status
Receive BIST Status
(Receive BIST = Enabled)
000
7
Normal character received. The valid Data
character on the output bus meets all the
formatting requirements of Data characters
BIST Data Compare. Character compared correctly.
001
7
Special code detected. The valid special
character on the output bus meets all the
formatting requirements of Special Code
presently selected framing character or a
decoder violation indication.
BIST Command Compare. Character compared
correctly.
010
011
2
5
Receive Elasticity buffer underrun/overrun BIST Last Good. Last Character of BIST sequence
error. The receive buffer was not able to
detected and valid.
add/drop a K28.5 or framing character
Framing character detected. This indicates
that a character matching the patterns identified
as a framing character (as selected by
FRAMCHARx) was detected. The decoded
value of this character is present in the
associated output bus.
100
101
4
1
Codeword violation. The character on the
output bus is a C0.7. This indicates that the
received character cannot be decoded into any
valid character.
BIST Last Bad. Last Character of BIST sequence
detected invalid.
Loss of sync. This indicates a PLL Out of Lock BIST Start. Receive BIST is enabled on this channel,
condition
but character compares have not yet commenced. This
also indicates a PLL Out of Lock condition, and
Elasticity Buffer overflow/underflow conditions.
110
111
6
3
Running disparity error. The character on the BIST Error. While comparing characters, a mismatch
output bus is a C4.7, C1.7, or C2.7.
was found in one or more of the decoded character bits.
Reserved
BIST Wait. The receiver is comparing characters. but
has not yet found the start of BIST character to enable
the LFSR.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Figure 2. Receive BIST State Machine
Monitor Data
Received
Receive BIST
Detected LOW
RXSTx =
RX PLL
Out of Lock
BIST_START (101)
RXSTx =
BIST_START (101)
RXSTx =
BIST_WAIT (111)
Elasticity
Buffer Error
Yes
Start of
BIST Detected
No
No
Yes, RXSTx =
BIST_DATA_COMPARE (000) / BIST_COMMAND_COMPARE (001)
Compare
Next Character
RXSTx =
Mismatch
BIST_COMMAND_COMPARE (001)
Match
Command
Data or
Command
Auto-Abort
Condition
Yes
RXSTx =
BIST_DATA_COMPARE (000)
No
Data
End-of-BIST
State
End-of-BIST
State
No
Yes, RXSTx =
BIST_LAST_BAD (100)
Yes, RXSTx =
BIST_LAST_GOOD (010)
No, RXSTx =
BIST_ERROR (110)
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CYV15G0404DXB
Static Discharge Voltage..........................................> 2000 V
(according to MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of device.
These user guidelines are not tested.
Latch-up Current.....................................................> 200 mA
Power Up Requirements
Storage Temperature.................................. –65°C to +150°C
The CYP(V)15G0404DXB requires one power supply. The
Voltage on any input or IO pin cannot exceed the power pin
during power up.
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +3.8V
Operating Range
DC Voltage Applied to LVTTL Outputs
in High-Z State....................................... –0.5V to V + 0.5V
CC
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
Output Current into LVTTL Outputs (LOW) ................. 60 mA
+3.3V ±5%
+3.3V ±5%
DC Input Voltage ................................... –0.5V to V + 0.5V
CC
–40°C to +85°C
CYV15G0404DXB DC Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
V
Output HIGH Voltage
Output LOW Voltage
I
I
= − 4 mA, V = Min.
2.4
V
V
OHT
OLT
OH
CC
V
= 4 mA, V = Min.
0.4
–100
20
OL
CC
I
I
Output Short Circuit Current
V
V
= 0V , V = 3.3V
–20
–20
mA
µA
OST
OZL
OUT
OUT
CC
High-Z Output Leakage Current
= 0V, V
CC
LVTTL-compatible Inputs
V
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
2.0
V
+ 0.3
V
IHT
ILT
CC
–0.5
0.8
1.5
V
I
REFCLKx Input, V = V
CC
mA
µA
mA
µA
µA
µA
IHT
IN
Other Inputs, V = V
+40
–1.5
–40
IN
CC
I
Input LOW Current
REFCLKx Input, V = 0.0V
IN
ILT
Other Inputs, V = 0.0V
IN
I
I
Input HIGH Current with internal pull down
Input LOW Current with internal pull up
V
V
= V
CC
+200
–200
IHPDT
IN
IN
= 0.0V
ILPUT
LVDIFF Inputs: REFCLKx±
V
V
V
V
Input Differential Voltage
Highest Input HIGH Voltage
Lowest Input LOW voltage
Common Mode Range
400
1.2
0.0
1.0
V
V
mV
V
DIFF
CC
CC
IHHP
V
/2
V
ILLP
CC
V
– 1.2V
CC
V
COMREF
3-Level Inputs
V
Three-Level Input HIGH Voltage
Min. ≤ V ≤ Max.
0.87 * V
0.47 * V
0.0
V
CC
V
V
IHH
IMM
ILL
CC
CC
V
V
Three-Level Input MID Voltage
Three-Level Input LOW Voltage
Input HIGH Current
Min. ≤ V ≤ Max.
0.53 * V
0.13 * V
200
CC
CC
CC
Min. ≤ V ≤ Max.
V
CC
CC
I
I
I
V
V
V
= V
CC
µA
µA
µA
IHH
IN
IN
IN
Input MID current
= V /2
–50
50
IMM
CC
Input LOW current
= GND
–200
ILL
Notes
12. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
13. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (-) input. A logic-0 exists when the complement (-) input is more positive than true (+) input.
14. The common mode range defines the allowable range of REFCLKx+ and REFCLKx- when REFCLKx+ = REFCLKx-. This marks the zero-crossing between the
true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
CYV15G0404DXB DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
V
V
V
Output HIGH Voltage
100Ω differential load
150Ω differential load
100Ω differential load
150Ω differential load
100Ω differential load
150Ω differential load
V
V
V
V
– 0.5
– 0.5
– 1.4
– 1.4
V
V
V
V
– 0.2
– 0.2
– 0.7
– 0.7
V
V
OHC
OLC
ODIF
CC
CC
CC
CC
CC
CC
CC
CC
(V Referenced)
cc
Output LOW Voltage
V
(V Referenced)
CC
V
Output Differential Voltage
|(OUT+) − (OUT−)|
450
560
900
mV
mV
1000
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±
V
V
V
I
Input Differential Voltage |(IN+) − (IN−)|
Highest Input HIGH Voltage
Lowest Input LOW Voltage
Input HIGH Current
100
1200
mV
V
DIFFs
V
IHE
CC
V
– 2.0
V
ILE
CC
V
V
= V Max.
IHE
1350
+3.1
μA
μA
V
IHE
IN
IN
I
Input LOW Current
= V Min.
–700
ILE
ILE
VI
Common Mode input range
((V – 2.0V) + 0.5)min,
+1.25
COM
CC
(V – 0.5V) max.
CC
Power Supply
Typ.
Max.
1270
1320
1270
1320
I
I
Max Power Supply Current
REFCLKx= Commercial
910
mA
mA
mA
mA
CC
MAX
Industrial
Typical Power Supply Current
REFCLKx= Commercial
900
CC
125 MHz
Industrial
AC Test Loads and Waveforms
3.3V
RL = 100Ω
R
L
R1
R1 = 590Ω
(Includes fixture and
probe capacitance)
R2 = 435Ω
CL
CL ≤ 7 pF
(Includes fixture and
probe capacitance)
R2
(b) CML Output Test Load
(a) LVTTL Output Test Load
VIHE
3.0V
VIHE
2.0V
0.8V
2.0V
0.8V
80%
80%
Vth = 1.4V
Vth = 1.4V
20%
20%
VILE
≤ 270 ps
GND
VILE
≤ 270 ps
≤ 1 ns
≤ 1 ns
(d) CML/LVPECL Input Test Waveform
(c) LVTTL Input Test Waveform
Notes
15. The common mode range defines the allowable range of INPUT+ and INPUT- when INPUT+ = INPUT-. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
16. Maximum ICC is measured with VCC = MAX, RFENx = 0,TA = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01
pattern, and outputs unloaded.
17. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, RFENx = 0, with all channels enabled and one Serial Line Driver per
transmit channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
18. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
19. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
CYV15G0404DXB AC Electrical Characteristics
Parameter
Description
Min.
Max
Unit
CYV15G0404DXB Transmitter LVTTL Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
f
t
t
TXCLKx Clock Cycle Frequency
TXCLKx Period=1/f
19.5
6.66
2.2
150
MHz
ns
TS
51.28
TXCLK
TXCLKH
TS
[20]
TXCLKx HIGH Time
ns
[20]
TXCLKx LOW Time
2.2
ns
TXCLKL
TXCLKx Rise Time
0.2
1.7
1.7
ns
TXCLKR
TXCLKF
TXDS
TXCLKx Fall Time
0.2
ns
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx ≠ 0)
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx ≠ 0)
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
2.2
ns
1.0
ns
TXDH
19.5
6.66
–1.9
150
51.28
0
MHz
ns
TOS
TXCLKOx Period=1/f
TXCLKO
TOS
TXCLKO Duty Cycle centered at 60% HIGH time
ns
TXCLKOD
CYV15G0404DXB Receiver LVTTL Switching Characteristics Over the Operating Range
f
t
t
RXCLKx± Clock Output Frequency
RXCLKx± Period = 1/f
9.75
6.66
–1.0
150
102.56
+1.0
MHz
ns
RS
RXCLKP
RXCLKD
RS
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate when
RXCKSELx = 0)
ns
[20]
t
t
t
RXCLKx± Rise Time
RXCLKx± Fall Time
0.3
0.3
1.2
1.2
ns
ns
ns
RXCLKR
[20]
RXCLKF
[24]
[24]
[24]
[24]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0)
(Full Rate)
5UI–2.0
RXDv–
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx = 0)
(Half Rate)
5UI–1.3
ns
ns
ns
t
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0) 5UI–1.8
(Full Rate)
RXDv+
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx =0)
(Half Rate)
5UI–2.6
CYV15G0404DXB REFCLKx Switching Characteristics Over the Operating Range
f
t
t
REFCLKx Clock Frequency
REFCLKx Period = 1/f
19.5
6.6
150
MHz
ns
ns
ns
ns
ns
%
REF
51.28
REFCLK
REFH
REF
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
REFCLKx Duty Cycle
5.9
[20]
2.9
t
5.9
REFL
[20]
2.9
t
t
t
30
70
2
REFD
REFCLKx Rise Time (20%–80%)
ns
ns
REFR
REFCLKx Fall Time (20%–80%)
2
REFF
Notes
20. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
21. The ratio of rise time to falling time must not vary by greater than 2:1.
22. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
23. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
24. Receiver UI (Unit Interval) is calculated as 1/(f
* 20) (when TXRATEx = 1) or 1/(f
* 10) (when TXRATEx = 0). In an operating link this is equivalent to t .
REF
REF
B
25. The duty cycle specification is a simultaneous condition with the t
cannot be as large as 30%–70%.
and t
parameters. This means that at faster character rates the REFCLKx± duty cycle
REFH
REFL
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
CYV15G0404DXB AC Electrical Characteristics (continued)
Parameter
Description
Min.
Max
Unit
t
Transmit Data Set-up Time to REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
2.4
ns
TREFDS
Transmit Data Set-up Time to REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
2.3
1.0
1.6
ns
ns
ns
t
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
TREFDH
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
t
t
t
Receive Data Access Time to REFCLKx (RXCKSELx = 1)
Receive Data Valid Time Window (RXCKSELx = 1)
9.7
ns
ns
ns
RREFDA
RREFDW
REFxDV–
10UI – 5.8
Received Data Valid Time to RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 0)
10UI – 6.16
Received Data Valid Time to RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 1)
5UI – 2.53
ns
Received Data Valid Time to RXCLK when RXCKSELx = 1 (TXRATEx = 1) 10UI–5.86
ns
ns
t
Received Data Valid Time from RXCLK when RXCKSELx = 1
1.4
REFxDV+
(TXRATEx = 0, RXRATEx = 0)
Received Data Valid Time from RXCLK when RXCKSELx = 1
5UI – 1.83
ns
ns
%
(TXRATEx = 0, RXRATEx = 1)
Received Data Valid Time from RXCLK when RXCKSELx = 1
(TXRATEx = 1)
1.0
[28]
t
REFCLKx Frequency Referenced to Received Clock Period
–0.15
+0.15
REFRX
CYV15G0404DXB Bus Configuration Write Timing Characteristics Over the Operating Range
t
t
t
Bus Configuration Data Hold
0
ns
ns
ns
DATAH
DATAS
WRENP
Bus Configuration Data Setup
Bus Configuration WREN Pulse Width
10
10
CYV15G0404DXB JTAG Test Clock Characteristics Over the Operating Range
f
t
JTAG Test Clock Frequency
JTAG Test Clock Period
20
MHz
ns
TCLK
TCLK
50
30
CYV15G0404DXB Device RESET Characteristics Over the Operating Range
Device RESET Pulse Width
t
ns
RST
CYV15G0404DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
Parameter
Description
Condition
Min.
Max.
Unit
t
Bit Time
5128
666
ps
B
Notes
26. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
and set-up
RREFDA
time of the upstream device. When this condition is not true, RXCLKx± (a buffered or divided version of REFCLK when RXCKSELx = 1) could be used to clock
the receive data out of the device.
27. Measured using a 50% duty cycle reference clock
28. REFCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
REFCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver neces-
sitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the
limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit
Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.l.
29. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.
30. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLKx± input, over the
operating range.
31. Total jitter is calculated at an assumed BER of 1E -12. Hence: Total Jitter (tJ) = (tRJ * 14) + tDJ.
32. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259, SMPTE 292, ESCON, FICON, Fibre Channel, and DVB-ASI.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
CYV15G0404DXB AC Electrical Characteristics (continued)
Parameter
Description
Min.
60
Max
270
500
1000
270
500
1000
27
Unit
ps
ps
ps
ps
ps
ps
ps
ps
t
t
t
CML Output Rise Time 20−80% (CML Test Load)
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
IEEE 802.3z
RISE
100
180
60
FALL
CML Output Fall Time 80−20% (CML Test Load)
100
180
Deterministic Jitter (peak-peak)
DJ
Z
Random Jitter (σ)
IEEE 802.3z
11
RJ
t
t
REFCLKx jitter tolerance / Phase noise limits
TBD
200
REFJ
Transmit PLLx lock to REFCLKx±
μs
TXLOCK
CYV15G0404DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
t
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
Receive PLL Unlock Rate
376k
376k
46
UI
UI
UI
ps
ps
RXLOCK
t
t
t
RXUNLOCK
Total Jitter Tolerance
IEEE 802.3z
IEEE 802.3z
600
370
JTOL
Deterministic Jitter Tolerance
DJTOL
Capacitance[20]
Parameter
Description
TTL Input Capacitance
PECL input Capacitance
Test Conditions
Max.
Unit
C
C
T = 25°C, f = 1 MHz, V = 3.3V
7
4
pF
pF
INTTL
A
0
CC
T = 25°C, f = 1 MHz, V = 3.3V
INPECL
A
0
CC
CYV15G0404DXB HOTLink II Transmitter Switching Waveforms
tTXCLK
Transmit Interface
tTXCLKH
tTXCLKL
Write Timing
TXCLKx selected
TXCLKx
tTXDS
tTXDH
TXDx[7:0],
TXCTx[1:0],
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 0
tREFCLK
tREFH
tREFL
REFCLKx
tTREFDS
tTREFDH
TXDx[7:0],
TXCTx[1:0],
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
CYV15G0404DXB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
tREFCLK
Write Timing
REFCLKx selected
TXRATEx = 1
tREFH
tREFL
REFCLKx
Note 33
tTREFDS
tTREFDH
tTREFDS
tTREFDH
TXDx[7:0],
TXCTx[1:0],
Note
33. When REFCLKx± is configured for half rate operation (TXRATE = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using
both the rising and falling edges of REFCLKx.
Transmit Interface
TXCLKOx Timing
tREFCLK
tREFH
tREFL
TXRATEx = 1
REFCLKx
Note 34
tTXCLKO
Note 35
TXCLKOx
(internal)
Transmit Interface
TXCLKOx Timing
t
REFCLK
t
t
REFH
REFL
TXRATEx = 0
Note 34
REFCLKx
t
TXCLKO
t
t
TXOL
TXOH
Note 35
TXCLKOx
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver
Receive Interface
t
REFCLK
Read Timing
t
t
REFL
REFCLKx Selected
full rate RXCLKx±
REFH
REFCLKx
t
RREFDA
t
t
RREFDW
RREFDW
RXDx[7:0],
TXERRx
t
REFxDV+
t
REFxDV
–
RXCLKx
Notes
34. The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.
35. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.
36. TXERRx is synchronous to RXCLKx only when RXCLKx is selected as REFCLK.
Receive Interface
t
REFCLK
Read Timing
t
t
REFL
REFCLKx Selected
half rate RXCLKx±
REFH
REFCLKx
t
RREFDA
t
RREFDW
t
t
RREFDW
RREFDA
RXDx[7:0],
RXSTx[2:0],
TXERRx
t
REFxDV+
t
REFxDV
–
Note 37
RXCLKx
Receive Interface
Read Timing
Recovered Clock selected
RXRATEx = 0
t
RXCLKP
RXCLKx+
RXCLKx-
RXDx[7:0],
RXSTx[2:0],
t
RXDV
–
t
RXDV+
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver
Receive Interface
t
Read Timing
RXCLKP
Recovered Clock selected
RXRATEx = 1
RXCLKx+
RXCLKx-
t
RXDV
–
RXDx[7:0],
RXSTx[2:0]
t
RXDV+
Note
37. When operated with a half rate REFCLKx±, the setup and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the
respective clock output
Bus Configuration
Write Timing
ADDR[3:0]
DATA[7:0]
t
WRENP
t
DATAS
WREN
t
DATAH
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Table 11. Package Coordinate Signal Allocation
Ball
ID
Ball
ID
Ball
ID
Signal Name
Signal Type
Signal Name
Signal Type
Signal Name
Signal Type
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
INC1–
OUTC1–
INC2–
OUTC2–
VCC
CML IN
CML OUT
CML IN
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E17
E18
E19
E20
F01
ULCC
GND
LVTTL IN PU
GROUND
F17
F18
F19
F20
G01
G02
G03
G04
G17
G18
G19
G20
H01
H02
H03
H04
H17
H18
H19
H20
J01
J02
J03
J04
J17
J18
J19
J20
K01
K02
K03
K04
K17
K18
K19
K20
L01
L02
L03
L04
L17
L18
L19
RCLKENA
RXSTB[1]
TXCLKOB
RXSTB[0]
TXDC[7]
WREN
LVTTL IN PD
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
DATA[7]
DATA[5]
DATA[3]
DATA[1]
GND
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
GROUND
CML OUT
POWER
CML IN
IND1–
OUTD1–
GND
LVTTL IN PU
LVTTL IN
CML OUT
GROUND
CML IN
TXDC[4]
TXDC[1]
SPDSELB
LPENC
RCLKENB
SPDSELD
VCC
LVTTL IN PD
3-LEVEL SEL
POWER
LVTTL IN
IND2–
OUTD2–
INA1–
3-LEVEL SEL
LVTTL IN PD
3-LEVEL SEL
LVTTL OUT
GROUND
CML OUT
CML IN
LDTDEN
TRST
LVTTL IN PU
LVTTL IN PU
LVTTL IN PD
LVTTL 3-S OUT
LVTTL IN PD
LVTTL IN PU
LVTTL IN
SPDSELA
RXDB[1]
GND
OUTA1–
GND
CML OUT
GROUND
CML IN
LPEND
TDO
INA2–
GND
GROUND
OUTA2–
VCC
CML OUT
POWER
CML IN
TCLK
GND
GROUND
RESET
INSELD
INSELA
VCC
GND
GROUND
INB1–
GND
GROUND
OUTB1–
INB2–
CML OUT
CML IN
LVTTL IN
GND
GROUND
POWER
GND
GROUND
OUTB2–
INC1+
OUTC1+
INC2+
OUTC2+
VCC
CML OUT
CML IN
ULCA
LVTTL IN PU
3-LEVEL SEL
GROUND
GND
GROUND
SPDSELC
GND
TXCTC[1]
TXDC[5]
TXDC[2]
TXDC[3]
RXSTB[2]
RXDB[0]
RXDB[5]
RXDB[2]
RXDC[2]
REFCLKC–
TXCTC[0]
TXCLKC
RXDB[3]
RXDB[4]
RXDB[7]
LFIB
LVTTL IN
CML OUT
CML IN
LVTTL IN
DATA[6]
DATA[4]
DATA[2]
DATA[0]
GND
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
GROUND
LVTTL IN
CML OUT
POWER
CML IN
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
PECL IN
IND1+
OUTD1+
GND
CML OUT
GROUND
CML IN
LPENB
ULCB
LVTTL IN PD
LVTTL IN PU
POWER
IND2+
OUTD2+
INA1+
CML OUT
CML IN
VCC
LPENA
VCC
LVTTL IN PD
POWER
LVTTL IN
OUTA1+
GND
CML OUT
GROUND
CML IN
LVTTL IN PD
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
PECL IN
SCANEN2
TMEN3
VCC
LVTTL IN PD
LVTTL IN PD
POWER
INA2+
OUTA2+
VCC
CML OUT
POWER
CML IN
VCC
POWER
INB1+
VCC
POWER
RXDC[3]
REFCLKC+
LFIC
OUTB1+
INB2+
CML OUT
CML IN
VCC
POWER
VCC
POWER
LVTTL OUT
LVTTL IN
OUTB2+
TDI
CML OUT
LVTTL IN PU
LVTTL IN PU
LVTTL IN
VCC
POWER
TXDC[6]
RXDB[6]
RXCLKB+
RXCLKB–
VCC
POWER
LVTTL OUT
LVTTL OUT
LVTTL OUT
TMS
VCC
POWER
INSELC
RXDC[6]
LVTTL OUT
Document #: 38-02097 Rev. *B
Page 34 of 44
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CYV15G0404DXB
Table 11. Package Coordinate Signal Allocation (continued)
Ball
ID
Ball
ID
Ball
ID
Signal Name
Signal Type
Signal Name
Signal Type
Signal Name
Signal Type
C04
C05
C06
M03
M04
INSELB
VCC
LVTTL IN
POWER
F02
F03
F04
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
RXDC[7]
TXDC[0]
RCLKEND
TXDD[2]
TXCTD[1]
VCC
LVTTL OUT
LVTTL IN
L20
M01
M02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
TXDB[6]
RXDC[4]
RXDC[5]
LFID
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
POWER
ULCD
LVTTL IN PU
LVTTL IN PD
LVTTL OUT
PECL IN
LVTTL IN PD
LVTTL IN
RCLKENC
TXERRC
LVTTL IN
RXCLKD–
VCC
M17 REFCLKB+
M18 REFCLKB–
POWER
PECL IN
RXDD[2]
RXDD[1]
GND
LVTTL OUT
LVTTL OUT
GROUND
LVTTL IN
RXDD[4]
RXSTD[1]
GND
LVTTL OUT
LVTTL OUT
GROUND
M19
M20
N01
N02
N03
N04
N17
N18
N19
N20
P01
P02
P03
P04
P17
P18
P19
P20
R01
R02
R03
R04
R17
R18
R19
R20
T01
T02
T03
T04
T17
T18
T19
T20
U01
U02
TXERRB
TXCLKB
GND
LVTTL OUT
LVTTL IN PD
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
POWER
TXCTA[1]
ADDR [0]
REFCLKD–
TXDA[1]
GND
ADDR [3]
ADDR [1]
RXCLKA+
TXERRA
GND
LVTTL IN PU
LVTTL IN PU
LVTTL OUT
LVTTL OUT
GROUND
GND
LVTTL IN PU
PECL IN
GND
GND
LVTTL IN
GND
GROUND
LVTTL IN
GND
TXDA[4]
TXCTA[0]
VCC
TXDA[2]
TXDA[6]
VCC
LVTTL IN
GND
LVTTL IN
LVTTL IN
GND
POWER
POWER
RXDC[1]
RXDC[0]
RXSTC[0]
RXSTC[1]
TXDB[5]
TXDB[4]
TXDB[3]
TXDB[2]
RXSTC[2]
TXCLKOC
RXCLKC+
RXCLKC–
TXDB[1]
TXDB[0]
TXCTB[1]
TXDB[7]
VCC
RXDA[2]
TXCTB[0]
RXSTA[2]
RXSTA[1]
TXDD[3]
TXDD[4]
TXCTD[0]
RXDD[6]
VCC
LVTTL OUT
LVTTL IN
LFIA
LVTTL OUT
PECL IN
W18 REFCLKA+
LVTTL OUT
LVTTL OUT
LVTTL IN
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
RXDA[4]
RXDA[1]
TXDD[6]
TXCLKD
RXDD[7]
RXCLKD+
VCC
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN PD
LVTTL OUT
LVTTL OUT
POWER
LVTTL IN
LVTTL OUT
POWER
RXDD[3]
RXSTD[0]
GND
LVTTL OUT
LVTTL OUT
GROUND
LVTTL OUT
LVTTL IN PU
PECL IN
RXDD[5]
RXDD[0]
GND
LVTTL OUT
LVTTL OUT
GROUND
RXSTD[2]
ADDR [2]
REFCLKD+
TXCLKOA
GND
TXCLKOD
NC
LVTTL OUT
NO CONNECT
LVTTL IN PD
LVTTL OUT
GROUND
TXCLKA
RXCLKA–
GND
LVTTL OUT
GROUND
LVTTL IN
VCC
POWER
TXDA[3]
TXDA[7]
VCC
TXDA[0]
TXDA[5]
VCC
LVTTL IN
VCC
POWER
LVTTL IN
LVTTL IN
VCC
POWER
POWER
POWER
VCC
POWER
RXDA[7]
RXDA[3]
RXDA[0]
RXSTA[0]
TXDD[5]
TXDD[7]
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
TXERRD
REFCLKA–
RXDA[6]
RXDA[5]
LVTTL OUT
PECL IN
VCC
POWER
VCC
POWER
LVTTL OUT
LVTTL OUT
VCC
POWER
TXDD[0]
TXDD[1]
LVTTL IN
LVTTL IN
LVTTL IN
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
is set to D, xx is the decimal value of the binary number
composed of the bits E, D, C, B, and A in that order, and the y is
the decimal value of the binary number composed of the bits H,
G, and F in that order. When c is set to K, xx and y are derived
by comparing the encoded bit patterns of the Special Character
to those patterns derived from encoded valid data bytes and
selecting the names of the patterns most similar to the encoded
bit patterns of the special character.
X3.230 Codes and Notation Conventions
Information transmitted over a serial link is encoded eight bits at
a time into a 10-bit Transmission Character and then sent
serially, bit-by-bit. Information received over a serial link is
collected ten bits at a time, and those transmission characters
that are used for data characters are decoded into the correct
8-bit codes. The 10-bit transmission code supports all 256 8-bit
combinations. Some of the remaining transmission characters
(special characters) are used for functions other than data trans-
mission.
Using these conventions, the transmission character used for
the examples above, is referred to by the name D5.2. The special
character K29.7 is so named because the first six bits (abcdei)
of this character make up a bit pattern similar to that resulting
from the encoding of the unencoded 11101 pattern (29), and
because the second four bits (fghj) make up a bit pattern similar
to that resulting from the encoding of the unencoded 111 pattern
(7).
The primary use of a transmission code is to improve the trans-
mission characteristics of a serial link. The encoding defined by
the transmission code ensures that sufficient transitions are
present in the serial bit stream to make clock recovery possible
at the receiver. Such encoding also greatly increases the
likelihood of detecting any single or multiple bit errors that may
occur during transmission and reception of information. In
addition, some special characters of the transmission code
selected by Fibre Channel Standard contain a distinct and easily
recognizable bit pattern that assists the receiver in achieving
character alignment on the incoming bit stream.
Note. This definition of the 10-bit transmission code is based on
the following references, which describe the same 10-bit trans-
mission code.
■ A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-
tioned-Block, 8B/10B Transmission Code” IBM Journal of
ResearchandDevelopment, 27, No. 5:440-451(September, 1983).
Notation Conventions
■ U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.
Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned
Block Transmission Code” (December 4, 1984).
The documentation for the 8B/10B Transmission Code uses
letter notation for the bits in an 8-bit byte. Fibre Channel Standard
notation uses a bit notation of A, B, C, D, E, F, G, H for the 8-bit
byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j
for encoded 10-bit data. There is a correspondence between bit
A and bit a, B and b, C and c, D and d, E and e, F and f, G and
g, and H and h. Bits i and j are derived, respectively, from
(A,B,C,D,E) and (F,G,H).
■ Fibre Channel Physical and Signaling Interface (ANS
X3.230-1994 ANSI FC-PH Standard).
■ IBM Enterprise Systems Architecture/390 ESCON I/O
Interface (document number SA22-7202).
8B/10B Transmission Code
The bit labeled A in the description of the 8B/10B Transmission
Code corresponds to bit 0 in the numbering scheme of the FC-2
specification, B corresponds to bit 1, as shown below.
FC-2 bit designation—76543210
HOTLink D/Q designation—76543210
8B/10B bit designation—HGFEDCBA
The following information describes how the tables are used for
both generating valid transmission characters (encoding) and
checking the validity of received transmission characters
(decoding). It also specifies the ordering rules followed when
transmitting the bits within a character and the characters within
any higher level constructs specified by a standard.
To clarify this correspondence, the following example shows the
conversion from an FC-2 Valid Data Byte to a Transmission
Character.
Transmission Order
FC-2 45H
Within the definition of the 8B/10B transmission code, the bit
positions of the transmission characters are labeled a, b, c, d, e,
i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i,
f, g, h, and j in that order.
Bits: 7654 3210
0100 0101
Converted to 8B/10B notation, note that the order of bits has
been reversed):
Note that bit i is transmitted between bit e and bit f, rather than
in alphabetical order.
Data Byte Name D5.2
Bits: ABCDE FGH
10100 010
Valid and Invalid Transmission Characters
The following tables define the valid data characters and valid
special characters (K characters), respectively. The tables are
used for both generating valid transmission characters and
checking the validity of received transmission characters. In the
tables, each valid-data-byte or special-character-code entry has
two columns that represent two transmission characters. The
two columns correspond to the current value of the running
disparity. Running disparity is a binary parameter with either a
negative (–) or positive (+) value.
Translated to a transmission Character in the 8B/10B Trans-
mission Code:
Bits: abcdei fghj
101001 0101
Each valid transmission character of the 8B/10B Transmission
Code has been given a name using the following convention:
cxx.y, where c is used to show whether the Transmission
Character is a Data Character (c is set to D, and SC/D = LOW)
or a special character (c is set to K, and SC/D = HIGH). When c
After powering on, the transmitter may assume either a positive
or negative value for its initial running disparity. Upon trans-
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CYV15G0404DXB
mission of any transmission character, the transmitter selects the
proper version of the transmission character based on the
current running disparity value, and the transmitter calculates a
new value for its running disparity based on the contents of the
transmitted character. Special character codes C1.7 and C2.7
can be used to force the transmission of a specific special
character with a specific running disparity as required for some
special sequences in X3.230.
transmitted, a new value of the running disparity is calculated.
This new value is used as the transmitter’s current running
disparity for the next valid data byte or Special Character byte
examples of valid transmission characters.
Use of the Tables for Checkingthe Validity ofReceived
Transmission Characters
After powering on, the receiver may assume either a positive or
negative value for its initial running disparity. Upon reception of
any transmission character, the receiver decides whether the
transmission character is valid or invalid according to the
following rules and tables and calculates a new value for its
running disparity based on the contents of the received
character.
The column corresponding to the current value of the receiver’s
running disparity is searched for the received transmission
character. If the received transmission character is found in the
proper column, then the transmission character is valid and the
associated data byte or special character code is determined
(decoded). If the received transmission character is not found in
that column, then the transmission character is invalid. This is a
code violation. Independent of the transmission character’s
validity, the received transmission character is used to calculate
a new value of running disparity. The new value is used as the
receiver’s current running disparity for the next received trans-
mission character.
The following rules for running disparity are used to calculate the
new running disparity value for transmission characters that
have been transmitted and received.
Running disparity for a transmission character is calculated from
subblocks, where the first six bits (abcdei) form one subblock and
the second four bits (fghj) form the other subblock. Running
disparity at the beginning of the 6-bit subblock is the running
disparity at the end of the previous transmission character.
running disparity at the beginning of the 4-bit subblock is the
running disparity at the end of the 6-bit subblock. Running
disparity at the end of the transmission character is the running
disparity at the end of the 4-bit subblock.
Table 12. Valid Transmission Characters
Data
D
or Q
OUT
IN
Byte Name
Hex Value
765
43210
D0.0
D1.0
D2.0
000 00000
000 00001
000 00010
00
01
02
Running disparity for the subblocks is calculated as follows:
1. Running disparity at the end of any subblock is positive if the
subblock contains more ones than zeros. It is also positive at
the end of the 6-bit subblock if the 6-bit subblock is 000111,
and it is positive at the end of the 4-bit subblock if the 4-bit
subblock is 0011.
.
.
.
.
.
.
.
.
2. Running disparity at the end of any subblock is negative if the
subblock contains more zeros than ones. It is also negative
at the end of the 6-bit subblock if the 6-bit subblock is 111000,
and it is negative at the end of the 4-bit subblock if the 4-bit
subblock is 1100.
D5.2
010 00101
45
.
.
.
.
.
.
.
.
D30.7
D31.7
111 11110
111 11111
FE
FF
3. Otherwise, running disparity at the end of the subblock is the
same as at the beginning of the subblock.
Use of the Tables for Generating Transmission
Characters
Detection of a code violation does not necessarily show that the
transmission character in which the code violation was detected
is in error. Code violations may result from a prior error that
altered the running disparity of the bit stream which did not result
in a detectable error at the transmission character in which the
error occurred. Table 12 shows an example of this behavior.
character is generated. The current value of the transmitter’s
running disparity is used to select the transmission character
from its corresponding column. For each transmission character
Table 13. Code Violations Resulting from Prior Errors
RD
–
Character
D21.1
RD
–
Character
D10.2
RD
–
Character
D23.5
RD
+
Transmitted data character
Transmitted bit stream
Bit stream after error
–
101010 1001
101010 1011
D21.0
–
010101 0101
010101 0101
D10.2
–
111010 1010
111010 1010
Code Violation
+
–
+
+
+
Decoded data character
–
+
+
+
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CYV15G0404DXB
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)
Data
Byte
Data
Byte
Name HGF EDCBA
Bits
Current RD−
Current RD+
abcdei fghj
Bits
Current RD−
abcdei fghj
Current RD+
abcdei fghj
Name HGF EDCBA
abcdei fghj
D0.0
D1.0
D2.0
D3.0
D4.0
D5.0
D6.0
D7.0
D8.0
D9.0
000 00000 100111 0100 011000 1011
000 00001 011101 0100 100010 1011
000 00010 101101 0100 010010 1011
000 00011 110001 1011 110001 0100
000 00100 110101 0100 001010 1011
000 00101 101001 1011 101001 0100
000 00110 011001 1011 011001 0100
000 00111 111000 1011 000111 0100
000 01000 111001 0100 000110 1011
000 01001 100101 1011 100101 0100
D0.1
D1.1
D2.1
D3.1
D4.1
D5.1
D6.1
D7.1
D8.1
D9.1
001 00000 100111 1001 011000 1001
001 00001 011101 1001 100010 1001
001 00010 101101 1001 010010 1001
001 00011 110001 1001 110001 1001
001 00100 110101 1001 001010 1001
001 00101 101001 1001 101001 1001
001 00110 011001 1001 011001 1001
001 00111 111000 1001 000111 1001
001 01000 111001 1001 000110 1001
001 01001 100101 1001 100101 1001
D10.0 000 01010 010101 1011 010101 0100
D11.0 000 01011 110100 1011 110100 0100
D12.0 000 01100 001101 1011 001101 0100
D13.0 000 01101 101100 1011 101100 0100
D14.0 000 01110 011100 1011 011100 0100
D15.0 000 01111 010111 0100 101000 1011
D16.0 000 10000 011011 0100 100100 1011
D17.0 000 10001 100011 1011 100011 0100
D18.0 000 10010 010011 1011 010011 0100
D19.0 000 10011 110010 1011 110010 0100
D20.0 000 10100 001011 1011 001011 0100
D21.0 000 10101 101010 1011 101010 0100
D22.0 000 10110 011010 1011 011010 0100
D23.0 000 10111 111010 0100 000101 1011
D24.0 000 11000 110011 0100 001100 1011
D25.0 000 11001 100110 1011 100110 0100
D26.0 000 11010 010110 1011 010110 0100
D27.0 000 11011 110110 0100 001001 1011
D28.0 000 11100 001110 1011 001110 0100
D29.0 000 11101 101110 0100 010001 1011
D30.0 000 11110 011110 0100 100001 1011
D31.0 000 11111 101011 0100 010100 1011
D10.1 001 01010 010101 1001 010101 1001
D11.1 001 01011 110100 1001 110100 1001
D12.1 001 01100 001101 1001 001101 1001
D13.1 001 01101 101100 1001 101100 1001
D14.1 001 01110 011100 1001 011100 1001
D15.1 001 01111 010111 1001 101000 1001
D16.1 001 10000 011011 1001 100100 1001
D17.1 001 10001 100011 1001 100011 1001
D18.1 001 10010 010011 1001 010011 1001
D19.1 001 10011 110010 1001 110010 1001
D20.1 001 10100 001011 1001 001011 1001
D21.1 001 10101 101010 1001 101010 1001
D22.1 001 10110 011010 1001 011010 1001
D23.1 001 10111 111010 1001 000101 1001
D24.1 001 11000 110011 1001 001100 1001
D25.1 001 11001 100110 1001 100110 1001
D26.1 001 11010 010110 1001 010110 1001
D27.1 001 11011 110110 1001 001001 1001
D28.1 001 11100 001110 1001 001110 1001
D29.1 001 11101 101110 1001 010001 1001
D30.1 001 11110 011110 1001 100001 1001
D31.1 001 11111 101011 1001 010100 1001
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CYV15G0404DXB
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Data
Byte
Bits
Current RD−
Current RD+
abcdei fghj
Bits
Current RD−
abcdei fghj
Current RD+
abcdei fghj
Name HGF EDCBA
abcdei fghj
Name HGF EDCBA
D0.2
D1.2
D2.2
D3.2
D4.2
D5.2
D6.2
D7.2
D8.2
D9.2
010 00000 100111 0101 011000 0101
010 00001 011101 0101 100010 0101
010 00010 101101 0101 010010 0101
010 00011 110001 0101 110001 0101
010 00100 110101 0101 001010 0101
010 00101 101001 0101 101001 0101
010 00110 011001 0101 011001 0101
010 00111 111000 0101 000111 0101
010 01000 111001 0101 000110 0101
010 01001 100101 0101 100101 0101
D0.3
D1.3
D2.3
D3.3
D4.3
D5.3
D6.3
D7.3
D8.3
D9.3
011 00000 100111 0011 011000 1100
011 00001 011101 0011 100010 1100
011 00010 101101 0011 010010 1100
011 00011 110001 1100 110001 0011
011 00100 110101 0011 001010 1100
011 00101 101001 1100 101001 0011
011 00110 011001 1100 011001 0011
011 00111 111000 1100 000111 0011
011 01000 111001 0011 000110 1100
011 01001 100101 1100 100101 0011
D10.2 010 01010 010101 0101 010101 0101
D11.2 010 01011 110100 0101 110100 0101
D12.2 010 01100 001101 0101 001101 0101
D13.2 010 01101 101100 0101 101100 0101
D14.2 010 01110 011100 0101 011100 0101
D15.2 010 01111 010111 0101 101000 0101
D16.2 010 10000 011011 0101 100100 0101
D17.2 010 10001 100011 0101 100011 0101
D18.2 010 10010 010011 0101 010011 0101
D19.2 010 10011 110010 0101 110010 0101
D20.2 010 10100 001011 0101 001011 0101
D21.2 010 10101 101010 0101 101010 0101
D22.2 010 10110 011010 0101 011010 0101
D23.2 010 10111 111010 0101 000101 0101
D24.2 010 11000 110011 0101 001100 0101
D25.2 010 11001 100110 0101 100110 0101
D26.2 010 11010 010110 0101 010110 0101
D27.2 010 11011 110110 0101 001001 0101
D28.2 010 11100 001110 0101 001110 0101
D29.2 010 11101 101110 0101 010001 0101
D30.2 010 11110 011110 0101 100001 0101
D31.2 010 11111 101011 0101 010100 0101
D10.3 011 01010 010101 1100 010101 0011
D11.3 011 01011 110100 1100 110100 0011
D12.3 011 01100 001101 1100 001101 0011
D13.3 011 01101 101100 1100 101100 0011
D14.3 011 01110 011100 1100 011100 0011
D15.3 011 01111 010111 0011 101000 1100
D16.3 011 10000 011011 0011 100100 1100
D17.3 011 10001 100011 1100 100011 0011
D18.3 011 10010 010011 1100 010011 0011
D19.3 011 10011 110010 1100 110010 0011
D20.3 011 10100 001011 1100 001011 0011
D21.3 011 10101 101010 1100 101010 0011
D22.3 011 10110 011010 1100 011010 0011
D23.3 011 10111 111010 0011 000101 1100
D24.3 011 11000 110011 0011 001100 1100
D25.3 011 11001 100110 1100 100110 0011
D26.3 011 11010 010110 1100 010110 0011
D27.3 011 11011 110110 0011 001001 1100
D28.3 011 11100 001110 1100 001110 0011
D29.3 011 11101 101110 0011 010001 1100
D30.3 011 11110 011110 0011 100001 1100
D31.3 011 11111 101011 0011 010100 1100
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CYV15G0404DXB
Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Data
Byte
Bits
Current RD−
Current RD+
abcdei fghj
Bits
Current RD−
abcdei fghj
Current RD+
abcdei fghj
Name HGF EDCBA
abcdei fghj
Name HGF EDCBA
D0.4
D1.4
D2.4
D3.4
D4.4
D5.4
D6.4
D7.4
D8.4
D9.4
100 00000 100111 0010 011000 1101
100 00001 011101 0010 100010 1101
100 00010 101101 0010 010010 1101
100 00011 110001 1101 110001 0010
100 00100 110101 0010 001010 1101
100 00101 101001 1101 101001 0010
100 00110 011001 1101 011001 0010
100 00111 111000 1101 000111 0010
100 01000 111001 0010 000110 1101
100 01001 100101 1101 100101 0010
D0.5
D1.5
D2.5
D3.5
D4.5
D5.5
D6.5
D7.5
D8.5
D9.5
101 00000 100111 1010 011000 1010
101 00001 011101 1010 100010 1010
101 00010 101101 1010 010010 1010
101 00011 110001 1010 110001 1010
101 00100 110101 1010 001010 1010
101 00101 101001 1010 101001 1010
101 00110 011001 1010 011001 1010
101 00111 111000 1010 000111 1010
101 01000 111001 1010 000110 1010
101 01001 100101 1010 100101 1010
D10.4 100 01010 010101 1101 010101 0010
D11.4 100 01011 110100 1101 110100 0010
D12.4 100 01100 001101 1101 001101 0010
D13.4 100 01101 101100 1101 101100 0010
D14.4 100 01110 011100 1101 011100 0010
D15.4 100 01111 010111 0010 101000 1101
D16.4 100 10000 011011 0010 100100 1101
D17.4 100 10001 100011 1101 100011 0010
D18.4 100 10010 010011 1101 010011 0010
D19.4 100 10011 110010 1101 110010 0010
D20.4 100 10100 001011 1101 001011 0010
D21.4 100 10101 101010 1101 101010 0010
D22.4 100 10110 011010 1101 011010 0010
D23.4 100 10111 111010 0010 000101 1101
D24.4 100 11000 110011 0010 001100 1101
D25.4 100 11001 100110 1101 100110 0010
D26.4 100 11010 010110 1101 010110 0010
D27.4 100 11011 110110 0010 001001 1101
D28.4 100 11100 001110 1101 001110 0010
D29.4 100 11101 101110 0010 010001 1101
D30.4 100 11110 011110 0010 100001 1101
D31.4 100 11111 101011 0010 010100 1101
D10.5 101 01010 010101 1010 010101 1010
D11.5 101 01011 110100 1010 110100 1010
D12.5 101 01100 001101 1010 001101 1010
D13.5 101 01101 101100 1010 101100 1010
D14.5 101 01110 011100 1010 011100 1010
D15.5 101 01111 010111 1010 101000 1010
D16.5 101 10000 011011 1010 100100 1010
D17.5 101 10001 100011 1010 100011 1010
D18.5 101 10010 010011 1010 010011 1010
D19.5 101 10011 110010 1010 110010 1010
D20.5 101 10100 001011 1010 001011 1010
D21.5 101 10101 101010 1010 101010 1010
D22.5 101 10110 011010 1010 011010 1010
D23.5 101 10111 111010 1010 000101 1010
D24.5 101 11000 110011 1010 001100 1010
D25.5 101 11001 100110 1010 100110 1010
D26.5 101 11010 010110 1010 010110 1010
D27.5 101 11011 110110 1010 001001 1010
D28.5 101 11100 001110 1010 001110 1010
D29.5 101 11101 101110 1010 010001 1010
D30.5 101 11110 011110 1010 100001 1010
D31.5 101 11111 101011 1010 010100 1010
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Table 14. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Data
Byte
Bits
Current RD−
Current RD+
abcdei fghj
Bits
Current RD−
abcdei fghj
Current RD+
abcdei fghj
Name HGF EDCBA
abcdei fghj
Name HGF EDCBA
D0.6
D1.6
D2.6
D3.6
D4.6
D5.6
D6.6
D7.6
D8.6
D9.6
110 00000 100111 0110 011000 0110
110 00001 011101 0110 100010 0110
110 00010 101101 0110 010010 0110
110 00011 110001 0110 110001 0110
110 00100 110101 0110 001010 0110
110 00101 101001 0110 101001 0110
110 00110 011001 0110 011001 0110
110 00111 111000 0110 000111 0110
110 01000 111001 0110 000110 0110
110 01001 100101 0110 100101 0110
D0.7
D1.7
D2.7
D3.7
D4.7
D5.7
D6.7
D7.7
D8.7
D9.7
111 00000 100111 0001 011000 1110
111 00001 011101 0001 100010 1110
111 00010 101101 0001 010010 1110
111 00011 110001 1110 110001 0001
111 00100 110101 0001 001010 1110
111 00101 101001 1110 101001 0001
111 00110 011001 1110 011001 0001
111 00111 111000 1110 000111 0001
111 01000 111001 0001 000110 1110
111 01001 100101 1110 100101 0001
D10.6 110 01010 010101 0110 010101 0110
D11.6 110 01011 110100 0110 110100 0110
D12.6 110 01100 001101 0110 001101 0110
D13.6 110 01101 101100 0110 101100 0110
D14.6 110 01110 011100 0110 011100 0110
D15.6 110 01111 010111 0110 101000 0110
D16.6 110 10000 011011 0110 100100 0110
D17.6 110 10001 100011 0110 100011 0110
D18.6 110 10010 010011 0110 010011 0110
D19.6 110 10011 110010 0110 110010 0110
D20.6 110 10100 001011 0110 001011 0110
D21.6 110 10101 101010 0110 101010 0110
D22.6 110 10110 011010 0110 011010 0110
D23.6 110 10111 111010 0110 000101 0110
D24.6 110 11000 110011 0110 001100 0110
D25.6 110 11001 100110 0110 100110 0110
D26.6 110 11010 010110 0110 010110 0110
D27.6 110 11011 110110 0110 001001 0110
D28.6 110 11100 001110 0110 001110 0110
D29.6 110 11101 101110 0110 010001 0110
D30.6 110 11110 011110 0110 100001 0110
D31.6 110 11111 101011 0110 010100 0110
D10.7 111 01010 010101 1110 010101 0001
D11.7 111 01011 110100 1110 110100 1000
D12.7 111 01100 001101 1110 001101 0001
D13.7 111 01101 101100 1110 101100 1000
D14.7 111 01110 011100 1110 011100 1000
D15.7 111 01111 010111 0001 101000 1110
D16.7 111 10000 011011 0001 100100 1110
D17.7 111 10001 100011 0111 100011 0001
D18.7 111 10010 010011 0111 010011 0001
D19.7 111 10011 110010 1110 110010 0001
D20.7 111 10100 001011 0111 001011 0001
D21.7 111 10101 101010 1110 101010 0001
D22.7 111 10110 011010 1110 011010 0001
D23.7 111 10111 111010 0001 000101 1110
D24.7 111 11000 110011 0001 001100 1110
D25.7 111 11001 100110 1110 100110 0001
D26.7 111 11010 010110 1110 010110 0001
D27.7 111 11011 110110 0001 001001 1110
D28.7 111 11100 001110 1110 001110 0001
D29.7 111 11101 101110 0001 010001 1110
D30.7 111 11110 011110 0001 100001 1110
D31.7 111 11111 101011 0001 010100 1110
Document #: 38-02097 Rev. *B
Page 41 of 44
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CYV15G0404DXB
Table 15. Valid Special Character Codes and Sequences (TXCTx = special character code or RXSTx[2:0] = 001)
S.C. Byte Name
Cypress
Alternate
Current RD−
abcdei fghj
Current RD+
abcdei fghj
S.C. Code Name
Bits
Bits
Name
HGF EDCBA
Name
HGF EDCBA
K28.0
C0.0
(C00)
(C01)
(C02)
(C03)
(C04)
(C05)
(C06)
(C07)
(C08)
(C09)
000 00000
000 00001
000 00010
000 00011
000 00100
000 00101
000 00110
000 00111
000 01000
000 01001
000 01010
000 01011
C28.0 (C1C)
C28.1 (C3C)
C28.2 (C5C)
C28.3 (C7C)
C28.4 (C9C)
C28.5 (CBC)
C28.6 (CDC)
C28.7 (CFC)
C23.7 (CF7)
C27.7 (CFB)
C29.7 (CFD)
C30.7 (CFE)
000 11100
001 11100
010 11100
011 11100
100 11100
101 11100
110 11100
111 11100
111 10111
111 11011
111 11101
111 11110
001111 0100
001111 1001
001111 0101
001111 0011
001111 0010
001111 1010
001111 0110
001111 1000
111010 1000
110110 1000
101110 1000
011110 1000
110000 1011
110000 0110
110000 1010
110000 1100
110000 1101
110000 0101
110000 1001
110000 0111
000101 0111
001001 0111
010001 0111
100001 0111
K28.1
C1.0
C2.0
C3.0
C4.0
C5.0
C6.0
C7.0
C8.0
C9.0
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
C10.0 (C0A)
C11.0 (C0B)
End of Frame Sequence
EOFxx C2.1
[44]
(C22)
001 00010
C2.1
(C22)
001 00010
−K28.5,Dn.xxx0
+K28.5,Dn.xxx1
Code Rule Violation and SVS Tx Pattern
Exception
C0.7
C1.7
C2.7
(CE0)
(CE1)
(CE2)
111 00000
111 00001
111 00010
C0.7
C1.7
C2.7
(CE0)
(CE1)
(CE2)
111 00000
111 00001
111 00010
100111 1000
001111 1010
110000 0101
011000 0111
001111 1010
110000 0101
−K28.5
+K28.5
Running Disparity Violation Pattern
Exception
C4.7
(CE4)
111 00100
C4.7
(CE4)
111 00100
110111 0101
001000 1010
Notes
38. All codes not shown are reserved.
39. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).
40. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received
characters generates Cypress codes or Alternate codes as selected by the BOE[7:0] configuration inputs.
41. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON
protocols.
42. The K28.5 character is used for framing operations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data is
available.
43. Care must be taken when using this Special Character code. When a C7.0 or a C0.7 is followed by a D11.x or D20.x, an alias K28.5 sync character is created.
These sequences can cause erroneous framing and should be avoided while RFENx = 1.
44. C2.1 = Transmit either –K28.5+ or +K28.5– as determined by Current RD and modify the Transmission Character that follows, by setting its least significant bit
to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (–) the LSB becomes 1. This modification
allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.
For example, to send “EOFdt” the controller could issue the sequence C2.1–D21.4– D21.4–D21.4, and the HOTLink Transmitter sends either
K28.5–D21.4–D21.4–D21.4 or K28.5–D21.5– D21.4–D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence
C2.1–D10.4–D21.4–D21.4, and the HOTLink Transmitter sends either K28.5–D10.4–D21.4– D21.4 or K28.5–D10.5–D21.4–D21.4 based on Current RD.
The receiver never outputs this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.
45. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special
Character has the same effect as asserting TXSVS = HIGH. The receiver only outputs this Special Character if the Transmission Character being decoded is
not found in the tables.
46. C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD. The receiver only outputs this Special Character if K28.5 is received with the wrong running
disparity. The receiver outputs C1.7 if −K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.
47. C2.7 = Transmit Positive K28.5 (+K28.5−) disregarding Current RD. The receiver only outputs this Special Character if K28.5 is received with the wrong running
disparity. The receiver outputs C2.7 if +K28.5 is received with RD−, otherwise K28.5 is decoded as C5.0 or C1.7.
48. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver only outputs this Special Character if the Transmission
Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.
Document #: 38-02097 Rev. *B
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CYV15G0404DXB
Ordering Information
Operating
Range
Speed
Ordering Code
Package Name
Package Type
Standard
Standard
CYV15G0404DXB-BGC
CYV15G0404DXB-BGI
BL256
BL256
256-Ball Thermally Enhanced Ball Grid Array
256-Ball Thermally Enhanced Ball Grid Array
Commercial
Industrial
Package Diagram
256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256
51-85123-*E
Document #: 38-02097 Rev. *B
Page 43 of 44
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CYV15G0404DXB
Document History Page
Document Title: CYV15G0404DXB Independent Clock Quad HOTLink II™ Transceiver with Reclocker
Document Number: 38-02097
ISSUE
DATE
ORIG. OF
CHANGE
REV.
ECN NO.
DESCRIPTION OF CHANGE
**
231494
384307
See ECN
See ECN
BCD
AGT
New Data Sheet
Revised setup and hold times (t
*A
, t
,t
, t
t
,t
TXDH TXDS TREFDH RXDv+, TXCLKOD,
t
, t
, t
, t
, t
, t , t
,t
)
RXDv– RXDv+ TREFDS REFxDV– REFxDV+ RST RISE FALL DJ
*B
1845306
See ECN
UKK/VED
Added clarification for the necessity of JTAG controller reset and the
methods to implement it.
© Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-02097 Rev. *B
Revised December 14, 2007
Page 44 of 44
IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of
Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
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