CY25566
Spread Spectrum Clock Generator
• Center spread modulation
• Low cycle-to cycle jitter
• 16-pin SOIC package
Features
• 25- to 200-MHz operating frequency range
• Wide range of spread selections (9)
• Accepts clock or crystal inputs
• Provides four clocks
Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Printers and MFPs
— SSCLK1a
— SSCLK1b
— SSCLK2
Benefits
— REFOUT
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
• Cost reduction
• Low-power dissipation
—3.3V = 70 mW (typical @ 40 MHz, no load)
Pin Configuration
Block Diagram
REFOFF
2
300K
XIN/CLKIN
REFOFF
REFOUT
VDD
1
2
3
4
5
6
7
8
16 XOUT
15 SSCLK2
14 VSS
13 S0
3
REFOUT
REFERENCE
DIVIDER
Xin/
CLK
1
Loop
Filter
PD
CP
VSS
12 S1
Xout
16
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
S2
11 VSS
10 SSCC
S3
SSCLK1a
9
SSCLK1b
VDD
VSS
4
INPUT
DECODER
LOGIC
DIVIDER
&
MUX
8 SSCLK1a
9 SSCLK1b
15 SSCLK2
5
VDD
VDD
20 K
20 K
11
14
VSS
VSS
/2
RANGE
CONTROL
20 K
VSS
20 K
VSS
6
13
12
S1 S0
7
10
SSCC
S2 S3
Cypress Semiconductor Corporation
Document #: 38-07429 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised October 26, 2005
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CY25566
SSCLK1a/b
Control Logic Structures
SSCLK1a and SSCLK1b are spread spectrum clock outputs
used for the purpose of reducing EMI in digital systems.
SSCLK1a and SSCLK1b can be connected in several different
ways to provide flexibility in application designs. Each clock
can drive separate nets with a capacitative load up to 15 pF
each or connected together to provide drive to a single net with
a capacitative load as high as 33 pF. When both clocks are
connected together, the CY25566 is capable of driving 3.3V
CMOS-compatible clocks to frequencies as high as 200 MHz.
If one clock output is not connected to a load, negligible EMI
will be generated at the unused pin because there is no current
being driven. The frequency and bandwidth of SSCLK1a and
SSCLK1b is programmed by the logic states presented to S2
and S3. The frequency multiplication at SSCLK1a and
SSCLK1b is either 1X or 2X, controlled by S2 and S3. The
modulated output clock SSCLK1 is provided at pins 8 and 9
with each pin having separate but identical drivers. Refer to
Figure 1 below.
The CY25566 has six input control pins for programming VCO
range, BW %, Mod ON/OFF and REFOUT ON/OFF. These
programmable control pins are described below.
REFOFF
The output clock REFOUT can be enabled or disabled by
controlling the state of REFOFF. When REFOFF is at a logic
low(0) state, REFOUT is enabled and the reference clock
frequency is present at pin 3. When REFOFF is at a logic high
state (1), REFOUT is disabled and is set to a logic low state
on pin 3. REFOFF has a 400-KW internal pull-up resistor to
V
.
DD
S0 and S1 (Tri-level Inputs)
S0 and S1 are used to program the frequency range and
bandwidth of the modulated output clocks SSCLK1a/b and
SSCLK2. S0 and S1 of the CY25566 are designed to sense
three different analog levels. With this tri-level structure, the
CY25566 is able to detect 9 different logic states. Refer to
tables 5, 6 and 7 for the results of each of these 9 states. The
level of each state is defined as follows:
9
C Y 2 5 5 6 6
8
Logic State “0” is a voltage that is between 0 and 0.15 × V V.
3 3 p f .
DD
Logic State “M” is a voltage between 0.4 × V and 0.6 × V V.
DD
DD
Logic State “1” is a voltage between 0.85 × V and V
.
DD
DD
Figure 2 illustrates how to program tri-level logic.
9
C Y 2 5 5 6 6
S2 and S3
1 5 p f .
S2 and S3 are used to program the CY25566 into different
frequency ranges and multipliers. The CY25566 operates over
a frequency range of 25 to 200 MHz and a 1X or 2X multipli-
cation of the reference frequency. S2 and S3 are binary logic
8
1 5 p f .
Figure 1. SSCLK1a/b Driver Configurations
SSCLK2
inputs and each has a 400 K W pull-up resistor to V . See
DD
Table 1, Table 2, and Table 3 for programming details.
SSCC
SCLK2 is a Spread Spectrum Clock with a frequency half that
of the SSCLK1a clock frequency. When SSCLK1a is
programmed to provide a 2.5% modulated clock at 1X times
the reference clock, 40 MHz for example, the frequency of
SSCLK2 will be 20 MHz with a BW of 2.5%. Note that by
programming the frequency of SSCLK1a to 2X, the frequency
of SSCLK2 will be 1X times the reference clock frequency.
SSCC is an input control pin that enables or disables SSCG
modulation of the output clock at SSCLK1a/b and SSCLK2.
Disabling modulation is a method of comparing radiated EMI
in a product with SSCG turned on or off.
The CY25566 can be used as a conventional low jitter multiple
output clock when SSCC is set to low (0). SSCC has a 400-KW
internal pull-up resistor. Logic high (1) = Modulation ON, logic
low (0) = Modulation OFF. Default is modulation ON.
VDD
VDD
CY25566
CY25566
CY25566
S0
S0
S0
S1
S0 = "M" (N/C)
13
12
13
13
12
10
S0 = "1"
S1 = "0" (GND)
SSCC = "1"
S0 = "1"
S1
S1
S1 = "0" (GND)
SSCC = "1"
S1 = "1"
12
10
VDD
VDD
10
SSCC = "1"
Figure 2.
Document #: 38-07429 Rev. *B
Page 3 of 9
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CY25566
Modulation Rate
Spread Spectrum clock generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmod.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The CY25566 has three frequency groups to select from. Each
combination of frequency and bandwidth can be selected by
programming the input control lines, S0–S3, to the proper logic
state.
Group 1 is the 1X low-frequency range and operates from 25
to 100 MHz.
Group 2 is the 1X high-frequency range and operates from 50
to 200 MHz.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. The CY25566 utilizes
two different modulation rate dividers, depending on the range
selected on S2 and S3 digital control inputs. Refer to the
example below.
Group 3 is the 2X low frequency range and operates from 25
to 50 MHz and 50 to 100 MHz output.
S3, S2
0,0
CDiv
1166
1166
2332
N/A
Output Frequency
1X
2X
0,1
1,0
1X
1,1
N/A
Example:
Device = CY25566
Fin = 65 MHz
Range = S3 = 0, S2 = 1, S0 = 0
Then: modulation rate = Fmod = 65 MHz/1166 = 55.7 kHz
Spectrum Analyzer
Modulation Profile
Figure 3. SSCG Clock, CY25566, 65 MHz
Document #: 38-07429 Rev. *B
Page 4 of 9
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CY25566
Table 1. Frequency and Bandwidth Selection Chart (Group 1)(Low Frequency (1x) Selection Chart)
25–50 MHz (Low Range)
XIN/CLK
(MHz)
S1 = M
S0 = M
S1 = M
S0 = 0
S1 = 1
S0 = 0
S1 = 0
S0 = 0
S1 = 0
S0 = M
25–35
35–40
40–45
45–50
4.3
3.9
3.7
3.4
3.8
3.5
3.3
3.1
3.4
3.1
2.8
2.6
2.9
2.5
2.4
2.2
2.8
2.4
2.3
2.1
S3
0
S2
0
50–100 MHz (High Range)
XIN/CLK
(MHz)
S1 = 1
S0 = M
S1 = 0
S0 = 1
S1 = 1
S0 = 1
S1 = M
S0 = 1
50–60
60–70
70–80
80–100
2.9
2.8
2.6
2.4
2.1
2.0
1.8
1.7
1.5
1.2
1.4
1.1
S3
0
S2
0
1.3
1.1
1.2
1.0
Table 2. Frequency and Bandwidth Selection Chart (Group 2)(High Frequency (1x) Selection Chart)
50–100 MHz (Low Range)
XIN/CLK
(MHz)
S1 = M
S0 = M
S1 = M
S0 =0
S1 = 1
S0 = 0
S1 = 0
S0 = 0
S1 = 0
S0 = M
50–60
60–70
70–80
80–100
4.2
4.0
3.8
3.5
3.8
3.6
3.4
3.1
3.2
3.1
2.9
2.7
2.8
2.6
2.5
2.2
2.7
2.5
2.4
2.1
S3
1
S2
0
100–200 MHz (High Range)
XIN/CLK
(MHz)
S1 = 1
S0 = M
S1 = 0
S0 = 1
S1 = 1
S0 = 1
S1 = M
S0 = 1
100–120
120–130
130–140
140–150
150–160
160–170
170–180
180–190
190–200
3.0
2.7
2.6
2.6
2.5
2.4
2.4
2.3
2.3
2.4
2.1
2.0
2.0
1.8
1.8
1.8
1.7
1.6
1.6
1.3
1.4
1.1
1.3
1.1
1.3
1.1
1.2
1.0
S3
1
S2
0
1.2
1.0
1.2
1.0
1.1
0.9
1.1
0.9
Table 3. Frequency and Bandwidth Selection Chart (Group 3)(Low Frequency (2x) Selection Chart)
25–50 MHz (Low Range, 2X)
XIN/CLK
(MHz)
SSCLK1
(MHz)
S1 = M
S0 = M
S1 = M
S0 = 0
S1 = 1
S0 = 0
S1 = 0 S1 = 0
S0 = 0 S0 = M
25–35
35–40
40–45
45–50
50-70
70-80
80-90
90-100
4.0
3.8
3.5
3.3
3.5
3.3
3.1
2.9
3.0
2.9
2.7
2.5
2.6
2.4
2.2
2.1
2.5
2.3
2.1
2.0
S3
0
S2
1
Document #: 38-07429 Rev. *B
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CY25566
Application Schematic
In this example, the CY25566 is being driven by a 75-MHz
reference clock.
V
= 3.30 VDC.
DD
SSCLK1a = 75 MHz @ 2.5% center spread modulation.
SSCLK1b = 75 MHz @ 2.5% center spread modulation.
SSCLK 2 = 37.5 MHz @ 2.5% center spread modulation.
REFOUT = 37.5 MHz non-modulated clock.
S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%.
(Refer to Table 1 and 2.)
S2 = 0 and S3 = 1 are programmed to select the Group 2
range.
VDD
0.1 uF
4
75 MHz Clock source
1
VDD
XIN/CLKIN
3
REFOUT
SSCLK2
REFOUT
SSCLK2
SSCLK1a
SSCLK1b
16
XOUT
15
8
CY25566
2
REFOFF
VDD
SSCLK1a
SSCLK1b
10
SSCC
7
S3
S2
S1
6
9
12
13
S0
VSS
VSS
11
VSS
14
5
Figure 4. Application Schematic
Document #: 38-07429 Rev. *B
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CY25566
Absolute Maximum Ratings[1, 2]
Supply Voltage (V : .......................................................+6V
DD
Operating Temperature:......................................0°C to 70°C
Storage Temperature ..................................–65°C to +150°C
Table 4. DC Electrical Characteristics V = 3.3V, Temp. = 25°C, unless otherwise noted
DD
Parameter
Description
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Conditions
Min.
Typ.
Max.
Unit
V
V
±10%
2.97
3.3
3.63
DD
V
V
V
V
V
V
V
S0 and S1 only.
S0 and S1 only.
S0 and S1 only.
0.85V
0.40V
0.0
V
V
DD
V
INH
INM
INL
DD
DD
DD
0.50V
0.0
0.60V
0.15V
V
V
DD
DD
DD
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
I
I
I
I
= 6 ma, SSCLKa
= 20 ma, SSCLKb
= 6 ma, SSCLKa
= 20 ma, SSCLKb
2.4
V
OH1
OH2
OL1
OL2
OH
OH
OH
OH
2.0
V
0.4
1.2
5
V
V
C
C
C
Xin/CLK (Pin 1)
3
6
3
4
8
pF
pF
pF
mA
mA
mA
mA
in1
in2
Input Capacitance
Xout (Pin 8)
10
5
Input Capacitance
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
All input pins except 1.
FIN = 40 MHz,15 pF@all outputs
FIN = 40 MHz, No Load
FIN = 165 MHz,15 pF@all outputs
FIN = 165 MHz, No Load
4
in2
I
I
I
I
27
21
68
48
32
28
80
60
DD1
DD1
DD2
DD2
Table 5. Electrical Timing Characteristics V = 3.3V, T = 25°C and C = 15 pF, unless otherwise noted. Rise/Fall @ 0.4–2.4V,
DD
L
Parameter
Description
Conditions
Min.
25
Typ.
Max
200
1.6
1.6
1.8
1.8
1.7
1.7
1.6
1.6
70
Unit
MHz
ns
I
t
t
t
t
t
t
t
t
Input Clock Frequency Range Non-crystal, 3.0V Pk–Pk ext. source
CLKFR
Clock Rise Time
SSCLK1a or SSCLK1b, Freq = 100 MHz
SSCLK1a or SSCLK1b, Freq = 100 MHz
SSCLK1(a+b), CL = 33 pF, 100 MHz
SSCLK1(a+b), CL = 33 pF, 100 MHz
SSCLK1(a+b), CL = 33 pF, 200 MHz
SSCLK1(a+b), CL = 33 pF, 200 MHz
REFOUT, Pin 3, CL = 15 pF, 50 MHz
REFOUT, Pin 3, CL = 15 pF, 50 MHz
XIN/CLK (Pin)
1.0
1.0
1.2
1.2
1.1
1.1
1.0
1.0
30
1.3
1.3
1.5
1.5
1.4
1.4
1.3
1.3
50
RISE(a)
Clock Fall Time
ns
FALL(a)
Clock Rise Time
ns
RISE(a+b)
FALL(a+b)
RISE(a+b)
FALL(a+b)
RISE(REF)
FALL(REF)
Clock Fall Time
ns
Clock Rise Time
ns
Clock Fall Time
ns
Clock Rise Time
ns
Clock Fall Time
ns
D
D
C
C
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
Refout Frequency Range
%
TYin
TYout
CJ1
SSCLK1a/b (Pin 8 and 9)
45
50
55
%
F = 100 MHz, SSCLK1a/b CL = 33 pF
F = 200 MHz, SSCLK1a/b CL = 33 pF
CL = 15 pF
300
500
400
600
108
ps
ps
CJ2
REFOUT
25
MHz
Note:
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-07429 Rev. *B
Page 7 of 9
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CY25566
Ordering Information
Part Number
CY25566SC
Package Type
Product Flow
Commercial, 0° to 70°C
16-pin SOIC
16-pin SOIC–Tape and Reel
CY25566SCT
Commercial, 0° to 70°C
Package Drawing and Dimensions
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07429 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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CY25566
Document Title:CY25566 Spread Spectrum Clock Generator
Document Number: 38-07429
Issue
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
115771
122705
404070
07/01/02
12/30/02
See ECN
OXC
RBI
New Data Sheet
*A
*B
Added power up requirements to maximum ratings information.
Minor Change: Typo error on table 1, column 2 , S0 = 0 (not M)
RGL
Document #: 38-07429 Rev. *B
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