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COMPACTPCI-824
FEP BLADE INTELLIGENT
I/O CONTROLLER
USER’S MANUAL
The information in this document has been carefully checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, Cyclone Microsystems, Inc. reserves the right to make
changes to any products herein to improve reliability, function, or design. Cyclone Microsystems, Inc. neither
assumes any liability arising out of the application or use of any product or circuit described herein, nor does it
convey any license under its right or the rights of others.
Revision 1.0, January 2006
Cyclone P/N 800-0824
Copyright 2005 by Cyclone Microsystems, Inc.
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CONTENTS
LIST OF FIGURES
Figure 1-1. CPCI-824 Block Diagram ....................................................................................................1-1
Figure 1-2. CPCI-824 Physical Configuration........................................................................................1-4
Figure 2-1. CPCI-824 Memory Map.......................................................................................................2-2
Figure 2-2. LED Register Bitmpa, E800 0001H.....................................................................................2-7
Figure 2-3
Figure 2-4
Geographic Addressing Register, B800 0001h ...................................................................2-8
Power Supply Status Register, E000 0000H.......................................................................2-9
LIST OF TABLES
Table 1-1.
Table 1-2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table A-1.
Table A-2.
Table A-3.
Table A-4.
Table A-5.
Table B-1.
CPCI-824 Power Requirements .........................................................................................1-3
Environmental Specifications ..............................................................................................1-3
SDRAM Configurations .......................................................................................................2-3
External Interrupts ...............................................................................................................2-4
Console Serial Port Connector............................................................................................2-5
Gigabit Port Connector........................................................................................................2-5
10/100 Fast Port Connector ................................................................................................2-6
Breeze Start-up LEDs..........................................................................................................2-8
2
I C Device Addresses .......................................................................................................2-10
JTAG Emulator Pin Assignment........................................................................................2-11
PMC Clock & Arbitration Assignment................................................................................. A-2
PMC Interrupt Assignment ................................................................................................. A-2
P21 PMC Module Connector Pinout................................................................................... A-3
P22 PMC Module Connector Pinout................................................................................... A-4
P23 PMC Module Connector Pinout................................................................................... A-5
CPCI-821 J2 Definition....................................................................................................... B-1
CPCI-824 User;s Manual
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CONTENTS
LIST OF FIGURES
Figure 1-1. CPCI-824 Block Diagram ....................................................................................................1-1
Figure 1-2. CPCI-824 Physical Configuration........................................................................................1-4
Figure 2-1. CPCI-824 Memory Map.......................................................................................................2-2
Figure 2-2. LED Register Bitmpa, E800 0001H.....................................................................................2-7
Figure 2-3
Figure 2-4
Geographic Addressing Register, B800 0001h ...................................................................2-8
Power Supply Status Register, E000 0000H.......................................................................2-9
LIST OF TABLES
Table 1-1.
Table 1-2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table A-1.
Table A-2.
Table A-3.
Table A-4.
Table A-5.
Table B-1.
CPCI-824 Power Requirements .........................................................................................1-3
Environmental Specifications ..............................................................................................1-3
SDRAM Configurations .......................................................................................................2-3
External Interrupts ...............................................................................................................2-4
Console Serial Port Connector............................................................................................2-5
Gigabit Port Connector........................................................................................................2-5
10/100 Fast Port Connector ................................................................................................2-6
Breeze Start-up LEDs..........................................................................................................2-8
2
I C Device Addresses .......................................................................................................2-10
JTAG Emulator Pin Assignment........................................................................................2-11
PMC Clock & Arbitration Assignment................................................................................. A-2
PMC Interrupt Assignment ................................................................................................. A-2
P21 PMC Module Connector Pinout................................................................................... A-3
P22 PMC Module Connector Pinout................................................................................... A-4
P23 PMC Module Connector Pinout................................................................................... A-5
CPCI-821 J2 Definition....................................................................................................... B-1
CPCI-824 User;s Manual
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CHAPTER 1
GENERAL INTRODUCTION
1.1
INTRODUCTION
The CompactPCI-824 is a Hot Swap Intelligent I/O Controller.
The CPCI-824 card is based on the AMCC™ PowerPC™ 440GX, which is AMCC’s next generation
integrated processor based on the PowerPCI 440 core operating at a frequency of 667 MHz. The 440GX
supplies memory controller functions with up to 512 Mbytes of DDR SDRAM (64-bit with ECC) on an
SoDIMM module at 333 MHz DDR. The PowerPC core with 256K L2 cache, the memory controller,
the PCI-X Bridge, and the DMA controller of AMCC 440GX are among the features on the Processor
local bus operating at 128-bit and a frequency of 166 MHz. The 440GX Peripheral Bus (EPC) has three
devices; 8 Mbytes of Flash ROM, software LEDs, and external revision control registers. Additionally,
the 440GX contains four Ethernet MACs. Four Ethernet ports are provided on the CPCI-824. Two are
10/100/1Gb ports configured as RGMII and two are 10/100 Mbps ports and reconfigured as SMII. The
CPCI-824 also utilized one of the I2C bus interface units, and one of the two UART units. A block
diagram of the CPCI-824 is shown on Figure 1-1.
Figure 1-1. CPCI-824 Block Diagram
10/100
Ethernet
Port
10/100/1000
Ethernet Port
10/100/1000
Ethernet Port
10/100
Ethernet Port
PHY
PHY
PHY
DDR SDRAM
333 MHz
Console
Serial
Port
Flash
ROM
AMCC PPC440GX
MHz
JTAG
I/F
Local Bus PCI-X
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GENERAL INTRODUCTION
1.2
FEATURES
•
PowerPC™ Processor
An AMCC 440GX embedded processor based on the AMCC
PowerPC superscalar core. It operates at a maximum frequency of
667 MHz internally.
•
•
SDRAM
Up to 512 MByte of 333 MHz DDR SDRAM is supported via a 200
pin SoDIMM module.
Flash ROM
8 Mbytes of in-circuit sector-programmable Flash ROM provides
non-volatile storage on the CPCI-824. One 128 Kbyte sector of the
Flash ROM is reserved for the storage of non-volatile boot and
system parameters. System calls for storing parameters in this
memory are included in the Breeze Development Environmentª
•
•
Console Serial Port
Ethernet Ports
An asynchronous serial port based on a 16C750 UART with an RS-
232 interface is provided for a console terminal or workstation
connection.
Two 10/100/1Gb Base-TX Ethernet ports are provided. Each port
supports up to 1Gbps and uses a RJ45 style modular phone jack. The
MAC contained within the 440GX interfaces with 2 Broadcom
BMC5461S PHY transceivers.
Two 10/100 Base-TX Ethernet ports. Each supports up to 100 Mbps
and also uses a RJ45 style modular phone jack. In this case the MAC
contained within the 440GX interfaces with a Broadcom BCM5248.
The BCM5248 is an eight port PHY, but we are only using the first 2
ports.
•
•
•
Temperature Sensors
Two LM75 type programmable temperature sensors with interrupt
signaling capability are provided for system monitoring purposes.
I O Messaging
The CPCI-824 supports the I O specification for interprocessor
2
2
communication.
DMA Controller
The 440GX supports 4 separate DMA channels for high throughput
data transfers between PCI bus agents and the local SDRAM
memory.
•
•
•
Breeze Development
Environment™
Flash-resident ROM monitor / firmware package which supports
board-level initialization and application software development.
More information on the Breeze Development Environment™ can
be found in Breeze Developer’s Manual.
Blade Style Interface
Hot Swap
The CPCI-824 receives power, fan detect, power supply status and
geographic addressing from J1 and J2. Note that the fan detect and
power supply status signals are only available when a CPCI-824 is
installed in the system slot.
The CPCI-824 is a Basic Hot Swap board, compliant with PICMG
2.1.
1-2
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GENERAL INTRODUCTION
1.3
SPECIFICATIONS
Physical Characteristics
The CPCI-824 is a single slot, double high CompactPCI™ card with a
peripheral slot interface. This product is equipped with an AMCC
PowerPC 440GX mcroprocessor.
Height
Double Eurocard
Depth
9.187” (233.35mm)
(6U)
6.299” (160mm)
.8” (20.32mm)
Width
Power Requirements
The CPCI-824 requires +5V, +12V, -12V and +3.3V from the
CompactPCI™ backplane J1 connector. The card is Universal and
support either +3.3V or +5V V(I/O).
Table 1-1. CPCI-824 Power Requirements
Voltage
Current Typical
Current Maximum
+3.3V
+5V
3.49 Amps
0.03 Amps
0.01 Amps
0.02 Amps
4.99 Amps
0.04 Amps
0.02 Amps
0.03 Amps
+12V
-12V
1.4
ENVIRONMENTAL
A small amount of airflow will be required, such as is found in a typical Eurocard enclosure.
Table 1-2. Environmental Specifications
Operating Temperatures
0 to 55 Degrees Celsius
Relative Humidity
0-95%
(non-condensing)
Storage Temperatures
-55 to 125 Degrees Celsius
Figure 1-2 is a physical diagram (not to scale) of the CPCI-824 adapter, showing the location
designators of jumpers, connectors, and major ICs. Refer to this figure when component locations are
referenced in the manual text.
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GENERAL INTRODUCTION
Figure 1-2. CPCI-824 Physical Configuration
1-4
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GENERAL INTRODUCTION
1.5
REFERENCE MANUALS
PowerPC 440GX Processor
User’s Manual, Document#
Data Sheet, Document #
Applied Micro Circuits Corporation
6290 Sequence Drive
San Diego, CA 92121
(800) 755-2622
RC28F640J3 Strata Flash Data Sheet
Developer’s Manual, Document #278848
Data Sheet, Document #278821
Intel Corporation
Literature Sales
P.O. Box 7641
16215 Alton Parkway
Irvine, CA 92619-7013
LM75 Digital Temperature Sensor
National Semiconductor
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
(800) 272-9959
CompactPCI™ Specification PICMG 2.0R PCI Industrial Computers Manufacturing Group
3.0
401 Edgewater Place, Suite 500
Wakefield, MA 01880
(781) 224-1100
(781) 224-1239 Fax
PCI Local Bus Specification, Revision 2.2
PCI-X Addendum Rev 1.0
PCI special Interest Group
5440 SW Westgate Dr. Suite #217
Portland, OR 97221
(800) 433-5177 (U.S.)
(503) 222-6190 (International)
(503)222-6190 (Fax)
administration@PCISIG.com
Breeze for XScale 80331 Developer’s Part Number 850-0151
Manual
Cyclone Microsystems Inc.
370 James Street
New Haven, CT 06513
(203) 786-5536
2
2
I 0 Specification, Revision 1.0
I 0 Special Interest Group
(415) 750-8352
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GENERAL INTRODUCTION
JTAG Debugger
Wind River HSI
500 Wind River Way
Alameda, CA 94501
(510) 748-4100
1.6
SOFTWARE DEVELOPMENT
To simplify software development, Cyclone Microsystems has created the Breeze Development
EnvironmentTM. Breeze includes initialization routines, hardware control routines and functions which
provide a simple interface to the PCI bus. Source code for accessing the Breeze Development Environ-
mentTM is included with the CPCI-824, allowing Breeze functions to be incorporated in a real-time
operating system as well.
The Breeze Development EnvironmentTM has been designed to make the development cycle on the
CPIC-713 as simple as possible. Source code provided for Breeze also acts as example code to aid
developers in creatnig their own applications. Breeze is present on all CPCI-824 systems and its
debugging facilities are available during the development cycle.
Breeze for the CPCI-824 has been developed with the aid of the Wind River HSI VisionPROBE
software debugger and VisionCLICK user interface. The VisionPROBE degugger communicates with
a JTAG port on the CPCI-824. It provides the capability to download user code to Flash ROM or
SDRAM. It is recommended that developers obtain a set of these tools or their equivalents to support
application code development.
A complete description of the Breeze Development EnvironmentTM can be found in the “Breeze for
PowerPC 440GX Developer’s Manual”, see Section 1.5, Reference Manuals.
1-6
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HARDWARE
CHAPTER 2
HARDWARE
2.1
AMCC POWERPC 440GX PROCESSOR
The AMCC PowerPC 440GX Embedded Processor is a member of AMCC’s PowerPC 400 family of
microprocessors. The 440GX on the CPCI-824 combines a powerful 667 MHz PowerPC core with
intelligent peripherals and is designed to optimize I/O processing tasks. The 440GX processor consoli-
dates into a single system:
• AMCC PowerPC core.
• 256 Kbyte L2 Cache.
•32 Kbyte Data and Instruction Caches.
•PCI-X interface.
•High-Performance Memory Controller
•Interrupt Controller with 18 external interrupt inputs.
•Four Direct Memory Access (DMA) Controllers.
•Two 10/100/1Gb Ethernet ports with TCP/IP acceleration hardware (TAH)
•Two 10/100Mb Ethernet ports.
•Messaging Unit
•External Bus Control (EBC) interface.
2
•Two I C Bus Interface Units.
• Two 16750 compatible UARTS.
• Thirty two General Purpose Input Output (GXIO) ports.
For detailed descriptions of the 440GX, including programming information, consult the AMCC
PowerPC 440GX User’s Manual.
2.2
BYTE ORDERING
The CPCI-824 is configured to access external devices in big endian mode. The byte ordering determines
which memory location stores the least significant byte of the operand. Big endian stores the most sig-
nificant byte in the lowest address.
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2.3
MEMORY MAP
Figure 2-1 shows the CPCI-824 memory map, as configured by Breeze firmware.
FFFF FFFFh
FLASH ROM
FF80 0000h
UNUSED
F000 0000h
PERIPHERALS
E000 0000h
PCI I/O
Local PCI
Interrupts (Read Only)
D000 0000h
INTERNAL SRAM
E800 0002h
E800 0001h
LED Register
(Write Only)
C000 0000h
PCI Memory
Geographic Address
8000 0000h
6000 0000h
(Read Only)
E800 0001h
E800 0000h
UNUSED
Power Supply Status
(Read Only)
DDR*
SDRAM
NON-CACHEABLE
4000 0000h
2000 0000h
* These are physically the
same locations
UNUSED
DDR*
SDRAM
CACHEABLE
0000 0000h
Figure 2-1. CPCI-824 Memory Map
DDR SDRAM INTERFACE
2.4
The CPCI-824 is equipped with a 200 pin SoDIMM socket formatted to accept +2.5V synchronous
double data rate DRAM (DDR SDRAM) with or without Error Correction Code (ECC). The socket will
accept DDR SDRAM from 64 Mbytes to 1 Gbyte. The SDRAM is accessible from the host PCI bus.
The CPCI-824 uses 72-bit DDR SDRAM with ECC or 64-bit DDR SDRAM without ECC. DDR
SDRAM allows zero data-to-data wait state operation with an effective data transfer rate of 333 MHz.
The CPCI-824 is shipped with unbuffered ECC DDR SDRAM installed in the SoDIMM socket. The
memory may be expanded by inserting up to a 1 GByte module into the 200 pin SoDIMM socket. The
various memory combinations are shown in Table 2-1. Only 200 pin, one or two bank, +2.5V DDR
SDRAM modules with or without ECC rated as PC2700 or faster should be used on the CPCI-824.
2-2
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Table 2-1. SDRAM Configurations
DDR
SDRAM
Technology
DDR SDRAM
Arrangement
#
Total
Memory Size
Row
Column
Banks
128 Mbit
256 Mbit
512 Mbit
16M x 8 bit
1
2
1
2
1
2
1
2
1
2
1
2
12
12
12
12
13
13
13
13
13
13
13
13
10
10
9
128 Mbyte
256 Mbyte
64 Mbyte
128 Mbyte
256 Mbyte
512 Mbyte
128 Mbyte
256 Mbyte
512 Mbyte
1 Gbyte
8M x 16 bit
32M x 8 bit
16M x 16 bit
64M x 8 bit
32M x 16 bit
9
10
10
9
9
11
11
10
10
256 Mbyte
512 Mbyte
2.4.1
Installation and Removal of Memory Modules
Installation or removal of SoDIMM memory on the CPCI-824 is a simple procedure and requires no
special tools. The CPCI-824 should be removed from the host system before changing a memory
module and care must be taken to avoid static discharge while contacting the board. A properly
connected grounding strap should be worn while installing or removing memory modules on the CPCI-
824 adapter.
Memory modules are removed by rotating the latches located on each end of the SoDIMM socket
outward, away from the module. As the latches are moved outward, the module will pop up, partially
out of the socket. Grasp the module by its edges and slide it out of the socket.
To install a memory module, first identify its proper orientation. Each module is keyed with a notch in
the card edge of the circuit board that corresponds to a tab in the socket. With the correct orientation
established, hold the module at an angle to the surface of the CPCI-824 and insert the module into the
card edge receptacle on the socket. When the module is fully inserted (the gold contacts on the module
will not be visible) press down on the high edge of the module until it snaps behind the latches.
2.5
INTERRUPTS
An Interrupt is the action in which the PPC440GX saves its old context (Machine State Register (MSR)
and next instruction address) and begins execution at a pre-determined interrupt-handler address, with a
modified MSR. Exceptions are the events that may cause the processor to take an interrupt, if the corre-
sponding interrupt type is enabled.
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Exceptions may be generated by the execution of instructions, or by signs from devices external to the
PPCI440GX, the internal timer facilities, debug events, or error conditions.
All interuupts, except for Machine Check, can be categorized according to two independent character-
istics of the interrupt. They are asynchronous or synchronous and critical and non-critical.
Asynchronous interrupts are caused by events that are independent of instruction execution. For
asynchronous interrupts, the address reproted to the interrupt handling routine is the address of the
instruction that would have executed next, had the asynchronous interrupt not occurred. Synchronous
interrupts are those that are caused directly by the execution (or attempted execution) of instructions.
Critical interrupt and non-critical interrupts use different save/restore register pairs. Machine check
interrupts are typically caused by some kind of hardware or storage subsystem failure, or by an attempt
to access an invalid address.
2.5.1
External Interrupts
On the CPCI-824, the external interrupts are connected to the PPC440GX as shown in Table 2-2. The
local PCI interrupts are shared. Therefore, to determine which of the four local PCI interrupts caused
the interrupt, a local board register is provided at address E800 0002h.
Table 2-2. External Interrupts
Interrupt
Interrupt Type
Input
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
TEMPERATURE INTERRUPT
FAN 0 INTERRUPT
FAN 1 INTERRUPT
POWER GOOD INTERRUPT
LOCAL PCI BUS INTERRUPT
2.6
CONSOLE SERIAL PORT
The CPCI-824 adapter utilizes the first of the two UART units of the 440GX. The console serial port
with an RS-232 line interfaces has been included on the CPCI-824. The port is connected to a RJ-11
type phone jack on the adapter and can be connected to a host system using the included phone jack to
DB-25 cable (Cyclone P/N 530-2006)
The serial port is capable of operating at speeds from 300 to 115200 bps and can be operated in
interrupt-driven or polled mode. Breeze firmware uses serial settings of 9600 bps, 8 bit data, no parity,
one stop bit, and no flow control. (9600-8N-1). The console serial port connector pin assignment is
shown in Table 2-3.
2-4
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Table 2-3. Console Serial Port Connector
Pin
Signal
Description
1
2
3
4
5
6
N/C
GND
TXD
RXD
N/C
Not Used
Signal Ground
Transmit Data
Receive Data
Not Used
N/C
Not Used
2.7
ETHERNET
The CPCI-824 has two 1 Gigabit Ethernet ports for CAT5 UTP (category 5 unshielded twisted pair).
The CPCI-824 1 Gigabit Ethernet is based on the 10/100/1G Ethernet MAC contained in the 440GX
and the Broadcom BCM5461 Gigabit Transciever (PHY). The interface between the MAC and PHY is
RGMII. The BCM5461 automatically negotiates with its link partner to determine the highest possible
operating speed. The two 10/100 Mbps Ethernet ports interface between the MAC contained within the
440GX and a Broadcom BCM5248 octal 10/100 Mbit PHY. Only two of the BCM5248 ports are used
in an SMII configuration.
2.7.1
Gigabit Ethernet Port
The copper line interface of each Gigabit Ethernet port is a shielded RJ45 (modular phone type)
connector. The connector conforms to the 1000/100/10Base-T specification. The aggregated input and
output ports exit the panel of the CPCI-824.
Note that in 10Base-T and 100Base-T mode, only two pairs are used, one for transmit data and one for
receive data. The pin assignment of copper port 0 (J13) and port 1 (J11) is shown on Table 2-4.
Table 2-4. Gigabit Port Connector
Signal
(10/100Base-T)
Description
(10/100Base-T)
Signal
(1000Base-T)
Description
(1000Base-T)
Pin
11
10
4
TX+
TX-
Output
Output
Input
TRD0+
TRD0-
TRD1+
Input/Output
Input/Output
Input/Output
RX+
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5
3
2
8
9
RX-
Input
TRD1-
TR2+
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Not Used
Not Used
Not Used
Not Used
TRD2-
TRD3+
TRD3-
2.7.2
Gigabit Ethernet Port LEDs
Both of the Gigabit Ethernet prots of the CPCI-824 have LEDs associated with the connector. The ports
have the LEDs built into the RJ45 connectors. The “LNK” LED indicates, when lit, that the port is
LINKed to a functional ethernet network. The “ACT” LED indicates, when lit, that there is ACTivity
of transmit or receive data. Normal operation on a 1000Base-T network would have the “LNK” LED lit
and the “ACT” LED flashing.
2.7.3
Fast Ethernet Port
The copper line interface of each 10/100 Mbit Fast Ethernet port is a shielded RJ45 (modular phone
type) connector. The aggregated input and output ports exit the panel of the CPCI-824.
The pin assignment of Port 0 (J8) and port 1 (J5) is shown on Table 2-5.
Table 2-5. 10/100 Fast Port Connector
Signal
(10/100Base-T)
Description
(10/100Base-T)
Pin
1
2
3
6
TX+
TX-
Output
Output
Input
RX+
RX-
Input
2.7.4
Fast Ethernet Port LEDs
Both of the Fast Ethernet ports of the CPCI-824 have LEDs associated with the connector. The ports
have the LEDs adjacent to the RJ45 connectors. The “LNK” LED indicates, when lit, that the port is
LINKed to a functional ethernet network. The “ACT” LED indicates, when lit, that there is ACTivity
of transmit or receive data. Normal operation on a 10/100 Base-T network would have the “LNK” LED
lit and the “ACT” LED flashing.
2-6
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2.8
PERIPHERAL BUS
The CPCI-824 utilizes the 440GX External Bus Controller (EBC) as a data communication path to the
Flash memory and other peripheral devices such as LEDs and the CPLD for the external register
control. The address/data path is on a programmable 8-bit width bus and operates at high bandwidth.
2.8.1
Flash ROM
The CPCI-824 provides 8 Mbytes of sector-programmable Flash ROM for non-volatile code storage.
The CPCI-824 Flash ROM is an Intel Strataflash J3 type-device, 8 (28F640J3) MBytes in size. The
width of the flash bus is 8 bits.
On the CPCI-824, the Flash ROM is mapped beginning at address FF80 0000h, and is divided into four
separate memory regions by Breeze firmware: boot region, flash file system, free flash, and boot
parameter region. The mapping ensures that, after a reset, the processor can begin execution at the reset,
the processor can begin execution at the reset vector address FFFF FFFCh. The size and start location
of each of these regions is defined by Breeze software. Refer to the Breeze for 440GX Developer’s
Manual for more information.
2.8.2
LEDS
The CPCI-824 front panel has four green LEDs. The four green LEDs labeled IOP, ACT, STAT0, and
STAT1 are under software control. The LEDs are controlled by a write-only register which is located at
address E000 0001H. The LED Register bitmap is shown in Figure 2-2. A given LED is turned ON by
writing a “1” to the appropriate bit in the LED register.
Figure 2-2. LED Register Bitmap, E800 0001H
STAT0
Activity
IOP
STA1
(write only)
(1) LED on
(0) LED off
0
1
2
4
5
6
7
3
Reserved
2.8.3
User LEDs During Initialization
Breeze indicates the progress of its hardware initialization on the user LEDS. In the event that initial-
ization should fail for some reason, the number of lit LEDs can be used to determine the cause of
failure. Table 2-6 lists the tests that correspond to each LED.
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Table 2-6. Breeze Start-up LEDS
TESTS
LED
ACT
ST0
TLBs set. External bus controller set
PCB arbitration priorities set
Interrupt controller set
UART set
ST1
IOP
ACT, ST0
ACT, ST1
ACT, IOP
ST0, ST1
ST0, IOP
ST1, IP
ACT, ST0, ST1
None
System reset check done.
I2C bus set. (first pass)
Board configuration initialized
Board strapping validated
I2C bus set. (second pass)
SDRAM initialized
SDRAM checked and cleared.
Breeze entry
2.8.4
Geographic Addressing
CompactPCI backplanes that support 64-bit connector pin assignments are required to provide a unique
differentiation based upon which physical slot the board has been inserted. The CPCI-824 makes this
definition available to the software. The definition for GA[4:0] is shown in Figure 2.3.
Figure 2-3. Geographic Addressing Register, E800 0001h
GA0
GA1
GA2
GA3
GA4
READ Only
(1) +5V
(0) GND
7
6
5
3
2
1
0
4
2-8
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2.8.5
Power Supply Monitoring
Two circuits are provided for monitoring the health of power supplies. Additional inputs to the
CompactPCI connector define pins for degraded, failed and detected power supplies. The definitions
for the CompactPCI connector J2 is provided in Appendix B. A failed or degraded power supply, as
long as it is detected, will cause an interrupt to the processor. Additionally, the state of the power
supply as defined by POWERGOOD, i.e. the power supply is neither degraded or failed, is displayed in
a green LED. Figure 2-4 shows the bit definition for the power supply status register.
Figure 2-4. Power Supply Status Register, E800 0000H
PS0 Failed
PS1 Failed
PS0 Detected
PS1 Detected
Degraded
0
1
2
3
4
5
6
7
2.9
FAN MONITORING
Two circuits are provided for monitoring of the two fan frequency inputs. As in the case of the power
supply monitoring signals, additional inputs to J2 have been defined for the two fan inputs. Refer to
Appendix B for their pin locations. The fan monitoring circuits will provide an interrupt to the
processor if the frequency of the fan output falls below approximately 8K RPM. Green LEDs are
provided for fan interrupt status. If a fan frequency input causes an interrupt, the corresponding LED is
turned off.
2
2.10
I C BUS
2
The CPCI-824 has five components attached to the Inter-Integrated Circuit (I C) bus interface #0 of the
PPC440GP processor: the DDR SDRAM EEPROM, the two temperature sensors, the reset configu-
2
ration Serial EEPROM, and the DDR SDRAM phase lock loop clock driver. The I C addresses of the
devices are shown in Table 2-7.
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2
Table 2-7. I C Device Addresses
Designator
Device
Function
Address
DDR SDRAM
EEPROM SODIMM
Memory
Configuration
J10
10100011
U13
U1
LM75
LM75
Temperature Sensor
Temperature Sensor
Serial EEPROM
1001000x
1001001x
1010000x
U16
24C08-LV
2.10.1
2.10.2
SDRAM EEPROM
The EEPROM located on the DDR SDRAM module contains identification and configuration infor-
mation. Breeze code will read this information on power-up and will properly configure the
PPC440GX processor to the SDRAM type. No user intervention is required.
Temperature Sensors
The LM75 temperature sensors have overtemperature trip points that will trigger an interrupt when
crossed. The sensors have been placed on the board U1 & U14 and share an interrupt line to the
processor. Polling the two devices will be required to determine which part has triggered the interrupt.
The sensors are placed in interrupt mode by the Breeze initialization code. The default overtemperature
point is 80 degrees Celsius. The sensors can be read for a temperature reading at any time, reading after
an interrupt clears the interrupt. The sensor will not interrupt again until the temperature has dropped
below the hysteresis value (default is 75 degrees Celsius) and risen again passed the trip point. Consult
the LM75 data sheet for more details on programming the temperature sensors.
2.10.3
Serial EEPROM
The first time a CPCI-820 is powered up, initial conditions are read from a serial EEPROM connected
to the I2C bus. The device is read during reset. Initially, the serial EEPROM is disabled and the
processor powers up in a default state. Once the board is programmed and the serial EEPROM is
programmed, then subsequent power ups will use the data stored.
2.10.4
2.11
Phase Lock Loop Clock Driver
The PPC440GX memory controller generates a single differential pair memory clock for the DDR
SDRAM devices. The CDCV850 is a low skew, low jitter, zero delay buffer that distributes the differ-
ential clock to the three input pairs of the 200 pin SoDIMM.
JTAG EMULATOR SUPPORT
The CPCI-824 provides a joint test action group JTAG emulator interface at J27 for XScale compatible
emulators. The JTAG emulator interface connects to the JTAG port of the IOP331 processor and has the
ability to assert a reset to the secondary PCI bus. The JTAG emulator header definition is shown in
Table 2-8
2-10
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Table 2-8. JTAG Emulator Pin Assignment
Signal
TDO
Pin
1
Pin
2
Signal
No Connect
TRST#
TDI
3
4
NO Connect
TCK
5
6
VREF
7
8
No Connect
No Connect
No Connect
No Connect
GND
TMS
9
10
12
12
16
SYS_HALT#
No Connect
No Connect
11
11
15
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APPENDIX A
PMC MODULE INTERFACE
A.1
INTRODUCTION
The PMC Module Interface allows PCI devices to be connected to the Local PCI interface of the CPCI-
824 host. The IEEE STD P1386.1, PCI Mezzanine Card (PMC), provides for one set of clocking and
arbitration signals per PMC Module. Cyclone Microsystems has expanded this to two sets per PMC
Module on the CPCI-824. With ability to connect a PMC module on the CPCI-824, up to two devices
are supported. Otherwise, with a few exceptions, the standard signals defined for 64-bit CPCI
connectors are used for the PMC Modules. The exceptions are noted in Section A.3. The timing for
devices on PMC Modules is the same as the timing for any other PCI device; see the PCI Local Bus
Specification revision 2.2 for details. The CPCI-824 PMC module location is defined as +3.3V
signalling. Note that only +3.3V or universal signalling PMC modules may be used on the CPCI-824.
A number of PMC Modules are available from Cyclone Microsystems. This section is intended for
users interested in developing their own modules.
A.2
A.3
PHYSICAL ATTRIBUTES
Please refer to IEEE P1386/Draft 2.0 for the physical dimensions of PMC modules.
PMC MODULE SIGNAL DEFINITIONS
PMC Modules use the signals defined in the IEEE STD P1386.1. The following four signals are added
to this definition to handle the expansion from one to two devices per PMC module:
•
•
•
•
GNT1#
REQ1#
CLK1
IDSEL1
Please note that the added signals used the PMC-RSVD signals as defined in IEEE STD P1386.1. The
PCI-RSVD remain untouched.
Also, note that GNT1# follows the description for GNT#, REQ1# follows the description for REQ#,
CLK1 follows the description for CLK, and IDSEL1 follows the description for IDSEL. When the
appropriate signals are connected to PCI devices on a PMC Module, each device has the full
complement of PCI signals defined in the specification.
IDSEL signals are not provided. The designer of a PMC Module should connect the proper AD signal to
a device’s IDSEL pin. AD21:16 may be used depending on the desired number mapping scheme. The
suggested signal connections are shown in tables A-1 and A-2.
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Table A-1. PMC Clock & Arbitration Assignment
MODULE
IDSEL
ADDR
IDSEL#
CLOCK
ARBITRATION
PMC 0
PMC 0
IDSEL#
AD17
AD18
J12.25
J12.34
CLKA
CLKB
REQ0#,GNT0#
REQ1#,GNT1#
IDSEL1#
Table A-2. PMC Interrupt Assignment
ST
ND
DEVICE INTx#
1
DEVICE
2
DEVICE
INTA#
INTB#
INTC#
INTD#
INTA#
INTB#
INTC#
INTD#
INTB#
INTC#
INTD#
INTA#
A.4
PMC MODULE CONNECTOR
PMC Modules use three board-to-board connectors (plug) with 64 pins each. The receptacles (i.e. AMP
P/N 120521-2) are located on the host platform and attach to the plugs (i.e. AMP P/N 120527-2). This
connector combination allows for a 10 mm board-to-board spacing. See IEEE P1386/Draft 2.0 for
dimensions and component clearance details.
A-2
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PMC MODULE INTERFACE
Table A-3. P21 PMC Module Connector Pinout
Pin
Signal
Pin
Signal
1
TCK
GND
2
-12V
INTA#
INTC#
+5V
3
4
5
INTB#
BUSMODE1#
INTD#
GND
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PCI-RSVD
PCI-RSVD
GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CLK
GND
GNT#
+5V
REQ#
V(I/O)
AD28
AD31
AD27
GND
AD25
GND
C/BE3#
AD21
+5V
AD22
AD19
V(I/O)
FRAME#
GND
AD17
GND
IRDY#
+5V
DEVSEL#
GND
LOCK#
SBO#
GND
SDONE#
PAR
V(I/O)
AD12
AD15
AD11
+5V
AD09
GND
C/BE0#
AD05
GND
AD06
AD04
V(I/O)
AD02
AD03
AD01
+5V
AD00
GND
REQ64#
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Table A-4. P22 PMC Module Connector Pinout
Pin
Signal
Pin
Signal
1
+12V
TMS
2
TRST#
TDO
3
4
5
TDI
6
GND
7
GND
8
PCI-RSVD
PCI-RSVD
+3.3V
9
PCI-RSVD
BUSMODE2#
RST#
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
BUSMODE3#
BUSMODE4#
GND
+3.3V
PCI-RSVD
AD30
AD29
GND
AD26
AD24
+3.3V
IDSEL
+3.3V
AD23
AD20
AD18
GND
AD16
C/BE2#
PMC+IDSEL1
+3.3V
GND
TRDY#
GND
STOP#
GND
PERR#
+3.3V
SERR#
GND
C/BE1#
AD14
AD13
GND
AD10
AD08
+3.3V
AD07
PMC+REQ1
PMC+CLK1
GND
+3.3V
PMC+GNT1#
PMC-RSVD
GND
PMC-RSVD
PMC-RSVD
+3.3V
ACK64#
GND
PMC-RSVD
A-4
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Table A-5. P23 PMC Module Connector Pinout
Pin
Signal
Pin
Signal
1
PCI-RSVD
GND
2
GND
C/BE7#
C/BE5#
GND
3
4
5
C/BE6#
C/BE4#
V(I/O)
AD63
AD61
GND
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PAR64
AD62
GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
AD60
AD58
GND
AD59
AD57
V(I/O)
AD55
AD55
GND
AD56
AD54
GND
AD52
AD50
GND
AD51
AD49
GND
AD48
AD46
GND
AD47
AD45
V(I/O)
AD43
AD41
GND
AD44
AD42
GND
AD40
AD38
GND
AD39
AD37
GND
AD36
AD34
GND
AD35
AD33
V(I/O)
PCI-RSVD
PCI-RSVD
GND
AD32
PCI-RSVD
GND
PCI-RSVD
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APPENDIX B
CPCI J2 DEFINITION
B.1
INTRODUCTION
The CPCI-824 utilizes some of the reserved pins in J2 for Fan and Power Supply status information.
Differences from the CPCI specification are shown in table B-1.
Table B-1. CPCI-824 J2 Definition
Pin
20
21
C
D
E
FAL1#
FAN1
GND
FAN0
DET0#
DET1#
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