Technical Reference Guide
For
Compaq Evo D300/D500 Personal Computers and
W4000 Workstations
Covers Small Form Factor, Desktop, and Configurable Minitower Models
Featuring the
Intel Pentium 4 Processor and the 845 Chipset
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This document is designed to fit into a standard 3-ring binder. Provided below is a title block that can be
copied and/or cut out and placed into a slip or taped onto the binder.
Evo D300/D500 Personal Computers and
W4000 Workstations
TRG
Featuring the Intel Pentium 4 Processor
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Technical Reference Guide
NOTICE
© 2002 Compaq Information Technologies Group, L.P.
Compaq, the Compaq logo, Deskpro, and Evo are trademarks of the Compaq Information
Technologies Group, L.P. iPAQ is a trademark of Compaq Information Technologies
Group, L.P. in the United States and other countries. Microsoft, MS-DOS, Windows,
Windows NT are trademarks of Microsoft Corporation in the United States and other
countries. Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in
the U. S. and/or other countries. The Open Group, Motif, OSF/1, UNIX, the "X" device,
and IT DialTone are trademarks of The Open Group in the U. S. and other countries.
All other product names mentioned herein may be trademarks of their respective
companies.
Compaq shall not be liable for technical or editorial errors or omissions contained herein.
The information in this document is provided “as is” without warranty of any kind and is
subject to change without notice. The warranties for Compaq products are set forth in the
express limited warranty statements accompanying such products. Nothing herein should
be construed as constituting an additional warranty.
For more information regarding specifications and Compaq-specific parts please contact Compaq
Computer Corporation.
For more information regarding specifications and Compaq-specific parts please contact Compaq
Computer Corporation.
Technical Reference Guide
for
Compaq Evo D300/D500 Personal Computers and W4000 Workstations
First Edition - April 2002
Second Edition – January 2003
Document Part Number 329001-001
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
i
Second Edition - January 2003
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Technical Reference Guide
ii
Compaq Evo and Workstation Personal Computers
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Technical Reference Guide
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION ..................................................................................................................
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
ABOUT THIS GUIDE ................................................................................................................ 1-1
ONLINE VIEWING............................................................................................................ 1-1
HARDCOPY....................................................................................................................... 1-1
ADDITIONAL INFORMATION SOURCES............................................................................. 1-2
MODEL NUMBERING CONVENTION................................................................................... 1-2
SERIAL NUMBER ..................................................................................................................... 1-2
NOTATIONAL CONVENTIONS.............................................................................................. 1-3
VALUES ............................................................................................................................. 1-3
RANGES............................................................................................................................. 1-3
REGISTER NOTATION AND USAGE ............................................................................ 1-3
BIT NOTATION AND BYTE VALUES ........................................................................... 1-3
COMMON ACRONYMS AND ABBREVIATIONS................................................................. 1-4
1.5.1
1.5.2
1.5.3
1.5.4
1.6
CHAPTER 2 SYSTEM OVERVIEW ..........................................................................................................
2.1
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
INTRODUCTION....................................................................................................................... 2-1
FEATURES AND OPTIONS...................................................................................................... 2-2
STANDARD FEATURES .................................................................................................. 2-2
OPTIONS ............................................................................................................................ 2-3
MECHANICAL DESIGN........................................................................................................... 2-4
CABINET LAYOUTS ........................................................................................................ 2-5
CHASSIS LAYOUTS......................................................................................................... 2-7
BOARD LAYOUTS ......................................................................................................... 2-10
SYSTEM ARCHITECTURE .................................................................................................... 2-12
INTEL PENTIUM 4 PROCESSOR.................................................................................. 2-14
CHIPSET........................................................................................................................... 2-15
SUPPORT COMPONENTS.............................................................................................. 2-15
SYSTEM MEMORY ........................................................................................................ 2-16
MASS STORAGE............................................................................................................. 2-16
SERIAL AND PARALLEL INTERFACES..................................................................... 2-16
UNIVERSAL SERIAL BUS INTERFACE...................................................................... 2-16
NETWORK INTERFACE CONTROLLER..................................................................... 2-16
GRAPHICS SUBSYSTEM............................................................................................... 2-17
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10 AUDIO SUBSYSTEM...................................................................................................... 2-18
2.5
SPECIFICATIONS ................................................................................................................... 2-18
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM.............................................................................
3.1
3.2
3.2.1
3.2.2
3.3
3.4
INTRODUCTION....................................................................................................................... 3-1
PENTIUM 4 PROCESSOR......................................................................................................... 3-2
PROCESSOR OVERVIEW................................................................................................ 3-2
PROCESSOR UPGRADING.............................................................................................. 3-4
MEMORY SUBSYSTEM........................................................................................................... 3-5
SUBSYSTEM CONFIGURATION............................................................................................ 3-8
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CHAPTER 4 SYSTEM SUPPORT ..............................................................................................................
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
INTRODUCTION....................................................................................................................... 4-1
PCI BUS OVERVIEW ................................................................................................................ 4-2
PCI BUS TRANSACTIONS............................................................................................... 4-3
PCI BUS MASTER ARBITRATION................................................................................. 4-6
OPTION ROM MAPPING ................................................................................................. 4-7
PCI INTERRUPTS.............................................................................................................. 4-7
PCI POWER MANAGEMENT SUPPORT........................................................................ 4-7
PCI SUB-BUSSES .............................................................................................................. 4-7
PCI CONFIGURATION..................................................................................................... 4-8
PCI CONNECTOR ............................................................................................................. 4-9
AGP BUS OVERVIEW ............................................................................................................ 4-10
BUS TRANSACTIONS.................................................................................................... 4-10
AGP CONFIGURATION ................................................................................................. 4-13
AGP CONNECTOR.......................................................................................................... 4-14
SYSTEM RESOURCES ........................................................................................................... 4-15
INTERRUPTS................................................................................................................... 4-15
DIRECT MEMORY ACCESS.......................................................................................... 4-19
SYSTEM CLOCK DISTRIBUTION ........................................................................................ 4-22
REAL-TIME CLOCK AND CONFIGURATION MEMORY.................................................. 4-23
CLEARING CMOS........................................................................................................... 4-23
CMOS ARCHIVE AND RESTORE................................................................................. 4-24
STANDARD CMOS LOCATIONS ................................................................................. 4-24
SYSTEM MANAGEMENT...................................................................................................... 4-25
SECURITY FUNCTIONS ................................................................................................ 4-25
POWER MANAGEMENT ............................................................................................... 4-27
SYSTEM STATUS ........................................................................................................... 4-27
THERMAL SENSING AND COOLING ......................................................................... 4-28
REGISTER MAP AND MISCELLANEOUS FUNCTIONS.................................................... 4-30
SYSTEM I/O MAP ........................................................................................................... 4-30
LPC47B367 I/O CONTROLLER FUNCTIONS .............................................................. 4-31
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.5
4.6
4.6.1
4.6.2
4.6.3
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.8
4.8.1
4.8.2
CHAPTER 5 INPUT/OUTPUT INTERFACES..........................................................................................
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
INTRODUCTION....................................................................................................................... 5-1
ENHANCED IDE INTERFACE................................................................................................. 5-1
IDE PROGRAMMING....................................................................................................... 5-1
IDE CONNECTOR............................................................................................................. 5-3
DISKETTE DRIVE INTERFACE .............................................................................................. 5-4
DISKETTE DRIVE PROGRAMMING.............................................................................. 5-5
DISKETTE DRIVE CONNECTOR ................................................................................... 5-7
SERIAL INTERFACE ................................................................................................................ 5-8
RS-232 INTERFACE.......................................................................................................... 5-8
COM1 PORT HEADER...................................................................................................... 5-9
SERIAL INTERFACE PROGRAMMING......................................................................... 5-9
PARALLEL INTERFACE........................................................................................................ 5-11
STANDARD PARALLEL PORT MODE........................................................................ 5-11
ENHANCED PARALLEL PORT MODE........................................................................ 5-12
EXTENDED CAPABILITIES PORT MODE.................................................................. 5-12
PARALLEL INTERFACE PROGRAMMING ................................................................ 5-13
PARALLEL INTERFACE CONNECTOR ...................................................................... 5-15
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
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5.6
5.6.1
5.6.2
5.6.3
5.6.4
KEYBOARD/POINTING DEVICE INTERFACE................................................................... 5-16
KEYBOARD INTERFACE OPERATION ...................................................................... 5-16
POINTING DEVICE INTERFACE OPERATION .......................................................... 5-18
KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING .......................... 5-18
KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR ................................. 5-21
UNIVERSAL SERIAL BUS INTERFACE .............................................................................. 5-22
USB DATA FORMATS ................................................................................................... 5-22
USB PROGRAMMING.................................................................................................... 5-24
USB CONNECTOR.......................................................................................................... 5-25
USB CABLE DATA ......................................................................................................... 5-25
AUDIO SUBSYSTEM.............................................................................................................. 5-26
FUNCTIONAL ANALYSIS............................................................................................. 5-26
AC97 AUDIO CONTROLLER ........................................................................................ 5-28
AC97 LINK BUS .............................................................................................................. 5-28
AUDIO CODEC................................................................................................................ 5-29
AUDIO PROGRAMMING............................................................................................... 5-30
AUDIO SPECIFICATIONS ............................................................................................. 5-31
NETWORK INTERFACE CONTROLLER ............................................................................. 5-32
WAKE ON LAN SUPPORT............................................................................................. 5-33
ALERT ON LAN SUPPORT............................................................................................ 5-33
POWER MANAGEMENT SUPPORT............................................................................. 5-34
NIC PROGRAMMING..................................................................................................... 5-35
NIC CONNECTOR........................................................................................................... 5-36
NIC SPECIFICATIONS ................................................................................................... 5-36
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
5.9
5.9.1
5.9.2
5.9.3
5.9.4
5.9.5
5.9.6
CHAPTER 6 POWER SUPPLY AND DISTRIBUTION...........................................................................
6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
INTRODUCTION....................................................................................................................... 6-1
POWER SUPPLY ASSEMBLY/CONTROL ............................................................................. 6-1
POWER SUPPLY ASSEMBLY......................................................................................... 6-2
POWER CONTROL ........................................................................................................... 6-3
POWER DISTRIBUTION .......................................................................................................... 6-5
3.3/5/12 VDC DISTRIBUTION.......................................................................................... 6-5
LOW VOLTAGE PRODUCTION/DISTRIBUTION ........................................................ 6-7
SIGNAL DISTRIBUTION.......................................................................................................... 6-8
CHAPTER 7 BIOS ROM ..............................................................................................................................
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
INTRODUCTION....................................................................................................................... 7-1
ROM FLASHING ....................................................................................................................... 7-2
UPGRADING...................................................................................................................... 7-2
CHANGEABLE SPLASH SCREEN.................................................................................. 7-3
BOOT FUNCTIONS................................................................................................................... 7-4
BOOT DEVICE ORDER.................................................................................................... 7-4
NETWORK BOOT (F12) SUPPORT................................................................................. 7-4
MEMORY DETECTION AND CONFIGURATION ........................................................ 7-5
BOOT ERROR CODES...................................................................................................... 7-5
SETUP UTILITY ........................................................................................................................ 7-4
7.4
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7.5
CLIENT MANAGEMENT FUNCTIONS ................................................................................ 7-12
7.5.1
SYSTEM ID AND ROM TYPE ....................................................................................... 7-14
EDID RETRIEVE ............................................................................................................. 7-14
TEMPERATURE STATUS.............................................................................................. 7-15
DRIVE FAULT PREDICTION ........................................................................................ 7-15
PNP SUPPORT ......................................................................................................................... 7-15
SMBIOS ............................................................................................................................ 7-16
POWER MANAGEMENT FUNCTIONS ................................................................................ 7-17
INDEPENDENT PM SUPPORT...................................................................................... 7-17
ACPI SUPPORT ............................................................................................................... 7-19
APM 1.2 SUPPORT.......................................................................................................... 7-19
USB LEGACY SUPPORT........................................................................................................ 7-23
7.5.2
7.5.3
7.5.4
7.6
7.6.1
7.7
7.7.1
7.7.2
7.7.3
7.8
APPENDIX A ERROR MESSAGES AND CODES...................................................................................
A.1
A.2
A.3
A.4
INTRODUCTION...................................................................................................................... A-1
BEEP/KEYBOARD LED CODES............................................................................................. A-1
POWER-ON SELF TEST (POST) MESSAGES........................................................................ A-2
SYSTEM ERROR MESSAGES (1XX-XX)................................................................................. A-3
MEMORY ERROR MESSAGES (2XX-XX) .......................................................................................... A-4
A.6
A.7
A.8
A.9
KEYBOARD ERROR MESSAGES (30X-XX)........................................................................... A-4
PRINTER ERROR MESSAGES (4XX-XX)................................................................................ A-5
VIDEO (GRAPHICS) ERROR MESSAGES (5XX-XX)............................................................. A-5
DISKETTE DRIVE ERROR MESSAGES (6XX-XX) ................................................................ A-6
A.10 SERIAL INTERFACE ERROR MESSAGES (11XX-XX).......................................................... A-6
A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12XX-XX) ......................................... A-7
A.12 SYSTEM STATUS ERROR MESSAGES (16XX-XX)............................................................... A-8
A.13 HARD DRIVE ERROR MESSAGES (17XX-XX) ...................................................................... A-8
A.14 HARD DRIVE ERROR MESSAGES (19XX-XX) ...................................................................... A-9
A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24XX-XX)........................................................... A-9
A.16 AUDIO ERROR MESSAGES (3206-XX) ................................................................................ A-10
A.17 DVD/CD-ROM ERROR MESSAGES (33XX-XX)................................................................... A-10
A.18 NETWORK INTERFACE ERROR MESSAGES (60XX-XX).................................................. A-10
A.19 SCSI INTERFACE ERROR MESSAGES (65XX-XX, 66XX-XX, 67XX-XX)............................. A-11
A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-XX).................................... A-11
APPENDIX B ASCII CHARACTER SET ..................................................................................................
B.1
INTRODUCTION.......................................................................................................................B-1
APPENDIX C KEYBOARD .........................................................................................................................
C.1
C.2
INTRODUCTION.......................................................................................................................C-1
KEYSTROKE PROCESSING ....................................................................................................C-2
C.2.1
C.2.2
C.2.3
C.2.4
C.2.5
C.2.6
PS/2-TYPE KEYBOARD TRANSMISSIONS ..................................................................C-3
USB-TYPE KEYBOARD TRANSMISSIONS ..................................................................C-4
KEYBOARD LAYOUTS ...................................................................................................C-5
KEYS...................................................................................................................................C-8
KEYBOARD COMMANDS ............................................................................................C-11
SCAN CODES ..................................................................................................................C-11
C.3
CONNECTORS ........................................................................................................................C-16
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APPENDIX D COMPAQ/NVIDIA VANTA LT AGP GRAPHICS CARD.............................................
D.1
D.2
D.3
D.4
D.5
D.6
INTRODUCTION...................................................................................................................... D-1
FUNCTIONAL DESCRIPTION................................................................................................ D-2
DISPLAY MODES .................................................................................................................... D-3
SOFTWARE SUPPORT INFORMATION................................................................................ D-4
POWER MANAGEMENT AND CONSUMPTION ................................................................. D-4
CONNECTORS ......................................................................................................................... D-5
D.6.1
MONITOR CONNECTOR................................................................................................ D-5
APPENDIX E COMPAQ/NVIDIA QUADRO2 EX/MXR AGP GRAPHICS CARDS...........................
E.1
E.2
E.3
E.4
E.5
E.6
INTRODUCTION.......................................................................................................................E-1
FUNCTIONAL DESCRIPTION.................................................................................................E-2
DISPLAY MODES .....................................................................................................................E-3
SOFTWARE SUPPORT INFORMATION.................................................................................E-4
POWER MANAGEMENT AND CONSUMPTION ..................................................................E-4
CONNECTORS ..........................................................................................................................E-5
E.6.1
MONITOR CONNECTOR.................................................................................................E-5
APPENDIX F COMPAQ/MATROX MILLENNIUM G450 AGP GRAPHICS CARD.........................
F.1
F.2
F.3
F.4
F.5
F.6
INTRODUCTION....................................................................................................................... F-1
FUNCTIONAL DESCRIPTION................................................................................................. F-2
DISPLAY MODES ..................................................................................................................... F-3
SOFTWARE SUPPORT INFORMATION................................................................................. F-4
POWER MANAGEMENT AND CONSUMPTION .................................................................. F-4
CONNECTORS .......................................................................................................................... F-5
F.6.1
F.6.2
MONITOR CONNECTOR................................................................................................. F-5
VIDEO FEATURE CONNECTOR .................................................................................... F-6
APPENDIX G COMPAQ/ADAPTEC SCSI HOST ADAPTER ...............................................................
G.1
G.2
G.3
INTRODUCTION...................................................................................................................... G-1
FUNCTIONAL DESCRIPTION................................................................................................ G-2
SCSI ADAPTER PROGRAMMING ......................................................................................... G-3
G.3.1
G.3.2
G.4
G.5
SCSI ADAPTER CONFIGURATION .............................................................................. G-3
SCSI ADAPTER CONTROL ............................................................................................ G-3
SPECIFICATIONS .................................................................................................................... G-3
SCSI CONNECTORS ................................................................................................................ G-4
G.5.1
G.5.2
G.5.3
EXTERNAL 50-PIN ULTRA SCSI CONNECTOR ......................................................... G-4
INTERNAL 50-PIN ULTRA SCSI CONNECTOR .......................................................... G-5
INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR .................................................... G-6
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APPENDIX H COMPAQ/MATROX G200 MMS QUAD-HEAD PCI GRAPHICS CARD..................
H.1
H.2
H.3
H.4
INTRODUCTION...................................................................................................................... H-1
FUNCTIONAL DESCRIPTION................................................................................................ H-2
DISPLAY MODES .................................................................................................................... H-4
DISPLAY CONFIGURATION.................................................................................................. H-5
H.4.1
H.4.2
H.5
H.6
H.7
SINGLE-CARD CONFIGURATION................................................................................ H-5
MULTI-CARD CONFIGURATION WITH WINDOWS NT 4.0.................................... H-5
SOFTWARE SUPPORT INFORMATION................................................................................ H-5
POWER MANAGEMENT AND CONSUMPTION ................................................................. H-6
CONNECTORS ......................................................................................................................... H-7
H.7.1
H.7.2
H.7.3
ADAPTER CABLE CONNECTOR .................................................................................. H-7
ANALOG MONITOR CONNECTOR .............................................................................. H-8
DIGITAL MONITOR CONNECTOR............................................................................... H-9
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LIST OF FIGURES
FIGURE 2–1. COMPAQ EVO PERSONAL COMPUTERS AND WORKSTATIONS................................................. 2-1
FIGURE 2–2. COMPAQ EVO AND WORKSTATIONS, FRONT VIEWS............................................................... 2-5
FIGURE 2–3. COMPAQ DESKPROS, REAR VIEWS ......................................................................................... 2-6
FIGURE 2–4. SMALL FORM FACTOR CHASSIS LAYOUT, TOP VIEW ............................................................. 2-7
FIGURE 2–5. DESKTOP CHASSIS LAYOUT, TOP VIEW ................................................................................. 2-8
FIGURE 2–6. CONFIGURABLE MINITOWER CHASSIS LAYOUT, LEFT SIDE VIEW (MINITOWER
CONFIGURATION).................................................................................................................................. 2-9
FIGURE 2–7. SMALL FORM FACTOR BOARD LAYOUTS ............................................................................ 2-10
FIGURE 2–8. DESKTOP OR CONFIGURABLE MINITOWER MAIN BOARD LAYOUTS.................................... 2-11
FIGURE 2–9. SYSTEM ARCHITECTURE, BLOCK DIAGRAM .......................................................................... 2-13
FIGURE 2–10. PROCESSOR ASSEMBLY AND MOUNTING........................................................................... 2-14
FIGURE 3–1. PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE............................................................... 3-1
FIGURE 3–2. PENTIUM 4 PROCESSOR INTERNAL ARCHITECTURE................................................................ 3-3
FIGURE 3–3. SYSTEM MEMORY MAP.......................................................................................................... 3-7
FIGURE 4-1. PCI BUS DEVICES AND FUNCTIONS ......................................................................................... 4-2
FIGURE 4-2. CONFIGURATION CYCLE ......................................................................................................... 4-4
FIGURE 4-3. PCI CONFIGURATION SPACE MAPPING ................................................................................... 4-5
FIGURE 4-4. PCI BUS CONNECTOR (32-BIT TYPE)...................................................................................... 4-9
FIGURE 4-5. AGP 1X DATA TRANSFER (PEAK TRANSFER RATE: 266 MB/S) ........................................... 4-11
FIGURE 4-6. AGP 2X DATA TRANSFER (PEAK TRANSFER RATE: 532 MB/S) ........................................... 4-12
FIGURE 4-7. AGP 4X DATA TRANSFER (PEAK TRANSFER RATE: 1064 MB/S) ......................................... 4-12
FIGURE 4-8. UNIVERSAL AGP BUS CONNECTOR ...................................................................................... 4-14
FIGURE 4-9. MASKABLE INTERRUPT PROCESSING, BLOCK DIAGRAM....................................................... 4-15
FIGURE 4-10. CONFIGURATION MEMORY MAP......................................................................................... 4-23
FIGURE 4-11. SMALL FORM FACTOR FAN CONTROL BLOCK DIAGRAM..................................................... 4-29
FIGURE 4-12. DESKTOP/CONFIGURABLE MINITOWER FAN CONTROL BLOCK DIAGRAM ........................... 4-29
FIGURE 5-1. 40-PIN PRIMARY IDE CONNECTOR (ON SYSTEM BOARD)........................................................ 5-3
FIGURE 5-2. 34-PIN DISKETTE DRIVE CONNECTOR. ................................................................................... 5-7
FIGURE 5-3. SERIAL INTERFACE CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSIS) .............. 5-8
FIGURE 5-4. COM1 SERIAL INTERFACE HEADER (SMALL FORM FACTOR SYSTEM BOARD ONLY) .............. 5-9
FIGURE 5-5. PARALLEL INTERFACE CONNECTOR (FEMALE DB-25 AS VIEWED FROM REAR OF CHASSIS).. 5-15
FIGURE 5-6. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM.............................. 5-16
FIGURE 5-7. KEYBOARD OR POINTING DEVICE INTERFACE CONNECTOR.................................................. 5-21
FIGURE 5-8. USB I/F, BLOCK DIAGRAM................................................................................................... 5-22
FIGURE 5-9. USB PACKET FORMATS........................................................................................................ 5-23
FIGURE 5-10. UNIVERSAL SERIAL BUS CONNECTOR ................................................................................ 5-25
FIGURE 5-11. AUDIO SUBSYSTEM FUNCTIONAL BLOCK DIAGRAM........................................................... 5-27
FIGURE 5-12. AC’97 LINK BUS PROTOCOL .............................................................................................. 5-28
FIGURE 5-13. AD1885 AUDIO CODEC FUNCTIONAL BLOCK DIAGRAM .................................................... 5-29
FIGURE 5-14. NETWORK INTERFACE CONTROLLER BLOCK DIAGRAM...................................................... 5-32
FIGURE 5-15. ETHERNET TPE CONNECTOR (RJ-45, VIEWED FROM CARD EDGE) ...................................... 5-36
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FIGURE 6–1. POWER DISTRIBUTION AND CONTROL, BLOCK DIAGRAM ...................................................... 6-1
FIGURE 6–2. SMALL FORM FACTOR POWER CABLE DIAGRAM.................................................................... 6-5
FIGURE 6–3. DESKTOP AND CONFIGURABLE MINITOWER POWER CABLE DIAGRAM .................................. 6-6
FIGURE 6–4. LOW VOLTAGE SUPPLY AND DISTRIBUTION DIAGRAM .......................................................... 6-7
FIGURE 6–5. SMALL FORM FACTOR SIGNAL DISTRIBUTION DIAGRAM....................................................... 6-8
FIGURE 6–6. DESKTOP/MINITOWER SIGNAL DISTRIBUTION DIAGRAM....................................................... 6-9
FIGURE 6–7. HEADER PINOUTS................................................................................................................. 6-10
FIGURE B–1. ASCII CHARACTER SET ........................................................................................................B-1
FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM.......................................................C-2
FIGURE C–2. PS/2 KEYBOARD-TO-SYSTEM TRANSMISSION, TIMING DIAGRAM ........................................C-3
FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS ..........................................................C-5
FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS ...............................................................C-5
FIGURE C–5. U.S. ENGLISH WINDOWS (101W-KEY) KEYBOARD KEY POSITIONS .....................................C-6
FIGURE C–6. NATIONAL WINDOWS (102W-KEY) KEYBOARD KEY POSITIONS ..........................................C-6
FIGURE C–7. 7-BUTTON EASY ACCESS KEYBOARD LAYOUT .....................................................................C-7
FIGURE C–8. 8-BUTTON EASY ACCESS KEYBOARD LAYOUT .....................................................................C-7
FIGURE C–9. PS/2 KEYBOARD CABLE CONNECTOR (MALE) ....................................................................C-16
FIGURE C–10. USB KEYBOARD CABLE CONNECTOR (MALE)..................................................................C-16
FIGURE D-1. COMPAQ/NVIDIA VANTA LT AGP GRAPHICS CARD (P/N 192174-002) LAYOUT .............. D-1
FIGURE D-2. COMPAQ/NVIDIA VANTA LT GRAPHICS CARD BLOCK DIAGRAM......................................... D-2
FIGURE D-3. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR). ............................. D-5
FIGURE E-1. COMPAQ/NVIDIA QUADRO2 EX OR MXR AGP GRAPHICS CARD LAYOUT .........................E-1
FIGURE E-2. NVIDIA QUADRO2 EX/MXR GRAPHICS CARD BLOCK DIAGRAM ..........................................E-2
FIGURE E-3. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR)................................E-5
FIGURE F-1. COMPAQ/MATROX MILLENNIUM G450 AGP GRAPHICS CARD LAYOUT (PCA# 202901-001)F-1
FIGURE F-2. MATROX MILLENNIUM G450 GRAPHICS CARD BLOCK DIAGRAM............................................ F-2
FIGURE F-3. VGA MONITOR CONNECTOR, (ONE OF TWO FEMALE DB-15, AS VIEWED FROM REAR)............ F-5
FIGURE F-4. FEATURE CONNECTOR (26-PIN HEADER)................................................................................. F-6
FIGURE G–1. COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER CARD LAYOUT (PCA# 157342-001) .... G-1
FIGURE G–2. COMPAQ/ADAPTEC ULTRA SCSI ADAPTER CARD BLOCK DIAGRAM................................... G-2
FIGURE G–3. EXTERNAL ULTRA SCSI CONNECTOR (50-PIN)...................................................................... G-4
FIGURE G–4. INTERNAL 50-PIN ULTRA SCSI CONNECTOR......................................................................... G-5
FIGURE G–5. ULTRA 160 SCSI CONNECTOR (68-PIN HEADER TYPE) .......................................................... G-6
FIGURE H-1. COMPAQ/MATROX G200 MMS QUAD-HEAD PCI GRAPHICS CARD LAYOUT....................... H-1
FIGURE H-2. MATROX G200 MMS QUAD-HEAD PCI GRAPHICS CARD BLOCK DIAGRAM.......................... H-2
FIGURE H-3. MGA G200 GRAPHICS CONTROLLER ARCHITECTURE ........................................................... H-3
FIGURE H-4. ADAPTER CABLE CONNECTOR, (ONE OF TWO AS VIEWED FROM REAR). ................................. H-7
FIGURE H-5. ANALOG (VGA) MONITOR CONNECTOR (ONE OF TWO FEMALE DB-15 CONNECTORS)......... H-8
FIGURE H-6. DVI-D MONITOR CONNECTOR (24-PIN CONNECTOR)............................................................ H-9
x
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LIST OF TABLES
TABLE 1–1. ACRONYMS AND ABBREVIATIONS........................................................................................... 1-4
TABLE 2-1. FEATURE DIFFERENCE MATRIX ............................................................................................... 2-2
TABLE 2-2. CHIPSET COMPARISON ........................................................................................................... 2-15
TABLE 2-3. SUPPORT COMPONENT FUNCTIONS ........................................................................................ 2-15
TABLE 2-4. STANDARD GRAPHICS SUBSYSTEM COMPARISON.................................................................. 2-17
TABLE 2-5. ENVIRONMENTAL SPECIFICATIONS ........................................................................................ 2-18
TABLE 2-6. ELECTRICAL SPECIFICATIONS ................................................................................................ 2-18
TABLE 2-7. PHYSICAL SPECIFICATIONS .................................................................................................... 2-19
TABLE 2-8. DISKETTE DRIVE SPECIFICATIONS.......................................................................................... 2-19
TABLE 2-9. 48X CD-ROM DRIVE SPECIFICATIONS .................................................................................. 2-20
TABLE 2-10. HARD DRIVE SPECIFICATIONS.............................................................................................. 2-20
TABLE 3–1. SPD ADDRESS MAP (SDRAM DIMM) .................................................................................... 3-6
TABLE 3–2. HOST/PCI BRIDGE CONFIGURATION REGISTERS (GMCH, FUNCTION 0).................................. 3-8
TABLE 4-1. PCI DEVICE CONFIGURATION ACCESS..................................................................................... 4-4
TABLE 4-2. SYSTEM BOARD PCI DEVICE IDENTIFICATION ......................................................................... 4-5
TABLE 4-3. PCI BUS MASTERING DEVICES ................................................................................................ 4-6
TABLE 4-4. LPC BRIDGE CONFIGURATION REGISTERS (ICH2, FUNCTION 0) .............................................. 4-8
TABLE 4-5. PCI BUS CONNECTOR PINOUT ................................................................................................. 4-9
TABLE 4-6. PCI/AGP BRIDGE CONFIGURATION REGISTERS (MCH, FUNCTION 1).................................... 4-13
TABLE 4-7. AGP BUS CONNECTOR PINOUT .............................................................................................. 4-14
TABLE 4-8. MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS......................................................... 4-16
TABLE 4-9. MASKABLE INTERRUPT CONTROL REGISTERS........................................................................ 4-17
TABLE 4-10. DEFAULT DMA CHANNEL ASSIGNMENTS............................................................................ 4-19
TABLE 4-11. DMA PAGE REGISTER ADDRESSES...................................................................................... 4-20
TABLE 4-12. DMA CONTROLLER REGISTERS........................................................................................... 4-21
TABLE 4-13. CLOCK GENERATION AND DISTRIBUTION ............................................................................ 4-22
TABLE 4-14. CONFIGURATION MEMORY (CMOS) MAP ........................................................................... 4-24
TABLE 4-15. SYSTEM BOOT/ROM FLASH STATUS LED INDICATIONS ...................................................... 4-27
TABLE 4-16. SYSTEM OPERATIONAL STATUS LED INDICATIONS.............................................................. 4-28
TABLE 4-17. SYSTEM I/O MAP ................................................................................................................. 4-30
TABLE 4-18 LPC47B367 I/O CONTROLLER REGISTERS............................................................................ 4-31
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS..................................................................................... 5-2
TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS ................................................................................. 5-2
TABLE 5–3. 40-PIN PRIMARY IDE CONNECTOR PINOUT ............................................................................ 5-3
TABLE 5–4. DISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ................................................. 5-5
TABLE 5–5. DISKETTE DRIVE INTERFACE CONTROL REGISTERS ................................................................ 5-5
TABLE 5–6. 34-PIN DISKETTE DRIVE CONNECTOR PINOUT ........................................................................ 5-7
TABLE 5–7. DB-9 SERIAL CONNECTOR PINOUT ......................................................................................... 5-8
TABLE 5–8. SERIAL INTERFACE CONFIGURATION REGISTERS .................................................................... 5-9
TABLE 5–9. SERIAL INTERFACE CONTROL REGISTERS.............................................................................. 5-10
TABLE 5–10. PARALLEL INTERFACE CONFIGURATION REGISTERS ........................................................... 5-13
TABLE 5–11. PARALLEL INTERFACE CONTROL REGISTERS ...................................................................... 5-14
TABLE 5–12. DB-25 PARALLEL CONNECTOR PINOUT .............................................................................. 5-15
TABLE 5–13. 8042-TO-KEYBOARD COMMANDS ...................................................................................... 5-17
TABLE 5–14. KEYBOARD INTERFACE CONFIGURATION REGISTERS.......................................................... 5-18
TABLE 5–15. CPU COMMANDS TO THE 8042........................................................................................... 5-20
TABLE 5–16. KEYBOARD/POINTING DEVICE CONNECTOR PINOUT........................................................... 5-21
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TABLE 5–17. USB INTERFACE CONFIGURATION REGISTERS .................................................................... 5-24
TABLE 5–18. USB CONTROL REGISTERS.................................................................................................. 5-24
TABLE 5–19. USB CONNECTOR PINOUT................................................................................................... 5-25
TABLE 5–20. USB CABLE LENGTH DATA ................................................................................................ 5-25
TABLE 5–21. AC’97 AUDIO CONTROLLER PCI CONFIGURATION REGISTERS........................................... 5-30
TABLE 5–22. AC’97 AUDIO CODEC CONTROL REGISTERS ....................................................................... 5-30
TABLE 5–23. AUDIO SUBSYSTEM SPECIFICATIONS................................................................................... 5-31
TABLE 5–24. AOL EVENTS ...................................................................................................................... 5-33
TABLE 5–25. NIC CONTROLLER PCI CONFIGURATION REGISTERS .......................................................... 5-35
TABLE 5–26. NIC CONTROL REGISTERS................................................................................................... 5-35
TABLE 5–27. 82559 NIC OPERATING SPECIFICATIONS............................................................................. 5-36
TABLE 7–1. BOOT BLOCK CODES ............................................................................................................... 7-2
TABLE 7–2. BOOT ERROR CODES ............................................................................................................... 7-5
TABLE 7–3. SETUP UTILITY FUNCTIONS ..................................................................................................... 7-6
TABLE 7–4. CLIENT MANANGEMENT FUNCTIONS (INT15) ...................................................................... 7-12
TABLE 7–5. PNP BIOS FUNCTIONS .......................................................................................................... 7-15
TABLE 7–6. APM BIOS FUNCTIONS ........................................................................................................ 7-20
TABLE A–1. BEEP/KEYBOARD LED CODES .............................................................................................. A-1
TABLE A–2. POWER-ON SELF TEST (POST) MESSAGES ........................................................................... A-2
TABLE A–3. SYSTEM ERROR MESSAGES ................................................................................................... A-3
TABLE A–4. MEMORY ERROR MESSAGES ................................................................................................. A-4
TABLE A–5. KEYBOARD ERROR MESSAGES .............................................................................................. A-4
TABLE A–6. PRINTER ERROR MESSAGES................................................................................................... A-5
TABLE A–7. VIDEO (GRAPHICS) ERROR MESSAGES .................................................................................. A-5
TABLE A–8. DISKETTE DRIVE ERROR MESSAGES ..................................................................................... A-6
TABLE A–9. SERIAL INTERFACE ERROR MESSAGES .................................................................................. A-6
TABLE A–10. SERIAL INTERFACE ERROR MESSAGES ................................................................................ A-7
TABLE A–11. SYSTEM STATUS ERROR MESSAGES .................................................................................... A-8
TABLE A–12. HARD DRIVE ERROR MESSAGES.......................................................................................... A-8
TABLE A–13. HARD DRIVE ERROR MESSAGES.......................................................................................... A-9
TABLE A–14. VIDEO (GRAPHICS) ERROR MESSAGES ................................................................................ A-9
TABLE A–15. AUDIO ERROR MESSAGES ................................................................................................. A-10
TABLE A–16. DVD/CD-ROM DRIVE ERROR MESSAGES........................................................................ A-10
TABLE A–17. NETWORK INTERFACE ERROR MESSAGES ......................................................................... A-10
TABLE A–18. SCSI INTERFACE ERROR MESSAGES ................................................................................. A-11
TABLE A–19. POINTING DEVICE INTERFACE ERROR MESSAGES ............................................................. A-11
TABLE C–1. KEYBOARD-TO-SYSTEM COMMANDS ...................................................................................C-11
TABLE C–2. KEYBOARD SCAN CODES......................................................................................................C-12
TABLE D-1. NVIDIA VANTA LT 2D GRAPHICS DISPLAY MODES .............................................................. D-3
TABLE D-2. MONITOR POWER MANAGEMENT CONDITIONS ...................................................................... D-4
TABLE D-3. DB-15 MONITOR CONNECTOR PINOUT .................................................................................. D-5
TABLE E-1. NVIDIA QUADRO2 MXR GRAPHICS DISPLAY MODES ............................................................E-3
TABLE E-2. MONITOR POWER MANAGEMENT CONDITIONS .......................................................................E-4
TABLE E-3. DB-15 MONITOR CONNECTOR PINOUT....................................................................................E-5
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TABLE F-1. MATROX MILLENNIUM G450 GRAPHICS DISPLAY MODES........................................................ F-3
TABLE F-2. MONITOR POWER MANAGEMENT CONDITIONS........................................................................ F-4
TABLE F-3. DB-15 MONITOR CONNECTOR PINOUT.................................................................................... F-5
TABLE F-4. VIDEO IN CONNECTOR PINOUT ................................................................................................ F-6
TABLE G-1. SCSI HOST ADAPTER CARD CONTROL REGISTER MAPPING................................................... G-3
TABLE G-2. ULTRA SCSI HOST ADAPTER CARD SPECIFICATIONS.............................................................. G-3
TABLE G-3. EXTERNAL 50-PIN ULTRA SCSI CONNECTOR PINOUT............................................................. G-4
TABLE G-4. INTERNAL 50-PIN ULTRA SCSI CONNECTOR PINOUT.............................................................. G-5
TABLE G-5. ULTRA160 SCSI CONNECTOR PINOUT .................................................................................... G-6
TABLE H-1. MATROX G200 MMS GRAPHICS DISPLAY MODES.................................................................. H-4
TABLE H-2. MONITOR POWER MANAGEMENT CONDITIONS ...................................................................... H-6
TABLE H-3. ADAPTER CABLE CONNECTOR PINOUT .................................................................................. H-7
TABLE H-4. DB-15 MONITOR CONNECTOR PINOUT .................................................................................. H-8
TABLE H-5. VIDEO IN CONNECTOR PINOUT .............................................................................................. H-9
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Technical Reference Guide
Chapter 1
INTRODUCTION
1.1
ABOUT THIS GUIDE
This guide provides technical information about Compaq Evo D300/D500 small form factor,
desktop, and configurable minitower personal computers and W4000 workstations that feature the
Intel Pentium 4 processor. This document describes in detail the system’s design and operation for
programmers, engineers, technicians, and system administrators, as well as end-users wanting
detailed information.
The chapters of this guide primarily describe the hardware and firmware elements and primarily
deal with the system board and the power supply assembly. The appendices contain general data
such as error codes and information about standard peripheral devices such as keyboards, graphics
cards, and communications adapters.
This guide can be used either as an online document or in hardcopy form.
1.1.1 ONLINE VIEWING
Online viewing allows for quick navigating and convenient searching through the document. A
color monitor will also allow the user to view the color shading used to highlight differential data.
A softcopy of the latest edition of this guide is available for downloading in .pdf file format at the
URL listed below:
Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe
Systems, Inc. at the following URL:
When viewing with Adobe Acrobat Reader, click on the (
) icon or "Bookmarks" tab to
display the navigation pane for quick access to particular places in the guide.
1.1.2 HARDCOPY
A hardcopy of this guide may be obtained by printing from the .pdf file. The document is
designed for printing in an 8 ½ x 11-inch format. Note that printing in black and white will lose
color shading properties.
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Chapter 1 Introduction
1.2
ADDITIONAL INFORMATION SOURCES
For more information on components mentioned in this guide refer to the indicated
manufacturers’ documentation, which may be available at the following online sources:
♦
♦
♦
♦
♦
Compaq Computer Corporation: http://www.compaq.com
Standard Microsystems Corporation: http://www.smsc.com
Texas Instruments Inc.: http://www.ti.com
USB user group: http://www.usb.org
1.3
MODEL NUMBERING CONVENTION
The model numbering convention for Compaq systems is as follows:
XXX/XNN/NN/N/NNNx
Removable storage: b = CD/CDRW, c = CD, d = DVD, r = CDRW, z = ZIP
Memory (in MB)
OS type: 2 = Windows 2000, 6 = Dual install, Windows NT 4.0 or 2000,
8 = Windows 98SE, P = Dual install Windows XP Pro/2000
Hard drive size (in GB)
Processor speed (2 digits in GHz)
Processor type: P = Pentium 4
Form factor: S = Small form factor, D = desktop, C = Convertible minitower
Model: D3 = Evo D300, D5 = Evo D500; W4 = Workstation 4000
1.4
SERIAL NUMBER
The unit’s serial number is located on a sticker placed on the exterior cabinet. The serial number
may also be read with the Compaq Diagnostics or Compaq Insight Manager utilities.
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1.5
NOTATIONAL CONVENTIONS
The notational guidelines used in this guide are described in the following subsections.
1.5.1 VALUES
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise
stated.
1.5.2 RANGES
Ranges or limits for a parameter are shown using the following methods:
Example A:
Example B:
Bits <7..4> = bits 7, 6, 5, and 4.
IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9
1.5.3 REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.5.4 BIT NOTATION AND BYTE VALUES
Bit designations are labeled between brackets (i.e., “bit <0 >”). Binary values are shown with the
most significant bit (MSb) on the far left, least significant bit (LSb) at the far right. Byte values in
hexadecimal are also shown with the MSB on the left, LSB on the right.
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Chapter 1 Introduction
1.6
COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation
A
Description
ampere
AC
alternating current
ACPI
A/D
Advanced Configuration and Power Interface
analog-to-digital
ADC
AGP
API
APIC
APM
AOL
Analog-to-digital converter
Accelerated graphics port
application programming interface
Advanced Programmable Interrupt Controller
advanced power management
Alert-On-LAN™
ASIC
AT
ATA
ATAPI
AVI
application-specific integrated circuit
1) attention (modem commands) 2) 286-based PC architecture
AT attachment (IDE protocol)
AT attachment w/packet interface extensions
audio-video interleaved
AVGA
AWG
BAT
Advanced VGA
American Wire Gauge (specification)
Basic assurance test
BCD
binary-coded decimal
BIOS
bis
basic input/output system
second/new revision
BNC
bps or b/s
BSP
Bayonet Neill-Concelman (connector type)
bits per second
Bootstrap processor
BTO
Built to order
CAS
column address strobe
CD
compact disk
CD-ROM
CDS
compact disk read-only memory
compact disk system
CGA
Ch
color graphics adapter
Channel, chapter
cm
centimeter
CMC
CMOS
Cntlr
cache/memory controller
complimentary metal-oxide semiconductor (configuration memory)
controller
Cntrl
control
codec
CPQ
CPU
1. coder/decoder; 2. compressor/decompressor
Compaq
central processing unit
CRIMM
CRT
Continuity (blank) RIMM
cathode ray tube
CSM
Compaq system management / Compaq server management
Continued
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Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
DAC
DC
Description
digital-to-analog converter
direct current
DCH
DDC
DDR
DIMM
DIN
DOS compatibility hole
Display Data Channel
Double data rate (memory)
dual inline memory module
Deutche IndustriNorm (connector type)
dual inline package
DIP
DMA
DMI
dpi
direct memory access
Desktop management interface
dots per inch
DRAM
DRQ
DVI
EDID
EDO
EEPROM
EGA
EIA
EISA
EPP
EIDE
ESCD
EV
ExCA
FIFO
FL
dynamic random access memory
data request
Digital video interface
extended display identification data
extended data out (RAM type)
electrically eraseable PROM
enhanced graphics adapter
Electronic Industry Association
extended ISA
enhanced parallel port
enhanced IDE
Extended System Configuration Data (format)
Environmental Variable (data)
Exchangeable Card Architecture
first in / first out
flag (register)
FM
frequency modulation
fast page mode (RAM type)
Floating point unit (numeric or math coprocessor)
Frames per second
FPM
FPU
FPS
ft
Foot/feet
GB
gigabyte
GMCH
GND
GPIO
GPOC
GART
GUI
Graphics/memory controller hub
ground
general purpose I/O
general purpose open-collector
Graphics address re-mapping table
graphic user interface
hexadecimal
h
HW
hardware
hex
hexadecimal
Hz
ICH
Hertz (cycles-per-second)
I/O controller hub
IDE
IEEE
IF
integrated drive element
Institute of Electrical and Electronic Engineers
interrupt flag
I/F
interface
Continued
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Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
in
inch
INT
interrupt
I/O
input/output
IPL
IrDA
IRQ
initial program loader
InfraRed Data Association
interrupt request
ISA
industry standard architecture
kilobits / kilobytes (x 1024 bits / x 1024 bytes)
kilobits per second
Kb / KB
Kb/s
kg
kilogram
KHz
kV
kilohertz
kilovolt
lb
pound
LAN
LCD
LED
LPC
LSI
LSb / LSB
LUN
m
local area network
liquid crystal display
light-emitting diode
Low pin count
large scale integration
least significant bit / least significant byte
logical unit (SCSI)
Meter
MCH
MMX
MPEG
ms
Memory controller hub
multimedia extensions
Motion Picture Experts Group
millisecond
MSb / MSB
mux
MVA
MVW
n
most significant bit / most significant byte
multiplex
motion video acceleration
motion video window
variable parameter/value
network interface card/controller
nickel-metal hydride
non-maskable interrupt
Non-return-to-zero inverted
nanosecond
NIC
NiMH
NMI
NRZI
ns
NT
nested task flag
NTSC
NVRAM
OS
National Television Standards Committee
non-volatile random access memory
operating system
PAL
PC
1. programmable array logic 2. phase alternating line
Personal computer
PCA
PCI
PCM
PCMCIA
Printed circuit assembly
peripheral component interconnect
pulse code modulation
Personal Computer Memory Card International Association
Continued
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Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
PFC
PIN
PIO
Power factor correction
personal identification number
Programmed I/O
PN
Part number
POST
PROM
PTR
power-on self test
programmable read-only memory
pointer
RAM
RAS
rcvr
random access memory
row address strobe
receiver
RDRAM
RGB
RH
(Direct) Rambus DRAM
red/green/blue (monitor input)
Relative humidity
RMS
root mean square
ROM
RPM
RTC
read-only memory
revolutions per minute
real time clock
R/W
Read/Write
SCSI
SDR
SDRAM
SEC
small computer system interface
Singles data rate (memory)
Synchronous Dynamic RAM
Single Edge-Connector
SECAM
SF
sequential colour avec memoire (sequential color with memory)
sign flag
SGRAM
SIMD
SIMM
SMART
SMI
SMM
SMRAM
SPD
Synchronous Graphics RAM
Single instruction multiple data
single in-line memory module
Self Monitor Analysis Report Technology
system management interrupt
system management mode
system management RAM
serial presence detect
SPDIF
SPN
Sony/Philips Digital Interface (IEC-958 specification)
Spare part number
SPP
standard parallel port
SRAM
SSE
STN
static RAM
Streaming SIMD extensions
super twist pneumatic
SVGA
SW
super VGA
software
Continued
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Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
TAD
TAFI
TCP
TF
telephone answering device
Temperature-sensing And Fan control Integrated circuit
tape carrier package
trap flag
TFT
TIA
TPE
TPI
thin-film transistor
Telecommunications Information Administration
twisted pair ethernet
track per inch
TTL
TV
transistor-transistor logic
television
TX
transmit
UART
UDMA
URL
us / µs
USB
UTP
V
universal asynchronous receiver/transmitter
Ultra DMA
Uniform resource locator
microsecond
Universal Serial Bus
unshielded twisted pair
volt
VAC
VDC
VESA
VGA
VLSI
VRAM
W
Volts alternating current
Volts direct current
Video Electronic Standards Association
video graphics adapter
very large scale integration
Video RAM
watt
WOL
WRAM
ZF
Wake-On-LAN
Windows RAM
zero flag
ZIF
zero insertion force (socket)
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Chapter 2
SYSTEM OVERVIEW
2.1
INTRODUCTION
Compaq Evo Personal Computers and Compaq Workstations (Figure 2-1) deliver an outstanding
combination of manageability, serviceability, and consistency for enterprise environments. Based
on the Intel Pentium 4 processor with the Intel 845 Chipset, these systems emphasize performance
along with industry compatibility. These models feature architectures incorporating the PCI bus.
All models are easily upgradable and expandable to keep pace with the needs of the office
enterprise.
Compaq Evo D500
Desktop
Compaq Evo D500 or Workstation W4000
Small Form Factor
Compaq Workstation W4000
Compaq Evo D300/D500
Configurable Minitower
Configurable Minitower
Figure 2–1. Compaq Evo Personal Computers and Workstations
This chapter includes the following topics:
♦
♦
♦
♦
Features and options (2.2)
Mechanical design (2.3)
System architecture (2.4)
Specifications (2.5)
page 2-2
page 2-4
page 2-8
page 2-13
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Chapter 2 System Overview
2.2
FEATURES AND OPTIONS
This section describes the standard features and available options.
2.2.1 STANDARD FEATURES
The following standard features are included on all models:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Intel Pentium 4 processor in PPGA478 (Socket N) package
Intel 845 Chipset
Support for three PC133 DIMMs (2 DDR DIMMs on select W4000 systems)
3.5 inch, 1.44-MB diskette drive
48x Max CD-ROM drive
IDE controller w/UATA/100 mode support
Hard drive fault prediction
Two serial, two USB, one parallel, and one network interface
APM 1.2 power management support
Plug ’n Play compatible (with ESCD support)
Intelligent Manageability support
Energy Star compliant
Security features including:
•
•
•
•
•
Flash ROM Boot Block
Diskette drive disable, boot disable, write protect
Power-on password
Administrator password
Serial/parallel port disable
♦
♦
PS/2 Compaq Easy-Access keyboard w/Windows support
PS/2 Compaq Scroll Mouse
Table 2-1 shows the differences in features between the Deskpro series’ based on form factor:
Table 2-1.
Feature Difference Matrix (by Form Factor)
Configurable
Small Form Factor
Evo / Workstation
Compaq Proprietary
3
Desktop
Evo
ATX
Minitower
Evo / Workstation
Series
Chassis type
Drive bays
ATX
5
5
Memory
Audio
PC133 SDRAM
Premier Sound
Standard
PC133 SDRAM
Business Audio
Optional
3
Yes/Optional
235 watt
PC133 / PC2100 (DDR) SDRAM
Business Audio
Front panel audio/USB access
# of PCI slots
Smart Cover Sensor/Lock
Power Supply
NOTES:
[1]
5
2
Yes/Optional
175 watt
No/Optional
250 watt
[1] Optional for Evo systems, standard on Workstation systems
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2.2.2 OPTIONS
The following items are available as options for all models and may be included in the standard
configuration of some models:
♦
System Memory:
PC133 or PC266 64-MB DIMM (non-ECC)
PC133 or PC266 128-MB DIMM (non-ECC)
PC133 or PC266 256-MB DIMM (non-ECC)
PC133 or PC266 512-MB DIMM (non-ECC)
♦
♦
Hard drives/controllers: 20-, 40-, or 60-GB UATA/100 hard drive
32-GB Wide Ultra3 SCSI hard drive
Removeable media drives:16x/10x/40x CD-RW drive
10x/40x Max DVD-ROM drive
LS-120 Super Disk drive
PCI DXR DVD Decoder kit
♦
♦
Graphics Monitors:
Compaq P700 17” CRT
Compaq P900 19” CRT
Compaq P1100 21” CRT
Compaq TFT5010 15” Flat Panel
Compaq TFT8020 18” Flat Panel
Other:
Hood (cover) lock assembly
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2.3
MECHANICAL DESIGN
These systems are available in three form factors:
♦
Small Form Factor – a small-footprint desktop designed for environments where both
performance and space are critical issues.
♦
♦
Desktop – a low-profile ATX-type desktop that satisfies standard expandability needs.
Configurable Minitower – an ATX-type unit providing the most expandability and being
adaptable to desktop (horizontal) or floor-standing (vertical) placement.
The following subsections describe the mechanical (physical) aspects of the Compaq Evo models.
CAUTION: Voltages are present within the system unit whenever the unit is plugged
into a live AC outlet, regardless of the system's “Power On” condition. Always
disconnect the power cable from the power outlet and/or from the system unit
before handling the system unit in any way.
!
NOTE: The following information is intended primarily for identification purposes
only. Before servicing these systems refer to the applicable Maintenance And
Service Guide. Service personnel should review training materials also available on
these products.
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2.3.1 CABINET LAYOUTS
2.3.1.1 Front Views
1
2
4
1
2
4
3
5
6
3
6
9
10 11 12
10
8
9
11
7
12
5
7
8
Evo D300/D500 Desktop
Evo or Workstation Small Form Factor
1
1
2
4
6
11
4
6
2
3
11
12
7
3
5
12
7
5
10
8
10
8
9
9
Evo D300/D500
Workstation W4000
Configurable Minitower
(as a Minitower)
Configurable Minitower
(as a Minitower)
Item
1
2
3
4
5
6
7
Description
CD-ROM drive headphone jack
CD-ROM drive volume control
CD-ROM drive activity LED
CD-ROM drive open/close button
1.44-MB diskette drive activity LED
1.44-MB diskette drive eject button
Microphone In Jack
8
Headphone Out Jack
9
Universal Serial Bus Connector
Power LED
Power Button
10
11
12
Hard Drive Activity LED
Figure 2–2. Compaq Evos and Workstations, Front Views
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2.3.1.2 Rear Views
11
12
12
5
11
6
1
2
6
4
5
3
7
9
10
10
1
2
3
4
13
8
8
9
7
Small Form Factor
Desktop
10
12
1
2
3
4
6
5
13
8
9
7
11
Configurable Minitower
(as a Minitower)
Item
Description
Mouse connector
Item
8
9
10
11
12
13
—
Description
1
2
3
4
5
6
7
Audio line input jack
Microphone input jack
AC power connector
VGA monitor connector
AC line voltage selector switch
Audio headphone/line output in jack
—
Keyboard connector
Serial port A connector
Parallel connector
Network interface connector
Serial port B connector
USB connector
Figure 2–3. Compaq Evos and Workstation, Rear Views
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2.3.2 CHASSIS LAYOUTS
This section describes the internal layouts of the chassis. For detailed information on servicing
the chassis refer to the multimedia training CD-ROM and/or the maintenance and service guide
for these systems.
The chassis layout for the Small Form Factor is shown in Figure 2-4. Service features include:
♦
♦
Easily-removable card cage assembly.
Tilting drive bay assembly (for easy access to processor and memory sockets).
PCI Conn. 2 (Slot 2)
PCI Conn. 1 (Slot 1)
Slots On Backplane,
Rear View
Hood Lock Solenoid
(Optional)
Back
Power Supply
Card Cage
Assembly
Speaker Assembly [1]
Lower Drive Bay
System Board
Upper Drive Bays
(Tilting Assembly)
Processor Fan
Front
Figure 2–4. Small Form Factor Chassis Layout, Top View
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Figure 2-5 shows the layout for the Slim Desktop. Service features include:
♦
♦
Tilting upper drive bay assembly (for easy access to all drive bays).
Easy access to expansion slots and all socketed system board components.
Speaker
Auxiliary Chassis Fan
PCI Slot 1
PCI Slot 2
PCI Slot 3
AGP Slot
Hood Lock Solenoid
(Optional)
Back
Power Supply
Air Baffle
Assembly
Smart Cover
Sensor Switch
Upper Drive Bays
(Tilting Assembly)
Lower Drive Bays
Front
Figure 2–5. Desktop Chassis Layout, Top View
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Figure 2-5 shows the layout for the Configurable Minitower in the minitower configuration.
Features include:
♦
♦
Externally accessible drive bay assembly may be configured for minitower (vertical) or
desktop (horizontal) position.
Easy access to expansion slots and all socketed system board components.
Drive Lock
Power Supply
Processor/Heat Sink/Fan
Assembly
Chassis Fan
Externally Accessible
Drive Bays
Hood Lock
Solenoid
(Optional)
Internal
Drive Bays
Back
Front
AGP Slot
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
Speaker
Figure 2–6. Configurable Minitower Chassis Layout, Left Side View (Minitower configuration)
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2.3.3 BOARD LAYOUTS
Figure 2-7 shows the system and riser boards for the small form factor unit.
13
1
2
3
4
5
6
7
8
11
9
10
12
32
31
30
29
28
27
14
15
26
25
24
19
17
22
16
23
21 20
18
System Board PCA# 011466-101
Riser Board SP# 252298-001
Item
1
2
3
4
5
6
7
8
Description
System board
Audio line in jack
Audio line out jack
USB connectors (2)
Serial port A
Network interface connector
Battery
Parallel port
Serial port B
Top: Mouse conn.; Bottom: keyboard conn.
Riser board slot
Riser board
PCI slot connectors (2)
Hood (cover) sensor switch
Processor power connector
Processor socket (mPGA478)
Item
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Description
Processor fan connector
Hard drive activity LED
Power button
Power LED
USB ports (2)
Audio headphones output jack
Audio microphone input jack
CD-ROM audio input connector
Diskette drive connector
Secondary IDE connector
Primary IDE connector
Power supply connector
Internal speaker connector
CMOS clear button
9
10
11
12
13
14
15
16
Hood (cover) lock solenoid connector
DIMM sockets
Figure 2–7. Small Form Factor Board Layouts
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Figure 2-7 shows the system and PCI slot expansion boards. The system board (with three PCI
slots) is common to both the desktop and the configurable minitower units. The PCI slot
expansion board is attached to the system board in the configurable minitower unit to provide a
total of 5 PCI slots.
1
2
3
4
5
6
11 12
7
8
9
10
13
14
15
16
17
18
34
33
19
32
31
30
24 23 22 21 20
System Board
29 28 27 26 25
PCI Slot Expansion Board [1]
SP# 252609-001
PCA# 011345-101 or 011348-101
Item
1
2
3
4
5
6
7
8
Description
PCI slot expansion board [1]
PCI slots
System board
Front panel headphone/microphone conn.
AGP connector
Top: NIC port; Bottom: USB ports (2)
Microphone Input jack
Serial port (B)
Audio line input jack
Audio line output jack
Item
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Description
Processor fan connector
DIMM sockets
Power supply connector
Diskette drive connector
SCSI hard drive LED connector
Power button/Pwr & HD LED connector
Primary IDE hard drive connector
Secondary IDE hard drive connector
CMOS clear button
Hood (cover) sense connector
Front panel USB port connector
Password clear jumper
Chassis speaker connector
CMOS battery
Auxiliary audio connector
CD-ROM audio connector
PCI slot expansion connector
9
10
11
12
13
14
15
16
17
NOTE:
Parallel port
Serial port (A)
Top: Mouse port; bottom: keyboard port
Processor power connector
Processor socket
Chassis fan connector
Hood (cover) lock solenoid connector
] Third DIMM socket present on PC133-type board (PCA# 011345) only.
[1] Used in configurable minitower units only.
Figure 2–8. Desktop or Configurable Minitower Main Board Layouts
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2.4
SYSTEM ARCHITECTURE
The Compaq Evo and Workstation systems covered in this guide feature an architecture based on
the Intel Pentium 4 processor and the Intel 845 chipset (Figure 2-9). These models use either
PC133 or DDR (PC266) SDRAM for system memory, provide AGP 4X graphics support, and
include PCI bus expansion capability.
The Intel 845 chipset includes the 82845 MCH designed to support the Pentium 4 processor with
an FSB speed of 400 MHz. The 82845 MCH also includes an SDRAM controller supporting up to
three PC133 DIMMs or two DDR DIMMs, depending on model configuration.
All systems feature AC’97-compatible audio subsystems and include a microphone input, a line
input and headphone and/or line output. The Small Form Factor system features Compaq Premier
Sound components while Desktop and Configurable Minitower systems provide a business audio
solution.
The 845 chipset also includes the 82801BA I/O Controller Hub (ICH2) that integrates two IDE
controllers with ATA100 support, two USB interfaces, and a PCI bus controller. Also integrated
into the 82801BA is an 82562 network interface controller. An SMC LPC47B367 Super I/O
Controller provides serial, parallel, keyboard, mouse, and diskette drive interface functions.
All models covered in this guide support ATA100-type hard drives. Select Compaq Workstation
W4000 models feature a SCSI PCI adapter controlling a Wide Ultra3 SCSI hard drive.
Below is a matrix defining the architectural differences based on form factor and series.
SFF
Evo/Workstation
SDR
Premier Sound
Standard
Standard
2
Desktop
Evo
SDR
Business
Optional
Optional
3
Configurable Minitower
Series Type
Evo
SDR
Workstation
SDR/DDR
Business
Standard
Standard
5
SDRAM Memory Speed
Audio subsystem type
Front panel audio ports
Front panel USB ports
PCI slots
Business
Optional
Optional
5
Hard Drive Type
ATA100
ATA100
ATA100
ATA100 or SCSI
SDR = Single data rate
DDR = Double data rate
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Pentium 4
Processor
400-MHz FSB
845 Chipset
82845
GMCH
Memory
Bus
Monitor
RGB
AGP 4X
Graphics
Controller
AGP
4X
I/F
SDRAM
Cntlr.
System
Memory
Hub Link
Bus
Pri. IDE
Cntlr.
NIC
IDE
Hard Drive
82801BA
ICH2
Serial
I/F (2)
Parallel
I/F
Sec. IDE
Cntlr.
USB
Cntlr.
LPC
Bus
LPC47B367 I/O Controller
Keyboard/
Mouse I/F
Diskette
I/F
82802
FWH
CD
Audio
Beep
Audio
33-MHz
32-Bit PCI Bus
Audio
Subsystem
AC’97
Link Bus
Power
Supply
Adaptec
29160N
SCSI
Adapter Card
SCSI
Hard Drive
PCI Slots
NOTES:
Select Workstation models only.
Figure 2–9. System Architecture, Block diagram
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2.4.1 INTEL PENTIUM 4 PROCESSOR
The models covered in this guide feature the Intel Pentium 4 processor. This processor is
backward-compatible with software written for the Pentium III, Pentium II, Pentium MMX,
Pentium Pro, Pentium, and x86 microprocessors. The processor architecture includes a floating-
point unit, 32-KB first and 512-KB secondary caches, and enhanced performance for multimedia
applications through the use of multimedia extension (MMX) instructions. Also included are
streaming SIMD extensions (SSE and SSE2) for enhancing 3D graphics and speech processing
performance. The Pentium 4 processor features Net-Burst Architecture that uses hyper-pipelined
technology and a rapid-execution engine that runs at twice the processor's core speed.
These systems employ an mPGA478B zero-insertion-force (ZIF) socket designed for mounting a
“Flip-Chip” (FC-PGA2) processor package (Figure 2-10). Small form factor units use a passive
heat sink held in place over the FC-PGA package with two retaining clips. Desktop and
configurable minitower units use an active assembly (which integrates the heat sink and fan) that
clips on to the processor socket over the FC-PGA package.
Heat Sink
Retaining Clips
Heat Sink / Fan Assembly for
Heat Sink for
Desktop and
Configurable Minitower Units
Small Form Factor Units
FC-PGA2 Package
(w/ Integrated Heat
Spreader)
Lock/Unlock
Handle
(Shown in unlock position)
mPGA478B
Socket
Figure 2–10. Processor Assembly And Mounting
These systems support processors fitted with passive heat sinks or processors fitted with heat
sink/fan assembly with a power cable that attaches to a fan-power header provided on the system
board. There are three types of passive heat sinks.
NOTE: The two types of heat sinks are not interchangeable. Also, these systems support
processors using the FC-PGA2 package only.
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2.4.2 CHIPSET
The Intel 845 chipset consists of a Memory Controller Hub (MCH), an enhanced I/O controller
hub (ICH2), and a firmware hub (FWH). Table 2-2 lists the integrated functions provided by the
chipset.
Table 2-2.
845 Chipset Functions
Component Type
Function
82845 MCH
AGP 4X interface
SDRAM controller supporting PC133 DIMMs or 266-MHz DDR DIMMs [1]
400-MHz FSB
82801BA ICH2
PCI bus I/F
LPC bus I/F
SMBus I/F
IDE I/F with UATA/100 support
AC ’97 controller
RTC/CMOS
IRQ controller
Power management logic
USB controllers #1 and #2 (supporting up to 4 ports)
Network interface controller
Loaded with Compaq BIOS
Random number generator
82802 FWH
NOTE:
[1] Dependent on system board type. System supports one or the other.
2.4.3 SUPPORT COMPONENTS
Input/output functions not provided by the chipset are handled by other support components.
Some of these components also provide “housekeeping” and various other functions as well.
Table 2-3 shows the functions provided by the support components.
Table 2-3.
Support Component Functions
Component Name
Function
LPC47B367 I/O Controller
Keyboard and pointing device I/F
Diskette I/F
Serial I/F (COM1and COM2)
Parallel I/F (LPT1, LPT2, or LPT3)
AGP, PCI reset generation
Interrupt (IRQ) serializer
Power button logic
GPIO ports
AD1885 Audio Codec
Audio mixer
Digital-to-analog converter
Analog-to-digital converter
Analog I/O
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2.4.4 SYSTEM MEMORY
Two memory types are used in these systems:
♦
♦
PC133-based with three DIMM sockets supporting up to 3 gigabytes of SDRAM memory
266-MHz DDR-based with two DIMM sockets supporting up to 2 gigabytes of DDR
memory.
NOTE: The maximum memory amounts stated above are with 1-GB memory modules
using 512 Mb technology DIMMs.
Industry-standard SDRAM DIMMs and DDR266 DIMMs are not interchangable in these
systems.
2.4.5 MASS STORAGE
All models include a 3.5 inch 1.44-MB diskette drive installed as drive A. Most models also
include a CD-ROM and either a 10-, 15-, or 20-GB hard drive. Standard hard drives feature Drive
Protection System (DPS) support. All systems provide two (one primary, one secondary) PCI
bus-mastering Enhanced IDE (EIDE) controllers integrated into the chipset. Each controller
provides UATA/100 support for two drives for a total of four IDE devices, although the form
factor will determine the actual number of drive spaces available.
2.4.6 SERIAL AND PARALLEL INTERFACES
All models include two serial ports and a parallel port accessible at the rear of the chassis. Each
serial port is RS-232-C/16550-compatible and supports standard baud rates up to 115,200 as well
as two high-speed baud rates of 230K and 460K, and utilize DB-9 connectors. The parallel
interface is Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and
supports bi-directional data transfers through a DB-25 connector.
2.4.7 UNIVERSAL SERIAL BUS INTERFACE
All models feature a minimum of two Universal Serial Bus (USB) v1.1 ports that provide a
12Mb/s interface for peripherals. The Compaq Evo desktop and configurable minitower models
may be upgraded to include two additional USB ports on the front panel. All small form factor
and Workstation models include front panel USB ports in the standard configuration. The USB
provides hot plugging/unplugging (Plug ’n Play) functionality.
2.4.8 NETWORK INTERFACE CONTROLLER
All models feature a Network Interface Controller (NIC) integrated on the system board.
Equivalent to the Intel 82562 10/100 NIC, the controller provides automatic selection of 10BASE-
T or 100BASE-TX operation with a local area network and includes power-down, wake-up, and
Alert-On-LAN features. An RJ-45 connector is provided on the rear panel.
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2.4.9 GRAPHICS SUBSYSTEM
The 82845 MCH component includes an AGP 4X interface that supports an AGP graphics
controller installed in the AGP slot. The AGP slot includes both Type 1 and Type 2 retention
mechanisms. Dual-monitor support is possible by adding a PCI graphics card to the standard
configuration. Table 2-4 lists the key features of the standard graphics subsystems employed in
these systems:
Table 2-4.
Standard AGP Graphics Comparison
Matrox
nVIDIA
Vanta
nVIDIA
Quadro2 EX/MXR
Millennium
G450 Dual-Head
Matrox
G200 MMS
Std. Config. In
Recommended
for:
Evo
Hi 2D,
Wkstn. W4000
Hi 2D,
Evo
Hi 2D,
Entry 3D
AGP 4X
16 / 32 MB
SDRAM
360 MHz (Pri)
200 MHz (Sec)
2048x768
Wkstn. W4000
Multi-monitor
Hi 2D
Entry 3D
AGP 4X
16 MB
SGRAM
300 MHz
Entry 3D
AGP 4X
32 MB
SDRAM
350 MHz
Bus Type
PCI
Mem. Amount
Mem. Type
DAC Speed
8 MB x 4
SGRAM
250 MHz
Max. 2D Res.
1920x1200
1920x1200
1920x1200
(analog mon.)
Quick Draw,
DCI/DirectX,
Direct Draw,
MPEG 1/2,
OpenGL,
Software
Compatibility
Quick Draw,
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
Quick Draw,
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
Quick Draw,
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
Direct 3D
Aux. I/O
Outputs
NOTES:
VESA I/F
1 RGB
VESA I/F
1 RGB, 1 DVI [1]
VESA I/F
2 RGB
VESA I/F
4 RGB/4DVI [2]
[1] DVI connector on MXR card only.
[2] Supports up to four monitors.
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2.4.10 AUDIO SUBSYSTEM
These systems use the integrated AC97 audio controller of the 845 chipset and an AC’97-
compliant audio codec. These systems include microphone and line inputs and headphone and line
outputs. The Desktop and Configurable Minitower models include a 3-watt output amplifier
driving an internal speaker. The Small Form Factor models feature Compaq Premier Sound
consisting of a five-level equalizer designed to compensate for chassis acoustics and a low-
distortion 5-watt amplifier driving a speaker for optimum sound. Small form factor and all
Workstation models front panel-accessible audio jacks as standard while Evo desktop and
configurable minitower models may be upgraded to include front panel audio jacks.
2.5
SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq
Evo and Worksstation Personal Computers. Where provided, metric statistics are given in
parenthesis. All specifications subject to change without notice.
Table 2-5.
Environmental Specifications (Factory Configuration)
Parameter
Ambient Air Temperature
Operating
Nonoperating
50o to 95o F (10o to 35o C, max. rate
of change < 10°C/Hr)
5 Gs [1]
-24o to 140o F (-30o to 60o C, max. rate
of change < 20°C/Hr )
20 Gs [1]
Shock (w/o damage)
Vibration
Humidity
0.000215 G2/Hz, 10-300 Hz
10-90% Rh @ 28o C max.
wet bulb temperature
10,000 ft (3048 m) [2]
0.0005 G2/Hz, 10-500 Hz
5-95% Rh @ 38.7o C max.
wet bulb temperature
Maximum Altitude
NOTE:
30,000 ft (9,144 m) [2]
[1] Peak input acceleration during an 11 ms half-sine shock pulse.
[2] Maximum rate of change: 1500 ft/min.
Table 2-6.
Electrical Specifications
Parameter
U.S.
International
Input Line Voltage:
Nominal:
Maximum:
100 - 127 VAC
90 - 132 VAC
200 - 240 VAC
180 - 264 VAC
Input Line Frequency Range:
Nominal:
Maximum:
50 - 60 Hz
47 - 63 Hz
50 - 60 Hz
47 - 63 Hz
Power Supply:
Maximum Continuous Power
Small Form Factor
Desktop
Configurable Minitower
Maximum Line Current Draw
Small Form Factor
Desktop
175 watts
235 watts
250 watts
175 watts
235 watts
250 watts
2.7 A @ 100 VAC
3.6 A @ 100 VAC
3.6 A @ 100 VAC
2.7 A @ 100 VAC
3.6 A @ 100 VAC
3.6 A @ 100 VAC
Configurable Minitower
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Table 2-7.
Physical Specifications
Small
Configurable
Parameter
Height
Width
Depth
Weight (nom.) [1]
Maximum Supported Weight [2]
NOTES:
Form Factor
Desktop
5.72 in (14.5 cm)
15.25 in (38.7 cm)
17.90 in (45.5 cm)
26 lb (12 kg)
Minitower [3]
17.65 in (44.8 cm)
6.60 in (16.8 cm)
16.80 in (42.7 cm)
26 lb (12 kg)
3.9 in (9.90 cm)
13.1 in (33.3 cm)
14.4 in (36.6 cm)
20 lb (9.1 kg)
100 lb (45.5 kg)
100 lb (45.5 kg)
100 lb (45.5 kg)
[1] System weight may vary depending on installed drives/peripherals.
[2] Assumes reasonable article(s) such as a display monitor and/or another system unit.
[3] Minitower configuration. For desktop configuration, swap Height and Width dimensions.
Table 2-8.
Diskette Drive Specifications
(Compaq SP# 179161-001)
Parameter
Media Type
Height
Measurement
3.5 in 1.44 MB/720 KB diskette
1/3 bay (1 in)
Bytes per Sector
Sectors per Track:
High Density
512
18
9
Low Density
Tracks per Side:
High Density
Low Density
Read/Write Heads
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
80
80
2
3 ms/6 ms
94 ms/173ms
15 ms
Latency Average
100 ms
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Table 2-9.
Optical Drive Specifications
Parameter
48x CD-ROM
16/10/40x CD-RW Drive
Interface Type
Media Type (reading)
IDE
IDE
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
N/a
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
CD-R, CD-RW
Media Type (writing)
Transfer Rate (Reads)
4.8 Kb/s (max sustained)
CD-ROM, 4.8 Kb/s;
CD-ROM/CD-R, 1.5-6 Kb/s
CD-R, 2.4 Kbps (sustained);
CD-RW, 1.5 Kbps (sustained);
650 MB @ 12 cm
Transfer Rate (Writes):
N/a
Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm
Center Hole Diameter
Disc Diameter
Disc Thickness
Track Pitch
550 MB
640 MB
180 MB
15 mm
8/12 cm
1.2 mm
1.6 um
15 mm
8/12 cm
1.2 mm
1.6 um
Laser
Beam Divergence
Output Power
Type
53.5 + 1.5°
53.6 0.14 mW
GaAs
53.5 +/- 1.5 °
53.6 0.14 mW
GaAs
Wave Length
790 +/- 25 nm
790 +/- 25 nm
Average Access Time:
Random
Full Stroke
Audio Output Level
Cache Buffer
<100 ms
<150 ms
0.7 Vrms
128 KB
<120 ms
<200 ms
0.7 Vrms
128 KB
Table 2-10.
Hard Drive Specifications
Parameter
Drive Size
Interface
Transfer Rate
Drive Protection System Support?
20.0 GB
3.5”
UATA/100
100 MBps
Yes
32.0 GB
3.5"
Ultra3 SCSI
160 MBps
Yes
40.0 GB
3.5”
UATA/100
100 MBps
Yes
60.0 GB
3.5”
UATA/100
100 MBps
Yes
Typical Seek Time (w/settling) [1]
Single Track
Average
1.2 ms
8.0 ms
0.6 ms
4.7 ms
1.2 ms
8.0 ms
1.0 ms
9.0 ms
Full Stroke
18 ms
12 ms
18 ms
20 ms
Disk Format (logical blocks)
Rotation Speed
Drive Fault Prediction
39,102,336
7200 RPM
SMART III
71,132,000
10,000 RPM
N/a
78,165,360
7200 RPM
SMART III
78,165,360
7200 RPM
SMART III
NOTE:
Actual times may vary depending on specific drive installed.
All ATA drives are Quiet Drives.
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Technical Reference Guide
Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.1
INTRODUCTION
This chapter describes the processor/memory subsystem of Compaq Deskpro Personal Computers
featuring the Pentium 4 processor. These systems feature the Pentium 4 processor and the 845
chipset (Figure 3-1). The 82845 MCH component of the 845 chipset supports SDRAM memory
of either the standard PC133 or the DDR type, depending on model.
Pentium 4
Processor
400-MHz
64-Bit FSB
Cntl
System Memory
XMM2
XMM3
XMM1
FSB I/F
Mem. Bus
DIMM
Socket
DIMM
Socket
DIMM
In
Socket
Memory
Cntlr.
82845
MCH
AGP
I/F
Hub I/F
Present in PC133 systems only.
Covered in Chapter 4
Figure 3–1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
♦
♦
♦
Pentium 4 processor [3.2]
Memory subsystem [3.3]
Subsystem configuration {3.4]
page 3-2
page 3-5
page 3-8
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Chapter 3 Processor/Memory Subsystem
3.2
PENTIUM 4 PROCESSOR
These systems each feature an Intel Pentium 4 processor in a FC-PGA478 package mounted with
a passive heat sink in a mPGA478B zero-insertion force socket. The mounting socket allows the
processor to be easily changed for servicing and/or upgrading.
3.2.1 PROCESSOR OVERVIEW
The Intel Pentium 4 processor represents the latest generation of Intel’s IA32-class of processors.
Featuring Intel’s NetBurst architecture, the Pentium 4 processor is designed for intensive
multimedia and internet applications of today and the future while maintaining compatibility with
software written for earlier (Pentium III, Pentium II, Pentium, Celeron, and x86) microprocessors.
Key features of the Pentium 4 processor include:
♦
♦
Hyper-Pipelined Technology – The main processing loop has twice the depth (20 stages) of
the Pentium III allowing for increased processing frequencies.
Execution Trace Cache – A new feature supporting the branch prediction mechanism, the
trace cache stores translated sequences of branching micro-operations (µops) and is checked
when suspected re-occurring branches are detected in the main processing loop. This feature
allows instruction decoding to be removed from the main processing loop.
Rapid Execution Engine – Arithmetic Logic Units (ALUs) run at twice (2x) processing
frequency for higher throughput and reduced latency.
256-KB Advanced transfer L2 cache – Using 32-byte-wide interface at processing speed, the
L2 cache can provide 48 GB/s performance (3x over the Pentium III)
Advanced dynamic execution – Using a larger (4K) branch target buffer and improved
prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the
Pentium III.
♦
♦
♦
♦
♦
Enhanced Floating Point Processor - With 128-bit integer processing and deeper pipelining
the Pentium 4’s FPU provides a 2x performance boost over the Pentium III.
Additional Streaming SIMD extensions (SSE2) – In addition to the SSE support provided by
previous Pentium processors, the Pentium 4 processor includes an additional 144 MMX
instructions, further enhancing:
•
•
•
•
•
Streaming video/audio processing
Photo/video editing
Speech recognition
3D processing
Encryption processing
♦
Quad-pumped Front Side Bus (FSB) – The FSB uses a 100-MHz clock for qualifying the
buses’ control signals. However, address information is transferred using a 200-MHz strobe
while data is transferred with a 400-MHz strobe, providing a maximum data transfer rate of
3.2 GB/s. This is a boost of over three times that of a Pentium III with a 133-MHz FSB.
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Figure 3-1 illustrates the internal architecture of the Pentium 4 processor.
Pentium 4 Processor
Execution
Branch
Prediction
256-KB
8-Way
L2
128-bit
Trace Cache
Integer
FPU
L1
Data
Cache
CPU
Adv.
Transfer
Cache
Rapid Exe. Eng.
ALUs
Out-of-
Order Core
FSB
I/F
ALU Speed: Core speed x2
Core Speed: 1.4, 1.5, 2.0, 2.2 GHz
FSB Speed: 400 MHz (effective data transfer rate)
Figure 3–2. Pentium 4 Processor Internal Architecture
The Pentium 4 increases processing speed with higher clock speeds made possible with hyper-
pipelined technology that can handle significantly more instructions at a time. Since branch mis-
predicts would result in serious performance hits with such a long pipeline, the Pentium 4 features
a branch prediction mechanism improved with the addition of an execution trace cache and a
refined prediction algorithm. The execution trace cache can store 12k micro-ops (decoded
instructions dealing with branching sequences) that are checked when re-occurring branches are
processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the
case in the Pentium III.
The out-of-order core features Advanced Dynamic Execution, which provides a large window
(126 instructions) for execution units to work with. A more accurate branch prediction algorithm,
along with a larger (4-KB) branch target buffer that stores more details on branch history results
in a 33% reduction in branch mis-predictions over the Pentium III.
The L1 data cache features a low-latency design for minimum response to cache hits. The 256-KB
advanced transfer L2 cache features a 256-bit (32-byte) interface operating at processing speed.
The L2 cache of the 1.5 GHz Pentium 4 can therefore provide a transfer rate of 48 GB/s.
The combined improvements of the Pentium 4’s CPU core the rapid execution engine’s ALUs to
operate at twice the processing frequency to handle the steady stream of instructions.
The front side bus (FSB) of the Pentium 4 uses a 100-MHz clock but provides bi- and quad-
pumped transfers through the use of 200- and 400-MHz strobes. The Pentium 4 can transfer a
complete 64-byte cache line in two 100-MHz bus cycles for a throughput rate of 3.2 GB/s.
Address information is transferred at a 200-MHz rate.
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Chapter 3 Processor/Memory Subsystem
The Pentium 4 processor is software-compatible with Celeron, Pentium II, Pentium MMX,
Pentium, and x86 processors, but will require the latest versions of operating system software to
take advantage of the Streaming SIMD extensions (SSE2).
3.2.2 PROCESSOR UPGRADING
All units use mPGA478B ZIF mounting socket and ship with the Pentium 4 processor in a Flip-
Chip (FC-PGA478) package installed with a passive heat sink. The FC-PGA478 package consists
of the processor die mounted “upside down” on a PC board. This arrangement allows the heat
sink to come in direct contact with the processor die. The heat sink and attachment clip are
specially designed provide maximum heat transfer from the processor component.
CAUTION: Attachment of the heat sink to the processor is critical on these systems.
Improper attachment of the heat sink will likely result in a thermal condition.
Although the system is designed to detect thermal conditions and automatically shut
down, such a condition could still result in damage to the processor component. Refer to
the applicable Maintenance and Service Guide for processor installation instructions.
!
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3.3
MEMORY SUBSYSTEM
These systems support one of two types of memory: single data rate (SDR) SDRAM or double
data rate (DDR) SDRAM. The system board determines the type of memory supported:
♦
♦
SDR SDRAM-based system board: Three 168-pin DIMM sockets that accept PC100 or
PC133 (PC133 supplied) DIMMs.
DDR SDRAM-based system board: Two 184-pin DIMM sockets that accept PC1600 or
PC2100 (PC2100 supplied) DIMMs.
NOTE: The two memory types are not interchangeable within a system. The system
board determines memory type.
NOTE: The SDR SDRAM "PCxxx" reference designates bus speed (i.e, a PC133
DIMM is designed for 133 MHz operation). The DDR SDRAM "PCxxxx" reference
designates bus bandwidth (i.e., a PC2100 DIMM can, operating at a 266-MHz effective
speed, provide a throughput of 2100 MBps (8 bytes × 266 MHz)).
These systems accept DIMMs with the following parameters:
♦
♦
♦
Unbuffered, compatible with SPD rev. 1.0
32-, 64-, 128-, 256-, and 512-Mb memory technology
Single or double-sided
NOTE: Systems that support DDR SDRAM accept either ECC or non-ECC DIMMs,
but not both.
The SPD format supported by these systems complies with the JEDEC specification for 128-byte
EEPROMs. This system also provides support for 256-byte EEPROMs to include additional
Compaq-added features such as part number and serial number. The SPD format as supported in
this system (SPD rev. 1) is shown in Table 3-3.
The key SPD bytes that BIOS checks for compatibility are 2, 9, 10, 18, 23, 24, and 126. If BIOS
detects EDO or ECC DIMMs a “memory incompatible” message will be displayed and the
system will halt. This system is designed for using non-ECC DIMMs only. Refer to chapter 8
for a description of the BIOS procedure of interrogating DIMMs.
An installed mix of DIMM types (PC100 and PC133, CL 2 and CL 3) is acceptable but operation
will be constrained to the level of the DIMM with the lowest performance specification.
If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time during
POST and an error message may or may not be displayed before the system hangs.
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Chapter 3 Processor/Memory Subsystem
The SPD address map is shown below.
Table 3-3.
SPD Address Map (SDRAM DIMM)
Byte
Description
Notes
Byte
Description
Notes
0
No. of Bytes Written Into EEPROM
[1]
25
Min. CLK Cycle Time at
CL X-2
[7]
1
Total Bytes (#) In EEPROM
[2]
[3]
26
Max. Acc. Time From
CLK @ CL X-2
Min. Row Prechge. Time
Min. Row Active to Delay
Min. RAS to CAS Delay
Reserved
[7]
2
3
4
5
6, 7
8
Memory Type
27
28
29
30, 31
32..61
62
63
64-71
72
73-90
91, 92
93, 94
95-98
99-125
126
[7]
[7]
[7]
No. of Row Addresses On DIMM
No. of Column Addresses On DIMM
No. of Module Banks On DIMM
Data Width of Module
Voltage Interface Standard of DIMM
Cycletime @ Max CAS Latency (CL)
Access From Clock
Config. Type (Parity, Nonparity, etc.)
Refresh Rate/Type
Width, Primary DRAM
Error Checking Data Width
Min. Clock Delay
Burst Lengths Supported
No. of Banks For Each Mem. Device
CAS Latencies Supported
CS# Latency
Superset Data
SPD Revision
[7]
[7]
9
[4]
[4]
Checksum Bytes 0-62
JEP-106E ID Code
DIMM OEM Location
OEM’s Part Number
OEM’s Rev. Code
Manufacture Date
OEM’s Assembly S/N
OEM Specific Data
Intel frequency check
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NOTES:
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[4] [5]
[6]
[4]
[4]
[4]
[4]
127
128-131 Compaq header “CPQ1”
132 Header checksum
133-145 Unit serial number
146
147
[9]
[9]
[9] [10]
[9] [11]
[9]
Write Latency
DIMM Attributes
Memory Device Attributes
Min. CLK Cycle Time at CL X-1
Max. Acc. Time From CLK @ CL X-1
DIMM ID
Checksum
Reserved
[7]
[7]
[9]
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] Compaq usage. This system requires that the DIMM EEPROM have this
space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is
invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system
Tampering.
[11] Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to
note [10]).
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Figure 3-4 shows the system memory map.
4 GB
FFFF FFFFh
FFE0 0000h
High BIOS Area
(2 MB)
FFDF FFFFh
PCI Memory
(18 MB)
FEC1 0000h
FEC0 FFFFh
APIC Config. Space
(64 KB)
FEC0 0000h
FEBF FFFFh
Host,
PCI, AGP Area
PCI Memory
Expansion
(3060 MB)
2000 0000h
1FFF FFFFh
512 MB
Host/PCI Memory
Expansion
(496 MB)
0100 0000h
00FF FFFFh
16 MB
1 MB
Host, PCI,
ISA Area
Extended Memory
(15 MB)
0010 0000h
000F FFFFh
System BIOS Area
(64 KB)
000F 0000h
000E FFFFh
Extended BIOS
Area
000E 0000h
000D FFFFh
Option ROM
(128 KB)
000C 0000h
000B FFFFh
Graphics/SMRAM
RAM (128 KB)
DOS Compatibility
Area
000A 0000h
0009 FFFFh
640 KB
512 KB
Fixed Mem. Area
(128 KB)
0008 0000h
0007 FFFFh
Base Memory
(512 KB)
0000 0000h
NOTE: All locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128 KB
fixed memory area can, through the north bridge, be mapped to DRAM or to PCI space. Graphics RAM area is
mapped to PCI or AGP locations.
Figure 3–3. System Memory Map
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Chapter 3 Processor/Memory Subsystem
3.4
SUBSYSTEM CONFIGURATION
The 82815 GMCH component provides the configuration function for the processor/memory
subsystem. Table 3-4 lists the configuration registers used for setting and checking such
parameters as memory control and PCI bus operation. These registers reside in the PCI
Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3-4.
Host/PCI Bridge Configuration Registers (GMCH, Device 0)
PCI Config.
Addr.
Reset
Value
PCI Config.
Addr.
Reset
Value
Register
Register
00, 01h
02, 03h
04, 05h
06, 07h
08h
0A..0Bh
0Dh
0Eh
10..13h
50, 51h
53h
55..56h
57h
Vender ID
Device ID
Command
Status
Revision ID
Class Code
Latency Timer
Header Type
Aperture Base Config.
PAC Config. Reg.
Data Buffer Control
DRAM Row Type
DRAM Control
DRAM Timing
PAM 0..6 Registers
DRAM Row Boundary
Fixed DRAM Hole
8086h
1130h
0006h
[1]
--
--
00h
00h
[2]
00h
83h
00h
01h
00h
00h
01h
00h
6A, 6Bh
6C..6Fh
70h
71h
72h
90h
91h
92h
93h
A0..A3h
A4..A7h
A8..ABh
B0..B3h
B4h
B8..BBh
BCh
BDh
DRAM Control Reg.
Memory Buffer Strength
Multi-Transaction Timer
CPU Latency Timer
SMRAM Control
00h
55h
00h
10h
02h
00h
00h
00h
00h
N/A
N/A
00h
00h
0000h
0000h
00h
00h
Error Command
Error Status Register 0
Error Status Register 1
Reset Control
AGP Capability Identifier
AGP Status
AGP Command
AGP Control
Aperture Size
58h
59..5Fh
60..67h
68h
Aperture Translation Table
Aperture I/F Timer
Low Priority Timer
NOTES:
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.
[1] = 0090h for AGP (external graphics) implementation; = 0080h for GFX (internal i740)
implementation.
[2] = 8 for AGP; = 0 for GFX.
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Chapter 4
SYSTEM SUPPORT
4.1
INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following
topics:
♦
♦
♦
♦
♦
♦
♦
PCI bus overview (4.2)
AGP bus overview (4.3)
System resources (4.4)
page 4-2
page 4-10
page 4-15
page 4-22
System clock distribution (4.5)
Real-time clock and configuration memory (4.6) page 4-23
System management (4.7) page 4-33
Register map and miscellaneous functions (4.8) page 4-38
This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic
aspects of these functions as well as information unique to the systems covered in this guide. For
detailed information on specific components, refer to the applicable manufacturer’s
documentation.
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Chapter 4 System Support
4.2
PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation
in this particular system. For detailed information regarding PCI bus operation, refer to
the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the MCH and ICH2 are organized as multiple
devices). A function is defined as the end source or target of the bus transaction. A device may
contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the 815E chipset components and is not physically accessible. The AGP
bus that services the AGP slot (or resident AGP controller on the Small Form Factor) is
designated as PCI bus #1. All PCI slots and the NIC function internal to the 82801BA reside on
PCI bus #2.
82845 MCH Component
Mem. Cntlr.
Function
PCI Bus #1
(AGP Bus)
PCI
Bus #0
AGP
Bridge
AGP Connector
Function
Hub Link I/F
Hub Link Bus
Hub Link I/F
82801BA ICH2 Component
PCI Bus #0
PCI Bridge
Function
EIDE
Controller
Function
USB
I/F
Function
SMBus
Controller
Function
LPC
Bridge
Function
AC97
Audio
Function
PCI
Bus #2
NIC
I/F
Function
PCI
Bus #2
PCI Connector 1
PCI Connector 2
PCI Connector 3 [1]
PCI Connector 4 [2]
PCI Connector 5 [2]
NOTES:
[1] Desktop and Configurable minitower models only.
[2] Configurable minitower models only
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Figure 4-1. PCI Bus Devices and Functions
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Chapter 4 System Support
4.2.1 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using auto-
incremented addressing. Four types of address cycles can take place on the PCI bus; I/O, memory,
configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).
4.2.1.1 I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing
is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linear-
incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with
addressing assumed to increment accordingly (four bytes at a time).
4.2.1.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by
software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Address Register
PCI Configuration Data Register
I/O Port 0CF8h, R/W, (32-bit access only)
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Function
Bit
Function
Bit
31
Configuration Enable
0 = Disabled
31..0
Configuration Data.
1 = Enable
30..24
23..16
15..11
Reserved - read/write 0s
Bus Number. Selects PCI bus
PCI Device Number. Selects PCI
device for access
10..8
Function Number. Selects function of
selected PCI device.
Register Index. Specifies config. reg.
Configuration Cycle Type ID.
00 = Type 0
7..2
1,0
01 = Type 1
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Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream
PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge
may convert a Type 1 to a Type 0 if it’s destined for a device being serviced by that bridge or it
may forward the Type 1 cycle unmodified if it is destined for a device being serviced by a
downstream bridge. Figure 4-2 shows the configuration cycle format and how the loading of
0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11>
determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which
acts as a “chip select” function for the PCI device to be configured. The function number (CF8h,
bits <10..8>) is used to select a particular function within a PCI component.
3
2 2
1
1
1
1
8 7
2 1 0 [1]
Bus
Number
Device
Number
Function
Number
Register
Index
Reserved
Register 0CF8h
Results in:
AD31..0
(w/Type 00
Config. Cycle)
Function
Number
Register
Index
IDSEL (only one signal line asserted)
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycle, 01 = Type 1 cycle
Type 01 cycle only. Reserved on Type 00 cycle.
Figure 4-2. Configuration Cycle
Table 4-1 shows the standard configuration of device numbers and IDSEL connections for
components and slots residing on a PCI bus.
e 4-1. PCI Device Configu
Table 4-1.
PCI Component Configuration Access
PCI
IDSEL
PCI Component
Notes
Function #
Device #
Bus #
Wired to:
82845 MCH:
--
0
0
0
0 (00h)
1 (01h)
0 (00h)
0
0
1
Memory Controller
AGP Bridge
AGP slot
--
--
82801BA ICH2:
0
0
1
2
3
4
5
6
0
30 (1Eh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
8 (08h)
0
0
0
0
0
0
0
0
2
PCI Bridge
LPC Bridge
EIDE Controller
USB I/F #1
SMBus Controller
USB I/F #2
AC97 Audio Controller
AC97 Modem Controller
Network Interface Controller
PCI Connector 1 (slot 1)
PCI Connector 2 (slot 2)
PCI Connector 3 (slot 3)
PCI Connector 4 (slot 4)
PCI Connector 5 (slot 5)
[1]
[2]
[2]
[2, 3]
[2, 4]
[2, 4]
0
0
0
0
0
4 (04h)
9 (09h)
10 (0Ah)
11 (0Bh)
13 (0Dh)
2
2
2
2
2
AD20
AD25
AD26
AD27
AD29
NOTES:
[1] Not implemented.
[2] PCI bus number given is for standard configuration.
[3] Desktop and Configurable Minitower models only.
[4] Configurable minitower models only.
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The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space
of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration
data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Register
Index
Register
Index
31
24 23
16 15
8
7
0
31
24 23
16 15
Bridge Control Int. Pin
8
7
0
FCh
FCh
40h
3Ch
38h
40h
3Ch
38h
Min. Lat.
Min. GNT
Reserved
Reserved
Expansion ROM Base Address
Subsystem ID Subsystem Vendor ID
Int. Pin
Int. Line
Int. Line
Expansion ROM Base Address
Reserved
34h
30h
2Ch
28h
34h
30h
2Ch
28h
I/O Base Upper 16 Bits
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Prefetch. Mem. Limit Prefetch. Mem. Base
Memory Limit Memory Base
Secondary Status I/O Limit I/O Base
I/O Limit Upper 16 Bits
Card Bus CIS Pointer
24h
Configuration
Space
20h
1Ch
18h
Header
2nd Lat.Tmr Sub. Bus # Sec. Bus # Pri. Bus #
Base Address Registers
10h
10h
0Ch
08h
BIST
Hdr. Type Lat. Timer Line Size
Class Code
Revision ID
Status Command
Device ID Vendor ID
BIST
Hdr. Type Lat. Timer Line Size
Class Code
Revision ID
Status Command
Device ID Vendor ID
0Ch
08h
04h
04h
00h
00h
PCI Configuration Space Type 1
PCI Configuration Space Type 0
Data required by PCI protocol
Not required
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on
the system board are listed in Table 4-2.
Table 4-2.
System Board PCI Device Identification
PCI Device
Vendor ID
Device ID
82845 MCH:
Memory Controller
AGP Bridge
8086h
8086h
1A30h
1A31h
82801 ICH2:
PCI Bridge
LPC Bridge
8086h
8086h
8086h
8086h
8086h
8086h
8086h
244Eh
2440h
244Bh
2444h
(Hidden)
2445h
2449h
EIDE Controller
USB I/F #2
SMBus Controller
AC97 Audio Controller
Network Interface Controller
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4.2.2 PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and
request signals assignments for the devices on the PCI bus.
Table 4-3.
PCI Bus Mastering Devices
REQ/GNT Line
REQ0/GNT0
REQ1/GNT1
REQ2/GNT2
REQ3/GNT3
REQ4/GNT4
GREQ/GGNT
NOTE:
Device
PCI Connector Slot 1
PCI Connector Slot 2
PCI Connector Slot 3 [1]
PCI Connector Slot 4 [2]
PCI Connector Slot 5 [2]
AGP Slot
[1] Desktop and Configurable Minitower models only.
[2] Configurable minitower models only
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur
concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for
PCI bus ownership.
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4.2.3 OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility
area (refer to the system memory map shown in chapter 3).
4.2.4 PCI INTERRUPTS
Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals
may be generated by on-board PCI devices or by devices installed in the PCI slots. For more
information on interrupts including PCI interrupt mapping refer to the “System Resources” section
4.4.
4.2.5 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI
Power Management Enable (PME-) signal is supported by the chipset and allows compliant PCI
and AGP peripherals to initiate the power management routine.
4.2.6 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
4.2.6.1 Hub Link Bus
The chipset implements a Hub Link bus between the MCH and the ICH2. This bus is transparent
to software and is not accessible for expansion purposes.
4.2.6.2 LPC Bus
The 82801 ICH2 implements a Low Pin Count (LPC) bus for handling transactions to and from
the 47B367 Super I/O Controller as well as the 82802 Firmware Hub (FWH). The LPC bus
transfers data a nibble (4 bits) at a time at a 33-MHz rate. Generally transparent in operation, the
only consideration required of the LPC bus is during the configuration of DMA channel modes
(see section 4.4.3 “DMA”).
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4.2.7 PCI CONFIGURATION
PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA
channel configuration, RTC control, port decode ranges, and power management options. These
parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of the ICH2
component and configured through the PCI configuration space registers listed in Table 4-4.
Configuration is provided by BIOS at power-up but re-configurable by software.
Table 4-4.
LPC Bridge Configuration Registers
(ICH2, Function 0, Device 31)
PCI
PCI
Config.
Addr.
Reset
Value
Config.
Addr.
Reset
Value
Register
Register
00, 01h
02, 03h
04, 05h
06, 07h
08h
0A-0Bh
0Eh
40-43h
44h
4E, 4Fh
54h
58-5Bh
5Ch
60-63h
64h
68-6B
88h
Vendor ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
ACPI Base Address
ACPI Control
BIOS Control
TCO Control
GPIO Base Address
GPIO Control
INTA-D Routing Cntrl.
Serial IRQ Control
INTE-F Routing Cntrl.
Dev. 31 Error Config.
8086h
2440h
000Fh
0280h
00h
0106h
80h
1
00h
0000h
00h
1
00h
8Ah
Device 31 Error Status
PCI DMA Configuration
Power Management
General Control
00h
0000h
90, 91h
A0-CFh
D0-D3h
D4-D7h
D8h
E0h
E1h
E2h
E3h
E4, E5h
E6, E7h
E8-EBh
EC, EDh
EE, EFh
F0h
0’s
F00h
00h
00h
00h
General Status
RTC Configuration
LPC COM Port Dec. Range
LPC FDD & LPT Dec. Rge
LPC Audio Dec. Range
FWH Decode Enable
LPC I/F Decode Range 1
LPC I/F Enables
FWH Select 1
LPC I/F Decode Range 2
FWH Select 2
80h
FFh
0000h
0000h
00112233
0000h
5678h
0Fh
80h [1]
10h
80h [1]
00h
FWH Decode Enable 2
Function Disable Register
F2h
00h
NOTE:
[1] Value for each byte.
Assume unmarked locations/gaps as reserved.
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4.2.8 PCI CONNECTOR
B1
B49
A49
B62
B52
A52
A1
A62
Figure 4-4. PCI Bus Connector (32-Bit Type)
Table 4-5.
PCI Bus Connector Pinout
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
B Signal
-12 VDC
TCK
GND
TDO
+5 VDC
+5 VDC
INTB-
INTD-
PRSNT1-
RSVD
PRSNT2-
GND
GND
RSVD
GND
CLK
GND
REQ-
+5 VDC
AD31
AD29
GND
AD27
AD25
+3.3 VDC
C/BE3-
AD23
GND
AD21
AD19
+3.3 VDC
—
A Signal
TRST-
+12 VDC
TMS
TDI
+5 VDC
INTA-
INTC-
+5 VDC
Reserved
+5 VDC
Reserved
GND
GND
+3.3 AUX
RST-
+5 VDC
GNT-
GND
PME-
AD30
+3.3 VDC
AD28
AD26
GND
AD24
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
—
B Signal
AD17
A Signal
AD16
+3.3 VDC
FRAME-
GND
TRDY-
GND
STOP-
+3.3 VDC
SDONE n
SBO-
GND
PAR
AD15
+3.3 VDC
AD13
AD11
GND
AD09
Key
Key
94
C/BE2-
GND
IRDY-
+3.3 VDC
DEVSEL-
GND
LOCK-
PERR-
+3.3 VDC
SERR-
+3.3 VDC
C/BE1-
AD14
GND
AD12
AD10
GND
Key
Key
AD08
AD07
+3.3 VDC
AD05
AD03
GND
AD01
+5 VDC
ACK64-
+5 VDC
+5 VDC
—
C/BE0-
+3.3 VDC
AD06
AD04
GND
IDSEL
+3.3 VDC
AD22
AD20
GND
AD02
AD00
+5 VDC
REQ64-
+5 VDC
+5 VDC
—
GND
AD18
—
Reserved
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4.3
AGP BUS OVERVIEW
NOTE: For a detailed description of AGP bus operations refer to the AGP Interface
Specification Rev. 2.0 available at the following AGP forum web site:
http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high-
performance interface for graphics adapters, especially those designed for 3D operations. The
AGP interface is designed to give graphics adapters dedicated pipelined access to system memory
for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics
operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapter
only requires enough memory for frame buffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined
protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also
behave as a “PCI” target during fast writes from the MCH.
Key differences between the AGP interface and the PCI interface are as follows:
♦
♦
Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request
for data and the transfer of data may be separated by other operations.
Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in AGP operations is the same linear space used by PCI memory space
commands, but is further specified by the graphics address re-mapping table (GART) of the
north bridge component.
♦
♦
Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries.
If a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary
data that is discarded by the target.
Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer
lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data
transfers. These actions are separate from each other.
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4.3.1.1 Data Request
Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD
lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for
addressing only and the AD lines for data only). Even though there are only eight SBA lines (as
opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by
allowing the AD lines to be exclusively used for data transfers. Sideband addressing occurs at the
same rate (1X, 2X, or 4X) as data transfers. The differences in rates will be discussed in the next
section describing data transfers. Note also that sideband addressing is limited to 48 bits (address
bits 48-63 are assumed zero). The MCH component supports both SBA and AD addressing , but
the method and rate is selected by the AGP graphics adapter.
4.3.1.2 Data Transfers
Data transfers use the AD lines and occur as the result of data requests described previously. Each
transaction resulting from a request involves at least eight bytes, requiring the 32 AD lines to
handle at least two transfers per request. The 82845 MCH supports three transfer rates: 1X, 2X,
and 4X. Regardless of the rate used, the speed of the bus clock is constant at 66 MHz. The
following subsections describe how the use of additional strobe signals makes possible higher
transfer rates.
AGP 1X Transfers
During a AGP 1X transfer the 66-MHz CLK signal is used to qualify the control and data signals.
Each 4-byte data transfer is synchronous with one CLK cycle so it takes two CLK cycles for a
minimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals
retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with
“000” for low priority and “001” indicating high priority. The signal level for AGP 1X transfers
may be 3.3 or 1.5 VDC.
T1
T2
T3
T4
T5
T6
T7
CLK
AD
D1A
xxx
D1B
xxx
D2A
D2B
xxx
GNT-
TRDY-
ST0..2
xxx
00x
xxx
Figure 4-5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)
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AGP 2X Transfers
During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-
MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an
additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 4-
6). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx
and the second four bytes (DnB) are latched on the rising edge of AD_STBx. The signal level for
AGP 2X transfers may be 3.3 or 1.5 VDC.
T1
T2
T3
T4
T5
T6
T7
CLK
AD
D1A D1B D2A D2B D3A D3B D4A D4B
AD_STBx
GNT-
TRDY-
ST0..2
xxx
xxx
xxx
xxx
00x
xxx
Figure 4-6. AGP 2X Data Transfer (Peak Transfer Rate: 532 MB/s)
AGP 4X Transfers
The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock cycle. As in
2X transfers the 66-MHz CLK signal is used only for qualifying control signals while strobe
signals are used to latch each 4-byte transfer on the AD lines. As shown in Figure 4-7, 4-byte
block DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of
AD_STBx-. The signal level for AGP 4X transfers is 1.5 VDC.
T1
T2
T3
T4
CLK
AD
D1A D1B D2A D2B D3A D3B D4A D4B
AD_STBx
AD_STBx-
ST0..2
xxx
00x
xxx
xxx
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Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s)
4.3.2 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory
access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device
integrated within the north bridge (MCH, device 1) component. The AGP function is, from the
PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI
configuration registers (Table 4-6). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the
MCH. Function 0 registers (listed in Table 3-4) include functions that affect basic
control (GART) of the AGP.
Table 4-6.
PCI/AGP Bridge Function Configuration Registers
(MCH, Function 1)
PCI
PCI
Config.
Addr.
Reset
Value
Config.
Addr.
Reset
Value
Register
Register
00, 01h
02, 03h
04, 05h
06, 07h
08h
0A, 0Bh
0Eh
18h
Vendor ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
8086h
1131h
0000h
0020h
00h
0406h
01h
00h
1Bh
1Ch
1Dh
1E, 1Fh
20, 21h
22, 23h
24, 25h
26, 27h
3Eh
Sec. Master Latency Timer
I/O Base Address
I/O Limit Address
Sec. PCI/PCI Status
Memory Base Address
Memory Limit Address
Prefetch Mem. Base Addr.
Prefetch Mem. Limit Addr.
PCI/PCI Bridge Control
Reserved
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
00h
19h
1Ah
00h
00h
3F-FFh
00h
NOTE:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed
register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI device.
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4.3.3 AGP CONNECTOR
A66
A1
B66
B1
Figure 4-8. Universal AGP Bus Connector
Table 4-7.
AGP Bus Connector Pinout
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
A Signal
+12 VDC
Type Det-
NC
USBN
GND
INTA-
RESET
GNT-
VDD3
ST1
B Signal
OVRCNT-
VDD
VDD
USBP
GND
INTB-
CLK
REQ-
VDD3
ST0
ST2
RBF-
GND
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A Signal
GND
NC
VDD3
PAD30
PAD28
VDD3
PAD26
PAD24
GND
B Signal
GND
VDD3 Aux
VDD3
PAD31
PAD29
VDD3
PAD27
PAD25
GND
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
A Signal
VDD3
TRDY-
STOP-
PME-
B Signal
VDD3
DEVSEL-
VDDQ
PERR-
GND
SERR-
CBE1-
VDDQ
PAD14
PAD12
GND
PAD10
PAD08
VDDQ
GND
PAR
PAD15
VDDQ
PAD13
PAD11
GND
PAD09
CBE0-
VDDQ
AD_STB0- AD_STB0
PAD06
GND
PAD04
PAD02
VDDQ
PAD00
VREFGC
AD_STB1- AD_STB1
NC
PIPE-
GND
CBE3-
VDDQ
PAD22
PAD20
GND
PAD18
PAD16
VDDQ
FRAME-
NC
PAD23
VDDQ
PAD21
PAD19
GND
PAD17
CBE2-
VDDQ
IRDY-
VDD3 Aux
GND
WBF-
SBA1
VDD3
SBA3
SB_STB-
GND
SBA5
SBA7
NC
NC
SBA0
VDD3
SBA2
SB_STB
GND
SBA4
DBA6
NC
PAD07
GND
17
18
19
20
21
22
PAD05
PAD03
VDDQ
PAD01
VREFCG
GND
NC
NC
NOTES;
NC = Not connected
VDDQ = 3.3 VDC when TYPE DET- is left open by AGP 1X/2X card.
VDDQ = 1.5 VDC when TYPE DET- is grounded by AGP 4X card.
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Chapter 4 System Support
4.4
SYSTEM RESOURCES
This section describes the availability and basic control of major subsystems, otherwise known as
resource allocation or simply “system resources.” System resources are provided on a priority
basis through hardware interrupts and DMA requests and grants.
4.4.1 INTERRUPTS
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A
maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and
CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor,
although it may be inhibited by hardware or software means external to the microprocessor.
4.4.1.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt
(INTR-) input to the microprocessor. The microprocessor halts execution to determine the source
of the interrupt and then services the peripheral as appropriate.
Figure 4-9 shows the routing of PCI and ISA interrupts. Most IRQs are routed through the I/O
controller, which contains a serializing function. A serialized interrupt stream is applied to the
82801 ICH2.
LPC47B367
IRQ3..7,
9..12,
14,15
t
I/O &
SM Functions
Serial IRQ
82801
ICH2
IDE
Hard Drives
INTR-
IRQ14,15
INTA-..H-
Interrupt
Processing
Processor
APIC bus
PCI Peripherals
Figure 4-9. Maskable Interrupt Processing, Block Diagram
Interrupts may be processed in one of two modes (selectable through the F10 Setup utility):
♦
♦
8259 mode
APIC mode
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8259 Mode
The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259-
equivalent logic. Table 4-8 lists the standard source configuration for maskable interrupts and
their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest
number) is processed first.
Table 4-8.
Maskable Interrupt Priorities and Assignments
Priority
1
2
Signal Label
IRQ0
Source (Typical)
Interval timer 1, counter 0
Keyboard
IRQ1
3
4
IRQ8-
IRQ9
Real-time clock
Unused
5
6
7
8
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
PCI devices/slots
Audio codec
Mouse
Coprocessor (math)
Primary IDE controller
Secondary IDE I/F controller
Serial port (COM2)
Serial port (COM1)
Network interface controller
Diskette drive controller
Parallel port (LPT1)
NOT AVAILABLE (Cascade from interrupt controller 2)
9
10
11
12
13
14
15
--
IRQ2
APIC Mode
The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt
processing with the following advantages:
♦
♦
♦
Eliminates the processor’s interrupt acknowledge cycle by using a separate (APIC) bus
Programmable interrupt priority
Additional interrupts (total of 24)
The APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI
devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:
ICH2
Int. Cntlr.
INTA-
PCI
Slot 1
INTA-
--
PCI
Slot 2
INTD-
--
PCI
Slot 3
INTC-
--
Slot 4
INTB-
--
Slot 5
INTD-
--
AGP
Slot
--
NIC
I/F [1]
--
--
USB
I/F #2
--
--
INTB-
--
INTC-
INTD-
INTE-
INTF-
INTG-
INTH-
INTB-
--
--
INTC-
INTD-
--
INTA-
--
--
INTB-
INTC-
--
INTD-
--
--
INTA-
INTB-
--
INTC-
--
--
INTD-
INTA-
--
INTA-
--
---
INTB-
INTC-
--
INTA-
INTB-
--
--
--
--
--
INTA-
--
--
--
--
--
--
--
--
Wired
to
--
INTC-
NOTES:
[1] Connection internal to the ICH2. Will be reported by BIOS as using INTA but is NOT shared with
other functions using INTA.
Desktop and configurable minitower systems only.
Configurable minitower systems only.
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The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the
standard ISA interrupts (IRQn).
NOTE: The APIC mode is supported by the Windows NT and Windows 2000 operating
systems. Systems running the Windows 95 or 98 operating system will need to run in
8259 mode.
Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped
registers. These registers are listed in Table 4-9.
Table 4-9.
Maskable Interrupt Control Registers
I/O Port
020h
Register
Base Address, Int. Cntlr. 1
021h
0A0h
0A1h
Initialization Command Word 2-4, Int. Cntlr. 1
Base Address, Int. Cntlr. 2
Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
4.4.1.2 Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be
maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
♦
♦
Parity errors detected on a PCI bus (activating SERR- or PERR-).
Microprocessor internal error (activating IERRA or IERRB)
The SERR- and PERR- signals are routed through the ICH2 component, which in turn activates
the NMI to the microprocessor.
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The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit
Function
7
NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
6
IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
IOCHK- NMI Enable/Disable:
5
4
3
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
2
1 = Parity error NMI disabled and cleared (R/W)
1
0
Speaker Data (R/W)
Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or
<3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for the
QuickLock/QuickBlank functions as well.
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Chapter 4 System Support
4.4.2 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which a device accesses system memory without
involving the microprocessor. Although the DMA method has been traditionally used to transfer
blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for
other processing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the data manual for the Intel 82801BA I/O Controller Hub.
The 82801 ICH2 component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels, each (excepting channel 4) configurable to a specific
device. Table 4-10 lists the default configuration of the DMA channels.
Table 4-10.
Default DMA Channel Assignments
DMA Channel
Device ID
Controller 1 (byte transfers)
0
Spare
1
2
3
Audio subsystem
Diskette drive
Parallel port
Controller 2 (word transfers)
4
5
6
7
Cascade for controller 1
Spare
Spare
Spare
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that
channel 4 is not available for use other than its cascading function for controller 1. The DMA
controller 2 can transfer words only on an even address boundary. The DMA controller and page
register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuration, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:
♦
♦
LPC DMA
PC/PCI DMA
The LPC DMA mode uses the LPC bus to communicate DMA channel control and is
implemented for devices using DMA through the LPC47B367 I/O controller such as the diskette
drive controller.
The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control and
is used by PCI expansion devices.
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The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers.
4.4.2.1 DMA Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works in
conjunction with the DMA controllers to define the complete (24-bit)address for the DMA
channels. Table 4-11 lists the page register port addresses.
Table 4-11.
DMA Page Register Addresses
DMA Channel
Page Register I/O Port
Controller 1 (byte transfers)
Ch 0
Ch 1
Ch 2
Ch 3
087h
083h
081h
082h
Controller 2 (word transfers)
Ch 4
Ch 5
n/a
08Bh
Ch 6
089h
Ch 7
08Ah
Refresh
08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address - Controller 1 (Byte Transfers)
8-Bit Page Register
A23..A16
8-Bit DMA Controller
A15..A00
24-Bit Address - Controller 2 (Word Transfers)
8-Bit Page Register
A23..A17
16-Bit DMA Controller
A16..A01, (A00 = 0)
Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
when word-length transfers are selected.
By not connecting A00, the following applies:
♦
♦
The size of the the block of data that can be moved or addressed is measured in 16-bits
(words) rather than 8-bits (bytes).
The words must always be addressed on an even boundary.
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Chapter 4 System Support
DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can
move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only
possible between 16-bit memory and 16-bit peripherals.
The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses
in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit
memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.
Address lines LA23..17, SA18,19 are driven low.
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
4.4.2.2 DMA Controller Registers
Table 4-12 lists the DMA Controller Registers and their I/O port addresses. Note that there is a set
of registers for each DMA controller.
Table 4-12.
DMA Controller Registers
Register
Status
Command
Mode
Write Single Mask Bit
Write All Mask Bits
Software DRQx Request
Base and Current Address - Ch 0
Current Address - Ch 0
Base and Current Word Count - Ch 0
Current Word Count - Ch 0
Base and Current Address - Ch 1
Current Address - Ch 1
Base and Current Word Count - Ch 1
Current Word Count - Ch 1
Base and Current Address - Ch 2
Current Address - Ch 2
Base and Current Word Count - Ch 2
Current Word Count - Ch 2
Base and Current Address - Ch 3
Current Address - Ch 3
Controller 1
008h
008h
00Bh
00Ah
00Fh
009h
000h
000h
001h
001h
002h
002h
003h
003h
004h
004h
005h
005h
006h
006h
007h
007h
00Dh
00Ch
00Dh
00Eh
Controller 2
0D0h
0D0h
0D6h
0D4h
0DEh
0D2h
0C0h
0C0h
0C2h
0C2h
0C4h
0C4h
0C6h
0C6h
0C8h
0C8h
0CAh
0CAh
0CCh
0CCh
0CEh
0CEh
0DAh
0D8h
0DAh
0DCh
R/W
R
W
W
W
W
W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Base and Current Word Count - Ch 3
Current Word Count - Ch 3
Temporary (Command)
Reset Pointer Flip-Flop (Command)
Master Reset (Command)
Reset Mask Register (Command)
W
R
R
W
W
W
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4.5
SYSTEM CLOCK DISTRIBUTION
These systems use an Intel CK-type clock generator and crystal for generating the clock signals
required by the system board components. Table 4-13 lists the system board clock signals and
how they are distributed.
Table 4-13.
Clock Generation and Distribution
Frequncy
Source
Destination
66, 100, or 133 MHz
100 or 133 MHz
66 MHz
CK
CK
CK
Processor, MCH
DIMM sockets
ICH2, AGP Graphics Cntlr. [1]
ICH2, I/O Cntlr.
48 MHz
CK
33 MHz
14.31818 MHz
CK
Crystal
Processor, ICH2, PCI Slots
CK
NOTES:
[1] Routed to on-board controller on Deslpro EN SFF.
Routed to AGP slot on Desktop and Configurable Minitower.
Certain clock outputs are turned off during reduced power modes to conserve energy. Clock
output control is handled through the SMBus interface by BIOS.
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Chapter 4 System Support
4.6
REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are
provided by the 82801 ICH2 component and is MC146818-compatible. As shown in the
following figure, the 82801 ICH2 component provides 256 bytes of battery-backed RAM divided
into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the
standard memory area. All locations of the standard memory area (00-7Fh) can be directly
accessed using conventional OUT and IN assembly language instructions through I/O ports
70h/71h, although the suggested method is to use the INT15 AX=E823h BIOS call.
82801
Register D
Register C
Register B
Register A
Year
Month
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
0Dh
0Ch
0Bh
FFh
Extended Config.
Memory Area
(128 bytes)
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
80h
7Fh
Standard Config.
Memory Area
(114 bytes)
0Eh
0Dh
RTC Area
(14 bytes)
00h
CMOS
Figure 4-10. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. During system operation a wire-Ored circuit allows the RTC and
configuration memory to draw power from the power supply. The battery is located in a battery
holder on the system board and has a life expectancy of four to eight years. When the battery has
expired it is replaced with a Renata CR2032 or equivalent 3-VDC lithium battery.
4.6.1 CLEARING CMOS
The contents of configuration memory (including the Power-On Password) can be cleared by the
following procedure:
1. Turn off the unit.
2. Disconnect the AC power cord from the outlet and/or system unit.
3. Remove the chassis hood (cover) and insure that no LEDs on the system board are
illuminated.
4. Press and release the CMOS clear button on the system board.
5. Replace the chassis hood (cover).
6. Reconnect the AC power cord to the outlet and/or system unit.
7. Turn the unit on.
To clear only the Power-On Password refer to section 4.7.1.1.
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4.6.2 CMOS ARCHIVE AND RESTORE
During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and
other system variables) in a portion of the flash ROM. Should the system become un-usable, the
last good copy of NVRAM data can be restored with the Power Button Override function. This
function is invoked with the following procedure:
1. With the unit powered down, press and release the power button.
2. Immediately after releasing the power button in step 1, press and hold the power button until
the unit powers down. This action will be recorded as a Power Button Override event.
With the next startup sequence the BIOS will detect the occurrence of the Power Button Override
event and will load the backup copy of NVRAM from the ROM to the CMOS.
NOTE: The Power Button Override feature does not allow quick cycling of the system
(turning on then off). If the power cord is disconnected during the POST routine, the
splash screen image may become corrupted, requiring a re-flashing of the ROM (refer to
chapter 8, BIOS ROM).
4.6.3 STANDARD CMOS LOCATIONS
Table 4-14 and the following paragraphs describe standard configuration memory locations 0Ah-
3Fh. These locations are accessible through using OUT/IN assembly language instructions using
port 70/71h or BIOS function INT15, AX=E823h.
Table 4-14.
Configuration Memory (CMOS) Map
Location Function
Location
Function
00-0Dh
0Eh
0Fh
10h
11h
Real-time clock
Diagnostic status
System reset code
Diskette drive type
Reserved
Hard drive type
Security functions
24h
25h
26h
27h
28h
29h
2Ah
System board ID
System architecture data
Auxiliary peripheral configuration
Speed control external drive
Expanded/base mem. size, IRQ12
Miscellaneous configuration
Hard drive timeout
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Equipment installed
2Bh
2Ch
2Dh
2Eh-2Fh
30h-31h
32h
33h
34h
35h
36h
37h-3Fh
40-FFh
System inactivity timeout
Monitor timeout, Num Lock Cntrl
Additional flags
Checksum of locations 10h-2Dh
Total extended memory tested
Century
Miscellaneous flags set by BIOS
International language
APM status flags
ECC POST test single bit
Power-on password
Base memory size, low byte/KB
Base memory size, high byte/KB
Extended memory, low byte/KB
Extended memory, high byte/KB
Hard drive 1, primary controller
Hard drive 2, primary controller
Hard drive 1, secondary controller
Hard drive 2, secondary controller
Enhanced hard drive support
Reserved
Power management functions
Feature Control/Status
NOTES:
Assume unmarked gaps are reserved.
Higher locations (>3Fh) contain information that should be accessed using the INT15, AX=E845h
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BIOS function (refer to Chapter 8 for BIOS function descriptions).
4.7
SYSTEM MANAGEMENT
This section describes functions having to do with security, power management, temperature, and
overall status. These functions are handled by hardware and firmware (BIOS) and generally
configured through the Setup utility.
4.7.1 SECURITY FUNCTIONS
These systems include various features that provide different levels of security. Note that this
subsection describes only the hardware functionality (including that supported by Setup) and
does not describe security features that may be provided by the operating system and application
software.
4.7.1.1 Power-On Password
These systems include a power-on password, which may be enabled or disabled (cleared) through
a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH2 that is
checked during POST. The password is stored in configuration memory (CMOS) and if enabled
and then forgotten by the user will require that either the password be cleared (preferable solution
and described below) or the entire CMOS be cleared (refer to section 4.6).
To clear the password, use the following procedure:
1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2. Remove the cover (hood) as described in the appropriate User Guide or Maintainance And
Service Guide. Insure that all system board LEDs are off (not illuminated).
3. Locate the password clear jumper (header is labeled E49 on these systems) and move the
jumper from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4. Replace the cover.
5. Re-connect the AC power cord to the AC outlet and/or system unit.
6. Turn on the system. The POST routine will clear and disable the password.
7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.
4.7.1.2 Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a
password. The password is held on CMOS and, if forgotten, will require that CMOS be cleared
(refer to section 4.6).
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4.7.1.3 Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock
mechanism.
4.7.1.4 I/O Interface Security
The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup
utility to guard against unauthorized access to a system. In addition, the ability to write to or boot
from a removable media drive (such as the diskette drive) may be enabled through the Setup
utility. The disabling of the serial, parallel, and diskette interfaces are a function of the
LPC47B367 I/O controller. The USB ports are controlled through the 82801 ICH2.
4.7.1.5 Chassis Security
The Small Form Factor and Desktop systems feature Smart Cover (hood) Sensor and Smart Cover
(hood) Lock mechanisms to inhibit unauthorized tampering of the system unit.
Smart Cover Sensor
The Small Form Factor and Desktop systems include a plunger switch that, when the cover (hood)
is removed, closes and grounds an input of the 82801 ICH2. The battery-backed logic will record
this “intrusion” event by setting a specific bit. This bit will remain set (even if the cover is
replaced) until the system is powered up and the user completes the boot sequence successfully, at
which time the bit will be cleared. Through Setup, the user can set this function to be used by
Alert-On-LAN and or one of three levels of support for a “cover removed” condition:
Level 0 - Cover removal indication is essentially disabled at this level. During POST, status bit is
cleared and no other action is taken by BIOS.
Level 1 - During POST the message “The computer’s cover has been removed since the last
system start up” is displayed and time stamp in CMOS is updated.
Level 2 - During POST the “The computer’s cover has been removed since the last system start
up” message is displayed, time stamp in CMOS is updated, and the user is prompted for the
administrator password.
Smart Cover Lock
The Small Form Factor and Desktop systems include a solenoid-operated locking bar that, when
activated, prevents the cover (hood) from being removed. The GPIO ports 44 and 45 of the
LPC47B367 I/O controller provide the lock and unlock signals to the solenoid. A locked hood
may be bypassed by removing special screws that hold the locking mechanism in place. The
special screws are removed with the Compaq Smart Cover Lock Failsafe Key.
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4.7.2 POWER MANAGEMENT
This system provides baseline hardware support of ACPI- and APM-compliant firmware and
software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be
placed into a reduced power mode either automatically or by user control. The system can then be
brought back up (“wake-up”) by events defined by the ACPI specification. The ACPI wake-up
events supported by this system are listed as follows:
ACPI Wake-Up Event
Power Button
RTC Alarm
Wake On LAN (w/NIC)
PME
System Wakes From
Suspend or soft-off
Suspend or soft-off
Suspend or soft-off
Suspend or soft-off
Suspend or soft-off
Suspend only
Serial Port Ring
USB
Keyboard
Suspend only
Mouse
Suspend only
4.7.3 SYSTEM STATUS
These systems provide a visual indication of system boot and ROM flash status through the
keyboard LEDs and operational status using bi-colored power and hard drive activity LEDs as
indicated in Tables 4-15 and 4-16 respectively.
NOTE: The LED indications listed in Table 4-15 are valid only for PS/2-type
keyboards. A USB keyboard will not provide LED status for the listed events, although
audible (beep) indications will occur.
Table 4-15.
System Boot/ROM Flash Status LED Indications
NUM Lock
LED
CAPs Lock
LED
Scroll Lock
LED
Event
System memory failure [1]
Blinking
Off
Off
On
Off
Off
Blinking
Off
Off
On
Off
Off
Blinking
Off
Graphics controller failure [2]
System failure prior to graphics cntlr. initialization [3]
ROMPAQ diskette not present, faulty, or drive prob.
Password prompt
Off
Invalid ROM detected - flash failed
Keyboard locked in network mode
Successful boot block ROM flash
Blinking [4]
Blinking [5]
On [6]
Blinking [4]
Blinking [5]
On [6]
Blinking [4]
Blinking [5]
On [6]
NOTES:
[1] Accompanied by 1 short, 2 long audio beeps
[2] Accompanied by 1 long, 2 short audio beeps
[3] Accompanied by 2 long, 1 short audio beeps
[4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps
[5] LEDs will blink in sequence (NUM Lock, then CAPs Lock, then Scroll Lock)
[6] Accompanied by rising audio tone.
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Table 4-16.
System Operational Status LED Indications
Power
LED
Hard Drive
LED
System Status
S0: System on (normal operation)
S1: Suspend
S3: Suspend to RAM
S4: Suspend to disk
S5: Soft off
Steady green
Green w/HD activity
Blinks green @ 1 Hz
Blinks green @ 1 Hz
Blinks green @ 0.5 Hz
Off - clear
Off
Off
Off
Off
Processor not seated
CPU thermal shutdown
ROM error
Power supply crowbar activated
System off
Steady red
Off
Off (system powers down)
Blinks red @ 1 Hz
Blinks red @ .5 Hz
Off
Off (system powers down)
Off
Off
Off
4.7.4 THERMAL SENSING AND COOLING
All systems feature a variable-speed fan as part of the power supply assembly. All systems also
provide a system board connection for a processor fan, which is present in all units. Desktop and
Configurable Minitower systems provide an auxiliary chassis fan. All fans are controlled through
temperature sensing logic both on the system board and in the power supply. Electrically, there
are slight differences between the Small Form Factor (Figure 4-11) and the desktop and
configurable minitower (Figure 4-12), although functionally operation is the same.
An ASIC monitors a thermal diode internal to the processor and provides a Fan CMD signal that
the Speed Control logic uses to vary the speed of the fan(s) through the negative terminal of the
fan(s). The turning off of the fan(s) as the result from the system being placed into a Sleep
condition is initiated by the control ASIC asserting the Fan Off- signal, which results in the
On/Off Control logic shutting off the +12 volts to the fan(s).
The main differences between the system types are as follows:
♦
♦
In the Small Form Factor system the processor fan, controlled by a separate speed control
circuit, is mounted in the front of the chassis (separate from the heat sink assembly) and air is
conducted across the processor's heat sink by an air baffle.
Desktop/Configurable Minitower systems use an integrated heat sink/fan assembly, with all
fans speed-controlled by the ASIC through the power supply so that a thermal condition of
the processor or power supply will affect all fans simultaneously.
Typical cooling conditions include the following:
1. Normal – Low fan speed.
2. Hot processor – ASIC directs Speed Control logic to increase speed of fan(s).
3. Hot power supply – Power supply increases speed of fan(s).
4. Sleep state – Fan(s) turned off. Hot processor or power supply will result in starting fan(s).
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Chapter 4 System Support
High and low thermal parameters are programmed into the ASIC by BIOS during POST. If the
high thermal parameter is reached then the fan(s) will be turned on full speed and the Therm-
signal will be asserted. The asserted Therm- signal can, with the proper software setup, be used by
the 82801 ICH2 to initiate an AOL message for transmission over a network (refer to Network
Interface Controller subsection in Chapter 5).
NOTE: These systems do not support thermister-based fans used on earlier products.
Fan Header
P70
Speed
Control
(-)
1
2
3
Processor
(+)
+5 VDC
Fan
Sense
P1
Fan
Sink
Power Supply Assembly
PS Fan
10
13
Fan
SPD
Fan CMD
Speed
Control
(-)
Therm-
Interrupt
SMBus
(+)
+5 VDC
ICH2
PS
Circuits
Figure 4-11. Small Form Factor Fan Control Block Diagram
Chassis Fan
Header P8
CPU Fan Header
P70
(-)
(-)
1
2
3
1
(+)
(+)
+5 VDC
+5 VDC
3
Chassis
Fan Sense
Fan
Sink
Power Supply Assembly
P1
CPU Fan Sense
Fan CMD
24
PS Fan
Fan
SPD
Speed
Control
(-)
Control
ASIC
12
Therm-
(+)
801
SMBus
PS
Circuits
Figure 4-12. Desktop/Configurable Minitower Fan Control Block Diagram
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4.8
REGISTER MAP AND MISCELLANEOUS FUNCTIONS
This section contains the system I/O map and information on general-purpose functions of the
ICH2 and I/O controller.
4.8.1 SYSTEM I/O MAP
Table 4-17 lists the fixed addresses of the input/output (I/O) ports.
Table 4-17.
System I/O Map
I/O Port
Function
0000..001Fh
0020..002Dh
002E, 002Fh
0030..003Dh
0040..0042h
004E, 004Fh
0050..0052h
0060..0067h
0070..0077h
0080..0091h
0092h
0093..009Fh
00A0..00B1h
00B2h, 00B3h
00B4..00BDh
00C0..00DFh
00F0h
DMA Controller 1
Interrupt Controller 1
Index, Data Ports to LPC47B367 I/O Controller (primary)
Interrupt Controller
Timer 1
Index, Data Ports to LPC47B367 I/O Controller (secondary)
Timer / Counter
Microcontroller, NMI Controller (alternating addresses)
RTC Controller
DMA Controller
Port A, Fast A20/Reset Generator
DMA Controller
Interrupt Controller 2
APM Control/Status Ports
Interrupt Controller
DMA Controller 2
Coprocessor error register
0170..0177h
01F0..01F7h
0278..027Fh
02E8..02EFh
02F8..02FFh
0370..0377h
0376h
0378..037Fh
03B0..03DFh
03BC..03BEh
03E8..03EFh
03F0..03F5h
03F6h
03F8..03FFh
04D0, 04D1h
0678..067Fh
0778..077Fh
07BC..07BEh
0CF8h
IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
IDE Controller 1 (active only if standard I/O space is enabled for secondary drive)
Parallel Port (LPT2)
Serial Port (COM4)
Serial Port (COM2)
Diskette Drive Controller Secondary Address
IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
Parallel Port (LPT1)
Graphics Controller
Parallel Port (LPT3)
Serial Port (COM3)
Diskette Drive Controller Primary Addresses
IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)
Serial Port (COM1)
Interrupt Controller
Parallel Port (LPT2)
Parallel Port (LPT1)
Parallel Port (LPT3)
PCI Configuration Address (dword access only )
Reset Control Register
0CF9h
0CFCh
PCI Configuration Data (byte, word, or dword access)
NOTE:
Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O
address mapping. Some ranges may include reserved addresses.
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4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS
The LPC47B367 I/O controller contains various functions such as the keyboard/mouse interfaces,
diskette interface, serial interfaces, and parallel interface. While the control of these interfaces
uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these
functions uses indexed ports unique to the LPC47B367. In these systems, hardware strapping
selects I/O addresses 02Eh and 02Fh at reset as the Index/Data ports for accessing the logical
devices within the LPC47B367. Table 4-18 lists the PnP standard control registers for the
LPC47B367.
Table 4-18.
LPC47B367 I/O Controller Control Registers
Index
02h
03h
Function
Configuration Control
Reserved
Reset Value
00h
07h
Logical Device (Interface) Select:
00h = Diskette Drive I/F
01h = Reserved
00h
02h = Reserved
03h = Parallel I/F
04h = Serial I/F (UART 1/Port A)
05h = Serial I/F (UART 2/Port B)
06h = Reserved
07h = Keyboard I/F
08h = Reserved
09h = Reserved
0Ah = Runtime Registers (GPIO Config.)
0Bh = SMBus Configuration
Super I/O ID Register (SID)
Revision
20h
21h
56h
--
22h
23h
24h
25h
Logical Device Power Control
Logical Device Power Management
PLL / Oscillator Control
Reserved
00h
00h
04h
26h
27h
28-2Fh
Configuration Address (Low Byte)
Configuration Address (High Byte)
Reserved
NOTE:
For a detailed description of registers refer to appropriate SMC documentation.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the
configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface
(logical device) is initiated by firmware selecting logical device number of the 47B347 using the
following sequence:
1. Write 07h to I/O register 2Eh.
2. Write value of logical device to I/O register 2Fh.
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase.
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The systems covered in this guide utilize the following specialized functions built into the LPC
47B367 I/O Controller:
♦
Power/Hard drive LED control – The I/O controller provides color and blink control for the
front panel LEDs used for indicating system events as listed below:
System Status
S0: System on (normal operation)
S1: Suspend
S3: Suspend to RAM
S4: Suspend to disk
S5: Soft off
Power LED
Steady green
Blinks green @ 1 Hz
Blinks green @ 1 Hz
Blinks green @ 0.5 Hz
Off - clear
HD LED
Green w/HD activity
Off
Off
Off
Off
Processor not seated
CPU thermal shutdown
ROM error
Power supply crowbar activated
System off
Steady red
Off
Off (system powers down)
Blinks red @ 1 Hz
Blinks red @ 0.5 Hz
Off
Off (system powers down)
Off
Off
Off
NOTE:
[1] Later systems using PCA#s 011305, 011308, or 011311 will power down for this condition.
♦
Intruder sensing – Used on Small Form Factor and Desktop models, battery-backed D-latch
logic internal to the LPC47B367 is connected to the hood sensor switch to record hood
(cover) removal.
♦
♦
Hood lock/unlock – Used on Small Form Factor and Desktop models, logic internal to the
LPC47B34x controls the lock bar mechanism.
I/O security – The parallel, serial, and diskette interfaces may be disabled individually by
software and the LPC47B367’s disabling register locked. If the disabling register is locked, a
system reset through a cold boot is required to gain access to the disabling (Device Disable)
register.
♦
♦
Processor present/speed detection – One of the battery-back general-purpose inputs (GPI26)
of the LPC47B367 detects if the processor has been removed. The occurrence of this event is
passed to the ICH2 that will, during the next boot sequence, initiate the speed selection
routine for the processor. The speed selection function replaces the manual DIP switch
configuration procedure required on previous systems.
Legacy/ACPI power button mode control – The LPC47B367 receives the pulse signal from
the system’s power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.
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Chapter 5
INPUT/OUTPUT INTERFACES
5.1
INTRODUCTION
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:
♦
♦
♦
♦
♦
♦
♦
♦
Enhanced IDE interface (5.2)
Diskette drive interface (5.3)
Serial interfaces (5.4)
page 5-1
page 5-4
page 5-8
page 5-11
page 5-16
page 5-22
page 5-26
page 5-32
Parallel interface (5.5)
Keyboard/pointing device interface (5.6)
Universal serial bus interface (5.7)
Audio subsystem (5.8)
Network interface controller (5.9)
5.2
ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into
the 82801 ICH2 component of the chipset. Two 40-pin IDE connectors (one for each controller)
are included on the system board. Each controller can be configured independently for the
following modes of operation:
♦
♦
♦
Programmed I/O (PIO) mode – CPU controls drive transactions through standard I/O mapped
registers of the IDE drive.
8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates
up to 16 MB/s.
Ultra ATA/100 mode – Preferred bus mastering source-synchronous protocol providing
transfer rates of 100 MB/s.
NOTE: These systems include 80-conductor data cables required for UATA/66 and /100
modes.
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped
registers at runtime.
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Hard drives types not found in the ROM’s parameter table are automatically configured as to
(soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66
Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive
configuration.
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5-1.
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf.
Addr.
Reset
Value
PCI Conf.
Addr.
Reset
Value
Register
Register
00-01h
02-03h
04-05h
06-07h
08h
09h
0Ah
0Bh
0Dh
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming
Sub-Class
Base Class Code
Master Latency Timer
Header Type
8086h
244Bh 20-23h
0000h
0280h
00h
80h
01h
01h
00h
0F..1Fh
Reserved
0’s
1
0000h
0000h
0’s
0’s
00h
00h
0000h
00h
BMIDE Base Address
Subsystem Vender ID
Subsystem ID
2C, 2Dh
2E, 2Fh
30..3Fh
40-43h
44h
48h
4A-4Bh
54h
Reserved
Pri./Sec. IDE Timing
Slave IDE Timing
Sync. DMA Control
Sync. DMA Timing
EIDE I/O Config.Register
0Eh
00h
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
Size
(Bytes)
Default
Value
Register
00h
02h
04h
08h
0Ah
0Ch
1
1
4
1
2
4
Bus Master IDE Command (Primary)
Bus Master IDE Status (Primary)
Bus Master IDE Descriptor Pointer (Pri.)
Bus Master IDE Command (Secondary)
Bus Master IDE Status (Secondary)
Bus Master IDE Descriptor Pointer (Sec.)
00h
00h
0000 0000h
00h
00h
0000 0000h
NOTE:
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.
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5.2.2 IDE CONNECTOR
This system uses a standard 40-pin connector for the primary IDE device and connects (via a
cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined
for UATA/33 and higher modes, which require a special 80-conductor cable (supplied) designed
to reduce cross-talk. Device power is supplied through a separate connector.
Figure 5-1. 40-Pin Primary IDE Connector (on system board).
Table 5-3.
40-Pin Primary IDE Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
RESET- Reset
Description
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
DRQ
GND
IOW-
GND
IOR-
GND
IORDY
CSEL
DAK-
GND
IRQn
IO16-
DA1
DSKPDIAG
DA0
DA2
CS0-
CS1-
Description
DMA Request
Ground
I/O Write [1]
Ground
I/O Read [2]
Ground
I/O Channel Ready [3]
Cable Select
DMA Acknowledge
Ground
Interrupt Request [4]
16-bit I/O
Address 1
Pass Diagnostics
Address 0
Address 2
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
--
Ground
Data Bit <7>
Data Bit <8>
Data Bit <6>
Data Bit <9>
Data Bit <5>
Data Bit <10>
Data Bit <4>
Data Bit <11>
Data Bit <3>
Data Bit <12>
Data Bit <2>
Data Bit <13>
Data Bit <1>
Data Bit <14>
Data Bit <0>
Data Bit <15>
Ground
9
10
11
12
13
14
15
16
17
18
19
20
NOTES:
Chip Select
Chip Select
Drive Active (front panel LED) [5]
Ground
HDACTIVE-
GND
Key
[1] On UATA/33 and higher modes, re-defined as STOP.
[2] On UATA/33 and higher mode reads, re-defined as DMARDY-.
On UATA/33 and higher mode writes, re-defined as STROBE.
[3] On UATA/33 and higher mode reads, re-defined as STROBE-.
On UATA/33 and higher mode writes, re-defined as DMARDY-.
[4] Primary connector wired to IRQ14, secondary connector wired to IRQ15.
[5] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)
when synchronous drives are connected.
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Chapter 5 Input/Output Interfaces
5.3
DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives, each of which use a common cable
connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch
1.44-MB diskette drive installed as drive A. The drive designation is determined by which
connector is used on the diskette drive cable. The drive attached to the end connector is drive A
while the drive attached to the second (next to the end) connector) is drive B.
On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O
component. The internal logic of the I/O controller is software-compatible with standard 82077-
type logic. The diskette drive controller has three operational phases in the following order:
♦
♦
♦
Command phase - The controller receives the command from the system.
Execution phase - The controller carries out the command.
Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters
of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette
drive controller and must be polled between each byte transfer during the Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.
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5.3.1 DISKETTE DRIVE PROGRAMMING
Programming the diskette drive interface consists of configuration, which occurs typically during
POST, and control, which occurs at runtime.
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected by
firmware through the PnP configuration registers of the 47B357 I/O controller during POST.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the
configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F is
initiated by firmware selecting logical device 0 of the 47B357 using the following sequence:
1. Write 07h to I/O register 2Eh.
2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration
registers are listed in the following table:
Table 5-4.
Diskette Drive Interface Configuration Registers
Index
Address
30h
60-61h
70h
74h
F0h
F1h
F2h
Reset
Value
01h
03F0h
06h
02h
02h
00h
FFh
00h
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Base Address
Interrupt Select
DMA Channel Select
DD Mode
DD Option
DD Type
F4h
F5h
DD 0
DD 1
00h
For detailed configuration register information refer to the SMSC data sheet for the LPC47B357
I/O component.
5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette
drive interface can be controlled by software through the LPC47B357’s I/O-mapped registers
listed in Table 5-5. The diskette drive controller of the LPC47B357 operates in the PC/AT mode
in these systems.
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Table 5-5.
Diskette Drive Interface Control Registers
Pri.
Sec.
Addr.
Addr.
Register
R/W
3F0h
370h
Status Register A:
R
<7> Interrupt pending
<6> Reserved (always 1)
<5> STEP pin status (active high)
<4> TRK 0 status (active high)
<3> HDSEL status (0 = side 0, 1 = side 1)
<2> INDEX status (active high)
<1> WR PRTK status (0 = disk is write protected)
<0> Direction (0 = outward, 1 = inward)
Status Register B:
<7,6> Reserved (always 1’s)
<5> DOR bit 0 status
<4> Write data toggle
<3> Read data toggle
3F1h
3F2h
371h
372h
R
<2> WGATE status (active high)
<1,0> MTR 2, 1 ON- status (active high)
Digital Output Register (DOR):
<7,6> Reserved
R/W
<5,4> Motor 1, 0 enable (active high)
<3> DMA enable (active high)
<2> Reset (active low)
<1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 = Tape drive)
Tape Drive Register (available for compatibility)
Main Status Register (MSR):
3F3h
3F4h
373h
374h
R/W
R
<7> Request for master (host can transfer data) (active high)
<6> Transfer direction (0 – write, 1 = read)
<5> non-DMA execution (active high)
<4> Command busy (active high)
<3,2> Reserved
<1,0> Drive 1, 2 busy (active high)
Data Rate Select Register (DRSR):
<7> Software reset (active high)
<6> Low power mode enable (active high)
<5> Reserved (0)
W
<4..2> Precompensation select (default = 000)
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1
Mb/s)
3F5h
375h
Data Register:
R/W
<7..0> Data
3F6h
3F7h
376h
377h
Reserved
Digital Input Register (DIR):
--
R
<7> DSK CHG status (records opposite value of pin)
<6..0> Reserved (0’s)
Configuration Control Register (CCR):
<7..2> Reserved
W
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1
Mb/s)
NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.
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5.3.2 DISKETTE DRIVE CONNECTOR
This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-6 for the pinout) for
diskette drives. Drive power is supplied through a separate connector.
2
1
4
6
5
8
7
10 12 14 16 18 20 22 24 26 28 30 32 34
11 13 15 17 19 21 23 25 27 29 31 33
9
Figure 5-2. 34-Pin Diskette Drive Connector.
Table 5-6.
34-Pin Diskette Drive Connector Pinout
Pin
1
2
Signal
GND
LOW DEN-
---
Description
Ground
Low density select
(KEY)
Pin
18
19
20
Signal
DIR-
GND
STEP-
Description
Drive head direction control
Ground
Drive head track step
control
3
4
5
6
MEDIA ID-
GND
DRV 4
SEL-
Media identification
Ground
Drive 4 select
21
22
23
GND
WR DATA-
GND
Ground
Write data
Ground
7
8
9
10
11
12
GND
INDEX-
GND
MTR 1 ON-
GND
DRV 2
SEL-
Ground
Media index is detected
Ground
Activates drive motor
Ground
Drive 2 select
24
25
26
27
28
29
WR ENABLE-
GND
TRK 00-
GND
WR PRTK-
GND
Enable for WR DATA-
Ground
Heads at track 00 indicator
Ground
Media write protect status
Ground
13
14
GND
DRV 1
SEL-
Ground
Drive 1 select
30
31
RD DATA-
GND
Data and clock read off disk
Ground
15
16
17
GND
MTR 2 ON-
GND
Ground
Activates drive motor
Ground
32
33
34
SIDE SEL-
GND
DSK CHG-
Head select (side 0 or 1)
Ground
Drive door opened indicator
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Chapter 5 Input/Output Interfaces
5.4
SERIAL INTERFACE
All models include two RS-232-C type serial interfaces to transmit and receive asynchronous
serial data with external devices. The serial interface function is provided by the LPC47B357 I/O
controller component that includes two NS16C550-compatible UARTs.
Each UART supports the standard baud rates up through 115200, and also special high speed
rates of 239400 and 460800 baud. The baud rate of the UART is typically set to match the
capability of the connected device. While most baud rates may be set at runtime, baud rates
230400 and 460800 must be set during the configuration phase.
5.4.1 SERIAL CONNECTOR
The serial port uses a DB-9 connector as shown in the following figure with the pinout listed in
Table 5-5.
Figure 5-3. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)
Table 5-7.
DB-9 Serial Connector Pinout
Pin
1
2
3
4
Signal
CD
RX Data
TX Data
DTR
Description
Pin
6
7
8
9
--
Signal
DSR
RTS
CTS
RI
Description
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
--
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Ground
5
GND
--
The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and
DCE (modem) should be followed to minimize transmission errors. Higher baud rates may require
shorter cables.
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5.4.2 SERIAL INTERFACE PROGRAMMING
Programming the serial interfaces consists of configuration, which occurs during POST, and
control, which occurs during runtime.
5.4.2.1 Serial Interface Configuration
The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also
must be activated before it can be used. Address selection and activation of the serial interface are
affected through the PnP configuration registers of the LPC47B357 I/O controller.
The serial interface configuration registers are listed in the following table:
Table 5-8.
Serial Interface Configuration Registers
Index
Address
Function
R/W
R/W
R/W
R/W
R/W
R/W
30h
60h
61h
70h
Activate
Base Address MSB
Base Address LSB
Interrupt Select
Mode Register
F0h
NOTE:
Refer to LPC47B357 data sheet for detailed register information.
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5.4.2.2 Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be directly controlled by software through the I/O-mapped registers listed in Table 5-9.
Table 5-9.
Serial Interface Control Registers
COM1
Addr.
COM2
Addr.
Register
R/W
3F8h
2F8h
Receive Data Buffer
Transmit Data Buffer
R
W
Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set)
Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set)
Interrupt Enable Register
W
W
R/W
R
3F9h
3FAh
2F9h
2FAh
Interrupt ID Register
FIFO Control Register
W
3FBh
3FCh
3FDh
3FEh
2FBh
2FCh
2FDh
2FEh
Line Control Register
Modem Control Register
Line Status Register
Modem Status
R/W
R/W
R
R
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5.5
PARALLEL INTERFACE
The legacy-light models include a parallel interface for connection to a peripheral device that has
a compatible interface, the most common being a printer. The parallel interface function is
integrated into theLPC47B277 I/O controller component and provides bi-directional 8-bit parallel
data transfers with a peripheral device. The parallel interface supports three main modes of
operation:
♦
♦
♦
Standard Parallel Port (SPP) mode
Enhanced Parallel Port (EPP) mode
Extended Capabilities Port (ECP) mode
These three modes (and their submodes) provide complete support as specified for an IEEE 1284
parallel port.
5.5.1 STANDARD PARALLEL PORT MODE
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes
of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s.
In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read
of the parallel port yields the last data byte that was written.
The following steps define the standard procedure for communicating with a printing device:
1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.
2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.
3. The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output data
while allowing a CPU read to fetch data present on the data lines, thereby providing bi-directional
parallel transfers to occur.
The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0
and A1.
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5.5.2 ENHANCED PARALLEL PORT MODE
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to
a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and
1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation
phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If
compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP
timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with
the parallel interface. Address decoding includes address lines A0, A1, and A2.
5.5.3 EXTENDED CAPABILITIES PORT MODE
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well
as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or programmed
I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is entered to
detect whether or not the connected peripheral is compatible with ECP mode. If compatible, then
ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.
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5.5.4 PARALLEL INTERFACE PROGRAMMING
Programming the parallel interface consists of configuration, which typically occurs during POST,
and control, which occurs during runtime.
5.5.4.1 Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also
must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
LPC47B357 I/O controller. Address selection and enabling are automatically done by the BIOS
during POST but can also be accomplished with the Setup utility and other software.
The parallel interface configuration registers are listed in the following table:
Table 5-10.
Parallel Interface Configuration Registers
Index
Address
Reset
Value
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
30h
60h
61h
70h
74h
F0h
F1h
00h
00h
00h
00h
04h
00h
00h
Base Address MSB
Base Address LSB
Interrupt Select
DMA Channel Select
Mode Register
Mode Register 2
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5.5.4.2 Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT 17.
The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-11
lists the parallel registers and associated functions based on mode.
Table 5-11.
Parallel Interface Control Registers
SPP
Mode
Ports
LPT1,2,3
LPT1,2,3
LPT1,2,3
EPP
Mode
Ports
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
--
ECP
Mode
Ports
LPT1,2,3
LPT1,2,3
LPT1,2,3
--
I/O
Address
Register
Base
Data
Base + 1h
Base + 2h
Base + 3h
Base + 4h
Base + 5h
Base + 6h
Base + 7h
Base + 400h
Base + 400h
Base + 400h
Base + 400h
Base + 401h
Base + 402h
Printer Status
Control
Address
Data Port 0
Data Port 1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Data Port 2
Data Port 3
Parallel Data FIFO
ECP Data FIFO
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
--
--
--
--
--
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
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5.5.5 PARALLEL INTERFACE CONNECTOR
Figure 5-5 and Table 5-12 show the connector and pinout of the parallel interface connector. Note
that some signals are redefined depending on the port’s operational mode.
Figure 5-4. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)
Table 5-12.
DB-25 Parallel Connector Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Signal
STB-
D0
D1
D2
D3
D4
D5
D6
Function
Strobe / Write [1]
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Pin
14
15
16
17
18
19
20
21
22
23
24
25
--
Signal
LF-
Function
Line Feed [2]
Error [3]
Initialize Paper [4]
ERR-
INIT-
SLCTIN-
GND
GND
GND
GND
GND
GND
GND
GND
--
Select In / Address. Strobe [1]
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
--
D7
Data 7
ACK-
BSY
PE
Acknowledge / Interrupt [1]
Busy / Wait [1]
Paper End / User defined [1]
Select / User defined [1]
SLCT
NOTES:
[1] Standard and ECP mode function / EPP mode function
[2] EPP mode function: Data Strobe
ECP modes: Auto Feed or Host Acknowledge
[3] EPP mode: user defined
ECP modes:Fault or Peripheral Req.
[4] EPP mode: Reset
ECP modes: Initialize or Reverse Req.
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Chapter 5 Input/Output Interfaces
5.6
KEYBOARD/POINTING DEVICE INTERFACE
The keyboard/pointing device interface function is provided by the LPC47B357 I/O controller
component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as
simply the “8042”) to communicate with the keyboard and pointing device using bi-directional
serial data transfers. The 8042 handles scan code translation and password lock protection for the
keyboard as well as communications with the pointing device. This section describes the interface
itself. The keyboard is discussed in the Appendix C.
5.6.1 KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in Appendix
C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action or
indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-6). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
D1
0
D2
1
D3
1
D4
0
D5
1
D6
1
Parity
1
Start
Bit
D0
(LSb)
D7
(MSb)
Stop
Bit
0
1
1
0
Data
Clock
Tcy
Tcl Tch
Parameter
Tss Tsh
Th
Minimum Maximum
Tcy (Cycle Time)
Tcl (Clock Low)
Tch (Clock High)
Th (Data Hold)
Tss (Stop Bit Setup) 8 us
Tsh (Stop Bit Hold) 15 us
0 us
25 us
25 us
0 us
80 us
35 us
45 us
25 us
20 us
25 us
Figure 5-5. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
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Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042.
Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard.
Table 5-13.
8042-To-Keyboard Commands
Command
Value
Description
Set/Reset Status Indicators
EDh
Enables LED indicators. Value EDh is followed by an
option byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Keyboard returns EEh when previously enabled.
These commands are not acknowledged.
Instructs the keyboard to select another set of scan codes
and sends an option byte after ACK is received:
01h = Mode 1
Echo
EEh
EFh/F1h
F0h
Invalid Command
Select Alternate Scan Codes
02h = Mode 2
03h = Mode 3
Read ID
F2h
F3h
Instructs the keyboard to stop scanning and return two
keyboard ID bytes.
Instructs the keyboard to change typematic rate and delay
to specified values:
Set Typematic Rate/Display
Bit <7>, Reserved - 0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Enable
F4h
F5h
F6h
Instructs keyboard to clear output buffer and last typematic
key and begin key scanning.
Resets keyboard to power-on default state and halts
scanning pending next 8042 command.
Resets keyboard to power-on default state and enable
scanning.
Default Disable
Set Default
Set Keys - Typematic
Set Keys - Make/Brake
Set Keys - Make
Set Keys - Typematic/Make/Brake
Set Type Key - Typematic
Set Type Key - Make/Brake
Set Type Key - Make
Resend
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
8042 detected error in keyboard transmission.
Resets program, runs keyboard BAT, defaults to Mode 2.
Reset
Note:
[1] Used in Mode 3 only.
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Chapter 5 Input/Output Interfaces
5.6.2 POINTING DEVICE INTERFACE OPERATION
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical
to the keyboard connector both physically and electrically. The operation of the interface (clock
and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING
Programming the keyboard interface consists of configuration, which occurs during POST, and
control, which occurs during runtime.
5.6.3.1 8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the LPC47B357 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.
The keyboard interface configuration registers are listed in the following table:
Table 5-14.
Keyboard Interface Configuration Registers
Index
Address
30h
70h
72h
Function
Activate
Primary Interrupt Select
Secondary Interrupt Select
Reset and A20 Select
R/W
R/W
R/W
R/W
R/W
F0h
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5.6.3.2 8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Sub-
functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the
keyboard’s scan codes into ASCII codes). The keyboard/pointing device interface is accessed by
the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
♦
♦
♦
♦
Output buffer reads
Input buffer writes
Status reads
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for
a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the
Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except bytes
that follow a multibyte command that was written to 64h
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by
the CPU will yield the status byte defined as follows:
Bit
7..4
3
Function
General Purpose Flags.
CMD/DATA Flag (reflects the state of A2 during a CPU write).
0 = Data
1 = Command
2
1
General Purpose Flag.
Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
0
Output Buffer Full (if set). Cleared by a CPU read of the
buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
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Table 5-15 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.
Table 5-15.
CPU Commands To The 8042
Value
20h
Command Description
Put current command byte in port 60h.
60h
Load new command byte.
A4h
Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
A5h
Load password. This multi-byte operation places a password in the 8042 using the following manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
A6h
A7h
A8h
A9h
Enable security. This command places the 8042 in password lock mode following the A5h command.
The correct password must then be entered before further communication with the 8042 is allowed.
Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock line
of the pointing device interface low.
Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the clock
line of the pointing device interface.
Test the clock and data lines of the pointing device interface and place test results in the output
buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
AAh
ABh
Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places
55h into the output buffer.
Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
ADh
AEh
C0h
Disable keyboard command (sets bit <4> of the 8042 command byte).
Enable keyboard command (clears bit <4> of the 8042 command byte).
Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port
to the output buffer so that they can be read at port 60h.
C2h
C3h
D0h
D1h
D2h
Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the
upper half of the status byte on a continous basis until another command is received.
Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the
lower half of the status byte on a continous basis until another command is received.
Read output port. This command directs the 8042 to transfer the contents of the output port to the
output buffer so that they can be read at port 60h.
Write output port. This command directs the 8042 to place the next byte written to port 60h into the
output port (only bit <1> can be changed).
Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if
it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is
generated if enabled.
D3h
Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port
60h as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.
Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.
Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t pulse).
Note that pulsing bit <0> will reset the system.
D4h
E0h
F0h-
FFh
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5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR
The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device.
Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-16 show the
connector and pinout of the keyboard/pointing device interface connectors.
Figure 5-6. Keyboard or Pointing Device Interface Connector
(as viewed from rear of chassis)
Table 5-16.
Keyboard/Pointing Device Connector Pinout
Pin
1
2
Signal
DATA
NC
Description
Data
Not Connected
Ground
Pin
4
5
6
Signal
+ 5 VDC
CLK
Description
Power
Clock
3
GND
NC
Not Connected
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Chapter 5 Input/Output Interfaces
5.7
UNIVERSAL SERIAL BUS INTERFACE
The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers of up
to 12 Mb/s with compatible peripherals such as keyboards, printers, or modems. This high-speed
interface supports hot-plugging of compatible devices, making possible system configuration
changes without powering down or even rebooting systems.
NOTE: It is recommended to run the Windows 98 (or later) operating system when
using USB peripherals, especially a USB keyboard and USB mouse. Problems may be
encountered when using USB devices with a system running Windows 95, although
some peripherals may operate satisfactorily. More information on USB compatibility and
As shown in Figure 5-8, the USB interface is provided by the 82801 ICH2 component. All models
provide two rear-panel accessible type-A USB ports. Front panel USB ports are standard on small
forma factor and all Workstation units. The Evo desktop and configurable minitower units may be
upgraded to include two front panel USB ports. For more information on the USB interface refer
to the following web site:
82801 ICH2
Rear Panel
USB Port 1
Tx/Rx Data
USB
I/F #1
Tx/Rx Data
USB Port 2
P24
Front Panel
USB Port 3
Tx/Rx Data
Tx/Rx Data
USB
I/F #2
USB Port 4
Standard on small form factor and all Workstation units.
Optional on Evo desktop and configurable minitower units.
Desktop and configurable minitower systems only.
Figure 5-7. USB I/F, Block Diagram
5.7.1 USB DATA FORMATS
The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a
1 is represented by no change (between bit times) in signal level and a 0 is represented by a
change in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a
string of 1’s is transmitted (normally resulting in a steady signal level) a 0 is inserted after every
six consecutive 1’s to ensure adequate signal transitions in the data stream.
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The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that
include two or more of seven field types.
♦
♦
Sync Field – 8-bit field that starts every packet and is used by the receiver to align the
incoming signal with the local clock.
Packet Identifier (PID) Field – 8-bit field sent with every packet to identify the attributes (in.
out, start-of-frame (SOF), setup, data, acknowledge, stall, preamble) and the degree of error
correction to be applied.
♦
♦
♦
Address Field – 7-bit field that provides source information required in token packets.
Endpoint Field – 4-bit field that provides destination information required in token packets.
Frame Field – 11-bit field sent in Start-of-Frame (SOF) packets that are incremented by the
host and sent only at the start of each frame.
♦
♦
Data Field – 0-1023-byte field of data.
Cyclic Redundancy Check (CRC) Field – 5- or 16-bit field used to check transmission
integrity.
Sync Field
(8 bits)
PID Field
(8 bits)
Addr. Field
(7 bits)
ENDP. Field
(4 bits)
CRC Field
(5 bits)
Token Packet
SOF Packet
Sync Field
(8 bits)
PID Field
(8 bits)
Frame Field
(11 bits)
CRC Field
(5 bits)
Sync Field
(8 bits)
PID Field
(8 bits)
Data Field
(0-1023 bytes)
CRC Field
(16 bits)
Data Packet
Sync Field
(8 bits)
PID Field
(8 bits)
Handshake Packet
Figure 5-8. USB Packet Formats
Data is transferred LSb first. A cyclic redundancy check (CRC) is applied to all packets (except a
handshake packet). A packet causing a CRC error is generally completely ignored by the receiver.
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Chapter 5 Input/Output Interfaces
5.7.2 USB PROGRAMMING
Programming the USB interface consists of configuration, which typically occurs during POST,
and control, which occurs at runtime.
5.7.2.1 USB Configuration
The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is
configured using PCI Configuration Registers as listed in Table 5-17.
Table 5-17.
USB Interface Configuration Registers
PCI
PCI
Config.
Addr.
Reset
Value
Config.
Addr.
Reset
Value
Register
Register
00, 01h
02, 03h
04, 05h
06, 07h
08h
09h
0Ah
0Bh
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming I/F
Sub Class Code
Base Class Code
8086h
2444h
0000h
0280h
00h
00h
03h
0Ch
0Eh
Header Type
I/O Space Base Address
Sub. Vender ID
Interrupt Line
Interrupt Pin
Serial Bus Release No.
USB Leg. Kybd./Ms. Cntrl.
USB Resume Enable
00h
1
20-23h
2C, 2Dh
3Ch
3Dh
60h
00h
00h
03h
10h
2000h
00h
C0, C1h
C4h
5.7.2.2 USB Control
The USB is controlled through I/O registers as listed in table 5-18.
Table 5-18.
USB Control Registers
I/O Addr.
00, 01h
02, 03h
04, 05h
06, 07
08, 0B
0Ch
10, 11h
12, 13h
18h
Register
Command
Status
Interupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Port 1 Status/Control
Port 2 Status/Control
Test Data
Default Value
0000h
0000h
0000h
0000h
0000h
40h
0080h
0080h
00h
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5.7.3 USB CONNECTOR
The USB interface provides two series-A connectors on the front panel and, on legacy-free
models, three series-A USB connectors on the rear panel.
1
2
3
4
Figure 5-9. Universal Serial Bus Connector
Table 5-19.
USB Connector Pinout
Pin
1
2
Signal
Vcc
USB-
Description
+5 VDC
Data (minus)
Pin
3
4
Signal
USB+
GND
Description
Data (plus)
Ground
5.7.4 USB CABLE DATA
The recommended cable length between the host and the USB device should be no longer than
sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following
table).
Table 5-20.
USB Cable Length Data
Conductor Size
20 AWG
Resistance
0.036 Ω
0.057 Ω
0.091 Ω
0.145 Ω
0.232 Ω
Maximum Length
16.4 ft (5.00 m)
9.94 ft (3.03 m)
6.82 ft (2.08 m)
4.30 ft (1.31 m)
2.66 ft (0.81 m)
22 AWG
24 AWG
26 AWG
28 AWG
NOTE:
For sub-channel (1.5 MB/s) operation and/or when using sub-standard cable
shorter lengths may be allowable and/or necessary.
The shield, chassis ground, and power ground should be tied together at the host end but left
unconnected at the device end to avoid ground loops.
Color code:
Signal
Data +
Data -
Vcc
Insulation color
Green
White
Red
Ground Black
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Chapter 5 Input/Output Interfaces
5.8
AUDIO SUBSYSTEM
The systems covered in this guide come configured with one of two types of audio support:
♦
♦
Desktop/configurable minitower audio subsystem
Small form factor audio subsystem
5.8.1 FUNCTIONAL ANALYSIS
A block diagram of the audio subsystem is shown in Figure 5-11. These systems use the AC’97
Audio Controller of the 82801 ICH2 component to access and control an Analog Devices
AD1885 Audio Codec, which provides the analog-to-digital (ADC) and digital-to-analog (DAC)
conversions as well as the mixing functions. All control functions such as volume, audio source
selection, and sampling rate are controlled through software over the PCI bus through the AC97
Audio Controller of the 82801 ICH2. Control data and digital audio streams (record and playback)
are transferred between the Audio Controller and the Audio Codec over the AC97 Link Bus.
Desktop and Configurable Minitower systems implement Business Audio, which has the codec
stereo analog output applied through a headphone jack(s) and switch logic to a mono 3-watt
amplifier that drives a 16-ohm speaker. The switch logic allows a system with two headphone
jacks equal functionality between jacks.
Small Form Factor systems feature Premier Sound, which includes a 6-level equalizer that
compensates for chassis acoustics and a low-distortion 8-watt amplifier driving a speaker.
The analog interfaces allowing connection to external audio devices include:
Mic In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for
connection of a condenser microphone with an impedance of 10-K ohms. This is the default
recording input after a system reset. On desktops and CMTs, if the front panel assembly is
installed then either microphone jack is available for use (but not simultaneously).
Line In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for
connection of a high-impedance (10k-ohm) audio source such as a tape deck.
Headphones Out - This input uses a three-conductor (stereo) mini-jack that is designed for
connecting a set of 16-ohm (nom.) stereo headphones or powered speakers. Plugging into the
Headphones jack mutes the signal to the internal speaker and, on SFF systems, the Line Out jack
as well. On desktops and CMTs, if the front panel assembly is installed then either headphone
jack is available for use (but not simultaneously).
Line Out (SFF only) - This output uses a three-conductor (stereo) mini-jack for connecting left
and right channel line-level signals (20-K ohm impedance). A typical connection would be to a
tape recorder’s Line In (Record In) jacks, an amplifier’s Line In jacks, or to powered speakers that
contain amplifiers. Plugging into the Line Out mutes the internal speaker.
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PC Beep Audio
82801 ICH2
PCI
Internal
Speaker
AC’97
Bus
AC97
Link Bus
Audio
Cntlr.
L+R (Mono)
Audio
+
TDA
7056
-
P23
(L)
Front Panel Assembly
HP Out
Audio (L/R)
(R)
Line In
CD ROM
Mic In
(L)
AD1885
Audio
Codec
Headphones/
(R)
Line Out
CD Audio (L)
CD Audio (R)
Panel En
Switch
Logic
Audio
Bias
Audio
Bias
Mic In
(L)
Headphones/
Line Out
(R)
L+R Audio
Desktop/Configurable Minitower Audio Subsystem
Small Form Factor Audio Subsystem
82801 ICH2
PC Beep Audio
PCI
Bus
AC’97
Audio
Cntlr.
AC97
Link Bus
Equalizer
Internal
Speaker
Mono
Audio
+
Audio
LA
4301
-
Bias
Mic In
Line
Sense
(L)
AD1885
Audio
Codec
Line In
(R)
Line Out Audio (L/R)
(L)
Line
Out
(R)
CD Audio (L)
CD Audio (R)
HP
Sense
CD ROM
HP Out Audio (L/R)
(L)
(R)
Headphones
Out
Optional on Evo units, standard on workstation
units.
Figure 5-10. Audio Subsystem Functional Block Diagram
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Chapter 5 Input/Output Interfaces
5.8.2 AC97 AUDIO CONTROLLER
The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the
82801 ICH component and supports the following functions:
♦
♦
♦
♦
♦
♦
Read/write access to audio codec registers
16-bit stereo PCM output @ up to 48 KHz sampling
16-bit stereo PCM input @ up to 48 KHz sampling
Acoustic echo correction for microphone
AC’97 Link Bus
ACPI power management
5.8.3 AC97 LINK BUS
The audio controller and the audio codec communicate over a five-signal AC97 Link Bus (Figure
5-12). The AC97 Link Bus includes two serial data lines (SD OUT/SD IN) that transfer control
and PCM audio data serially to and from the audio codec using a time-division multiplexed
(TDM) protocol. The data lines are qualified by a 12.288 MHz BIT_CLK signal driven by the
audio codec. Data is transferred in frames synchronized by the 48-KHz SYNC signal, which is
derived from the clock signal and driven by the audio controller. The SYNC signal is high during
the frame’s tag phase then falls during T17 and remains low during the data phase. A frame
consists of one 16-bit tag slot followed by twelve 20-bit data slots. When asserted (typically
during a power cycle), the RESET- signal (not shown) will reset all audio registers to their default
values.
T1
T2
T18
T19
T38
T39
T58
BIT_CLK
(12.288 MHz)
SYNC
(48 KHz)
Codec
Ready
SD OUT
or SD IN
Bit 15 Bit 14
it 0 Bit 19 Bit 18
it 0 Bit 19 Bit 18
it 0 Bit 19
Slot 0
(Tag)
Slot 1
(Data)
Slot 2
(Data)
Slot
Description
0
Bit 15: Frame valid bit
Bits 14-3: Slots 1-12 valid bits
Bits 2-0: Codec ID
1
2
3
Command address: Bit 19, R/W; Bits 18..12, reg. Index; Bits 11..0, reserved.
Command data
Bits 19-4: PCM audio data, left channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
4
Bits 19-4: PCM audio data, right channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
5
Modem codec data (not used in this system)
6-11
12
Reserved
I/O control
Figure 5-11. AC’97 Link Bus Protocol
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5.8.4 AUDIO CODEC
The audio codec provides pulse code modulation (PCM) coding and decoding of audio
information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13,
analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a
disk drive, routed through an analog-to-digital converter (ADC). The resulting left and right PCM
record data are muxed into a time-division-multiplexed (TDM) data stream (SD IN signal) that is
routed to the audio controller. Playback (PB) audio takes the reverse path from the audio
controller to the audio codec as SD OUT data and is decoded and processed by the digital-to-
analog converter (DAC). The codec supports simultaneous record and playback of stereo (left
and right) audio. The Sample Rate Generator may be set for sampling frequencies up to 48 KHz.
Analog audio may then be routed through 3D stereo enhancement processor or bypassed to the
output selector (SEL). The integrated analog mixer provides the computer control-console
functionality handling multiple audio inputs.
Audio
Format
Mic In
S
Rec
Data (L)
Left
Audio
e
l
e
c
t
Line In (L)
Line In (R)
Rec
Gain
ADC
ADC
SD IN
Rec
Data (R)
Right
Audio
Rec
Gain
CD In (L)
CD In (R)
o
r
AC97
Link
I/F
Sample
Rate
Gen.
Audio
Controller
Σ/Mixer
SW
PB
Data (L)
(L)
(L)
3D Proc.
3D Proc.
PB
Gain
(L)
DAC
DAC
Analog
Output
Circuits
S
E
L
SD Out
PB
Data (R)
(R)
(R)
(R)
PB
Gain
Figure 5-12. AD1885 Audio Codec Functional Block Diagram
All inputs and outputs are two-channel stereo except for the microphone input, which is inputted
as a single-channel but mixed internally onto both left and right channels. The microphone input
is the default active input. All block functions are controlled through index-addressed registers of
the codec.
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Chapter 5 Input/Output Interfaces
5.8.5 AUDIO PROGRAMMING
Audio subsystem programming consists configuration, typically accomplished during POST, and
control, which occurs during runtime.
5.8.5.1 Audio Configuration
The audio subsystem is configured according to PCI protocol through the AC’97 audio controller
function of the 82801 ICH2. Table 5-21 lists the PCI configuration registers of the audio
subsystem.
Table 5-21.
AC’97 Audio Controller
PCI Configuration Registers (82801 Device 31/Function 5)
PCI
Conf.
Addr.
Value
on
Reset
PCI
Conf.
Addr.
Value
on
Reset
Register
Register
00-01h
02-03h
04-05h
06-07h
08h
09h
0Ah
0Bh
0Eh
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming
Sub-Class
Base Class Code
Header Type
Native Audio Mixer Base Addr.
8086h
2445h
0000h
0280h
XXh
00h
01h
04h
00h
1
14-17h
18-1Bh
1C-2Bh
2C-2Dh
2E-2Fh
30-3Bh
3Ch
3Dh
3E-FFh
--
Native Audio Bus Mstr. Addr.
Reserved
Reserved
Subsystem Vender ID
Subsystem ID
Reserved
Interrupt Line
Interrupt Pin
Reserved
1
1h
1h
0000h
0000h
--
00h
02h
0’s
10-13h
--
--
5.8.5.2 Audio Control
The audio subsystem is controlled through a set of indexed registers that physically reside in the
audio codec . The register addresses are decoded by the audio controller and forwarded to the
audio codec over the AC97 Link Bus previously described. The audio codec’s control registers
(Table 5-22) are mapped into 64 kilobytes of variable I/O space.
Table 5-22.
AC’97 Audio Codec Control Registers
Value
On
Value
On
Value
On
Offset
Offset
Offset
Addr. / Register
Reset
Addr. / Register
Reset
Addr. / Register
Reset
00h Reset
0100h
8000h
--
8000h
--
8000h
8008h
8008h
8808h
8808h
14h Video Vol.
16h Aux Vol.
8808h
8808h
8808h
0000h
8000h
--
0000h
0000h
--
28h Ext. Audio ID.
2Ah Ext. Audio Ctrl/Sts
2Ch PCM DAC SRate
32h PCM ADC SRate
34h Reserved
0001h
0000h
BB80h
BB80h
--
02h Master Vol.
04h Reserved
06h Mono Mstr. Vol.
08h Reserved
0Ah PC Beep Vol.
0Ch Phone In Vol.
0Eh Mic Vol.
18h PCM Out Vol.
1Ah Record Sel.
1Ch Record Gain
1Eh Reserved
20h Gen. Purpose
22h 3D Control
24h Reserved
72h Reserved
--
74h Serial Config.
76h Misc. Control Bits
7Ch Vender ID1
7x0xh
0404h
4144h
5340h
10h Line In Vol.
12h CD Vol.
26h Pwr Mgnt.
000xh
7Eh Vender ID2
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5.8.6 AUDIO SPECIFICATIONS
The specifications for the integrated AC97 audio subsystem are listed in Table 5-23.
Table 5-23.
AC97 Audio Subsystem Specifications
Paramemter
Sampling Rate
Resolution
Measurement
5.51 KHz to 44 KHz
16 bit
Nominal Input Voltage:
Mic In (w/+20 db gain)
Line In
.283 Vp-p
2.83 Vp-p
Impedance:
Mic In
Line In
Line Out
1 K ohms (nom)
10 K ohms (min)
800 ohms
Signal-to-Noise Ratio (input to Line Out)
Max. Power Output (with 10% THD):
Small Form Factor
Slim Desktop/Configurable Minitower
Input Gain Attenuation Range
Master Volume Range
Frequency Response:
Codec
90 db (nom)
8 watts (into 8 ohms)
3 watts (into 16 ohms)
46.5 db
-94.5 db
20-20 KHz
Speaker (Small Form Factor)
450 - 4000 Hz
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Chapter 5 Input/Output Interfaces
5.9
NETWORK INTERFACE CONTROLLER
These systems include a 10/100 Mbps network interface controller (NIC) consisting of a 82562-
equivalent controller integrated into the 82801BA ICH2 component coupled with a physical
interface (PHY) component and an RJ-45 jack with integral status LEDs (Figure 5-14). The
support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or full-
duplex modes, and provides auto-negotiation of both mode and speed. Half-duplex operation
features an Intel-proprietary collision reduction mechanism while full-duplex operation follows
the IEEE 802.3x flow control specification. Transmit and receive FIFOs of 3 kilobytes each
reduce the chance of overrun while waiting for bus access.
RJ-45
Connector
Active/
Link
(Green)
82801 ICH2
Network
Interface
Function
LAN
PHY
I/F
TX/RX
TX/RX
Speed
(Yellow)
LED
Function
Green
Activity/Link: Indicates network activity and link pulse
reception.
Yellow
Speed: Indicates link detection in 100 MB/s mode
(always on if 100Base-Tx is forced).
Figure 5-13. Network Interface Controller Block Diagram
The Network Interface Controller includes the following features:
♦
♦
♦
♦
♦
♦
Fast Ethernet controller with 32-bit architecture and 3-KB TX/RX buffers.
Dual-mode support with auto-switching between 10BASE-T and 100BASE-TX.
Power down and Wake up support in both APM and ACPI environments (PME- and WOL).
Alert-on-LAN (AOL v1.0) support.
Link and Activity LED indicator drivers
AOL support for upgrade card
The controller features high and low priority queues and provides priority-packet processing for
networks that can support that feature. The controller’s micro-machine processes transmit and
receive frames independently and concurrently. Receive runt (under-sized) frames are not passed
on as faulty data but discarded by the controller, which also directly handles such errors as
collision detection or data under-run.
The NIC uses 3.3 VDC auxiliary power, which allows the controller to support Wake-On-LAN
(WOL) and Alert-On-LAN (AOL) functions while the main system is powered down.
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NOTE: For the WOL and AOL features to function as described in the following
paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit
power through a switchable power strip will, with the strip turned off, disable WOL and
AOL functionality.
5.9.1 WAKE ON LAN SUPPORT
The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that
allows the system to be booted up from a powered-down or low-power condition upon the
detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power
while the system unit is powered down in order to process special packets. The detection of a
Magic Packet by the NIC results in the PME- signal on the PCI bus to be asserted, initiating
system wake-up from an ACPI S1 or S3 state.
5.9.2 ALERT ON LAN SUPPORT
Alert-On-LAN (AOL) support allows the NIC to communicate the occurrence of certain events
over a network even while the system unit is powered off. In a system-off (powered down)
condition the network function of the 82801 ICH2 component receives auxiliary +3.3 VDC power
(derived from the +5 VDC auxiliary power from the power supply assembly). Certain events
(listed in Table 5-24) will result in the network function of the ICH2 to transmit an appropriate
pre-constructed message over the network to a system management console.
Reportable AOL events are listed in the following table:
Table 5-24.
AOL Events
Event
Description
BIOS Failure
System fails to boot successfully.
OS Problem
System fails to load operating system after POST.
Processor fails to fetch first instruction.
Thermal ASIC reports high temperature.
Indication of system’s network presence (sent approximately every 30
seconds in normal operation).
Missing/Faulty Processor
Thermal Condition
Heartbeat
The AOL implementation requirements are as follows:
1. Intel PRO/100 VM Network Connection drivers 3.80 or later (available from Compaq).
2. Intel Alert-On-LAN Utilities, version 2.5 (available from Compaq).
3. Management console running one of the following:
a. HP OpenView Network Node Manager 6.x
b. Intel LANDesk Client Manager
c. Sample Application Console from the Intel AOL Utilities (item #2 above)
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Chapter 5 Input/Output Interfaces
5.9.3 POWER MANAGEMENT SUPPORT
The NIC features Wired-for-Management (WfM) support providing system wake up from
network events (WOL) as well as generating system status messages (AOL) and supports both
APM and ACPI power management environments. The controller receives 3.3 VDC (auxiliary)
power as long as the system is plugged into a live AC receptacle, allowing support of wake-up
events occuring over a network while the system is powered down or in a low-power state.
5.9.3.1 APM Environment
The Advanced Power Management (APM) functionality of system wake up is implemented
through the system’s APM-compliant BIOS and the controller’s Magic Packet-compliant
hardware. This environment bypasses operating system (OS) intervention allowing a plugged in
unit to be turned on remotely over the network (i.e., “remote wake up”). In APM mode the
controller will respond upon receiving a Magic Packet, which is a packet where the node’s
address is repeated 16 times. Upon Magic packet detection, the controller initiates the boot
sequence.
5.9.3.2 ACPI Environment
The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is
implemented through an ACPI-compliant OS and is the default power management mode. The
following wakeup events may be individually enabled/disabled through the supplied software
driver:
♦
Magic Packet – Packet with node address repeated 16 times in data portion
NOTE: The following functions are supported in NDIS5 drivers but implemented through
remote management software applications (such as LanDesk).
♦
♦
♦
♦
Individual address match – Packet with matching user-defined byte mask
Multicast address match – Packet with matching user-defined sample frame
ARP (address resolution protocol) packet
Flexible packet filtering – Packets that match defined CRC signature
The PROSet Application software (pre-installed and accessed through the System Tray or
Windows Control Panel) allows configuration of operational parameters such as WOL and duplex
mode.
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5.9.4 NIC PROGRAMMING
Programming the NIC consists of configuration, which occurs during POST, and control, which
occurs at runtime.
5.9.4.1 Configuration
The network interface function is a PCI device and configured though PCI configuration space
registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in
the following table:
Table 5-25.
NIC Controller PCI Configuration Registers (ICH2 Device 8/Function 0)
PCI
Conf.
Addr.
00-01h
02-03h
04-05h
06-07h
08h
Value on PCI
Value
on
Reset
0000h
DCh
00h
Reset
Conf.
Register
Vender ID
Device ID
PCI Command
PCI Status
Addr.
2E, 2Fh
34h
3Ch
3Dh
Register
8086h
2449h
0000h
0290h
Xxh
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
01h
08h
Revision ID
3Eh
Min. Grant
09-0Bh
0Dh
0Eh
10-13h
14-17h
Class Code
Latency Timer
Header Type
Cntrl. Reg. Base Addr. (Mem)
Cntrl. Reg. Base Addr. (I/O)
0002h
00h
00h
8
1
3E, 3Fh
DCh
DDh
DE, DFh
E0, E1h
E3h
Max. Latency
Capability ID
Next Item Pointer
Pwr. Mgmt. Functions
Pwr. Mgmt. Cntrl./Sts
Data
38h
01h
00h
FE21h
0000h
--
2C, 2Dh Subsystem Vender ID
0000h
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.9.4.2 Control
The 82562 controller is controlled though registers that may be mapped in system memory space
or variable I/O space. The registers are listed in the following table:
Table 5-26.
NIC Control Registers
Offset
Addr. / Register
No. of
Bytes
Offset
Addr. / Register
No. of
Bytes
00h SCB Status
02h SCB Command
04h SCB General Pointer
08h PORT
0Ch Flash Control Reg.
0Eh EEPROM Control Reg.
10h Mgmt. Data I/F Cntrl. Reg.
14h Rx Direct Mem. Access Byte Cnt.
18h Early Receive Interrupt
2
2
4
4
2
2
4
4
1
19h Flow Control Register
1Bh PMDR
1Ch General Control
1Dh General Status
1E-2Fh Reserved
30h Function Event Register
34h Function Event Mask Register
38h Function Present State Register
20h Force Event Register
2
1
1
1
10
4
4
4
4
Not implemented in these systems (CardBus registers).
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Chapter 5 Input/Output Interfaces
5.9.5 NIC CONNECTOR
Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the
two status LEDs as part of the connector assembly.
Activity LED
Speed LED
Pin
1
2
3
6
Description
Transmit+
Transmit-
Receive+
Receive-
8 7 6 5 4 3 2 1
Figure 5-14. Ethernet TPE Connector (RJ-45, viewed from card edge)
5.9.6 NIC SPECIFICATIONS
Table 5-27.
NIC Specifications
Parameter
Modes Supported
10BASE-T half duplex @ 10 MB/s
10Base-T full duplex @ 20 MB/s
100BASE-TX half duplex @ 100 MB/s
100Base-TX full duplex @ 200 MB/s
IEEE 802.2
IEEE 802.3 & 802.3u
IEEE Intel priority packet (801.1p)
Standards Compliance
OS Driver Support
MS-DOS
MS Windows 3.1
MS Windows 95 (pre-OSR2), 98, and 2000
Professional
MS Windows NT 3.51 & 4.0
Novell Netware 3.x, 4.x, 5x
Novell Netware/IntraNetWare
SCO UnixWare 7
OpenServer
Boot ROM Support
F12 BIOS Support
Bus Inteface
Intel PRO/100 Boot Agent (PXE 3.0, RPL)
Yes
PCI 2.2
Power Management Support
APM, ACPI, PCI Power Management Spec.
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5.9.7 NIC UPGRADING/CHANGING
The integrated NIC may be used in conjunction with another NIC card in a PCI slot. These
systems provide AOL support for NIC cards that are AOL-compliant to the extent described
previously in section 5.9.2. These systems also provide Remote System Alert (RSA) support for
such NIC cards as the 3Com 3C905C-TX NIC card. The RSA function is similar to AOL in that
the unit provides, even while powered off, system status alert messages to a network console.
Note that NIC cards implementing the RSA method do not use the PCI/SMBus for receiving alert
information and therefore require, in addition to the PCI connection, an auxiliary cable connection
with the system as shown in Figure 5-16.
NIC Card in PCI Slot
AOL/SOS Cable
Network
Cable
AOL/SOS
Header P12
System or
Backplane
board
Figure 5-15. Remote System Alert Implementation (Generic Representation)
In the Remote System Alert implementation, the NIC card receives event notification directly
from the system’s thermal and hood sensors and the LPC47B357 I/O controller over an AOL/SOS
cable connection (Figure 5-17). During system-off conditions the NIC card receives auxiliary
power from the 3.3 VDC auxiliary power rail on the PCI bus.
System or Backplane Board
Optional NIC Card
SOS
AOL/SOS
Header
BIOS Fail
47B37x
1
OS Fail
I/O Cntlr.
Hood Sensor
NC
Intrusion
Fan
7
NC
Fan Alert
NC
Thermal
ASIC
Fan Therm.
PCI
Connector
PCI
Bus
PCI
Bus
Not connected on Configurable Minitower models.
Figure 5-16. RSA Logic, Block Diagram
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Chapter 5 Input/Output Interfaces
Reportable RSA events are listed in the following table:
Table 5-28.
Remote System Alert Events
Event
Description
BIOS Failure
System fails to boot successfully.
Thermal Condition
Thermal ASIC reports high temperature. Some systems may generate an
alert message when increasing fan speed.
Chassis Intrusion [1]
Smart Cover (hood) Sensor detected cover removal. This event is battery
backed, meaning that should the unit be unplugged (from AC power) during
cover removal, notification will occur after AC power is restored.
Indication of system’s network presence (sent approximately every 30
seconds in normal operation).
Heartbeat
NOTE:
[1] Not supported on Configurable Minitower models.
The current Remote System Alert implementation requirements are as follows:
1. 3Com Etherlink 3C905C-TX NIC.
2. 7-pin AOL/SOS cable.
3. 3Com EtherDisk Driver 5.x or later (available from Compaq).
4. Client-side utility software (included with driver).
5. Server-side utility software (called 3Com Remote System Alert Manager on the compaq.com
web site ).
6. Management console running one of the following:
a. HP OpenView Network Node Manager 6.x
b. Microsoft Systems Management Server (SMS), version 1.2
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Chapter 6
POWER and SIGNAL
DISTRIBUTION
6.1
INTRODUCTION
This chapter describes the power supply and method of general power and signal distribution.
Topics covered in this chapter include:
♦
♦
♦
Power supply assembly/control (6.2) page 6-1
Power distribution (6.3)
Signal distribution (6.4)
page 6-5
page 6-8
6.2
POWER SUPPLY ASSEMBLY/CONTROL
This system features a power supply assembly that is controlled through programmable logic
(Figure 6-1).
Front Bezel
System Board
Power On/Off
CPU, Slots, Chipsets, Logic
& Voltage Regulators
Power On
+3.3
AUX
PS Fan
On Off
Fan
Spd
+12.8 VDC
+5 VDC
+5
AUX
+5 VDC
-5 VDC
+12 VDC
-12 VDC
110/230 VAC
Drives
Power Supply
Assembly
Mains
+12 VDC
Figure 6–1. Power Distribution and Control, Block Diagram
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Chapter 6 Power and Signal Distribution
6.2.1 POWER SUPPLY ASSEMBLY
These systems feature auto-ranging power supplies with power factor-correction logic. The SFF
systems use a 175-watt supply while the desktop and configurable minitower systems employ a
250-watt supply. Tables 6-1 and 6-2 list the specifications of the power supplies.
Table 6-1.
175-Watt Power Supply Assembly Specifications (PN 243891)
Range/
Tolerance
Min. Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
Input Line Voltage:
115 - 230 VAC (auto-ranging)
Line Frequency
Constant Input (AC) Current
+3.33 VDC Output
+5 VDC Output
+3.30 AUX Output
+5.05 AUX Output
+12 VDC Output
+12.8 VDC Output (Vcpu)
-12 VDC Output
90 - 264 VAC
47 - 63 Hz
--
+/- 6 %
+/- 5 %
+/- 5 %
+/- 4 %
+/- 3 %
+/- 12 %
+/- 10 %
--
--
--
0.6 A
0.5 A
1.0 A
0.1 A
0.0 A
0.1 A
0.0 A
--
--
--
--
--
--
--
--
--
--
--
--
4.5 A
--
--
2.7 A
12.0 A
8.0 A
1.0 A
2.4 A
3.0 A
7.5 A
0.3 A
50 mV
50 mV
50 mV
50 mV
120 mV
120 mv
200 mV
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds with 12-volt tolerance +/- 10%.
Table 6-2.
250-Watt Power Supply Assembly Specifications (PN 243890)
Range/
Tolerance
Min. Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
Input Line Voltage:
115 - 230 VAC Setting
Line Frequency
Constant Input (AC) Current
+3.3 VDC Output
+5 VDC Output
+3 AUX Output
+5 AUX Output
+12 VDC Output
+12.8 VDC Output (Vcpu)
-12 VDC Output
90 - 264 VAC
47 - 63 Hz
--
--
--
--
1.0 A
1.0 A
0.0 A
0.0 A
0.1 A
0.0 A
0.0 A
--
--
--
--
--
--
--
--
3.6 A
17.0 A
11.0 A
2.20 A
1.70 A
5.00 A
7.50 A
0.15 A
+/- 5%
17.0 A
11.0 A
2.20 A
1.70 A
7.50 A
10.5 A
0.15 A
50 mV
50 mV
50 mV
50 mV
120 mV
200 mv
200 mV
+/- 5 %
+/- 5 %
+/- 4 %
+/- 5 %
+/- 5 %
+/- 10 %
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds with 12-volt tolerance +/- 10%.
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6.2.2 POWER CONTROL
The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On
is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When
PS On is de-asserted, the Power Supply Assembly is off and all voltages (except +3.3 AUX and
+5 AUX) are not generated. Note that the +3.3 AUX and +5 AUX voltages are always
produced as long as the system is connected to a live AC source.
6.2.2.1 Power Button
The PS On signal is typically controlled through the Power Button which, when pressed and
released, applies a negative (grounding) pulse to the power control logic. The resultant action of
pressing the power button depends on the state and mode of the system at that time and is
described as follows:
System State
Pressed Power Button Results In:
Off
Negative pulse, of which the falling edge results in power control logic asserting PS
On signal to Power Supply Assembly, which then initializes. ACPI four-second
counter is not active.
On, ACPI Disabled
On, ACPI Enabled
Negative pulse, of which the falling edge causes power control logic to de-assert the
PS On signal. ACPI four-second counter is not active.
Pressed and Released Under Four Seconds:
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit
within four seconds and the Suspend state is entered. If the status bit is
not cleared by software in four seconds PS On is de-asserted and the
power supply assembly shuts down (this operation is meant as a guard if
the OS is hung).
Pressed and Held At least Four Seconds Before Release:
If the button is held in for at least four seconds and then released, PS On is
negated, de-activating the power supply.
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Chapter 6 Power and Signal Distribution
6.2.2.2 Power LED Indications
A dual-color LED located on the front panel (bezel) is used to indicate system power status. The
front panel (bezel) power LED provides a visual indication of key system conditions listed as
follows:
Power LED
Condition
Steady green
Normal full-on operation
Blinks green @ 1 Hz
Blinks green @ 2 Hz
Blinks green @ 4 Hz
Steady red
Suspend state (S1)
Sleep (suspend to RAM) state (S3)
Sleep (suspend to disk) state (S4)
Processor not seated
Blinks red @ 0.5 Hz
Blinks red @ 1 Hz
Blinks red @ 4 Hz
Power supply crowbar activated
BIOS ROM error
Thermal condition: processor has overheated and shut down
6.2.2.3 Wake Up Events
The PS On signal can be activated with a power “wake-up” of the system due to the occurrence of
a magic packet, serial port ring, or PCI power management (PME) event. These events can be
individually enabled through the Setup utility to wake up the system from a sleep (low power)
state.
NOTE: Wake-up functionality requires that certain circuits receive auxiliary power
while the system is turned off. The system unit must be plugged into a live AC outlet
for wake up events to function. Using an AC power strip to control system unit power
will disable wake-up event functionality.
The wake up sequence for each event occurs as follows:
Wake-On-LAN
The network interface controller (NIC) can be configured for detection of a “Magic Packet” and
wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus.
Refer to Chapter 5, “Network Support” for more information.
Modem Ring
A ring condition on serial port A (COM1) or serial port B (COM2) can be detected by the power
control logic and, if so configured, cause the PS On signal to be asserted.
Power Management Event
A power management event that asserts the PME- signal on the PCI bus can be enabled to cause
the power control logic to generate the PS On. Note that the PCI card must be PCI ver. 2.2
compliant to support this function.
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6.2.3 POWER MANAGEMENT
These systems include power management functions designed to conserve energy. These
functions are provided by a combination of hardware, firmware (BIOS) and software. The system
provides the following power management features:
J
J
J
J
Intel Pentium III processor with SpeedStep technology
ACPI v1.0b compliant (ACPI modes C1, C2, S1, and S3, )
API 1.2 compliant
U.S. EPA Energy Star compliant
Table 6-1 shows the comparison in power states.
Table 6-1.
System Power States
Power
State
Power
Consumption
Transition
To S0 by [2]
OS Restart
Required
System Condition
G0, S0, D0
System fully on. OS and application
is running, all components.
Maximum
N/A
No
G1, S1, C1, D1
System on, CPU is executing and
data is held in memory. Some
peripheral subsystems may be on
low power. Monitor is blanked.
Low
< 2 sec after
keyboard or
pointing device
action
No
G1, S2/3, C2,
D2 (Standby/
suspend)
System on, CPU not executing,
cache data lost. Memory is holding
data, display and I/O subsystems on
low power.
Low
< 5 sec. after
keyboard,
pointing device,
or power button
action
No
G1, S4, D3
(Hibernation)
System off. CPU, memory, and
most subsystems shut down.
Memory image saved to disk for
recall on power up.
System off. All components either
completely shut down or receiving
minimum power to perform system
wake-up.
Low
Minimum
None
<25 sec. after
power button
action
Yes
Yes
—
G2, S5, D3cold
<35 sec. after
power button
action
G3
System off (mechanical). No power
to any internal components except
RTC circuit. [1]
—
NOTES:
Gn = Global state.
Sn = Sleep state.
Cn = ACPI state.
Dn = PCI state.
[1] Power cord is disconnected for this condition.
[2] Actual transition time dependent on OS and/or application software.
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Chapter 6 Power and Signal Distribution
6.3
POWER DISTRIBUTION
6.3.1 3.3/5/12 VDC DISTRIBUTION
The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5
VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive
assemblies. Figure 6-2 shows the power supply cabling for small form factor series units.
P3-P4
P4
P3
P2
To
Drive
Assemblies
1
2
3
4
P2
P5
P5
P1
4
3
2
1
2
1
To
System
Board
Power Supply
Assembly
(PN 243891)
4
3
P1
8 10 12 14
9 11 13
2
4
3
6
5
1
7
Conn.
P1
Pin 1
Pin 2
+3.3
Pin 3
RTN
Pin 4
+5
Pin 5
RTN
Pin 6
+5
Pin 7
RTN
+3.3
+3.3
+5
P1 [1]
P2, 4-7
P3
-12
GND
GND
FS
GND
+12.8
PS On +5 Aux
+12
+12.8
FC
+12
GND
NOTES:
Connectors not shown to scale.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
FC = Fan command
FO = Fan off
FSpd = Fan speed
FS = Fan Sink
[1] This row represents pins 8 - 14 of connector P1.
Figure 6–2. Small Form Factor Power Cable Diagram
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Figure 6-3 shows the cabling for the desktop and configurable minitower systems.
P8
P2
P6
P4
P7, P8
To
P7
P5
Drive
Assemblies
4
3
2
1
P2, P4-6
P3
2
1
1
2
3
4
P3
P1
4
3
To
System
Board
Power Supply
Assembly
(PN 243890)
P1
13 14 15 16 17 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9 10 11 12
Conn.
P1
P1 [1]
P2, 4-7
P3
Pin 1
Pin 2
+3.3
-12
GND
GND
Pin 3
RTN
RTN
GND
+12.8
Pin 4
+5
PS On
+12
Pin 5
RTN
RTN
Pin 6
+5
RTN
Pin 7
RTN
RTN
Pin 8
FO
-5
Pin 9
+5 Aux
+5
Pin 10
+12
+5
Pin 11
+3.3 Aux
+3.3
Pin 12
FC
FS
+3.3
+3.3
+5
GND
+12.8
NOTES:
Connectors not shown to scale.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
FO = Fan off
FSpd = Fan speed
FS = Fan Sink
FC = Fan Command
[1] This row represents pins 13 - 24 of connector P1.
Figure 6–3. Desktop and Configurable Minitower Power Cable Diagram
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Chapter 6 Power and Signal Distribution
6.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION
Voltages less than 3.3 VDC including processor core (VccP) voltage are produced through
regulator circuitry (Figure 6-4) on the system board.
+5 AUX
3.3
3.3 VDC
DIMM
Circuit
DIMMs
+5 VDC
+3.3 VDC
+12 VDC
AGP
PWR
VDDQ (1.5 VDC)
AGP Bus
2.5 S3 VDC
+1.8 VDC
+1.4 Ref
Power Supply
+3.3 VDC
DDR
Power
Circuitry
DDR DIMMs
+3 AUX
+5 VDC
+12 VDC
+12.8 Vcpu
VID0
VID1
VID2
VID3
VID4
VccP (see text)
Regulator
Circuit
Processor
Processor
Figure 6–4. Low Voltage Supply and Distribution Diagram
The VccP regulator produces the VccP (processor core) voltage according to the strapping of
signals VID4..0 by the processor. The possible voltages available are listed as follows:
VID 4..0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
VccP
VID 4..0
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
VccP
VID 4..0
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
--
VccP
2.05 VDC
2.00 VDC
1.95 VDC
1.90 VDC
1.85 VDC
1.80 VDC
1.75 VDC
1.70 VDC
1.65 VDC
1.60 VDC
1.55 VDC
1.50 VDC
1.45 VDC
1.40 VDC
1.35 VDC
1.30 VDC
3.50 VDC
3.40 VDC
3.30 VDC
3.20 VDC
3.10 VDC
3.00 VDC
2.90 VDC
2.80 VDC
2.70 VDC
2.60 VDC
2.50 VDC
2.40 VDC
2.30 VDC
2.20 VDC
2.10 VDC
No CPU
--
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6.4
SIGNAL DISTRIBUTION
Figures 6-5 and 6-6 shows general signal distribution between the main subassemblies of the
system units.
Chassis
Fan
Cover Sensor
Graphics
Controller
Audio
Fan
PWR
AGP
Bus
PCI Bus
AGP
Conn. J40
Conn.
P70
Conn.
P6
Riser
Card
(SPN 252298)
Riser
Conn.
J30
Cover Lock
Solenoid
Cover Sensor
(Optional)
Conn.
P124
Conn.
J4002
12.8 Vcpu
Power
Supply
Assembly
3/5/12 VDC, 3/5AUX
Fan Cntrl., PS On
Conn.
P1
IDE
Data, Cntl
System
Board
(PCA #011466
or 011351)
5, 12 VDC
5, 12 VDC
Pri. IDE
Conn. P20
IDE
Hard Drive
CD-ROM
IDE I/F
Sec. IDE
Conn. P21
L/R Audio
Audio
Conn. P7
Dskt.
Diskette Drive
Data, Cntl
Dsk.
Conn. P10
5, 12 VDC
Mouse
Mouse
Kybd.
Conn. J68
Keyboard
NOTES:
[1] See Figure 6-7 for header pinout.
Figure 6–5. Small Form Factor Signal Distribution Diagram
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Chapter 6 Power and Signal Distribution
Chassis
Fan
Graphics
Audio
Cover Sensor [3]
Controller
AGP
Bus
Fan
PWR
Cover Lock
Solenoid
(Optional)
Conn. Conn.
Conn.
P125
AGP
Connector
P8
P6
Power On/Off
Power On
HD Activity
Conn.
P124
Conn.
P5 [1]
Pwr Btn, Pwr/HD LED
12.8 Vcpu
Conn.
P3
Power
Supply
Assembly
3/5/12 VDC, 3/5AUX
Fan Cntrl., PS On
Conn.
P1
System
Board
(PCA #011345 or
011348)
IDE
Data, Cntl
5, 12 VDC
5, 12 VDC
Pri. IDE
Conn. P20
IDE
Hard Drive
CD-ROM
IDE I/F
Sec. IDE
Conn. P21
L/R Audio
Audio
Conn. P7
Dskt.
Diskette Drive
Data, Cntl
Dsk.
Conn. P10
5, 12 VDC
Mouse
Mouse
Kybd.
Conn. J68
Keyboard
Headphones Out
Microphone In
Audio
Conn. P23
Audio/USB
I/O Board
Assembly [2]
USB Conn.
Conn. P24
USB Data 3, USB Data 4
PCI Slot Exp.
Edge Connector
PCI Bus
PCI Slot Exp.
Card
NOTES:
] Configurable minitower only.
[1] Header pinout shown in Figure 6-7.
[2] Optional on Evo systems. Standard on Workstation systems.
[3] Sensor switch installed on desktop only.
Figure 6–6. Desktop/Minitower Signal Distribution Diagram
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Power Button/LED Header P5
HD LED Cathode
HD LED Anode
GND
1
3
5
7
9
2
4
6
8
PS LED cathode
PS LED anode
PWR Btn
M Reset
GND
+5 VDC
10 Chassis ID0
12 GND
NC 11
GND 13
NC 15
16 +5 VDC
18 GND
Chassis ID1 17
CD ROM Audio Header P7
1 Audio (Left Channel)
2 Ground
3 Ground
4 Audio (right channel)
NOTE:
No polarity consideration required for connection to speaker header P6 or SCSI HD LED header P29.
[1] Separate cable connection for these two pins (equivalent of header P29 on other systems).
Figure 6–7. Header Pinouts
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Chapter 7
BIOS ROM
7.1
INTRODUCTION
The Basic Input/Output System (BIOS) of the computer is a collection of machine language
programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such
functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power
management activities, and the Setup utility. The firmware contained in the BIOS ROM supports
the following operating systems and specifications:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
DOS 6.2
Windows 3.1 (and Windows for Workgroups 3.11)
Windows 95, 98SE, 2000, XP Professional, and XP Home
Windows NT 4.0 (SP6 required for PnP support)
OS/2 ver 2.1 and OS/2 Warp
SCO Unix
DMI 2.1
Intel Wired for Management (WfM) ver. 2.2
Alert-On-LAN (AOL) and Wake-On-LAN (WOL)
ACPI and OnNow
APM 1.2
SMBIOS 2.3.1
PC98/99/00 and NetPC
Boot Integrity Services (BIS)
Intel PXE boot ROM for the integrated LAN controller
BIOS Boot Specification 1.01
Enhanced Disk Drive Specification 3.0
“El Torito” Bootable CD-ROM Format Specification 1.0
ATAPI Removeable Media Device BIOS Specification 1.0
The BIOS ROM is a 512KB Intel Firmware Hub (or Firmware Hub-compatible) part. The runtime
portion of the BIOS resides in a 128KB block from E0000h to FFFFFh.
This chapter includes the following topics:
♦
♦
♦
♦
♦
♦
♦
ROM flashing (7.2)
Boot functions (7.3)
Setup utility (7.4)
Client management functions (7.5)
PnP support (7.6)
page 7-2
page 7-4
page 7-6
page 7-13
page 7-15
page 7-17
page 7-24
Power management functions (7.7)
USB legacy support (7.8)
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Chapter 7 BIOS ROM
7.2
ROM FLASHING
The system BIOS firmware is contained in a flash ROM device that can be re-written with BIOS
code (using the ROMPAQ utility or a remote flash program) allowing easy upgrading, including
changing the splash screen displayed during the POST routine.
7.2.1 UPGRADING
Upgrading the BIOS is not normally required but may be necessary if changes are made to the
unit’s operating system, hard drive, or processor. All BIOS ROM upgrades are available directly
from Compaq. Flashing is done either locally with the CPQFLASH Windows program, a
ROMPaq diskette or remotely using the network boot function (described in the section 7.3.2).
This system includes 64 KB of write-protected boot block ROM that provides a way to recover
from a failed flashing of the system BIOS ROM. If the BIOS ROM fails the flash check, the boot
block code provides the minimum amount of support necessary to allow booting the system from
the diskette drive and re-flashing the system ROM with a ROMPAQ diskette. Note that if an
administrator password has been set in the system the boot block will prompt for this password by
illuminating the caps lock keyboard LED and displaying a message if video support is available.
A PS/2 keyboard must be used during bootblock operation.
Since video may not be available during the initial boot sequence the boot block routine uses the
Num Lock, Caps Lock, and Scroll Lock LEDs of the PS/2 keyboard to communicate the status of
the ROM flash as follows:
Table 7-1.
Boot Block Codes
Num Lock
LED
Cap Lock
LED
Scroll Lock
LED
Meaning
Off
On
Off
On
On
Off
Off
On
Off
Off
On
On
Administrator password required.
Boot failed. Reset required for retry.
Flash failed.
Flash complete.
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7.2.2 CHANGEABLE SPLASH SCREEN
NOTE: A corrupted splash screen may be restored by the user with the ROMPAQ
software. Depending on system, changing (customizing) the splash screen is a function
may only be available though Compaq PC Customization Services.
The splash screen (image displayed during POST) is stored in the BIOS ROM and may be
replaced with another image of choice by using the Image Flash utility (Flashi.exe). The Image
Flash utility allows the user to browse directories for image searching and pre-viewing.
Background and foreground colors can be chosen from the selected image’s palette.
The splash screen image requirements are as follows:
♦
♦
♦
♦
Format:
Size:
Colors:
File Size:
Windows bitmap with 4-bit RLE encoding
424 (width) x 320 (height) pixels
16 (4 bits per pixel)
< 64 KB
The Image Flash utility can be invoked at a command line for quickly flashing a known image as
follows:
>\Flashi.exe [Image_Filename] [Background_Color] [Foreground_Color]
The utility checks to insure that the specified image meets the splash screen requirements listed
above or it will not be loaded into the ROM.
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Chapter 7 BIOS ROM
7.3
BOOT FUNCTIONS
The BIOS supports various functions related to the boot process, including those that occur during
the Power On Self-Test (POST) routine.
7.3.1 BOOT DEVICE ORDER
The default boot device order is as follows:
1. CD-ROM drive (EL Torito CD images)
2. Diskette drive (A)
3. Hard drive (C)
4. Network boot
The order can be changed in the ROM-based Setup utility (accessed by pressing F10 when so
prompted during POST).
7.3.2 NETWORK BOOT (F12) SUPPORT
The BIOS supports booting the system to a network server. The function is accessed by pressing
the F12 key when prompted at the lower right hand corner of the display during POST. Booting to
a network server allows for such functions as:
♦
♦
♦
Flashing a ROM on a system without a functional operating system (OS).
Installing an OS.
Installing an application.
These systems include, as standard, an integrated Intel 82562-equivalent NIC with Preboot
Execution Environment (PXE) ROM and can boot with a NetPC-compliant server.
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7.3.3 MEMORY DETECTION AND CONFIGURATION
This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM
configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus to
obtain data on the following DIMM parameters:
♦
♦
♦
♦
♦
Presence
Size
Type
Timing/CAS latency
PC133 capability
NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and
DIMM data specific to this system.
The BIOS performs memory detection and configuration with the following steps:
1. Program the buffer strength control registers based on SPD data and the DIMM slots that are
populated.
2. Determine the common CAS latency that can be supported by the DIMMs.
3. Determine the memory size for each DIMM and program the GMCH accordingly.
4. Enable refresh
5. Determine if the memory configuration will allow for 133MHz memory operation and
program the memory clock and MCH (see note below)
NOTE: The presence of PC133-compliant DIMMS will be indicated by BIOS reading
75h from byte 9 and 64h or 85h from byte 126. For PC133 operation to occur the FSB of
the processor must be running at 133 MHz and all installed DIMMs must be
PC133-compliant and total no more than four “sides.” Refer to Chapter 3 for more details
on PC133 operation.
7.3.4 BOOT ERROR CODES
The BIOS provides visual and audible indications of a failed system boot by using the keyboard
LEDs and the system speaker. The error conditions are listed in the following table.
Table 7-2. Boot Error Codes
Visual [1]
Audible
Meaning
Num Lock LED blinks
Scroll Lock LED blinks
Caps Lock LED blinks
1 short, 2 long beeps
2 long, 1 short beeps
1 long, 2 short beeps
System memory not present or incompatible.
Hardware failure before graphics initialization.
Graphics controller not present or failed to
initialize.
Num, Caps, Scroll Lock LEDs
blink
Num, Caps, Scroll Lock LEDs
blink in sequence
1 long, 3 short beeps
none
ROM failure.
Network service mode
NOTE:
[1] Provided with PS/2 keyboard only.
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Chapter 7 BIOS ROM
7.4
SETUP UTILITY
The Setup utility (stored in ROM) allows the user to configure system functions involving
security, power management, and system resources. The Setup utility is ROM-based and invoked
when the F10 key is pressed during the time the F10 prompt is displayed in the lower right-hand
corner of the screen during the POST routine. Highlights of the Setup utility are described in the
following table.
NOTE: Support for Computer Setup options may vary depending on your specific
hardware configuration.
Table 7-3. Setup Utility Functions
Table 7-3.
Setup Utility Functions
Heading
Option
Description
File
System Information
Lists:
Product name
Processor type/speed/stepping
Cache size (L1/L2)
Installed memory size and frequency
System ROM (includes family name and version)
System board revision
Chassis serial number
Asset tracking number
Integrated MAC for embedded, enabled NIC (if
applicable)
About
Displays copyright notice.
Set Time and Date
Save to Diskette
Allows you to set system time and date.
Saves system configuration, including CMOS, to a
blank, formatted 1.44-MB diskette.
Restore from Diskette
Set Defaults and Exit
Ignore Changes and Exit
Save Changes and Exit
Device Configuration
Restores system configuration, including CMOS,
from a diskette.
Restores factory default settings, which includes
clearing any established passwords.
Exits Computer Setup without applying or saving
any changes.
Saves changes to system configuration and exits
Computer Setup.
Lists all installed storage devices. The following
options appear when a device is selected:
Diskette Type (For legacy diskette drives only)
Identifies the highest capacity media type accepted
by the diskette drive. Options are 3.5" 1.44 MB,
3.5" 720 KB, 5.25" 1.2 MB, 5.25" 360 KB, and Not
Installed.
Storage
Drive Emulation (LS-120 and ZIP drives only)
Allows you to select a drive emulation type for a
storage device. (For example, a Zip drive can be
made bootable by selecting hard disk or diskette
emulation.)
Transfer Mode (IDE devices only)
Specifies the active data transfer mode. Options
(subject to device capabilities) are PIO 0, Max PIO,
Enhanced DMA, Ultra DMA 0, and Max UDMA.
Continued
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Table 7-3. Setup Utility Functions Continued
Heading
Option
Description
Storage
Device
Translation Mode (IDE disks only)
(continued)
Configuration
(continued)
Lets you select the translation mode to be used for the
device. This enables the BIOS to access disks partitioned
and formatted on other systems and may be necessary for
users of older versions of Unix (e.g., SCO Unix version 3.2).
Options are Bit-Shift, LBA Assisted, User, and None.
CAUTION: Ordinarily, the translation mode
selected automatically by the BIOS should not
be changed. If the selected translation mode is
not compatible with the translation mode that
was active when the disk was partitioned and
formatted, the data on the disk will be
inaccessible.
Translation Parameters (IDE Disks only)
Allows you to specify the parameters (logical cylinders,
heads, and sectors per track) used by the BIOS to translate
disk I/O requests (from the operating system or an
application) into terms the hard drive can accept. Logical
cylinders may not exceed 1024. The number of heads may
not exceed 256. The number of sectors per track may not
exceed 63. These fields are only visible and changeable
when the drive translation mode is set to User.
Multisector Transfers (IDE ATA devices only)
Specifies how many sectors are transferred per multi-sector
PIO operation. Options (subject to device capabilities) are
Disabled, 8, and 16.
Quiet Drive (available on select drives only)
Performance - Allows the drive to operate at maximum
performance.
Quiet (will not be displayed if not supported by drive)-
Reduces noise from the drive during operation. When set to
Quiet, the drive will not operate at maximum performance.
Removable Media Boot
Enables/disables ability to boot the system from removable
media.
Storage Options
Note: After saving changes to Removable Media Boot, the
computer will restart. Turn the computer off, then on,
manually.
Removable Media Write
Enables/disables ability to write data to removable media.
Note: This feature applies only to legacy diskette, IDE LS-120
Superdisk, and IDE PD-CD drives.
Primary IDE Controller
Allows you to enable or disable the primary IDE controller.
Secondary IDE Controller
Allows you to enable or disable the secondary IDE controller.
Diskette MBR Validation
Allows you to enable or disable strict validation of the diskette
Master Boot Record (MBR).
Note: If you use a bootable diskette image that you know to
be valid, and it does not boot with Diskette MBR Validation
enabled, you may need to disable this option in order to use
the diskette.
Continued
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Chapter 7 BIOS ROM
Table 7-3. Setup Utility Functions Continued
Option
Description
Heading
Storage
(continued)
DPS Self-Test
Allows user to execute self-tests on IDE hard drives
capable of performing the Drive Protection System
(DPS) self-tests.
Note: This selection will only appear when at least one
drive capable of performing the IDE DPS self-tests is
attached to the system
Boot Order
Allows user to specify the order in which attached
peripheral devices (such as diskette drive, hard drive,
CD-ROM, or network interface card) are checked for a
bootable operating system image. Each device on the
list may be individually excluded from or included for
consideration as a bootable operating system source.
Note: MS-DOS drive lettering assignments may not
apply after a non-MS-DOS operating system has started.
To boot one time from a device other than the default
device specified in Boot Order, restart the computer and
press F9 when the F10=Setup message appears on the
screen. When POST is completed, a list of bootable
devices is displayed. Use the arrow keys to select a
device and press the Enter key.
Security
Setup Password
Allows user to set and enable setup (administrator)
password.
Note: If the setup password is set, it is required to
change Computer Setup options, flash the ROM, and
make changes to certain plug and play settings under
Windows. Also, this password must be set in order to
use some Compaq remote security tools.
See the Troubleshooting Guide for more information.
Allows user to set and enable power-on password.
See the Troubleshooting Guide for more information.
Allows user to:
Power-On Password
Password Options
Enable/disable network server mode.
Note: This selection will appear only if a power-on
password is set.
Specify whether password is required for warm boot
(CTRL+ALT+DEL).
Note: This selection is available only when Network
Server Mode is disabled.
See the Desktop Management Guide for more
information.
Smart Cover
Allows user to:
Enable/disable the Smart Cover Lock
Enable/disable Smart Cover Sensor.
Notify User alerts the user that the sensor has
detected that the cover has been removed. Setup
Password requires that the setup password be
entered to boot the computer if the sensor detects that
the cover has been removed.
Feature supported on select models only. Refer to the
Desktop Management Guide for more information.
Continued
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Table 7-3. Setup Utility Functions Continued
Heading
Option
Description
Security
(continued)
Master Boot Record Security
Allows user to enable or disable Master Boot
Record (MBR) Security. When enabled, the BIOS
rejects all requests to write to the MBR on the
current bootable disk. Each time the computer is
powered on or rebooted, the BIOS compares the
MBR of the current bootable disk to the previously-
saved MBR. If changes are detected, you are given
the option of saving the MBR on the current
bootable disk, restoring the previously-saved MBR,
or disabling MBR Security. You must know the
setup password, if one is set.
Note: Disable MBR Security before intentionally
changing the formatting or partitioning of the
current bootable disk. Several disk utilities (such as
FDISK and FORMAT) attempt to update the MBR.
If MBR Security is enabled and disk accesses are
being serviced by the BIOS, write requests to the
MBR are rejected, causing the utilities to report
errors. If MBR Security is enabled and disk
accesses are being serviced by the operating
system, any MBR change will be detected by the
BIOS during the next reboot, and an MBR Security
warning message will be displayed.
Save Master Boot Record
Saves a backup copy of the Master Boot Record of
the current bootable disk.
Note: Only appears if MBR Security is enabled.
Restores the backup Master Boot Record to the
current bootable disk.
Restore Master Boot Record
Note: Only appears if all of the following conditions
are true:
MBR Security is enabled
A backup copy of the MBR has been previously
saved
The current bootable disk is the same disk from
which the backup copy of the MBR was saved.
Device Security
Enables/disables serial, parallel, and USB ports
and audio security.
Network Service Boot
Enables/disables the computer’s ability to boot from
an operating system installed on a network server.
(Feature available on NIC models only; the network
controller must reside on the PCI bus or be
embedded on the system board.)
System IDs
Allows user to set:
Asset tag (16-byte identifier) and Ownership Tag
(80-byte identifier displayed during POST) -
Refer to the Desktop Management guide for
more information
Chassis serial number or Universal Unique
Identifier (UUID) number - If current number is
invalid (these ID numbers are normally set in the
factory and are used to uniquely identify the
system)
Keyboard locale setting (e.g., English or
German) for System ID entry.
Continued
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Chapter 7 BIOS ROM
Table 7-3. Setup Utility Functions Continued
Option
Description
Heading
Power
Energy Saver
Allows user to set the energy saver mode
(advanced, disable, or minimal).
Note: In the minimal energy saver mode setting, the
hard drive and system do not go into energy saver
mode, but the setting allows you to press the power
button to suspend the system.
This option is not available under ACPI-enabled
operating systems.
Timeouts
Allows user to disable or manually select timeout
values for the system and/or all attached IDE hard
drives.
Note: This option has no effect under ACPI-enabled
operating systems. This selection will only appear
when energy saver mode is set to advanced.
Allows user to set:
Energy Saver Options
Power button configuration (on/off or sleep/wake)
under
APM-enabled operating systems
Power LED blink in suspend mode
(enable/disable). This option is not available under
ACPI-enabled operating systems.
Note: Energy Saver Options will not appear if the
energy saver mode is disabled.
Advanced
(Advanced
users only)
Power-On Options
Allows user to set:
POST mode (QuickBoot, FullBoot, or FullBoot
every 1-30
days)
POST messages (enable/disable)
Safe POST (enable/disable)
F10 prompt (enable/disable)
F12 prompt (enable/disable)
Option ROM prompt (enable/disable)
Remote wakeup boot sequence (remote
server/local hard drive)
After power loss (off/on)
If you connect your computer to an electric power
strip, and would like to turn on power to the
computer using the switch on the power strip, set
this option to on.
Note: If you turn off power to your computer
using the switch on a power strip, you will not
be able to use the suspend/sleep feature or the
Remote Management features.
UUID (Universal Unique Identifier) (enable/disable)
Onboard Devices
PCI Devices
Allows you to set resources for or disable onboard
system devices (diskette controller, serial port,
parallel port).
Lists currently installed PCI devices and their IRQ
settings.
Allows you to reconfigure IRQ settings for these
devices or to disable them entirely.
Continued
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Table 7-3. Setup Utility Functions Continued
Heading
Option
Description
Advanced
(continued)
Bus Options
Allows user to enable or disable:
PCI bus mastering, which allows a PCI device
to take control of the PCI bus
PCI VGA palette snooping, which sets the VGA
palette snooping bit in PCI configuration
space; this is only needed with more than
one graphics controller installed
PCI SERR# Generation.
Device Options
Allows user to set:
Printer mode (bi-directional, EPP & ECP,
output only)
Num Lock state at power-on (off/on)
PME (power management event) wakeup
events (enable/disable)
Processor cache (enable/disable)
Processor Number (enable/disable) for Pentium
III processors.
ACPI S3 support (enable/disable). S3 is an
ACPI (advanced configuration and power
interface) sleep state that some add-in
hardware options may not support.
AGP Aperture size (options vary depending on
platform) allows you to modify the size of
your AGP aperture size window.
Appears only if there are multiple PCI video
adapters in the system. Allows users to specify
which VGA controller will be the “boot” or primary
VGA controller.
PCI VGA Configuration
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7.5
CLIENT MANAGEMENT FUNCTIONS
Table 7-4 lists the client management BIOS functions supported by the systems covered in this
guide. These functions, designed to support intelligent manageability applications, are Compaq-
specific unless otherwise indicated.
Table 7-4.
Client Management Functions (INT15)
AX
Function
Get system ID
Get monitor data
Mode
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real
E800h
E813h
E814h
E816h
E817h
E818h
E819h
E820h [1]
E81Ah
E81Bh
E81Eh
E827h
NOTE:
Get system revision
Get temperature status
Get drive attribute
Get drive off-line test
Get chassis serial number
Get system memory map
Write chassis serial number
Get hard drive threshold
Get hard drive ID
Real
Real, 16-, & 32-bit Prot.
Real
Real
Real
Real
DIMM EEPROM Access
Real, 16-, & 32-bit Prot.
[1] Industry standard function.
All 32-bit protected-mode functions are accessed by using the industry-standard BIOS32 Service
Directory. Using the service directory involves three steps:
1. Locating the service directory.
2. Using the service directory to obtain the entry point for the client management functions.
3. Calling the client management service to perform the desired function.
The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the
physical address range of 0E0000h-0FFFFFh. The format is as follows:
Offset No. Bytes
Description
00h
04h
08h
09h
0Ah
0Bh
4
4
1
1
1
5
Service identifier (four ASCII characters)
Entry point for the BIOS32 Service Directory
Revision level
Length of data structure (no. of 16-byte units)
Checksum (should add up to 00h)
Reserved (all 0s)
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To support Windows NT an additional table to the BIOS32 table has been defined to contain 32-
bit pointers for the DDC locations. The Windows NT extension table is as follows:
; Extension to BIOS SERVICE directory table (next paragraph)
db
db
db
dd
dw
db
dd
dw
“32OS”
2
“$DDC”
?
; sig
; number of entries in table
; DDC POST buffer sig
; 32-bit pointer
; byte size
; ESCD sig
; 32-bit pointer
; bytes size
?
“$ERB”
?
?
The service identifier for client management functions is “$CLM.” Once the service identifier is
found and the checksum verified, a FAR call is invoked using the value specified at offset 04h to
retrieve the CM services entry point. The following entry conditions are used for calling the
Desktop Management service directory:
INPUT:
EAX
= Service Identifier [$CLM]
EBX (31..8)
EBX (7..0)
CS
= Reserved
= Must be set to 00h
= Code selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. CS is execute/read.
= Data selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. DS is read only.
= Stack selector must provide at least 1K of stack space and be 32-bit.
DS
SS
(I/O permissions must be provided so that the BIOS can support as necessary)
OUTPUT:
AL
= Return code:
00h, requested service is present
80h, requested service is not present
81h, un-implemented function specified in BL
86h and CF=1, function not supported
EBX
ECX
EDX
= Physical address to use as the selector BASE for the service
= Value to use as the selector LIMIT for the service
= Entry point for the service relative to the BASE returned in EBX
The following subsections provide a brief description of key Client Management functions.
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7.5.1 SYSTEM ID AND ROM TYPE
Applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This
function will return the system ID in the BX register. These systems have the following IDs and
ROM family types:
System
System ID
ROM Family
PnP ID
Small Form Factor
SDR SDRAM
DDR SDRAM
Desktop
788h
78Ch
686Y2
686Y2
CPQ0042
CPQ0042
SDR SDRAM
DDR SDRAM
Configurable Minitower
SDR SDRAM
DDR SDRAM
77Ch
784h
686Y2
686Y2
CPQ003E
CPQ0040
77Ch
784h
686Y2
686Y2
CPQ003F
CPQ0041
The ROM family and version numbers can be verified with the Setup utility or the Compaq
Insight Manager or Diagnostics applications.
7.5.2 EDID RETRIEVE
The BIOS function INT 15, AX=E813h is a tri-modal call that retrieves the VESA extended
display identification data (EDID). Two subfunctions are provided: AX=E813h BH=00h retrieves
the EDID information while AX=E813h BX=01h determines the level of DDC support.
Input:
AX
BH
BH
= E813h
= 00 Get EDID .
= 01 Get DDC support level
If BH = 00 then
DS:(E)SI = Pointer to a buffer (128 bytes) where ROM will return block
If 32-bit protected mode then
DS:(E)SI = Pointer to $DDC location
Output:
(Successful)
If BH
= 0:
DS:SI=Buffer with EDID file.
= Number of bytes written
= 0
CX
CF
AH
=00h Completion of command
If BH
BH
= 1:
= System DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
= Monitor DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
<2>=1 Screen blanked during transfer
BL
(Failure)
CF
AH
= 1
= 86h or 87h
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7.5.3 TEMPERATURE STATUS
The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system’s interior
temperature. This function allows an application to check whether the temperature situation is at a
Normal, Caution, or Critical condition.
7.5.4 DRIVE FAULT PREDICTION
The Compaq BIOS directly supports Drive Fault Prediction for IDE-type hard drives. This feature
is provided through two Client Management BIOS calls. Function INT 15, AX=E817h is used to
retrieve a 512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve
the drive’s warranty threshold data. If data is returned indicating possible failure then the
following message is displayed:
“1720-SMART Hard Drive detects imminent failure”
7.6
PNP SUPPORT
The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A. Table 7-5 lists the PnP
functions supported.
Table 7-5.
PnP BIOS Functions
Function Register
00h
01h
02h
03h
04h
50h
51h
Get number of system device nodes
Get system device node
Set system device node
Get event
Send message
Get SMBIOS Structure Information
Get Specific SMBIOS Structure
The BIOS call INT 15, AX=E841h, BH=01h can be used by an application to retrieve the default
settings of PnP devices for the user. The application should use the following steps for the display
function:
1. Call PnP function 01(get System Device Node) for each devnode with bit 1 of the control flag
set (get static configuration) and save the results.
2. Call INT 15, AX=E841h, BH=01h.
3. Call PnP “Get Static Configuration” for each devnode and display the defaults.
4. If the user chooses to save the configuration, no further action is required. The system board
devices will be configured at the next boot. If the user wants to abandon the changes, then the
application must call PnP function 02 (Set System Device Node) for each devnode (with bit 1
of the control flag set for static configuration) with the results from the calls made prior to
invoking this function.
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7.6.1 SMBIOS
In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the
SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and
SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS
version 2.3.1 and the following structure types:
Type
0
Data
BIOS Information
1
System Information
3
4
7
System Enclosure or Chassis
Processor Information
Cache Information
8
9
Port Connector Information
System Slots
13
15
16
17
19
20
31
32
BIOS Language Information
System Event Log Information
Physical Memory Array
Memory Devices
Memory Array Mapped Addresses
Memory Device Mapped Addresses
Boot Integrity Service Entry Point
System Boot Information
128 OEM Defined Structure with Intel Alert-On-LAN (AOL) Information
NOTE: System information on these systems is handled exclusively through the
SMBIOS. The System Information Table (SIT) method (and it’s associated BIOS
functions) used on previous systems is no longer supported.
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7.7
POWER MANAGEMENT FUNCTIONS
The BIOS ROM provides three types of power management support: independent PM support;
APM support, and ACPI support.
7.7.1 INDEPENDENT PM SUPPORT
The BIOS can provide power management (PM) of the system independently from an operating
system that doesn’t support APM (including DOS, Unix, NT & older versions of OS/2). In the
Independent PM environment the BIOS and hardware timers determine when to switch the system
to a different power state. State switching is not reported to the OS.
7.7.1.1 Staying Awake In Independent PM
There are two "Time-out to Standy" timers used in independent PM: the System Timer
and the IDE Hard Drive Timer.
System Timer
In POST, the BIOS enables a timer in the ICH that generates an SMI once per minute. When the
BIOS detects the SMI it checks status bits in the ICH for device activity. If any of the device
activity status bits are set at the time of the 1-minute SMI, BIOS resets the time-out minute
countdown. The system timer can be configured through the Setup utility for counting down 0, 5,
10, 15, 20, 30, 40, 50, 60, 120, 180, or 240 minutes. The following devices are checked for
activity:
♦
♦
♦
♦
♦
Keyboard
Mouse
Serial port(s)
Parallel port
IDE primary controller
NOTE: The secondary controller is NOT included. This is done to support auto-
sense of a CD-ROM insertion (auto-run) in case Windows or NT is running.
Note also that SCSI drive management is the responsibility of the SCSI driver.
Any IDE hard drive access resets the hard drive timer.
IDE Hard Drive Timer
During POST, an inactivity timer each IDE hard drive is set to control hard drive spin down.
Although this activity is independent of the system timer, the system will not go to sleep until the
primary IDE controller has been inactive for the system time-out time. The hard drive timer can
be configured through the Setup utility for being disabled or counting down 10, 15, 20, 30, 60,
120, 180, or 240 minutes, after which time the hard drive will spin down.
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7.7.1.2 Going to Sleep in Independent PM
When a time-out timer expires, Standby for that timer occurs.
System Standby
When the system acquires the Standby mode the BIOS blanks the screen. Since the hard
drive inactivity timer is in the drive and triggered by drive access, the system can be in
Standby with the hard drives still spinning (awake).
NOTE: The BIOS does not turn the fan(s) off (as on previous products).
IDE Hard Drive Standby
During hard drive standby the platters stop spinning. Depending on drive type, some hard drives
will also cut power to some of the drive electronics that are not needed. The drives can be in this
state with the system still awake.
7.7.1.3 Suspend
Suspend is not supported in the Independent PM mode.
7.7.1.4 System OFF
When the system is turned Off but still plugged into a live AC outlet the NIC, ICH2, and I/O
components continue to receive auxiliary power in order to power-up as the result of a Magic
Packet™ being received over a network. Some NICs are able to wake up a system from Standby
in PM, most require their Windows/NT driver to reset them after one wake-up.
7.7.1.5 Waking Up in Independent PM
Activity of either of the following devices will cause the system to wake up with the screen
restored:
♦
♦
Keyboard
Mouse (if driver installed)
The hard drive will not spin up until it is accessed. Any hard drive access will cause it to wake up
and resume spinning. Since the BIOS returns to the currently running software, it is possible for
the drive to spin up while the system is in Standby with the screen blanked.
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7.7.2 ACPI SUPPORT
This system meets the hardware and firmware requirements for being ACPI compliant.
This system supports the following ACPI functions:
♦
♦
♦
♦
♦
♦
♦
PM timer
Power button
Power button override
RTC alarm
Sleep/Wake logic (S1,S3, S4 (Windows 2000), S5)
C1 state (Halt)
PCI Power Management Event (PME)
7.7.3 APM 1.2 SUPPORT
Advanced Power Management (APM) is an extension of power management. In APM, the O/S
decides when a transition to another power state should occur. If going to Standby or Suspend, it
notifies all APM-aware drivers requesting approval for the state change. If all drivers approve (the
BIOS is not involved in this process) each is instructed to go to that state, then the BIOS is told to
go to that state. All versions of Windows, later versions of OS/2 and Linux support APM. . The
BIOS ROM for these systems support APM 1.2
The APM functions are initialized when the O/S loads. An INT 15h call is made to see if APM is
supported by the BIOS, and at what level (1.0, 1.1 or 1.2). After that, the O/S gets a 32-bit address
from the BIOS ROM so it can subsequently make 32 bit protected mode calls to access the
different APM functions in the ROM.
Table 8-6 lists all the APM calls that the O/S can make to the BIOS. These functions are the major
difference between PM and APM.
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Table 7-6.
APM BIOS Functions
Description
APM BIOS Function
APM Installation Check
Allows the O/S to determine if the system's BIOS supports
the APM functionality and if so, which version of the
specification it supports. The APM version number
returned from this call is the highest level of APM
supported by the BIOS.
APM Real Mode Interface
Connect
Establishes the cooperative interface between the O/S and the
BIOS. The BIOS provides OEM-defined power management
functionality before the interface is established. Once the interface
is established, the BIOS and the O/S Driver coordinate power
management activities. The BIOS rejects an interface connect
request if any real or protected mode connection already exists.
Initializes the 16-bit protected mode interface between the O/S and
the BIOS. This interface allows a protected mode caller to invoke
the BIOS functions without first switching into real or virtual-86
mode. This function must be invoked in real mode. This is not
currently used by any O/S.
APM Protected Mode 16-bit
APM Protected Mode 32-bit
APM Interface Disconnect
Iinitializes the 32-bit protected mode interface between the O/S and
the BIOS. This interface allows a protected mode O/S to invoke the
BIOS functions without the need to first switch into real or virtual-86
mode. This function must be invoked in real mode.
Breaks the cooperative connection between the BIOS and the O/S,
and returns control of the power management policy to the BIOS.
Power management parameter values (timer values, enable/disable
settings, etc.) in effect at the time of the disconnect remain in effect.
The O/S uses this call to tell BIOS that the system is idle.
Informs the BIOS that the O/S has determined that the system is
now busy. The BIOS should restore the CPU clock rate to full
speed.
CPU Idle
CPU Busy
Set Power State
Sets the system or device specified in the power device ID into the
requested power state.
Enable/Disable Power
Management
Enables or disables all APM BIOS automatic power management.
When disabled, the BIOS does not automatically power manage
devices, enter the Standby State, enter the Suspend State, or take
power saving steps in response to CPU Idle calls.
Restore Power-On Defaults
Get Power Status
Re-initializes all power-on defaults.
This call returns the system current power status.
Get PM Event
Returns the next pending PM event, or indicates if no PM events
are pending.
Get Power State
Enable/Disable Device PM
Returns the device power state when a specific device ID is used.
Enables or disables APM BIOS automatic power management for a
specified device. When disabled, the APM BIOS does not
automatically power manage the device.
APM Driver Version
Engage/Disengage PM
Get Capabilities
The O/S uses this call to indicate its level of APM support to the
BIOS. The BIOS returns the APM connection version number.
Engages or disengages cooperative power management of the
system or device.
Returns the features which this particular APM 1.2 BIOS
implementation supports.
Get/Set/Disable Resume
Timer
This call gets, sets, or disables the system resume timer.
Enable/Disable Resume on
Ring
Enable/Disable Timer Based
Request
Enables or disables the system's resume on ring indicator
functionality. It also returns the enabled/disabled status.
Enables or disables the BIOS's generation of global Standby and
global Suspend requests based on inactivity timers.
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7.7.3.1 Staying Awake in APM
There are two "Time-out to Standby" timers used in APM: the System Timer and the IDE
had Drive Timer.
System Timer
In POST, the ROM enables a timer in the ICH2 that generates an SMI once per minute.
When the ROM gets the SMI it checks status bits in the ICH2 for activity at any of the
following devices:
♦
♦
♦
♦
♦
Keyboard
Mouse
Serial port(s)
Parallel port
IDE primary controller
NOTE: The secondary controller is NOT included in order to support auto-
sense of a CD-ROM insertion (auto-run) in case Windows or NT is running.
Note also that management of SCSI drives is the responsibility of the SCSI
driver. Any IDE hard drive access resets the hard drive timer.
If any of the activity status bits are set when the ROM gets the 1-minute SMI, it resets its
time-out minute countdown according to the value (0 (default), 5, 10, 15, 20, 30, 40, 50,
60, 120, 180, or 240 minutes) selected in the Setup utility (F10).
IDE Hard Drive Timer
During POST, an inactivity timer in the IDE hard drive controller is set to control hard
drive spin down. This activity is independent of the system timer. The BIOS will not
inform the O/S that it is time to go to sleep until there has been no IDE primary activity
for the system time-out time. The IDE hard drive will spin down when its timer expires
according to the countdown time (0 (disabled), 10, 15, 20, 30, 60, 120, 180, or 240
minutes) selected in the Setup utility (F10).
NOTE: The O/S (Win98 and later) can use the "Enable/Disable Timer Based Request"
APM BIOS call to disable the system timer the BIOS uses so that the O/S can have direct
control of the timing.
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7.7.3.2 Going to Sleep in APM
There are three levels of system sleep in APM: System/Hard Drive Standby, System
Suspend, and System Off.
System/Hard Drive Standby
System Standby is achieved only by a system timer time-out, at such time the following
occurs:
1. All APM-aware device drivers put their respective devices into “Device Standby.”
2. The O/S makes a BIOS call to go into System Standby.
NOTE: The BIOS ROM of these systems will not turn the fan(s) off as on
previous systems).
If the hard drive timer times out due to inactivity the hard drive motor stops spinning the
platters. Depending on drive type, some drives can cut power to some of the drive
electronics that are not needed during standby. The drive(s) can be in this state with the
system still awake. Since the hard drive timer is in the hard drive controller and triggered
by drive access, the system can be in Standby with the hard drive(s) still spinning
(awake).
System Suspend
System Suspend is invoked by pressing and releasing the power switch in under four
seconds (pressing and holding the switch longer that four seconds will turn the system
off).. The system does not time-out from Standby into Suspend.
Upon invoking Suspend, the following actions occur:
1. All APM-aware device drivers put their associated devices into “Device Standby.”
2. The O/S makes a BIOS call to go into Standby, and the BIOS:
a. Spins down the IDE drives
b. Halts the processor. The processor remains halted until the next 55ms tick from
the RTC.
c. At the 55ms tick of the RTC the processor executes a BIOS routine to check to
see if anything has happened to wake the system up. If not, the processor is
halted again.
d. Steps B and C are repeated until a wake-up event occurs.
NOTE: These systems will not turn the fan(s) off as in previous systems.
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System OFF
There are two ways to turn the system off:
1. Software shut-down as directed by the O/S. This, being the normal procedure, allows
a NIC driver to re-arm the NIC for a Magic Packet™
2. Press and hold the power button for longer than 4 seconds (not recommended unless
necessary).
7.7.3.3 Waking Up in APM
Any of the following activities will cause the system to wake up:
♦
♦
♦
♦
♦
Keyboard
Mouse
Ring Indicate
RTC alarm
Magic Packet
The hard drive will not spin up until it is accessed. Any hard drive access will cause it to
wake up and resume spinning. Since the BIOS returns to the currently running software,
it is possible for the drive to spin up while the system is in Standby with the screen
blanked.
7.8
USB LEGACY SUPPORT
The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This
allows a system with only a USB keyboard to be used during ROM-based setup and also on a
system with an OS that does not include a USB driver.
On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data
from the device and convert it to PS/2 data. The data will be passed to the keyboard controller and
processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB keyboard
though BIOS function INT 16 is not supported.
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Appendix A
ERROR MESSAGES AND CODES
A.1 INTRODUCTION
This appendix lists the error codes and a brief description of the probable cause of the error.
NOTE: Errors listed in this appendix are applicable only for systems running Compaq
BIOS.
NOTE: Not all errors listed in this appendix may be applicable to a particular system
model and/or configuration.
A.2 BEEP/KEYBOARD LED CODES
Table A-1.
Beep/Keyboard LED Codes
Beeps
LED [1]
Probable Cause
1 short, 2 long
1 long, 2 short
2 long, 1 short
1 long, 3 short
None
NUM lock blinking
CAP lock blinking
Scroll lock blinking
(None)
All three blink in sequence
NUM lock steady on
Base memory failure.
Video/graphics controller failure.
System failure (prior to video initialization).
Boot block executing
Keyboard locked in network mode.
ROMPAQ diskette not present, bad, or drive not
ready.
None
None
None
None
CAP lock steady on
All three blink together
All three steady on
Password prompt.
ROM flash failed.
Successful ROM flash.
NOTE:
[1] PS/2 keyboard only.
Compaq Personal Computers
A-1
Changed – November 2000
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Appendix A Error Messages and Codes
A.3 POWER-ON SELF TEST (POST) MESSAGES
Table A-2.
Power-On Self Test (POST) Messages
Error Message
Probable Cause
Invalid Electronic Serial Number
Network Server Mode Active (w/o
kybd)
Chassis serial number is corrupt. Use Setup to enter a valid number.
System is in network mode.
101-Option ROM Checksum Error
102-system Board Failure
150-Safe POST Active
162-System Options Not Set
163-Time & Date Not Set
164-Memory Size Error
A device’s option ROM has failed/is bad.
Failed ESCD write, A20, timer, or DMA controller.
An option ROM failed to execute on a previous boot.
Invalid checksum, RTC lost power, or invalid configuration.
Date and time information in CMOS is not valid.
Memory has been added or removed.
201-Memory Error
Memory test failed.
213-Incompatible Memory Module
216-Memory Size Exceeds Max
301-Keyboard Error
303-Keyboard Controller Error
304-Keyboard/System Unit Error
404-Parallel Port Address Conflict
510-Slpash Image Corrupt
601-Diskette Controller Error
BIOS detected installed DIMM(s) as being not compatible.
Installed memory exceeds the maximum supported by the system.
Keyboard interface test failed (improper connection or stuck key).
Keyboard buffer failed empty (8042 failure or stuck key).
Keyboard controller failed self-test.
Current parallel port address is conflicting with another device.
Corrupted splash screen image. Restore default image w/ROMPAQ.
Diskette drive removed since previous boot.
912-Computer Cover Removed Since Cover (hood) removal has been detected by the Smart Cover Sensor.
Last System Start Up
917-Expansion Riser Not Detected
1720-SMART Hard Drive Detects
Imminent Failure
Expansion (backplane) board not seated properly.
SMART circuitry on an IDE drive has detected possible equipment
failure.
1721-SMART SCSI Hard Drive
Detects Imminent Failure
SMART circuitry on a SCSI drive has detected possible equipment
failure.
1801-Microcode Patch Error
A processor is installed for which the BIOS ROM has no patch.
Check for ROM update.
1998-Master Boot Record Backup
Has Been Lost
Backup copy of the hard drive master boot record is corrupted. Use
Setup to restore the backup from the hard drive.
If Master Boot Record Security is enabled, this message indicates
that the MBR has changed since the backup was made.
1999-Master Boot Record Has
Changed. Press Any Key To Enter
Setup to Restore the MBR.
2000-Master boot Record hard drive
has changed
The hard drive has been changed. Use Setup to create a backup of
the new hard drive.
A-2 Compaq Personal Computers
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Technical Reference Guide
A.4 SYSTEM ERROR MESSAGES (1xx-xx)
Table A-3.
System Error Messages
Message Probable Cause
Message Probable Cause
101
102
103
Option ROM error
110-01
110-02
110-03
111-01
112-01
112-02
112-03
112-04
112-05
112-06
112-07
112-08
112-09
112-10
112-11
112-12
113-01
114-01
116-xx
162-xx
Programmable timer load data test failed
Programmable timer dynamic test failed
Program timer 2 load data test failed
Refresh detect test failed
Speed test Slow mode out of range
Speed test Mixed mode out of range
Speed test Fast mode out of range
Speed test unable to enter Slow mode
Speed test unable to enter Mixed mode
Speed test unable to enter Fast mode
Speed test system error
Unable to enter Auto mode in speed test
Unable to enter High mode in speed test
Speed test High mode out of range
Speed test Auto mode out of range
Speed test variable speed mode inop.
Protected mode test failed
System board failure
System board failure
Master int. cntlr. test fialed
Slave int. cntlr. test failed
(see note)
104-01
104-02
104-03
105-01
105-02
105-03
105-04
105-05
105-06
105-07
105-08
105-09
105-10
105-11
105-12
105-13
105-14
Int. cntlr. SW RTC inoperative
Port 61 bit <6> not at zero
Port 61 bit <5> not at zero
Port 61 bit <3> not at zero
Port 61 bit <1> not at zero
Port 61 bit <0> not at zero
Port 61 bit <5> not at one
Port 61 bit <3> not at one
Port 61 bit <1> not at one
Port 61 bit <0> not at one
Port 61 I/O test failed
Port 61 bit <7> not at zero
Port 61 bit <2> not at zero
No int. generated by failsafe timer
NMI not triggered by failsafe timer
Speaker test failed
Way 0 read/write test failed
Sys. options failed (mismatch in drive
type)
106-01
107-01
108-02
108-03
109-01
109-02
109-03
Keyboard controller test failed
CMOS RAM test failed
CMOS interrupt test failed
163-xx
164-xx
199-00
Time and date not set
Memory size
Installed devices test failed
CMOS not properly initialized (int.test)
CMOS clock load data test failed
CMOS clock rollover test failed
CMOS not properly initialized (clk test)
NOTE: A 102 message code may be caused by one of a variety of processor-related problems
that may be solved by replacing the processor, although system board replacement may be needed.
Compaq Personal Computers
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Appendix A Error Messages and Codes
A.5 MEMORY ERROR MESSAGES (2xx-xx)
Table A-4.
Memory Error Messages
Message
200-04
200-05
200-06
200-07
200-08
201-01
202-01
202-02
202-03
203-01
203-02
203-03
204-01
204-02
204-03
204-04
204-05
205-01
205-02
205-03
206-xx
207-xx
210-01
210-02
210-03
211-01
211-02
211-03
213-xx
214-xx
215-xx
Probable Cause
Real memory size changed
Extended memory size changed
Invalid memory configuration
Extended memory size changed
CLIM memory size changed
Memory machine ID test failed
Memory system ROM checksum failed
Failed RAM/ROM map test
Failed RAM/ROM protect test
Memory read/write test failed
Error while saving block in read/write test
Error while restoring block in read/write test
Memory address test failed
Error while saving block in address test
Error while restoring block in address test
A20 address test failed
Page hit address test failed
Walking I/O test failed
Error while saving block in walking I/O test
Error while restoring block in walking I/O test
Increment pattern test failed
ECC failure
Memory increment pattern test
Error while saving memory during increment pattern test
Error while restoring memory during increment pattern test
Memory random pattern test
Error while saving memory during random memory pattern test
Error while restoring memory during random memory pattern test
Incompatible DIMM in slot x
Noise test failed
Random address test
A.6 KEYBOARD ERROR MESSAGES (30x-xx)
Table A-5.
Keyboard Error Messages
Message Probable Cause
Message
303-05
303-06
303-07
303-08
303-09
304-01
304-02
304-03
304-04
304-05
304-06
--
Probable Cause
300-xx
301-01
301-02
301-03
301-04
301-05
302-xx
302-01
303-01
303-02
303-03
303-04
Failed ID test
LED test, LED command test failed
LED test, LED command test failed
LED test, LED command test failed
LED test, command byte restore test failed
LED test, LEDs failed to light
Keyboard repeat key test failed
Unable to enter mode 3
Incorrect scan code from keyboard
No Make code observed
Cannot /disable repeat key feature
Unable to return to Normal mode
--
Kybd short test, 8042 self-test failed
Kybd short test, interface test failed
Kybd short test, echo test failed
Kybd short test, kybd reset failed
Kybd short test, kybd reset failed
Failed individual key test
Kybd long test failed
LED test, 8042 self-test failed
LED test, reset test failed
LED test, reset failed
LED test, LED command test failed
A-4 Compaq Personal Computers
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A.7 PRINTER ERROR MESSAGES (4xx-xx)
Table A-6.
Printer Error Messages
Message Probable Cause
Message
402-11
402-12
402-13
402-14
402-15
Probable Cause
401-01
402-01
402-02
402-03
402-04
Printer failed or not connected
Interrupt test, data/cntrl. reg. failed
Interrupt test and loopback test failed
Int. test, LpBk. test., and data register failed
Int. test, LpBk. test., and cntrl. register failed
Int. test, LpBk. test., and data/cntrl. reg.
failed
Printer data register failed
Printer control register failed
Data and control registers failed
Loopback test failed
402-05
402-06
402-07
402-08
402-09
402-10
Loopback test and data reg. failed
Loopback test and cntrl. reg. failed
Loopback tst, data/cntrl. reg. failed
Interrupt test failed
Interrupt test and data reg. failed
Interrupt test and control reg. failed
402-16
402-01
403-xx
404-xx
498-00
--
Unexpected interrupt received
Printer pattern test failed
Printer pattern test failed
Parallel port address conflict
Printer failed or not connected
--
A.8 VIDEO (GRAPHICS) ERROR MESSAGES (5xx-xx)
Table A-7.
Video (Graphics) Error Messages
Message Probable Cause
Message
508-01
509-01
510-01
511-01
512-01
514-01
516-01
Probable Cause
501-01
502-01
503-01
504-01
505-01
506-01
507-01
Video controller test failed
Video memory test failed
Video attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
320x200 mode, color set 0 test failed
320x200 mode, color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
Noise pattern test failed
See Table A-14 for additional graphics messages.
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Appendix A Error Messages and Codes
A.9 DISKETTE DRIVE ERROR MESSAGES (6xx-xx)
Table A-8.
Diskette Drive Error Messages
Message Probable Cause
Message
6xx-20
6xx-21
6xx-22
6xx-23
6xx-24
6xx-25
6xx-26
6xx-27
6xx-28
--
Probable Cause
6xx-01
6xx-02
6xx-03
6xx-04
6xx-05
6xx-06
6xx-07
6xx-08
6xx-09
6xx-10
Exceeded maximum soft error limit
Failed to get drive type
Failed to get change line status
Failed to clear change line status
Failed to set drive type in ID media
Failed to read diskette media
Failed to verify diskette media
Failed to read media in speed test
Failed speed limits
Exceeded maximum hard error limit
Previously exceeded max soft limit
Previously exceeded max hard limit
Failed to reset controller
Fatal error while reading
Fatal error while writing
Failed compare of R/W buffers
Failed to format a tract
Failed sector wrap test
Failed write-protect test
--
600-xx = Diskette drive ID test
601-xx = Diskette drive format
602-xx = Diskette read test
603-xx = Diskette drive R/W compare test
604-xx = Diskette drive random seek test
605-xx = Diskette drive ID media
606-xx = Diskette drive speed test
607-xx = Diskette drive wrap test
608-xx = Diskette drive write-protect test
609-xx = Diskette drive reset controller test
610-xx = Diskette drive change line test
611-xx = Pri. diskette drive port addr. conflict
612-xx = Sec. diskette drive port addr. conflict
694-00 = Pin 34 not cut on 360-KB drive
697-00 = Diskette type error
698-00 = Drive speed not within limits
699-00 = Drive/media ID error (run Setup)
A.10 SERIAL INTERFACE ERROR MESSAGES (11xx-xx)
Table A-9.
Serial Interface Error Messages
Message Probable Cause
Message
1101-13
1101-14
1109-01
1109-02
1109-03
1109-04
1109-05
1109-06
1150-xx
1151-xx
1152-xx
1155-xx
Probable Cause
1101-01
1101-02
1101-03
1101-04
1101-05
1101-06
1101-07
1101-08
1101-09
1101-10
1101-11
1101-12
UART DLAB bit failure
Line input or UART fault
Address line fault
UART cntrl. signal interrupt failure
DRVR/RCVR data failure
Clock register initialization failure
Clock register rollover failure
Clock reset failure
Input line or clock failure
Address line fault
Data line fault
Comm port setup error (run Setup)
COM1 address conflict
COM2 address conflict
COM port address conflict
Data line fault
UART cntrl. signal failure
UART THRE bit failure
UART Data RDY bit failure
UART TX/RX buffer failure
Interrupt circuit failure
COM1 set to invalid INT
COM2 set to invalid INT
DRVR/RCVR cntrl. signal failure
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A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx)
Table A-10.
Serial Interface Error Messages
Message Probable Cause
Message
1204-03
1204-04
1204-05
1204-06
1204-07
1204-08
1204-09
1204-10
1204-11
Probable Cause
1201-XX
1201-01
1201-02
1201-03
1201-04
1201-05
1201-06
1201-07
1201-08
Modem internal loopback test
Data block retry limit reached [4]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote
connection
UART DLAB bit failure
Line input or UART failure
Address line failure
Data line fault
UART control signal failure
UART THRE bit failure
UART DATA READY bit failure
UART TX/RX buffer failure
1201-09
1201-10
1201-11
1201-12
1201-13
Interrupt circuit failure
COM1 set to invalid inturrupt
COM2 set to invalid
DRVR/RCVR control signal failure
UART control signal interrupt
failure
1205-XX
1205-01
1205-02
1205-03
1205-04
Modem auto answer test
Time-out waiting for SYNC [5]
Time-out waiting for response [5]
Data block retry limit reached [5]
RX exceeded carrier lost limit
1201-14
1201-15
1201-16
1201-17
1202-XX
1202-01
1202-02
DRVR/RCVR data failure
Modem detection failure
Modem ROM, checksum failure
Tone detect failure
Modem internal test
Time-out waiting for SYNC [1]
Time-out waiting for response [1]
1205-05
1205-06
1205-07
1205-08
1205-09
1205-10
1205-11
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote
connection
1202-03
1202-11
1202-12
1202-13
1202-21
1202-22
1202-23
1203-XX
1203-01
1203-02
1203-03
1204-XX
1204-01
1204-02
Data block retry limit reached [1]
Time-out waiting for SYNC [2]
Time-out waiting for response [2]
Data block retry limit reached [2]
Time-out waiting for SYNC [3]
Time-out waiting for response [3]
Data block retry limit reached [3]
Modem external termination test
Modem external TIP/RING failure
Modem external data TIP/RING fail
Modem line termination failure
Modem auto originate test
1206-XX
1206-17
1210-XX
1210-01
1210-02
1210-03
1210-04
1210-05
1210-06
1210-07
1210-08
1210-09
1210-10
1210-11
Dial multi-frequency tone test
Tone detection failure
Modem direct connect test
Time-out waiting for SYNC [6]
Time-out waiting for response [6]
Data block retry limit reached [6]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote
connection
Time-out waiting for SYNC [4]
Time-out waiting for response [4]
NOTES:
[1] Local loopback mode
[2] Analog loopback originate mode
[3] Analog loopback answer mode
[4] Modem auto originate test
[5] Modem auto answer test
[6] Modem direct connect test
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A-7
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Appendix A Error Messages and Codes
A.12 SYSTEM STATUS ERROR MESSAGES (16xx-xx)
Table A-11.
System Status Error Messages
Message
1601-xx
1611-xx
Probable Cause
Temperature violation
Fan failure
A.13 HARD DRIVE ERROR MESSAGES (17xx-xx)
Table A-12.
Hard Drive Error Messages
Message Probable Cause
Message
17xx-51
17xx-52
17xx-53
17xx-54
17xx-55
17xx-56
17xx-57
17xx-58
17xx-59
17xx-60
17xx-62
17xx-63
17xx-65
17xx-66
17xx-67
17xx-68
17xx-69
17xx-70
17xx-71
17xx-72
17xx-73
--
Probable Cause
17xx-01
17xx-02
17xx-03
17xx-04
17xx-05
17xx-06
17xx-07
17xx-08
17xx-09
17xx-10
17xx-19
17xx-40
17xx-41
17xx-42
17xx-43
17xx-44
17xx-45
17xx-46
17xx-47
17xx-48
17xx-49
17xx-50
Exceeded max. soft error limit
Failed I/O read test
Exceeded max. Hard error limit
Previously exceeded max. soft error limit
Previously exceeded max.hard error limit
Failed to reset controller
Fatal error while reading
Fatal error while writing
Failed compare of R/W buffers
Failed to format a track
Failed diskette sector wrap during read
Cntlr. failed to deallocate bad sectors
Cylinder 0 error
Failed file I/O compare test
Failed drive/head register test
Failed digital input register test
Cylinder 1 error
Failed controller RAM diagnostics
Failed controller-to-drive diagnostics
Failed to write sector buffer
Failed to read sector buffer
Failed uncorrectable ECC error
Failed correctable ECC error
Failed soft error rate
Exceeded max. bad sectors per track
Failed to initialize drive parameter
Failed to write long
Failed to read long
Failed to read drive size
Failed translate mode
Drive not ready
Failed to recalibrate drive
Failed to format a bad track
Failed controller diagnostics
Failed to get drive parameters from ROM
Invalid drive parameters from ROM
Failed to park heads
Failed to move hard drive table to RAM
Failed to read media in file write test
Failed I/O write test
Failed non-translate mode
Bad track limit exceeded
Previously exceeded bad track limit
--
1700-xx = Hard drive ID test
1701-xx = Hard drive format test
1702-xx = Hard drive read test
1719-xx = Hard drive power mode test
1720-xx = SMART drive detects imminent failure
1721-xx = SCSI hard drive imminent failure
1724-xx = Net work preparation test
1736-xx = Drive monitoring test
1703-xx = Hard drive read/write compare test
1704-xx = Hard drive random seek test
1705-xx = Hard drive controller test
1706-xx = Hard drive ready test
1707-xx = Hard drive recalibrate test
1708-xx = Hard drive format bad track test
1709-xx = Hard drive reset controller test
1710-xx = Hard drive park head test
1714-xx = Hard drive file write test
1715-xx = Hard drive head select test
1716-xx = Hard drive conditional format test
1717-xx = Hard drive ECC test
1771-xx = Pri. IDE controller address conflict
1772-xx = Sec. IDE controller address conflict
1780-xx = Disk 0 failure
1781-xx = Disk 1 failure
1782-xx = Pri. IDE controller failure
1790-xx = Disk 0 failure
1791-xx = Disk 1 failure
1792-xx = Se. controller failure
1793-xx = Sec. Controller or disk failure
1799-xx = Invalid hard drive type
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A.14 HARD DRIVE ERROR MESSAGES (19xx-xx)
Table A-13.
Hard Drive Error Messages
Message Probable Cause
Message
19xx-21
19xx-22
19xx-23
19xx-24
19xx-25
19xx-26
19xx-27
19xx-28
19xx-30
19xx-31
19xx-32
19xx-33
19xx-34
19xx-35
19xx-36
19xx-37
19xx-38
19xx-39
19xx-40
19xx-91
Probable Cause
19xx-01
19xx-02
19xx-03
19xx-04
19xx-05
19xx-06
19xx-07
19xx-08
19xx-09
19xx-10
19xx-11
19xx-12
19xx-13
19xx-14
19xx-15
19xx-16
19xx-17
19xx-18
19xx-19
19xx-20
Drive not installed
Cartridge not installed
Tape motion error
Drive busy erro
Track seek error
Tape write-protect error
Tape already Servo Written
Unable to Servo Write
Unable to format
Got servo pulses second time but not first
Never got to EOT after servo check
Change line unset
Write-protect error
Unable to erase cartridge
Cannot identify drive
Drive not compatible with controller
Format gap error
Exception bit not set
Unexpected drive status
Device fault
Illegal command
Format mode error
Drive recalibration error
Tape not Servo Written
Tape not formatted
Drive time-out error
Sensor error flag
Block locate (block ID) error
Soft error limit exceeded
Hard error limit exceeded
Write (probably ID ) error
NEC fatal error
No data detected
Power-on reset occurred
Failed to set FLEX format mode
Failed to reset FLEX format mode
Data mismatch on directory track
Data mismatch on track 0
Failed self-test
Power lost during test
1900-xx = Tape ID test failed
1901-xx = Tape servo write failed
1902-xx = Tape format failed
1904-xx = Tape BOT/EOT test failed
1905-xx = Tape read test failed
1906-xx = Tape R/W compare test failed
1907-xx = Tape write-protect failed
1903-xx = Tape drive sensor test failed
A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24xx-xx)
Table A-14.
Video (Graphics) Error Messages
Message Probable Cause
Message Probable Cause
2402-01
2403-01
2404-01
2405-01
2406-01
2407-01
2408-01
2409-01
2410-01
2411-01
2412-01
2414-01
2416-01
2417-01
2417-02
2417-03
2417-04
2418-01
Video memory test failed
Video attribute test failed
2418-02
2419-01
2420-01
2421-01
2422-01
2423-01
2424-01
2425-01
2431-01
2432-01
2448-01
2451-01
2456-01
2458-xx
2468-xx
2477-xx
2478-xx
2480-xx
EGA shadow RAM test failed
EGA ROM checksum test failed
EGA attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
320x200 mode color set 0 test failed
320x200 mode color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
640x200 mode test failed
640x350 16-color set test failed
640x350 64-color set test failed
EGA Mono. text mode test failed
EGA Mono. graphics mode test failed
640x480 graphics mode test failed
320x200 256-color set test failed
Advanced VGA controller test failed
132-column AVGA test failed
AVGA 256-color test failed
AVGA BitBLT test failed
Noise pattern test failed
Lightpen text test failed, no response
Lightpen text test failed, invalid response
Lightpen graphics test failed, no resp.
Lightpen graphics tst failed, invalid resp.
EGA memory test failed
AVGA DAC test failed
AVGA data path test failed
AVGA BitBLT test failed
AVGA linedraw test failed
Compaq Personal Computers
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Appendix A Error Messages and Codes
A.16 AUDIO ERROR MESSAGES (3206-xx)
Table A-15.
Audio Error Message
Message
3206-xx
Probable Cause
Audio subsystem internal error
A.17 DVD/CD-ROM ERROR MESSAGES (33xx-xx)
Table A-16.
DVD/CD-ROM Drive Error Messages
Message
3301-xx
3305-XX
Probable Cause
Drive test failed
Seek test failed
See Table A-18 for additional messages.
A.18 NETWORK INTERFACE ERROR MESSAGES (60xx-xx)
Table A-17.
Network Interface Error Messages
Message Probable Cause
Message
6054-xx
6056-xx
6068-xx
6069-xx
6089-xx
Probable Cause
6000-xx
6014-xx
6016-xx
6028-xx
6029-xx
Pointing device interface error
Ethernet configuration test failed
Ethernet reset test failed
Ethernet int. loopback test failed
Ethernet ext. loopback test failed
Token ring configuration test failed
Token ring reset test failed
Token ring int. loopback test failed
Token ring ext. loopback test failed
Token ring open
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A.19 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx)
Table A-18.
SCSI Interface Error Messages
Message Probable Cause
Message
6nyy-33
6nyy-34
6nyy-35
6nyy-36
6nyy-39
6nyy-40
6nyy-41
6nyy-42
6nyy-43
6nyy-44
6nyy-50
6nyy-51
6nyy-52
6nyy-53
6nyy-54
6nyy-60
6nyy-61
6nyy-65
6nyy-90
6nyy-91
6nyy-92
6nyy-99
Probable Cause
6nyy-02
6nyy-03
6nyy-05
6nyy-06
6nyy-07
6nyy-08
6nyy-09
6nyy-10
6nyy-11
6nyy-12
6nyy-13
6nyy-14
6nyy-15
6nyy-16
6nyy-17
6nyy-18
6nyy-21
6nyy-24
6nyy-25
6nyy-30
6nyy-31
6nyy-32
Drive not installed
Media not installed
Seek failure
Drive timed out
Drive busy
Drive already reserved
Reserved
Reserved
Media soft error
Drive not ready
Media error
Drive hardware error
Illegal drive command
Media was changed
Tape write-protected
No data detected
Drive command aborted
Media hard error
Reserved
Illegal controller command
Invalid SCSI bus phase
Invalid SCSI bus phase
Invalid SCSI bus phase
Error status from drive
Drive timed out
SSI bus stayed busy
ACK/REQ lines bad
ACK did not deassert
Parity error
Data pins bad
Data line 7 bad
MSG, C/D, or I/O lines bad
BSY never went busy
BSY stayed busy
Controller CONFIG-1 register fault
Controller CONFIG-2 register fault
Media not unloaded
Fan failure
Controller timed out
Unrecoverable error
Controller/drive not connected
Over temperature condition
Side panel not installed
Autoloader reported tape not loaded properly
n = 5, Hard drive
= 6, CD-ROM drive
= 7, Tape drive.
yy = 00, ID
= 03, Power check
= 05, Read
= 06, SA/Media
= 08, Controller
= 23, Random read
= 28, Media load/unload
A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-xx)
Table A-19.
Pointing Device Interface Error Messages
Message Probable Cause
Message
8601-07
8601-08
8601-09
8601-10
8602-xx
--
Probable Cause
Right block not selected
Timeout occurred
Mouse loopback test failed
Pointing device is inoperative
I/F test failed
8601-01
8601-02
8601-03
8601-04
8601-05
8601-06
Mouse ID fails
Left mouse button is inoperative
Left mouse button is stuck closed
Right mouse button is inoperative
Right mouse button is stuck closed
Left block not selected
--
Compaq Personal Computers
A-11
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Appendix A Error Messages and Codes
This page is intentionally blank.
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Technical Reference Guide
Appendix B
ASCII CHARACTER SET
B.1 INTRODUCTION
This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and
hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode
editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad
to enter the decimal value of the symbol. The extended ASCII characters (decimals 128-255) can
only be called using the Alt + Numeric Keypad keys.
NOTE: Regarding keystrokes, refer to notes at the end of the table. Applications may interpret
multiple keystroke accesses differently or ignore them completely.
Table B-1.
ASCII Character Set
Dec
0
1
2
3
4
5
6
7
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Symbol
Blank
Dec
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Hex
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Symbol
Space
Dec
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
Symbol
Dec
96
97
98
99
Hex
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Symbol
@
A
B
C
D
E
F
G
H
I
‘
a
b
c
d
e
f
g
h
I
j
k
l
m
n
o
p
q
r
!
“
♥
♦
♣
♠
O
#
$
%
&
‘
(
)
*
+
`
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
P
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
J
K
L
-
.
/
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
4
0
1
2
3
4
5
6
7
8
9
:
3
¦
!!
¶
§
0
¦
s
t
u
v
w
x
y
z
{
↑
↓
→
←
;
<
=
>
?
\
]
^
_
|
}
↔
V
~
[1]
W
Continued
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Appendix B ASCII Character Set
Table B-1. ASCII Code Set (Continued)
Dec
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
NOTES:
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
Symbol
Dec
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
Hex
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Symbol
Dec
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
Hex Symbol
Dec
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Hex
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Symbol
Ç
á
└
┴
┬
├
─
┼
╞
╟
╚
╔
╩
╦
╠
═
╬
╧
╨
╤
╥
╙
╘
╒
╓
╫
╪
┘
┌
█
▄
▌
▐
▀
α
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
ü
é
â
ä
à
å
ç
ê
ë
è
ï
î
ì
Ä
Å
É
æ
Æ
ô
ö
ò
û
ù
ÿ
Ö
Ü
¢
£
¥
₧
ƒ
í
ó
ú
ñ
Ñ
ª
º
¿
⌐
¬
½
¼
¡
«
»
░
▒
▓
│
┤
╡
╢
╖
╕
╣
║
╗
╝
╜
╛
┐
ß
Γ
π
Σ
σ
µ
τ
Φ
Θ
Ω
δ
∞
φ
ε
∩
≡
±
≥
≤
⌠
⌡
÷
≈
°
·
·
√
ⁿ
²
■
Blank
[1] Symbol not displayed.
Keystroke Guide:
Dec #
0
Keystroke(s)
Ctrl 2
1-26
27
Ctrl A thru Z respectively
Ctrl [
28
Ctrl
29
Ctrl ]
30
31
32
Ctrl 6
Ctrl -
Space Bar
33-43
44-47
48-57
58
Shift and key w/corresponding symbol
Key w/corresponding symbol
Key w/corresponding symbol, numerical keypad w/Num Lock active
Shift and key w/corresponding symbol
Key w/corresponding symbol
59
60
61
Shift and key w/corresponding symbol
Key w/corresponding symbol
62-64
65-90
Shift and key w/corresponding symbol
Shift and key w/corresponding symbol or key w/corresponding symbol and
Caps Lock active
91-93
94, 95
96
Key w/corresponding symbol
Shift and key w/corresponding symbol
Key w/corresponding symbol
97-126 Key w/corresponding symbol or Shift and key w/corresponding symbol
and Caps Lock active
127
Ctrl -
128-255 Alt and decimal digit(s) of desired character
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Technical Reference Guide
Appendix C
KEYBOARD
C.1 INTRODUCTION
This appendix describes the Compaq keyboard that is included as standard with the system unit.
The keyboard complies with the industry-standard classification of an “enhanced keyboard” and
includes a separate cursor control key cluster, twelve “function” keys, and enhanced
programmability for additional functions.
This appendix covers the following keyboard types:
♦
♦
Standard enhanced keyboard.
Space-Saver Windows-version keyboard featuring additional keys for specific support of the
Windows operating system.
♦
Easy Access keyboard with additional buttons for internet accessibility functions.
Only one type of keyboard is supplied with each system. Other types may be available as an
option.
NOTE: This appendix discusses only the keyboard unit. The keyboard interface is a
function of the system unit and is discussed in Chapter 5, Input/Output Interfaces.
Topics covered in this appendix include the following:
♦
♦
Keystroke processing (C.2)
Connectors (C.3)
page C-2
page C-16
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Appendix C Keyboard
C.2 KEYSTROKE PROCESSING
A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power
(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a
Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for
pressed keys while at the same time monitoring communications with the keyboard interface of
the system unit. When a key is pressed, a Make code is generated. A Break code is generated
when the key is released. The Make and Break codes are collectively referred to as scan codes. All
keys generate Make and Break codes with the exception of the Pause key, which generates a
Make code only.
Scroll
Lock
Num
Lock
Caps
Lock
Matrix
Drivers
Data/
CLK
Keyboard
Interface
(System Unit)
Keyswitch
Matrix
Keyboard
Processor
Matrix
Receivers
Figure C–1. Keystroke Processing Elements, Block Diagram
When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal
after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT)
that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from
300 to 500 ms to complete.
If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until
an input command is received. After successful completion of the POR and BAT, a completion
code (AAh) is sent to the CPU and the scanning process begins.
The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system is
ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16
bytes held) a 17th byte of a successive scan code results in an overrun condition and the overrun
code replaces the scan code byte and any additional scan code data (and the respective key
strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective
keystroke can be registered.
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C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS
The PS/2-type keyboard sends two main types of data to the system; commands (or responses to
system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data
lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and
loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers (in the default mode) consist of 11 bits as shown in Figure C-2.
Tcy
Tcl
Tch
Clock
Th-b-t
(LSb)
(MSb)
Start
Bit
Parity
Bit
Stop
Bit
Dat
a
Dat
a
Dat
a
Dat
a
Dat
a
Dat
a
Dat
a
Dat
a
Data
Parameter
Minimum
Nominal
Maximum
Tcy (clock cycle)
Tcl (clock low)
Tch (clock high)
60 us
30 us
30 us
--
--
41 us
--
80 us
50 us
40 us
--
Th-b-t (high-before-transmit)
20 us
Figure C–2. PS/2 Keyboard-To-System Transmission, Timing Diagram
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks
the clock line every 60 us to verify the state of the signal. If a low is detected, the keyboard will
finish the current transmission if the rising edge of the clock pulse for the parity bit has not
occurred. The system uses the same timing relationships during reads (typically with slightly
reduced time periods).
The enhanced keyboard has three operating modes:
♦
♦
♦
Mode 1 - PC-XT compatible
Mode 2 - PC-AT compatible (default)
Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode
produces a different set of scan codes. When a key is pressed, the keyboard processor sends that
key’s make code to the 8042 logic of the system unit. The When the key is released, a release
code is transmitted as well (except for the Pause key, which produces only a make code). The
8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is
processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The
service routine takes the appropriate action based on which key was pressed.
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Appendix C Keyboard
C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS
The USB-type keyboard sends essentially the same information to the system that the PS/2
keyboard does except that the data receives additional NRZI encoding and formatting (prior to
leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this
guide).
Packets received at the system’s USB I/F and decoded as originating from the keyboard result in
an SMI being generated. An SMI handler routine is invoked that decodes the data and transfers
the information to the 8042 keyboard controller where normal (legacy) keyboard processing takes
place.
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C.2.3 KEYBOARD LAYOUTS
Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems.
Actual styling details including location of the Compaq logo as well as the numbers lock, caps
lock, and scroll lock LEDs may vary.
C.2.3.1 Standard Enhanced Keyboards
6
1
2
4
8
3
5
7
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
30
71
86
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
75
92
48 49
68 69
51
70
76 77 78 79 80 81 82 83
93 94
84 85
95
87
91
96
100
101
97 98 99
Figure C–3. U.S. English (101-Key) Keyboard Key Positions
6
1
2
3
4
5
7
8
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
75
92
48 49
68 69
51
71
70
103
86
76 77 78 79 80 81 82 83
87
84 85
95
104
91
100
101
93
94
96
97 98 99
Figure C–4. National (102-Key) Keyboard Key Positions
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Appendix C Keyboard
C.2.3.2
Windows Enhanced Keyboards
6
1
2
4
8
3
5
7
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
30
71
86
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
75
92
48 49
68 69
51
70
76 77 78 79 80 81 82 83
93 94
84 85
95
87
91
96
100
101
97 98 99
110
111 112
Figure C–5. U.S. English Windows (101W-Key) Keyboard Key Positions
6
1
2
3
4
5
7
8
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
48 49
68 69
51
71
70
103
86
75
92
76 77 78 79 80 81 82 83
87
84 85
95
104
110
91
100
101
93
94
96
97 98 99
111 112
Figure C–6. National Windows (102W-Key) Keyboard Key Positions
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C.2.3.3 Easy Access Keyboards
The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons
allowing quick internet navigation. Depending on system, either a 7-button or an 8-button layout
may be supplied.
The 7-button Easy Access Keyboard uses the layout shown in Figure C-7 and is available with
either a legacy PS/2-type connection or a Universal Serial Bus (USB) type connection.
Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7
NOTE:
Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Figure C–7. 7-Button Easy Access Keyboard Layout
The 8-button Easy Access Keyboard uses the layout shown in Figure C-8 and uses the PS/2-type
connection.
Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8
NOTE:
Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Figure C–8. 8-Button Easy Access Keyboard Layout
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Appendix C Keyboard
C.2.4 KEYS
All keys generate a make code (when pressed) and a break code (when released) with the
exception of the Pause key (pos. 16), which produces a make code only. All keys with the
exception of the Pause and Easy Access keys are also typematic, although the typematic action
of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the
BIOS. Typematic keys, when held down longer than 500 ms, send the make code repetitively at a
10-12 Hz rate until the key is released. If more than one key is held down, the last key pressed
will be typematic.
C.2.4.1 Special Single-Keystroke Functions
The following keys provide the intended function in most applications and environments.
Caps Lock - The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS
routine that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68,
and 76-82. When pressed and released again, these keys revert to the lower case state and the
LED is turned off. Use of the Shift key will reverse which state these keys are in based on the
Caps Lock key.
Num Lock - The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine
that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,
100, and 101. When pressed and released again, these keys revert to the lower case state and the
LED is turned off.
The following keys provide special functions that require specific support by the application.
Print Scrn - The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that initiates
a print routine. This function may be inhibited by the application.
Scroll Lock - The Scroll Lock key (pos. 15) when pressed and released, , invokes a BIOS
routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and
released again, the LED is turned off and the function is removed. This keystroke is always
serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the
application.
Pause - The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to
loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an
operation. The key that is pressed to resume operation is discarded. This function may be ignored
by the application.
The Esc, Fn (function), Insert, Home, Page Up/Down, Delete, and End keys operate at the
discretion of the application software.
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C.2.4.2
Multi-Keystroke Functions
Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in
positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled
off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case
for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions
55-57, 72, 74, 88-90, 100, and 101.
Ctrl - The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16, 17-
34, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key
positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16)
results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of
exiting an application and generally halts execution of the current program.
Alt - The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use
with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position 16
(Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-57,
72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The
application determines the actual function of the keystrokes. Both Alt key positions provide
identical functionality. The combination keystroke of Alt and SysRq results in software interrupt
15h, AX=8500h being executed. It is up to the application to use or not use this BIOS function.
The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34, 39-
54, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are
pressed make no difference as long as they are held down at the time the third key is pressed. The
Ctrl, Alt, and Delete keystroke combination (required twice if in the Windows environment)
initiates a system reset (warm boot) that is handled by the BIOS.
C.2.4.3 Windows Keystrokes
Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111
(marked with the Windows logo
) have the same functionality and are used by themselves or
in combination with other keys to perform specific “hot-key” type functions for the Windows
operating system. The defined functions of the Windows logo keys are listed as follows:
Keystroke
Function
Window Logo
Open Start menu
Window Logo + F1
Window Logo + TAB
Window Logo + E
Window Logo + F
Window Logo + CTRL + F
Window Logo + M
Shift + Window Logo + M
Window Logo + R
Window Logo + PAUSE
Window Logo + 0-9
Display pop-up menu for the selected object
Activate next task bar button
Explore my computer
Find document
Find computer
Minimize all
Undo minimize all
Display Run dialog box
Perform system function
Reserved for OEM use (see following text)
The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for
auxiliary functions (speaker volume, monitor brightness, password, etc.).
Key position 112 (marked with an application window icon
other keys for invoking Windows application functions.
) is used in combination with
Compaq Personal Computers
C-9
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Appendix C Keyboard
C.2.4.4 Easy Access Keystrokes
The Easy Access keyboards (Figures C-7 and C-8) include additional keys (also referred to as
buttons) used to streamline internet access and navigation.
These buttons, which can be re-programmed to provide other functions, have the default
functionality described below:
7-Button Easy Access Keyboard:
Button #
Description
Check email
Default Function
Email
Emoney
Compaq web site
AltaVista web site
Search
Travel expenses
Shopping
1
2
3
4
5
6
7
Go to community
Extra web site
Go to favorite web site
Internet search
Instant answer
E-commerce
8-Button Easy Access Keyboard:
Button #
Description
Default Function
1
2
3
4
5
6
7
8
Go to favorite web site
Go to AltaVista
Search
Customer web site of choice
AltaVista web site
AltaVista search engine
Launches user Email
Industry specification info
Launches Bloomberg market monitor
Links to user’s project center
News retrieval service
Check Email
Business Community
Market Monitor
Meeting Center
News/PC Lock
All buttons may be re-programmed by the user through the Easy Access utility.
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C.2.5 KEYBOARD COMMANDS
Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042-
type logic).
Table C-1.
Keyboard-to-System Commands
Command
Key Detection Error/Over/run
Value
00h [1]
FFh [2]
AAh
FCh
EEh
Description
Indicates to the system that a switch closure couldn’t be
identified.
Indicates to the system that the BAT has been successful.
Indicates failure of the BAT by the keyboard.
Indicates that the Echo command was received by the
keyboard.
BAT Completion
BAT Failure
Echo
Acknowledge (ACK)
FAh
Issued by the keyboard as a response to valid system
inputs (except the Echo and Resend commands).
Issued by the keyboard following an invalid input.
Upon receipt of the Read ID command from the system,
the keyboard issues the ACK command followed by the
two IDS bytes.
Resend
Keyboard ID
FEh
83ABh
Note:
[1] Modes 2 and 3.
[2] Mode 1 only.
C.2.6 SCAN CODES
The scan codes generated by the keyboard processor are determined by the mode the keyboard is
operating in.
♦
♦
Mode 1:
In Mode 1 operation, the keyboard generates scan codes compatible with 8088-
/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard
controller must be disabled. Since translation is not performed, the scan codes generated in
Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by sending command
F0h with the 01h option byte. Applications can obtain system codes and status information by
using BIOS function INT 16h with AH=00h, 01h, and 02h.
Mode 2:
Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic
translates the make codes from the keyboard processor into the codes required by the BIOS.
This mode was made necessary with the development of the Enhanced III keyboard, which
includes additional functions over earlier standard keyboards. Applications should use BIOS
function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode
2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code
immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).
♦
Mode 3:
Mode 3 generates a different scan code set from Modes 1 and 2. Code
translation must be disabled since translation for this mode cannot be done.
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Appendix C Keyboard
Table C-2.
Keyboard Scan Codes
Make / Break Codes (Hex)
Key
Pos.
Legend
Esc
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
Print Scrn
Mode 1
Mode 2
Mode 3
08/na
07/na
0F/na
17/na
1F/na
27/na
2F/na
37/na
3F/na
47/na
4F/na
56/na
5E/na
57/na
1
2
3
4
5
6
7
8
01/81
3B/BB
3C/BC
3D/BD
3E/BE
3F/BF
40/C0
41/C1
42/C2
43/C3
44/C4
57/D7
76/F0 76
05/F0 05
06/F0 06
04/F0 04
0C/F0 0C
03/F0 03
0B/F0 0B
83/F0 83
0A/F0 0A
01/FO 01
09/F0 09
78/F0 78
07/F0 07
9
10
11
12
13
14
58/D8
E0 2A E0 37/E0 B7 E0 AA
E0 2A E0 7C/E0 F0 7C E0 F0 12
E0 7C/E0 F0 7C [1] [2]
84/F0 84 [3]
E0 37/E0 B7 [1] [2]
54/84 [3]
15
16
Scroll Lock
Pause
46/C6
E1 1D 45 E1 9D C5/na
E0 46 E0 C6/na [3]
7E/F0 7E
5F/na
62/na
E1 14 77 E1 F0 14 F0 77/na
E0 7E E0 F0 7E/na [3]
0E/F0 E0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
`
1
2
3
4
5
6
7
8
9
0
-
=
\
29/A9
02/82
03/83
04/84
05/85
06/86
07/87
08/88
09/89
0A/8A
0B/8B
0C/8C
0D/8D
0E/F0 0E
46/F0 46
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5C/F0 5C
66/F0 66
67/na
16/F0 16
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5D/F0 5D
66/F0 66
2B/AB
0E/8E
Backspace
Insert
E0 52/E0 D2
E0 70/E0 F0 70
E0 F0 12 E0 70/E0 F0 70 E0 12 [5]
E0 12 E0 70/E0 F0 70 E0 F0 12 [6]
E0 6C/E0 F0 6C
E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]
E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]
E0 7D/E0 F0 7D
E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]
E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]
77/F0 77
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 52/E0 D2 E0 AA [6]
E0 47/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 47/E0 C7 E0 AA [6]
E0 49/E0 C7
E0 AA E0 49/E0 C9 E0 2A [4]
E0 2A E0 49/E0 C9 E0 AA [6]
45/C5
33
34
Home
6E/na
6F/na
Page Up
35
36
Num Lock
/
76/na
77/na
E0 35/E0 B5
E0 AA E0 35/E0 B5 E0 2A [1]
37/B7
E0 4A/E0 F0 4A
E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]
7C/F0 7C
37
38
39
40
*
-
7E/na
84/na
0D/na
15/na
4A/CA
0F/8F
10/90
7B/F0 7B
0D/F0 0D
15/F0 15
Tab
Q
Continued
([x] Notes listed at end of table.)
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Table C-2. Keyboard Scan Codes (Continued)
Make / Break Codes (Hex)
Key
Pos
Legend
Mode 1
Mode 2
Mode 3
1D/F0 1D
24/F0 24
2D/F0 2D
2C/F0 2C
35/F0 35
3C/F0 3C
43/F0 43
44/F0 44
4D/F0 4D
54/F0 54
5B/F0 5B
64/F0 64
41
42
43
44
45
46
47
48
49
50
51
52
W
E
R
T
Y
U
I
O
11/91
12/92
13/93
14/94
15/95
16/96
17/97
18/98
19/99
1D/F0 1D
24/F0 24
2D/F0 2D
2C/F0 2C
35/F0 35
3C/F0 3C
43/F0 43
44/F0 44
P
[
]
4D/F0 4D
54/F0 54
5B/F0 5B
1A/9A
1B/9B
Delete
E0 53/E0 D3
E0 71/E0 F0 71
E0 AA E0 53/E0 D3 E0 2A [4]
E0 2A E0 53/E0 D3 E0 AA [6]
E0 F0 12 E0 71/E0 F0 71 E0 12
[5]
E0 12 E0 71/E0 F0 71 E0 F0 12
[6]
E0 69/E0 F0 69
E0 F0 12 E0 69/E0 F0 69 E0 12
[5]
E0 12 E0 69/E0 F0 69 E0 F0 12
[6]
E0 7A/E0 F0 7A
E0 F0 12 E0 7A/E0 F0 7A E0 12
[5]
53
54
End
E0 4F/E0 CF
E0 AA E0 4F/E0 CF E0 2A [4]
E0 2A E0 4F/E0 CF E0 AA [6]
65/F0 65
6D/F0 6D
Page Down
E0 51/E0 D1
E0 AA E0 51/E0 D1 E0 2A [4]
E0 @a E0 51/E0 D1 E0 AA [6]
E0 12 E0 7A/E0 F0 7A E0 F0 12
[6]
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
7
8
9
+
47/C7 [6]
48/C8 [6]
49/C9 [6]
4E/CE [6]
3A/BA
1E/9E
1F/9F
20/A0
21/A1
22/A2
23/A3
24/A4
25/A5
26/A6
27/A7
28/A8
1C/9C
4B/CB [6]
4C/CC [6]
4D/CD [6]
2A/AA
2C/AC
2D/AD
2E/AE
6C/F0 6C [6]
75/F0 75 [6]
7D/F0 7D [6]
79/F0 79 [6]
58/F0 58
1C/F0 1C
1B/F0 1B
23/F0 23
2B/F0 2B
34/F0 34
33/F0 33
3B/F0 3B
42/F0 42
4B/F0 4B
4C/F0 4C
52/F0 52
5A/F0 5A
6B/F0 6B [6]
73/F0 73 [6]
74/F0 74 [6]
12/F0 12
1A/F0 1A
22/F0 22
21/F0 21
2A/F0 2A
32/F0 32
6C/na [6]
75/na [6]
7D/na [6]
7C/F0 7C
14/F0 14
1C/F0 1C
1B/F0 1B
23/F0 23
2B/F0 2B
34/F0 34
33/F0 33
3B/F0 3B
42/F0 42
4B/F0 4B
4C/F0 4C
52/F0 52
5A/F0 5A
6B/na [6]
73/na [6]
74/na [6]
12/F0 12
1A/F0 1A
22/F0 22
21/F0 21
2A/F0 2A
32/F0 32
Caps Lock
A
S
D
F
G
H
J
K
L
;
‘
Enter
4
5
6
Shift (left)
Z
X
C
V
B
2F/AF
30/B0
Continued
([x] Notes listed at end of table.)
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Appendix C Keyboard
Table C-2. Keyboard Scan Codes (Continued)
Make / Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
31/F0 31
3A/F0 3A
41/F0 41
49/F0 49
4A/F0 4A
59/F0 59
63/F0 63
81
82
83
84
85
86
87
N
M
,
.
31/B1
32/B2
33/B3
34/B4
35/B5
31/F0 31
3A/F0 3A
41/F0 41
49/F0 49
4A/F0 4A
/
Shift (right)
36/B6
59/F0 59
E0 48/E0 C8
E0 AA E0 48/E0 C8 E0 2A [4]
E0 2A E0 48/E0 C8 E0 AA [6]
4F/CF [6]
E0 75/E0 F0 75
E0 F0 12 E0 75/E0 F0 75 E0 12 [5]
E0 12 E0 75/E0 F0 75 E0 F0 12 [6]
69/F0 69 [6]
88
89
90
91
1
2
3
69/na [6]
72/na [6]
7A/na [6]
79/F0
50/D0 [6]
51/D1 [6]
E0 1C/E0 9C
72/F0 72 [6]
7A/F0 7A [6]
E0 5A/F0 E0 5A
Enter
79[6]
92
93
94
95
96
97
Ctrl (left)
Alt (left)
(Space)
Alt (right)
Ctrl (right)
1D/9D
38/B8
39/B9
14/F0 14
11/F0 11
29/F0 29
11/F0 11
19/F0 19
29/F0 29
39/na
58/na
61/F0 61
E0 38/E0 B8
E0 1D/E0 9D
E0 4B/E0 CB
E0 11/F0 E0 11
E0 14/F0 E0 14
E0 6B/Eo F0 6B
E0 AA E0 4B/E0 CB E0 2A [4]
E0 2A E0 4B/E0 CB E0 AA [6]
E0 50/E0 D0
E0 AA E0 50/E0 D0 E0 2A [4]
E0 2A E0 50/E0 D0 E0 AA [6]
E0 4D/E0 CD
E0 F0 12 E0 6B/E0 F0 6B E0 12[5]
E0 12 E0 6B/E0 F0 6B E0 F0 12[6]
E0 72/E0 F0 72
E0 F0 12 E0 72/E0 F0 72 E0 12[5]
E0 12 E0 72/E0 F0 72 E0 F0 12[6]
E0 74/E0 F0 74
98
99
60/F0 60
6A/F0 6A
E0 AA E0 4D/E0 CD E0 2A [4]
E0 2A E0 4D/E0 CD E0 AA [6]
52/D2 [6]
E0 F0 12 E0 74/E0 F0 74 E0 12[5]
E0 12 E0 74/E0 F0 74 E0 F0 12[6]
70/F0 70 [6]
100
101
102
103
104
110
0
.
na
na
70/na [6]
71/na [6]
7B/F0 7B
53/F0 53
13/F0 13
8B/F0 8B
53/D3 [6]
7E/FE
2B/AB
36/D6
71/F0 71 [6]
6D/F0 6D
5D/F0 5D
61/F0 61
na
(Win95) [7]
E0 5B/E0 DB
E0 1F/E0 F0 1F
E0 AA E0 5B/E0 DB E0 2A [4]
E0 2A E0 5B/E0 DB E0 AA [6]
E0 5C/E0 DC
E0 AA E0 5C/E0 DC E0 2A [4]
E0 2A E0 5C/E0 DC E0 AA [6]
E0 5D/E0 DD
E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]
E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]
E0 2F/E0 F0 27
E0 F0 12 E0 27/E0 F0 27 E0 12 [5]
E0 12 E0 27/E0 F0 27 E0 F0 12 [6]
E0 2F/E0 F0 2F
111
112
(Win95) [7]
8C/F0 8C
8D/F0 8D
(Win
Apps)
[7]
E0 AA E0 5D/E0 DD E0 2A [4]
E0 2A E0 5D E0 DD E0 AA [6]
E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]
E0 12 E0 2F/E0 F0 2F E0 F0 12 [6
Continued
([x] Notes listed at end of table.)
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Table C-2. Keyboard Scan Codes (Continued)
Make / Break Codes (Hex)
Key
Pos.
Legend
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
[9]
Mode 1
Mode 2
Mode 3
95/F0 95
9C/F0 9C
9D/F0 9D
9A/F0 9A
99/F0 99
96/F0 96
97/F0 97
9A/F0 9A
80/F0 80
99/F0 99
95/F0 95
0C/F0 0C
9D/F0 9D
96/F0 96
97/F0 97
Btn 1
Btn 2
Btn 3
Btn 4
Btn 5
Btn 6
Btn 7
Btn 1
Btn 2
Btn 3
Btn 4
Btn 5
Btn 6
Btn 7
Btn 8
NOTES:
E0 1E/E0 9E
E0 26/E0 A6
E0 25/E0 A5
E0 23/E0 A3
E0 21/E0 A1
E0 12/E0 92
E0 32/E0 B2
E0 23/E0 A3
E0 1F/E0 9F
E0 1A/E0 9A
E0 1E/E0 9E
E0 13/E0 93
E0 14/E0 94
E0 15/E0 95
E0 1B/E0 9B
E0 1C/E0 F0 1C
E0 4B/E0 F0 4B
E0 42/E0 F0 42
E0 33/E0 F0 33
E0 2B/E0 F0 2B
E0 24/E0 F0 24
E0 3A/E0 F0 3A
E0 33/E0 F0 33
E0 1B/E0 F0 1B
E0 54/E0 F0 54
E0 1C/E0 F0 1C
E0 2D/E0 F0 2D
E0 2C/E0 F0 2C
E0 35/E0 F0 35
E0 5B/E0 F0 5B
All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.
NA = Not applicable
[1] Shift (left) key active.
[2] Ctrl key active.
[3] Alt key active.
[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36
codes.
[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes
for F0 59/59 codes.
[6] Num Lock key active.
[7] Windows keyboards only.
[8] 7-Button Easy Access keyboard.
[9] 8-Button Easy Access keyboard.
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Appendix C Keyboard
C.3 CONNECTORS
Two types of keyboard interfaces are used in Compaq systems: PS/2-type and USB-type. System
units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support
simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will
ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to
chapter 5 “Input/Output” of this guide. The keyboard cable connectors and their pinouts are
described in the following figures:
Pin
1
2
Function
Data
Not connected
Ground
5
6
3
3
4
4
5
+5 VDC
Clock
1
2
6
Not connected
Figure C–9. PS/2 Keyboard Cable Connector (Male)
Pin
1
2
3
4
Function
+5 VDC
Data (+)
Data (-)
Ground
4
3
2
1
Figure C–10. USB Keyboard Cable Connector (Male)
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Technical Reference Guide
Appendix D
COMPAQ/NVIDIA VANTA LT
AGP GRAPHICS CARD
D.1 INTRODUCTION
This appendix describes the Compaq/NVIDIA Vanta LT AGP Graphics Card used in the standard
configuration on some models and also available as an option. This card (layout shown in the
following figure) installs in a system’s AGP slot. The Compaq/NVIDIA Vanta LT AGP Graphics
card (P/N 192174-002) provides high 2D performance as well as 3D capabilities.
SDRAM
SDRAM
SDRAM
SDRAM
NVIDIA
Vanta LT
Controller
Analog
Monitor
Connector
Figure D-1. Compaq/NVIDIA Vanta LT AGP Graphics Card (P/N 192174-002) Layout
This appendix covers the following subjects:
♦
♦
♦
♦
♦
Functional description (D.2)
Display modes (D.3)
Software support information (D.4)
Monitor power management (D.5)
Connectors (D.6)
page D-2
page D-3
page D-4
page D-4
page D-5
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Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card
D.2 FUNCTIONAL DESCRIPTION
The Compaq/NVIDIA Vanta LT Graphics Card provides high performance 2D and 3D display
imaging. The card’s AGP design provides an economical approach to 3D processing by off-
loading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
8 megabytes of on-board SDRAM stores the main display image.
128-bit
100-MHz
Data Bus
NVIDIA Vanta LT Graphics Controller
Memory
I/F
16 MB SDRAM
Frame Buffer
Video
AGP
Bus
Scalar
VSync
HSync
Card
Edge
Connector
CRT
Controller
AGP 4X
I/F
Analog
Monitor
Connector
3D Array
Engine
2D/VGA
Engine
250-MHz
RAM
RGB
DAC
BIOS
ROM
Figure D-2. Compaq/NVIDIA Vanta LT Graphics Card Block diagram
The Compaq/NVIDIA Vanta LT Pro Graphics Card includes the following features:
♦
♦
♦
8-MB SDRAM frame buffer using 128-bit 100-MHz access
AGP 2X transfers with sideband addressing
2D drawing engine providing:
•
•
•
•
•
•
3 ROP BtBLT
Triangle BLT
Stretch BLT
Line and poly draw
Color expansion
Coor conversion and scaling
♦
3D rendering engine with:
•
•
•
•
•
Triangle setup
Anistropic filtering
Flat and Gouraud shading
Trilinear filtering
TwinTexel engine
♦
♦
♦
♦
♦
250-MHz RAMDAC
32-bit Z/stencil buffer eliminates hidden screen portions for faster loading
32-bit color for increased image quality
30-fps full-screen DVD playback
Dual-monitor support with a PCI graphics card
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D.3 DISPLAY MODES
The 2D graphics display modes supported by the Compaq/NVIDIA Vanta LT Graphics Card are
listed in Table D-1.
Table D-1.
NVIDIA Vanta LT Display Modes
Max. Refresh Frequency (Hz)
Resolution
640 x 480
640 x 480
640 x 480
800 x 600
Bits per pixel
Color Depth
8
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
75
16
24
8
16
24
8
16
24
8
16
24
8
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
16
24
8
16
Compaq Personal Computers
D-3
Changed - October 2000
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Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card
D.4 SOFTWARE SUPPORT INFORMATION
The Compaq/NVIDIA Vanta LT Pro graphics card is fully compatible with software written for
legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the
current operating systems and programming environments such as:
♦
♦
♦
♦
♦
♦
♦
♦
Windows 98, 95
Windows NT 4.0, 3.51
Windows 3.11, 3.1
OS/2
Quick Draw
MS Direct Draw and Direct X
Direct 3D
OpenGL
D.5 POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power
condition. Table I-2 lists the monitor power conditions.
Table D-2.
Monitor Power Management Conditions
HSYNC
VSYNC
Power Mode
Description
Active
Active
On
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed
to timeout, another SMI is generated and serviced, resulting in
the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Active
Inactive
Inactive
Suspend
Inactive
Off
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
The graphics card’s maximum power consumption on the AGP bus is listed below:
Typical current draw @ 3.3 VDC: 1.5 A
Typical current draw @ 5.0 VDC: 50 mA
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D.6 CONNECTORS
There is one connector associated with this graphics card; the monitor connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the
system board. This interface is described in chapter 4 of this guide.
The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog
monitor. The Feature connector allows the attachment of an optional card such as a video tuner.
D.6.1 MONITOR CONNECTOR
9
Figure D-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table D-3.
DB-15 Monitor Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Red Analog
Blue Analog
Green Analog
Not Connected
Ground
Red Analog Ground
Green Analog Ground
Blue Analog Ground
Pin
9
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
10
11
12
13
14
15
--
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
Compaq Personal Computers
D-5
Changed - October 2000
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Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card
This page is intentionally blank.
D-6 Compaq Personal Computers
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Technical Reference Guide
Appendix E
COMPAQ/NVIDIA QUADRO2 EX/MXR
AGP GRAPHICS CARDS
E.1 INTRODUCTION
This appendix describes the Compaq/NVIDIA Quadro2 EX and MXR AGP Graphics Cards used
in the standard configuration on some models and also available as an option. These cards (layout
shown in the following figure) installs in a system’s AGP slot and provide high 2D performance
as well as entry-level 3D capabilities.
Feature Connector
DVI
Monitor
Connector
SDRAM
SDRAM
SDRAM
SDRAM
NVIDIA
NV11GL
Controller
Analog
Monitor
Connector
NOTES:
NVIDIA Quadro2 EX Graphics Card
NVIDIA Quadro2 MXR Graphics Card only
Figure E-1. Compaq/NVIDIA Quadro2 EX or MXR AGP Graphics Card Layout
This appendix covers the following subjects:
♦
♦
♦
♦
♦
Functional description (E.2)
Display modes (E.3)
Software support information (E.4)
Monitor power management (E.5)
Connectors (E.6)
page E-2
page E-3
page E-4
page E-4
page E-5
Compaq Personal Computers
E-1
Changed - October 2001
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
E.2 FUNCTIONAL DESCRIPTION
The NVIDIA Quadro2 MXR Graphics Card provides high performance 2D and 3D display
imaging. The card’s AGP design provides an economical approach to 3D processing by off-
loading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
32 megabytes of on-board SDRAM stores the main display image.
128-bit
166-MHz
Data Bus
NVIDIA NV11GL Graphics Controller
32 MB
SDRAM
Frame Buffer
Memory
I/F
Video
Scalar
AGP
Bus
VSync
HSync
Card
Edge
CRT
AGP 4X
I/F
Controller
Connector
Analog
Monitor
Connector
3D Array
Engine
2D/VGA
Engine
350-MHz
RAM
DAC
RGB
DVI
BIOS
ROM
DVI
Monitor
Connector
(Quadro MXR only)
Digital Video
Interface
Figure E-2. NVIDIA Quadro2 EX/MXR Graphics Card Block diagram
The NVIDIA Quadro2 EX/MXR Graphics Cards include the following features:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
32-MB SDRAM frame buffer using 128-bit 183-MHz access
AGP 4X transfers with sideband addressing
2D drawing engine
3D rendering engine
350-MHz RAMDAC
32-bit Z/stencil buffer eliminates hidden screen portions for faster loading
32-bit color for increased image quality
30-fps full-screen DVD playback
Dual-monitor support with a PCI graphics card
DVI monitor support (Quadro MXR only)
The NVIDIA Quadro2 MXR provides, in addition to the RGB monitor connector, a digital video
interface (DVI) connector that can directly drive a DVI monitor or another RGB monitor through
an adapter.
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Technical Reference Guide
E.3 DISPLAY MODES
The 2D graphics display modes supported by the NVIDIA Quadro2 MXR Graphics are listed in
Table E-1.
Table E-1.
NVIDIA Quadro2 EX/MXR Graphics Display Modes
Max. Refresh
Frequency (Hz) [1]
Memory Used
For Texture
Resolution
640 x 480
640 x 480
640 x 480
800 x 600
Bits per pixel
Color Depth
256
8
240
240
240
240
240
240
200
200
200
170
170
170
150
150
150
120
120
120
100
100
100
100
100
100
85
N/A
N/A
28.4 MB
N/A
N/A
26.4 MB
N/A
N/A
22.8 MB
N/A
N/A
20.3 MB
N/A
N/A
16.6 MB
N/A
22.6 MB
13.3 MB
N/A
20.8 MB
9.5 MB
N/A
20.0 MB
8.0 MB
N/A
19.9 MB
7.7 MB
N/A
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1000
1600 x 1000
1600 x 1000
1600 x 1200
1600 x 1200
1600 x 1200
1600 x 1280
1600 x 1280
1600 x 1280
1920 x 1080
1920 x 1080
1920 x 1080
1920 x 1200
1920 x 1200
1920 x 1200
NOTE:
16
32
8
16
32
65K
16.7M
256
65K
16.7M
85
85
85
85
18.5 MB
5.0 MB
85
[1] Values reflect hardware capability. May be restricted to lower frequency by operating system.
Compaq Personal Computers
E-3
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
E.4 SOFTWARE SUPPORT INFORMATION
The NVIDIA Quadro2 MXR graphics card is fully compatible with software written for legacy
video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the
current operating systems and programming environments such as:
♦
♦
♦
♦
♦
♦
♦
♦
♦
Windows 3.1, 95, 98, 2000, ME
Windows NT 4.0, 3.51
Whistler
Linux
OS/2
Quick Draw
MS Direct Draw and Direct X
Direct 3D
OpenGL
E.5 POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power
condition. Table E-2 lists the monitor power conditions.
Table E-2.
Monitor Power Management Conditions
HSYNC VSYNC
Power Mode
Description
Active
Active
On
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
timeout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed
to timeout, another SMI is generated and serviced, resulting in
the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Active
Inactive
Suspend
Inactive
Inactive
Off
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
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Technical Reference Guide
E.6 CONNECTORS
There are two connectors associated with the graphics subsystem; the display/monitor connector
and the Feature connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the
system board. This interface is described in chapter 4 of this guide.
The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog
monitor. The Feature connector allows the attachment of an optional card such as a video tuner.
E.6.1 MONITOR CONNECTOR
5
4
3
2
1
10
7
9
8
6
11
15
13
12
14
Figure E-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table E-3.
DB-15 Monitor Connector Pinout
Pin
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Pin
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
1
2
3
4
5
6
7
8
Red Analog
Blue Analog
9
10
11
12
13
14
15
--
Green Analog
Not Connected
Ground
Red Analog Ground
Green Analog Ground
Blue Analog Ground
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
Compaq Personal Computers
E-5
Changed - October 2001
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Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
This page is intentionally blank.
E-6 Compaq Personal Computers
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Technical Reference Guide
Appendix F
COMPAQ/Matrox Millennium G450
AGP GRAPHICS CARD
F.1
INTRODUCTION
This appendix describes the Compaq/Matrox Millennium G450 AGP Graphics Card used in the
standard configuration on some models and also available as an option. This card (layout shown
in the following figure) installs in a system’s AGP slot. The Compaq/Matrox Millennium G450
graphics card (SP# 203626-001) provides high 2D performance and entry-level 3D capabilities.
This card features a dual-RAMDAC design for driving two analog displays.
Feature Connector
SD
RAM
SD
RAM
RGB Monitor
Connectors
SDRAM
SDRAM
MGA
Dual-RAMDAC
Controller
Figure F-1. Compaq/Matrox Millennium G450 AGP Graphics Card Layout (PCA# 202901-001)
This appendix covers the following subjects:
♦
♦
♦
♦
♦
Functional description (F.2)
Display modes (F.3)
Software support information (F.4)
Monitor power management (F.5)
Connectors (F.6)
page F-2
page F-3
page F-4
page F-4
page F-5
Compaq Personal Computers
F-1
Original - November 2000
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.2
FUNCTIONAL DESCRIPTION
The Matrox Millennium G450-SD Graphics Card provides high performance 2D and 3D display
imaging. The card’s AGP design provides an economical approach to 3D processing by off-
loading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
16 or 32 megabytes of on-board SDRAM stores the main display image.
128-bit
166-MHz
Data Bus
MGA Graphics Controller
16 / 32 MB
SDRAM
Memory
I/F
Video
AGP
Bus
Scalar
Frame Buffer
Card
Edge
Connector
RGB
AGP 4X
I/F
350-MHz
RAMDAC
Analog
Monitor
Connector 1
H/VSync
H/VSync
3D Array
Engine
2D/VGA
Engine
CRT
Controller
BIOS
ROM
Analog
Monitor
Connector 2
RGB
200-MHz
RAMDAC
Figure F-2. Matrox Millennium G450 Graphics Card Block diagram
The Matrox Millennium G450 Graphics Card includes the following features:
♦
♦
♦
64-MB SDRAM frame buffer using 128-bit 166-MHz access
AGP 4X transfers with sideband addressing
2D drawing engine with:
•
•
•
128-bit BitBLTs, rectangle/polygon fills, line draws
Hardware cursor
8-/16-/32-bpp mode acceleration
♦
♦
Dual-head features:
•
•
•
•
•
Two analog monitor (RGB) ports
DVD max mode
DualHead zoom mode
DualHead clone mode
DualHead TV output mode
3D accelerator with:
•
•
•
•
Hardware transform and lighting
Anistropic filtering
Specular lighting diffuse, flat and Gouraud shading
16-/24-bit Z-buffering
♦
♦
360-MHz primary RAMDAC, 200-MHz secondary RAMDAC
VESA compliancy:
•
•
•
Dual DDC2B monitor support
VIP 2.0 interface
DPMS, EPA Energy Star, and ACPI-compliant power management
F-2 Compaq Personal Computers
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Technical Reference Guide
F.3
DISPLAY MODES
The graphics display modes supported by the Matrox Millennium G450 Graphics are listed in
Table F-1.
Table F-1.
Matrox Millennium G450 Graphics Display Modes
Max. Vertical
Refresh Freq. [1]
Supporting
RAMDAC
Resolution
640 x 480
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
800 x 600
Bits per pixel
Color Depth
256
8
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
75 Hz
75 Hz
75 Hz
75 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
75 Hz
75 Hz
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
8
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
1024 x 768
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1152 x 864
1280 x 960
1280 x 960
1280 x 960
1280 x 960
1280 x 1024
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
1600 x 1200
1600 x 1200
1800 x 1440
1800 x 1440
1800 x 1440
1856 x 1392
1856 x 1392
1856 x 1392
1920 x 1440
1920 x 1440
1920 x 1440
2048 x 768
2048 x 768
NOTE:
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
16
24
8
16
24
8
Primary
Primary
16
65K
[1] Value reflects hardware capabilities only. May be restricted by operating system.
Compaq Personal Computers
F-3
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.4
SOFTWARE SUPPORT INFORMATION
The Matrox Millennium G450 graphics card is fully compatible with software written for legacy
video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the
current operating systems and programming environments such as:
♦
♦
♦
♦
♦
♦
♦
Windows 2000
Windows NT 4.0
Autodesk AutoCAD R14 and 2000
Kintex 3D Studio Max
2D GDI
MS DirectDraw DX6-7, ActiveX, DirectX, Direct3D,
OpenGL 1.1 and 1.2
F.5
POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power
condition. Table F-2 lists the monitor power conditions.
Table F-2.
Monitor Power Management Conditions
HSYNC VSYNC
Power Mode
Description
Active
Active
On
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed
to timeout, another SMI is generated and serviced, resulting in
the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Active
Inactive
Suspend
Inactive
Inactive
Off
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
Power consumption of this card on the PCI bus is listed in the following table:
VddQ
(1.5 VDC)
.05 A
Vcc3
(3.3 VDC)
2.4 A
Vcc5
(5.0 VDC)
0.2 A
Voltage
Maximum Current Drain
Maximum Power Consumption
0.75 W
7.99 W
1.04 W
Total maximum power consumption for this card is 9.1 watts.
F-4 Compaq Personal Computers
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Technical Reference Guide
F.6
CONNECTORS
There are three connectors associated with the graphics subsystem; two display/monitor
connectors and the Feature connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the
system board. This interface is described in chapter 4 of this guide.
F.6.1 MONITOR CONNECTOR
The display/monitor connector is provided for connection of a compatible RGB/analog monitor.
5
4
3
2
1
10
7
9
8
6
11
15
13
12
14
Figure F-3. VGA Monitor Connector, (One of two female DB-15, as viewed from rear).
Table F-3.
DB-15 Monitor Connector Pinout
Pin
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Pin
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
1
2
3
4
5
6
7
8
Red Analog
Blue Analog
9
10
11
12
13
14
15
--
Green Analog
Not Connected
Ground
Red Analog Ground
Green Analog Ground
Blue Analog Ground
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
Compaq Personal Computers
F-5
Original - November 2000
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Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.6.2 VIDEO FEATURE CONNECTOR
The Video Feature connector allows a video peripheral such as a TV tuner card to provide video
input to the graphics card. This interface is compliant with VESA VIP specification 1.1.
26 / Y13
2 / Y1
1 / Z1
25 / Z13
Figure F-4. Feature Connector (26-Pin Header)
Table F-4.
Video In Connector Pinout
Pin
Signal
GND
GND
GND
HAD1
HAD0
HCTL
SCL
GND
GND
GND
GND
VIRQ
SDA
Description
Pin
Signal
P0
P1
P2
P3
P4
P5
P6
P7
DCLK
NC
NC
--
Description
Pixel Data 0
Pixel Data 1
Pixel Data 2
Pixel Data 3
Pixel Data 4
Pixel Data 5
Pixel Data 6
Pixel Data 7
Pixel Data Clock
Not Connected
Not Connected
Key
1 / Z1
3 / Z2
5 / Z3
7 / Z4
Ground
Ground
Ground
2 / Y1
4 / Y2
6 / Y3
8 / Y4
10 / Y5
12 / Y6
14 / Y7
16 / Y8
18 / Y9
20 / Y10
22 / Y11
24 / Y12
26 / Y13
9 / Z5
External Sync
External Clock
Serial Clock
Ground
Ground
Ground
11 / Z6
13 / Z7
15 / Z8
17 / Z9
19 / Z10
21 / Z11
23 / Z12
25 / Z13
Ground
Serial Data
GND
Ground
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Technical Reference Guide
Appendix G
COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER
G.1 INTRODUCTION
The Compaq/Adaptec 29160N SCSI Host Adapter (Compaq SP# 158364-001) is a PCI peripheral
that provides high performance interfacing with compatible SCSI peripherals, typically SCSI hard
drives. The card installs in a PCI slot and supports full bus mastering capability.
This appendix covers the following subjects:
♦
♦
♦
♦
Functional description (G.2)
SCSI adapter programming (G.3)
Specifications (G.4)
page G-2
page G-3
page G-3
page G-4
SCSI connectors (G.5)
Internal
Wide-Ultra SCSI Connector
Internal
Ultra SCSI Connector
External
Ultra
SCSI Connector
AIC7892
Figure G–1. Compaq/Adaptec 29160N SCSI Host Adapter Card Layout (PCA# 157342-001)
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter
G.2 FUNCTIONAL DESCRIPTION
A block diagram of the SCSI Adapter is shown in Figure L-2. The adapter’s architecture is based
on the AIC-7892 SCSI controller working off the 32-bit, 66-/33-MHz PCI bus. Providing full bus
mastering capability, the adapter supports data transfers up to 266 MB/s using the burst mode rate
on a 66-MHz 32-bit PCI bus. The AIC-7892 controller is an Ultra160 controller with an on-board
20-MIPS SCSI sequencer that can process SCSI commands without intervention from the host
microprocessor. The sequencer uses micro-code that is downloaded from the host during
initialization. Single-ended SCSI drivers are built into the controller and a 1-K data FIFO and an
internal 4-KB SRAM memory. An LED is provided to indicate SCSI bus activity.
The AIC7892 provides a memory interface that is used by the Serial EEPROM and the BIOS
ROM. The serial EEPROM stores non-volatile configuration data and the BIOS ROM (which is a
flash ROM) contains additional configuration data and SCSI functions. The programmable array
logic (PAL) controls the Serial EEPROM-to-AIC7892 interface.
SCSI
Activity
PAL
Chip
Active Ultra160
SE Term.
Serial
EEPROM
40-MHz
Clock
PCI Bus
AIC7892
SCSI
PCI
Slot
Int. SCSI Connector (SE)
Ext. SCSI Connector (SE)
Int. SCSI Connector (SE/LVD)
Controller
AIC3860
Transceiver
Chip
BIOS
ROM
Active Ultra160
SE/LVD Term.
Figure G–2. Compaq/Adaptec Ultra SCSI Adapter Card Block Diagram
The AIC7892 controller supports dual-mode low-voltage differential (LVD) SCSI I/O up to the
Ultra160 data rate of 160 Mbytes. Both single-ended (SE) and LVD devices can co-exist on the
SCSI bus, although operation will default to the SE mode. In SE mode, transfer rates are limited
to the speed of the slower device. High-voltage differential (HVD) devices are supported for rates
up to Ultra speeds.
The AIC7892 also supports cyclic redundancy check (CRC) codes, an improvement over parity
checking used earlier.
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G.3 SCSI ADAPTER PROGRAMMING
G.3.1 SCSI ADAPTER CONFIGURATION
The Adaptec SCSI Host Adapter Card is a PCI device and configured using PCI protocol and PCI
Configuration Space registers (PCI addresses 00h-FFh) as discussed in Chapter 4 of this guide.
Configuration is accomplished by BIOS during POST and re-configurable with software. The
vender ID and device ID for the adapter are as follows:
Vender ID (PCI config. addr. 00h): 9005h
Device ID (PCI config, addr. 02h): 0080h
G.3.2 SCSI ADAPTER CONTROL
Control of the SCSI host adapter is affected through I/O mapped registers mapped as listed in
Table G-1.
Table G-1.
Ultra SCSI Host Adapter Card
Control Register Mapping
I/O Addr.
Function
n00h-n1Fh
n20h-n5Fh
n60h-n7Fh
n80h-n9Fh
n00h-nFFh
SCSI Register Array
Scratch RAM
Phase Engine (Sequencer)
Host Registers
SCB Array
n = prefix address supplied by the BASEADR0 PCI Config. Reg.
G.4 SPECIFICATIONS
The operating specifications are listed in Table G-2.
Table G-2.
Ultra SCSI Host Adapter Card Specifications
Operating Voltage
+5 VDC
Maximum Current Draw
Operating Temperature
2 A
32°F (0°C) to 131°F (55°C)
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter
G.5 SCSI CONNECTORS
This SCSI card provides two internal header-type connectors (one 50-pin, one 68-pin) and one
external D-type connector (50-pin).
G.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR
The card provides one external 50-pin D-type Ultra SCSI connector. External cabling should meet
T-10 SPI-2 standards (50-conductor, round shielded).
Pin 1
Figure G–3. External Ultra SCSI Connector (50-pin)
Table G-3.
External Ultra SCSI Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Function
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Reserved
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal
DB0-
DB1-
DB2-
DB3-
DB4-
DB5-
DB6-
DB7-
DBP
Function
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bus Pulse
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
GND
GND
Ground
Ground
TERMPWR Termination Power
GND
GND
ATN-
GND
BSY-
ACK-
SBRST-
MSG-
SEL-
C-/D
Ground
Ground
Attention
Ground
Busy
Acknowledge
Burst
Message Activity
Select
Control/Data Transfer Indicator
Request
REQ-
I-/O
Input/Output Indicator
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G.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR
The card provides one internal 50-pin header-type Ultra SCSI connector. Internal cabling to this
connector should consists of an unshielded connector with a 50-conductor flat cable as specified
in ANSI standard X3T9.2/375R.
Pin 1
Pin 49
Pin 2
Pin 50
Figure G–4. Internal 50-Pin Ultra SCSI Connector
Table G-4.
Internal 50-Pin Ultra SCSI Connector Pinout
Pin
1
3
5
7
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Function
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Open
Pin
2
4
6
8
Signal
DB0-
DB1-
DB2-
DB3-
DB4-
DB5-
DB6-
DB7-
DBP
GND
CS
Function
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bus Pulse
Ground
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Cable Sense
Open
Open
Open
Open
TERMPWR Termination Power
Open
GND
ATN-
GND
BSY-
ACK-
SBRST-
MSG-
SEL-
C-/D
Open
Ground
Attention
Ground
Busy
Acknowledge
Reset
Message Activity
Select
Control/Data Transfer Indicator
Request
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
REQ-
I-/O
Input/Output Indicator
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Appendix G Compaq/Adaptec 29160N SCSI Host Adapter
G.5.3 INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR
The card provides one internal 68-pin Ultra160 SCSI connector. This connection is designed for a
68-conductor unshielded Twist ‘N Flat cable as specified in the T-10 SPI-2 standard.
Pin 1
Pin 34
Pin 35
Pin 68
Figure G–5. Ultra 160 SCSI Connector (68-pin header type)
Table G-5.
Ultra160 SCSI Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Function
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
DB12
DB13
DB14
DB15
DBP-
DB0-
DB1-
DB2-
DB3-
DB4-
DB5-
DB6-
DB7-
DBP-
GND
GND
Function
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Data Bus Parity
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bus Parity
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Ground
TERMPWR Termination Power
TERMPWR Termination Power
TERMPWR Termination Power
TERMPWR Termination Power
Int_Out-
SBRST-
ATN-
GND
BSY-
ACK-
RESET-
MSG-
SEL-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Interrupt Out
Burst
Attention
Ground
Busy
Acknowledge
Reset
Message Activity
Select
Control/Data Transfer Indicator
Request
Input/Output Indicator
Data Bit 8
C-/D
REQ-
I-/O
DB8-
DB9-
Data Bit 9
Data Bit 10
Data Bit 11
DB10-
DB11-
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Appendix H
COMPAQ/Matrox G200 MMS Quad-Head
PCI GRAPHICS CARD
H.1 INTRODUCTION
This appendix describes the Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card used in
the standard configuration on some models and also available as an option. This card (layout
shown in the following figure) installs in a system’s PCI slot. The Compaq/Matrox G200 MMS
graphics card provides high performance multi-monitor imaging well suited for business
environments where displaying large amounts of 2D data is needed. This card includes four
separate G200 graphics controllers for supporting up to two pairs of analog or digital displays.
This card is available in both analog and digital kit forms. The analog kit (SPN 159513-B21)
includes adapter cables for connecting analog (RGB) monitors while the digital kit (SPN 179597-
B21) includes adapter cables for connecting DVI-compliant digital displays. Either kit can be
adapted to support analog or digital displays by ordering the appropriate adapter cable.
Adapter
Connector
For Monitors # 3 & 4
Adapter Cable
Adapter
Connector
For Monitors # 1 & 2
Figure H-1. Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card Layout
This appendix covers the following subjects:
♦
♦
♦
♦
♦
Functional description (F.2)
Display modes (F.3)
Software support information (F.4)
Monitor power management (F.5)
Connectors (F.6)
page F-2
page F-3
page F-4
page F-4
page F-5
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card
H.2 FUNCTIONAL DESCRIPTION
The Matrox G200 MMS Quad-Head PCI Graphics Card provides high performance, multi-
monitor 2D imaging. With four G200 graphics controllers each supported with an 8-MB SGRAM
frame buffer, the card can provide, with appropriate OS, separate images on up to four displays.
Each controller can drive either an analog RGB monitor or a digital video interface-compliant
monitor (but not both).
8 MB SGRAM
Frame Buffer
BIOS
ROM
RGB
MGA G200
Graphics
Controller #4
DVI
Adapter
Connector
For Monitors
#3 & 4
RGB
DVI
MGA G200
Graphics
Controller #3
PCI
Bus
Intel
21152
PCI Bridge
Controller
8 MB SGRAM
Frame Buffer
Card
Edge
Connector
8 MB SGRAM
Frame Buffer
RGB
DVI
MGA G200
Graphics
Controller #2
Adapter
Connector
For Monitors
#1 & 2
RGB
DVI
MGA G200
Graphics
Controller #1
8 MB SGRAM
Frame Buffer
Figure H-2. Matrox G200 MMS Quad-Head PCI Graphics Card Block diagram
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The card includes four MGA G200 graphics controllers. Each controller includes a VGA
controller core, 2D and 3D engines, and a 250-MHz RAMDAC. Each controller can drive either
an analog RGB monitor or a DVI-compliant digital monitor.
MGA G200 Graphics Controller
128-bit
Data Bus
Video
Scalar
Memory
I/F
PCI
Bus
Card
Edge
Connector
RGB
PCI
I/F
250-MHz
RAMDAC
Analog
Monitor
3D Array
Engine
2D/VGA
Engine
H/VSync
CRT
Controller
DVI Data
Digital
Monitor
DVI
Controller
Figure H-3. MGA G200 Graphics Controller Architecture
The MGA G200 graphics controller includes the following features:
♦
♦
♦
64-bit SGRAM interface
PCI bus 2.1 compliant with bus-mastering support
2D drawing engine with:
•
•
•
128-bit BitBLTs, rectangle/polygon fills, line draws
Hardware cursor
8-/16-/32-bpp mode acceleration
♦
♦
Analog (RGB) or DVI monitor support
3D accelerator with:
•
•
•
•
Vertex fog
Anistropic filtering
Specular lighting diffuse, flat and Gouraud shading
Full-scene anti-aliasing
♦
♦
250-MHz RAMDAC
VESA compliancy:
•
•
•
Dual DDC2B monitor support
VIP 2.0 interface
DPMS, EPA Energy Star, and ACPI-compliant power management
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card
H.3 DISPLAY MODES
The graphics display modes supported by each monitor port on the Matrox G200 MMS Graphics
card are listed in Table H-1.
Table H-1.
Matrox G200 MMS Graphics Controller Display Modes
Max. Vertical
Refresh Freq. [1]
Monitor
Support
Resolution
640 x 480
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
800 x 600
Bits per pixel
Color Depth
256
8
200 Hz
200 Hz
200 Hz
200 Hz
200 Hz
200 Hz
200 Hz
200 Hz
140 Hz
140 Hz
140 Hz
140 Hz
120 Hz
120 Hz
120 Hz
120 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
90 Hz
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog or Digital
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
Analog only
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
32
8
16
24
8
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
1024 x 768
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1152 x 864
1280 x 720
1280 x 720
1280 x 720
1280 x 720
1280 x 1024
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1024
1600 x 1024
1600 x 1024
1600 x 1024
1600 x 1200
1600 x 1200
1600 x 1200
1800 x 1440
1800 x 1440
1920 x 1080
1920 x 1080
1920 x 1080
1920 x 1200
1920 x 1200
NOTE:
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
256
65K
256
65K
16.7M
256
90 Hz
90 Hz
70 Hz
70 Hz
80 Hz
80 Hz
80 Hz
76 Hz
16
8
16
24
8
16
65K
76 Hz
Analog only
[1] Value reflects hardware capabilities only. May be restricted to lower frequency by
operating system.
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H.4 DISPLAY CONFIGURATION
H.4.1 SINGLE-CARD CONFIGURATION
The Matrox G200 MMS Quad-Head PCI Graphics Card supports multiple monitors through the
use of adapter cables. The graphics card as ordered from Compaq comes with either an analog
adapter cable or a digital adapter cable, depending on order number. The card supports the
following display configurations:
♦
♦
♦
Up to four analog (RGB) monitors
Up to four digital (DVI-compliant) monitors
One or two analog monitors and one or two digital monitors (NOTE: An analog/digital "mix"
requires ordering the appropriate other cable type (analog or digital)).
H.4.2 MULTI-CARD CONFIGURATION WITH WINDOWS NT 4.0
Multiple Matrox G200 MMS Quad-Head PCI Graphics Cards can be installed in a single system
to increase the amount of video real estate. Up to 16 monitors can be driven by a system using
four cards and running Windows NT 4.0.
H.5 SOFTWARE SUPPORT INFORMATION
The Matrox G200 MMS graphics card is fully compatible with software written for legacy video
modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the
current operating systems such as:
♦
♦
♦
Windows 2000
Windows 98
Windows NT 4.0
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card
H.6 POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power
condition. Table H-2 lists the monitor power conditions.
Table H-2.
Monitor Power Management Conditions
HSYNC VSYNC
Power Mode
Description
Active
Active
On
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed
to timeout, another SMI is generated and serviced, resulting in
the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Active
Inactive
Suspend
Inactive
Inactive
Off
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
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H.7 CONNECTORS
There are four types of connectors associated with the graphics card; an analog monitor
connector, digital monitor connector, adapter cable connectors and the card edge connector.
NOTE: The graphic card’s edge connector mates with a PCI slot connector on the
system board. This interface is described in chapter 4 of this guide.
H.7.1 ADAPTER CABLE CONNECTOR
A display or monitor cannot be attached directly to the graphics card. The graphics card includes
two connectors for attaching adapter cables that are used to attach the monitor(s).
P15
P1
P16
P30
P31
P60
P45
P1
Figure H-4. Adapter Cable Connector, (One of two as viewed from rear).
Table H-3.
Adapter Cable Connector Pinout
Pin
1
2
3
4
5
6
7
8
Description
Ground
Analog Red
Analog Blue
Ground
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Description
Not used
TMDS Clock Data -
TMDS Cllock Data +
TMDS Data 1 -
TMDS Data 1+
Ground
Analog Green
Not used
Ground
HSYNC
VSYNC
Ground
Not used
Ground
VSYNC
HSYNC
Ground
Not used
Not used
Not used
Not used
Not used
Not used
TMDS Data 2 -
TMDS Data 2 +
TMDS Data 0 -
TMDS Data 0 +
TMDS Data 1 +
TMDS Data 1 -
TMDS Clock Data +
TMDS Clock Data -
Not used
Hot plug detect
Not used
Not used
Not used
5 VDC
SCL (DDC)
SDA (DDC)
Ground
SDA (DDC)
SCL (DDC)
5 VDC
9
10
11
12
13
14
15
16
17
18
19
Ground
Analog Blue
Analog Red
Ground
TMDS Data 0 +
TMDS Data 0 -
TMDS Data 2 +
TMDS Data 2 -
Not used
Analog Green
Ground
Monitor #1 or #3
Monitor #2 or #4
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card
H.7.2 ANALOG MONITOR CONNECTOR
The analog adapter cable supplied with the analog version of the graphics card kit provides two
DB-15 VGA monitor connectors.
5
4
3
2
1
10
7
9
8
6
11
15
13
12
14
Figure H-5. Analog (VGA) Monitor Connector (One of two female DB-15 connectors).
Table H-4.
DB-15 Monitor Connector Pinout
Pin
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Pin
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
1
2
3
4
5
6
7
8
Red Analog
Blue Analog
9
10
11
12
13
14
15
--
Green Analog
Not Connected
Ground
Red Analog Ground
Green Analog Ground
Blue Analog Ground
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
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H.7.3 DIGITAL MONITOR CONNECTOR
The digital adapter cable supplied with the digital version of the graphics card kit provides two
DVI-D monitor connectors.
P8
P1
P9
P16
P17
P24
Figure H-6. DVI-D Monitor Connector (24-Pin Connector)
Table H-4.
DVI-D Connector Pinout
Pin
Description
Pin
Description
1
2
3
4
5
6
7
8
TMDS Data 2 -
TMDS Data 2 +
TMDS Data 2 & 4 Shield
TMDS Data 4 -
TMDS Data 4 +
DDV Clock
DDC Data
Not used
TMDS Data 1 -
TMDS data 1 +
TMDS Data 1 & 3 Shield
TMDS Data 3 -
13
14
15
16
17
18
19
20
21
22
23
24
TMDS Data 3 +
5 VDC
Ground
Hot plug detect
TMDS Data 0 -
TMDS Data 0 +
TMDS Data 0 & 5 Shield
TMDS Data 5 -
TMDS Data 5 +
TMDS Clock Shield
TMDS Clock +
TMDS Clock -
9
10
11
12
Compaq Personal Computers
H-9
Original - March 2002
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Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card
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H-10 Compaq Personal Computers
Original - March 2002
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INDEX
3D effects, D-2, E-2, F-2, H-2
abbreviations, 1-4
AC97 link bus, 5-28
Accelerated Graphics Port (AGP), 4-10
ACPI, 5-34
diskette drive interface, 5-7
display (VGA monitor), D-5, E-5, F-5, H-8
IDE interface, 5-3
keyboard/pointing device interface, 5-21
Network RJ-45, 5-36
acronyms, 1-4
parallel interface, 5-15
AGP, 4-10
PCI bus, 4-9
Alert-On-LAN, 5-33
AOL, 5-33
AOL requirements, 5-33, 5-38
APIC, 4-16
serial interface (RS-232), 5-8
Ultra SCSI (50-pin D-type), G-4
Ultra SCSI (50-pin header type), G-5
Universal Serial Bus interface, 5-25
VGA pass-through (feature), F-6, H-9
Wide Ultra SCSI (68-pin header type), G-6
cooling, 4-28
APM, 5-34
APM BIOS support, 7-19
arbitration, PCI bus master, 4-6
ASCII character set, B-1
audio, 5-26
core voltage, 6-8
DIMM detection, 7-5
audio controller (AC97), 5-28
audio subsystem, 2-18
backplane, 2-7
battery replacement, 4-23
BIOS, ROM, 7-1
DIMM support, 7-15
Direct Rambus, 3-5
diskette drive interface, 5-4
display modes, D-3
display modes, Matrox Millennium G450, F-3,
H-4, H-5
blinking LED, 6-4
boot block ROM, 7-2
cable lock, 4-26
display modes, NVIDIA Quadro2 EX/MXR, E-3
DMA, 4-19
CAS latency, 3-5
DMI, 7-16
Celeron processor, 2-14
chassis fan, 4-29
chipsets, 2-15
drive fault prediction, 7-15
dual-head support, F-2, H-3
East Access keys, C-10
Client Management, 7-12
CMOS, 4-23
CMOS, archive, 4-24
CMOS, clearing, 4-23
CMOS, restoring, 4-24
codec, audio, 5-29
Configuration Cycle, 4-4
configuration cycle (PCI), 4-4
configuration memory, 4-23
configuration space (PCI), 4-5
Connector
Easy Access keyboards, C-7
effects, 3D, D-2, E-2, F-2, H-2
EIDE interface, 5-1
Enhanced Parallel Port (EPP), 5-12
events, wake up, 6-4
expansion card cage, 2-7
Extended Capabilities Port (ECP), 5-12
fan
boxed processor, 4-29
chassis, 4-29
power supply, 4-29
AGP bus, 4-14
Audio, CD, 5-27
feature connector, F-6, H-9
features, standard, 2-2
audio, headphones out, 5-26
audio, line in, 5-26
audio, line out, 5-26
Audio, Mic In, 5-26
Audio, Speaker, 5-27
flash ROM, 7-2
graphics card, Matrox G200 MMS Quad-Head
PCI, H-1
graphics card, Matrox Millennium G450, F-1
graphics card, NVIDIA Quadro2 EX/MXR, E-1
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graphics card, NVIDIA Vanta LT, D-1
graphics subsystem, 2-17
graphics, 3D, D-2, E-2, F-2, H-2
Hard drive activity indicator, 4-32
Hub link bus, 4-7
I/O controller (LPC47B34x), 4-31
I/O map, 4-30
IDE interface, 5-1
password, power-on, 4-25
PCI bus, 2-16, 4-2
PCI Configuration Space, 4-5
PCI interrupts, 4-7
Pentium 4 processor, 3-2
Pentium II, 2-15
Pentium II processor, 2-14
PHY, 5-32
IDSEL, 4-4
index addressing, 1-3
interface
pinouts, header (connector), 6-11
Plug ’n Play, 2-2, 2-16, 7-15
Plug 'n Play BIOS function, 7-15
power button, 6-3
audio, 2-18, 5-26
diskette drive, 5-4
IDE, 5-1
keyboard/pointing device, 5-16
parallel, 2-16, 5-11
serial, 2-16, 5-8
Power Button Override, 4-24
power consumption, graphics card, D-4
power distribution, 6-6
Power indicator, 4-32
power LED, 6-4
USB, 2-16, 5-22
power management
interrupts
ACPI, 4-27
maskable (IRQn), 4-15
nonmaskable (NMI, SMI), 4-17
interrupts, PCI, 4-7
key (keyboard) functions, C-8
keyboard, C-1
network interface controller (NIC), 5-34
PCI, 4-7
power management BIOS function, 7-17
power states, system, 6-5
power supply, 6-1
keyboard (micro)processor, C-2
keyboard layouts, C-5
keyboard, USB, C-4
keyboards, Easy Access, C-7
keys, Easy Access, C-10
keys, Windows, C-9
LED, 5-32
power supply assembly, 6-2
power-on password, 4-25
processor upgrading, 3-4
processor, Celeron, 2-14
processor, Pentium 4, 3-2
processor, Pentium II, 2-14
RAM, 2-16
LED indications, 4-27, 6-4
LED, HD, 4-32
LED, Power, 4-32
RDRAM, 3-5
reference sources, 1-2
remote flashing, 7-2
low voltages, 6-8
LPC bus, 4-7
LPC47B34x I/O controller, 4-31
Magic Packet, 5-34
remote wake up, 5-34
restoring CMOS, 4-24
RIMM, 3-5
ROM BIOS, 7-1
mass storage, 2-16
ROM flashing, 7-2
memory detection, 7-5
memory map, 3-7
ROM, option, 4-7
RS-232, 5-8
memory, system (RAM), 2-16
microphone, 5-26
RTC, 4-23
scan codes (keyboard), C-11
SCSI Host card, Adaptec 29160N, G-1
SDRAM, D-2, H-3
monitor power control, D-4, E-4, F-4, H-6
mouse interface, 5-18
network interface controller, 5-32
network support, 5-32
NIC, 5-32
NIC upgrading, 5-37
notational conventions, 1-2, 1-3
NUM lock, 3-5
option ROM, 4-7
options, 2-3
parallel interface, 2-16, 5-11
password, clearing, 4-23
security functions, 4-25
security, chassis, 4-26
security, interface, 4-26
sensor, thermal, 4-28
serial interface, 2-16, 5-8
sideband addressing, 4-11
signal distribution, 6-9, 6-11
Smart Cover Lock, 4-26
Smart Cover Sensor, 4-26
SMBIOS, 7-16
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SMI, 4-18
speaker, 5-26
specifications
temperature status, 7-15
thermal sensing, 4-28
typematic, C-8
electrical, 2-18
UART, 5-8
environmental, 2-18
physical, 2-19
power supply, 6-9, 6-10, 6-11
Specifications
8x CD-ROM Drive, 2-20
Audio subsystem, 5-31
Diskette Drive, 2-19
SCSI Host Adapter, G-3
specifications, system, 2-18
SSE2, 3-2
Universal Serial Bus (USB) interface, 5-22
upgrading, BIOS, 7-2
upgrading, NIC, 5-37
upgrading, processor, 3-4
USB interface, 5-22
USB keyboard, C-4
USB legacy support, 7-23
USB ports, 2-16
VESA connector, F-6, H-7, H-9
voltage, core, 6-8
status, LED, 4-27
wake up (power), 6-4
wake up events, 6-4
wake up, remote, 5-34
Wake-On-LAN, 5-33, 6-4
Windows keys, C-9
system board, 2-10, 2-11
system ID, 7-6, 7-14
system memory, 2-16
system resources, 4-15
system ROM, 7-1
WOL, 5-33, 6-4
system status indications, 4-27
TAFI, 4-29
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