DLP PROJECTOR
SERVICE MANUAL
MODEL：PE8700
CAUTION
BEFORE SERVICING THE PROJECTOR,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
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1. Safety Precautions
1. Be sure to read this manual before servicing and save it for future reference.
2. The lamp becomes extremely hot during operation. Allow the projector to cool for
approximately 45 minutes prior to removing the lamp assembly for replacement. Do not
operate lamps beyond the rated lamp life. Excessive operation of lamps beyond the
rated life could cause them to explode on rare occasions.
3. Never replace the lamp assembly or any electronic components unless the projector is
unplugged.
4. To reduce the risk of electric shock, do not disassemble this appliance. Take it to a
qualified technician when service or repair is required. Incorrect re-assembly can cause
electric shock when the appliance is subsequently used.
5. Do not place this product on an unstable cart, stand, or table. The product may fail,
sustaining serious damage.
2. Servicing Precautions
1. When replace the lamp, be sure to avoid burns your fingers because the lamp becomes
too hot.
2. Never touch the lamp bulb with a finger or anything else. Never drop it or give it a shock.
They may cause bursting of the bulb.
3. This projector is provided with a high voltage circuit for the lamp. Do not touch the
electric parts of power unit when turn on the projector.
4. Do not touch the exhaust fan during operation.
2
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3. Engineering Specification
Superscripts indicate the method in Appendix B used for a given measurement, unless otherwise
noted.
1.0 Image Quality
1.1 Brightness
All tests must adhere to the assumptions in Appendix A
(In ‘optical test’ mode)
660 ANSI Lumens
450 ANSI Lumens
(In ‘optical test’ mode)
73 %
1.1.1 Typical
1.1.2 Minimum
1.2 Brightness Uniformity
1.2.1 Typical
1.2.2 Minimum
60 %
1.3 Contrast Ratio
1.3.1 Peak Contrast
1.4 Light Leakage
1.4.1 Blue Edge
(In ‘optical test’ mode)
1400:1 (Minimum)
Procedure: Test @ distance 3m with 100% white pattern
Criteria: Color coordinateΔx,Δy≦0.015 (compared with the
center)
1.4.2 Light Leakage out of < 1 lux @ diagonal 60”
Active Area
1.4.3 Reflective Edge
Condition: distance 3m or image of 100” wide
Test Pattern: without connecting any source to projector
Criteria: No horizontal and vertical lines outside of the image
Test Pattern: Blue 90 with linear de-gamma / Gray 6
1.4.4 Blemish / Dust
Criteria: Follow HD2 DMD image quality specifications
All Color Measurements must adhere to the assumptions in
1.5 Color
Appendix A
TBD --PPR final
X
Y
1.5.1 100% Gray (White)
1.5.4 Red
.274 ± .04
.647 ± .04
.304 ± .04
.129 ± .04
x
.318 ± .04
.341 ± .04
.566 ± .04
.080 ± .04
y
1.5.5 Green
1.5.6 Blue
1.6 Color Uniformity20
1.6.1 100% Gray (White)
1.6.2.1 L1->L9
±.04
±.04
±.04
±.04
1.6.2.2 E10->E13
1.7 Mirror Defects / Dot Defects Dark pixels<=2, bright pixels =0 (See Appendix D)
1.8 Image Distortion Pincushion 1.0%
3
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Keystone
1.0%
1.9 Descriptive Image Quality
1.10 Lateral Color
There should be no streaks or jitter, good saturated colors, and
crisp resolution. Must adhere to Appendix E
1 Pixel
1). 52” Diagonal for OPT test;
2). Distance 3.0m for Focus test. ( Tele @ the same Throw
Distance. )
1.11 Screen Size for Testing
Criteria: Pixel clear ( same as test chart )
2.0 Optical
2.1 Optical Structure
Single Chip 0.8” 12° tilt DMD ( HD2 ) from Texas Instruments
(HD2 Front Projection Image Quality Specification described in
Appendix D)
2.2 Projection Lens
2.2.2 F/#
Manual Zoom & Focus
2.8
2.2.3 Throw Ratio
2.2.4 Zoom Ratio
100” Diagonal at 3m ( Wide )
1.2 : 1
2.2.5 Focus and flare As following chart:
2.3 Lamp
2.3.1 Maker
Ushio
2.3.2 Model
NSH 210 MD
DC lamp
2.3.3 Type
2.3.4 Lamp Wattage
2.3.5 Lamp life
210 watts
1000 Hours ( Typical )
1.5 – 5m
2.4 Focus Distance
2.5 Keystone Correction
2.5.1 Electronic
± 12°
2.6 Colors
24-bit color
2.7 Native Resolution
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2.7.1 PC Mode
1280 x 720 pixels
1280 x 720 pixels
2.7.2 Video Mode
3.0 Mechanical & Cosmetic
3.1 Dimensions
3.2 Weight
400L x 347W x 116H
16.7 lbs (7581 g)
3.3 Security Slot
3.4 Feet
Kensington compatible slot 150N break away force
4 adjustable feet
3.5 Lamp Replace Position
4.0 Compatibility
4.1 RGB
Front
Supporting timing: see appendix E
PC Compatible VGA, SVGA, XGA
Composite, S-Video, Y/CB/CR
DTV Y/PB/PR , DTV RGBHV ,DTV DVI-I ( 480P, 1080i, 720P,
576P, 540P)
4.2 Video Signal
4.3 HDTV
4.4 Image Inversion
4.5 Scaling
Mirror, Upside-down, Mirror Upside-down
Scaling from other resolutions to native by O-plusTM scaling
chip
4.6 Aspect ratio
5.0 Interface Connectors
5.1 RGB Input
ANAMORPHIC, 4x3, LETTER BOX, VIRTUAL WIDE.
DVI x 1 (include 5.2.5)
5.2 Video Input
RCA x 1
5.2.1 Composite
5.2.2 S-Video
S-Video x 1
RCA x 3
5.2.3 Component
5.2.4 Progressive component BNC x 5
and DTV RGBHV
5.2.5 Digital Video
5.3 RS232C Input
DVI x 1 with HDCP
Telephone jack
6.0 Electrical
6.1 RGB
6.1.1 Input
6.1.1.1 Amplitude
0.7 ± 0.1 VPP at 75Ω termination, positive bright
75Ω
6.1.1.2 Input
Impedance
6.1.1.3 Synch
TTL compatible
6.1.2 Computer
Compatibility
The unit should be compatible with normal computer formats
ranging from VGA to XGA.
6.1.3 Video Compatibility Don’t use BUBUKAU DVD for test equipment.
5
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6.2 Control
6.2.1 IR Receivers
6.2.1.1 Location
6.2.1.2 Range
2receiver, located on the front and rear of this projector
8m ( front ) / 5m ( rear ) with 30 degree horizontal Angle and 15
degree vertical angle
7.0 Power Requirements
7.1 Power Supply
7.2 Power Consumption
7.3 Power Connector
8.0 Audible Noise Level
9.0 Thermal
VAC 100 – 240 Full range switch (50/60Hz), 3 Wire Grounded
310W max.
IEC
34 dB ( Max) @ 25℃ sea level
9.1 Surface Metal
60°C
65°C
80°C
70°C
9.2 Surface Plastic
9.3 Exhaust Air
9.4 Screws, Terminals
10.0 Contamination
10.1 Prevention
Optical system is closed
No noticeable dust
10.2 Dust in Optical Path
11.0 Included Accessories
11.1 Cables
Power Cord Set (US, UK, Euro) x 1, VGA Cable (1.8m) x 1,
Projector Common Cable x 1
11.2 Printed Matter
11.3 Remote Control
12.0 User Interface
12.0 Backlight
User’s manual
IR Remote x 1, AAA Batteries x 2
NO
12.1 Operator Panel
12.2 Indicators
YES
Power Status LED, Lamp Status LED
12.3 Remote Control
12.4 Onscreen Menu
12.8 User’s Manual
13.0 Reliability
Front IR receiver , Rear IR receiver
Should be in 3 languages (English, French, Spanish )
Should be in 3 languages (English, French, Spanish )
13.1 General Failure Def.
13.2 MTBF
See Appendix B
20000 hours except for DMD chip , lamp , fans and color wheel.
14.0 Environmental
14.1 Operating
10 – 35°C, 20 – 90%RH, without condensation
-10 – 70°C, 20 – 90%RH, without condensation
0 – 6000 feet above sea level, ambient 30 ℃
14.2 Storage
14.3 Altitude
14.4 Shock
6
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14.4.1 Straight Drop
14.4.2 Tilt Over
50mm
Should be able to fall over from tilting without taking any
damage. Must Adhere to Appendix B
No corrosive, toxic, or combustible gas should be emitted
comply to the acceptance criteria as specified in EN
61000-4-2/1995
14.5 Gas
14.6 Electrostatic Discharge
15.0 Regulatory
UL, CE, FCC Class B. Must Adhere to Appendix B Section 10.0
UL compliance: UL6500 (2th Version)
CSA compliance: E60065-00
15.1 Safety Requirements
TUV compliance: IEC60065:2001
CCC: GB8898; GB13837; GB17625.1: 1998
1. CE Mark compliance: EMC: 89/336/EEC
15.1 EMI Requirements
EN 55013:1990+A12 :1994+A13 :1996+A14 :1999
EN 61000-3-2:1995+A1 :1998+A2 :1998+A14 :2000
EN 61000-3-3:1995+A1 :2001
EN 55020:1994+A1 :1996+A12/A13/A14 :1999
IEC 61000-4-2/2001
IEC 61000-4-3/2001
IEC 61000-4-4/1995+A1:2000+A2:2001
2. FCC
FCC Part 15B
3. C-Tick
ASIN2S 1053:1996
4. VCCI
VCCI/2002(15th Edition)
16.0 Packaging
16.1 Packaging Form
16.1.1 Dimensions
16.1.2 Weight
Must adhere to attached file
537 x 520 x 260 mm
TBD
16.1.3 Palletization
16.1.4 Carton Labeling
16.2 Vibration
1140 x 1050 x 120 mm
Must adhere to attached file
Must adhere to Appendix B
Must adhere to Appendix B
16.3 Drop Test
7
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Appendix A Optical Measurement
This part of the Optical Test Instruction describes those measurements to be executed
during the production of the optical engines.
Content:
A1 BRIGHTNESS
A2 BRIGHTNESS UNIFORMITY
A3 BRIGHTNESS DIFFERENCE
A4 ANSI CONTRAST
A5 PEAK CONTRAST
A6 LIGHT LEAKAGE
A7 IMAGE DISTORTION
A8 THROW RATIO
A9 ZOOM RATIO
A10 FOCUS RANGE
A11 COLOR
A12 COLOR UNIFORMITY
A13 OPTICAL KEYSTONE (FIXED)
ꢀ
General requirements
1. The unit shall be allowed to stabilize without further adjustment for a
minimum of 10 minutes, at nominal ambient room temperature of 25°C,
before making measurements.
2. Measurements shall take place in a light proof room, where the only source of
illumination is the projector. Less than 1% of the light on the screen shall be
from any source other than the projector.
3. All measurements shall be made on flat screens that do not provide any
advantage to the performance of the unit
4. All measurements shall be made at standard color temperature setting, 100%
white image (per ANSI IT7.228-1997), except where noted
8
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ꢀ Practical consideration
1. When measuring contrast manually, operators should not wear white
clothing since light reflected from white clothing can influence the
measurement.
2. Unless otherwise specified the projection lens is set in the widest zoom
position since zoom function can influence the measurement.
3. Measurement should be performed with Minolta Chromameter, Model
CL-100, or equivalent.
ꢀ A1. BRIGHTNESS
Unit:
Lumen
Brightness: Default
Contrast:Default
W: width of projected image; H: height of projected image
A (Area) = W * H (in meters)
L1+ L2 + L3+ L4 + L5 + L6 + L7 + L8 + L9
ANSI Lumens =
(lux) ∗ A(m2 )
9
1
3
1
6
W
W
1
6
H
H
1
3
9
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ꢀ
A2. BRIGHTNESS UNIFORMITY
Unit:
Brightness: Default
%
Contrast:
Default
MIN(E10, E11, E12, E13)
Uniformity =
L1+ L2 + L3 + L4 + L5 + L6 + L7 + L8 + L9
9
1/20w
1/20h
E10
E11
L5
E12
E13
ꢀ
A3. BRIGHTNESS DIFFERENCE
Unit:
%
Brightness: Default
Contrast:Default
Brightness Difference=
(MAX (E10, E11, E12, E13) − MIN (E10, E11, E12, E13))
L1 + L2 + L3 + L4 + L5 + L6 + L7 + L8 + L9
9
ꢀ
A4. ANSI CONTRAST
Unit: Contrast : 1
Brightness: Default
Contrast:Default
Contrast Ratio shall be determined from illuminance values obtained from a
black-and-white ”chessboard” pattern consisting of 16 equal rectangles. The
white rectangles shall be at 100% gray and the black rectangles at 0% gray.
Illuminance measurements shall be made at the center of each of the rectangles.
Contrast Ratio = Average lux value of the white rectangles/Average lux value
of the black rectangles
10
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ꢀ
ꢀ
ꢀ
A5. PEAK CONTRAST
Unit: Contrast : 1
Brightness: Default
Contrast:Default
Contrast Ratio = Lux value at the center of a solid white screen/the lux value
of a solid black screen
A6. LIGHT LEAKAGE
Unit:
Lux
Brightness: Default
Contrast:Default
Leakage = The maximum light leakage of a solid black screen outside the
projected image
A7. IMAGE DISTORTION
Unit:
Brightness: Default
Contrast: Default
%
Measurement procedure:
Measure the dimensions H1, H2 and H3, with H3 at the half image width, as
shown above for both zoom settings. For each the distortion is defined as:
H1+ H 2 − 2* H3
TV − dist =
*100%
2* H3
All should be within the absolute specification tolerance.
ꢀ
A8. THROW RATIO
Unit:
Ratio : 1
Brightness: Default
Contrast:Default
Throw ratio = projection distance / the width of the projected image
11
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ꢀ
ꢀ
A9. ZOOM RATIO
Unit: Ratio : 1
Brightness: Default
Contrast:Default
Zoom ratio = maximum / minimum image diagonal size at a fixed projection
distance.
A10. FOCUS RANGE
Unit:
m (Max~Min)
Brightness: Default
Contrast:Default
The minimum/maximum focus distance is the minimum/maximum projection
distance (front side projection lens and the image lane), expressed in meter,
at which the image is still at its best for focus.
A11. COLOR
ꢀ
Unit:
x, y
Measurements at the center (except in the case of color uniformity
measurements) of a screen which is entirely of the color being measured and
at default brightness and contrast settings.
ꢀ
ꢀ
A12. COLOR UNIFORMITY
Unit:
x, y
Difference between any two points out of Lx and Ex should not exceed the
specification for the given color.
A13. OPTICAL KEYSTONE (FIXED)
Unit:
%
Brightness: Default
Contrast: Default
Measure the dimensions W1, W2 and W3 at the half image height, as shown
above. The distortion is defined as:
W1−W3
W3
W 2 −W3
W3
TV − dist =
*100% & TV − dist =
*100%
12
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Appendix B Design Verification Test Procedure
1.Purpose
This standard establishes the environmental specification for projector related
products, which defines the level of product performance and reliability in the field. It is not
necessary the intent of these specification to simulate a typical user environment, but rather
to provide for a level of product robustness that when applied over a wide range of
manufacturing variability and environmental usage conditions.
2.Test Summary
Dynamic Testing
Package Drop
Specification
76cm, 1 drop per orientation, all 6 primary surfaces, plus a selected
corners, and three selected edges, total of 10 drops
Random , 0.01g2/Hz, 5~100Hz, all primary axis, 20 min per orientation,
total of 60min
Package Vibration
Sine, 0.5g, 5~200Hz, 1 octave/min, 15 min dwell on each resonant
frequency, all primary axis, one sweep (30min minimum) per orientation,
total of 90+min
Shock, non-operating
50g, 20ms half-sine, all primary axis, 1 shock per orientation, total of 3
shocks
Security Lock
Fragility
150N break away force
Shock, 50g, 20ms half-sine, all primary axis, 1 shock per orientation, total
of 3 shocks
o
Accelerate Life Test (operating), 65 C, 72hr
o
Thermal shock(bare board), -65~125 C, 48hr
Input Voltage, 90~264V
Input RGB signal, 0.7V±0.1
Atmospherics
Temperature/Humidity,
operating
o
10~35 C/10~80RH, 48hr
o
Temperature/Humidity,
non-operating
Altitude, operation
Safety/EMC
-10~70 C/10~80RH, 48hr
o
0~6000ft@30 C, 4hr
UL/cUL
TUV Rheinland
Fcc/CE/C-Tick
13
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3.Definition
3.1 Failure Criteria:
The product is expected to perform to its full potential without loss of function,
performance, critical parametric changes, and other undesirable anomalies, over the
applied boundaries of this specification. The following product failure are not allowed within
the boundaries defined in this specification:
1.Failure including permanent damage, critical parametic changes (optical
performance defined in Appendix A), and latent defects.
2.Failure requiring operator intervention.
3.Failure violating external laws, regulatory agency standards, and government
directives.
4.Failure resulting in a safety, potential safety, issue.
3.2 EUT: Equipment under Test
3.3 Q: Peak Acceleration Response divided by acceleration input peak
4.Test Order
Atmospherics, Dynamic, and Safety test sets require separate units and can be
processed in parallel. EUT testing shall be performed serially within each set.
Set 1 (3 units)
Dynamics:
Set 2 (3 units)
Set 3
Atmospherics:
Safety/EMC:
EFT
Package Drop
Temperature/Humidity, Operating
Package Vibration Temperature/Humidity,
Non-operating
ESD
Shock
Altitude, Operating
Aging
EMI-Radiated
Bench Drop
EMI-Conducted
EMI-Susceptibility
14
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Appendix C
Drawings and Attachments
Drawing 1: Top view of BENQ PE8700 video projector
15
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Appendix D HD2 Front Projection Image Quality Specification
1. SCOPE
This document specifies the image quality requirements applicable to the HD2 Component
Set for Front Projection image display. The HD2 Component Set provides digital imaging
functionality based on Digital Micromirror Device (DMD) technology.
2. DEFINITIONS
2.1 Blemish
A blemish is an obstruction (dark blemish), reflection, or refraction of light (light blemish)
that is visible, but out of focus in the projected image under specified conditions of
inspection (see Table 1). It is caused by a particle, scratch, or other artifact located in the
image illumination path.
2.2 Dark pixel
A dark pixel is a single pixel or mirror that is non-functional (stuck) in the OFF position.
2.3 Bright pixel
A bright pixel is a single pixel or mirror that is non-functional (stuck) in the ON position.
2.4 Unstable pixel
An unstable pixel is a single pixel or mirror that does not operate in sequence with
parameters loaded into memory. The unstable pixel appears to be flickering
asynchronously with the image.
2.5 Adjacent pixels
Adjacent pixels are defined as sharing a common border or common point.
2.6 Border defects
Border defects are bright blemishes (see 2.1) or bright pixel defects (see 2.3) in the
non-active area that may be visible in front projection mode.
2.7 Blue test screen
This screen is used to test for major dark blemishes and dark pixels. All areas of the screen
are colored at a specific blue level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish
Blue Value
Red Value
Green Value
90
0
0
17
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2.8 Gray 6 test screen
This screen is used to test light blemishes and bright pixels. All areas of the screen are
colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Light Blemish
Blue Value
Red Value
Green Value
6
6
6
2.9 Gray 10 test screen
This screen is used to test light blemishes and bright pixels. All areas of the screen are
colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Light Blemish
Blue Value
Red Value
Green Value
10
10
10
2.10 White test screen
This screen is used to test light border blemishes and bright pixels. All areas of the active
area are colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish
Blue Value
Red Value
Green Value
255
255
255
2.11 black test screen
This screen is used to test light border blemishes and bright pixels. All areas of the active
area are colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish
Blue Value
Red Value
Green Value
0
0
0
18
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2.12 Red Ramp test screen
This screen is used to test light border blemishes and bright pixels. All areas of the active
area are colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish
Blue Value
Red Value
Green Value
0
Start 0,end 255
0
3. ACCEPTANCE REQUIREMENTS
3.1 Test Conditions (as tested in OEM projector)
· Projector degamma correction shall be linear. Using HD Control “Curtain” Mode is
equivalent.
· Image noise reduction algorithms “Blue Noise STM” and “Boundary Dispersion” shall be
set to “off”.
· Projector shall be used in front projection mode using a customer-specified screen, and
OEM optical system.
· The diagonal size of the projected image shall be 52 inches (132cm).
· The projected image shall be inspected from a 60 inches (1.52 meter) minimum viewing
distance.
· Projector will be properly focused on the DMD array as shown on the screen.
· Testing time is limited to 20seconds per screen.
· Refer to Table 1 for acceptance criteria, in specified order:
TEST
TEST
SCREEN
ACCEPTANCE CRITERIA
ORDER
1
2
Major Dark Blemish Blue 90
No dark blemishes visible on Blue 90
Dark Pixel
Blue 90
0
dark pixels allowed in Zone A
Zoned Screen (see <=2 dark pixels allowed in Zone B
below figure 1)
Gray 10
No adjacent dark pixels
No border defects visible
3
4
Border Defects
Major Light Blemish Gray 6
No light blemishes visible on Gray 6
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5
6
Light Pixel
Gray 6
No light pixels visible on Gray 6
Total of Dark and Light Blemishes ≦
Minor Blemishes
White or Black
4
(See Test 4 , 5)
7
Unstable Pixel
Red Ramp
Screen(or any
other
No unstable pixels
TABLE 1. Image Quality Specification
Notes:
1. The acceptance basis for all cosmetic DMD defects will be the projected image tests
referenced in Table 1.
2. Projected blemish numbers include the shadow of the artifact in addititon to the artifact
itself.(Count=4)
4. The projected image shall not contain any blemish more than 15 cm long, measured on
a 1.32m diagonal screen.
20
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Appendix E Supporting Timings
Table 1: Support Timings by DVI-I Input (Analog or Digital PC signals)
Resolution
Vert. Freq
(Hz)
Hori. Freq
(kHz)
Pixel freq
(MHz)
25.167
25.167
36.0
Digital (D)/
Analog (A)
D/A
Polarity
1
2
3
4
5
6
7
8
9
VGA
VGA
640 x 400
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
70.089
59.590
85.008
60.317
75.000
85.061
60.004
75.029
84.997
31.470
31.470
43.269
37.879
46.875
53.674
48.363
60.023
68.677
-/+
-/-
D/A
VGA
D/A
-/-
SVGA
SVGA
SVGA
XGA
40.0
D/A
+/+
+/+
+/+
-/-
49.5
D/A
56.25
65.0
D/A
D/A
XGA
78.75
94.5
D/A
+/+
+/+
XGA
D/A
Table 2: Support Timing by DVI-I Input
Index Format
name
Line
Pixel
Rate
Frame Line
Rate active total
(pixel) (pixel) (line)
Line
Frame Frame H back H sync V back V sync
Rate
active total
porch width porch width
(pixel) (pixel) (line) (line)
(kHz) (MHz) (HZ)
480p59 31.469 27 59.94 720
576p50 31.25 27
720p50 37.5 74.25 50
(line)
525
1
2
3
4
5
6
7
8
858
480
59
63
64
40
40
40
44
44
44
30
39
20
20
20
15
15
15
6
5
5
5
5
5
5
5
50
720
864
576
625
68
1280
1980
1650
1650
2640
2200
2200
720
750
260
260
260
148
192
192
720p59 44.955 74.176 59.94 1280
720
750
720p60 45
74.25 60
1280
1920
720
750
1080i25 28.125 74.25 25
1080
1080
1080
1125
1125
1125
1080i29 33.716 74.176 29.97 1920
1080i30 33.75 74.25 30 1920
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Table 3: EDTV and HDTV Timing supported by component (YPBPR) and RGBHV Input
Index Format Line
name Rate
Pixel
Rate
Frame Line
Rate active total
(pixel) (pixel) (line)
Line
Frame Frame H back H sync V back V sync
active total
porch width porch width
(pixel) (pixel) (line) (line)
(kHz) (MHz) (HZ)
(line)
525
1
480i
576i
480p
576p
15.734 13.5
15.625 13.5
31.469 27
31.25 27
59.94 720
50 720
59.94 720
858
480
576
59
63
64
63
64
40
40
40
44
44
44
30
39
30
39
20
20
20
15
15
15
6
5
6
5
5
5
5
5
5
5
2
864
625
68
3
858
480
525
59
4
50
720
864
576
625
68
5
720p50 37.5
74.25 50
1280
1980
1650
1650
2640
2200
2200
720
750
260
260
260
148
192
192
6
720p59 44.955 74.176 59.94 1280
720
750
7
720p60 45
74.25 60
1280
1920
720
750
8
1080i25 28.125 74.25 25
1080
1080
1080
1125
1125
1125
9
1080i29 33.716 74.176 29.97 1920
1080i30 33.75 74.25 30 1920
10
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Chapter 4 Spare Parts List
Projector PE8700
99.J5877.B21
NO
1
Parts NO
Description
55.J2003.001 IR BD HT480W MI
2
55.J5801.011 PCBA MAIN/BD FOR BENQ
3
55.J5824.001 PCBA DMD BOTTOM/BD HT720G
55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI
65.J2004.001 COLOR WHEEL SIX SEGMENT UNAXI
55.J5802.001 PCBA DMD/BD HT720G
4
5
6
7
65.J5801.001 ASSY LENS ZOOM HT720G PROT
71.00HD2.A00 IC MUSTANG DMD PREMIUM CLGA
65.J3403.001 ASSY BALLAST210W/USHIO DX660
55.J2006.010 PCBA KEYPAD/BD HT720G BENQ
55.J5817.001 PCBA TRANSLATION/BD HT720G
60.J2020.021 ASSY CVR BASE HT720W/BENQ
60.J2023.022 ASSY L/C HT720W/BENQ
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
60.J2037.011 ASSY CVR FRONT HT720W/BENQ
60.J2038.011 ASSY CVR BACK CONTOR HT720W
60.J2112.001 ASSY CVR LENS HT720W BENQ
55.J2013.001 PCBA THERMAL SENSOR/B HT480W
55.J2021.001 PCB FPC/BD FOR HT480W
55.J5810.011 PCBA CONNECTOR/BD FOR BENQ
55.J2005.001 PCBA POWER BD HT480W MI
55.J5811.001 PCBA PFC/BD HT720G
44.J2003.021 CTN AB 455X500X228 HT720G/BEN
47.J2008.001 CUSHION FRONT EPE HT480W
47.J5804.001 CUSHION REAR EPE HT720G BENQ
50.J2103.501 CABLE RGA/DVI-A (WHDDC) 1.8M
50.L2508.501 SIGNAL/C DUAL DVI-D/DVI-D 200
60.J2028.R01 ASSY AV CABLE RUNCO CL-500
98.J2032.B01 HT480W BENQ REMOTE CONTROL
60.J2104.CG1 ASSY CSD LAMP MODULE PE8700
23
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5. Black Diagram
Conntctor Board
Main Board
DMD Board
Sil169
(U17)
RGB DVI
RGB PC
DMD
MUX
(U2,U3,U4)
ADC AD9883
(U7)
RGB/YPbPr
BNC
Color
Cheel
HD2
Scaler
RM1-A
(U5)
YCbCr
YPbPr
Reset IC
(U18)
De-interlace
SII504
(U2)
Blaster
Lamp
MUX
(U5)
Video Port
SDRAM
(U19,U20,
U21)
S-video
Video
YCbCr
Video Decoder
SAA7118
400V
SDRAM
(U3)
MCU503
(U4)
(U10)
IR Board
PFC
Board
RS232
Download
(U14)
SRAM
(U9)
RS232 RJ11
IR (TOP)
3.3V
CPU RDC8820
(U10)
Frash
(U12)
IR
(U12)
Power
Board
5V
12V
RS232
Hardware
Monitor
(U14)
12V
(Q2,Q3)
12V Trigger O/P
IR BoaIR
Board
Translation Board
Protection
IR (front)
Keyboard
Fan
Driver
(U1,U3)
Circuit
(U4)
Thermal
Sensor
Thermal
Break
Fans
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6. Packaging Description
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7. Appearance Description
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8. Alignment Procedure
1. DMD Bias Voltage Alignment
Equipment:
- None
Procedure:
1. Watch DMD chip Label
2. Switch the DIP switch on DMD board according to the character on the DMD chip
B
1 of SW H1 1
2 of SW H2 1
C
0
1
D
1
0
E
0
0
0: Left; 1:Right
2.Color Wheel Delay Alignment
Equipment:
- Battery Biased Silicon PIN Detector
- Oscilloscope
- Probe
OSD Default value used for color delay alignment
Item
Value
Item
Value
USER>DVI-A>
Brightness
Contrast
Color
Factory>DLP>
Brightness
Contrast
0
30
60
15
0
0
49
20
CW delay
Tint
User>Setup>Whit
Red Gamma
Green Gamma
Blue Gamma
R gain
Sharpness
Filter
66
66
66
512
512
512
0
2
Color Temp
0
G gain
B gain
R Offset
G Offset
0
B Offset
0
The default values let optical engine to get maximum contrast and brightness.
28
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Procedure:
1. Probe impedance matches 50 ohm
2. Change Timing and pattern of pattern generator :
Timing : 800x600@60Hz (H:37.879Khz,V:60.317Hz)
pattern : full white
3. Adjust user & factory OSD values to default.
4. Open Factory OSD, and select color wheel delay item.
5. The image will become white.
6. Put the detector on the screen that white image was projected.
7. Watch the oscilloscope and notice the square waveform
8. Use the “ꢁ” and “ꢂ” key to increment or decrement the color wheel delay value
9. No matter the waveform is square or not, let the waveform was lagged first
Lag
Exact
10. Then increment or decrement the value to let the waveform to be square
11. Do not adjust too much, let the signal get ahead, if it happens, go back to step 7 and do
it again.
Ahead
12. Select “Save Setting” at “Factory OSD>Factory>”.
29
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3. DVI-Analog Color Alignment Procedure
Default valve(User menu)
contrast
color
23
Sharpness
Video
S-Video
Comp
17
17
17
17
17
17
3
1
0
3
3
1
23
30
Comp-HD
RGBHV
DVI-I
30
30
30
The Gamma(RED ,GREEN,BLUE) is 66 for temperature 0,1,2,3,4.
Equipment:
- Pattern generator (Chroma 2250)
- Lux meter ( CL-100)
OSD Default value used for DVI-Analog color alignment
Item
Value
Item
Value
USER>Picture>
Brightness
Contrast
Color
Factory>HDADJ>RG
R offset
30
17
30
15
1
55
63
62
89
89
89
G offset
B offset
Tint
R Gain
Sharpness
Filter
G Gain
1
B Gain
Color Temp
2
Factory>DLP
Brightness
0
Contrast
49
User>Setup>White
Gamma Red, Green,
Gamma Red, Green,
66
0
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Procedure:
A. Black Level Adjustment: (DLP brightness)
1.
2.
Change pattern of pattern generator :
Pattern : Black (Gray 0)
Adjust DLP Brightness to let the black picture to just distinguish.
B. White Level Adjustment: (AD contrast---R,G,B gain)
1. Change pattern of pattern generator :
pattern : White (100% Gray)
2. Use Lux meter to measure the white level. Adjust the contrast value of AD9883 (RGB)
to let the light output to just max.
3. Change to 32-gray (0 ~ 100%) pattern. All steps must appear,
C. Offset adjustment at low brightness (AD R, G, B offset)
1. Change Timing and pattern of pattern generator :
pattern : 10% Gray
2. Set user color temp to 6500K.
3. Adjust AD9883 Red and Blue Offset to meet 6500K color spec.
D. Color Temperature at high brightness (Scalar Gamma R, G, B Gain)
1. Change Timing and pattern of pattern generator :
Timing : 800x600@60Hz (H:37.879Khz,V:60.317Hz)
Pattern : 80% gray
2 Color temperature spec: CIE 1976 u’, v’ chromaticity)
Color temperature
5400°K
6500°K
7500°K
27u'
18u' − 48v' + 36
0.333
0.312
0.296
x =
12v'
0.333
0.210
0.329
0.197
0.316
0.190
y =
18u' − 48v' + 36
4x
u' =
− 2x +12 y + 3
9y
v' =
0.473
0.468
0.459
− 2x +12 y + 3
Deviation:
<=0.010
<=0.010
<=0.010
u’v’= (∆u'2 + ∆v'2
Color Temp 4 = color temp is the same as that of 6500K
31
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3 The variance of color coordinate via R,G,B gains:
x
X ↓
-
Y
-
R ↓
G ↓
B ↓
y ↓
y ↑
X ↑
4. Adjust 6500K temperature color by changing Gamma-Rgain, Ggain, and Bgain.
5. Open Factory OSD and set the factory default value :
user>setup>white
C0
C1(5400k C2(6500k C3(7500k
Gamma-Rgain
512
512
412
398
512
467
452
512
479
490
Gamma-Ggain
Gamma-Bgain
512
512
User the lux meter and adjust Gamma-Rgain, Gamma-Ggain, & Gamma-Bgain to
meet the spec.
6. Press “Save Graphics Color Temp” to save current setting into memory.
7. Select “Save Setting” at “Factory OSD>Factory>”.
8.Change pattern to 10% gray pattern and measure the color temp. If 6500K color spec is
not met, repeat all procedures in C and D.
9. Follow step 1 to 8 to adjust 5400K, 7500K color temperature.
10. For auto-alignment, use Command Y31/Y32/Y33 to save 5400K/6500K/7500K
temperature
11. For auto alignment, use Command to reset Temp4 color temp to 6500K
4. YPBPR Color Alignment
(A) YPbPr Component:
Equipment:
- Pattern generator (VG-828)
- Lux meter ( CL-100)
OSD Default value used for YPBPR color alignment
Item
Value
Item
Value
USER>Picture>
Brightness
Contrast
Color
30
17
30
15
Tint
Factory>HD ADJ>YPbPr>
Sharpness
3
Brightness
60
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Filter
1
2
Contrast
Saturation
Pb offset
Pr offset
76
49
60
60
Color Temp
Procedure:
(a). PBPR Offset adjustment: (AD PB, PR Offset)
1. The variance of color coordinate via Pb offset and Pr offset:
x
y
Pb offset ↓
Pb offset ↑
Pr offset ↓
Pr offset ↑
x ↓
x ↑
x ↑
x ↓
y ↓
y ↑
y ↓
y ↑
If we line the x and y, then the Pb offset is the shift action and the Pr offset is the
rotational action.
2. Connect power, YPbPr Video into projector.
3. Change Timing and pattern of pattern generator :
Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : 10gray Pattern
4. Turn on projector
5. Set user OSD values to default.
6. Enter factory mode.
7. Set Factory values to default.
8. Follow the Pb, Pr offset adjustment flow chart to adjust color temperature to 6500K
b). Gray Level: (AD YPBPR Contrast, Brightness)
1.
2.
Change Timing and pattern of pattern generator :
Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : gray 32( or gray16 only for overscan)
Adjust the Brightness of AD9883 (RGB) to let the black level of the gray
32 to just distinguish. Use Lux meter to measure the white level of the gray 32. Adjust
the contrast value of AD9883 (RGB) to let the light output to just max.
3. Check the 32 levels of gray. All steps must appear,
33
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(c). Saturation Level: (Scalar)
1. Change Timing and pattern of pattern generator :
Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : 100% blue
2. Adjust saturation and use lux meter to measure to let the light output just max.
3. Select “Save Setting” at “Factory OSD>Factory>”.
UseLuxmeterto
readthecoordinateof
blackandthevalue
note(x1,y1).
Case
x1>x0& y1>y0
Case
x1<x0& y1<y0
Case
x1>x0& y1<y0
Case
x1<x0& y1>y0
DecreasePboffset
until x<=x0or
y<=y0
IncreasePboffset
until x>=x0or
y>=y0
IncreaseProffsetuntil
x<=x0ory>=y0
DecreaseProffset
until x>=x0ory<=y0
D
A
B
C
Casex<=x0:
Thevaluenote(x2,y2).
Dy=y2-y0.
Casey<=y0:
Thevaluenote(x2,y2).
Dx=x2-x0.
Casex>=x0:
Thevaluenote(x2,y2).
Dy=y0-y2.
Casey>=y0:
Thevaluenote(x2,y2).
Dx=x0-x2.
Casex<=x0:
Casey>=y0:
Casex>=x0:
Casey>=y0:
DecreasePboffsetuntilthey
value<=y2-1/2Dy.Now,the
readingoftheLuxmeter=
(x3,y3)andx3will<x0,y3will
>y0.
DecreasePboffsetuntilthex
value<=x2-1/2Dx.Now,the
readingoftheLuxmeter=
(x3,y3)andx3will>x0,y3will
<y0.
IncreasePboffsetuntilthey
value>=y2+1/2Dy.Now,the
readingoftheLuxmeter=
(x3,y3)andx3will>x0,y3will
<y0.
IncreasePboffsetuntilthex
value>=x2+1/2Dx.Now,the
readingoftheLuxmeter=
(x3,y3)andx3will<x0,y3will
>y0.
C
B
A
D
DecreaseProffsetthexvalue
willincreaseandyvaluewill
decreasetomeetthespec.
IncreaseProffsetthexvaluewill
decreaseandyvaluewillincrease
tomeetthespec.
IncreaseProffsetthexvaluewill
decreaseandyvaluewillincrease
tomeetthespec.
DecreaseProffsetthexvalue
willincreaseandyvaluewill
decreasetomeetthespec.
34
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Case x1>x0 & y1 > y0 :
y =.331
dy=.01
1/2dy=0.005
dec. Pb
x =.291
x =.281
y =.321
y =.316
dec. Pb
dec. Pr
x0 =.281
y0 =.311
x0 =.281
y0 =.311
x0 =.281
x =.276
y0 =.311
x =.281
y =.311
x =.301
dx=.01
1/2dx=0.005
dec. Pb
y =.321
x =.291
y =.311
x =.286
dec. Pb
inc. Pr
x0 =.281
y0 =.311
x0 =.281
y0 =.311
x0 =.281
y0 =.311
y =.306
x =.281
y =.311
Case x1<x0 & y1 < y0 :
dy=.01
1/2dx=0.005
inc. Pb
x =.286
inc. Pb
inc. Pr
x0 =.281
x =.271
y0 =.311
x0 =.281
x =.281
y0 =.311
y =.301
x0 =.281
y0 =.311
y =.306
x =.281
y =.311
y =.291
dx=.01
1/2dx=0.005
inc. Pb
y =.316
dec. Pb
dec. Pr
x0 =.281
x =.261
y0 =.311
y =.301
x0 =.281
x =.271
y0 =.311
y =.311
x0 =.281
x =.276
y0 =.311
x =.281
y =.311
Case x1>x0 & y1 < y0 :
dy=.01
1/2dx=0.005
inc. Pb
x =.291
x =.286
inc. Pr
x =.281
inc. Pr
x0 =.281
y0 =.311
y =.291
x0 =.281
y0 =.311
y =.301
x0 =.281
y0 =.311
y =.306
x =.281
y =.311
x =.301
dx=.01
1/2dx=0.005
dec. Pb
x =.291
y =.311
x =.286
inc. Pr
inc. Pr
x0 =.281
y0 =.311
y =.301
x0 =.281
y0 =.311
x0 =.281
y0 =.311
y =.306
x =.281
y =.311
Case x1<x0 & y1>y0
y =.331
dy=.01
1/2dy=0.005
dec. Pb
y =.321
y =.316
dec. Pr
dec. Pr
x0 =.281
x =.271
y0 =.311
x0 =.281
x =.281
y0 =.311
x0 =.281
x =.276
y0 =.311
x =.281
y =.311
dx=.01
1/2dx=0.005
inc. Pb
y =.321
y =.316
dec. Pr
dec. Pr
x0 =.281
x =.261
y0 =.311
x0 =.281
x =.271
y0 =.311
y =.311
x0 =.281
x =.276
y0 =.311
x =.281
y =.311
35
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5. TV Color Alignment Procedure
5.1 TV Color Temp Alignment
Equipment:
- Pattern generator (VG-828)
- Lux meter ( CL-100)
OSD Default value used for YCBCR color temp alignment
Item
Value
Item
Value
USER>Picture>
Brightness
Contrast
Color
30
17
30
15
0
Tint
Factory>SD
Sharpness
Filter
Brightness
180
92
3
Contrast
Color Temp
2
Saturation
90
User>Setup>White
Gamma Red, Green,
Gamma Red, Green,
66
0
1. Connect the signal to YCBCR component connector, and change Timing and pattern of
pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : 80% Gray
2. Color temperature spec:
Color temp. 4 is the same as that of 6500K
3. The variance of color coordinate via R,G,B gains:
4. Adjust 5400K / 6500K / 7500K temperature color.
5. Open Factory OSD and set the factory default value :
User>setup>white
C0
C1(5700k C2(6500k C3(9300k
Gamma-Rgain
512
512
416
408
512
467
460
512
490
508
Gamma-Ggain
Gamma-Bgain
512
512
36
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6. User the lux meter and adjust Gamma-Rgain, Gamma-Ggain, & Gamma-Bgain to meet
the spec.
7. Press “Save Color Temp. Videos > AS Color Temp 5400” to save into memory.
8. Repeat 6~7 to perform the 6500K and 7500K color temperature.
9. Select “Save Setting” at “Factory OSD>Factory>”.
10. For auto-alignment, use Command Y80/Y81/Y82 to save 5700K/6500K/9300K
temperature.
5.2 Gray Level for YCBCR Component
Procedure:
(a). Gray Level:
1. Connect power, YCbCr Video into projector.
2. Change Timing and pattern of pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : gray 32( or gray16 only for overscan)
3. Light on projector
4. Set user OSD values to default.
5. Enter factory mode.
6. Set Factory values to default.
7. Adjust the Brightness and Contrast to let the black level to just distinguish, and the
light output of white level to just max.
8. Check the 32 levels of gray. All steps must appear,
(b). Saturation Level:
9. Change Timing and pattern of pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : 100% blue
10.Adjust saturation and use the Lux meter to measure to let the light output just max.
11.Select “Save Setting” at “Factory OSD>Factory>”.
37
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5.3 Gray Level for Composite Video & S-Video
Equipment:
- Pattern generator (VG-828)
- Lux meter ( CL-100)
OSD Default value:
Item
Value
Item
Factory>SD
Value
USER>Picture>
Brightness
Contrast
Color
30
17
23
15
3
Brightness
Contrast
Saturation
Hue
158
75
91
0
Tint
Sharpness
Filter
3
Color Temp
2
Procedure:
(a) Gray Level
1. Connect power, Composite video or S-Video, into projector.
2. Change Timing and pattern of pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : gray 32( or gray16 only for overscan)
3. Light on projector
4. Set user OSD values to default.
5. Enter factory mode.
6. Set Factory values to default.
7. Adjust the Brightness and Contrast to let the black level to just distinguish, and the light
output of white level to just max.
8. Check the 32 levels of gray. All steps must appear,
(b). Saturation Level:
9. Change Timing and pattern of pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : 100% blue
10. Adjust saturation and use lux meter to measure to let the light output just max.
11. Select “Save Setting” at “Factory OSD>Factory>”.
6. Additional Patterns used for color final check
(a). Pattern 1: 0 ~ 14% gray, 2% change per step, (For DVI-A, YPBPR inputs)
Criteria: All gray bars should have the same color. Brightness change should be linear.
(b) Pattern 2: 16-gray (0 ~ 100%), For all input sources
Criteria: All gray bars should have the same color. Brightness change should be linear.
38
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9. Trouble Shooting Guide
1. System trouble shooting :
Is LED light when
n
Check door luck
switch
1.Check +3Vs, +5Vs
n
Main Power Switch
2. Check power
on?
y
Is Orange LED
n
Are fans spinning?
Check fans, wire and
Translation board
n
active when remote
power on?
y
Check DMD board
Check ballast
Check lamp
Is lamp turned on?
n
Check DMD board
Check DMD
socket
y
y
Does starting OSD
n
Does any stripe
shows normally?
shows on screen?
n
Check Main board, DMD
board
y
Does DVI-I signal
n
Check Connector
board and FPC
board
shows normally?
y
Does Video signal
shows normally?
Check Main board ,
FPC and Connector
board
n
39
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2. Main board trouble shooting:
(1) Main:
1. See CPU trouble shooting
REMOTE
U18, reset successful?
2. U17, RP25, RP24 OK?
3. CPU (U10) 56pin(IR) signal?
POWERON
NO
NO
YES
OSD ok?
When no valid
signal
1. RP19,RP17,RP15,RP13
ok?
2. U19, U20 OK?
3. Check L8 with 100Mhz ok?
4. check L9 with 40Mhz ok?
YES
OSD ok.
When input PC
signal
1.check J2
NO
NO
YES
1. RP1, RP2, RP3, RP4, R6
R3, R2, R4 ok? (SIL504
output)
OSD ok.
When input
Video signal
2. check J2
YES
1.Replace U6 (EEPROM)
2.check R36 R37(IIC pull high
resistors)
Saving data in
EEPROM
NO
40
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(2) SIL504 trouble shooting: (U4, U2)
1. check X1, C41, C42
X1, 20Mhz?
RESET
2. check U17,RP25
successful?
No
No
No
No
YES
System IIC ok?
(U4 pin 15,14)
1.Q2,Q3 ok? (level shift )
2. RP7 ok? ( IIC Pull high)
YES
SIL504 IIC ok?
(U4 pin 2, 3)
1. R10,R11ok? ( IIC Pull
high)
2. Replace U4
YES
DEINTDONE
Signal ok? (U4
pin21)
1. check SIL504 1.8V ok?
2. check U2, U3 ok?
41
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(3) CPU (U10) trouble shooting guide :
Check +3Vs
(pin92)
YES
NO
Check X1
crystal
1. Check C75, C76
2. replace X1
YES
NO
check U18, make sure U18
pin1 has delayed for certain
period of time ,from L go H.
RESET
Successful?
YES
1. Check U9(SRAM), check CPU_LCS_N (pin 58) and
CPU_BHE_N is active?
2. Check U12(Flash), check R68 and CPU_UCS_N (pin
57) is active?
42
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3. DMD board trouble shooting guide.
NO
RESETZ And
POWERGOO
D?
1. No RESETZ check main board and
translation board.
2. No POWERGOOD check main board
YES
NO
NO
Color wheel
Spinning?
1. Check Color wheel and CW connector (J4)
2. CW power supply P12V of U13
YES
Color wheel
Feedback (J3
pin3) ok?
1. Check CW sensor board and CW tag
2. Feedback 150Hz
YES
1. Check J1 pin 1 (lampon) , normal status is
low
NO
Lamp light ok?
2. Check J1 pin 3(lamp light feedback) should
be low.
YES
Normal Image
on screen ?
(32-Gray Pattern
in Factory mode
is
DMD pixels always on
Check DMD socket.
Horizontal dark/bright lines
Check C-spring
Check DMD B/D : DAD1000(U1) VCC (5V), VBIAS
(23 ~ 26V), VRST (-26V)
recommended)
Vertical dark/bright lines
Color missing
Check C-spring
Check DMD socket.
43
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4. Connector board trouble shooting guide.
S-video is OK?
Check L14,L17
Check U5
No
Check U10
Composite is
OK?
Check L13
Check U5
Check U10
No
Component is
OK?
Check L15,L16,L18
Check U10
No
No
DVI- A is
OK?
Check L28,,L29,L31,L32,L33
Check U17
DVI-D (HDCP)is
OK?
Check U18ꢁDDC
No
Check U17
YPbPr is OK?
Check L2,L3,L4
Check U2
Check U7
Check L2,L3,L4,L5,L6
Check U2,U3,U4
BNC-PC is OK?
J6 12V output?
No
No
Check F1
Check Q2
Check L24
Check Q3
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Check R61,R62
Check U14
RS232 is OK?
No
Check main board
5. Power board trouble shooting guide.
Pow erB D C heck.
D isconnectthe w ire
Fuse B roken ?
N o
form buttom bd. to
pow er bd.
Y es
Proceed to "Prim ary
C ircuitC heck".
ShortPin12& Pin9.
C heck output
voltages.(1)+3.3V (2)
+12V (3)+5V (4)+5V -
Fix(5)+3.3V -Fix.
N o +3.3V O utput.
Proceed to "N o +3.3V -
Fix output".
C heck +3.3V -Fix exists ?
N o
Y es
C heck Q 702,Q 703,
and O n/O ff signal.
F704 B roken ?
N o
Q 704 w orks norm ally ?
N o
Y es
Y es
R eplace new fuse.
C heck trace.
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N
o
+ 1 2 V
O
u tp u t
P ro c e e d to " N
O
o
1 2 V
C
h e c k 1 2 V
e x is ts
?
N
N
N
o
o
o
u tp u t" .
Y
e s
Q
7 0 3 d a m a g e s a n d
re p la c e n e w
tra n s is to r.
C o rk s
n o rm a lly ? (V c e < 0 .2 V
h e c k
Q
7 0 3
w
)
Y
e s
Q
7 0 2 d a m a g e s a n d
re p la c e n e w
tra n s is to r.
C Q
n o rm a lly ? (V c e > 1 0 V
h e c k
7 0 2
w
o rk s
)
Y
e s
C
h e c k
la y o u t tra c e .
R
7 3 0 a n d
N
o
+ 5 V
o u tp u t.
P ro c e e d to " N
o
F ix o u tp u t" .
+ 5 V
-
C
h e c k + 5 V -F ix e x is t ?
N
N
N
o
o
o
Y
e s
Q
7 0 1 d a m a g e s
re p la c e n e w
tra n s is to r.
a n d
C
h e c k
Q
7 0 1
w
n o rm a lly ? (V c e < 0 2 V
o rk s
)
Y
e s
C
h e c k
Q
n o rm a lly
7 0 5
w
o rk s
R
e p la c e n e w
S F E T .
P -
?
M
O
Y
e s
C
h e c k th e tra c e o f
+ 5 V
.
46
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N o 1 2 V
o u tp u t
o r
N o + 5 V -F ix
o u tp u t
C h e c k D 7 0 1 h a d b e e n
in se rte d p ro p e rly ?
N o
Y e s
N o
S o ld e r it a g a in .
R e p la c e n e w IC 7 0 1 .
S o ld e r it a g a in .
Y e s
C h e c k IC 7 0 1 d a m a g e s ?
N o
C h e c k D 7 0 2 h a d b e e n
in se rte d p ro p e rly ?
Y e s
P ro c e e d to " C h e c k
p rim a ry c irc u it" .
N o + 3 .3 V -F ix
O u tp u t
C h e c k IC 7 0 5 , IC 6 0 2 ,
R 7 1 8 , R 7 4 2 , R 6 1 7 ,
R 6 1 6 .
P ro c e e d to " C h e c k
p rim a ry c irc u it" .
47
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C heck prim ary
circuit.
Proceed to "C heck
IC 601".
Fuse B roken ?
N o
Y es
C heck Q 601 dam ages ?
Y es
Proceed to "C heck
IC 601".
N o
C heck B D 651 dam ages ?
N o
Y es
PinD & PinS ofQ 601
are shorted. R eplace
new
R 612,Q 601,R 611,ZD
602,IC 601 and Fuse.
Inside diodes of
B D 601 are shorted.
R eplace new bridge
diode.
C heck IC 601.
O pen R 612 and inject
12V to Pin7 of
IC 601.
Is the PW M w aveform of
Pin6 of IC 601 is correct?
N o
R eplace IC 601.
Y es
R eplace ZD 601 and
IC 603.
48
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10. Factory OSD Operation
There are 10 pages in this OSD, the ways to enter factory OSD are open user OSD, then
press power on button. If you have to return user OSD, open factory OSD and press power
on button again.
Go to \User OSD\Environment\lamp hours\minutes, then press Right, Left, Right, Left,
Enter in a row to switch to factory OSD.
1. Factory
This page is mostly for our factory to use.
Page
Items
Return User OSD
Comment
Quit Factory OSD and return user OSD
Save current settings of factory OSD to EEPROM
Save Settings
Load Saved Settings
Load Factory Default
Load previous saved settings from EEPROM
Load factory default
Restore all settings of user
Load All User Default
OSD and PC/HD timing parameters
Burn-In mode On/Off
Burn In Mode
Factory
Burn In Timer Setup hours
Set burn-in hours
Burn In Timer Running hours &
minutes
Running hours of burn-in mode
Set baudrate of RS2329600 or 115200
RS232 Baudrate
OSD Timer
OSD automatic off time
Usage Hour
Record total usage hours of this projector
Software version
Software version
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2. HD Adj
This page is the settings of A/D converter. There are 2 sections, one is for RGBHV format
signal (DVI-A input and RGB-HD input), the other is for YPbPr format signal
(Comp-HD input).
Page
Items
Comment
Range
0~127
0~127
0~127
0~255
0~255
0~255
Red Offset A/D converter red offset
Green Offset A/D converter green offset
Blue Offset A/D converter blue offset
RGBHV format
Red Gain
A/D converter red gain
Green Gain A/D converter green gain
Blue Gain A/D converter blue gain
Page
Items
Comment
Range
0~127
0~255
0~255
0~127
0~127
Brightness A/D converter green offset
Contrast A/D converter green gain
YPbPr format Saturation A/D converter red and blue gain
Pb-Offset A/D converter blue offset
Pr-Offset A/D converter red offset
3. STD Adj
This page is the settings of video decoder. There are 2 sections, one is for Video and
S-Video input, the other is for component input.
Page
Items
Brightness V/D brightness
Contrast V/D contrast
Saturation V/D saturation
Hue V/D hue
Comment
Range
0~255
-128~127
-128~127
-128~127
Video & S-Video
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Page
Items
Brightness V/D brightness
Contrast V/D contrast
Saturation V/D saturation
Comment
Range
0~255
Component
-128~127
-128~127
4. Color Balance
For color temperature settings, they are the combination of gamma gain and gamma
offset. This page allows operator to adjust gamma correction to fit the expected color
temperature, and save these settings as one of the color temperature settings. And this
page also provides the function to restore color temperature setting to default gamma
combination.
Page
Items
Red
Comment
Range
0~128
Adjust the shape of RM-1A gamma curve
Gamma
Green
Blue
Adjust the shape of RM-1A gamma curve
Adjust the shape of RM-1A gamma curve
0~128
0~128
Page
Items
Red
Comment
Range
1~512
Multiply gamma curve by a gain
(gain= settings/512)
Multiply gamma curve by a gain
(gain= settings/512)
Green
Blue
1~512
1~512
Gamma Gain
Multiply gamma curve by a gain
(gain= settings/512)
Page
Items
Red
Comment
Range
0~90
Add an offset value to gamma curve
Gamma
Offset
Green
Blue
Add an offset value to gamma curve
Add an offset value to gamma curve
0~90
0~90
51
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Page
Items
Comment
Save gamma gain and gamm offset
as color temp 9300K
For data input (Component >= 480p
signal, DVI-A, and DVI-D)
Save gamma gain and gamm offset
as color temp 6500K
For data input (Component >= 480p
signal, DVI-A, and DVI-D)
Save Data Temp.
Save gamma gain and gamm offset
as color temp 5700K
For data input (Component >= 480p
signal, DVI-A, and DVI-D)
Restore default value of gamma
correction
Restore combination
Page
Items
Comment
Save gamma gain and gamm offset as
color temp 9300K
For video input (Component < 480p
signal, Video, and S-Video)
Save gamma gain and gamm offset as
color temp 6500K
For video input (Component < 480p
signal, Video, and S-Video)
For video input (Component < 480p
signal, Video, and S-Video)
Restore default value of gamma
correction
Save Video Temp.
Save gamma gain and gamm offset as
color temp 5700K
Restore combination
5. Filter Bypass
Page
Items
V-in
Comment
On/Off status of RM-1A's video input filter
Filter Bypass
V-out
G-in
On/Off status of RM-1A's video output filter
On/Off status of RM-1A's graphics input filter
52
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6. DLP
This page allows user to change DLP settings.
Page
DLP
Items
Brightness
Contrast
CW delay
Degamma
Table
Comment
DLP brightness
Range
-64~64
0~100
DLP contrast
DLP color wheel delay
0~1023
DLP degamma table
0~6
7.Pattern1
This page allows user to call up DLP present curtains and RM-1A patterns.
Page
Items
Red Curtain
Green Curtain
Blue Curtain
Black Curtain
Color Bar
Comment
DLP present curtain. For CW delay measurement
DLP present curtain. For CW delay measurement
DLP present curtain. For CW delay measurement
DLP present curtain. For optical experiment.
RM-1A pattern. For checking gray scale.
Patterns 1
Checker Board
13-Points
RM-1A pattern. For optical contrast measurement.
RM-1A pattern. For optical experiment.
Reflective Edge
RM-1A pattern. For optical light leakage experiment
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8.Pattern2
This page allows user to call up DLP DDP1010 series present patterns.
Page
Items
Comment
Solid Field - Yellow
DLP DDP1010 present pattern. For checking color.
Solid Field - Cyan
DLP DDP1010 present pattern. For checking color.
Solid Field - Magenta
DLP DDP1010 present pattern. For checking color.
DLP DDP1010 present pattern. Monochrome pattern,
for checking gray scale.
Horizontal Ramp
Vertical Ramp
DLP DDP1010 present pattern. Monochrome pattern,
for checking gray scale.
Patterns 2
Horizontal Lines
Diagonal Lines
Vertical Lines
Grid
DLP DDP1010 present pattern. Monochrome pattern.
DLP DDP1010 present pattern. Monochrome pattern.
DLP DDP1010 present pattern. Monochrome pattern.
DLP DDP1010 present pattern. Monochrome pattern.
DLP DDP1010 present pattern. Monochrome pattern.
Checker Board
9.Pattern3
This page allows user to call up DLP DDP1010 series present patterns, the major goal
of this page is for DMD inspection.
Page
Items
Comment
DLP DDP1010 present pattern. For inspection of 'major dark blemish' and
'dark pixel' on DMD chip.
Patterns 3
Blue 90
DLP DDP1010 present pattern. For inspection of 'border defects' on DMD
chip.
Gray 10
Gray 6
DLP DDP1010 present pattern. For inspection of 'major light blemish' and
light pixel' on DMD chip.
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DLP DDP1010 present pattern. For inspection of 'minor blemishes' on
White Full
Black Full
Red Ramp
DMD chip.
DLP DDP1010 present pattern. For inspection of 'minor blemishes' on
DMD chip.
DLP DDP1010 present pattern. For inspection of 'unstable pixel' on DMD
chip.
10 . Test Mode
For different situation, we need different settings. Here we define 5 kinds of settings in
‘Picture Adjust’ page to fit some situations.
Page
Items
Optical Test
Comment
High brightness, high contrast, high saturation
All settings in the middle value
Middle Value
Play DVD
Test Mode
Optimal settings for watching DVD
Color Wheel Delay Low brightness, high contrast, high saturation
Blue Filter Only 'blue' is left, for 'color' and 'tint' adjustment
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11. Firmware Upgrade Procedure
1. Connect specific download cable to RS232 (RJ-11) connector. Remember to turn the
AC switch off.
2. Execute the ‘Flash Loader’ program. If the ‘COM Settings’ item is ready, you can see
‘Identifying target…’ at the bottom of flash loader. If not, open ‘COM Settings’ item.
Choose the ‘COM Port’ you use, always set the baud rate 115200, then press ‘Connect’
and ‘OK’ button. The program returns to its main page, and ‘Connected’ and ‘Identifying
target’ are supposed to be displayed at the bottom of the flash loader.
56
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3. Turn the AC switch on. In 3 seconds, ‘flash loader’ will identify the flash ROM of this
unit. Choose ‘Hex File Format’ as ‘Intel Extended’, ‘Operation’ as ‘Program’, and
‘Browse’ the ‘File Name’. After that, press the ‘Start’ button. ‘Flash Loader’ starts to
load program to Flash ROM.
4. After download procedure finished, remove download cable and turn the AC switch off.
Then the user can operate this machine in normal condition.
5. The hex file to be loaded, the format of its name is
BenQ_PE8700_RM1A_Ver102_20030619.hex
I.
II.
III.
IV.
V.
I.
Brand name
Model name
Scaler type
II.
III.
IV.
V.
Version of SW
Released date
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12. RS232 Codes
1. Set up peripherals
BenQ PE8700 provides an RJ-11 connector for RS232 serial communication control. The
user can use the ‘Hyper Terminal’ program of Microsoft Windows to control this unit.
To set the settings of serial port first is necessary. Choose which COM port you want
to connect, and set its settings as below:
Baud Rate:
Parity:
115200 or 9600
None
Data bits:
Stop bits:
Flow Control:
8
1
None
For baud rate setting, it depends on the settings in our \Factory OSD\FACTORY\RS232
BAUDRATE\ 9600 or 115200.
58
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After settling down, connect our specific RS232 cable and press the ‘call’ icon of ‘Hyper
Terminal’ program. After this, press ‘Enter’ key, if an ‘>’ symbol come up, that means the unit
is ready to accept commands for computer.
2. Commands list
There are 3 kinds of serial commands, X-group, Y-group and Z-group.
For X-group, these functions are public. Any end-user can control the unit by these
commands, as long as they set correct RS232 communication. Following table is the codes
list of X-group command.
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Code
X00
X01
X02
X03
X04
X05
X06
X07
X08
Function
Must be Reversed , no function
Power On
Power Off
Message On
Message Off
Lamp hours reset
Load all user OSD default value
Save current active source settings
Change active OSD
X10
X11
X12
X13
X14
X15
X16
Menu
Enter
Exit
Up(arrow key)
Down(arrow key)
Left(arrow key)
Right(arrow key)
X20
X21
X22
X23
X24
X25
X26
X27
Switch to Composite input
Switch to S-Video input
Switch to Component input
Switch to Dsub_PC input
Switch to YPbPr input
Switch to BNC_PC input
Switch to DVI input
Switch to DVI_I input
X30
X31
4:3 screen
16:9 screen
X35
Aspect - Anamorphic
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X36
X37
X38
X39
Aspect - Standard (4:3)
Aspect - Letter box
Aspect - Virtual wide
Aspect - Through
X40
X41
X42
X43
X44
X45
X46
X47
X48
X49
Load memory 1 settings
Load memory 2 settings
Load memory 3 settings
Load 'optical test' mode settings
Load 'middle' mode settings
Load 'CW delay adjustment' mode settings
Load default of current source
Save memory 1 settings
Save memory 2 settings
Save memory 3 settings
X50
X51
Scale up
Scale down
X55
X56
X57
Switch active source
Picture in picture display
Picture by picture display
X60
X61
X62
X63
X64
X65
X66
X67
Switch language 1
Switch language 2
Switch language 3
Switch language 4
Switch language 5
Switch language 6
Switch language 7
Switch language 8
X85
PC input - auto
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X90
X91
X92
X93
X94
X95
Image orientation - floor front
Image orientation - ceiling front
Image orientation - floor rear
Image orientation - ceiling rear
Back light board On
Back light Board Off
X99
On line help
When an user sends a command, he must follow the command format in the list. After
he sends a command, program will acknowledge 2 pieces of information. This information,
we call it ‘ACK’ in the following content.
The format of first ACK is XnX
The length is 3, first and last characters are always be X. And the number ‘n’ is 0, 1 or
2. The explanation of n is
0: Right command format and function
1: Illegal format
2: Illegal function
So, if the user presses XA85, this one is wrong format, ACK will be X1X.
And if the user presses X98, because this function is not included in our command
table, ACK will be X2X.
For above situation, program sends the user an ACK, then waiting for a new
command.
If the user presses correct command, take an example, X35, first ACK, X0X will send
to the user. That tells the user it’s a right command. Then program starts to deal with this
command, and changes the aspect ratio to ‘anamorphic’ mode. When finish, the user will
receive 2nd ACK. The format is Xn_ccX
The length is 6. First and last characters are X, second character is the ACK, followed
by a ‘_’ character. ‘cc’ is the function number. So, in this case, the 2nd ACK is X0_35X. And
the user can continue to send next command.
For Y-group, this one is for our factory, not public. When our operators send
commands to the unit, the ACK format is identical as X-group, difference is only ‘Y’ instead
of ‘X’.
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Following is the list of Y-group:
Code
Function
Save current factory settings
Load saved factory settings
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Load factory default
Load all user default
Burn-In mode on
Burn-In mode off
Set RS232 baudrate as 9600
Set RS232 baudrate as 115200
Y10
Y11
Y12
Save as data color temperature 1
Save as data color temperature 2
Save as data color temperature 3
Y20
Y21
Y22
Save as video color temperature 1
Save as video color temperature 2
Save as video color temperature 3
Y30
Y31
Y32
Restore data color temperature to default
Restore video color temperature to default
Restore white balance settings to default
Y40
Y41
Y42
Y43
Y44
DMD -- Degamma table 0
DMD -- Degamma table 1
DMD -- Degamma table 2
DMD -- Degamma table 3
DMD -- Degamma table 4
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Y52
Y53
Y54
Y55
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Red Curtain
Green Curtain
Blue Curtain
Black Curtain
Color Bar
Chess Board
Optical 13-point
Reflective Edge
Grid
Blue 90 Curtain
Gray 10 Curtain
Gray 6 Curtain
Full White Curtain
Full Black Curtain
Red Ramp Curtain
Gray 20 Curtain
Y70
Y71
Y72
Y73
Y74
Load 'optical test' mode settings
Load 'middle value' mode settings
Load 'Play DVD' mode settings
Load 'CW delay adjustment' mode settings
Load 'Blue filter' mode for color and tint adjustment
Y80
Y81
Load default for factory auto alignment procedure
Save corresponding settings after auto alignment
Y98
Y99
Display version
On line help
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Example:
1. Command = Y89893 (Enter)
ACK = Y1Y (Illegal format, wrong length)
2. Command = Y98 (Enter)
ACK = Y2Y (Illegal function)
3. Command = Y52 (Enter)
1st ACK = Y0Y
2nd ACK = Y0_52Y
For Z-group, this one is for ‘auto-alignment’ procedure in our factory. This one allows
engineers to read or write the unit settings without OSD operation, it will save time to set
the value. Following is the table of Z-group.
Code
Z001
Z002
Z003
Z004
Z005
Z006
Z007
Z008
Z009
Z010
Z011
Z012
Function
Brightness adjustment
Contrast adjustment
Color adjustment
Sharpness adjustment
Tint adjustment
Color temperature adjustment
Filters adjustment
Independent color control - Red adjustment
Independent color control - Green adjustment
Independent color control - Blue adjustment
Independent color control - Yellow adjustment
DMD white peaking adjustment
Z020
Z021
Z022
Z023
Frequency adjustment
Phase adjustment
H - Position adjustment
V - Position adjustment
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Z030
Keystone adjustment
Z034
Z035
Z036
Z037
Z038
Z039
RGBHV input -- Red offset
RGBHV input -- Green offset
RGBHV input -- Blue offset
RGBHV input -- Red gain
RGBHV input -- Green gain
RGBHV input -- Blue gain
Z042
Z043
Z044
Z045
Z046
YPbPr input -- Brightness
YPbPr input -- Contrast
YPbPr input -- Saturation
YPbPr input -- Pb Offset
YPbPr input -- Pr Offset
Z050
Z051
Z052
Z053
Z054
Z055
Z056
CVBS & S-Video -- Brightness
CVBS & S-Video -- Contrast
CVBS & S-Video -- Saturation
CVBS & S-Video -- Hue
Component -- Brightness
Component -- Contrast
Component -- Saturation
Z060
Z061
Z062
Z063
Z064
Z065
Z066
Z067
Z068
Gamma--Index
Gamma--Red
Gamma--Green
Gamma--Blue
Gamma gain -- Red
Gamma gain -- Green
Gamma gain -- Blue
Gamma offset -- Red
Gamma offset -- Green
66
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Z069
Gamma offset -- Blue
Z070
Z071
Z072
Z073
DMD -- Brightness
DMD -- Contrast
DMD -- Color Wheel Delay
DMD -- Degamma table
Z080
Z099
Burn-in hours
On line help
The length of the command must be 11. The format, take an example, to read DMD
color wheel delay:
Z072RxxxxxZ, where
Byte 1: must be 'Z' or 'z'
Byte 2~4: function code
Byte 5: action, must be ‘r’ or ‘R’
Byte 6~10: Don’t care
Byte 11: must be 'Z' or 'z'
In contrast, if write DMD color wheel delay:
Z072W+0025Z, where
Byte 1: must be 'Z' or 'z'
Byte 2~4: function code
Byte 5: action, must be ‘w’ or ‘W’
Byte 6: sign byte, must be ‘-‘ or ‘+’
Byte 7~10: the value to be written
Byte 11: must be 'Z' or 'z'
67
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And the length of ACK must be 12, and format is
Z0_072+0025Z
Byte 1: Always ‘Z’
Byte 2: ACK
Byte 3: Always ‘_’
Byte 4~6: function code
Byte 7: sign byte, ‘+’ or ‘-‘
Byte 8~11: the current value after writing
Byte 12: Always ‘Z’
And ‘ACK’ value is
0: Right command and function
1: Illegal Format
2: Illegal Function
3: Illegal Action,
4: Illegal Adjusted Situation,
5. Written value is over up limit,
6. Written value is over down limit
If the ACK is 0, 5, 6, program will deal this command. If ACK = 5, program writes the legal
maximum value to the setting. If ACK = 6, writes the legal minimum value to the setting.
68
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5
4
3
2
1
TP2
TP4
TP1
TP3
E1 E1 E1 E1
RM1
120-Pin B2B Connectors
D_INA[0..23]
D_VSYNC
D_HSYNC
DIN_CLK
80 Pin Connector to DLP
OP_A[0..23]
D_INA[0..23]
D_VSYNC
D_HSYNC
DIN_CLK
D_INA[0..23]
D
C
B
A
D
C
B
A
OP_A[0..23]
D_VSYNC
D_HSYNC
DIN_CLK
OP_A[0..23]
DMD_SCL
DMD_SDA
DMD_SCL
DMD_SDA
OP_VSYNC
OP_HSYNC
OP_ENABLE
OCLK_OUT
OP_VSYNC
OP_HSYNC
OP_ENABLE
OCLK_OUT
OP_VSYNC
OP_HSYNC
OP_ENABLE
OCLK_OUT
TP5
E1
DVI_SCDT
DVI_SCDT
OP_FIELD
OP_FIELD
OP_FIELD
MEM_DQ[0..79]
MEM_A[0..11]
MEM_RAS_N
MEM_CAS_N
MEM_BS
MEM_DQ[0..79]
MEM_A[0..11]
MEM_RAS_N
MEM_CAS_N
MEM_BS
MEM_DQ[0..79]
MEM_A[0..11]
MEM_RAS_N
MEM_CAS_N
MEM_BS
DLP
POWER
LAMPLIT
POWER
LAMPLIT
Connector/POWER
MEM_CLK
MEM_CLK
MEM_CLK
MEM_WE_N
MEM_CS_N
MEM_DQM_L
MEM_DQM_U
MEM_WE_N
MEM_CS_N
MEM_DQM_L
MEM_DQM_U
MEM_WE_N
MEM_CS_N
MEM_DQM_L
MEM_DQM_U
+3VA +5VA +12VA +3VS +5VS
+5VS
+3VS
+12VA
+5VA
+3VA
+3VA
+3VA
7_100 Pin Connector to DLP/POWE
8_SDRAM 64MBit
SDRAM 64MBit
x
3
3
TP6
E1
x
Sil503_Deinterlacer
DI_IN[2..9]
DI_IN[2..9]
DI_27M_CLK
DI_VSYNC
DI_HSYNC
DI_IN[2..9]
DI_27M_CLK
DI_VSYNC
DI_27M_CLK
DI_VSYNC
DI_HSYNC
I/O
CPU_A1
CPU_A2
CPU_A3
CPU_A4
KEYPAD&THERMAL_CONNECTOR
CPU_A1
CPU_A2
CPU_A3
CPU_A4
DLP_RESETZ
POWERON
DI_HSYNC
IR
POWERON
IR
V_IN[0..15]
V_ACTIVE
V_VSYNC
V_HSYNC
V_CLK
MCURESET
TRIGGER
RESET_DVDO
DEINTDONE
V_IN[0..15]
V_ACTIVE
V_VSYNC
V_HSYNC
VCLK
V_IN[0..15]
V_ACTIVE
V_VSYNC
V_HSYNC
VCLK
MCURESET
TRIGGER
KEYPAD[0..9]
KEYPAD[0..9]
KEYPAD[0..9]
SII141_PDO
MUX_SEL
LAMP_PROTECT
SII141_PDO
MUX_SEL
DVI_SCDT
LAMP_PROTECT
LAMP_PROTECT
DVI_SCDT
SCL
SDA
SCL
SDA
RM1_RST_N
RM1_RST_N
RM1_RST_N
BACKLIGHT_CTRL
BACKLIGHT_CTRL
+3VA +1_8V
E1
TP11
+3VS +5VS +12VA
+3VS
DI_SDA
DI_SCL
+1_8V
+3VS
+3VA
+3VS
2_Sil504_Deinterlacer
+5VS
CPU_RD_N
CPU_D[0..7]
CPU_RD_N
CPU_D[0..7]
MCU503 Controller
+12VA
10_KEYPAD&THERMAL_CONNECTOR
6_I/O
DI_SCL
DI_SDA
TP16
E1
TP13
DEINTDONE
TP7
E1
MCURESET
E1
RESET_DVDO
MCURESET
CPU_FLASH_SRAM
DMD_SDA
DMD_SCL
DMD_SDA
DMD_SCL
SII141_PDO
TRIGGER
SII141_PDO
TRIGGER
CPU_RD_N
CPU_D[0..7]
CPU_A[0..7]
CPU_RD_N
CPU_D[0..7]
CPU_A[0..7]
RM1_WR_N
RM1CLKIN
RM1_CS_N
RM1_IRQ
CPU_RD_N
CPU_D[0..7]
CPU_A[0..7]
RM1_WR_N
RM1CLKIN
RM1_CS_N
RM1_IRQ
RM1_RST_N
MUX_SEL
RM1_RST_N
MUX_SEL
+1_8V
+3VA
+3VA
+5VA
RM1_WR_N
RM1CLKIN
RM1_CS_N
RM1_IRQ
LAMPLIT
LAMPLIT
SCL
SDA
SCL
SDA
SPAREI
TP20 TP19
E1 E1
TP18 TP17
E1 E1
SPAREI
SPAREO
POWER
SPAREO
+5VA
+3VA
+1_8V
POWER
+3VA
3_MCU503 Controller
4_RM1
DMD_SCL
DMD_SDA
SCL
SDA
SCL
SDA
SCL
SDA
+5VS +1_8V +12VA +5VA +3VA
CPU
CPU_RXD0
CPU_TXD0
CPU_RXD0
CPU_TXD0
MUX_SEL_P
MUX_BUFFER
DVI_ACTDATA
CPU_RXD0
CPU_TXD0
MUX_SEL_P
MUX_BUFFER
+3VA
+5VA
+12VA
+1_8V
+5VS
MUX_SEL_P
MUX_BUFFER
+12VA
+5VS
+3VS
DVI_ACTDATA
+5VA
+3VA
BACKLIGHT_CTRL
MUX_SEL_Q
IR
BACKLIGHT_CTRL
MUX_SEL_Q
IR
+12VA
+5VA
+5VS
+3VA
+3VS
MUX_SEL_Q
IR
1_120Pin B2B Connectors
5_CPU_FLASH_SRAM
TP8 TP9 TP15
E1 E1 E1
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
1
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
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5
4
3
2
5
4
3
2
1
D
C
B
A
+5VS
+5VS
C1
0.1UF
+12VA
J5
J1
SDA
SCL
1
2
3
4
5
6
7
8
9
+12VA
SDA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
KEY_LED0
KEY_LED1
KEY_LED2
IR
FAN_CTRL
DLP_RST
POWERON
DLP_RESETZ
LAMP_PROTECT
BACK_LIGHT_CTRL
10
11
12
10
11
12
KEYPAD0
KEYPAD1
KEYPAD2
KEYPAD3
KEYPAD4
KEYPAD5
KEYPAD6
KEYPAD7
KEYPAD8
KEYPAD9
+3VS
CON_12P
+3VS
KEYPAD[0..9]
CON20
THERMAL CONNECTOR
KEYPAD CONNECTOR
+3VS
Benq Corporation
U8D
74HC132
Project Code
Model Name
OEM/ODM Model Name
NA
12
13
HT720G
99.J5877.001
BACKLIGHT_CTRL
BACK_LIGHT_CTRL
11
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
of
10
2
Approved By
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COLIN CHANG
BEN CHEN
ANGEL HU
5
4
3
2
1
D
C
B
A
D
C
B
A
DI_IN[2..9]
Screw Holes
D_INA[0..23]
RED -- D_INA[23..16]
GREEN -- D_INA[15..8]
BLUE -- D_INA[7..0]
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
J2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
1
2
3
4
5
6
7
8
DVI_SCDT
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
1
2
3
4
5
6
7
8
9
TRIGGER
MUX_SEL_P
CPU_RXD0
CPU_TXD0
MUX_BUFFER
D_HSYNC
3
3
3
3
2
2
2
2
IR
H1
H2
H3
H4
+5VS
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
9
MUX_SEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
+5VS
D_VSYNC
DIN_CLK
D_INA23
D_INA22
D_INA21
D_INA20
D_INA19
D_INA18
D_INA17
D_INA16
D_INA15
D_INA14
D_INA13
D_INA12
D_INA11
D_INA10
D_INA9
D_INA8
D_INA7
D_INA6
D_INA5
D_INA4
D_INA3
D_INA2
D_INA1
D_INA0
SII141_PDO
93
94
95
96
97
98
99
94
95
96
97
98
99
SPARE for DVI interface
DVI_ACTDATA
SCL
SDA
DI_IN8
DI_IN9
DI_IN6
DI_IN4
DI_IN2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DI_IN7
DI_IN5
DI_IN3
RM1_RST_N
DI_HSYNC
DI_27M_CLK
SPAREO
DI_VSYNC
SPAREI
Optical Points
MUX_SEL_Q
OP1
OP
OP2
OP
OP3
OP
OP4
OP
OP5
OP
OP6
OP
OP7
OP
+12VA
+12VA
+5VA
OP8
OP
OP9
OP
OP10
OP
OP11
OP
OP12
OP
OP13
OP
OP14
OP
+5VA
C2
0.1UF
AMP 120P D0.8
C3
10UF/16
C4
0.1UF
+
OP15
OP
OP16
OP
OP17
OP
OP18
OP
U1
L1
1
+3VA
+1_8V
LM8117A-1.8(SOT223)
+1.8VOUT
C5
3
2
1
2
+1_8V
+3VA
VIN
VOUT
2
FCB3216K
+
C6
0.1UF
22UF/16
C7
0.1UF
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
3
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
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5
4
3
2
5
4
3
2
1
V_IN[0..15]
V_IN[0..15]
DI_VSYNC
DI_HSYNC
DI_VSYNC
DI_HSYNC
TP21
E1
DEINTDONE
DEINTDONE
TP22
R1
10K
D
C
B
A
D
C
B
A
TP23
E1
INTERLACE_DETECT
2:2_DETECT
3:2_DETECT
1
TP24
E1
1
VDD_PLL
1
VDD_CORE
E1
RESET_DVDO
RESET_DVDO
+3VA
TP27
E1
TP25
E1
TP26
E1
1
2
3
4
5
6
7
8
9
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
NC
HOSTADDR5
VDDCORE_1.8
GND
LCDPWREN
/CBLANK
/CSYNC
/VSYNC
/HSYNC
BLUE_CB0
BLUE_CB1
BLUE_CB2
BLUE_CB3
BLUE_CB4
BLUE_CB5
GND
HOSTADDR4
HOSTADDR3
HOSTADDR2
HOSTADDR1
HOSTADDR0
GND
TP28
Note: The Sil 503 does not support a standard
I2C protocol. See data sheet page 22.
R2
R3
R4
33 E1 503CBLANK
V_ACTIVE
V_CSYNC
503VSYNC
503HSYNC
1
33
33
V_VSYNC
V_HSYNC
/HOSTCS
DI_SDA
DI_SCL
DI_SDA
DI_SCL
/HOSTRD_SDA
/HOSTWR_SCL
VDDCORE_1.8
VIDLNCLK
GND
VIDLNDATA9
VIDLNDATA8
VIDLNDATA7
VIDLNDATA6
VIDLNDATA5
VIDLNDATA4
VIDLNDATA3
VIDLNDATA2
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V_IN0
V_IN1
V_IN2
V_IN3
CB0
CB1
CB2
CB3
2
4
6
8
1
3
5
7
DI_27M_CLK
DI_27M_CLK
DI_IN[2..9]
Input Port
DI_IN[2..9]
DI_IN9
DI_IN8
DI_IN7
DI_IN6
DI_IN5
DI_IN4
DI_IN3
DI_IN2
RP1
47_RP
VDD
V_IN4
V_IN5
V_IN6
V_IN7
CB4
CB5
CB6
CB7
2
4
6
8
1
3
5
7
BLUE_CB6
BLUE_CB7
BLUE_CB8
BLUE_CB9
GND
GREEN_Y0
GREEN_Y1
GREEN_Y2
GREEN_Y3
VDD
GREEN_Y4
GREEN_Y5
GREEN_Y6
GREEN_Y7
GREEN_Y8
GREEN_Y9
GND
RED_CR0
RED_CR1
RED_CR2
RED_CR3
RED_CR4
RED_CR5
GND
U2
SII504
RP2
47_RP
RSVD
RSVD
VDD
GND
V_IN8
V_IN9
V_IN10
V_IN11
GREEN_Y2
GREEN_Y3
DI_RSVD1
R5
10K
2
4
6
8
RP3
1
3
5
7
GREEN_Y4
GREEN_Y5
GREEN_Y6
GREEN_Y7
GREEN_Y8
GREEN_Y9
DQ16
DQ17
MEMDATA16
MEMDATA17
MEMDATA18
MEMDATA19
GND
MEMDATA20
MEMDATA21
MEMDATA22
MENDATA23
GND
47_RP
V_IN12
V_IN13
V_IN14
V_IN15
DQ18
DQ19
2
4
6
8
1
3
5
7
DQ20
DQ21
DQ22
DQ23
RP4 47_RP
DQ31
MEMDATA31
MEMDATA30
GND
DQ30
VDD
DQ29
DQ28
VDDCORE_1.8
RED_CR6
RED_CR7
RED_CR8
RED_CR9
VIDOUTCLK
GND
MEMDATA29
MEMDATA28
GND
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA15
/BYPPLLMEMCLK
GND
TP29
E1
DQ27
DQ25
DQ26
DQ24
DQ15
VCLK
R6
33
VIDOUTCLK
VCLK
/BYPPLLCLK48M
CLK48M
GND
VDDCORE_1.8
ExtRefSel_N
VDDCORE_1.8
NC
Note: For compatability with Sil504
place bypass resistors
R99
NC_R0603
M_CLK
DQ[0..31]
+3VA
+3V_MEM
DQ15
DQ14
DQ13
DQ12
DQ11
R98
4.7K
U3
1
2
3
4
5
6
7
8
9
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VDD
VSS
L2
DQ0
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VDD_PLL
VDD_CORE Z1000/100MHZ
PLL Power
DQ1
DQ2
DQ14
DQ13
DQ3
DQ4
DQ12
DQ11
+
C8
0.1UF
C9
10UF/16
C10
0.1UF
AVSSI
DQ5
DQ6
DQ10
DQ9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ[0..31]
DQ7
DQ8
+3VA
VSS
Note: Connect RP4, RP5 and R256 to bypass Sil503
DQM
DQM
+3VA
DQM1
NC
WEN
CASN
RASN
V_IN8
V_IN9
DI_IN2
DI_IN3
DI_IN4
DI_IN5
DI_IN6
DI_IN7
DI_IN8
DI_IN9
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
RP5
NC_RP
NC
CLK
CKE
A9
A8
A7
A6
A5
M_CLK
V_IN10
V_IN11
V_IN12
V_IN13
V_IN14
V_IN15
+
C11
10UF/16
C12
0.1UF
C13
0.1UF
C14
0.1UF
C15
0.1UF
C16
0.1UF
A9
A8
A7
A6
A5
A4
A3
A11
A12
A10
A0
A1
A2
RP6
NC_RP
VCLK
R7
NC_R0603 DI_27M_CLK
A4
A3
VDD_CORE
DQM3
VSS
NC
A[0..11]
A[0..11]
DQ16
DQ31
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
C17
0.1UF
C18
0.1UF
C19
0.1UF
C20
0.1UF
C21
0.1UF
C22
0.1UF
DQ17
DQ18
DQ30
DQ29
DQ19
DQ20
DQ28
DQ27
L5
Z1000/100MHZ
+1_8V
L3
Z1000/100MHZ
+3V_MEM
DQ21
DQ22
DQ26
DQ25
+3VA
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
DQ23
DQ24
+
C23
C24
C25
0.1UF
C26
0.1UF
C27
0.1UF
C28
0.1UF
C29
C34
0.1UF
C35
10UF/16
C36
0.1UF
C37
C38
0.1UF
C39
0.1UF
4.7UF/16 0.1UF
0.1UF
0.1UF
+1_8V
Title
K4S643232C-TC/L10
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
4
Approved By
Download from Www.Somanuals.com. All Manuals Search And Download.
COLIN CHANG
BEN CHEN
ANGEL HU
5
4
3
2
1
D
C
B
A
D
C
B
A
RESET_DVDO
R120
R121
0
0
(open)
(open)
DMD_SDA
DMD_SCL
+3VA
3
D
+3VA
1
G
2
S
Q1
+5VA
2
3
MCURESET
+5VA
BSN20
BSN20
Q2
+5VA
2
3
SDA
SCL
BSN20
Q3
R8
470
R9
RP7
+5VA
470
2
3
4.7K_RP
BSN20
C40
0.1UF
R10
2.2K
R11
2.2K
U4
D1
LED_1206
D2
LED_1206
RESET_DVDO
1
20
DVRESET
VDD
DEINTDONE
SDA_5V
SCL_5V
DI_SDA
DI_SCL
15
14
2
3
DI_SDA
DI_SCL
SDA
SCL
DVSDA
DVSCL
+5VA
DEINTDONE
LED0
LED1
21
23
24
VSYNC
PRMODE0
PRMODE1
MCEN
MCADDRSEL
FILM
SUBT
GAME
EXTGAME
CLKSPEED
2
4
6
8
RP8
2
4
6
8
RP9
1
3
5
7
6
7
5
ENABLE
SA
22
27
GPIO0
GPIO1
LED2
LED3
ON
SOURCE
3:2
FILMBIAS
SUBTITLE
GMODE
EXTGMD
MCKSEL
SQMODE
YPRPB
4
4.7K_RP
11
12
13
25
26
28
ON
1
3
5
18
17
RX
TX
ON
OFF
ON
2:2
YPBPR
7
16
OFF
OFF
VID
RSVD0
4.7K_RP
WAVE
OFF
GAME
PICXIN
PICXOUT
9
10
19
8
OSC1
OSC2
Vss
Vss
R13
10M
MCU503
X1
3
20MHZ
1
C41
22PF
C42
22PF
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
o f
10
5
Reviewed By
COLIN CHANG
1
Approved By
Download from Www.Somanuals.com. All Manuals Search And Download.
BEN CHEN
ANGEL HU
5
4
3
2
5
4
3
2
1
MEM_DQ[0..79]
MEM_DQ[0..79]
RED -- D_INA[23..16]
GREEN -- D_INA[15..8]
BLUE -- D_INA[7..0]
D
C
B
A
D
C
B
A
Place the resistors as close to the RM1
pins as possible.
D_INA[0..23]
D_INA[0..23]
CPU_D[0..7]
CPU_D[0..7]
+3VA
+3VA
LEFT EDGE
U5A
BOTTOM EDGE
RIGHT EDGE
U5C
+3VA
+1_8V
+3VA
+1_8V
+1_8V
TOP EDGE
U5B
VDP01
VDP01
VDP01
+3VA
U5D
+1_8V
VDP01
R14
120
A1
B1
B2
AF1
AF2
AE2
AF3
AE3
AD3
AF4
AE4
AD4
AC4
AF5
AE5
AD5
AC5
AF6
AE6
AD6
AC6
AF7
AE7
AD7
AC7
AF8
AE8
AD8
AC8
AF9
AE9
AD9
B26
C25
C26
D24
D25
D26
E23
E24
E25
E26
F23
GND
D_INA12
GND
D_INA14
D_INA13
GND
D_INA17
D_INA15
D_INA16
GND
GND
DB1
GND
DB3
DB2
GND
DB6
DB4
GND
D_INA12
CPU_D0
CPU_D1
MEM_DQ22
MEM_DQ24
MEM_DQ23
A2
A3
B3
A4
B4
C4
A5
B5
C5
D5
A6
MEM_DQ22
MEM_DQ24
MEM_DQ23
VDD33
MEM_DQ20
GND
GND
D_INA11
D_INA9
D_INA7
D_INA5
D_INA10
D_INA3
D_INA2
D_INA8
D_INA6
D_INA0
DINA_OVERFLOW2
D_INA4
VDD33
DINA_OVERFLOW0
D_FIELD
D_INA1
GND
D_INA11
D_INA9
D_INA7
D_INA5
D_INA10
D_INA3
D_INA2
D_INA8
D_INA6
D_INA0
D_INA14
D_INA13
D_INA22
D_INA17
D_INA15
D_INA16
D_INA23
D_INA21
D_INA18
D_INA20
D_INA19
CPU_D3
CPU_D2
C1
C2
C3
D1
D2
D3
D4
E1
E2
E3
E4
F1
TP30 TP31
E1 E1
R15
180
MEM_DQ20
MEM_DQ21
CPU_D6
CPU_D4
CPU_D5
CPU_D7
MEM_DQ21
VDD18
DB5
GND
GND
33
R16
RM1_OP_ENABLE
OP_ENABLE
D_INA21
D_INA18
D_INA20
D_INA19
D_INB1
D_INA22
D_INB0
VDD50
D_INB3
D_INB2
D_INB4
D_INA23
D_INB6
D_INB5
D_INB7
GND
D_INB9
D_INB8
D_INB11
VDD18
D_INB12
D_INB10
D_INB14
GND
D_INB15
D_INB13
D_INB18
VDD50
D_INB17
D_INB16
D_INB21
VDD33
D_INB20
D_INB19
V_IN1
OP_ENABLE
VDD33
F24
F25
F26
DB7
GND
33
33
R17
R18
RM1_OP_HSYNC
RM1_OP_VSYNC
MEM_DQ19
OVERFLOW2
B6
OP_HSYNC
OP_VSYNC
OP_HSYNC
OP_VSYNC
VDD18
OP_FIELD
OPLL_CLK_IN
VDD33
GND
MEM_DQ19
TEST
C6
D6
A7
D_INA4
WIRE_TP31
G23
G24
G25
G26
H23
H24
H25
H26
J23
J24
J25
J26
K23
K24
K25
K26
L23
GND
OP_FIELD
RM1CLKIN
MEM_DQ16
MEM_DQ17
F2
F3
F4
RM1CLKIN
MEM_A11 R19
OP_FIELD
RM1CLKIN
MPLL_CLK_IN
MEM_DQ16
MEM_DQ17
VDD18
MEM_DQ18
MEM_DQ13
MEM_DQ14
GND
RM1CLKIN
NC_R0603
B7
33
1
D_INA1
RM1_D_FIELD
RM1_D_VALID
C7
D7
A8
R20
TP32
E1
G1
G2
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
K1
K2
K3
K4
L1
L2
L3
L4
M1
M2
M3
M4
N1
N2
N3
N4
P1
P2
P3
P4
R1
R2
R3
R4
T1
T2
T3
T4
U1
U2
U3
U4
V1
V2
V3
V4
W1
W2
W3
W4
Y1
+3VA
RM1_GP0 , RM1_GP1
Input Only or Output Only
MEM_DQ18
MEM_DQ13
MEM_DQ14
TP33
E1
1
1
GND
D_VALID
B8
DIN_CLK
VDD33
OP_FIELD_3D
RST_N
GND
DIN_CLK
DINA_OVERFLOW1
VDD18
D_VSYNC
DPLL_CLK
D_ACTIVE
GND
WIRE_TP30
C8
D8
A9
RM1_RST_N
RM1_RST_N
RM1_IRQ
MEM_DQ15
MEM_DQ10
MEM_DQ12
MEM_DQ9
MEM_DQ11
MEM_DQ6
MEM_DQ8
D_VSYNC
MEM_DQ15
MEM_DQ10
MEM_DQ12
MEM_DQ9
MEM_DQ11
MEM_DQ6
MEM_DQ8
VDD33
MEM_DQ7
MEM_DQ2
MEM_DQ4
MEM_DQ5
MEM_DQ3
MEM_DQ79
MEM_DQ1
MEM_DQ76
MEM_DQ0
MEM_DQ75
MEM_DQ77
GND
MEM_DQ78
MEM_DQ71
MEM_DQ73
MEM_DQ72
MEM_DQ74
MEM_DQ68
MEM_DQ69
VDD33
MEM_DQ70
MEM_DQ65
MEM_DQ67
GND
MEM_DQ66
MEM_DQ62
MEM_DQ64
VDD18
MEM_DQ63
MEM_DQ60
MEM_DQ61
GND
MEM_DQ59
MEM_DQ57
MEM_DQ58
MEM_DQ51
MEM_DQ56
MEM_DQ54
MEM_DQ55
VDD33
MEM_DQ52
MEM_DQ50
MEM_DQ53
NTRST
TP34
E1
RM1_DPLL_CLK
1
B9
IRQ
GND
RM1_OCLK_OUT
OUT_A23
C9
D9
A10
B10
C10
D10
A11
B11
C11
D11
DVI_ACTDATA
OP_A23
OCLK_OUT
OP_A21
VDD18
OP_A20
OP_A22
OP_A18
GND
OP_A17
OP_A19
OP_A14
VDD33
OP_A15
OP_A16
OP_A10
OP_A12
OP_A11
OP_A13
OP_A6
GND
OP_A7
OP_A9
OP_A4
OP_A8
OP_A3
OP_A5
OP_A1
OP_B23
OP_A0
OP_A2
OP_B21
VDD33
OP_B20
OP_B22
OP_B17
OP_B19
OP_B16
OP_B18
OP_B13
GND
TP49
E1
CLAMP_TESTPIN
CLAMP
OP_A23
OP_A21
OP_A20
OP_A22
OUT_A21
3
7
5
4
8
6
ADC_CLK
D_HSYNC
ADC_SYNC_INV
MCLK_IN
MCLK_OUTB
ADC_CLKB
VDD33
MEM_RAS_N
MCLK_OUT
DPLL_COAST
DPLL_DIV
MEM_WE_N
MEM_DQM_U
MEM_CS_N
MEM_DQM_L
MEM_A1
MEM_A3
MEM_CAS_N
GND
MEM_A5
MEM_A6
MEM_A0
MEM_A2
MEM_A7
MEM_A9
AC9
D_HSYNC
OUT_A20
OUT_A22
OUT_A18
ADC_SYNC_INV
0
RM1_MCLK_OUTB
AF10
AE10
AD10
AC10
AF11
AE11
AD11
AC11
AF12
AE12
AD12
AC12
AF13
AE13
AD13
AC13
AF14
AE14
AD14
AC14
AF15
AE15
AD15
AC15
AF16
AE16
AD16
AC16
AF17
AE17
AD17
AC17
AF18
AE18
AD18
AC18
AF19
AE19
AD19
AC19
AF20
AE20
AD20
AC20
AF21
AE21
AD21
AC21
AF22
AE22
AD22
AC22
AF23
AE23
AD23
AF24
AE24
AF25
MEM_DQ7
MEM_DQ2
MEM_DQ4
MEM_DQ5
MEM_DQ3
MEM_DQ79
MEM_DQ1
MEM_DQ76
MEM_DQ0
MEM_DQ75
MEM_DQ77
R23 RM1_MCLK_IN
1
2
L24
L25
L26
RP10
47_RP
TP35
E1
OP_A18
OP_A17
OP_A19
OP_A14
TP36
E1
RM1_ADC_CLKB
1
3
5
2
4
6
1
OUT_A17
OUT_A19
OUT_A14
M23
M24
M25
M26
N23
N24
N25
N26
P23
P24
P25
P26
R23
R24
R25
R26
T23
33
R24 RM1_MEM_RAS_N
A12
MEM_RAS_N
RM1_MCLK_OUT
7
8
B12
C12
D12
A13
B13
C13
D13
A14
B14
C14
D14
A15
B15
C15
D15
A16
B16
C16
D16
A17
B17
C17
D17
A18
B18
C18
D18
A19
B19
C19
D19
A20
B20
C20
D20
A21
B21
C21
D21
A22
B22
C22
D22
A23
B23
C23
D23
A24
B24
C24
A25
B25
A26
RP11
47_RP
DPLL_COAST
NC_R0603
1
E1
OP_A15
OP_A16
OP_A10
OP_A12
OUT_A15
OUT_A16
OUT_A10
OUT_A12
OUT_A11
OUT_A13
OUT_A6
TP50
R26 RM1_DPLL_DIV
RM1_MEM_WE_N
RM1_MEM_DQM_U
RM1_MEM_CS_N
RM1_MEM_DQM_L
RM1_MEM_A1
RM1_MEM_A3
RM1_MEM_CAS_N
3
1
7
5
3
1
5
4
2
8
6
+3VA
1
3
5
7
2
4
6
8
MEM_WE_N
MEM_DQM_U
MEM_CS_N
OP_A11 RP12
47_RP
4
2
6
8
MEM_DQM_L
OP_A13
OP_A6
OP_A7
MEM_DQ78
MEM_DQ71
MEM_DQ73
MEM_DQ72
MEM_DQ74
MEM_DQ68
MEM_DQ69
MEM_A1
1
3
5
7
2
4
6
8
MEM_A3
V_IN1
V_IN0
7
MEM_CAS_N
GND
V_IN0
D_INB22
V_IN3
D_INB23
V_IN4
V_IN2
V_IN6
V_IN8
RP14
47_RP
OUT_A7
OUT_A9
OUT_A4
OUT_A8
OUT_A3
OUT_A5
OUT_A1
OP_A9
OP_A4
OP_A8
OP_A3
MEM_A5
MEM_A6
MEM_A0
MEM_A2
MEM_A7
MEM_A9
MEM_A4
MEM_A10
MEM_A8
RM1_MEM_A5
RM1_MEM_A6
RM1_MEM_A0
RM1_MEM_A2
RM1_MEM_A7
RM1_MEM_A9
RM1_MEM_A4
RM1_MEM_A10
1
5
3
2
6
4
V_IN3
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
V_IN4
V_IN2
V_IN6
V_IN8
V_IN7
V_IN5
V_IN10
7
8
RP16
47_RP
MEM_DQ70
MEM_DQ65
MEM_DQ67
T24
T25
T26
OP_A5
OP_A1
OP_A0
OP_A2
1
5
7
2
6
8
MEM_A4
VDD33
MEM_A10
MEM_DQ47
MEM_A8
V_IN[0..15]
OUT_A0
OUT_A2
U23
U24
U25
U26
V23
V24
V25
V26
W23
W24
W25
W26
Y23
V_IN[0..15]
V_IN7
V_IN5
MEM_DQ66
MEM_DQ62
MEM_DQ64
3
4
RP18
47_RP
YUV422
Y -- V_IN[15..8]
UV -- V_IN[7..0]
V_IN10
VDD50
V_IN11
V_IN9
V_IN13
VDD33
V_IN14
V_IN12
V_VALID
GND
+3VA
RP13 33_RP
RP15 33_RP
RP17 33_RP
RP19 33_RP
RM1_MEM_A8
MEM_DQ47
MEM_DQ46
MEM_DQ45
V_IN11
V_IN9
GND
MEM_DQ63
MEM_DQ60
MEM_DQ61
MEM_DQ46
MEM_DQ45
MEM_BS
VDD18
MEM_DQ43
MEM_DQ42
MEM_DQ44
GND
MEM_DQ40
MEM_DQ39
MEM_DQ41
MEM_DQ36
MEM_DQ38
MEM_DQ35
MEM_DQ37
VDD33
MEM_DQ34
MEM_DQ31
MEM_DQ33
MEM_DQ32
MEM_DQ30
MEM_DQ28
MEM_DQ29
GND
V_IN13
V_IN14
V_IN12
V_IN15
V_VALID
R27
1K
R28
1K
RM1_MEM_BS
OP_A[0..23]
MEM_DQ59
MEM_DQ57
MEM_DQ58
MEM_DQ51
MEM_DQ56
MEM_DQ54
MEM_DQ55
MEM_DQ43
MEM_DQ42
MEM_DQ44
RED -- OP_A[23..16]
GREEN -- OP_A[15..8]
BLUE -- OP_A[7..0]
VCLK
VCLK
VCLK
OP_B14
OP_B15
OP_B10
VDD18
OP_B11
OP_B12
PPLL_CLK_IN
GND
MEM_DQ40
MEM_DQ39
MEM_DQ41
MEM_DQ36
MEM_DQ38
MEM_DQ35
MEM_DQ37
Y24
Y25
Y26
V_IN15
V_HSYNC
VDD18
V_FIELD
V_ACTIVE
RD_N
GND
CS_N
V_VSYNC
AD1
VDD33
AD0
WR_N
AD5
AD3
AD4
AD2
AD7
DB0
V_HSYNC
V_HSYNC
V_FIELD
V_ACTIVE
CPU_RD_N
AA23
AA24
AA25
AA26
AB23
AB24
AB25
AB26
AC23
AC24
AC25
AC26
AD24
AD25
AD26
AE25
AE26
AF26
MEM_A[0..11]
MEM_DQ52
MEM_DQ50
MEM_DQ53
Y2
Y3
Y4
V_ACTIVE
CPU_RD_N
RM1CLKIN
RM1_CS_N
V_VSYNC
CPU_A1
RM1_NTRST
RM1_TMS
AA1
AA2
AA3
AA4
AB1
AB2
AB3
AB4
AC1
AC2
AC3
AD1
AD2
AE1
RM1_CS_N
V_VSYNC
24.576MHz
OP_B8
OP_B9
GND
MEM_DQ48
MEM_DQ49
MEM_DQ34
MEM_DQ31
MEM_DQ33
MEM_DQ32
MEM_DQ30
MEM_DQ28
MEM_DQ29
MEM_DQ48
TMS
MEM_DQ49
MPLL_CLK_IN , OPLL_CLK_IN ,
PPLL_CLK_IN are 24.576MHz
VDD33
CPU_A0
GND
GND
TDI
TCK
TDO
VDD18
OP_B6
GND
OP_B7
VDD33
OP_B4
OP_B3
OP_B5
GND
CPU_A5
CPU_A3
CPU_A4
CPU_A2
CPU_A7
R29
1K
R30
1K
GND
MEM_DQ27
MEM_DQ26
OP_B1
OP_B0
MEM_DQ27
MEM_DQ26
GND
MEM_DQ25
GND
GND
CPU_A6
MEM_DQ25
AD6
GND
OP_B2
CPU_A[0..7]
RM1_WR_N
GND
R31
33
GND
RM1_WR_N
+3VA
MEM_BS
CPU_D0
+3VA
L8
RM1_MCLK_OUT
+
MEM_CLK
C43
10UF/16
C44
0.1UF
C45
0.1UF
C46
0.1UF
R32
1K
From Pin B12,
Former R25
Z1000/100MHZ
+1_8V
+3VA
+1_8V
+
C47
C48
C49
C50
0.1UF
C51
0.1UF
C52
C53
C54
0.1UF
C55
0.1UF
C56
0.1UF
C57
0.1UF
C58
0.1UF
R33
1K
10UF/16
0.1UF
0.1UF
0.1UF
0.1UF
+3VA
L9
+
C59
C60
C61
C62
0.1UF
C63
0.1UF
C64
C65
C66
0.1UF
C67
0.1UF
C68
0.1UF
C69
0.1UF
C70
0.1UF
C71
0.1UF
R34
1K
RM1_OCLK_OUT
OCLK_OUT
10UF/16
0.1UF
0.1UF
0.1UF
0.1UF
From Pin AE9,
Former R22
Z1000/100MHZ
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
modify this area
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
6
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
+3VS
+3VS
U6
R35
5.1K
R36
2K
R37
2K
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
WP
SCL
SDA
R114
5.1K
R115
5.1K
AT24C16
RESET_N
RESET_N
KEY_LED2
KEY_LED1
CPU_D[0..7]
PIO1
R38
33
CPU_D[0..7]
CPU_A[0..19]
CPU_D[0..15]
SDA
SCL
SDA
SCL
D
C
B
A
D
C
B
A
SDA
SCL
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
WRITE_PROT
WRITE_PROT
R122
0
+3VS
+3VS
FAN_CTRL
DMD_SCL
DMD_SDA
R123
0
+3VS
R39
10K
R40
10K
R41 R42
+3VS
10K
10K R43
R45
R44
5.1K
R105
2K
R46
5.1K
POWER
NC_R0603
5.1K
CPU_A[0..7]
CPU_A0
CPU_A1
CPU_A2
CPU_A3
CPU_A4
CPU_A5
CPU_A6
CPU_A7
R47
R48
PIO17_1
33
PIO17_2
Q28
1
R49
2N2907
10K
10K
PIO19
R50
33
DLP_RST
+3VS
R51
33
2K
BACKLIGHT_CTRL
U8A
CPU_PCS0_N
CPU_PCS0_N
(INT1)
74HC132
R52
+5VS
E1
TP37
IR_IN
1
INT0
3
R53
33
2
IR
Note: Instead of KM616V1000B,
IS61LV25616-12T (256K x 16 bit
4M) can be stuffed for debug.
C72
+3VS
470PF
(PIO2)
LAMPLIT
INT2
RM1_IRQ
+3VS
RM1_IRQ
CPU_A5
CPU_A4
CPU_A3
CPU_A2
CPU_A1
CPU_LCS_N
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_A6
CPU_A7
CPU_A8
CPU_RD_N
CPU_BHE_N
CPU_A0
CPU_D15
CPU_D14
CPU_D13
CPU_D12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A5
A6
A7
+3VS
U9
A2
A1
IS61LV25616-12T
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
R54
NC_R0603
A0
R55
R56
R57
NC_0603
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A15
A14
A13
A12
NC
CPU_D0
CPU_D8
CPU_D1
CPU_D9
CPU_D2
CPU_D10
CPU_D3
CPU_D11
CPU_D4
CPU_D12
CPU_D5
5.1K
5.1K
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
AD0
AD8
AD1
AD9
AD2
AD10
AD3
AD11
AD4
AD12
AD5
GND
AD13
AD6
VCC
AD14
AD7
AD15
S6/LOCK/CLKDIV2
UZI
TXD1
RXD1
CTS0/ENRX0
RXD0
TXD0
INT4
R58
33
52
INT4
CPU_MCS1_N
RM1_CS_N
R119
R59
R60
33
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
BALLAST_CTRL
RM1_CS_N
MUX_SEL_Q
KEY_LED0
MCS1
MCS0
DEN/DS
DT/R
NMI
SRDY
HOLD
HLDA
WLB
WHB
GND
A0
+3VS
PIO5
PIO4
33
33
+3VS
(PIO5)
(PIO4)
CPU_D4
CPU_D5
CPU_D6
CPU_D11
CPU_D10
CPU_D9
CPU_D8
CPU_NMI R61
0
SYNVAL
(PIO6)
E1
SYNCVALID
CPU_D7
CPU_HOLD
CPU_HLDA
CPU_WLB
CPU_WHB
R62 1K
CPU_WR_N
CPU_A16
CPU_A15
CPU_A14
CPU_A13
CPU_A17
R117
33
CPU_A9
1
1
E1
TP40
TP41
A8
A9
A10
A11
NC
CPU_A10
CPU_A11
CPU_A12
CPU_A18
CPU_D13
CPU_D6
U10
RDC8820
CPU_A0
CPU_A1
A1
VCC
A2
A3
A4
A5
A6
A7
A8
CPU_D14
CPU_D7
CPU_D15
CPU_A2
CPU_A3
CPU_A4
CPU_A5
CPU_A6
CPU_A7
CPU_A8
CPU_A9
CPU_A10
CPU_A11
(128KBytes SRAM)
CPU_D[0..15]
CPU_A[0..19]
E1
TP42
CPU_UZI
1
CPU_TXD1
CPU_RXD1
CPU_RXD0
CPU_TXD0
CPU_RXD0
CPU_TXD0
A9
A10
A11
2
J3
+3VS
CPU_A0
CPU_A10
CPU_A11
CPU_A12
CPU_A13
CPU_A14
CPU_A15
CPU_A16
CPU_A17
CPU_A18
CPU_A19
1
2
3
4
5
6
7
8
9
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
41
42
43
44
45
46
47
48
49
CPU_A17
CPU_A1
CPU_A2
CPU_A3
CPU_A4
CPU_A5
CPU_A6
CPU_A7
CPU_A8
CPU_A9
+3VS
CPU_A16
CPU_A15
CPU_A14
CPU_A13
CPU_A12
CPU_A11
CPU_A10
CPU_A9
R63
10K
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
CPU_D15
CPU_D7
CPU_D14
CPU_D6
CPU_D13
CPU_D5
CPU_D12
CPU_D4
CPU_ARDY
Link to test
board.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10 50
11 51
12 52
13 53
14 54
15 55
16 56
17 57
18 58
19 59
20 60
21 61
22 62
23 63
24 64
25 65
26 66
27 67
28 68
29 69
30 70
31 71
32 72
33 73
34 74
35 75
36 76
37 77
38 78
39 79
40 80
CPU_D0
CPU_D8
CPU_D9
10K HI_A19
CPU_A12
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
+3VS
R65
CPU_A13
CPU_A14
CPU_A15
CPU_A16
CPU_A17
CPU_A18
CPU_A19
CPU_D10
CPU_D11
CPU_D12
CPU_D13
CPU_D14
CPU_D15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU_WR_N
WE#
RESET#
NC
CPU_D11
CPU_D3
CPU_D10
CPU_D2
CPU_D9
CPU_D1
CPU_D8
CPU_D0
E1
NC
E1
TP43
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
CPU_A19
CPU_A18
CPU_A8
CPU_A7
CPU_A6
CPU_A5
CPU_A4
CPU_A3
CPU_A2
U12
RESETVCC
CPU_S0
CPU_S1
CPU_S2
POWERON_TEST
CPU_UCS_N
FLASH1_CE
RESET_N
RESETVCC
AM29LV160DT-90EI
TP44
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
CPU_RD_N
R67
1M
RM1_IRQ
SCL
SDA
RM1CLKIN
CPU_WR_N
CPU_RD_N
CPU_MCS1_N
CPU_MCS2_N
CPU_MCS3_N
X2
CPU_HOLD
CPU_HLDA
CPU_BHE_N
RM1_CS_N
CPU_LCS_N
25MHZ
+3VS
R69
R68
(256K x 16Bit FLASH)
CPU_A1
FLASH1_CE
CPU_UCS_N
3
1
NC_R0603
+3VS
+3VS
C75
C76
CPU_RXD0
CPU_TXD0
CPU_RXD1
CPU_TXD1
R70
33
10K
20PF
20PF
C Y
X
+3VA
CPU_WR_N
CPU_RD_N
CPU_WR_N
CPU_RD_N
L6
Z1000/100MHZ
+5VS
+5VA
+5VS
ANTI_CLKDIV
MUX_BUFFER
MUX_SEL_P
R71
R72
33
33
(PIO29)
AMP 80PIN D0.6
+12VA
MUX_BUFFER
MUX_SEL_P
RM1CLKIN
(PIO21)
R73
33
(PIO20)
Note: Infra-Red generates two interrupts: at the rising edge and at the falling edge,
for IR signal decoding.
TP45
+3VS
+3VS
The RM1_WR_N is
delayed by 2 gates
because the data
should be stable
during the falling
edge of the WRITE
signal.
+3VS
U7B
U7C
Benq Corporation
4
5
9
R74
33 CPU_DELAY2
CPU_DELAY1
CPU_WR_N
C77
22UF/16
6
8
Project Code
99.J5877.001
RM1_WR_N
Model Name
HT720G
OEM/ODM Model Name
NA
C78
0.1UF
C79
0.1UF
C80
0.1UF
C81
0.1UF
C82
0.1UF
C83
0.1UF
C84
0.1UF
C85
0.1UF
C86
0.1UF
C87
0.1UF
10
+
Title
74VHC32
74VHC32
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
Rev.
PCB P/N
<Size>
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
7
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
+3VS
KEYPAD[0..9]
RP20 47_RP
U13
KEYPAD0
KEYPAD1
KEYPAD2
KEYPAD3
KEYPAD4
KEYPAD5
KEYPAD6
KEYPAD7
INLTCH1_1
INLTCH1_2
INLTCH1_3
INLTCH1_4
INLTCH1_5
INLTCH1_6
INLTCH1_7
INLTCH1_8
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
2
4
6
18
16
14
12
9
7
5
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
8
11
13
15
17
D
C
B
A
D
C
B
A
3
IORD0_N
RP21 47_RP
1
19
1G
2G
+3VS
+3VS
74AHC244
+3VS
U14A
RP22 47_RP
U15
CPU_A3
CPU_A4
KEYPAD8
KEYPAD9
INLTCH2_1
INLTCH2_2
INLTCH2_3
INLTCH2_4
INLTCH2_5
INLTCH2_6
INLTCH2_7
INLTCH2_8
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
2
3
4
5
6
7
1
3
5
7
2
4
6
8
2
4
6
2
4
6
18
16
14
12
9
7
5
3
CPU_A3
CPU_A4
A
B
Y0
Y1
Y2
Y3
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
IORD0_N
IORD1_N
U7A
1
2
CPU_RD_N
LAMP_PROTECT
RP23
IOCS_RD_SET_N
E1 WIRE_TP53
E1 WIRE_TP52
E1 WIRE_TP51
E1 WIRE_TP46
3
1
1
1
1
1
8
8
G
CPU_PCS0_N
TP53
TP52
TP51
TP46
TP47
1
3
5
7
11
13
15
17
74VHC139
74VHC32
E1 WIRE_TP47
1
47_RP
IORD1_N
1
19
1G
2G
74AHC244
DVI_SCDT
SPAREI
CPU_D[0..7]
CPU_D[0..7]
+3VS
U17
RP24
47_RP
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
OUTLTCH1_1
OUTLTCH1_2
OUTLTCH1_3
OUTLTCH1_4
OUTLTCH1_5
OUTLTCH1_6
OUTLTCH1_7
OUTLTCH1_8
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1
2
4
6
8
2
4
6
8
MUX_SEL
TRIGGER
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
3
5
7
1
3
5
7
Note: All outputs are disabled
after power-up until
IOCS_WR_SET_N is activated by
software.
SII141_PDO
RM1_RST_N
MCURESET
POWERON
WRITE_PROT
DLP_SPARE
+3VS
+3VS
U14B
DLP_SPARE
CPU_A1
CPU_A2
14
13
12
11
10
9
CPU_A1
CPU_A2
A
B
Y0
Y1
Y2
Y3
IOWR0_N
IOWR0_N
RP25
47_RP
U7D
11
1
CLK
OC
CPU_WR_N
OUT_BUFFER_OE_N
12
13
CPU_WR_N
IOCS_WR_SET_N
11
15
G
CPU_PCS0_N
74ABT574
CPU_PCS0_N
74VHC139
R75 R76
74VHC32
10K
10K
+3VS
CPU_D[0..7]
CPU_D[0..7]
U22
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
CPU_D7
OUTSPARE1
OUTSPARE2
OUTSPARE3
OUTSPARE4
OUTSPARE5
OUTSPARE6
OUTSPARE7
OUTSPARE8
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
IOWR0_N1
11
1
CLK
OC
OUT_BUFFER_OE_N
R106
0
R107
0
R108
0
R109
0
R110
0
R111
R112
0
R113
0
0
74ABT574
+3VS
+3VS
SPAREO
U8B
74HC132
IOCS_WR_SET_N
4
5
+3VS
6
R77
180
U18
RESETVCC
3
1
RESETVCC
VDD
RES
+3VS
2
GND
S_BUFFER
+3VS
AME8500BEET
C89
0.1UF
C90
0.1UF
C91
0.1UF
C92
0.1UF
C93
0.1UF
C94
0.1UF
+3VS
R118
100K
R78
5.1K
R80
1K
D3
BAV99
9
OUT_BUFFER_OE_N
3.3VRESET
8
3
RESET_N
RESET_N
10
U8C
74HC132
C88
1U
Z
** Generate Harward RESET Singnal **
VDD
3
SOT23
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
1
2
RST
GND
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
AME8500AF27
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
8
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
OP_A[0..23]
J4
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
OP_A23
OP_A21
OP_A19
OP_A17
OP_A15
OP_A13
OP_A11
OP_A9
OP_A22
OP_A20
OP_A18
OP_A16
OP_A14
OP_A12
OP_A10
OP_A8
D
C
B
A
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
OP_A7
OP_A6
OP_A5
OP_A4
PIN41, 42 is prohibited by
mechanical design,
OP_A3
OP_A2
OP_A1
OP_A0
OCLK_OUT
OP_HSYNC
OP_VSYNC
LAMPLIT
OP_ENABLE
DMD_SDA
DMD_SCL
POWER
DLP_RESETZ
POWERON
DLP_SPARE
DLPSP
R124
0
+3VS
+5VS
+3VA
SYNVAGR125
BALLAG
0
0
SYNCVALID
BALLAST_CTRL
+5VA
R126
+12VA
OP_FIELD
THIS PIN ONLY FOR TEST
GOLDEN_FINGER
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
of
10
9
Approved By
Download from Www.Somanuals.com. All Manuals Search And Download.
COLIN CHANG
BEN CHEN
ANGEL HU
5
4
3
2
1
MEM_DQ[0..79]
+3VB_MEM
MEM_DQ[0..79]
+3VA
+3VB_MEM
MEM_DQ0
+3VA
+3VB_MEM
MEM_DQ48
+3VA
U19
VSS
U20
VSS
U21
VSS
1
2
3
4
5
6
7
8
9
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
MEM_DQ16
MEM_DQ31
MEM_DQ15
MEM_DQ63
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
MEM_DQ17
MEM_DQ18
MEM_DQ30
MEM_DQ29
MEM_DQ1
MEM_DQ2
MEM_DQ14
MEM_DQ13
MEM_DQ49
MEM_DQ50
MEM_DQ62
MEM_DQ61
D
C
B
A
D
C
B
A
MEM_DQ19
MEM_DQ20
MEM_DQ28
MEM_DQ27
MEM_DQ3
MEM_DQ4
MEM_DQ12
MEM_DQ11
MEM_DQ51
MEM_DQ52
MEM_DQ60
MEM_DQ59
MEM_DQ21
MEM_DQ22
MEM_DQ26
MEM_DQ25
MEM_DQ5
MEM_DQ6
MEM_DQ10
MEM_DQ9
MEM_DQ53
MEM_DQ54
MEM_DQ58
MEM_DQ57
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
MEM_DQ23
MEM_DQ24
MEM_DQ7
MEM_DQ8
MEM_DQ55
MEM_DQ56
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A11
MEM_A10
MEM_A0
MEM_A1
MEM_A2
MEM_A11
MEM_A10
MEM_A0
MEM_A1
MEM_A2
MEM_A11
MEM_A10
MEM_A0
MEM_A1
MEM_A2
A5
A4
A3
DQM3
VSS
A5
A4
A3
DQM3
VSS
A5
A4
A3
DQM3
VSS
NC
NC
NC
MEM_DQ32
MEM_DQ47
MEM_DQ64
MEM_DQ79
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
MEM_DQ33
MEM_DQ34
MEM_DQ46
MEM_DQ45
MEM_DQ65
MEM_DQ66
MEM_DQ78
MEM_DQ77
MEM_DQ35
MEM_DQ36
MEM_DQ44
MEM_DQ43
MEM_DQ67
MEM_DQ68
MEM_DQ76
MEM_DQ75
MEM_DQ37
MEM_DQ38
MEM_DQ42
MEM_DQ41
MEM_DQ69
MEM_DQ70
MEM_DQ74
MEM_DQ73
MEM_DQ39
MEM_DQ40
MEM_DQ71
MEM_DQ72
BS -- Bank Select
CS -- Chip Select
RAS -- Row Address Strobe
CAS -- Column Address Strobe
WE -- Write Enable
K4S643232C-TC/L10
K4S643232C-TC/L10
K4S643232C-TC/L10
DQM_L -- Lower Byte Data Qualifier
DQM_U -- Upper Byte Data Qualifier
(MEM_A11= =D_INA2_OVFL)
(Address and Control bus)
MEM_A[0..11]
MEM_DQM_L
MEM_WE_N
MEM_CAS_N
MEM_RAS_N
MEM_CS_N
MEM_CLK
MEM_BS
MEM_DQM_U
MEM_A11 -- Higher Bank Select (BA1)
MEM_BS -- Lower Bank Select (BA0)
+3VA
RP26
NC_RP
RP27
NC_RP
RP28
NC_RP
RP29
NC_RP
RP30
NC_RP
MEM_DQM_L
MEM_DQM_U
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
Test parts and resistors are located at the end of bus chain.
MEM_A6
MEM_A7
MEM_A8
MEM_A9
All address and control signals must be routed in a daisy
chain, with the same trace length from RM1 to each SDRAM.
MEM_A10
MEM_A11
MEM_BS
Termination resistors values = (traces impedance) x 2
MEM_CS_N
MEM_WE_N
MEM_RAS_N
MEM_CAS_N
MEM_CLK
RP31
NC_RP
RP32
NC_RP
RP33
NC_RP
RP34
NC_RP
RP35
NC_RP
VDD - Input buffers and the
core supply
+3VA
+
C95
10UF/16
C96
0.1UF
C97
0.1UF
C98
0.1UF
C99
0.1UF
C100
0.1UF
C101
0.1UF
C102
0.1UF
C103
0.1UF
L7
VDD - Output buffers
Z1000/100MHZ
+3VB_MEM
+3VA
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
+
C104
0.1UF
C105
10UF/16
C106
0.1UF
C107
0.1UF
C108
0.1UF
C109
0.1UF
C110
0.1UF
C111
0.1UF
C112
0.1UF
C113
0.1UF
C114
0.1UF
C115
0.1UF
C116
0.1UF
C117
0.1UF
C118
0.1UF
C119
0.1UF
C120
0.1UF
C121
0.1UF
Title
MAIN BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-001
Size
<Size>
Rev.
PCB P/N
0
48.J5801.S02
S02
Thursday, January 16, 2003
Prepared By
Date:
Sheet
Reviewed By
o f
10
10
Approved By
COLIN CHANG
BEN CHEN
ANGEL HU
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
P3P3V
LAMOLITZ CIRCUIT
VOUT_BV[7..0]
VOUT_GY[7..0]
VOUT_RU[7..0]
R16
1K
C22
0.047U K
R17
10K
R18
2K
D
C
B
A
D
C
B
A
LAMPLITZ
1
3
5
7
9
2
4
6
8
1
3
5
7
2
4
6
VOUT_RU7
VOUT_RU5
VOUT_RU3
VOUT_RU1
J2
VOUT_RU6
VOUT_RU4
VOUT_RU2
VOUT_RU0
VOUT_GY6
VOUT_GY4
VOUT_GY2
VOUT_GY0
VOUT_BV6
VOUT_BV4
VOUT_BV2
VOUT_BV0
Q1
LAMPD
1
MMBT2222AWT1
8
20D0038104
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Q2
LAMPHIGH
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
1
2
3
4
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MMBT2222AWT1
BALLAST_CTRL
VOUT_GY7
VOUT_GY5
VOUT_GY3
VOUT_GY1
J1
P3P3V
R126
NC
VOUT_BV7
VOUT_BV5
VOUT_BV3
VOUT_BV1
U11A
3
14
R124
1K
1K
R19
47
1
2
RESETZ
LAMPEN
TURNON
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
R112
7
C23
0.047U K
R123
R111
10K
74ACT08MTC
CLKIN
VIO20/M_DACT
SDA_DI
MHSYNCZ
MVSYNCZ
LAMPLITZ
10K
SCL_DI
RESETZ
LAMPEN CIRCUIT
BALLAST_CTRL
PWRGOOD
P3P3V
P3P3V_IN
R125
10K
L6 80 OHM
3V3_SENSOR
C24
0.1U Z
C25
0.1U Z
P3P3V
3V3_SENSOR
L9
P12V
SYNCVALID
R22
2K
L8
120 OHM
P12V_IN
P5V
R27
C36
0.047U K
80 OHM
P5V_IN
L7
C34
0.047U K
C35
4.7U Z
(1206)
R26
10K
80 OHM
C28
C29
R24
180
0.1U Z
0.1U Z
C26
C27
0.1U Z
510K
0.1U Z
20C1001100
2V_REF
3
4
+
-
1
CWINDEX
R29
6.8K
U4
LMC7225
(To DDP1010)
R25
75K
J3
INPUT SIGNALS FROM MAIN BOARD
OPDIODE
CWSPEED
R28
1
2
3
CWSPPED1
P3P3V
20L2021003
10K
C33
10P J
C30
0.1U Z
TP51
R121 NC_R0603
SCL_DI
SCL_D
CWINDEX CIRCUIT
R119
4.7K
R120
4.7K
J5
3
TP50 TP49
(IIC From Main CPU)
SW2
2240138001
SCL_DTI
SDA_DTI
2
1
INPUTS, LAMPEN, LAMPLIZ, CWINDEX
20L2021003
SDA_DI
(IIC From Computer)
(Connector for DLP FALSH DOWNLOAD)
Benq Corporation
Project Code
Model Name
OEM/ODM Model Name
NA
R122 NC_R0603
HT720G
99.J5877.001
SDA_D
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
0
48.J5802.S01
S01
TP52
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
1
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
FLDATA[0..15]
FLDATA[0..15]
P3P3V
D
C
B
A
D
C
B
A
C21
0.1U Z
DDP1010
U3
FLADDR[0..18]
FLDATA0
FLDATA1
FLDATA2
FLDATA3
FLDATA4
FLDATA5
FLDATA6
FLDATA7
FLDATA8
FLDATA9
FLDATA10
FLDATA11
FLDATA12
FLDATA13
FLDATA14
FLDATA15
AG26
AH26
AJ26
AF25
AG25
AJ25
AJ24
AF24
AG24
AH24
AF23
AG23
AG22
AJ22
AF20
AJ21
AH7
AF8
AG8
AF9
AG9
AH9
AG10
AJ10
AG13
AH13
AJ14
AF15
AJ15
AJ17
AH17
AH18
AG19
AH20
AJ20
AG20
FLDATA0
FLDATA1
FLDATA2
FLDATA3
FLDATA4
FLDATA5
FLDATA6
FLDATA7
FLDATA8
FLDATA9
FLDATA10
FLDATA11
FLDATA12
FLDATA13
FLDATA14
FLDATA15
FLADDR19
FLADDR18
FLADDR17
FLADDR16
FLADDR15
FLADDR14
FLADDR13
FLADDR12
FLADDR11
FLADDR10
FLADDR09
FLADDR08
FLADDR07
FLADDR06
FLADDR05
FLADDR04
FLADDR03
FLADDR02
FLADDR01
FLADDR0
FLADDR18
FLADDR17
FLADDR16
FLADDR15
FLADDR14
FLADDR13
FLADDR12
FLADDR11
FLADDR10
FLADDR9
FLADDR8
FLADDR7
FLADDR6
FLADDR5
FLADDR4
FLADDR3
FLADDR2
FLADDR1
FLADDR0
FLADDR0
FLADDR1
FLADDR2
FLADDR3
FLADDR4
FLADDR5
FLADDR6
FLADDR7
FLADDR8
FLADDR9
FLADDR10
FLADDR11
FLADDR12
FLADDR13
FLADDR14
FLADDR15
FLADDR16
FLADDR17
FLADDR18
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
15
47
A0
A1
A2
A3
A4
A5
A6
A7
FLDATA0
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
D0
D1
D2
D3
D4
D5
D6
D7
D8
P5V
FLDATA1
FLDATA2
FLDATA3
FLDATA4
FLDATA5
FLDATA6
FLDATA7
FLDATA8
FLDATA9
FLDATA10
FLDATA11
FLDATA12
FLDATA13
FLDATA14
FLDATA15
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC
R7
10K
R8
10K
D9
D10
D11
D12
D13
D14
D15/A-1
IIC Bus (open drain)
DDP2P5V
AH23
AF22
SDA_D
SCL_D
L4
SDA0
SCL0
RY/BY
BYTE
AH27
AJ27
AF19
120 OHM
FL_OE
FL_WE
FL_CS
AG28
AF28
AG29
Minimize Noise on PLL_VCCA
APLLMD1
APLLMD0
PLL_VCCA
14
28
11
26
NC
OE
WE
CE
C17
0.1U Z
C18
0.1U Z
FL_OEZ
FL_WEZ
FL_CSZ
AF27
OCLKA
COSC
P3P3V
12
RST
TP39 TP40 TP41
Master Clock (100MHz)
L5
FLASH
AM29LV800BB-120EC
F3
F2
G4
MOSCN
MOSC
MCRYSTALEN
VDDMOSC
MOSCEN
MOSC
4
3
2
VCC OUT
OE GND
MCRYSTALEN
V2
W3
SR16STROBE(To DAD1000)
120 OHM
SR16STRB
SR16OEZ
C31
22P J
R10
39.2F
1
SR16OEZ
7229800219
(Pin 14 should be disconnected from P3P3V)
R11
Y1
100MHZ
G3
G2
H4
R4
R1
U1
U2
SR16ADDR3
SR16ADDR2
SR16ADDR1
SR16ADDR0
10K
C20
0.1U Z
POSCN
POSC
PCRYSTALEN
SR16ADDR3
SR16ADDR2
SR16ADDR1
SR16ADDR0
L19
220OHM
C19
0.1U Z
68.00129.0D1
T26
WCLK
CLKIN
N2
P1
Pixel Clock (74.25MHz) from Scalar
SR16MODE1
SR16MODE0
SR16MODE1
SR16MODE0
TP30 TP29 TP28
DDP3P3V
R12
1K
AB28
AA26
AB27
AB26
AC28
AC27
AC26
AD28
Y2
Y1
SR16SEL1
SR16SEL0
DRCGPDZ
DADSELZ
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
SR16SEL1
SR16SEL0
J3
SERIES CONTROL PORT 0
(To MUSTANG)
DMDBIN3
DMDBIN2
DMDBIN1
DMDBIN0
K3
K1
N3
SCPDO
SCPDI
SCPCLK
TP31 PWM0
TP32 PWM1
TP37 TP38
DDP3P3V
AB1
Y4
AA1
Y3
SR16VCCEN
DMDVCCEN
VCC2EN
VBIASEN
VRSTEN
AD27
AD29
AE28
AE29
AE27
AE26
AF29
AH3
DIO8
DIO9
DIO10
DIO11/ASICID0
DIO12/ASICID1
DIO13/ASICID2
DIO14
MTRPWM
W4
SERIES CONTROL PORT 1
R13
R14
1.33KF
AF1
AF2
AF3
(To DAD1000)
SCP_CLK
SCP_DO
SCP_DI
SCP1_CLK
SCP1_DO
SCP1_DI
1.33KF
DMDSPARE0
DMDSPARE1
DMDSPARE0
DMDSPARE1
TP45
TP46 TP47 TP48
DIO15
TSTPNT3
TSTPNT2
TSTPNT1
TSTPNT0
A21
D19
C20
A20
TSTPNT3
TSTPNT2
TSTPNT1
TSTPNT0
AG4
AH4
AJ4
AF5
AG5
AH6
AF7
AG7
MTRRSTZ
MTRSELZ
MTRCLK
DIO16
DIO17
DIO18
DIO19
DIO20
DIO21
DIO22
DIO23
(To SSI Motor)
SW1
6240019001
(v-sync, delay CWI, spoketest for debug)
DDP3P3V
J2
MTRDATA
OCLKF
OCLKE
OCLKD
OCLKC
OCLKB
OCLKA
TP2
TP1
ARMTEST1
ARMTEST2
H3
F1
E1
D1
E3
DADINTZ
R114
10K
TP33TP27TP26
TP36
R115
10K
R113
10K
DIO24
IDO25
AB3
AB4
AC2
AC3
AC4
AD2
AD3
AD4
50MHz Clock
DIO24
DIO25
DIO26
DIO27
DIO28
DIO29
DIO30
DIO31
DDP1010 Flash, Micro, Clocks, DAD1000 Control
R15
22
OCLKA1
OCLKA
CWINDEX
MTRDMUX
DMDRSTZ
Benq Corporation
PUM_ARSTZ
EXT_ARSTZ
C1
D2
D3
PUM_ARSTZ
EXT_ARSTZ
EXT_ARST
Project Code
Model Name
OEM/ODM Model Name
NA
(To DAD1000)
DMDSELZ
DIO31
HT720G
99.J5877.001
Title
R116
NC_R0603
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
U2B
DDP1010
Size
<Size>
Rev.
PCB P/N
Micro, Clocks ,SR16 and Flash interface
TP34 TP35
0
48.J5802.S01
S01
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
2
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
TP42
VOUT_GY[7..0]
DDAP[15..0]
DDAN[15..0]
U2C
DDP1010
VOUT_GY7
VOUT_GY6
VOUT_GY5
VOUT_GY4
VOUT_GY3
VOUT_GY2
VOUT_GY1
VOUT_GY0
K28
K29
K27
L26
J29
J28
J27
K26
H29
H28
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DDAP15
DDAP14
DDAP13
DDAP12
DDAP11
DDAP10
DDAP9
DDAP8
DDAP7
DDAP6
DDAP5
DDAP4
DDAP3
DDAP2
DDAP1
DDAP0
DDAN15
DDAN14
DDAN13
DDAN12
DDAN11
DDAN10
DDAN9
DDAN8
DDAN7
DDAN6
DDAN5
DDAN4
DDAN3
DDAN2
DDAN1
DDAN0
H1
J1
K2
L1
L2
M2
N1
P3
T3
U3
V3
V4
AA2
AB2
AD1
AE3
K4
L4
L3
M4
M3
N4
P4
P2
T4
U4
W2
W1
AA3
AA4
AE2
AE4
DDAP15
DDAP14
DDAP13
DDAP12
DDAP11
DDAP10
DDAP9
DDAP8
DDAP7
DDAP6
DDAP5
DDAP4
DDAP3
DDAP2
DDAP1
DDAP0
DDAN15
DDAN14
DDAN13
DDAN12
DDAN11
DDAN10
DDAN9
DDAN8
DDAN7
DDAN6
DDAN5
DDAN4
DDAN3
DDAN2
DDAN1
DDAN0
LVDS Differential DataBus DDA
(To Mustang DMD)
Video Inputs From Scalar
RGB 888 Format (24bits)
D
C
B
A
D
C
B
A
TP43
VOUT_BV[7..0]
VOUT_BV7
VOUT_BV6
VOUT_BV5
VOUT_BV4
VOUT_BV3
VOUT_BV2
VOUT_BV1
VOUT_BV0
N29
N28
N27
N26
M28
M27
L28
M26
L29
L27
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
TP44
VOUT_RU[7..0]
VOUT_RU7
VOUT_RU6
VOUT_RU5
VOUT_RU4
VOUT_RU3
VOUT_RU2
VOUT_RU1
VOUT_RU0
T28
T29
R26
R27
R28
R29
P29
P28
P27
P26
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
LVDS Differential DataBus DDB
(To Mustang DMD)
DDBP[15..0]
DDBP15
AH22
AH21
AF18
AG18
AG17
AG16
AJ16
AG15
AH12
AH11
AJ11
AH10
AJ9
DDBP15
DDBP14
DDBP13
DDBP12
DDBP11
DDBP10
DDBP9
DDBP8
DDBP7
DDBP6
DDBP5
DDBP4
DDBP3
DDBP2
DDBP1
DDBP0
DDBN15
DDBN14
DDBN13
DDBN12
DDBN11
DDBN10
DDBN9
DDBN8
DDBN7
DDBN6
DDBN5
DDBN4
DDBN3
DDBN2
DDBN1
DDBN0
DDBP14
DDBP13
DDBP12
DDBP11
DDBP10
DDBP9
DDBP8
DDBP7
DDBP6
DDBP5
DDBP4
DDBP3
DDBP2
DDBP1
DDBP0
DDBN15
DDBN14
DDBN13
DDBN12
DDBN11
DDBN10
DDBN9
DDBN8
DDBN7
DDBN6
DDBN5
DDBN4
DDBN3
DDBN2
DDBN1
DDBN0
DDBN[15..0]
U26
U28
U27
VIO20/M_DACT
MACT
MVSYNCZ
MHSYNCZ
Video Syncs From Scalar MVSYNCZ
MHSYNCZ
W29
W27
V26
SACT
SVSYNCZ
SHSYNCZ
AH8
AF6
AJ5
V28
OSDACT
AF21
AG21
AJ19
AH19
AF17
AF16
AH16
AH15
AF13
AG12
AF12
AG11
AF11
AJ8
F29
E28
E29
E27
E26
D29
B27
A27
RMG7
RMG6
RMG5
RMG4
RMG3
RMG2
RMG1
RMG0
D24
C24
B24
D23
C23
B23
D22
C22
AG6
AH5
RMB7
RMB6
RMB5
RMB4
RMB3
RMB2
RMB1
RMB0
T1
T2
DCLKAP LVDS Differential DCLKA
DCKAP
DCKAN
DCLKAN
R3
R2
SCTRLAP LVDS Differential Series Control Bus A
SCAP
SCAN
SCTRLAN
C26
B26
A26
D25
C25
A25
B25
A24
RMR7
RMR6
RMR5
RMR4
RMR3
RMR2
RMR1
RMR0
AJ13
AF14
DCLKBP LVDS Differential DCLKB
DCLKBP
DCLKBN
DCLKBN
AG14
AH14
SCTRLBP LVDS Differential Series Control Bus B
SCBP
SCBN
SCTRLBN
AA27
AA28
RMHSOZ
RMVSOZ
H27
H26
G28
G27
G26
F28
F27
F26
J26
RMA7
RMA6
RMA5
RMA4
RMA3
RMA2
RMA1
RMA0
RMACT
DDP1010 Video Input and DMD Output
Y27
W26
HSYNCOZ
VSYNCOZ
Benq Corporation
DDP3P3V
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
AA29
FSD16
R70
(NC)
Y28
Y29
RMVSYNCZ
RMHSYNCZ
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
FSD16
T27
C28
0
48.J5802.S01
FILEDSYNC
SYNCVALID2
S01
SYNCVALID
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
3
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
VTERM (1.8V) Bulk Decoupling Caps
C207
C208
C209
C210
C211
0.1U Z
0.1U Z
0.1U Z
0.1U Z
0.1U Z
DDP3P3V
U10
MIC39100-1.8BS
R109
3.4KF
1
3
IN
OUT
C218
0.1U Z
C219
0.1U Z
C220
0.1U Z
C221
0.1U Z
C222
0.1U Z
R110
11.8KF
D
C
B
A
D
C
B
A
R6
R9
39.2F 39.2F
C223
4.7U Z
(1206)
C231
100U
6.3V
+
+
VTERM
C230
100U
6.3V
C226
0.1U Z
C227
0.1U Z
C228
0.1U Z
VTERM
1.8V
R108
110F
Termination Components
VREF_ASIC
VREF_RDRAM
U2A
DDP1010
C213
0.1U Z
C212
0.1U Z
RamBus Address Channel
RamBus Data Channel A
RamBus Data Channel B
RQ[7..0]
Rambus, JTAG and Customer Input
DQA[0..8]
V27
LAMPSTAT
LAMPLITZ
Y26
LAMPCTRL
DQB[0..8]
LAMPEN
RQ7
B11
RQ7
RQ6
RQ5
RQ4
RQ3
RQ2
RQ1
RQ0
AG2
C2
C12
C13
B13
D14
C14
A15
B15
PWRGOOD
STARTZ
RQ6
RQ5
RQ4
RQ3
RQ2
RQ1
RQ0
PWRGOOD
U8 K4R271669D
RESETZ
VREF_ASIC
RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7
DQB8
DQB7
DQB6
DQB5
DQB4
DQB3
DQB2
DQB1
DQB0
A11
B8
G1
F2
F6
F7
F1
E7
E6
E2
J1
J7
RD_VREF1
RD_VREF0
RD_AVDD0
RD_AVDD1
RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7
NC1
DQB7
DQB6
DQB5
DQB4
DQB3
DQB2
DQB1
DQB0
C225
0.1U Z
DDP2P5V
H2
H6
H7
H1
G2
G6
G7
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
B9
A4
D5
B5
A6
C6
B6
C7
B7
D8
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
D12
C194
0.1U Z
C195
68P J
C196
0.1U Z
R95
1K
VDRCG
VDRCG
U9
SIO1
SIO
CMD
SCK
J3
J5
A5
A3
SIO1
SIO0
CMD
SCK
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
C1
C2
C6
B1
B7
B6
B2
A7
A1
CDCR83
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
NC2
R94
110F
E4
C29
J4
TDO2
DDP2P5V
JTAG is inactive for normal operation
TRSTZ
TCK
2
7
6
REFCLK
SYNCLKN
PCLKM
CTM
CTM1_M
20
3
9
16
22
19
TMS2
CLK
VDD
VDD
VDD
VDD
NC
DQB8
DQB7
DQB6
DQB5
DQB4
DQB3
DQB2
DQB1
DQB0
CTM
CTMN
CFM
C19
A19
B19
C18
C17
B17
D16
C16
A16
E1
D1
C7
D7
D2
DQB8
DQB7
DQB6
DQB5
DQB4
DQB3
DQB2
DQB1
DQB0
CTM
CTMN
CFM
CFMN
VREF
TDO1
R98
R96
1K
R100
1K
15
14
MULT0
MULT1
R117
1K
R118
1K
CFMN
D27
B3
TMS1
56.2F
DDP3P3V
24
23
13
TDI
S0
S1
S2
C197
4.7P C
R104
39.2F
CLKTM
A2
J2
D5
A6
B3
C5
D3
E3
F5
G3
H3
J6
VCMOS
VCMOS
VDDA
P2P5V
P2P5V
P2P5V
P2P5V
P2P5V
P2P5V
GNDA
GND
GND
GND
GND
GND
GND
GND
GND
GND
AG1
C4
TRSTZ/IBMT_LT
TCK
C198
D6
B5
C3
E5
F3
G5
H5
4
5
8
17
21
GND
GND
GND
GND
GND
R101
10K
R102
10K
CLKFM
12
11
DRCGPDZ
PWRDNB
STOPB
0.1U Z
R99
56.2F
STOPZ
SCK
CMD
SIO
CFM
CFMN
CTM
R103
39.2F
C201
0.1U Z
B22
A22
D21
D10
C9
RD_SCK
RD_CMD
RD_SIO
DDP2P5V
1
VDDIR
ICEOENZ
ICTSENZ
A3
D28
AJ3
ICEOENZ
ICTSENZ
IBMT_RI
CTMN
CTMN1_M
18
10
RD_CFM
RD_CFMN
RD_CTM
RD_CTMN
CLKB
VDDIPD
R97
110F
C10
D11
C200
0.1U Z
CTMN
C199
0.1U Z
PCLKM1
R105
22
22
22
PCLKM
SCLKN
REFCLK
C21
D20
B21
PCLKM
SCLKN
W28
E2
POSTST
LSSDEN
SCLKN1
R106
R107
Direct Rambus Clock Generator (DRCG)
REFCLK1
REFCLK
P3P3V
VDRCG
RDRAM
L18
CDCR83 (DRCG) 3.3V Decoupling Caps
120 OHM
RDRAM Memory Control
C184
0.1U Z
C185
C186
C187
C188
0.1U Z
C189
68P J
C190
0.1U Z
C191
C192
C193
4.7U Z
0.1U Z
68P J
68P J
0.1U Z
68P J
(1206)
DDP2P5V
RDRAM VDD (2.5V) DECOUPING CAPS
C202
0.1U Z
C203
0.1U Z
C204
C205
C229
150U
6.3V
+
0.1U Z
0.1U Z
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
0
48.J5802.S01
S01
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
4
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
Screw Holes
Screw Holes
Optical Points
MARK1 MARK2 MARK3 MARK4 MARK5 MARK6 MARK7
OP OP OP OP OP OP OP
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
MARK9 MARK11 MARK12 MARK14 MARK17 MARK18 MARK20
OP OP OP OP OP OP OP
3
3
3
3
3
3
3
3
D
C
B
A
D
C
B
A
2
2
2
2
2
2
2
2
H1
H2
H3
H4
H5
H6
H7
H8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
MARK8 MARK10 MARK13 MARK15 MARK16 MARK19 MARK21
OP
OP
OP
OP
OP
OP
OP
MARK22 MARK23 MARK24
OP
OP
OP
DDP3P3V
U2D
DDP1010
C119 0.1U
C120 0.1U
C121 0.1U
C122 0.1U
C123 0.1U
C124 0.1U
C125 0.1U
C126 0.1U
C127 0.1U
C128 0.1U
C129 0.1U
C130 0.1U
C131 0.1U
C132 0.1U
C133 0.1U
C134 0.1U
Z
AE20
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
AE19
AE18
AE12
AE11
AE10
Y5
W5
V5
AJ29
AJ28
AJ23
AJ18
AJ12
AJ7
AJ6
AJ2
AJ1
AH29
AH28
AH25
AH2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M5
L5
K5
Y25
W25
V25
M25
L25
K25
AH1
AG27
AG3
AF26
AF10
AF4
AE25
AE21
AE17
AE13
AE9
C135 0.1U
Z
AE5
C136 0.1U
Z
DDP2P5V
U2E
DDP2P5V
B20
D15
B4
D18
D17
A17
B16
C15
B14
A13
B12
C11
B10
A9
RD_VDD5
RD_VDD3
RD_VDD0
RD_RSGND17
RD_RSGND16
RD_RSGND15
RD_RSGND14
RD_RSGND13
RD_RSGND12
RD_RSGND11
RD_RSGND10
RD_RSGND9
RD_RSGND8
RD_RSGND7
RD_RSGND6
RD_RSGND5
RD_RSGND3
RD_RSGND2
RD_RSGND1
C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
B18
A14
D13
A10
C5
RD_RGND10
RD_RGND7
RD_RGND6
RD_RGND4
RD_RGND0
A8
D9
D7
D6
C8
RD_RGNDC
A5
U7
MIC39100
DDP1010
P3P3V
4
2
GND
GND
1
IN
P3P3V
C180
4.7U
(1206)
DDP3P3V
Z
DDP2P5V
L15
L17
80 OHM
P2P5V_IN
C181
80 OHM
C182
0.1U
C183
0.1U
C115
0.1U
C116
0.1U
(1206)
C232
4.7U
(1206)
C233
4.7U
(1206)
C234
4.7U
(1206)
C235
4.7U Z
(1206)
+
C236
150U
4.7U
Z
Z
Z
Z
Z
Z
Z
Z
Benq Corporation
(1206)
6.3V
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
DDP3P3V Decoupling Caps
Size
<Size>
Rev.
PCB P/N
2.5V Regulator and Decoupling Caps
0
48.J5802.S01
S01
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
5
of
8
Approved By
ALEX HY TSENG
BEN CHEN
ANGEL HU
1
5
4
3
2
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
1
VCC
C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
C95 C96 C97 C98 C99 C100 C101 C102 C103 C104
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
VCC2
C113
1U Z
C114
1U Z
D
C
B
A
D
C
B
A
U6B
MUSTANG
DDAP[15..0]
DDAN[15..0]
P3P3V
VCC
L14
R52 R53 R54 R55 R56
10K 10K 10K 10K 10K
SCTRLAN
SCTRLAP
DCLKAN
DCLKAP
120 OHM
C111
0.1U Z
C112
0.1U Z
C107
2.2U Z
C108
2.2U Z
C109
2.2U Z
C110
2.2U Z
RV_A3
RV_A4
TP6
TP7
TP8
TP9
TP10
TPM0
TPM1
TPM2
U13
Y10
W11
TP0
TP1
TP2
READOUTA0
READOUTA1
V12
L5
READOUTA0
READOUTA1
MBRST[15..0]
B6
D6
B8
D8
SCPCLK
SCPDO
SCPDI
SCPCK
SCPDI
SCPDO
SCPEN
MBRST0
MBRST1
U5
N3
Y12
U15
P6
U6A
MBRST00
MBRST01
MBRST02
MBRST03
MBRST04
MBRST05
MBRST06
MBRST07
MBRST08
MBRST09
MBRST10
MBRST11
MBRST12
MBRST13
MBRST14
MBRST15
R57 33 SCPDOM
MBRST2
MBRST3
MBRST4
MBRST5
MBRST6
MBRST7
MBRST8
MBRST9
MBRST10
MBRST11
MBRST12
MBRST13
MBRST14
MBRST15
DMDSELZ
MUSTANG
C9
DMDRSTZ
DMD_RESETB
N5
U17
W13
W17
V16
N7
EVCC0
EVCC1
EVCC2
EVCC3
W9
V34
C33
A7
EVCC
EVCC
EVCC
EVCC
R58 R59 R60 R61
M4
W19
V18
M6
W7
V6
U7
FUSE_CLK
FUSE_DATA
PROG_FUSE_EN
TP11 TP12
0
0
0
0
L3
SCRLR
READOUTB0
READOUTB1
A9
D12
K4
SCR_CLR
READOUTB0
READOUTB1
R62
0
MUSTANG (HD2) DMD
RVB4
RVB3
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
DCLKBP
DCLKBN
Title
SCTRLBP
SCTRLBN
R63 R64 R65 R66 R67
10K 10K 10K 10K 10K
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
0
48.J5802.S01
S01
DDBP[15..0]
DDBN[15..0]
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
6
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
P3P3V
TP13
R1
1K
TP14
TP18
D
C
B
A
D
C
B
A
MBRST[15..0]
TP16
TP15
U1
RP1 10
5
6
7
8
RST15
RST14
RST13
RST12
RST11
RST10
RST9
MBRST15
MBRST14
MBRST13
MBRST12
MBRST11
MBRST10
MBRST9
56
57
42
58
79
77
74
72
69
67
64
62
4
3
2
1
SCP_CLK
SCP_DO
SCP_DI
SCP_CLK
SCPDI
SCPDO
SCPENZ
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT09
OUT08
DADSELZ
5
6
7
8
4
3
2
15
2
3
4
5
SR16STROBE
SR16MODE1
SR16MODE0
SR16SEL1
STORBE
MODE1
MODE0
SEL1
RST8
MBRST8
1
RP2
10
RP3
10
SR16SEL0
SEL0
RST7
RST6
RST5
RST4
RST3
RST2
RST1
RST0
MBRST7
MBRST6
MBRST5
MBRST4
MBRST3
MBRST2
MBRST1
MBRST0
39
37
34
32
29
27
24
22
5
6
7
8
4
3
2
1
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
P3P3V
TP19
16
17
18
19
SR16ADDR3
SR16ADDR2
SR16ADDR1
SR16ADDR0
A3
A2
A1
A0
P3P3V
P3P3V
5
6
7
8
4
3
2
1
DAD1000
TP17
R2
1K
R3
1K
R4
10K
45
44
DEV_ID1
DEV_ID0
RP4 10
43
DADINTZ
IRQZ
59
6
EXT_ARSTZ
RESETZ
OEZ
VCC2
SR16OEZ
78
73
68
63
38
33
28
23
49
VOFF_RAIL7
VOFF_RAIL6
VOFF_RAIL5
VOFF_RAIL4
VOFF_RAIL3
VOFF_RAIL2
VOFF_RAIL1
VOFF_RAIL0
VOFF
54
VCC
P12V
R5
52
51
V12_SWL1
V12_SWL0
C1
4.7U Z
(50V)
L1
C2
0.1U Z
C3
0.1U Z
10K
P12V_FLT
50
48
11
V12_3
V12_2
V12_1
120 OHM
C4
0.1U Z
C5
0.1U Z
C6
0.1U Z
C7
0.1U Z
C8
4.7U Z
(50V)
V5REG
80
71
70
61
40
31
30
21
47
VBIAS_RAIL7
VBIAS_RAIL6
VBIAS_RAIL5
VBIAS_RAIL4
VBIAS_RAIL3
VBIAS_RAIL2
VBIAS_RAIL1
VBIAS_RAIL0
V5REG
76
75
66
65
36
35
26
25
VRST_RAIL7
VRST_RAIL6
VRST_RAIL5
VRST_RAIL4
VRST_RAIL3
VRST_RAIL2
VRST_RAIL1
VRST_RAIL0
C9
0.22U M
(0805)
VBIAS
C11
--> (1U--> 0.22U) for more working margin
C12
0.1U Z
C10
4.7U Z
(50V)
0.1U Z
9
VBIAS
VRST
VBIAS_SWL
L2
22UH
8
13
VBIAS_SWL
VRST
D1
MBR0540T1
VRST_SWL
C15
C13
C14
4.7U Z
(50V)
0.1U Z
0.1U Z
VBIAS_LHI
10
12
VBIAS_LHI
VRST_SWL
L3
22UH
C16
10U
+
16V
DAD1000
Benq Corporation
Project Code
Model Name
OEM/ODM Model Name
NA
HT720G
99.J5877.001
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
0
48.J5802.S01
S01
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
7
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
P12V
P5V
SSI_VDD
V12A
L10
D8 RB051L-40
2
P12V
P5V
1
P12V
120 OHM
D2
D3
C37
1U Z
(0805)
C38
4.7U Z
(1206)
C39
1U Z
C40
1U Z
C41
4.7U Z
(3A, 40V)
(4.6x2.6)
(ROHM)
C42
0.1U Z
C43
0.1U Z
C44
0.1U Z
C45
0.1U Z
C46
0.1U Z
C47
0.1U Z
P12V_P
D9
D
C
B
A
1
2
1
2
D
C
B
A
C62
0.1U Z
(0805) (0805) (1210)
C58
+
15V,1.5W,5%
10U K
(83.3R002.08P)
R30
300
(1/8W)
(1SMB5929BT3)
(ONSEMI)
(83.15R03.03D)
BAT54SW
PUMPN2 PUMPN1
BAT54SW
TP5
35V
SSI_VDD
P12V
TP3
TP4
(80.10623.141)
V12A
C59
0.1U Z
C60
0.1U Z
C61
0.1U Z
V12A
4
2
C48
0.01U K
C49
0.01U K
Q5B
D4
BAT54SW
7
8
U13
3
11
10
9
5
MTRCLK
MTRDATA
MTRSELZ
SCLK
SDATA
SDEN
SWG
PUMPZ
PUMP
CP
6
7
8
PUMPZ
PUMP
CP
Q5A
FDS6930A
64
MTRPWM
PWMIN
4
PW
WHSD
WLSD
R35 100
38
37
36
35
34
33
61
53
52
SUM
AIN
ADUT
ERRN
ERR
PW
WHSD
WLSD
R36 AIN
1K
AOUT
ERRN
R37 ERR
1K
Q6B
D5
BAT54SW
PV
VHSD
VLSD
R38 100
R39 100
62
55
54
7
8
PV
VHSD
VLSD
DDP3P3V
U12
3
SOUT
200 OHM
24
2
RSV
L11
RSV
SSI_VDD
PU
UHSD
ULSD
63
57
56
PU
UHSD
ULSD
MDY1A
MDY2A
MDY1
19
15
14
PRG
PRI
PREG
SSI_VDD
Q6A
FDS6930A
1
5
NC
A
VCC
R68
4.7K
200 OHM
20K2002004
J4
L12
L13
RSM
CRH
2
3
58
44
2
4
SSI-32H6742T
MTRRSTZ
RSM
SGND
CRH
MDY2
18
17
16
NRG
NRC
NREG
C50
120P J
SSI_AMUX
TP24
R69
1K
PORZ
Q7B
4
GND
Y
1
2
3
4
D6
BAT54SW
200 OHM
41
3
4
7
8
AMUX
DMUX
CCLK
TP20
R71
10M
R72
10M
R73
10M
MDY3A
MDY3
32
31
3
MTRDMUX
TP25
ISET
GLS
CCLK
74LVC1G07
SSI_VDD
2
Motor Drive
20
49
26
23
25
RETZ
PORZ
GPA
VCMA
GNA
FDS6930A
Q7A
RSV
R40
2.74KF
C51
100P J
R41
3.3K
RSM
39
40
42
43
29
27
28
PWNSB
PMWLSB
VREFIN
2XVREF
GPB
VCMB
GNB
VREFIN
2XVREF
R42
NC_R1206
R43
R44
R45
NC_R0805 NC_R0805 NC_0805
R46
R47
R48
1
R49
2.26KF
1
1
13
DGND
12
FP
C52
0.1U Z
(1206)
(0805)
(0805)
(0805)
(0805) (0805)
(0805)
TP23
C/A
C/A
3
3
TP21
SSI_VDD
P45
SOT-323
SOT-323
1
A
2
C
1
A
2
C
TP22
SSI_RC
VMAG
1
2
R50
3K
D7
1N4148
R51
150K
C53
0.1U Z
(1206)
C54
330P J
C55
270P J
(0805)
C56
2.2U Z
C57
2700P K
SSI COLOR WHEEL DRIVE CIRCUIT
Benq Corporation
Project Code
Model Name
OEM/ODM Model Name
NA
HT720G
99.J5877.001
Title
DMD BOARD
PCB Rev. Document Number
99.J5877.R22-C3-304-002
Size
<Size>
Rev.
PCB P/N
0
48.J5802.S01
S01
Tuesday, January 14, 2003
Prepared By
Date:
Sheet
Reviewed By
8
of
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
+5VA
+3VA
+3VA
+5VA
+V_DAC
+V_DAC
OP_A[0..23]
OP_A16
OP_A17
OP_A18
OP_A19
OP_A20
OP_A21
OP_A22
OP_A23
R14
R15
R16
R17
R18
R19
R20
R21
10IN_OP_A16
10IN_OP_A17
10IN_OP_A18
10IN_OP_A19
10IN_OP_A20
10IN_OP_A21
10IN_OP_A22
10IN_OP_A23
0
R1
R3
R2
51K
NC
C11
C12
C13
C14
C15
4.7U K
0.047U K0.047U K0.047U K0.047U K
D
C
B
A
D
C
B
A
RST_DAC R4 560
+V_DAC
C16
0.1U Z
C17
VREF
COMP
J4
6
1
7
2
8
3
9
4
10
5
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLACK
SYNC
VREF
COMP
IOR
IOR
IOG
0
0
0.1U Z
OP_A8
OP_A9
R22
10IN_OP_A8
10IN_OP_A9
10IN_OP_A10
10IN_OP_A11
10IN_OP_A12
10IN_OP_A13
10IN_OP_A14
10IN_OP_A15
OUT_R
OUT_G
R5
R6
OUT_RED
11
12
13
14
15
R23
R24
R25
R26
R27
R28
R29
OP_A10
OP_A11
OP_A12
OP_A13
OP_A14
OP_A15
OUT_GREEN
OUT_BLUE
IOG
ADV7123
U1
VAA
VAA
IOB
IOB
GND
GND
OUT_B
R7
0
10
11
12
R8
75
R9
75
R10
75
2022012015
OP_ENABLE
OP_ENABLE
+V_DAC R11
10K
OP_A0
OP_A1
OP_A2
OP_A3
OP_A4
OP_A5
OP_A6
OP_A7
R30
10IN_OP_A0
10IN_OP_A1
10IN_OP_A2
10IN_OP_A3
10IN_OP_A4
10IN_OP_A5
10IN_OP_A6
10IN_OP_A7
R31
R32
R33
R34
R35
R36
R37
+V_DAC
BAV99
DN1
3
3
BAV99
DN2
R38
10
OCLK_OUT_INPUT
OCLK_OUT
OP_VSYNC
OP_VSYNC
R12
R13
75
VSYNC_OUT
HSYNC_OUT
75
OP_HSYNC
OP_HSYNC
Optical Points
OP1
OP
OP2
OP
OP3
OP
OP4
OP
OP5
OP
OP6
OP
OP7
OP
Screw Holes
OP8
OP
OP9
OP
OP10
OP
OP11
OP
OP12
OP
OP13
OP
OP14
OP
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
5
4
9
8
7
6
3
3
3
3
3
3
2
2
2
2
2
2
H1
H2
H3
H4
H5
H6
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
HOLE-V8
Title
DMD BOTTOM BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-003
Rev.
PCB P/N
0
48.J5824.S02
Wednesday, January 15, 2003
Date:
Sheet
1
of
2
Prepared By
ANGEL HU
Reviewed By
Approved By
BEN CHEN
ALEX HY TSENG
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
OP_A[0..23]
J1
J2
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
1
2
4
6
OP_A23
OP_A21
OP_A19
OP_A17
OP_A15
OP_A13
OP_A11
OP_A9
OP_A22
OP_A20
OP_A18
OP_A16
OP_A14
OP_A12
OP_A10
OP_A8
OP_A23
OP_A21
OP_A19
OP_A17
OP_A15
OP_A13
OP_A11
OP_A9
OP_A22
OP_A20
OP_A18
OP_A16
OP_A14
OP_A12
OP_A10
OP_A8
3
5
7
9
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
D
C
B
A
D
C
B
A
OP_A7
OP_A6
OP_A7
OP_A6
OP_A5
OP_A4
OP_A5
OP_A4
OP_A3
OP_A2
OP_A3
OP_A2
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
OP_A1
OP_A0
OP_A1
OP_A0
(CLK_OUT)
(OP_ENABLE)
(CLK_OUT)
(OP_ENABLE)
OCLK_OUT
OP_HSYNC
OP_VSYNC
LAMPLITZ
OCLK_OUT
OP_ENABLE
SDA
OP_HSYNC
OP_VSYNC
LAMPLITZ
OCLK_OUT
OP_HSYNC
OP_ENABLE
SDA
OP_ENABLE
OP_VSYNC
(For HD2)
(For HD2)
SCL
DLP_RESETZ
POWERON
SCL
DLP_RESETZ
POWERON
POWER
Ballast_Ctrl
(For HD2)
(For HD2)
PWRGOOD
+3VA
PWRGOOD
+3VA
+3VS
+3VA
+5VS
(For HD2)
(For HD2)
SYNCVALID
Ballast_Ctrl
SYNCVALID
+5VA
+5VA
+12VA
+12VA
+5VA
20C1001100
20C1001100
L4
+3VA
3VA
500 OHM
(1206)
C7
22U
35V
+
C8
0.1U K
L3
J3
+5VS
5VS
(1206)
3VA
3VA
7
1
2
3
4
5
6
7
1
2
3
4
5
6
500 OHM
3VS
8
9
8
C6
0.1U K
C5
22U
35V
+
+
+
5VS
9
5VA
10
11
12
10
11
12
POWER
+12VA
L1
L2
+5VA
12VA
5VA
500 OHM
20E1006206
500 OHM
C2
0.1U K
(1206)
(1206)
C1
22U
35V
+
C4
0.1U K
C3
22U
35V
Benq Corporation
L5
+3VS
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
3VS
500 OHM
Title
DMD BOTTOM BOARD
(1206)
C9
22U
35V
C10
0.1U K
Size
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-003
Rev.
PCB P/N
<Size>
0
48.J5824.S02
Wednesday, January 15, 2003
Date:
Sheet
2
of
2
Prepared By
ANGEL HU
Reviewed By
Approved By
BEN CHEN
ALEX HY TSENG
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
120-Pin B2B Connectors
Graphics_ADC_AD9883
D_INA[0..23]
D_INA[0..23]
D_INA[0..23]
D_VSYNC
D_HSYNC
DIN_CLK
D
C
B
A
D
C
B
A
D_VSYNC
D_HSYNC
DIN_CLK
D_VSYNC
D_HSYNC
DIN_CLK
Y /R
PB/G
PR/B
Y/R
PB/G
PR/B
Trigger/3D/Thermal/RS232
+5VS
+12VA
+5VS
DVI_PDO
DVI_PDO
VSYNC
H SYNC
VSYNC
HSYNC
SDA
SCL
SDA
SCL
SDA
SCL
+5V_AD +3VD
IR
IR
IR
+12VA
+3VD
+5V_AD
DVI_CLK
TRIGGER
TRIGGER
TRIGGER
3_Graphics ADC AD9883
DVI
CPU_TXD0
CPU_RXD0
Graphics_Inputs
DVI_PDO
PC_VS
PC_HS
PC_GREEN
PC_RED
PC_BLUE
PC_VS
PC_HS
PC_GREEN
PC_RED
PC_VS
PC_HS
PC_GREEN
PC_RED
PC_BLUE
+5V_AD
+5V_AD
PC_BLUE
SPAREI
SPAREO
MUX_SEL_Q
DVI_SCDT
MUX_SEL_Q
MUX_SEL_Q
MUX_SEL_Q
DVI_SCDT
DVI_SCDT
+5V_MUX
+5V_AD
D_HSYNC
D_VSYNC
+3VD
+5V_MUX
YpYcG
PbCbB
YpYcG
PbCbB
PrCrR
+5V_AD
+3VD
6_Trigger/3D/Thermal/RS232
D_INA[0..23]
PrCrR
DVI_ACTDATA
DVI_ACTDATA
DVI_ACTDATA
8_DVI INPUT&RECEIVER
MUX_SEL_P
MUX_SEL
1_Graphics Inputs
Video Inputs
Video Decoder SAA7118E
DI_IN[2..9]
DI_27M_CLK
YpYcG
PbCbB
DI_IN[2..9]
DI_27M_CLK
DI_IN[2..9]
DI_27M_CLK
DI_VSYNC
DI_HSYNC
DI_VSYNC
DI_HSYNC
DI_VSYNC
DI_HSYNC
MUX_BUFFER
MUX_BUFFER
+5V_MUX
PrCrR
Y1
Y_RCA
Y1
SDA
SCL
SDA
SCL
Cb_RCA
Cr_RCA
CB1
CB1
+5V_MUX
+5V_AD
CR1
COMPOSITE
CR1
COMPOSITE
COMPOSITE
Y
Y
C
Y
C
RESET_DEC
RESET_DEC
RESET_DEC
C
+5V_AD
+5V_AD
CPU_TXD0
CPU_RXD0
2_Video Inputs
+3VD
+3VD
+5V_AD
+5V_AD +12VA
5_Video Decoder SAA7118E
MUX_SEL
+3VD +5VS
MUX_SEL_P
MUX_BUFFER
+3VD
+5VS
Benq Corporation
MUX_BUFFER
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
MUX_SEL
MUX_SEL_P
+5V_AD
+12VA
Title
CONNECTOR BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
7_120Pin B2B Connector
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
1
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
5
4
3
2
1
-5V_RGB
-5V_RGB
C135
10UF/16
2
U16
NC
CAP+
GND
+5V_AD
1
2
3
4
8
7
6
5
V+
OSC
LV
CAPP+
1
CAPP-
C22
0.1UF
C23
0.1UF
C24
0.1UF
+5V_AD
CAP- VOUT
+5V_AD
ICL7660A
C136
10UF/16
L_Y_G
L_Pb
L_Pr
+
D1
D2
D3
BAV99
BAV99
BAV99
C18
0.1UF
C19
0.1UF
-5V
D
C
B
A
D
C
B
A
3
3
3
-5V
C1
10UF/16
2
U1
+5V_AD
1
2
3
4
8
7
6
5
NC
CAP+
GND
CAP- VOUT
ICL7660A
V+
OSC
LV
CAP+
1
J1
CAP-
C15
0.1UF
C16
C17
0.1UF
0.1UF
L2
R112 18
6
7
GND
Y_Y_G
YpYcG
PbCbB
C4
1
2
3
4
5
1
1
2
2
YpYcG
PbCbB
PrCrR
1
2
3
4
5
+
10UF/16
FCB3216K
L3
GND
GND
R113
18
18
Pb_Cb_B
FCB3216K
L4
+5V_MUX
8
R114
L1
+5V_MUX
Pr_Cr_R
+5V_AD Z1000/100MHZ
1
2
+5V_AD
FCB3216K
9
GND
GND
L5 FCB3216K
2
C2
0.1UF
C3
C5
0.1UF
C6
C7
0.1UF
C8
0.1UF
C9
0.1UF
C10
0.1UF
C11
C12
0.1UF
C13
0.1UF
C14
0.1UF
0.1UF
0.1UF
HS_B
0.1UF
1
1
BNC_HS
10
For AD8183
VS_B
2
BNC_VS
L6 FCB3216K
BNC_5_IN_1
C137
0.1UF
C138
C139
0.1UF
R1
56
R2
56
R3
56
R4
4.7K
R5
4.7K
0.1UF
C140
C141
C142
0.1UF
0.1UF
0.1UF
+5V_MUX
+5V_AD
+5V_MUX
D4
D5
BAV99
BAV99
U2
3
3
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
O_R
O_G
O_B
IN0A
DGND
VCC
OE
MUX_SEL
OUT_Y/R
OUT_PB/G
OUT_PR/B
MUX_SEL
IN1A SEL A/B
GND
IN2A
VCC
VEE
IN2B
GND
IN1B
VCC
OUT0
VEE
OUT1
VCC
R6
75
1
2
Y/R
R7
1
75
2
PB/G
PR/B
O_COMP_CR
O_COMP_CB
O_COMP_Y
R8
1
75
2
OUT2
VEE
+5V_AD
10
11
12
GND DVCC
IN0B VCC
-5V
AD8183
R9
1K
This MUX is for seletion between
BNC_YPbPr and DSUB_BNC_RGB
+5V_MUX
U3
1
2
3
4
5
6
7
8
9
24
23
L_Y_G
IN0A
DGND
VCC
OE
MUX_SEL_P
22
21
20
19
18
17
16
15
14
13
L_Pb
L_Pr
MUX_SEL_P
IN1A SEL A/B
GND
IN2A
VCC
VEE
IN2B
GND
IN1B
VCC
OUT0
VEE
OUT1
VCC
O_G
O_B
O_R
PC_RED
PC_BLUE
OUT2
VEE
+5V_AD
10
11
12
GND DVCC
IN0B VCC
PC_GREEN
AD8183
-5V_RGB
R10
10K
This MUX is for seletion between
BNC-RGB and DSUB_RGB
+5V_MUX
C25
0.1UF
U4
7
2
5
12
9
1
14
3
6
11
8
13
10
GND
A0
A1
A2
A3
OE0
OE1
VCC
O0
O1
O2
O3
OE2
OE3
O_HS
R11
75
1
2
HSYNC
BNC_HS
BNC_VS
PC_HS
O_VS
MUXPP
R12
1
75
2
PC_VS
VSYNC
MUX_SEL_Q
R73
1
0
4
2
+5V_MUX
74126(73.74126.0HB)
R13
5.1K
1:BNC-HV
OUT
0:DSUB-HV
OUT
SEL_HV
R14 1K
Q1
2N3904
SEL
1
MUX_SEL_P
Benq Corporation
Project Code
Model Name
OEM/ODM Model Name
NA
R15
10K
HT720G
99.J5877.001
Title
2N3904
3_C
CONNECTOR BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
2
8
Approved By
1_B 2_E
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
3
2
1
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
1
L39
L40
42 OHM
42 OHM
+5V_AD
D11
J3
BAV99
RCA-JACK
1
2
+5V_AD
The voltage level of CB/CR is
+0.35~-0.35 , add one diode
to prevent uncertain 'ON'
error
L41 42 OHM
D
C
B
A
D
C
B
A
L13
+5V_AD
D13
OUT_COMP
R21
18
1
1
2
1
2
COMPOSITE
FCB3216K
(open)
C144
0.1UF
D12
D14
R22
56
BAV99 BAV99 BAV99
C143
0.1UF
3
3
3
D15
BAV99
(open)
D16
BAV99
1
2
+5V_AD
ERRORON1
2
1
L14
ERRORON2
OUT_YY
SVIDEO_Y
R23 18
1
2
1
2
Y
FCB3216K
L15
(open)
C146
0.1UF
CRR
Cr
R24
1
18
2
3
4
1
2
CR1
3
4
C145
0.1UF
5
6
5
6
FCB3216K
R25
56
(open)
R26
56
C149
0.1UF
C150
0.1UF
J5
2
(open)
(open)
J4
S-VIDEO
2
4
6
1
3
5
1
3
5
D17
BAV99
L16
R27
1
2
+5V_AD
Cb
CBB
18
2
1
2
1
CB1
4
6
L17
18
2
FCB3216K
OUT_CC
SVIDEO_C
R28
1
1
2
C
FCB3216K
C151
0.1UF
C152
0.1UF
R29
56
(open)
(open)
C148
0.1UF
R30
56
RCA 3 IN 1
(open)
(open)
C147
0.1UF
+5V_AV
L18
Y CC
Y C
R31
1
18
2
1
2
Y1
FCB3216K
U5
Y CC
CBB
CRR
R124
R125
R126
0
0
0
YCC_U5
CBB_U5
CRR_U5
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
IN0A
DGND
VCC
OE
R35
56
C153
0.1UF
C154
0.1UF
MUX_BUFFER
O_COMP_Y
IN1A SEL A/B
GND
IN2A
VCC
VEE
IN2B
GND
IN1B
GND
IN0B
VCC
OUT0
VEE
OUT1
VCC
OUT2
VEE
DVCC
VCC
MUX_YP
MUX_PB
MUX_PR
R36
0
0
0
1
2
2
2
(open)
(open)
R37
1
O_COMP_CB
O_COMP_CR
L_Pr
R38
1
+5V_AD
10
11
12
L_Pb
L_Y_G
AD8183
-5V_AV
R70 R71 R72 R39
56 56 56 1K
This MUX is BUFFER of
Composite and
S-Video
(open) (open)
(open)
+5V_MUX
Open if -5V is not necessary
-5V_AV
+5V_AV
+5V_MUX
-5V_AV
L19
Z1000/100MHZ
+5V_AD
C26
10UF/16
U6
+5V_AD
1
2
3
4
8
+
C27
10UF/16
+
NC
CAP+
GND
V+
OSC
LV
CAPP+
2
1
7
6
5
Benq Corporation
C29
C30
0.1UF
C31
0.1UF
C28
10UF/16
C32
0.1UF
C33
0.1UF
C34
0.1UF
C35
0.1UF
C36
0.1UF
C37
0.1UF
0.1UF
CAPP-
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
CAP- VOUT
ICL7660A
C38
+
10UF/16
Title
For AD8183
CONNECTOR BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
3
8
Approved By
ALEX HY TSENG
1
BEN CHEN
ANGEL HU
Download from Www.Somanuals.com. All Manuals Search And Download.
5
4
3
2
TP2
E1
5
4
3
2
1
1
1
1
E1 TP4
1
TP1
E1
TP3
E1
TP5
E1
TP7
E1
TP9
E1
TP11
E1
TP13
E1
1
1
1
1
1
1
1
1
TP6
E1
E1 TP8
1
1
1
TP10
E1
E1
TP12
1
(open)
(open)
(open)
(open)
TP14
E1
TP16
E1
CN1
22P
CN2
22P
CN3
22P
CN4
22P
D_INA[0..23]
TP15
E1
LP1 120 OHM
D
C
B
A
D
C
B
A
D_INA8
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
D_INA9
D_INA10
D_INA11
D_INA12
D_INA13
D_INA14
D_INA15
LP2 120 OHM
LP4 120 OHM
AD_R0
D_INA16
1
2
3
4
1
2
8
7
6
5
8
7
6
5
AD_R1
AD_R2
AD_R3
AD_R4
AD_R5
D_INA17
D_INA18
D_INA19
D_INA20
D_INA21
D_INA22
D_INA23
AD_R6
3
4
AD_R7
LP3 120 OHM
DATACK
TP17
E1
1
AD_CLK
D_HSYNC
HSOUT
R41
33
2
D_HSYNC
1
TP19
E1
TP18
E1
R42
1
1
SOGOUT
VSOUT
33
2
D_VSYNC
D_VSYNC
C39
47NF
Y /R
AD_RIN
Y/R
C40
0.1UF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TP20
E1
GND
G7
G6
G5
G4
G3
G2
G1
G0
GND
VDD
B7
B6
B5
B4
B3
B2
B1
B0
GND
GND
VD
+3VB_A2D
REF_BYPASS
REF BYPASS
SDA
SCL
SDA
SCL
SDA
SCL
C41
47NF
A0
PB/G
PR/B
AD_GIN
AD_BIN
PB/G
PR/B
RAIN
GND
VD
TP21 TP22
E1 E1
U7
+5V_ADDVI
VD
AD9883
+3VD
GND
SOGIN
GAIN
GND
VD
R116
IN0A
0
C42
47NF
VD
R115
0
U22
GND
BAIN
VD
U22_ADCLK
1
2
3
4
5
6
7
8
9
24
AD_CLK
HSYNC
VCC
OE
IN1A SEL A/B
23
22
21
20
19
18
17
16
15
14
13
DGND
DVI_PDO
DIN_CLK
GND
L30
30 OHM
(open)
GND
IN2A
VCC
VEE
IN2B
GND
IN1B
VCC
OUT0
VEE
OUT1
VCC
OUT2
VEE
OUTDINCLK
R43
220
R44
220
R45
220
C156
22P
C155
J
22P
J
CN6
22P
C43 0.1UF
<Spec>
<Spec>
10
11
12
For AD8185
GND DVCC
IN0B VCC
R117
0
U22_DVICLK
DVI_CLK
MIDSCV
R=75
C44
1NF
LP6 120 OHM
AD8183
AD_SOGIN
AD_B0
AD_B1
AD_B2
AD_B3
AD_B4
AD_B5
AD_B6
AD_B7
+3VC_A2D
D_INA0
D_INA1
D_INA2
D_INA3
+5V_AD
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
R46
1K
R118
0
TP23
E1
D_INA4
D_INA5
D_INA6
D_INA7
C178
0.1U
Z
LP5 120 OHM
VSYNC
TP24
H_SYNC
1
1
1
1
1
1
1
FLT
2
1
TP25
E1
R48
51K
R47
2.7K
C45
82NK 16V
-5V_ADDVI
TP26
E1
FILT
(open)
C46
8200P
K
-5V_ADDVI
TP27
E1
+5V_AD
U23
C188
TP28
E1
1
2
3
4
8
7
6
5
NC
CAP+
GND
V+
OSC
LV
U23_CAP
2
1
TP29
E1
U23_CAP-
10U
16V
CAP- VOUT
C187
0.1U
ICL7660S 5V
TP30
E1
Z
C189
10U
16V
+
E1
-5V_ADDVI
+5V_ADDVI
C179
0.1U
C180
0.1U
C181
0.1U
C182
0.1U
C183
C184
0.1U
C185
0.1U
C186
U8
LD1117/SOT
Z
Z
Z
Z
0.1U
Z
Z
Z
0.1U
Z
+3VD
+5V_AD
+3VB_A2D
3
2
+3VD
VIN
VOUT
+
C47
0.1UF
C48
0.1UF
C49
0.1UF
C50
0.1UF
C51
0.1UF
C52
0.1UF
C53
4.7UF/16
C55
C56
C57
0.1UF
C58
0.1UF
C59
0.1UF
C60
0.1UF
C61
0.1UF
C62
0.1UF
C63
0.1UF
C64
0.1UF
C54
10UF/16
0.1UF
0.1UF
Benq Corporation
+5V_AD
U9
LD1117/SOT
+3VC_A2D
C68
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
3
2
+5V_AD
VIN
VOUT
+
10UF/16
Title
C65
4.7U/16V
C66
C67
0.1UF
CONNECTOR BOARD
0.1UF
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
4
8
Approved By
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
Download from Www.Somanuals.c3om. All Manuals Search And Download.
2
1
5
4
3
2
1
TP31
E1
TP32
E1
TP33
E1
TP34
E1
D
C
B
A
D
C
B
A
SY IN
S_YIN
Y
SDA
SCL
C69
47NF
SCL
INT_A
TP35
E1
1
RESET
RTS0
RTS1
R49
33
RESET_DEC
TP36
E1
TP38
LLC2
LLC
TP37
E1
TP39
1
1
1
1
E1
E1
TP40
E1
TP41 TP42 TP43 TP44 TP45
E1
E1
E1
E1
E1
S_CIN
C
C70
47NF
XRV
XRH
XRDY
XDQ
XCLK
XPD0
XPD1
XPD2
XPD3
XPD4
XPD5
XPD6
XPD7
R50
R51
33
33
M13
J2
K1
K2
L3
D8
C7
A6
B7
A7
A8
B8
A9
B9
DI_VSYNC
DI_HSYNC
FSW
AI11
AI12
AI13
AI14
AI1D
AGND
AI21
AI22
AI23
AI24
AI2D
AI31
AI32
AI33
AI34
XRV
XRH
XRDY
XDQ
AI1C
AI1D
R52 33
2
DI_27M_CLK
1
DI_27M_CLK
XCLK
XPD0
XPD1
XPD2
XPD3
XPD4
XPD5
XPD6
XPD7
HPD0
HPD1
HPD2
HPD3
HPD4
HPD5
HPD6
HPD7
ITRI
IGP1
IGP0
IGPV
IGPH
ITRDY
IDQ
ICLK
IPD0
IPD1
IPD2
C71 47NF
K3
C2
G4
G3
H2
J3
H1
E3
F2
F3
G1
F1
L2
B1
D2
D1
E1
D3
P3
M1
M2
J4
H3
E4
C1
M3
K4
H4
F4
D4
L1
A10
B10
A11
C11
D14
E11
E13
E12
E14
F13
F14
G13
L12
K13
L14
K14
K12
N12
L13
M14
G14
G12
H11
H14
H13
J14
J13
K11
N6
AI2C
AI2D
C72 47NF
C73 47NF
TP46 TP47 TP48 TP49 TP50 TP51 TP52 TP53
E1 E1 E1 E1 E1 E1 E1 E1
DI_IN[2..9]
AI3C
AI3D
TP54
E1
AI3D
AGNDA
AI41
AI42
AI43
DI_IN2
DI_IN3
DI_IN4
DI_IN5
1
8
7
6
5
2
3
4
U10
SAA7118E
AI4C
AI4D
EXMCLR
PrCrR
AI44
AI4D
C75 47NF
RP7
47_RP
C74
47NF
TP55
E1
1
EXMCLR
AOUT
VSSA0
VSSA1
VSSA2
VSSA3
VSSA4
VDDA0
VDDA1
VDDA2
VDDA3
VDDA4
VDDA1A
VDDA2A
VDDA3A
VDDA4A
DI_IN6
DI_IN7
DI_IN8
DI_IN9
1
2
3
4
8
7
6
5
+3VE
RP8
47_RP
TP56
E1
IPD3
IPD4
IPD5
IPD6
IPD7
CLKEXT
ADP0
J1
G2
E2
CR1_IN
CR1
N8
C76
47NF
TP57
E1
PbCbB
+3VD
+3VD
C77
47NF
XTALI
TP58
E1
R53
820K
I2C BUS SLAVE ADDRESS:
0x42 - W,0x43 - R
X1
3
24.576MHZ
1
L20
NC_L1206
CB1_IN
CB1
C79
22PF
C78
47NF
L21
Z1000/100MHZ
C80
22PF
XTALA
L22
Z1000/100MHZ
C81
0.1UF
SOG_Y
C83
NC_C0603
TP59
E1
C82
47NF
YpYcG
C84
47NF
U11
LD1117/SOT
L23
Z1000/100MHZ
+3VE
+5V_AD
ANALOG SAA7118E
3.3V_7118
3
2
+5V_AD
VIN
VOUT
+
C86
+
C87
10UF/16
C85
4.7UF/16
C88
0.1UF
C89
0.1UF
C90
0.1UF
C91
0.1UF
C92
0.1UF
C93
0.1UF
C94
0.1UF
C95
0.1UF
C96
0.1UF
SOG_Y_IN
10UF/16
TP60
E1
C97
47NF
+3VD
DIGITAL SAA7118E
-
CORE
Y_ IN
Y1
+3VD
C98
47NF
C99
0.1UF
C100
0.1UF
C101
0.1UF
C102
0.1UF
C103
0.1UF
C104
0.1UF
Benq Corporation
TP61
E1
SOG_RCA
RAC_IN
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
C105
47NF
DIGITAL SAA7118E
-
PERIPHERAL CELLS
Title
CONNECTOR BOARD
COMPOSITE
C107
0.1UF
C108
0.1UF
C109
0.1UF
C110
0.1UF
C111
0.1UF
C112
0.1UF
C113
0.1UF
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
C106
47NF
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
5
8
Approved By
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
Download from Www.Somanuals.c3om. All Manuals Search And Download.
2
1
5
4
3
2
1
+12VA
Q2
L24
J6
F1
VOUT_TRIGGER
DR
TOUT_12V
1
2
1
2
3
4
8
7
6
5
1
2
3
+12VA
S
D
D
D
D
+5VS
S
S
G
VCC_IR
R54
47
PICOFUSE
FCB3216K
69.42001.021
+
C114
10UF/25
R55
R74
10K
SCD437
+
G
Si4431DY
C115
10UF/25
C116
0.1UF
D
D
C
B
A
C117
0.1UF
C118
4.7UF/16
C119
0.1UF
84.04431.037
47K
U12
3
2
1
VCC
GND
VOUT
GG
R56 1K
Q3
2N3904
TRIGGER
TRIG
1
TRIGGER
FCB3216K
L27
1:TURN ON
0:TURN OFF
FM6038TM2
R57
10K
2N3904
3_C
1_B 2_E
R58
130
IR
C
+5VS
J9
1
2
3
IR
20.D0049.103
TX1
RX1
J7
+5VS
1
1
2
2
+5VS
R59 NC_R1206
3
3
1
2
4
4
C121
0.1UF
C122
R60 NC_R1206
0.1UF
C123
0.1UF
D18
27V
D19
27V
1
2
R61 150/1206
2213008001
B
U14
1
2
1
16
C1+
V+
C1-
C2+
C2-
V-
VCC
GND
RXX1
RSV+
RSV-
2
3
4
5
6
7
8
15
14
13
12
11
10
9
TXX1
T1OUT
R1IN
RX
R62 150/1206
T1OUT
R1IN
C124
0.1UF
232_C2+
232_C2-
1
2
D20
27V
D21
27V
R1OUT
T1IN
T2OUT
R2IN
T2IN
C125
0.1UF
R2OUT
SP232
C126
47PF/50
C127
47PF/50
R68
1K
R69
1K
+5VS
R63
1K
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
A
CPU_TXD0
Title
CPU_TXD0
CONNECTOR BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
CPU_RXD0R64
100
PCB P/N
CPU_RXD0
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
6
8
Approved By
Download from Www.Somanuals.com. All Manuals Search And Download.
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
3
2
1
DI_IN[2..9]
D_INA[0..23]
Optical Points
D
D
C
B
A
OP1
OP
OP2
OP
OP3
OP
OP4
OP
OP5
OP
OP6
OP
OP7
OP
J8
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
1
2
3
4
5
6
7
8
DVI_SCDT
IR
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
1
2
3
4
5
6
7
8
9
OP8
OP
OP9
OP
OP10
OP
OP11
OP
OP12
OP
OP13
OP
OP14 OP15 OP16
OP
TRIGGER
OP
OP
MUX_SEL_P
CPU_RXD0
CPU_TXD0
9
MUX_SEL
D_VSYNC
+5VS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
MUX_BUFFER
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
+5VS
D_HSYNC
DIN_CLK
C128
0.1UF
D_INA23
D_INA22
D_INA21
D_INA20
H1
HOLE-V8
H2
HOLE-V8
D_INA19
D_INA18
D_INA17
D_INA16
1
1
1
1
1
1
1
D_INA15
D_INA14
D_INA13
D_INA12
C
B
A
D_INA11
D_INA10
D_INA9
D_INA8
D_INA7
D_INA6
D_INA5
D_INA4
H3
HOLE-V8
D_INA3
D_INA2
H4
HOLE-V8
D_INA1
D_INA0
DVI_PDO
93
94
95
96
97
98
99
94
95
96
97
98
99
DVI_ACTDATA
SCL
SDA
DI_IN8
DI_IN9
DI_IN6
DI_IN4
DI_IN2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DI_IN7
DI_IN5
DI_IN3
H5
HOLE-V8
H6
HOLE-V8
RESET_DEC
DI_HSYNC
DI_VSYNC
SPA8 R65
NC_R0603
2
1
SPAREI
DI_27M_CLK
SPA9 R66
1
0
2
MUX_SEL_Q
R67
1
NC_R0603
2
SPA7
SPAREO
+5V_AD
L25
5VA
H7
HOLE-V8
1
2
+5V_AD
FCB3216K
+
C129
0.1UF
C130
10UF/16
C131
0.1UF
AMP 120P D0.8
+5V_AD
U15
LD1117/SOT
+3VD
L26
+12VA
3
2
+3VD
VIN
VOUT
12VA
1
2
+12VA
FCB3216K
C132
0.1UF
C133
0.1UF
C134
10UF/16
Benq Corporation
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
Title
CONNECTOR BOARD
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
7
8
Approved By
Download from Www.Somanuals.com. All Manuals Search And Download.
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
3
2
1
+5V_AD
+3VD
+5V_AD
+3VD
R122
4.7K
R123
4.7K
R120
4.7K
R121
4.7K
2
3
DVI_SCL
DVI_SCL3V
Q5
BSN20
2
3
DVI_SDA
DVI_SDA3V
D
C
B
A
D
C
B
A
Q4
BSN20
LP7
120 OHM
D_INA[0..23]
R1
0
D_INA23
D_INA22
D_INA21
D_INA20
D_INA19
D_INA18
D_INA17
D_INA16
5
6
7
8
5
6
7
8
4
3
2
1
4
3
2
1
DVI_ACTDATA
R87 33
DVI_CLK
D_VSYNC
D_HSYNC
R2
R3
0
0
+3VD
LP8
120 OHM
+5V_AD
+3VD
+5V_AD
R103
0
R105
(open)
0
(open)
D22
BAV99
D23
BAV99
D24
BAV99
D25
BAV99
D26
BAV99
D27
BAV99
3
3
3
3
3
3
R104
0
J10
R106
0
(open)
(open)
LP9
120 OHM
D2-
D1-
D0-
D2+
D1+
D0+
1
9
17
2
10
18
3
11
19
4
12
20
5
13
21
6
14
22
7
15
23
8
DVI_GREEN7
DVI_GREEN6
DVI_GREEN5
DVI_GREEN4
D_INA15
D_INA14
D_INA13
D_INA12
5
6
7
8
4
3
2
1
+5V_EDID
D38
+5V_AD
1N4148
(open)
LP10 120 OHM
1
2
2
51
25
QO2
QO3
QO4
QO5
QO6
QO7
OVCC
OGND
QO8
QE13
QE12
QE11
QE10
QE9
R79
51K
R80
4.7K
R81
75
R82
75
R83
75
R84
4.7K
+5V_EDID
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DVI_GREEN3
DVI_GREEN2
DVI_GREEN1
DVI_GREEN0
D_INA11
D_INA10
D_INA9
D_INA8
5
6
7
8
4
3
2
1
L34
D37
DVI_SCL
QE8
PC_5V
PC_5VIN
LP11 120 OHM
1
OGND
OVCC
QE7
DVI_BLUE7
DVI_BLUE6
DVI_BLUE5
DVI_BLUE4
D_INA7
D_INA6
D_INA5
D_INA4
5
6
7
8
4
42 OHM
1N4148
3
2
1
DVI_SDA
IDCK+
L28
QO9
QE6
QE5
QE4
QE3
QE2
QE1
QE0
PDO
42 OHM
+
C174
10U
16V
QO10
QO11
QO12
QO13
QO14
QO15
VCC
C175
0.1U
PC_V
U17
SII151B
PC_VS
Z
HOT_PLUG
DVI_BLUE3
DVI_BLUE2
DVI_BLUE1
DVI_BLUE0
D_INA3
5
6
7
8
4
3
2
1
16
24
D_INA2
D_INA1
D_INA0
IDCK-
L29 42 OHM
PC_R
PC_B
PC_RED
PC_BLUE
C1
C3
C5
C4
C2
LP12 120 OHM
DVI_SCDT
DVI_PDO
GND
SCDT
STAG_OUT
VCC
SG_OUT
L31
QO16
QO17
QO18
QO19
QO20
QO21
QO22
PC_H
PC_G
L33 42 OHM
42 OHM
L32
42 OHM
PC_HS
PC_GREEN
GND
PIXS
ST
PD
10K R98
2021008024
+5V_AD
HS_DJTR R101
0
RESETZ_DVI
HS-DJTR
(open)
R100
0
+3VD
R75
NC_R0603
D28
BAV99
D29
BAV99
D30
BAV99
D31
BAV99
D32
BAV99
D33
BAV99
D34
BAV99
D35
D36
R85 1.5K
(open)
ST
3
3
3
3
3
3
3
3
BAV99
3
BAV99
PD
+3VD
R96
10K
R86 1.5K
+3VD
R102
0
DVI_SDA3V
(open)
R110
180
U21
EDID_VCC
3
1
VDD
RES
2
GND
+3V_ADVI
+3V_PDVI
R111
100K
RESETZ_DVI
AME8500BEETAF29
L45
L44
42 OHM
42 OHM
D2+
D2-
D1+
D1-
D0+
D0-
IDCK+
IDCK-
R78
390
R99
0
(OPEN)
C176
1U
DVI_SCL3V
Z
L43
L42
42 OHM
42 OHM
R76
1.5K
+3VD
+5V_EDID
+3VD
(open)
+3VD
+5V_AD
+3V_ADVI
U19
3
+3VD
R77
10K
R107
1K
R108
4.7K
R109
4.7K
U18
2
VIN
VOUT
1
2
3
4
8
NC
NC
NC
GND
VCC
WP
SCL
SDA
WP
7
6
5
DVI_SCL
DVI_SDA
C157
4.7U
C158
4.7U
C159
0.1U
C160
C161
0.1U
C162
0.1U
C166
0.1U
C167
0.1U
C168
0.1U
C169
0.1U Z
LD1117-3.3V
Z
Z
Z
0.1U
Z
Z
Z
Z
Z
Z
AT24C16 16K
+3V_PDVI
+5V_AD
C170
0.1U
C171
0.1U
C172
0.1U
C173
0.1U Z
Benq Corporation
U20
Z
Z
Z
Project Code
99.J5877.001
Model Name
HT720G
OEM/ODM Model Name
NA
3
2
VIN
VOUT
Title
CONNECTOR BOARD
C163
4.7U
C164
4.7U
C165
0.1U Z
LD1117-3.3V
Z
Z
Size
<Size>
PCB Rev. Document Number
S02 99.J5877.R22-C3-304-004
Rev.
PCB P/N
48.J5810.S02
0
Monday, February 17, 2003
Prepared By
Date:
Sheet
Reviewed By
of
8
8
Approved By
ALEX HY TSENG
BEN CHEN
ANGEL HU
5
4
3
2
1
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