4 Channel Input Buffer Board
Model SDAIBB
Document No. SDAIBB1300
This product designed and manufactured in Ottawa, Illinois USA
of domestic and imported parts by
International Headquarters
B&B Electronics Mfg. Co. Inc. USA
707 Dayton Road -- P.O. Box 1040 -- Ottawa, IL 61350
Phone (815) 433-5100 -- General Fax (815) 433-5105
1999 B&B Electronics
August 1999 B&B Electronics RESERVED. No part of this publication may be reproduced or transmitted in
any form or by any means, electronic or mechanical, including photography, recording, or any information
storage and retrieval system without written consent. Information in this manual is subject to change without
notice, and does not represent a commitment on the part of B&B Electronics.
B&B Electronics shall not be liable for incidental or consequential damages resulting from the furnishing,
performance, or use of this manual.
All brand names used in this manual are the registered trademarks of their respective owners. The use of
trademarks or other designations in this publication is for reference purposes only and does not constitute an
endorsement by the trademark holder.
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Chapter 1: General Information
Introduction
The SDAIBB is a data acquisition module with four input buffers
with selectable gains and selectable output offsets. The gain can be set
from 1 to 1000 with a single resistor change. Gains of 1 and 22.28 are
provided. The output can be offset by the provided 0 V for positive ended
systems, by the provided 2.5 V for plus/minus applications, or by a user
selected amount that is brought in on terminal blocks or solder pads. The
SDAIBB is designed to amplify single ended or differential signals in the
range of –0.15 to +5.0 V into +0.01 to +5.0 V signals that are compatible
with the B&B line of data acquisition products. Sensor and power supply
connections are made through terminal blocks or solder pads. A/D
connections are made through DB25 connectors and are designed to
connect to many of the B&B data acquisition products. All lines on the
DB25 connectors are carried through, allowing boards to be “stacked” for
expanding the number of channels or bringing other lines in or out. Three
SDAIBB boards will fill all 11 channels of the 232SDAxx or 485SDAxx
modules.
Specifications
Number of Channels
Gain
4
1 to 1000
1 and 22.28 provided
0.35%
25 ppm
200 µV
2 µV/°C
2 GΩ, 2pF
Max. Gain Error
Max. Gain Drift
Max. Input Offset Voltage
Max. Input Offset Voltage Drift
Input Impedance
Input Voltage Range
Gain = 1
-0.15 to +5.00 V
-0.15 to +4.60 V
Gain > 1
Output Voltage Range
Gain = 1
0.01 to 5.00 V
0.01 to 4.95 V
Gain > 1
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Power Supply
Input Voltage
Single Module
Three Modules
Input Current
10 to 30 VDC
12 to 30 VDC
8 mA max. per Module
Current Draw From Precision 5 V 0.5 mA per board
Max. Current Throughput
1 A
Connections
Analog Input
Analog Output
Terminal Blocks/Solder Pads
DB25 Male Connector and
DB25 Female Connector
Terminal Blocks/Solder Pads
Pins 2 and 7 of the Male
DB25
Power
Environment
Operating Temperature
Storage Temperature
-40 to +85 °C
-65 to +125 °C
5.6 x 2.75 in.
14 x 7 cm
Size
2
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Chapter 2: Connections
Power Supply Connections
A single SDAIBB board requires 8 mA at 10 to 30 VDC, and can be
brought directly into the board through terminal blocks or solder pads
marked POWER and GND or passed from another board connected to the
male side of the board. See Figure 1 for a system where the power is
brought directly onto the board. When passing power through from
another board, POWER is carried through on pin 2 and GND is carried
through on pin 7. Powers flows in on the male DB25 connector and out on
the female DB25 connector with a 0.5 VDC drop across the board. This
allows multiple boards to be powered with a single power supply by
cascading them. See Table 4 for a list of B&B data acquisition products
that carry power through on pins 2 and 7. Using these devices, you can
power an entire system with a single power supply as shown in Figure 2.
P o we r S u p p ly
P o rt P o we re d
Figure 1: Port Powered SDA and Powered Board
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2 3 - 2 S R
M O D E L 2 3 2 S D A 1 0
E L U D O M
I O I T I S U Q C A T A D
N
0 5 3 1 6 s i o n i l l I
,
a
w a t t
O
I/O PORT
R8
JP9
USER 1
22.28/
JP10
JP4
GAIN
JP11
JP8
0V
OUT.
OFF.
22.28/USER
2.5V
1
JP2
GAIN
POWER
GND
TB5
R2
0V
OUT.
OFF.
2.5V
JP6
TB2
TB4
IN-
OUT
OFF
IN+
GND
GND
IN+
IN-
OFF
OUT
B
A
D
JP5
0V
OUT.
OFF.
JP7
0V
OUT.
OFF.
2.5V
2.5V
OUT
OFF
IN-
TB3
IN+
GND
GND
OFF
C
IN+
IN-
OUT
TB1
JP3
JP1
GAIN
1
GAIN
22.28/
USER
22.28/
USER
1
R1
R7
R8
JP9
USER 1
22.28/
JP10
JP4
GAIN
JP11
JP2
JP8
0V
OUT.
OFF.
22.28/USER
2.5V
1
GAIN
POWER
GND
TB5
TB4
R2
0V
OUT.
OFF.
2.5V
JP6
TB2
IN-
OUT
OFF
IN+
GND
GND
IN+
IN-
OFF
OUT
B
D
JP5
0V
OUT.
OFF.
JP7
0V
OUT.
OFF.
2.5V
2.5V
OUT
OFF
IN-
TB3
IN+
GND
GND
OFF
C
A
IN+
IN-
OUT
TB1
JP3
JP1
GAIN
GAIN
22.28/
USER
1
22.28/
USER
1
R1
R7
R8
JP9
USER 1
22.28/
JP10
JP4
GAIN
JP11
JP2
JP8
0V
OUT.
OFF.
22.28/USER
2.5V
1
GAIN
POWER
GND
TB5
TB4
R2
0V
OUT.
OFF.
2.5V
JP6
TB2
IN-
OUT
OFF
IN+
GND
GND
IN+
IN-
OFF
OUT
B
D
JP5
0V
OUT.
OFF.
JP7
0V
OUT.
OFF.
2.5V
2.5V
OUT
OFF
IN-
TB3
IN+
GND
GND
OFF
C
A
IN+
IN-
OUT
TB1
JP3
JP1
GAIN
GAIN
22.28/
USER
1
22.28/
USER
1
R1
R7
Figure 2: Single Power Supply System with 11 Channels Supported
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Input Voltage Connections
The SDAIBB can receive signals in the range of –0.15 to +5 VDC
when set to unity gain, and –0.15 to +3.5 VDC when set to any other gain.
Note: This voltage reading is taken from GND on the SDAIBB to
not
Input+ and GND to Input- voltages. It is
the differential voltage
Signals are brought into the buffer by terminal
from Input- to Input+.
blocks or solder pads. The terminal blocks are labeled Input+, Input-,
GND, and Output Offset. See Figures 3, 4, and 5 for typical input
configurations. The voltage that will be amplified is the reading taken from
Input- to Input+. GND is connected to the ground of the SDAIBB and is
provided for making a common reference for the SDAIBB and the input
device. The Output Offset is an input that shifts the output of the SDAIBB.
This feature is discussed further in Chapter 3, Output Offset.
OUT
OFF
GND
IN+
IN-
Figure 3: Differential Signal with GND
OUT
OFF
GND
S ig n a l
IN+
G N D
IN-
Figure 4: Single Ended Signal
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OUT
OFF
GND
IN+
IN-
Figure 5: Floating Differential Signal
Output Voltage Connections
The SDAIBB outputs voltages from +0.1 to +5.0 VDC at unity
gain, and +0.1 to +4.95 VDC at any other gain. All lines are carried
straight through on the DB25 connectors, allowing for the addition of extra
channels by connecting on another board.
The SDAIBB output connections are jumper selectable to line up
with the channels of the B&B line of SDAxx data acquisition devices.
When the 4-position shunt is set to JP9, input buffer A is connected to
channel 0 on pin 8, B is connected to channel 1 on pin 9, C is connected to
channel 2 on pin 10, and buffer D is connected to channel 3 on pin 11.
Setting the 4-position shunt to JP10 connects the buffers to channels 4 to 7
(pins 12, 13, 21, and 22 respectively), and setting the shunt to JP11
connects the buffers to channels 8 to 10 (pins 23 to 25). See Table 1 for a
list of the connections when the jumper is on JP9,
Table 2 for when the jumper is on JP10, and Table 3 for when the
jumper is on JP11.
Note: When the 4-position jumper is on JP11,
buffer D is not connected to any pins on the DB25 connector.
For a listing of which modules the SDAIBB can connect to and
which channels are compatible on each module, see Table 4.
6
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Table 1: Connections when the 4-position shunt is on JP9
Pin Connection Pin Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
---
Power
---
---
---
14
15
16
17
18
19
20
21
22
23
24
25
---
---
---
---
---
---
---
---
---
---
---
---
---
GND
A output
B output
C output
D output
---
---
Table 2: Connections when the 4-position shunt is on JP10
Pin Connection Pin Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
---
Power
---
---
---
---
GND
---
---
---
14
15
16
17
18
19
20
21
22
23
24
25
---
---
---
---
---
---
---
C output
D output
---
---
A output
B output
---
---
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Table 3: Connections when the 4-position shunt is on JP11
Pin Connection Pin Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
---
Power
---
---
---
---
GND
---
---
---
14
15
16
17
18
19
20
21
22
23
24
25
---
---
---
---
---
---
---
---
---
A output
B output
C output
---
---
---
Table 4: Models Compatible with SDAIBB
2.5V
Output
Offset
Channel Select
Jumper Connections
Supported
Power on
pins 2
and 7
Channels
Supported
Model
Available
485SDA10
485SDA12
232SDA10
232SDA12
232SPDA
232SPDACL
485SPDA
485SPDACL
232OPSDA
ADIO12
JP9, JP10, JP11
JP9, JP10, JP11
JP9, JP10, JP11
JP9, JP10, JP11
0-10
0-10
0-10
0-10
0-3
0-3
0-3
0-3
4 and 5
4-7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
JP9
JP9
JP9
JP9
*
JP9
JP9
No
No
No
No
ADIO10
4-7
Set the jumper for any position and use the solder pads on the DB25
connector to bring out connections for channels 4 and 5. The other
channels already have selectable gains.
To support all 11 channels on the SDAxx modules connect 3
SDAIBBs to the I/O port of the SDAxx as shown in Figure 2 on page 4 and
set one board to JP9, one to JP10, and the last to JP11. This will provide
11 independent buffered inputs.
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Chapter 3: Configuration
Output Offset
The output offset is the amount by which the output is shifted.
Equation 1 shows how the output offset affects the output of the buffer.
The negative output rail will clip any reading that has a negative input
differential unless the buffer’s output offset is raised. For this purpose,
output offsets of 0 V and 2.5 V are individually jumper selectable for each
channel on the SDAIBB when mated with a compatible data acquisition
model. JP5 corresponds to channel A, JP6 corresponds with channel B,
JP7 corresponds with channel C, and JP8 corresponds with channel D.
An output offset of 0 V is always available. See Table 4 for a list
of models that support the 2.5 V output offset. An output offset of 0 V is
used for positive only differentials, and an output offset of 2.5 V provides
the maximum input range for signals that run equally positive and negative.
A different output offset may be brought in on the terminal blocks
with the output offset jumper removed on the corresponding channel.
V
=
(IN+ − IN−
)
Gain + OutputOffset
Equation 1:
out
Gain Selection
The gain is individually selectable on each buffer with a two-
position jumper. Gains of 1 and 22.28 are conveniently provided on the
unit for each buffer. JP1 controls the gain on channel A, JP2 controls B,
JP3 controls C, and JP4 controls D. Unity gain is ideal for eliminating the
impedance mismatch between input devices and the data acquisition
module. Table 5 shows the maximum voltage ranges that can be amplified
by the provided gain of 22.28. To change the gain, leave the jumper in the
User/22.28 gain position, remove the through-hole 4.7 kΩ resistor, and
replace it with the appropriate value. See Table 6 for some standard inputs,
gains, and appropriate resistor values to achieve the expected gain.
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Table 5: Values for Use with the Provided Gain of 22.28
1%
Resistor
Calculated
Gain
Output
Range
VCM
VDIFF
Out Ref
27.5 mV max +55 mV
0 V ±52 mV
0 V
2.5 V
2.5 V
4.7 k
4.7 k
4.7 k
22.28
22.28
22.28
0.01 – 1.23 V
1.32 - 3.68 V
0.03 - 4.97 V
Ω
Ω
Ω
2.5 V ±110 mV
Table 6: Gains and Resistor Values for Standard Inputs
Out
Ref
Closest 1% Calculated
Output
Range
CM
V
DIFF
V
MAX
G
Resistor
Gain
866
8.66 k
86.6 k
866
9.31 k
412
5mV max +10 mV 0V
50mV max +100mV 0V 12.8
119
116.47 0.01 - 1.16 V
12.55 0.01 - 1.25 V
2.15 0.01 - 2.18 V
116.47 1.34 - 3.66 V
11.74 1.32 - 3.67 V
243.72 0.06 - 4.94 V
24.15 0.09 - 4.91 V
2.43 0.07 - 4.93 V
Ω
Ω
Ω
Ω
Ω
Ω
Ω
0.5V max
0V
+1 V 0V 2.18
±10 mV 2.5V 118
±100 mV 2.5V 11.8
±10 mV 2.5V 247
±100 mV 2.5V 24.7
±1 V 2.5V 2.47
0V
2.5V
2.5V
2.5V
4.32 k
69.8 k
Change R1 to change the gain on channel A, R2 to change channel
B, R7 to change channel C, and R8 to change channel D. The following
sections explain how to calculate the gain and gain resistor for other input
ranges.
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Maximum Gain
The maximum gain for a known differential voltage and common
mode voltage can easily be determined using the following set of equations.
Equation 5 calculates the maximum gain based on the positive internal rail
of the amplifier. Equation 6 gives the maximum gain based on the negative
internal rail of the amplifier. Equation 7 calculates the maximum gain
without overflowing the output range of the SDAIBB. The smallest
maximum gain value calculated using these equations is the maximum gain
that may be used.
2(4.4V −VCM
)
GMAX
=
Equation 2:
Equation 3:
VDIFF
2
(
Vcm + 0.59V
)
Gmax
=
VDIFF
4.94V
GMAX
=
Equation 4:
InputRange
G is the gain, Vcm is the common mode voltage, and Vdiff is the
differential voltage.
Find the maximum allowable gain for a differential voltage of
Example:
±10 mV and a common mode voltage of 2.5 V.
2(4.4 − 2.5)
From Equation 5: GMAX
=
= 380
= 618
0.01
2(2.5 + 0.59)
0.01
From Equation 6: Gmax
From Equation 7: GMAX
=
4.94
=
= 247
0.02
The minimum value calculated is 247, so the maximum allowable gain is
247.
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Gain Resistor Determination
Replacing a single resistor changes the gain on each buffer.
Change R1 to modify the gain on channel A, R2 to change channel B, R7
to change channel C, and R8 to change channel D. Use Equation 8 to
determine the value of the gain resistor to attain a calculated gain. To use
this gain value, place the gain jumper corresponding to the correct channel
in the User/22.28 position. JP1 corresponds to channel A, JP2 corresponds
to channel B, JP3 corresponds to channel C, and JP4 corresponds to
channel D.
100kΩ
RG =
Equation 8:
Equation 9:
(
)
G −1
100kΩ
G = 1+
RG
RG is the value of the gain resistor in ohms.
Find the appropriate 1% resistor for a maximum gain of 150 and
Example:
calculate the actual gain.
From Equation 8: RG
100000
=
= 671.141
(
150 −1)
The nearest 1% resistor that will produce a gain of 150 or less is 681Ω.
100000
From Equation 9: G = 1+
= 147.8
681
The nearest 1% resistor is 681Ω with a resulting gain of 147.8.
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Maximum and Minimum Common Mode Voltage
If the differential voltage range and desired gain are known, the
maximum and minimum common mode voltage can be determined.
Equation 10 is used to calculate the maximum common mode voltage
knowing the gain and the differential voltage. Equation 11 is used to
calculate the minimum common mode voltage. Remember that when
Input+ or Input- is connected to GND on the SDAIBB the
common mode voltage changes as the differential voltage changes.
VDIFF ×G
V
= 4.4V −
Equation 10:
CMMAX
2
VDIFF ×G
V
= −0.590V +
Equation 11:
CMMIN
2
Find the allowable range of the common mode voltage for a
Example:
input range of ±100 mV with a gain of 10.
0.1×10
From Equation 10: VCMMAX = 4.4 −
= 3.9V
2
0.1×10
From Equation 11: VCMMIN = −0.590 +
= −0.09V
2
The common mode voltage must be between –0.09 and 3.9 V.
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Maximum Differential
To determine the maximum differential voltage that can be
amplified, the gain and the common mode voltage must be known first.
Using this information, the most positive the differential voltage may be is
calculated using Equation 12. Equation 13 is used to calculate the most
negative that the differential voltage may swing. These two values are still
limited by the maximum allowable swing given by Equation 14.
2(4.4 −VCM
)
V
=
=
Equation 12:
DIFF
G
2
(
VCM + 0.590V
)
Equation 13: VDIFF
G
4.94V
InputRange ≤
Equation 14:
G
Find the allowable swing of a signal with a common mode
Example:
voltage of 1V with a gain of 50.
2(4.4 −1)
From Equation 12: VDIFF
=
=
= 0.136
50
2
(
1+ 0.590)
From Equation 13: VDIFF
0.0636
50
4.94
From Equation 14: InputRange ≤
= 0.0988
50
The differential voltage can swing as negative as –0.0636 V and as positive
as 0.136 V. However, this full range cannot be achieved with the same
output offset setting due to the 0.0988 V range from Equation 14. To find
the output offset voltage that allows the lower end of this range, use
Equation 1 with Vout set to 0.01 V.
Vout
=
(IN+ − IN−
)
G + OutputOffset
Rearranged to calculate the desired output offset it looks like this
OutputOffset =Vout −VDIFF ×G
Substitute in the appropriate values and solve for the output offset.
OutputOffset = 0.01− (− 0.0636)×50 = 3.19V
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Example Board Setup
Figure 6 is an example of one possible configuration for the
SDAIBB without modifying the board. Table 7 lists the setup for each
channel.
Table 7: Setup for Figure 6
Channel Output Pin Gain Output Offset
A
B
C
D
8
9
10
11
22.28
1
1
2.5 V
0.0 V
2.5 V
0.0 V
22.28
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R8
JP9
USER
22.28/
1
JP10
JP4
GAIN
JP11
JP8
0V
2.5V
OUT.
OFF.
22.28/USER
1
JP2
GAIN
POWER
GND
TB5
R2
0V
OUT.
OFF.
2.5V
JP6
TB2
IN-
TB4
OUT
OFF
IN+
GND
GND
IN+
IN-
OFF
OUT
B
D
JP5
0V
2.5V
OUT.
OFF.
JP7
0V
2.5V
OUT.
OFF.
IN-
OUT
OFF
TB3
IN+
GND
GND
OFF
C
A
IN+
IN-
OUT
TB1
JP3
JP1
GAIN
GAIN
22.28/
USER
1
22.28/
USER
1
R1
R7
Figure 6
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Appendix A: Glossary
(
VCM
)
The voltage about which a differential
Common Mode Voltage
:
voltage swings. When this is measured on the SDAIBB it is calculated
with all voltage readings taken in reference to GND of the SDAIBB as
(IN+ + IN−
)
. Note that when one of the inputs is connected to GND of
2
the SDAIBB the common mode voltage changes as the differential voltage
changes.
The difference in voltage across two points
Differential Voltage
(
V
)
:
DIFF
such as the two leads on a thermocouple. When this is measured on the
SDAIBB it is calculated with all voltage readings taken in reference to
GND of the SDAIBB as IN+ − IN− .
G
The amount by which the input is multiplied before it is output.
Gain ( ):
Vout
Gain =
IN+ − IN−
When the output impedance of sensor is different
Impedance Mismatch:
enough from the input impedance of the data acquisition device to cause
improper sensor readings.
When the voltage and IN- is higher than the
Negative Input Differential:
voltage at IN-. IN+ − IN− ≤ 0
The lowest possible voltage that can be output. For the
Negative Rail:
SDAIBB there is a negative rail internal to the buffer and a negative rail on
the output of the buffer.
The highest possible voltage that can be output. For the
Positive Rail:
SDAIBB there is a positive rail internal to the buffer and a positive rail on
the output of the buffer.
SDAIBB3599 Manual
A-1
B&B Electronics Mfg Co Inc – 707 Dayton Rd - PO Box 1040 - Ottawa IL 61350 - Ph 815-433-5100 - Fax 815-433-5104
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Appendix B: Error Budget Calculations
Important Specs @ 25°C:
V offset in
(
VOSI
)
200 µV
1000 µV
2nA
V offset out
(
VOSO
)
I offset (IOS
Gain Error
)
0.35%
Gain Nonlinearity
0.1Hz to 10Hz Noise
CMR
50ppm
3.0µV p-p
84dB @ 60 Hz
Error Contributions that can be Removed With
Calibration
VOSO
VOSI
+
G
V
=
Equation 15:
Equation 16:
OS
Vin
Sensor Impedance× Ios
IOS
=
Vin
Gain Error = 3500ppm
Equation 17:
Equation 18:
4ppm×VCM
CMR Error =
V
in
Vin is the input voltage.
Error Contributions that Cannot be Removed with
Calibration
Equation 19: Gain Nonlinearity = 50 ppm
3000nV
0.1Hz -10Hz noise =
Equation 20:
Vin
SDAIBB3599 Manual
B-1
B&B Electronics Mfg Co Inc – 707 Dayton Rd - PO Box 1040 - Ottawa IL 61350 - Ph 815-433-5100 - Fax 815-433-5104
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Calculate the error budget for a 350Ω, 100mV load cell with a
Example:
common mode voltage of 2.5V using a gain of 22.28.
500µV
200µV +
22.28
From Equation 15: VOS
=
= 2449ppm
100mV
350Ω× 2nA
From Equation 16:
IOS
=
= 7 ppm
100mV
From Equation 17: Gain Error = 3500ppm
4ppm× 2.5V
100mV
Gain Nonlinearity = 50 ppm
From Equation 18:
From Equation 19:
CMR Error =
= 100ppm
3000nV
From Equation 20: 0.1Hz -10Hz noise =
= 3ppm
100mV
Total Unadjusted Error = 6109ppm
Error After Calibration = 53ppm
B-2
SDAIBB3599Manual
B&B Electronics Mfg Co Inc – 707 Dayton Rd - PO Box 1040 - Ottawa IL 61350 - Ph 815-433-5100 - Fax 815-433-5104
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FEDERAL COMMUNICATIONS COMMISSION
RADIO FREQUENCY INTERFACE STATEMENT
Class A Equipment
This equipment has been tested and found to comply with the
limits for Class A digital device, pursuant to Part 15 of the FCC
Rules. These limits are designed to provide reasonable protection
against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in
accordance with the instructions, may cause harmful interference to
radio communications. Operation of this equipment in a residential
area is likely to cause harmful interference, in which case the user
will be required to correct the interference at personal expense.
FCC Class A Equipment Statement
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