CAPTM CUSTOMIZABLE MICROCONTROLLERS
AT91CAP7E
AT91CAP7E is an ARM7™-based MCU with a direct FPGA interface, six-layer advanced high-speed
bus (AHB), peripheral DMA controller and 160 Kbytes of on-chip SRAM. It offers seamless migration to
AT91CAP7 customizable MCUs for ARM7-plus-FPGA designs. It includes on-chip peripherals such as
USB 2.0 full speed device, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel/
10-bit analog to digital converter, plus a full-functioned system controller including interrupt and power
control and supervisory functions.
The FPGA interface on the AT91CAP7E provides the FPGA with direct access to the AT91CAP7E’s
on-chip AHB and peripheral DMA controller. This architecture eliminates FPGA-induced bus contention,
off-loads MCU-to-FPGA communications from the CPU, and frees up the external bus interface for
external memory access.
Interfacing an ARM7-based MCU to an FPGA has traditionally been done through the external bus
interface (EBI) or programmable I/O. Either arrangement requires that the CPU transfer data to and from
JTAG
System Controller
PLL
Main
OSC
ICE
PLL
EBI
WDT
PMC
PIT
AIC
FPGA Interface
Static Mem.
CF
ARM7TDMI
NAND Flash
SDRAM
32K OSC
RC OSC
SHWDC
RTT
POR
SRAM SRAM
GPBREG
96KB
64KB
POR
6 -layer AHB Matrix
AT91CAP7E
Peripheral DMA
Controller
ROM (256KB)
AMBA Bridge
APB
USB
FS
Device
PIO
x32
Timer
x3
SPI
USART
USART
ADC
the FPGA one word-at-a-time, basically stealing CPU cycles that should be conserved for processing and
limiting access to external memory during FPGA operations.
The FPGA interface on Atmel’s AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves,
a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM
that remaps the external RAM to emulate and debug the ROM code. Fourteen advanced peripheral bus
(APB) slaves, two full-duplex DMA channels and 32-bit programmable I/O may be hardware selected to
share I/O. An on-chip priority interrupt controller provides up to 13 encoded interrupts and two additional
un-encoded interrupts for DMA transfers.
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