Atmel Network Card AT90S8515 4 User Manual

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

• Data and Nonvolatile Program Memory

– 8K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 512 Bytes of SRAM

– 512 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler

Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Programmable Serial UART

– Master/Slave SPI Serial Interface

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

AT90S8515

Summary

– Active: 3.0 mA

– Idle Mode: 1.0 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 32 Programmable I/O Lines

– 40-lead PDIP, 44-lead PLCC and TQFP

• Operating Voltages

– 2.7 - 6.0V for AT90S8515-4

– 4.0 - 6.0V for AT90S8515-8

• Speed Grades

– 0 - 4 MHz for AT90S8515-4

– 0 - 8 MHz for AT90S8515-8

Rev. 0841GS–09/01

Note: This is a summary document. A complete document is

available on our web site at www.atmel.com.

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AT90S8515

Description

The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S8515

achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to

optimize power consumption versus processing speed.

Block Diagram

Figure 1. The AT90S8515 Block Diagram

The AVR core combines a rich instruction set with 32 general-purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

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one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90S8515 provides the following features: 8K bytes of In-System Programmable

Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 general-

purpose working registers, flexible timer/counters with compare modes, internal and

external interrupts, a programmable serial UART, programmable Watchdog Timer with

internal oscillator, an SPI serial port and two software-selectable power-saving modes.

The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and

interrupt system to continue functioning. The Power-down mode saves the register con-

tents but freezes the oscillator, disabling all other chip functions until the next external

interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip In-System Programmable Flash allows the program memory to be repro-

grammed In-System through an SPI serial interface or by a conventional nonvolatile

memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-

grammable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful

microcontroller that provides a highly flexible and cost-effective solution to many embed-

ded control applications.

The AT90S8515 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage.

Ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated. The Port A pins are

tri-stated when a reset condition becomes active, even if the clock is not active.

Port A serves as multiplexed address/data input/output when using external SRAM.

Port B (PB7..PB0)

Port C (PC7..PC0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S8515 as listed

on page 66.

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not active.

Port C also serves as address output when using external SRAM.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

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AT90S8515

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S8515 as listed

on page 73.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

ICP

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

ICP is the input pin for the Timer/Counter1 Input Capture function.

OC1B is the output pin for the Timer/Counter1 Output CompareB function.

OC1B

ALE

ALE is the Address Latch Enable used when the External Memory is enabled. The ALE

strobe is used to latch the low-order address (8 bits) into an address latch during the first

access cycle, and the AD0 - 7 pins are used for data during the second access cycle.

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Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

...

SREG

SPH

SPL

SP13

SP5

SP12

SP4

SP11

SP3

SP10

SP2

SP9

SP1

SP8

SP0

page 20

page 21

SP15

SP7

SP14

SP6

Reserved

GIMSK

GIFR

TIMSK

TIFR

INT1

INTF1

TOIE1

TOV1

INT0

INTF0

OCIE1A

OCF1A

page 26

page 27

page 28

OCIE1B

OCF1B

TICIE1

ICF1

TOIE0

TOV0

Reserved

MCUCR

Reserved

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

Reserved

ICR1H

ICR1L

SRE

SRW

ISC11

ISC10

CS02

ISC01

CS01

ISC00

CS00

page 29

page 33

page 34

Timer/Counter0 (8 Bits)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

...

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

COM1B0

PWM11

CS11

PWM10

CS10

page 35

page 36

page 38

page 39

CTC1

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Output Compare Register A High Byte

Timer/Counter1 – Output Compare Register A Low Byte

Timer/Counter1 – Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

$25 ($45)

$24 ($44)

...

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

page 39

Reserved

WDTCR

Reserved

EEARH

EEARL

EEDR

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

…

WDTOE

WDE

WDP2

WDP1

WDP0

page 42

EEAR8

page 44

page 63

page 65

page 70

page 71

page 73

page 51

page 50

page 49

page 55

page 56

page 58

page 59

EEPROM Address Register Low Byte

EEPROM Data Register

EECR

EEMWE

PORTA2

DDA2

PINA2

PORTB2

DDB2

EEWE

PORTA1

DDA1

PINA1

PORTB1

DDB1

EERE

PORTA0

DDA0

PINA0

PORTB0

DDB0

PORTA

DDRA

PINA

PORTB

DDRB

PINB

PORTA7

DDA7

PINA7

PORTB7

DDB7

PINB7

PORTC7

DDC7

PINC7

PORTD7

DDD7

PORTA6

DDA6

PINA6

PORTB6

DDB6

PINB6

PORTC6

DDC6

PINC6

PORTD6

DDD6

PORTA5

DDA5

PINA5

PORTB5

DDB5

PINB5

PORTC5

DDC5

PINC5

PORTD5

DDD5

PORTA4

DDA4

PINA4

PORTB4

DDB4

PINB4

PORTC4

DDC4

PINC4

PORTD4

DDD4

PORTA3

DDA3

PINA3

PORTB3

DDB3

PINB3

PORTC3

DDC3

PINC3

PORTD3

DDD3

PINB2

PINB1

PINB0

PORTC

DDRC

PINC

PORTD

DDRD

PIND

PORTC2

DDC2

PINC2

PORTD2

DDD2

PIND2

PORTC1

DDC1

PINC1

PORTD1

DDD1

PORTC0

DDC0

PINC0

PORTD0

DDD0

PIND7

PIND6

PIND5

PIND4

PIND3

PIND1

PIND0

SPDR

SPSR

SPCR

UDR

USR

UCR

SPI Data Register

MSTR

UART I/O Data Register

RXEN

SPIF

SPIE

WCOL

SPE

DORD

CPOL

CPHA

SPR1

SPR0

RXC

RXCIE

TXC

TXCIE

UDRE

UDRIE

TXEN

CHR9

RXB8

TXB8

UBRR

ACSR

Reserved

UART Baud Rate Register

ACI ACIE

ACD

ACO

ACIC

ACIS1

ACIS0

$00 ($20)

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

AT90S8515

0841GS–09/01

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AT90S8515

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ←=Rd • Rr

Rd ← Rd •=K

Rd ← Rd v Rr

Rd ←=Rd v K

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

ORI

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

Rd, K

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Z,N,V

None

Rd ← Rd - 1

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

BRANCH INSTRUCTIONS

RJMP

IJMP

RCALL

ICALL

RET

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

PC=← PC + k + 1

PC ← Z

PC ← PC + k + 1

PC ← Z

PC ← STACK

None

RETI

Interrupt Return

CPSE

CPC

Rd, Rr

Rd, K

Compare, Skip if Equal

Compare

Compare with Carry

if (Rd = Rr) PC=← PC + 2 or 3

Rd - Rr

Rd - Rr - C

None

Z,N,V,C,H

None

1/2/3

CPI

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ←=PC + k + 1

if (SREG(s) = 0) then PC ←=PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

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Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, -X

Rd, Y

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Move between Registers

Load Immediate

Load Indirect

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Indirect

Rd ← Rr

Rd ← K

Rd ← (X)

None

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd ← (Z), Z ← Z + 1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LDD

LDS

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Indirect

X, Rr

(X)=← Rr

X+, Rr

-X, Rr

Y, Rr

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

(X)=← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

STD

(Z) ← Rr

STD

STS

LPM

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

Rd, P

P, Rr

OUT

PUSH

POP

Out Port

Push Register on Stack

Pop Register from Stack

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P, b

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)

Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)

Rd(n) ← Rd(n+1), n = 0..6

Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I=← 0

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

None

LSL

Z,C,N,V

None

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Flag Set

Flag Clear

Bit Store from Register to T

Bit Load from T to Register

Set Carry

SREG(s)

None

Rr, b

Rd, b

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

Clear T in SREG

T ← 0

H ← 1

H ← 0

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

Sleep

Watchdog Reset

None

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

AT90S8515

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AT90S8515

AT90S8515 Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

2.7V - 6.0V

AT90S8515-4AC

AT90S8515-4JC

AT90S8515-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8515-4AI

AT90S8515-4JI

AT90S8515-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

4.0V - 6.0V

AT90S8515-8AC

AT90S8515-8JC

AT90S8515-8PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8515-8AI

AT90S8515-8JI

AT90S8515-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

Note:

Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed.

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

44-lead, Plastic J-leaded Chip Carrier (PLCC)

44A

44J

40P6

40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

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Packaging Information

44A

44-lead, Thin (1.0mm) Plastic Quad Flat Package

(TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch.

Dimension in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

12.25(0.482)

11.75(0.462)

PIN 1 ID

PIN 1

0.45(0.018)

0.30(0.012)

0.80(0.0315) BSC

10.10(0.394)

9.90(0.386)

1.20(0.047) MAX

0.20(0.008)

0.09(0.004)

0˚~7˚

0.75(0.030) 0.15(0.006)

0.45(0.018) 0.05(0.002)

*Controlling dimension: millimetter

REV. A 04/11/2001

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AT90S8515

44J

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Milimeters and (Inches)*

JEDEC STANDARD MS-018 AC

1.14(0.045) X 45˚

PIN NO. 1

IDENTIFY

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

16.00(0.630)

15.00(0.590)

0.533(0.021)

16.70(0.656)

16.50(0.650)

0.813(0.032)

0.660(0.026)

17.70(0.695)

17.40(0.685)

0.330(0.013)

1.27(0.050) TYP

0.50(0.020)MIN

2.11(0.083)

12.70(0.500) REF SQ

1.57(0.062)

3.05(0.120)

2.29(0.090)

4.57(0.180)

4.19(0.165)

0.51(0.020)MAX 45˚ MAX (3X)

*Controlling dimensions: Inches

REV. A 04/11/2001

0841GS–09/01

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40P6

40-lead, Plastic Dual Inline

Parkage (PDIP), 0.600" wide

Demension in Millimeters and (Inches)*

JEDEC STANDARD MS-011 AC

52.71(2.075)

51.94(2.045)

13.97(0.550)

13.46(0.530)

48.26(1.900) REF

4.83(0.190)MAX

SEATING

PLANE

0.38(0.015)MIN

3.56(0.140)

3.05(0.120)

0.56(0.022)

0.38(0.015)

1.65(0.065)

1.27(0.050)

2.54(0.100)BSC

15.88(0.625)

15.24(0.600)

0º ~ 15º REF

0.38(0.015)

0.20(0.008)

17.78(0.700)MAX

*Controlling dimension: Inches

REV. A 04/11/2001

AT90S8515

0841GS–09/01

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Atmel Headquarters

Atmel Product Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

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FAX (33) 0 2 40 18 19 60

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Japan

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Zone Industrielle

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TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Smart Card ICs

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TEL (44) 1355-357-000

FAX (44) 1355-242-743

e-mail

[email protected]

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®and AVR^®are the registered trademarks of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

0841GS–09/01/xM

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