Advantech Network Router SOM A2552 User Manual

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User’s Manual for Advantech SOM-A2552 series module V1.00

User’s Manual

Advantech RISC SOM-A2552 Series Module

System Module with Intel XScale PXA255 processor, SMI SM501

Graphic chip with Windows^®CE.NET

Released Version:V1.00

Released Date: May. 19. 2004

Advantech Co., Ltd

Risc Embedded Computing Division

http://www.advantech.com/risc

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User’s Manual for Advantech SOM-A2552 series module V1.00

Revision History

Version

V1.00

Date

2004.05.19

Reason

1^stOfficial released version. (For

9696255201, 9696255801, 9696255F01

& 9696255F12)

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User’s Manual for Advantech SOM-A2552 series module V1.00

Chapter 1 SOM-A2552 series Architecture

1.1 Introduction

The SOM-A2552 is WinCE ready, compact size module platform with

SBC-function-level functionality that is emphasis at high performance VGA

capability that offers Ultra low power consumption with SXGA LCD, Dual

Display, Analogy VGA in/out put, Audio Interface into a compact 68x68x6.8mm

size module.

By the integration of Intel PXA-255 32-bit SoC and SMI SM-501 VGA

controller, SOM-A2552 is perfect for Multimedia, mobility, battery powered,

great heavy display base embedded Internet appliance or so called smart

embedded devices.

SOM-A2552 series Design highlight:

- WinCE.NET-ready platform as functional system engine

- SoC Intel XScale PXA255 & Companion Graphic Chip SMI SM501provide

complete SBC functionality & high performance Graphic function in a

module

- Pre-define I/O Ready bus thru SODIMM-200 interface

- Design-in package: Reference kit with full design-in documentation

- Advantech RISC WinCE builder offers friendly application migration

interface

- Low profit 68x68mm

SOM-A200 architecture

SOM-A255x series are based on Advantech SOM-A200 architecture to

design. SOM-A200 is Advantech RISC ultra-low power series SOM

architecture. The following block diagram is the SOM-A200 architecture.

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Based on SOM-A200 architecture to design, SOM-A255x series have two

kinds of PCB form factors.

SOM-A2552 & SOM-A2558 series: 68mm x 68mm x 6.8mm

SOM-A255F series: 68mm x 102mm x 6.8mm

SOM-A2552 benefit

The SOM-A2552 series are very compact (68mm x 68mm x 6.8mm) and

highly integrated system module. SOM-A2552 series products have a

standardized form factor and standardized connectors (DDR-SODIMM

Memory Connector and two 100-pin board-to-board connectors) that carry a

specified set of signals. This standardization allows users to create

application-specified User Solution Board (CSB) which can accept a variety of

present and future SOM-A200 series modules.

SOM-A2552 series include popular & common peripheral functions such

as serial ports, USB, etc. The CSB designer can optimize exactly how each of

these functions is physically implemented. Connectors can be placed precisely

where they are needed for the application, on a baseboard designed to

optimally fit the system configuration and layout.

A CSB design may be used with a range of SOM-A2552 modules. This

flexibility can be used to differentiate products at various price/ performance

points, or to design “future proof” systems that have a built-in upgrade path.

The modularity of an SOM-A2552 solution also insures against obsolescence

as computer technology continues to evolve. A properly designed SOM-A2552

CSB can be used with several successive generations of SOM-A2552

modules. An SOM-A2552 CSB design thus has many of the advantages of a

custom computer board design, but delivers better obsolescence protection,

greatly reduced engineering effort, and faster time to market.

Based embedded platform integrates both low-level hardware and

software design and is always agreed to require heavy R&D resources, huge

development effort, risk as well as long time to market lead-time. Moreover,

the fast develop RISC SoC technology and short product life that has been

challenging System Integrators how to make a right product development

approach while foreseeing the huge advantage & benefit by adopting

RISC-base solution.

SOM-A2552 series are an innovate platform architecture of

WinCE.NET-ready complete functional system in a low profit module with

SODIMM 200-pin unified I/O ready bus interface that is designed to fit into

application-specified User Solution Board (CSB) with easy, risk-less, robust,

fast implementation approach. Dual expansion interface and Pre-select

Embedded OS also are well integrated on module. OS Board Support

Package (BSP) and advantech own-develop system utility & tools are also

supported for an easy design-in business philosophy.

SOM-A2552 series is designed for

Wireless broadband terminals: Wireless access to video/TV/DVD/PVR,

wireless access to broadband connection, digital picture viewer, remote

access to Internet/email, remote control of AV functions

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Smart display devices: Kiosks, small DTV, thin client, high end mobile

consumer devices, videoconferencing

Mobile, battery-powered device platforms with large display demand

Vehicle computing/telemetric platforms for navigation/entertainment

demands

Multimedia terminal device platforms with large display

Security surveillance platforms with digital or analog video input/output

SOM-A2552 series design-in package

The Design-in Kit package provides developer complete reference

design-in suit for application evaluation/ development and own Customer

Solution Board (CSB) development. It contains the needed information,

documentation and tools for starting their hands-on work as the followings

items:

Target SOM (SOM-A2552-440B0): SOM-A2552 standard version

board.

SOM-A255x series Reference Carrier Board (RCB): Sample CSB

for developer reference. The board can be used in SOM-A255x

series board. (SOM-A255x means SOM-A2552, SOM-A2558 and

SOM-A2552)

64MB compact flash card : the CF card is empty without any file

inside.

SOM-A255x series support CD : includes

sample image & boot loader

manuals & datasheets

SOM-A255x series CSB design guide

S/W utility(upgrade utility, testing utility)

SOM-A255x series WinCE 4.2 BSP & SDK

Application note

Testing Set:

It is designed for sample CSB or user own CSB/mass production test.

It includes:

H/W testing tools: RS232 loop-back testing tool, ADAM-4520

for RS485 testing, null MODEM cable, JTAG cable, USB

ActiveSync cable, Audio cable, RS232 cable and RS485

cable.

S/W testing Utility: Advantech-developed testing Utility. Testing

process will be implemented by S/W testing Utility and H/W

testing tools.

Document: “User's manual of SOM-A255x series testing kit”.

User can base on the documents to know how to implement

testing process.

Software Development Tools:

Software tools is the complete package for user developed their

target image to align with their target CSB and applications

BSP: Binary Board Support Package of target SOM Design-in Kit.

User can integrate their target WinCE platform in components &

Apps & drivers

SDK: For user target Apps development

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Reference Image: Reference Image for the selected model of

SOM.

Bootloader: Bootloader for the SOM-A255x series board.

Upgrade Utility: User can use Upgrade utility to upgrade boot

logo, image & bootloader.

Except the Design-in package, Advantech also supply many types of LCD

kits for users to reduce their developing effort. The LCD kit include the

following items :

LCD

Inverter

Cables: includes LCD signals cable, Inverter signals cable.

Document: The LCD kit installation guide.

Advantech supply the following LCD kits for user to choose

LCD-A057-STQ1-0 (Optional item)

5.7” STN QVGA LCD kit. The kit includes 5.7” STN QVGA LCD

(NAN-YA/ LCBFBTB61M23), 4-wires resistive T/S, inverter, cables

and installation guide. SOM-A2552 & SOM-A255F series don’t

support 320*240 STN panel in this moment, if user have this kind of

requirement, please contact with [email protected] or

advantech regional sales for further support.

LCD-A064-TTV1-0 (Optional item)

6.4” TFT VGA LCD kit. The kit includes 6.4” TFT VGA LCD

kit(PRIMEVIEW PD064VT2), 4-wires resistive T/S, inverter, cables

and installation guide. All SOM-A255x series support this LCD kit in

reference image.

LCD-A104-TTS1-0 (Optional item)

10.4” TFT SVGA LCD kit. The kit includes 10.4” TFT SVGA LCD

(AUO/ G104SN03v2), 4-wires resistive T/S, inverter, cables and

installation guide. Only SOM-A255F & SOM-A2552 series can

support this LCD-out mode.

LCD-A150-TTX2-0 (Optional item)

15” TFT XGA LCD kit. The kit includes 15” TFT XGA LCD (AUO/

M150XN07), 4-wires resistive T/S, inverter, cables and installation

guide. Only SOM-A255F & SOM-A2552 series can support this

LCD-out mode.

SOM-A2552 series design-in kit(SOM-ADK2552-B00) is not included

any LCD kit. If user needs LCD kit to evaluate, please order your suitable

size LCD kit.

Risc CE-Builder

SOM-A255x series all support the Advantech optional RISC CE-Builder by

which developers can manage the BSP for their own platform development

thru a friendly users interface over the web.

RISC CE-Builder Solution is constituted by two parts: Web Image Builder

and CE-TUner.

Web Image Builder offers developers an online image building

mechanism through a friendly user interface to remotely conduct low-level

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software and platform customization / integration for their target application

without knowing / using Microsoft Platform Builder. The image building

machine links to Advantech’s Board Support Package (BSP) library so

developers can leverage Advantech’s low-level software solution database.

CE-TUner is a powerful value-added system utility / tool suit for

developers easily and simply develop, validate and upgrade their own SW

platform solution. CE-Tuner helps users fine-tune their target SW image for

optimized performance, verify settings, and platform tests before the

production image is certified.

RISC CE-Builder is not included in Design-in kit. If you need more

information about it, please contact with [email protected] or

advantech regional sales for further support.

1.12 SOM-A2552 Block diagram

SOM-A2552 series bases on Dual-Chips design concept, SoC Intel

XScale PXA255 & Graphic chip SMI SM501. The Block diagram is as

following:

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SoC Intel XScale PXA255 introduction

Intel XScale PXA255 processor is continuing the advance in handheld

multimedia functionality.

PXA255 is Low power, high performance 32-bit Intel XScale® core-based

CPU (200, 300 and 400 MHz). The SoC is ARM Architecture v.5TE compliant.

0.18µ process for high core speeds at low power.

Intel® Media Processing Technology including 40-bit accumulator and 16-bit

SIMD to enhance audio/video decode performance.

In power field, Low Power and Turbo modes enables enhanced optimal

battery life. 32 KB data and 32 KB instruction caches, 2 KB Mini data cache for

streaming data.

About PXA255 I/O expansion function, Integrated Memory and

PCMCIA/Compact Flash Controller with 100 MHz Memory Bus, 16-bit or 32-bit

ROM/Flash/SRAM (six banks), 16-bit or 32-bit SDRAM, SMROM (four banks),

as well as PCMCIA and Compact Flash for added functionality and

expandability. System Control Module includes 17 dedicated general-purpose

interruptible I/O ports, real-time clock, watchdog and interval timers, power

management controller, interrupt controller, reset controller, and two on-chip

oscillators.

Peripheral Control Module offers 16 channel configurable DMA controller,

integrated LCD controller with unique DMA for fast color screen support,

Bluetooth** I/F, serial ports including IrDA, I2C, I2S, AC97, three UARTs(1 Full

H/W flow control), SPI and enhanced SSP, USB end point interface, and

MMC/SD Card Support for expandable memory and I/O functionality.

About Intel PXA255 SoC detail information, user could visit Intel web site

for more.

Enhance Graphic Chip SMI SM501 introduction

The SM501 is a Mobile System-on-a-Chip (MSOC™) device. This robust device

delivers high-performance video and 2D operation, providing a solution for embedded

mADKets. The SM501 also contains a wide variety of I/Os, such as analog RGB and

digital LCD Panel interfaces, an 8-bit parallel interface, USB, UART, IrDA, Zoom

Video, AC97 or I2S, SSP, PWM, and I2C interfaces. These built-in functionalities help

to reduce overall system cost. Additional programmable GPIO bits can be used to

interface to external devices as well.

About SMI SM501 display chip detail information, user could visit SMI web

site for more.

System Memory

SOM-A2552 SDRAM can be configured as 4/8/16/32/64/128/256MB.

Users can base on their requirement to reconfigure the SDRAM size.

There are two functions Flash on SOM-A2552 series. One is Boot Flash,

the other is Storage Flash.

Boot Flash is 1MB NOR flash. In standard SOM-A2552 series product,

Advantech will pre-install the WinCE bootloader in it.

Storage Flash is used to save image & user APs. Storage Flash size is

also reconfigurable. The Storage Flash is M-system Flash. Storage Flash size

could be 0/16/32/64 MB. SOM-A2552 series have Multiple boot options

through the on-board Flash or Compact Flash Card (CFC) for easy maintain

and cost saving. If Storage Flash is 0MB that means user should put the image

in Compact Flash Card.

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CPLD

SOM-A2552 series have one CPLD on board. The CPLD take charges of

the following function:

System memory assignments

I/O control

RTC control

Base on Advantech policy, Advantech won’t release the CPLD code to

user. In fact, when user designs their own target carrier board, they don’t need

to know the CPLD code. Advantech will release memory map of available

memory block and available GPIOs. These are fully enough to users to

develop their own carrier board.

1.2 System Specifications

The following table is SOM-A2552 series functional specifications.

SOM-A2552 standard product specification table

Model Name

SOM-A2552-440B0

Reconfiguration Option

Func.

CPU

PXA255-400MHz

200/300/400 MHz

SMI SM501 with 8MB embedded

SDRAM

SM501 with /without 8MB

embedded SDRAM

Graphic Chip

System Memory(SDRAM)

Booting Flash

64MB

16/32/64/128 MB

1MB NOR Flash

On-board Flash (Image &

Storage )

0MB

0/16/32/64MB

Linux(By customer request)

Yes

OS Image Storage

AMI Bus(X1 Bus)

WinCE.NET

100-pin B2B connector with driving

buffers

Feature Extension

Bus(X2 Bus)

100-pin B2B connector (Provide ZV

& SD/MMC I/F)

Yes

Watch Dog

PXA255 internal

External RTC w/backup power pin

RTC/SDRAM

Yes

RTC

System Backup battery

3x Full RS-232 (TTL), 1x 2-wires

RS-232 (TTL),1x 3-wires

RS-232/RS-485

Serial Port

PCMCIA/Compact flash

I/F

2 slots PCMCIA/CF or

1xPCMCIA, 1xCF

USB Host

1x USB 1.1 Host

1x USB Client

USB Client

Ix Ch(Support

Memory mode)

SD/MMC

CRT-out

Up to 1280*1024

TV out

TV Interface

ZV port

Yes

SM501 24 bit LCD interface,

resolution up to 1280*1024

LCD TTL Interface

Touch Screen Interface

4-wire resistive

Yes

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AC’97 codec on board, support

Audio Codec

Microphone-in, Line-in, Line-out

Speaker-out

Yes

Buzzer control

Yes

SM Bus Interface

H/W Reset, S/W Reset,

Suspend/Wake Up I/F

System Reset

Power input

3.3V/5V

0~60℃

Operating temperature

Operating humidity

Certification

Optional for -10~60℃ & -20~80℃

0%~90% relative humidity

FCC/CE

Form factor

68mm*68mm*6.8mm

Ps.. “Reconfiguration Option” column provide users many choices. “-“means

no option. If standard product SOM-A2552-440B0’s spec. doesn’t fit user’s

requirement, user could contact with Advantech for SOM-A2552

reconfiguration.

* Advantech SOM-A255x series have wide temperature products. About detail product

information, user could visit website http://www.advantech.com.tw/epc/phoenix/ . User also

could contact with [email protected] or advantech regional sales for further

information.

SOM-A2552-440B0 is off-the-shelf standard product. Advantech welcome

SOM-A2552 re-configuration demand. Users could base on the column of

SOM-A2552 spec. to re-configurate userized SOM-A2552. “Reconfiguration

Option” column provide users many choices. “-“means no option. If standard

product SOM-A2552-440B0’s spec. doesn’t fit user’s requirement, user could

contact with Advantech for SOM-A2552 reconfiguration.

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1.2.1 Mechanical Specification

Following figure shows the mechanical drawing of SOM-A2552 series.

The above figure shows the SOM-A2552 mechanical drawing. Users

could follow the above figure to implement the layout procedure.

1^stdrawing shows the SOM-A2552 module PCB mechanical data. When

users enter the layout procedure, user could follow the 1^stdrawing to place the

connector. SOM-A2552 series PCB form factor is 68mm*68mm*68mm.

The 2^nddrawing shows the PCB thickness limitation. The component side

height is 2.8mm, and the solder side maximum height is 3.00mm and the PCB

thickness is 1.00mm.

The 3^rddrawing shows allied mechanical data of SOM-A2552 series

board and CSB. Users could see that the matting height is 3.00mm and the

solder side maximum height of SOM-A2552 is also 3.00mm. So, Advantech

don’t suggest users to place any components between SOM module and

CSB in layout stage. It could be short!

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Most users will question the height of SOM structure product. Does

product be too thick based on SOM structure product? User could see the

answer in the 3^rdmechanical drawing. Maximum height of SOM module allied

with CSB is 5.20mm. One port USB 1.1 host connector height is 8.37mm, 1

DB-9 RS-232 connector is 12.53mm, 1 type-II CF slot is 8.72mm. So, this is

the answer! If users want to use any standard I/O connector on CSB, then

SOM structure is not the maximum height maker. The maximum highness is

decided by I/O connector, not SOM structure.

1.2.2 Power System Requirement

SOM-A2552 Operating DC value table

Symbol

Description

Min.

Typ.

3.3

Max.

SYS_VCC3P SOM system DC 3.3V DC-in

power source

3.6

SOM system DC 5.0V DC-in

power source

Back-up power source for RTC &

SDRAM

SYS_VCC

4.5

5.5

SYS_VC

C3P3

BAT_VCC

Input DC Operating Conditions

Input High Voltage, all standard

input and I/O pins

Input Low Voltage, all standard

input and I/O pins

VIH

VIL

0.8*VCC

VSS

VCC

0.2*VCC

Output DC Operating Conditions

Output High Voltage, all standard

output and I/O pins

Output Low Voltage, all standard

output and I/O pins

VOH

VOL

VCC-0.1

VSS

VCC

VSS+0.4

1.2.3 Power Consumption

In WinCE O.S. environment, SOM-A2552 series products have 3 kinds of

operating model :

Normal mode: I/O and system all work well. All component on

SOM-A55x are powered.

Idle mode: I/O and system all work well except backlight control

circuit. In order to do power-saving, LCD backlight control circuit

will disable the LCD backlight inverter.

Suspend mode: all devices are no-powered except SDRAM,

RTC(real time clock) & some CPU(PXA255) power pins. In

suspend mode, SOM-A255x series are only powered by

BAT_VCC pin ( Li-ion 3.0V coin battery from CSB).If user doesn’t

design coin battery to power BAT_VCC pin, then Suspend mode

doesn’t work on SOM-A55x series products.

About detail power consumption of every SOM-A255x series, please

contact with [email protected].

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Chapter 2 Assignments and Descriptions

2.1 Connector Locations

Figure SOM-A2552 series component side

Figure SOM-A2552 series solder side

SOM Connector vendor table

Connector

AMI bus (X1)

vendor

Matsushita electric works,

LTD.

AXK600335

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SOM-R200 (X2)

Standard Golden finger

200-pin

Feature extension bus

Matsushita electric works,

LTD.

PXA255 JTAG pin header

SOM CPLD JTAG port

AXK600335

(X3)

JP1

JP2

PS.JP1 & JP2 are 2.00 mm 6*1 pin-headers.

CSB Mating Connector table

vendor

Connector

AMI bus (X1)

Matsushita electric works,

LTD.

AXK500135

SODIMM-200 (X2)

Feature extension bus

(X3)

QUASAR SYSTEM INC.

Matsushita electric works,

LTD.

CA0075-200N31

AXK500135

Advantech RISC SOM-A200 ultra low power series (SOM-A2552,

SOM-A2558 and SOM-A255F) all follow the same pin definition in X1,X2 and

X3. So, users could design their own CSB to be compatible with all advantech

RISC ultra low power series SOM easily. In this way, users’ CSB will be

powerful upgrade capability & option choice.

X1: AMI bus

AMI bus connector is PXA255 ARM bus. It includes complete system

address lines, data lines, GPIOs (for interrupt source) and Chip select pins

(nCS). Users could use this bus to extend any other IC controller on CSB to

implement the function which SOM modules not provide. In order to keep the

system bus signals well, every address lines and data lines are driven by

buffers. Buffers’ signals direction controls are implemented by CPLD.

X2: SODIMM-200 connector

Most I/O functions fog in X2. X2 includes PCMCIA/CF, T/S, Audio, system

reset control, SOM system power input pins, I2C, USB host, USB client,

RS-232 ports, RS-485 port, LCD out, CRT out and PS/2 ports. Every I/O

functions will be described in the following content in detail.

X3: Feature Extension connector

Advantech SOM-A series products use dual-chip or triple-chip design

concepts. The companion chip’s I/O function will come out through the X3. In

SOM-A255F series, SD/MMC & ZV (zoom video) I/F are included in X3.

ADVANTECH SOM-A200 is a powerful and helpful architecture for users

to implement a RISC system. There are three types of interfaces. One is

SO-DIMM 200 gold finger interface and two 100-pin B2B connectors.

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Pin Definition

¦ JP1 PXA255 JTAG pin header

Pin Num.

Description

Note

TCK

TDI

TDO

TMS

nJTAGTRST

GND

nRESET

Pin type

P : DC power pin or system ground pin

I : digital input pin

O : digital output pin

IO : bidirectional pin

AI : analog input pin

AO : analog output pin

- : no function

¦ SODIMM-200 Pin Out Table (X2)

No.

Signals

Typ

Description

Default state

SA_SKT_D0 AIO PCMCIA/CF data 0

SA_SKT_D8 IO PCMCIA/CF data 8

SA_SKT_D1 IO PCMCIA/CF data 1

SA_SKT_D9 IO PCMCIA/CF data 9

SA_SKT_D2 IO PCMCIA/CF data 2

SA_SKT_D10 IO PCMCIA/CF data 10

SA_SKT_D3 IO PCMCIA/CF data 3

SA_SKT_D11 IO PCMCIA/CF data 11

SA_SKT_D4 IO PCMCIA/CF data 4

SA_SKT_D12 IO PCMCIA/CF data 12

SA_SKT_D5 IO PCMCIA/CF data 5

SA_SKT_D13 IO PCMCIA/CF data 13

SA_SKT_D6 IO PCMCIA/CF data 6

SA_SKT_D14 IO PCMCIA/CF data 14

SA_SKT_D7 IO PCMCIA/CF data 7

SA_SKT_D15 IO PCMCIA/CF data 15

SA_SKT_A14 IO PCMCIA/CF address 14

SA_SKT_A15 IO PCMCIA/CF address 15

SA_SKT_A12 IO PCMCIA/CF address 12

SA_SKT_A13 IO PCMCIA/CF address 13

SA_SKT_A10 IO PCMCIA/CF address 10

SA_SKT_A11 IO PCMCIA/CF address 11

SA_SKT_A8 IO PCMCIA/CF address 8

No pulling

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SA_SKT_A9 IO PCMCIA/CF address 9

SA_SKT_A6 IO PCMCIA/CF address 6

No pulling

SA_SKT_A7 IO PCMCIA/CF address 7

SA_SKT_A4 IO PCMCIA/CF address 4

SA_SKT_A5 IO PCMCIA/CF address 5

SA_SKT_A2 IO PCMCIA/CF address 2

SA_SKT_A3 IO PCMCIA/CF address 3

SA_SKT_A0 IO PCMCIA/CF address 0

SA_SKT_A1 IO PCMCIA/CF address 1

SA_SKT_A16 IO PCMCIA/CF address 16

SA_SKT_A17 IO PCMCIA/CF address 17

SA_SKT_A18 IO PCMCIA/CF address 18

SA_SKT_A19 IO PCMCIA/CF address 19

SA_SKT_A20 IO PCMCIA/CF address 20

SA_SKT_A21 IO PCMCIA/CF address 21

SA_SKT_A22 IO PCMCIA/CF address 22

40 nSA_SKT_IOR O PCMCIA I/O read. Performs read No pulling

transactions from PCMCIA I/O

space.

SA_SKT_A24 IO PCMCIA/CF address 24

No pulling

AI 4-wires resistive touch screen

signals: X+ Position Input.

43 nSA_SKT_WE O PCMCIA write enable. (output)

Performs writes to PCMCIA

No pulling

memory and to PCMCIA attribute

space. Also used as the write

enable signal for Variable Latency

I/O.

AI 4-wires resistive touch screen

signals: Y+ Position Input.

No pulling

45 nSA_SKT_IOW O PCMCIA I/O write signal. (output) No pulling

Performs write transactions to

PCMCIA I/O space.

AI 4-wires resistive touch screen

signals: X– Position Input

No pulling

nSA_SKT_RE O PCMCIA Register select. (output) No pulling

Indicates that the target address

on a memory transaction is

attribute space. Has the same

timing as the address bus.

AI 4-wires resistive touch screen

signals: Y– Position Input

No pulling

SA_SKT_A23 IO PCMCIA/CF address 23

GND P Ground

SA_SKT_A25 IO PCMCIA/CF address 25

No pulling

AC97_EAPD

O External audio Amplifier power

down control

53 nSA_SKT_OE O PCMCIA output enable. (output)

No pulling

Reads from PCMCIA memory and

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to PCMCIA attribute space.

LINEOUT_R AO Audio line-Out right channel

55 nSA_SKT1_CD

PCMCIA/CF slot 0 card detect pin No pulling

LINEOUT_L AO Audio line-Out left channel

57 nSA_SKT0_CD

PCMCIA/CF slot 1 card detect pin No pulling

58 AC97_LINEIN_ AI Audio line input right channel.

59 nSA_SKT1_CE O PCMCIA/CF slot 0 card enable pin No pulling

60 AC97_LINEIN_ AI Audio line input left channel.

61 nSA_SKT0_CE O PCMCIA/CF slot 0 card enable pin No pulling

MIC_IN

AI First Microphone input

63 nSA_SKT1_CE O PCMCIA/CF slot 1 card enable pin No pulling

GND

P Ground

65 SA_SKT1_VCC P PCMCIA/CF slot 1 power pin

66 nSA_SKT0_VS

PCMCIA/CF slot 0 voltage sense Pull high with

pin 1. 10Kohm

PCMCIA/CF slot 1 voltage sense Pull high with

pin 1. 10Kohm

67 nSA_SKT1_VS

68 nSA_SKT0_CE O PCMCIA/CF slot 0 card enable pin No pulling

69 SA_SKT1_RDY

PCMCIA/CF slot 1 ready pin.

Pull high with

10Kohm

Pull high with

10Kohm

70 SA_SKT0_RDY

PCMCIA/CF slot 0 ready pin.

71 nSA_SKT0_VS

PCMCIA/CF slot 0 voltage sense Pull high with

pin 2. 10Kohm

PCMCIA/CF slot 1 voltage sense Pull high with

72 nSA_SKT1_VS

pin 2.

10Kohm

73 SA_SKT0_RST O PCMCIA/CF slot 0 reset pin.

Pull high with

10Kohm

74 SA_SKT1_RST O PCMCIA/CF slot 1 reset pin.

Pull high with

10Kohm

75 nSA_SKT0_W

AIT

PCMCIA/CF slot 0 wait signals. Pull high with

Driven low by the PCMCIA card to 10Kohm

extend the length of the transfers

to/from the PXA255 processor.

76 nSA_SKT1_CD

PCMCIA/CF slot 1 card detect pin No pulling

77 nSA_SKT1_W

AIT

PCMCIA/CF slot 1 wait signals.

Pull high with

Driven low by the PCMCIA card to 10Kohm

extend the length of the transfers

to/from the PXA255 processor.

78 nSA_SKT0_CD

PCMCIA/CF slot 0 card detect pin No pulling

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IO Select 16. (input) Acknowledge Pull high with

79 nSA_SKT0_IOI

S16

from the PCMCIA card that the

current address is a valid 16 bit

wide I/O address.

10Kohm

80 SA_SKT0_VCC P PCMCIA/CF slot 0 power pin.

Powered

81 nSA_SKT1_IOI

S16

PCMCIA/CF slot 0 IO Select 16.

Acknowledge from the PCMCIA

card that the current address is a

valid 16 bit wide I/O address.

Pull high with

10Kohm

82 nSA_PWR_ON

System suspend/wakeup input pin. Pull high with

Falling edge triggered.

10Kohm

nBATT_FALT

Main Battery Fault. Signals that

main battery is low or removed.

Assertion causes PXA255

Pull high with

100Kohm

processor to enter sleep mode or

force an Imprecise Data Exception,

which cannot be masked. PXA255

processor will not recognize a

wakeup event while this signal is

asserted. Minimum assertion time

for nBATT_FAULT is 1 ms.

nSW_RESET

nVDD_FALT

System software reset input pin.

Falling edge triggered.

VDD Fault. Signals that the main Pull high with

Pull high with

10Kohm

power source is going out of

regulation. nVDD_FAULT causes

the PXA255 processor to enter

sleep mode or force an Imprecise

Data Exception, which cannot be

masked. nVDD_FAULT is ignored

after a wakeup event until the

power supply timer completes

(approximately 10 ms). Minimum

assertion time for nVDD_FAULT is

1 ms.

100Kohm

86 nRESET_OUT O Reset Out. Asserted when

nRESET is asserted and deasserts

after nRESET is deasserted but

before the first instruction fetch.

No pulling

nRESET_OUT is also asserted for

“soft” reset events: sleep,

watchdog reset, or GPIO reset.

GND

PWR_EN

P Ground

Power Enable for the power

Pull high with

O supply. (output) When negated, it 100Kohm

signals the power supply to

remove power to the core because

the system is entering sleep mode.

BAT_VCC

P 3.0V li-ion coin battery positive No pulling

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pole input pin.

nRESET

System hardware reset input pin. Pull high with

Falling edge triggered. Hard reset. 10Kohm

(input) Level sensitive input used

to start the processor from a known

address. Assertion causes the

current instruction to terminate

abnormally and causes a reset.

When nRESET is driven high, the

processor starts execution from

address 0. nRESET must remain

low until the power supply is stable

and the internal 3.6864 MHz

oscillator has stabilized.

nDC_IN

System DC input indicator pin.

When the pin is low, it means

Pull low with

1Kohm

system is powered by external DC

power source. If user target device

is not power by battery, use could

use this pin as GPIO. The pin

connects to SoC PXA255 GPIO16.

SYS_VCC

P SOM system DC power 5V input

pin. SYS_VCC should always be

mode.

SYS_VCC3P3 P SOM system DC power 3.3V input -

pin. SYS_VCC should always be

mode.

SYS_VCC

P SOM system DC power 5V input

pin. SYS_VCC should always be

mode.

SYS_VCC3P3 P SOM system DC power 3.3V input -

pin. SYS_VCC should always be

mode.

SMBUS_CLK IO System Management Bus clock Pull high with

pin. The pin is implemented by 4.7Kohm

SoC PXA255 I2C bus.

SYS_VCC3P3 P SOM system DC power 3.3V input -

pin. SYS_VCC should always be

mode.

SMBUS_DAT IO System Management Bus data pin. Pull high with

The pin is implemented by SoC

PXA255 I2C bus.

4.7Kohm

SYS_VCC3P3 P SOM system DC power 3.3V input -

pin. SYS_VCC should always be

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mode.

IO USB Client Positive pin

100

USB_CP

No pulling

101 SYS_VCC3P3 P SOM system DC power 3.3V input Powered

pin. SYS_VCC should always be

mode.

102

USB_CN

IO USB Client Negative pin.

No pulling

103 SYS_VCC3P3 P SOM system DC power 3.3V input -

pin. SYS_VCC should always be

mode.

104 BUZZER_OUT O Buzzer-out control signals. User

can use the pin to control buzzer

power pin.

No pulling

105 USB_LINK_5V

USB client link status indicator pin. Pull low with

When the pin is high, it means

USB client port has been

plugged-in USB device.

100Kohm

106

UART2_RTS

O UART2 Request-to-Send signal

pin. If user doesn’t need UART2

function, user could use this pin as

GPIO. The pin connects to SoC

PXA255 GPIO45.

Pull high with

100Kohm

107

GND

P Ground

108 UART2_DCD

109 UART3_DCD

110 UART2_DSR

111 UART3_DSR

UART2 data-Carrier-Detect signal Pull high with

pin. 100Kohm

UART3 data-Carrier-Detect signal Pull high with

pin. 100Kohm

UART2 Data-Set-Ready signal pin. Pull high with

100Kohm

UART3 Data-Set-Ready signal pin. Pull high with

100Kohm

112

UART2_TXD

O UART2 Transmit signal pin. If user Pull high with

doesn’t need UART2 function, user 100Kohm

could use this pin as GPIO. The

pin connects to SoC PXA255

GPIO43.

113 UART3_RXD

114 UART2_RXD

UART3 Receive signal pin. If user Pull high with

doesn’t need UART3 function, user 100Kohm

could use this pin as GPIO. The

pin connects to SoC PXA255

GPIO46.

UART2 Receive signal pin. If user Pull high with

doesn’t need UART2 function, user 100Kohm

could use this pin as GPIO. The

pin connects to SoC PXA255

GPIO42.

115

UART3_RTS

O UART3 Request-to-Send signal

pin.

Pull high with

100Kohm

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116

117

UART2_CTS

UART2 Clear-to-Send signal pin. If Pull high with

user doesn’t need UART2 function, 100Kohm

user could use this pin as GPIO.

The pin connects to SoC PXA255

GPIO44.

UART3_TXD

O UART3 Transmit signal pin. If user Pull high with

doesn’t need UART3 function, user 100Kohm

could use this pin as GPIO. The

pin connects to SoC PXA255

GPIO47.

118 UART2_DTR

O UART Data-Terminal-Ready signal Pull high with

pin.

100Kohm

119

120

UART3_CTS

UART2_RI

UART3 Clear-to-Send signal pin. Pull high with

100Kohm

UART2 Ring Indicator signal pin. Pull high with

100Kohm

121 UART3_DTR

122 UART3_RI

O UART3 Data-Terminal-Ready

signal pin.

Pull high with

100Kohm

UART3 Ring Indicator signal pin. Pull high with

100Kohm

UART1 Data-Set-Ready signal pin. Pull high with

100Kohm

UART1 Data-Carrier-Detect signal Pull high with

pin.

UART1 Clear-to-Send signal pin. Pull high with

100Kohm

UART1 Receive signal pin.

123 UART1_DSR

124 UART1_DCD

100Kohm

125

UART1_CTS

126 UART1_RXD

Pull high with

100Kohm

127

128

UART1_RTS

UART1_TXD

O UART1 Request-to-Send signal

pin.

O UART1 Transmit signal pin.

Pull high with

100Kohm

Pull high with

100Kohm

129 UART1_DTR

O UART1 Data-Terminal-Ready

signal pin.

Pull high with

100Kohm

130

131

GND

UART1_RI

P Ground

UART Ring Indicator signal pin.

Pull high with

100Kohm

132

133

134

135

136

137

N.C.

GND

- N.C. just float this pin.

P Ground

O LCD power control signal. User

can use this pin to control the LCD

logic power MOS switch to achieve

power-saving.

VDD_ENA

No pulling

138

139

N.C.

VEE_ENA

- N.C. just float this pin.

O STN LCD VEE power control

signal. User can use this pin to

No pulling

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control STN LCD VEE power MOS

switch to achieve power-saving.

140

141

N.C.

VBK_ENA

- N.C. just float this pin.

O LCD back light inverter power

control signal. User can use this

pin to control the LCD backlight

inverter to achieve power-saving.

IO USB host port1 D- data line.

- N.C. just float this pin.

IO USB host port1 D+ data line.

- N.C. just float this pin.

No pulling

142

143

144

145

146

147

USB_N1

N.C.

USB_P1

N.C.

No pulling

N.C.

- N.C. just float this pin.

148 UART5_RXD

UART5 Receive signal pin.

Pull high with

100Kohm

Pull high with

100Kohm

149 UART4_RXD

UART5 Receive signal pin.

150

151

152

UART5_RTS

UART4_TXD

UART5_TXD

O UART5

signal pin.

O UART4 Transmit signal pin.

Data-Terminal-Ready Pull high with

100Kohm

Pull high with

100Kohm

Pull high with

O UART5 Transmit signal pin.

100Kohm

153

154

155

156

N.C.

- N.C. just float this pin.

157 nVBRIR_INC O One of LCD inverter backlight No pulling

brightness control signals.

nVBRIR_INC is used to increase

or decrease Wiper Control.

Advantech suggests to connect the

pin to DS1804 1^stpin.

158

CRT_R

AO The red CRT output.

No pulling

159 nVBRIR_UnD O One of LCD inverter backlight No pulling

brightness control signals.

nVBRIR_UnD is used be Up/Down

Control. Advantech suggests to

connect the pin to DS1804 2^ndpin.

AO The Green CRT output. No pulling

O One of LCD inverter backlight No pulling

brightness control signals.

160

161

CRT_G

VBRIR_CS

VBRIR_CS is used be chip select

pin. Advantech suggests to

connect the pin to DS1804 7^thpin.

AO The blue CRT output. No pulling

162

CRT_B

163 nVCONR_INC O One of STN LCD contrast control No pulling

signals. nVCONR_INC is used be

increase/decrease Wiper Control

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pin. Advantech suggests to

connect the pin to DS1804 1^stpin.

164 CRT_HSYNC AO Horizontal sync for the CRT.

No pulling

165

VCONR_CS

O One of STN LCD contrast control No pulling

signals. VCONR_CS is used be

chip

select

pin.

Advantech

suggests to connect the pin to

DS1804 7^thpin.

166 CRT_VSYNC AO Vertical sync for the CRT.

No pulling

167 VCONR_UnD O One of STN LCD contrast control No pulling

signals. VCONR_UnD is used be

Up/Down

Control.

Advantech

suggests to connect the pin to

DS1804 2^ndpin.

168

169

CRT_SDA

CRT_CLK

- Reserved for future use. User can Pull high with

connect the pin to CRT I2C data 4.71Kohm

pin or just float it.

- Reserved for future use. User can Pull high with

connect the pin to CRT I2C clock 4.71Kohm

pin or just float it.

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

N.C.

O B0 in 24-bit TFT mode.

O B in 24-bit TFT mode.

O G in 24-bit TFT mode.

O R in 24-bit TFT mode.

- N.C. just float this pin.

No pulling

196 FLM_VSYNC O Flat Panel TFT Vertical Sync/STN No pulling

Frame Pulse. For TFT displays,

this output connects to the Vertical

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Sync input of the LCD panel. For

STN displays, this output connects

to the Frame Clock input of the

LCD panel.

This output indicates the start of a

new frame of pixels. The panel

needs to reset its line pointers to

the top of the screen.

197

LP_HSYNC

O Flat Panel TFT Vertical Sync/STN No pulling

Frame Pulse. For TFT displays,

this output connects to the Vertical

Sync input of the LCD panel. For

STN displays, this output connects

to the Frame Clock input of the

LCD panel.

This output indicates the start of a

new frame of pixels. The panel

needs to reset its line pointers to

the top of the screen.

198

199

GND

M_DE

P Ground

O Flat Panel Display Enable. This No pulling

signal is used as a data enable

when the pixel clock needs to latch

pixel data.

200

SHCLK

O Flat Panel Pixel Clock. The active No pulling

edge of FPCLK is programmable.

The LCD panel uses this clock

when loading pixel data into its

Line Shift register. This signal

connects to the TXCLK input of the

LVDS transmitter.

¦ 100-pin B2B connector Pin Out Table (X1 connector, For AMI

interface)

No.

Default

state

Signals

Type

Description

Static chip selects. Chip selects to

static memory devices such as ROM

and

Flash.

Individually

programmable in the memory

configuration registers. This pin can

be used with variable latency I/O

devices. nBUF_CS2 directly connect

to SoC PXA255 nCS2. User could

use this pin as chip select pin to

control the solution IC on carrier

board. This pin is reserved for user

to use.

Pull-high

with 100K

ohm

B1 nBUF_CS2

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A1 ADDR15

SoC PXA255 system address 15

No pulling

B2 ADDR14

A2 ADDR13

B3 ADDR12

A3 ADDR11

B4 ADDR10

A4 ADDR9

B5 ADDR8

A5 ADDR24

B6 ADDR25

SoC PXA255 system address 14

SoC PXA255 system address 13

SoC PXA255 system address 12

SoC PXA255 system address 11

SoC PXA255 system address 10

SoC PXA255 system address 9

SoC PXA255 system address 8

SoC PXA255 system address 24

SoC PXA255 system address 25

Memory output enable pin. Connect

A6 nBUF_OE

B7 ADDR20

A7 nBUF_WE

B8 ADDR22

to the output enables of memory No pulling

devices to control data bus drivers.

SoC PXA255 system address 20

Memory write enable. Connect to the

write

enables of memory devices.

SoC PXA255 system address 22

Read/Write for static interface.

No pulling

BUF_RD_nW

Signals that the current transaction No pulling

is a read or write.

B9 GND

Ground

Variable Latency I/O Ready pin.

Notifies the memory controller when

an external bus device is ready to

transfer data.

Pull high

with

100Kohm

A9 BUF_RDY

B10 DATA15

A10 DATA14

B11 DATA13

A11 DATA12

B12 DATA11

A12 DATA10

B13 DATA9

A13 DATA8

B14 DATA31

A14 DATA30

B15 DATA29

A15 DATA28

B16 DATA27

A16 DATA26

B17 DATA25

A17 DATA24

IO SoC PXA255 system data 15

IO SoC PXA255 system data 14

IO SoC PXA255 system data 13

IO SoC PXA255 system data 12

IO SoC PXA255 system data 11

IO SoC PXA255 system data 10

IO SoC PXA255 system data 9

IO SoC PXA255 system data 8

IO SoC PXA255 system data 31

IO SoC PXA255 system data 30

IO SoC PXA255 system data 29

IO SoC PXA255 system data 28

IO SoC PXA255 system data 27

IO SoC PXA255 system data 26

IO SoC PXA255 system data 25

IO SoC PXA255 system data 24

SDRAM RAS. Connect to the row

No pulling

nBUF_SDRA

B18

address strobe (RAS) pins for all No pulling

banks of SDRAM.

SDRAM CS for bank 0. Connect to

nBUF_SDCS

the chip select (CS) pin for SDRAM.

A18

No pulling

For

the

PXA255

processor

nBUF_SDCS0 can be Hi-Z.

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SDRAM DQM for data byte 0.

B19 BUF_DQM0

Connect to the data output mask No pulling

enables (DQM) for SDRAM.

SDRAM DQM for data byte 2.

Connect to the data output mask No pulling

enables (DQM) for SDRAM.

SDRAM DQM for data byte 3.

Connect to the data output mask No pulling

enables (DQM) for SDRAM.

A19 BUF_DQM2

B20 BUF_DQM3

PCMCIA wait. (input) Driven low by

Pull high

the PCMCIA card to extend the

with

A20 nBUF_PWAIT

length of the transfers to/from the

100Kohm

PXA255 processor.

SDRAM Clock 1. Connect SDCLK

[1] to the clock pins of SDRAM in

bank pairs 0/1. They are driven by

either the internal memory controller

clock, or the internal memory

controller clock divided by 2. At

reset, all clock pins are free running

BUF_SDCLK

at the divide by 2 clock speed and

may be turned off via free running

B21

No pulling

control register bits in the memory

controller. The memory controller

also provides control register bits for

clock division and deassertion of

each SDCLK pin. SDCLK[2:1]

control register assertion bits are

always deasserted upon reset.

SDRAM and/or Synchronous Static

Memory clock enable. Connect to No pulling

the clock enable pins of SDRAM. It is

deasserted during sleep. SOM-255F

BUF_SDCKE1 is always deasserted is

upon reset. The memory controller BUF_SDC

(For

BUF_SDCKE

A21

provides control register bits for

deassertion.

KE1)

B22 GND

Ground

A22 ADDR0

B23 ADDR1

A23 ADDR2

B24 ADDR3

A24 ADDR4

B25 ADDR5

A25 ADDR6

B26 ADDR7

A26 ADDR16

B27 ADDR17

A27 ADDR18

SoC PXA255 system address 0

SoC PXA255 system address 1

SoC PXA255 system address 2

SoC PXA255 system address 3

SoC PXA255 system address 4

SoC PXA255 system address 5

SoC PXA255 system address 6

SoC PXA255 system address 7

SoC PXA255 system address 16

SoC PXA255 system address 17

SoC PXA255 system address 18

No pulling

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B28 ADDR19

SoC PXA255 system address 19

SoC PXA255 system address 21

SoC PXA255 system address 23

No pulling

A28 ADDR21

B29 ADDR23

A29 DATA0

B30 DATA1

A30 DATA2

B31 DATA3

A31 DATA4

B32 DATA5

A32 DATA6

B33 DATA7

A33 DATA16

B34 DATA17

A34 DATA18

B35 DATA19

A35 DATA20

B36 DATA21

A36 DATA22

B37 DATA23

IO SoC PXA255 system data 0

IO SoC PXA255 system data 1

IO SoC PXA255 system data 2

IO SoC PXA255 system data 3

IO SoC PXA255 system data 4

IO SoC PXA255 system data 5

IO SoC PXA255 system data 6

IO SoC PXA255 system data 7

IO SoC PXA255 system data 16

IO SoC PXA255 system data 17

IO SoC PXA255 system data 18

IO SoC PXA255 system data 19

IO SoC PXA255 system data 20

IO SoC PXA255 system data 21

IO SoC PXA255 system data 22

IO SoC PXA255 system data 23

SDRAM CAS. Connect to the

nBUF_SDCA

A37

column address strobe (CAS) pins No pulling

for all banks of SDRAM.

SDRAM CS for banks 2. Connect to

the chip select (CS) pins for SDRAM.

For the PXA255 processor nSDCS0

nBUF_SDCS

B38

No pulling

can be Hi-Z, Nsdcs1-3 cannot.

SDRAM DQM for data bytes 1.

Connect to the data output mask No pulling

enables (DQM) for SDRAM.

A38 BUF_DQM1

SDRAM

Clock

Connect

BUF_SDCLK[2] to the clock pins of

SDRAM in bank pairs 2/3. They are

driven by either the internal memory

controller clock, or the internal

memory controller clock divided by

2. At reset, all clock pins are free

running at the divide by 2 clock

speed and may be turned off via free No pulling

running control register bits in the

memory controller. The memory

controller also provides control

deassertion of each SDCLK pin.

BUF_SDCLK

B39

SDCLK[2:1]

control

assertion bits are always deasserted

upon reset.

IO Select 16. Acknowledge from the Pull high

A39 nBUF_IOIS16

PCMCIA card that the current

with

address is a valid 16 bit wide I/O 100Kohm

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address.

PCMCIA write enable. Performs

writes to PCMCIA memory and to

PCMCIA attribute space. Also used No pulling

as the write enable signal for

Variable Latency I/O.

B40 nBUF_PWE

GPIO pin. Advantech default

function is used as matrix Keypad

IRQ. The pin directly connects to

PXA255 GPIO2 (L13 pin). If user No pulling

doesn’t use the matrix key pad

function, use can use this pin as

GPIO pin.

A40 KEYPAD_IRQ

B41

N.C.

N.C. just float this pin.

No pulling

(For

SOM-255F

PXA_GPIO

GPIO pin. The pin directly connects

IO to PXA255 GPIO7 (G15 pin). This

GPIO pin is available for user to use.

A41 PXA_GP7

Advantech use this pin to control

companion chip as IRQ function.

The pin is not available for CSB

design

SOM-A2558

B42 EVA_IRQ

SOM-A255F platform. SOM-A2558

& SOM-A255F user must float this

pin. This pin is directly connected to

SoC PXA255 GPIO9(F12).

Advantech default function is used

as external 16C950 solution IC IRQ.

The pin directly connects to PXA255

GPIO10 (F7 pin). If user doesn’t No pulling

design 16C950 on CSB to expand

COM function, user could use this

pin as GPIO.

Advantech default function is used

as external LAN solution IC IRQ. The

pin directly connects to PXA255

GPIO17 (D12 pin). If user doesn’t No pulling

design the other LAN chip on CSB to

expand LAN function, user could use

this pin as GPIO.

C950_485_IR

A42

B43 LAN1_IRQ

Advantech default function is used

as external USB host solution IC

IRQ. The pin directly connects to

PXA255 GPIO27 (B9 pin). If user

doesn’t design the other USB

A43 USB_IRQ

No pulling

solution chip on CSB to expand USB

host function, user could use this pin

as GPIO.

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Advantech default function is used

as external 16C954 solution IC IRQ.

The pin directly connects to PXA255

GPIO32 (A16 pin). If user doesn’t No pulling

design 16C950 on CSB to expand

COM function, user could use this

pin as GPIO.

B44 C954_IRQ

GPIO pin. The pin directly connects

A44 PXA_GP81

B45 PXA_GP82

A45 PXA_GP83

B46 PXA_GP84

IO to PXA255 GPIO81 (F16 pin). This No pulling

GPIO pin is available for user to use.

GPIO pin. The pin directly connects

IO to PXA255 GPIO82 (E16 pin). This No pulling

GPIO pin is available for user to use.

GPIO pin. The pin directly connects

IO to PXA255 GPIO83 (E15 pin). This No pulling

GPIO pin is available for user to use.

GPIO pin. The pin directly connects

IO to PXA255 GPIO84 (D16 pin). This No pulling

GPIO pin is available for user to use.

Static chip selects. Chip selects to

static memory devices such as ROM

and

Flash.

Individually

programmable in the memory

configuration registers. nBUF_CS1 Pull high

A46 nBUF_CS1

can be used with variable latency I/O

with

devices. Advantech default uses this 100Kohm

pin as storage flash chip select pin. If

no special application, Advantech

strongly suggest user to open this

pin in CSB.

Static chip selects. Chip selects to

static memory devices such as ROM

and Flash. Individually. nBUF_CS4

can be used with variable latency I/O

devices.

Pull high

Advantech default use this pin as

with

B47 nBUF_CS4

companion chip chip select pin.

100Kohm

nBUF_CS4 pin is used for

EVA-C210 on SOM-A255F

SOM-A2552 series. If no special

application, Advantech strongly

suggest user to open this pin in CSB.

Static chip selects. Chip selects to

static memory devices such as ROM

and Flash. Individually

programmable in the memory

configuration registers. nBUF_CS3

can be used with variable latency I/O

devices.

Pull high

with

100Kohm

A47 nBUF_CS3

Advantech uses the pin as I/O

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memory

block.

About

detail

description,

please

reference

“SOM-A255x series Memory and

Interrupt Map”.

Static chip selects. Chip selects to

static memory devices such as ROM

and

Flash.

Individually

programmable in the memory

configuration registers. nBUF_CS5

can be used with variable latency I/O

devices.

Advantech default uses the pin as

display chip chip select pin.

nBUF_CS4 pin is used for SM501 on

SOM-A2552 & SOM-A255F series. If

no special application, Advantech

strongly suggest user to open this

pin in CSB.

Pull high

with

100Kohm

B48 nBUF_CS5

Channel 1 DMA Request. Notifies

the DMA Controller that an external

device requires a DMA transaction. If

user wants to design a controller in

CSB with DMA mode, please check Pull low

with [email protected] first. with 1Kohm

If use doesn’t want to use this pin as

DMA_REQ, use could use the pin as

GPIO. The pin connects to SoC

PXA255 GPIO19.

A48 DMA_REQ1

Memory Controller alternate bus

master request. Allows an external

device to request the system bus

from the Memory Controller. If user

wants to design a controller in CSB

Pull low

B49 MBREQ

with this pin function, please check

with 1Kohm

with [email protected] first.

If use doesn’t want to use this pin as

DMA_REQ, use could use the pin as

GPIO. The pin connects to SoC

PXA255 GPIO14.

Channel

DMA acknowledge.

Notifies an external device that it has

been acknowledged the DMA

controller. If user wants to design a

controller in CSB with DMA mode,

A49 DMA_ACK1

please

check

with No pulling

[email protected] first.

If use doesn’t want to use this pin as

DMA_ACK, use could use the pin as

GPIO. The pin connects to SoC

PXA255 GPIO22.

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Memory Controller grant. Notifies an

external device that it has been

granted the system bus. If user

wants to design a controller in CSB

with this pin function, please check Pull low

with [email protected] first. with 1Kohm

If use doesn’t want to use this pin as

MBGNT, use could use the pin as

GPIO. The pin connects to SoC

PXA255 GPIO13.

B50 MBGNT

3.6864 MHz clock. Output from

A50 3M6864

No pulling

3.6864 MHz oscillator.

¦ 100-pin B2B connector Pin Out Table (X3 connector for PCI, ZV port,

MMC interface and Misc. function)

No.

Signals

Typ

Model

Default state

N.C.

GND

N.C.

GND

N.C.

- N.C. just float this pin.

P Ground

- N.C. just float this pin.

P Ground

B10

A10

B11

A11

B12

A12

B13

A13

B14

A14

B15

- N.C. just float this pin.

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A15

B16

A16

B17

A17

B18

A18

B19

A19

B20

A20

B21

A21

B22

A22

B23

A23

B24

A24

B25

A25

B26

A26

B27

A27

B28

A28

B29

A29

B30

A30

B31

A31

B32

A32

B33

A33

B34

A34

B35

N.C.

GND

N.C.

GND

N.C.

- N.C. just float this pin.

P Ground

- N.C. just float this pin.

P Ground

- N.C. just float this pin.

- N.C. float this pin.

SD/MMC interface card detect pin. Pull high with

If user doesn’t need MMC/SD

function, user could use this pin as

GPIO. The pin connects to SoC

PXA255 GPIO12.

MMC clock. Clock signal for the

MMC Controller. If user doesn’t

100Kohm

nMMCD

MMCLK

A35

No pulling

O need MMC/SD function, user could

use this pin as GPIO. The pin

connects to SoC PXA255 GPIO6.

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B36

Chip select pin for MMC controller. No pulling (For

If user doesn’t need MMC/SD

SOM-255F is

MMDAT3/

MMCCS0

O function, user could use this pin as MMCCS0)

GPIO. The pin connects to SoC

PXA255 GPIO8.

A36

B37

Multimedia Card Command.

Pull high with

10Kohm

Pull high with

10Kohm (For

SOM-255F is

MMCMD

MMDAT0

Multimedia Card Data pin.

MMCDAT)

A37

B38

A38

B39

A39

B40

N.C.

- N.C. float this pin.

16-bit R[4] video pixel input for

No pulling

RGB

ZV15

ZV14

ZV13

ZV12

ZV11

5:6:5 mode or Y[7] video pixel input

for YUV 4:2:2 mode.

16-bit R[3] video pixel input for

RGB

5:6:5 mode or Y[6] video pixel input

for YUV 4:2:2 mode.

16-bit R[2] video pixel input for

RGB

5:6:5 mode or Y[5] video pixel input

for YUV 4:2:2 mode.

16-bit R[1] video pixel input for

RGB

5:6:5 mode or Y[4] video pixel input

for YUV 4:2:2 mode.

16-bit R[0] video pixel input for

RGB

A40

B41

A41

B42

No pulling

5:6:5 mode or Y[3] video pixel input

for YUV 4:2:2 mode.

A42

B43

A43

B44

16-bit G[5] video pixel input for

RGB 5:6:5 mode or Y[2] video pixel

input for YUV 4:2:2 mode.

16-bit G[4] video pixel input for

RGB 5:6:5 mode or Y[1] video pixel

input for YUV 4:2:2 mode.

16-bit G[3] video pixel input for

RGB 5:6:5 mode or Y[0] video pixel

input for YUV 4:2:2 mode.

16-bit G[2] video pixel input for

RGB 5:6:5 mode, U[7] video pixel

input for YUV 4:2:2 mode, or V[7]

video pixel input for YUV 4:2:2

No pulling

ZV10

ZV9

ZV8

ZV7

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mode.

A44

B45

A45

B46

A46

B47

A47

16-bit G[1] video pixel input for

RGB 5:6:5 mode, U[6] video pixel

input for YUV 4:2:2 mode, or V[6]

video pixel input for YUV 4:2:2

mode.

16-bit G[0] video pixel input for

RGB 5:6:5 mode, U[5] video pixel

input for YUV 4:2:2 mode, or V[5]

video pixel input for YUV 4:2:2

mode.

16-bit B[4] video pixel input for

RGB 5:6:5 mode, U[4] video pixel

input for YUV 4:2:2 mode, or V[4]

video pixel input for YUV 4:2:2

mode.

16-bit B[3] video pixel input for

RGB 5:6:5 mode, U[3] video pixel

input for YUV 4:2:2 mode, or V[3]

video pixel input for YUV 4:2:2

mode.

16-bit B[2] video pixel input for

RGB 5:6:5 mode, U[2] video pixel

input for YUV 4:2:2 mode, or V[2]

video pixel input for YUV 4:2:2

mode.

16-bit B[1] video pixel input for

RGB 5:6:5 mode, U[1] video pixel

input for YUV 4:2:2 mode, or V[1]

video pixel input for YUV 4:2:2

mode.

16-bit B[0] video pixel input for

RGB 5:6:5 mode, U[0] video pixel

input for YUV 4:2:2 mode, or V[0]

video pixel input for YUV 4:2:2

mode.

No pulling

ZV6

ZV5

ZV4

ZV3

ZV2

ZV1

ZV0

B48

A48

B49

TV-in control serial data

input/output (I2C-bus).

Pull high with

4.71Kohm

Pull high with

4.71Kohm

SDAZV

SCLZV

TV-in control serial clock output

(I2C-bus)

Horizontal Sync. A falling or rising

edge on this input indicates the

end of the current scan line and the

beginning of the next.

No pulling

VPHREF

GND

A49

B50

P Ground

Vertical Sync. A rising or falling

No pulling

edge on

VPVSYNC

this input indicates the end of the

current capture field and the

beginning

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of the next one. The state of

VPHSYNC

determines whether the current

capture

field is ODD (VPHREF is High on

the

active edge of VPVSYNC) or

EVEN

(VPHREF is Low on the active

edge of

VPVSYNC).

A50

Pixel Clock. VPCLK is the

reference clock for data on the

ZV[31:0] video pixel bus.

No pulling

VPCLK

2.2 function description

2.2.1 System Bus

System Bus includes PXA255 address bus, data bus, memory control

signals and GPIOs.

System Bus enters CSB by X1. In order to make sure that system bus

signals have perfect electrical waves, System Bus signals are driven by buffers

to enhance signals performance.

DataBus

StrengthedDataBus

AddressBus

Buffers

StrengthedAddressBus

PXA255

X1conn.

StrengthedM emoryControl

signals

M emoryControl

signals

The buffers signals direction control is control by CPLD on SOM-A255x

module.

2.2.2 COM

SOM-A255x series (SOM-A2552, SOM-A2558, SOM-A255F) all support 5

x RS-232 ports: 3 full function (FF) RS-232 ports, 1x 2-wire (RX, TX) RS-232

and 1x 3-wire (RX, TX, RTS) RS-232 port. COM port function assignments are

as following:

COM1: FF RS-232

COM2: FF RS-232

COM3: FF RS-232

COM4: 2-wire (RX, TX) RS-232

COM5: 3-wire (RX, TX, RTS) RS-232

All RS-232 ports are TTL levels.

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According to user target CSB demand, user could define COM5 as 3-wire

(RX, TX, RTS) RS-232 port or pass through RS-485 transceiver to act as

RS-485 function. User could references “Advantech SOM-A255x series CSB

design guide “to design the COM5.

2.2.3 USB 1.1 Host

SOM-A255F & SOM-A2558 series supports 2 USB host ports.

SOM-A2552 series supports 1 USB host port. The USB host ports on the

SOM-A255x are USB 1.1 compatible. The default Windows CE.NET and Linux

on board support USB keyboards, mice and mass storage devices. User could

check the " SOM-A255x series verified compatible peripherals list " to know the

verified compatible peripherals. If user wants to connect other devices, it may

take customization on the Windows CE.

2.2.4 USB 1.1 client

The USB client port on the SOM-A255x is USB 1.1 compatible. USB client

connector is used to communicate with master device (ex: PC) for ActiveSync.

About SOM-A255x series ActiveSync installation, please reference to

“Installation Guide-Advantech RISC platform with Microsoft ActiveSync 3.7”.

2.2.5 T/S

SOM-A255x series supports 4-wires (X+, X-, Y+, Y-) resistive T/S

interface.

2.2.6 PCMCIA/CF

All SOM-A255x series supports 2 PCMCIA interface (I/F) or 2 CF I/F or 1

PCMCIA & 1 CF I/F. User could check “ SOM-A255x Series Carrier Board

Design Guide “ to know how to design the I/F.

PCMCIA/CF I/F power control circuit is designed on SOM module, so

PCMCIA/CF I/F is hot-swappable.

Advantech strongly suggest user to design one CF or one PCMCIA

slot on user’s target carrier board, even user doesn’t need this port in

target product. Advantech platform always use CF or PCMCIA slot to be

system S/W upgrading port. If user doesn’t design 1 CF or PCMCIA slot

on carrier board, user will run into trouble when user wants to upgrade

image, boot loader & boot-logo.

2.2.7 SD/MMC

All SOM-A255x series supports 1 slot SD/MMC port. The Multi Media

Card (MMC) is a low cost data storage and communication media. The MMC

controller in the SOM-A255x is compliant with The Multi Media Card System

Specification, Version 2.1. The only exception is one and three byte data

transfers are not supported.

SD/MMC I/F in SOM-A255x only support 1-bit memory mode, not support

I/O mode.

2.2.8 Audio (AC’97 Codec on board)

All SOM-A255x uses Realtek ALC202 AC97 audio Codec on SOM

module. SOM-A255x series provides mono microphone-in, stereo line-in, and

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stereo line-out interface. If users want to drive speakers, users could follow the

“Advantech SOM-A255x series CSB design guide “to design the audio

amplifier on CSB.

2.2.9 CRT-out

SOM-A255F & SOM-A2552 series supplies CRT-out I/F which resolution

is up to 1024*768. CRT-out function comes from SM501. CRT-out signals are

all analog signals; user must follow the analog signals layout rules.

SOM-A2558 series doesn’t support CRT-out function, but user could

design CRT-out solution IC on CSB to add the function on SOM-A2558

platform. About detail implement way, please check “Advantech SOM-A255x

series CSB design guide “.

2.2.10 LCD TTL interface w/LCD Brightness & Contrast Control

interface

SOM-A2552 & SOM-A255F series LCD-out interface comes from SM501.

SOM-A2552 & SOM-A255F LCD-out supports 24 bit and resolution up to

1024*768. SOM-A2552 & SOM-A255F supports both active and passive LCD

displays. SOM-A2558 series LCD-out function comes from SoC PXA255.

SOM-A2558 LCD-out supports 16 bit and resolution up to 800*600.

The LCD signals are 3.3V level in X2. If users’ CSB want to drive 5V level

panel, users could design buffers on CSB to translate LCD signals level. User

could refer “Advantech SOM-A255x series CSB design guide “.

Advantech design LCD brightness control circuit & LCD contrast control

circuit on SOM-A255x series modules. STN LCD panel needs contrast control

signals. In X2, LCD contrast control signals are nVCONR_INC, VCONR_CS

and VCONR_UnD. The control signals are based on DALLAS DS1804 NV

Trimmer Potentiometer to design. Users could check the “Advantech

SOM-A255x series CSB design guide “ to know how to wire. User could check

“to know how to control.

Brightness control signals are used to control the LCD backlight inverter

lamp current. In X2, LCD brightness control signals are nVBRIR_INC,

VBRIR_CS and nVBRIR_UnD. The control signals are based on DALLAS

DS1804 NV Trimmer Potentiometer to design. Users could check the

“Advantech SOM-A255x series CSB design guide “to know how to wire. User

could check appendix about SOM-A255F memory map to know how to control.

If user wants to connect CSB to LVDS type LCD, user could reference

“Advantech SOM-A255x series CSB design guide “to design LVDS

Transmitter on CSB. SOM-A255x series only support 1 channel LVDS LCD

panel.

The sample images of SOM-A2552, SOM-A255F series could support 4

kinds of display modes:

320x240 TFT: In SOM-A2552 & SOM-A255F module, user

CAN’T verify the performance by Advantech LCD kit

LCD-A057-STQ1-0. Because SOM-A2552 & SOM-A255F

supports 320x240 TFT mode, but LCD-A057-STQ1-0 is 320x240

STN panel.

640x480 TFT: user could verify the performance by Advantech

LCD kit LCD-A064-TTV1-0.

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800x600 TFT: user could verify the performance by Advantech

LCD kit LCD-A104-TTS1-0.

1024x768 TFT: user could verify the performance by Advantech

LCD kit LCD-A150-TTX2-0.

Except 320x240 TFT mode, user could verify the LCD-out function by

Advantech LCD kit. Advantech LCD kit LCD-A057-STQ1-0 is 320x240 STN

type LCD, not TFT type, so user couldn’t verify the 320x240 TFT function by

sample images.

The sample images of SOM-A2558 series could support 4 kinds of display

modes:

320x240 STN: User can use Advantech LCD kit

LCD-A057-STQ1-0 to evaluate the LCD-out performance of

SOM-A2558 platform.

640x480 TFT: User can use Advantech LCD kit

LCD-A064-TTV1-0 to evaluate the LCD-out performance of

SOM-A2558 platform.

2.2.11 Zoom Video (ZV) port

SOM-A255F & SOM-A2552 series ZV port comes from SM501.

SOM-A2558 series don’t support the function. ZV Port can interface with video

decoders, such as NTSC/PAL decoders, MPEG-2 decoders, and JPEG Codec.

The ZV Port supports resolutions up to 1280x1024. It directly accepts digitized

RGB or YUV signals, and does not accept analog signals.

In 16-bit mode, the ZV [15:8] signals are the most-significant eight video

pixel inputs. In 8-bit mode, these signals are not used. In 16-bit mode, the ZV

[7:0] signals are the least-significant eight video pixel inputs. In 8-bit mode,

these signals are the only eight video pixel inputs.

About how to wire the ZV port with NTSC/PAL decoders, please check

“Advantech SOM-A255x series CSB design guide “.

2.2.12 System Reset Interface

SOM-A255x series all supply 3 kinds of System reset interface as

following:

nRESET : hardware reset input pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

nSW_RESET : software rest input pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

nSA_PWR_ON : Suspend/wake-up pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

2.2.13 Buzzer Control Interface

SOM-A255x series all support this function. Buzzer-out control signal is

designed to control the buzzer on/off status.

If users want to design buzzer on CSB to be reminding or alarm system,

user could reference “Advantech SOM-A255x series CSB design guide “.

If users want to control the buzzer, users can check the memory map to

do it.

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2.2.14 System Management Bus (SM Bus) interface

SOM-A255x series SM Bus is implemented by PXA255 I2C bus. If users’ CSB is

SOM-A255x SM Bus to battery pack to monitor battery status. SOM-A255x series SM

bus directly support TI BQ2040 gas gauge IC.

2.2.15 Power-input

SOM-A255x needs 3.3V & 5V DC power inputs. The power sources (3.3V,

5V) must always be supplied even in system sleep mode. SOM-A255x power

management is completely implemented on itself; users’ CSB doesn’t need to

control the power supply to SOM-A255x.

2.2.16 Back-up power input

If user want to keep the real time clock(RTC) works well in power off mode,

user should connect the coin battery positive pin to BAT-VCC in X2

directly .The back-up power pin (BAT_VCC) is the only power source to supply

RTC power when SOM-A255x system power (3.3V, 5V) is off.

The coin battery must be 3.0V Li-ion coin type.

The coin battery charging circuit is designed on SOM-A255x, so user

shouldn’t and needn’t design the charging circuit on CSB.

If users don’t need RTC function in CSB, just let the BAT_VCC pin open.

2.2.17 PCI I/F (Thru X3)

SOM-A2558 & SOM-A255F could support 4 channels PCI device

controllers on CSB. The PCI clock is 33 MHz. PCI I/F comes from Advantech

EVA-C210 I/O enhancement chip. The PCI I/F feature is as followings:

Compatible with PCI specification version 2.2

32-bit data bus interface

Built-in PCI bus arbiter

Supports up to 3 individual external bus master devices

Support PCI Bus Controller (FPCI) to PCI slave I/O read/write,

memory read/write, configuration read/write cycle

PCI Bus master support all disconnect types (Master-Abort,

Target-Abort, Target-Retry, Disconnect with data, Disconnect without

data)

SOM-A2552 series don’t support PCI I/F.

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