Am186 ER and Am188 ER
Microcontrollers
User’s Manual
Download from Www.Somanuals.com. All Manuals Search And Download.
IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU.
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a
customer training center. Expert technical assistance is available from the worldwide staff
of AMD field application engineers and factory support staff to answer E86™ family
hardware and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides a toll-free number for direct access to
our corporate applications hotline. Also available is the AMD World Wide Web home page
and FTP site, which provides the latest E86 family product information, including technical
information and data on upcoming product releases.
For technical support questions on all E86 products, send E-mail to [email protected].
Corporate Applications Hotline
800-222-9323
toll-free for U.S. and Canada
44-(0) 1276-803-299
U.K. and Europe hotline
World Wide Web Home Page and FTP Site
To access the AMD home page go to http://www.amd.com.
To download documents and software, ftp to ftp.amd.com and log on as anonymous using
your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com.
Questions, requests, and input concerning AMD’s WWW pages can be sent via E-mail to
Documentation and Literature
Free E86 family information such as data books, user’s manuals, data sheets, application
notes, the FusionE86SM Partner Solutions Catalog, and other literature is available with a
simple phone call. Internationally, contact your local AMD sales office for complete E86
family literature.
Literature Ordering
800-222-9323
512-602-5651
512-602-7639
800-222-9323
toll-free for U.S. and Canada
direct dial worldwide
fax
AMD Facts-On-Demand™ faxback service
toll-free for U.S. and Canada
iii
Download from Www.Somanuals.com. All Manuals Search And Download.
iv
Download from Www.Somanuals.com. All Manuals Search And Download.
TABLE OF CONTENTS
PREFACE
INTRODUCTION AND OVERVIEW
Design Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
User’s Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
AMD Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
E86™ Microcontroller Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
CHAPTER 1
FEATURES AND PERFORMANCE
1.1 Key Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3.3 Serial Communications Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4 Third-Party Development Support Products . . . . . . . . . . . . . . . . . . . . . . . 1-8
CHAPTER 2
PROGRAMMING
2.1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Memory Organization and Address Generation . . . . . . . . . . . . . . . . . . . . 2-3
2.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5 Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.6 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
CHAPTER 3
SYSTEM OVERVIEW
3.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.2 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.3.1 Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.3.2 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.3.3 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . . 3-21
3.4 Clock and Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4.1 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4.2 Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.4.3 External Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.4.4 System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Peripheral Control Block Relocation Register
(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . . 4-5
4.1.3 Processor Release Level Register (PRL, Offset F4h). . . . . . . . . . 4-6
4.1.4 Power-Save Control Register (PDCON, Offset F0h). . . . . . . . . . . 4-7
4.2 Initialization and Processor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table of Contents
v
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5
CHIP SELECT UNIT
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Chip Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 Ready and Wait-State Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.4 Chip Select Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.5 Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . . 5-4
5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . . 5-6
5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) . . . 5-8
5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . . 5-10
5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . . 5-12
CHAPTER 6
INTERNAL MEMORY
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Interaction with External RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.3 Emulator and Debug Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.1 Internal Memory Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.2 Show Read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.4 Internal Memory Chip Select Register (IMCS, Offset ACh) . . . . . . . . . . . 6-3
CHAPTER 7
CHAPTER 8
REFRESH CONTROL UNIT
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Memory Partition Register (MDRAM, Offset E0h) . . . . . . . . . . . . 7-1
7.1.2 Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . . 7-2
7.1.3 Enable RCU Register (EDRAM, Offset E4h) . . . . . . . . . . . . . . . . 7-2
INTERRUPT CONTROL UNIT
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1.1 Interrupt Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1.2 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1.3 Maskable and Nonmaskable Interrupts. . . . . . . . . . . . . . 8-2
8.1.1.4 Interrupt Enable Flag (IF) . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.5 Interrupt Mask Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.6 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.7 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.8 Software Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.2 Interrupt Conditions and Sequence. . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.2.1 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.2.2 Maskable Hardware Interrupts . . . . . . . . . . . . . . . . . . . . 8-4
8.1.2.3 The Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.2.4 Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.2.5 Returning from the Interrupt . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.3 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.3.1 Nonmaskable Interrupts and Software
Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.3.2 Maskable Hardware Interrupt Priority . . . . . . . . . . . . . . . 8-5
8.1.4 Software Exceptions, Traps, and NMI. . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.4.1 Divide Error Exception (Interrupt Type 00h) . . . . . . . . . . 8-6
8.1.4.2 Trace Interrupt (Interrupt Type 01h) . . . . . . . . . . . . . . . . 8-6
8.1.4.3 Nonmaskable Interrupt—NMI (Interrupt Type 02h). . . . . 8-6
8.1.4.4 Breakpoint Interrupt (Interrupt Type 03h) . . . . . . . . . . . . 8-7
8.1.4.5 INTO Detected Overflow Exception
(Interrupt Type 04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.4.6 Array BOUNDS Exception (Interrupt Type 05h) . . . . . . . 8-7
8.1.4.7 Unused Opcode Exception (Interrupt Type 06h). . . . . . . 8-7
8.1.4.8 ESC Opcode Exception (Interrupt Type 07h) . . . . . . . . . 8-7
8.1.5 Interrupt Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.6 Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . . 8-9
vi
Table of Contents
Download from Www.Somanuals.com. All Manuals Search And Download.
8.2 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.2.5 End-of-Interrupt Write to the EOI Register . . . . . . . . . . . . . . . . . 8-12
8.3 Master Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . 8-13
8.3.1 INT0 and INT1 Control Registers
(I0CON, Offset 38h, I1CON, Offset 3Ah). . . . . . . . . . . . . . . . . . . 8-14
8.3.2 INT2 and INT3 Control Registers
(I2CON, Offset 3Ch, I3CON, Offset 3Eh) . . . . . . . . . . . . . . . . . . 8-16
8.3.3 INT4 Control Register (I4CON, Offset 40h). . . . . . . . . . . . . . . . . 8-17
8.3.4 Timer and DMA Interrupt Control Registers
(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,
Offset 36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.3.5 Watchdog Timer Interrupt Control Register
(WDCON, Offset 42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h). . . . 8-20
8.3.7 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 8-21
8.3.8 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 8-22
8.3.9 In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . . . . . . . . 8-23
8.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 8-24
8.3.11 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 8-25
8.3.12 Poll Status Register (POLLST, Offset 26h) . . . . . . . . . . . . . . . . . 8-26
8.3.13 Poll Register (POLL, Offset 24h). . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.3.14 End-of-Interrupt Register (EOI, Offset 22h). . . . . . . . . . . . . . . . . 8-28
8.4 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.4.1 Slave Mode Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
8.4.2 Slave Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . . 8-29
8.4.3 Timer and DMA Interrupt Control Registers
(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON,
Offset 3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h) . . . 8-30
8.4.4 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 8-31
8.4.5 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 8-32
8.4.6 In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . . . . . . . . 8-33
8.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 8-34
8.4.8 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 8-35
8.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) . . . . . . . . . . 8-36
8.4.10 Interrupt Vector Register (INTVEC, Offset 20h) . . . . . . . . . . . . . 8-37
CHAPTER 9
TIMER CONTROL UNIT
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1 Timer Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 Timer 0 and Timer 1 Mode and Control Registers (T0CON,
Offset 56h, T1CON, Offset 5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) . . . . . . 9-5
9.2.4 Timer Count Registers (T0CNT, Offset 50h, T1CNT,
Offset 58h, T2CNT, Offset 60h). . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.2.5 Timer Maxcount Compare Registers (T0CMPA, Offset 52h,
T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, T1CMPB,
Offset 5Ch, T2CMPA, Offset 62h). . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Table of Contents
vii
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10
DMA CONTROLLER
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 Programmable DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3.1 DMA Control Registers
(D0CON, Offset CAh, D1CON, Offset DAh) . . . . . . . . . . . . . . . . 10-3
10.3.2 DMA Transfer Count Registers
(D0TC, Offset C8h, D1TC, Offset D8h). . . . . . . . . . . . . . . . . . . . 10-5
10.3.3 DMA Destination Address High Register (High Order Bits)
(D0DSTH, Offset C6h, D1DSTH, Offset D6h). . . . . . . . . . . . . . . 10-6
10.3.4 DMA Destination Address Low Register (Low Order Bits)
(D0DSTL, Offset C4h, D1DSTL, Offset D4h) . . . . . . . . . . . . . . . 10-7
10.3.5 DMA Source Address High Register (High Order Bits)
(D0SRCH, Offset C2h, D1SRCH, Offset D2h) . . . . . . . . . . . . . . 10-8
10.3.6 DMA Source Address Low Register (Low Order Bits)
(D0SRCL, Offset C0h, D1SRCL, Offset D0h) . . . . . . . . . . . . . . . 10-9
10.4 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.1 Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.2 DMA Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.3 DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.4 DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.5 DMA Channels on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
CHAPTER 11
ASYNCHRONOUS SERIAL PORT
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.1 Serial Port Control Register (SPCT, Offset 80h) . . . . . . . . . . . . . 11-2
11.2.2 Serial Port Status Register (SPSTS, Offset 82h) . . . . . . . . . . . . 11-4
11.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) . . . . . . . 11-5
11.2.4 Serial Port Receive Data Register (SPRD, Offset 86h). . . . . . . . 11-6
11.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h). . 11-7
CHAPTER 12
SYNCHRONOUS SERIAL INTERFACE
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.1 Synchronous Serial Status Register (SSS, Offset 10h). . . . . . . . 12-3
12.2.2 Synchronous Serial Control Register (SSC, Offset 12h). . . . . . . 12-4
12.2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h)
Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) . . . 12-5
12.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) . . . . . . 12-6
12.3 SSI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
CHAPTER 13
PROGRAMMABLE I/O PINS
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 PIO Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.1 PIO Mode 1 Register (PIOMODE1, Offset 76h) . . . . . . . . . . . . . 13-3
13.2.2 PIO Mode 0 Register (PIOMODE0, Offset 70h) . . . . . . . . . . . . . 13-3
13.3 PIO Direction Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.1 PIO Direction 1 Register (PDIR1, Offset 78h) . . . . . . . . . . . . . . 13-4
13.3.2 PIO Direction 0 Register (PDIR0, Offset 72h) . . . . . . . . . . . . . . 13-4
13.4 PIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4.1 PIO Data Register 1 (PDATA1, Offset 7Ah) . . . . . . . . . . . . . . . . 13-5
13.4.2 PIO Data Register 0 (PDATA0, Offset 74h) . . . . . . . . . . . . . . . . 13-5
13.5 Open-Drain Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
APPENDIX A
REGISTER SUMMARY
viii
Table of Contents
Download from Www.Somanuals.com. All Manuals Search And Download.
LIST OF FIGURES
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 3-1
Am186ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Am188ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Basic Functional System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Processor Status Flags Register (FLAGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Physical Address Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Am186ER Microcontroller Address Bus—Normal Read
and Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-2
Am186ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-3
Figure 3-4
Am188ER Microcontroller Address Bus—Normal Read and Write Operation. 3-20
Am188ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Figure 3-5
Figure 3-6
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 6-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Oscillator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Clock Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Peripheral Control Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Peripheral Control Block Relocation Register (RELREG, offset FEh) . . . . . . . . 4-4
Reset Configuration Register (RESCON, offset F6h) . . . . . . . . . . . . . . . . . . . . 4-5
Processor Release Level Register (PRL, offset F4h). . . . . . . . . . . . . . . . . . . . . 4-6
Power-Save Control Register (PDCON, offset F0h) . . . . . . . . . . . . . . . . . . . . . 4-7
Upper Memory Chip Select Register (UMCS, offset A0h) . . . . . . . . . . . . . . . . . 5-4
Low Memory Chip Select Register (LMCS, offset A2h) . . . . . . . . . . . . . . . . . . . 5-6
Midrange Memory Chip Select Register (MMCS, offset A6h) . . . . . . . . . . . . . . 5-8
PCS and MCS Auxiliary Register (MPCS, offset A8h). . . . . . . . . . . . . . . . . . . 5-10
Peripheral Chip Select Register (PACS, offset A4h) . . . . . . . . . . . . . . . . . . . . 5-12
Internal Memory Chip Select Register (IMCS, offset ACh) . . . . . . . . . . . . . . . . 6-3
Memory Partition Register (MDRAM, offset E0h). . . . . . . . . . . . . . . . . . . . . . . . 7-1
Clock Prescaler Register (CDRAM, offset E2h). . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Enable RCU Register (EDRAM, offset E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
External Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Fully Nested (Direct) Mode Interrupt Controller Connections . . . . . . . . . . . . . 8-10
Cascade Mode Interrupt Controller Connections. . . . . . . . . . . . . . . . . . . . . . . 8-11
INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah) . . . . 8-14
INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh). . . . 8-16
INT4 Control Register (I4CON, offset 40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Timer/DMA Interrupt Control Registers
(TCUCON, DMA0CON, DMA1CON, offsets 32h, 34h, and 36h). . . . . . . . . . . 8-18
Figure 8-8
Figure 8-9
Watchdog Timer Interrupt Control Register (WDCON, offset 42h). . . . . . . . . . 8-19
Serial Port Interrupt Control Register (SPICON, offset 44h) . . . . . . . . . . . . . . 8-20
Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-22
In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Poll Status Register (POLLST, offset 26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Poll Register (POLL, offset 24h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Example EOI Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
End-of-Interrupt Register (EOI, offset 22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Timer and DMA Interrupt Control Registers (T0INTCON, T1INTCON,
T2INTCON, DMA0CON, DMA1CON, offsets 32h, 38h, 3Ah, 34h, and 36h) . . 8-30
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-31
Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-32
In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
Table of Contents
ix
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 8-25
Figure 8-26
Figure 9-1
Specific End-of-Interrupt Register (EOI, offset 22h). . . . . . . . . . . . . . . . . . . . . 8-36
Interrupt Vector Register (INTVEC, offset 20h) . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON,
offsets 56h and 5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 9-2
Figure 9-3
Figure 9-4
Timer 2 Mode and Control Register (T2CON, offset 66h) . . . . . . . . . . . . . . . . . 9-5
Timer Count Registers (T0CNT, T1CNT, T2CNT, offsets 50h, 58h, and 60h) . . 9-6
Timer Maxcount Compare Registers (T0CMPA, T0CMPB, T1CMPA,
T1CMPB, T2CMPA, offsets 52h, 54h, 5Ah, 5Ch, and 62h) . . . . . . . . . . . . . . . . 9-7
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
DMA Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
DMA Control Registers (D0CON, D1CON, offsets CAh and DAh) . . . . . . . . . 10-3
DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h) . . . . . . . 10-5
DMA Destination Address High Register
(D0DSTH, D1DSTH, offsets C6h and D6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Figure 10-5
Figure 10-6
Figure 10-7
DMA Destination Address Low Register
(D0DSTL, D1DSTL, offsets C4h and D4h). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
DMA Source Address High Register
(D0SRCH, D1SRCH, offsets C2h and D2h). . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
DMA Source Address Low Register
(D0SRCL, D1SRCL, offsets C0h and D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Figure 10-8
Figure 10-9
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 12-1
Figure 12-2
Figure 12-3
Figure 12-4
Figure 12-5
Figure 12-6
Figure 13-1
Figure 13-2
Figure 13-3
Figure 13-4
Figure 13-5
Figure 13-6
Figure 13-7
Figure A-1
Source-Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Destination Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Serial Port Control Register (SPCT, offset 80h) . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Serial Port Status Register (SPSTS, offset 82h) . . . . . . . . . . . . . . . . . . . . . . . 11-4
Serial Port Transmit Data Register (SPTD, offset 84h) . . . . . . . . . . . . . . . . . . 11-5
Serial Port Receive Data Register (SPRD, offset 86h) . . . . . . . . . . . . . . . . . . 11-6
Serial Port Baud Rate Divisor Register (SPBAUD, offset 88h) . . . . . . . . . . . . 11-7
Synchronous Serial Status Register (SSS, offset 10h) . . . . . . . . . . . . . . . . . . 12-3
Synchronous Serial Control Register (SSC, offset 12h). . . . . . . . . . . . . . . . . . 12-4
Synchronous Serial Transmit Register (SSD1, SSD0, offsets 14h and 16h). . 12-5
Synchronous Serial Receive Register (SSR, offset 18h) . . . . . . . . . . . . . . . . . 12-6
Synchronous Serial Interface Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Synchronous Serial Interface Multiple Read . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Programmable I/O Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
PIO Mode 1 Register (PIOMODE1, offset 76h) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
PIO Mode 0 Register (PIOMODE0, offset 70h) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
PIO Direction 1 Register (PDIR1, offset 78h). . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
PIO Direction 0 Register (PDIR0, offset 72h). . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
PIO Data 1 Register (PDATA1, offset 7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
PIO Data 0 Register (PDATA0, offset 74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4
x
Table of Contents
Download from Www.Somanuals.com. All Manuals Search And Download.
LIST OF TABLES
Table 2-1
Table 2-2
Table 2-3
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 4-1
Table 4-2
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 9-1
Table 10-1
Table 10-2
Table 10-3
Table 11-1
Table 11-2
Table 11-3
Table 12-1
Table 12-2
Table 13-1
Table 13-2
Table A-1
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Segment Register Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Memory Addressing Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
PIO Pin Assignments—Numeric Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PIO Pin Assignments—Alphabetic Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Bus Cycle Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Maximum and Minimum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Processor Release Level (PRL) Register High-Order Byte Values . . . . . . . . . . 4-6
Initial Register State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Chip Select Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
UMCS Block Size Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
LMCS Block Size Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
MCS Block Size Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
PCS Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
PCS3–PCS0 Wait-State Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Am186ER and Am188ER Microcontroller Interrupt Types. . . . . . . . . . . . . . . . . 8-3
Interrupt Controller Registers in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Priority Field Mask (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Interrupt Controller Registers in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Priority Field Mask (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Timer Control Unit Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
DMA Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Synchronization Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Maximum DMA Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Asynchronous Serial Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Parity Mode Bit Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Serial Port Baud Rate Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Synchronous Serial Interface Register Summary . . . . . . . . . . . . . . . . . . . . . . 12-1
SCLK Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
PIO Pin Assignments and Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
PIO Mode and PIO Direction Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
Table of Contents
xi
Download from Www.Somanuals.com. All Manuals Search And Download.
xii
Table of Contents
Download from Www.Somanuals.com. All Manuals Search And Download.
PREFACE
INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY
AMD’s Am186™ and Am188Q™ family of microcontrollers is based on the architecture of
the original 8086 and 8088 microcontrollers, and currently includes the 80C186, 80C188,
80L186, 80L188, Am186ER, Am188ER, Am186EMLV, Am188EMLV, Am186ES,
Am188ES, Am186ESLV, Am188ESLV, Am186EM, Am188EM, Am186ED, and
Am186EDLV microcontrollers. The Am186ER and Am188ER microcontrollers provide a
natural migration path for 80C186/188 designs that need performance and system cost
enhancements.
The Am186ER and Am188ER microcontrollers provide a low-cost, high-performance solution
for embedded system designers who want to use the x86 architecture. By integrating multiple
functional blocks and 32 Kbyte of internal RAM with the CPU, the Am186ER and Am188ER
microcontrollers eliminate the need for off-chip system-interface logic. It is possible to
implement a fully functional system with ROM and RAM, serial interfaces, and custom I/O
capability without additional system-interface logic.
The Am186ER and Am188ER microcontrollers can operate at frequencies up to 40 MHz.
The microcontrollers include an on-board PLL so that the clock input frequency can be as
little as one fourth the processor operating frequency. The Am186ER and Am188ER
microcontrollers are available in versions operating at 20, 25, 33, and 40 MHz.
PURPOSE OF THIS MANUAL
This manual describes the technical features and programming interface of the Am186ER
and Am188ER microcontrollers. The complete instruction set is documented in the Am186
and Am188 Family Instruction Set Manual, order #21267.
INTENDED AUDIENCE
This manual is intended for computer hardware and software engineers and system
architects who are designing or are considering designing systems based on the Am186ER
and Am188ER microcontrollers.
USER’S MANUAL OVERVIEW
This manual contains information on the Am186ER and Am188ER microcontrollers and is
essential for system architects and design engineers. Additional information is available in
the form of data sheets, application notes, and other documentation that is provided with
software products and hardware-development tools.
The information in this manual is organized into 12 chapters and 1 appendix.
n Chapter 1 introduces the features and performance aspects of the Am186ER and
Am188ER microcontrollers.
n Chapter 2 describes the programmer’s model of the Am186 and Am188 family
microcontrollers, including an instruction set overview and register model.
n Chapter 3 provides an overview of the system interfaces, along with clocking
features.
Introduction and Overview
xiii
Download from Www.Somanuals.com. All Manuals Search And Download.
n Chapter 4 provides a description of the peripheral control block along with power
management and reset configuration.
n Chapter 5 provides a description of the chip select unit.
n Chapter 6 provides a description of the internal memory.
n Chapter 7 provides a description of the refresh control unit.
n Chapter 8 provides a description of the on-chip interrupt controller.
n Chapter 9 describes the timer control unit.
n Chapter 10 describes the DMA controller.
n Chapter 11 describes the asynchronous serial port.
n Chapter 12 describes the synchronous serial interface.
n Chapter 13 describes the programmable I/O pins.
n Appendix A includes a complete summary of peripheral registers and fields.
For complete information on the Am186ER and Am188ER microcontroller pin lists, timing,
thermal characteristics, and physical dimensions, please refer to the Am186ER and
Am188ER Microcontrollers Data Sheet, order #20732.
AMD DOCUMENTATION
E86™ Microcontroller Family
ORDER NO. DOCUMENT TITLE
20732
Am186ER and Am188ER Microcontrollers Data Sheet
Hardware documentation: pin descriptions, functional descriptions, absolute
maximum ratings, operating ranges, switching characteristics and waveforms,
connection diagrams and pinouts, and package physical dimensions.
21267
19255
Am186 and Am188 Family Instruction Set Manual
Providesadetaileddescriptionandexamples foreachinstructionincludedinthe
Am186 and Am188 Family Instruction Set.
FusionE86SM Catalog
Provides information on tools that speed an E86 family embedded product to
market. Includes products from expert suppliers of embedded development so-
lutions.
20071
21058
E86 Family Support Tools Brief
Lists available E86 family software and hardware development tools, as well as
contact information for suppliers.
FusionE86 Development Tools Reference CD
Provides a single-source multimedia tool for customer evaluation of AMD prod-
ucts, aswellasFusionpartnertoolsandtechnologiesthatsupporttheE86family
of microcontrollers and microprocessors. Technical documentation for the E86
family is included on the CD in PDF format.
To order literature, contact the nearest AMD sales office or call 800-222-9323, option 3 (in
the U.S. and Canada) or direct dial from any location 512-602-5651.
Literature is also available in postscript and PDF formats on the AMD web site. To access the
AMD home page, go to http://www.amd.com. To download documents and software, ftp to
ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via
your web browser, go to ftp://ftp.amd.com.
xiv
Introduction and Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
FEATURES AND PERFORMANCE
1
Compared to the 80C186/188 microcontrollers, the Am186™ER and Am188™ER
microcontrollers enable designers to increase performance and functionality, while reducing
thecost,size,andpowerconsumptionofembeddedsystems.TheAm186ERandAm188ER
microcontrollers are cost-effective, enhanced versions of the AMD 80C186/188 devices.
The Am186ER and Am188ER microcontrollers deliver 80C186/188 compatibility plus
32 Kbyte of integrated memory, increased performance, reduced power consumption,
serial communications, and a glueless bus interface. Developed exclusively for the
embedded marketplace, the Am186ER and Am188ER microcontrollers increase the
performance of existing 80C186/188 systems while decreasing their cost.
Because the Am186ER and Am188ER microcontrollers integrate memory, on-chip
peripherals, and system logic and offer up to twice the performance of an 80C186/188,
they are ideal solutions for customers who need to enhance and cost-reduce their present
x86 designs.
1.1
KEY FEATURES AND BENEFITS
The Am186ER and Am188ER microcontrollers extend the AMD family of microcontrollers
based on the industry-standard x86 architecture. Upgrading to the Am186ER or Am188ER
microcontrollers is attractive for the following reasons:
n Minimized total system cost—The new on-chip RAM, peripherals, and system-interface
logic nearly eliminate the need for external devices, reducing the overall system cost of new
or existing 80C186/188 designs.
n Integrated RAM—32 Kbyte of internal RAM ensures a low-cost supply of memory and
also a smaller form factor and lower power consumption for system designs. The internal
memory provides the same performance as external zero-wait-state RAM devices.
n Enhanced performance—The Am186ER and Am188ER microcontrollers offer up to
40-MHz operation, which requires only a 10-MHz input clock. The nonmultiplexed
address bus offers faster, unbuffered access to memory.
n Zero-wait-state operation—Enhanced bus timing permits zero-wait-state operation at
40 MHz with internal RAM or inexpensive 70-ns memories.
n 3.3-V supply voltage with 5-V-tolerant I/O—The Am186ER and Am188ER
microcontrollers use a 3.3-V supply over the entire range of operating frequencies,
increasing the performance of one-supply 3.3-V systems while preserving much lower
power consumption when compared to 5-V operation. The 5-V-tolerant I/O
accommodates existing 5-V designs.
n Enhanced functionality—The new and enhanced on-chip peripherals include an
asynchronous serial port, a virtual watchdog timer, an additional interrupt pin, a high-
speed synchronous serial interface, a PSRAM controller, a 16-bit Reset Configuration
Register, enhanced chip-select functionality, and 32 programmable I/Os.
n x86 software compatibility—The Am186ER and Am188ER microcontrollers are
80C186/188-compatible and upward-compatible with the AMD E86 family.
Features and Performance
1-1
Download from Www.Somanuals.com. All Manuals Search And Download.
TheAm186ERandAm188ERmicrocontrollersarepartofthe AMDE86 familyofembedded
microcontrollers and microprocessors based on the x86 architecture. The 16-bit members of the
E86 family, referred to throughout this manual as the Am186 and Am188 family, include the
80C186, 80C188, 80L186, 80L188, Am186ER, Am188ER, Am186EM, Am188EM,
Am186EMLV, Am188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV,
Am186ED and Am186EDLV microcontrollers.
The Am186ER and Am188ER microcontrollers are designed to meet the most common
requirements of embedded products developed for the office automation, mass storage,
communications, and general embedded markets. Applications include disk drive
controllers, hand-held and desktop terminals, fax machines, printers, photocopiers, feature
phones, cellular phones, PBXs, multiplexers, modems, and industrial control.
1.2
DISTINCTIVE CHARACTERISTICS
Am186ER microcontroller uses a 16-bit external bus, while the Am188ER microcontroller
has an 8-bit external bus.
The Am186ER and Am188ER microcontrollers provide the following features:
n Memory Integration:
– 32 Kbyte of internal RAM with an internal chip select register
– Internal RAM provides same performance as zero-wait-state external memory
n Reduced power consumption:
– 3.3-V ± 0.3-V operation at all operating frequencies
– I/O drivers tolerate 5-V signals
n High performance:
– 20-, 25-, 33-, and 40-MHz operating frequencies
– Support for zero-wait-state operation at 40 MHz with 70-ns memory
– 1-Mbyte memory address space and 64-Kbyte I/O space
n New features remove the requirement for a 2x clock input and provide faster access to
memory:
– Phase-locked loop (PLL) allows processor to operate at up to four times the clock
input frequency
– Nonmultiplexed address bus
n New integrated peripherals increase functionality while reducing system cost:
– 32 programmable I/O (PIO) pins
– Asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers
– Synchronous serial interface allows high-speed, half-duplex, bidirectional data
transfer to and from application-specific integrated circuits (ASICs)
– Controller for external pseudo-static RAM (PSRAM) with auto refresh capability
– Reset Configuration Register
– Additional external and internal interrupts
– Timer 1 can be configured to provide a watchdog timer interrupt
1-2
Features and Performance
Download from Www.Somanuals.com. All Manuals Search And Download.
n Familiar 80C186 peripherals:
– Two independent DMA channels
– Programmable interrupt controller with six external interrupts
– Three programmable 16-bit timers
– Programmable memory and peripheral chip-select logic
– Programmable wait-state generator
– Power-save clock divider
n Software-compatible with the 80C186/188 microcontroller
n Widely available native development tools, applications, and system software
n Available for commercial or industrial temperature range
n Available in the following packages:
– 100-pin, thin quad flat pack (TQFP)
– 100-pin, plastic quad flat pack (PQFP)
Features and Performance
1-3
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 1-1
Am186ER Microcontroller Block Diagram
INT2/INTA0
INT3/INTA1/IRQ
INT4
INT1/SELECT
CLKOUTA
TMROUT0 TMROUT1
INT0
NMI
TMRIN0
TMRIN1
DRQ0
DRQ1
CLKOUTB
DMA
Unit
Timer Control
Unit
X2
X1
0
1 (WDT)
2
0
1
Clock and
Power
Management
Unit
Max Count B
Registers
20-Bit Source
Pointers
20-Bit Destination
Pointers
Interrupt
Control Unit
Execution
Unit
V
Max Count A
CC
Registers
16-Bit Count
Registers
Control
16-Bit Count
Registers
GND
Control
Control
Control
Registers
Registers
Registers
Registers
PIO
Unit
PIO31–
RES
1
PIO0
Control
Registers
Control
Registers
Control
Registers
Refresh
Control
Unit
PSRAM
Control
Unit
ARDY
SRDY
TXD
RXD
Asynchronous
Serial Port
S2
S1/IMDIS
S0/SREN
DT/R
32 Kbyte
RAM
(16K x 16)
Bus
Interface
Unit
Chip-Select
Unit
Control
Registers
DEN
HOLD
HLDA
Synchronous Serial
Interface
S6/
CLKSEL1
UZI/
CLKSEL2
RD
WHB
WLB
WR
BHE/ADEN
SDATA
PCS6/A2 SDEN0 SDEN1
PCS5/A1
PCS3–PCS0
UCS/ONCE1
SCLK
LCS/ONCE0
MCS3/RFSH
MCS2–MCS0
A19–A0
AD15–AD0
ALE
Notes:
1. All PIO signals are shared with other physical pins. See the pin descriptions in Chapter 3 and
Table 3-1 on page 3-10 for information on shared functions.
1-4
Features and Performance
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 1-2
Am188ER Microcontroller Block Diagram
INT2/INTA0
INT3/INTA1/IRQ
INT4
INT1/SELECT
CLKOUTA
TMROUT0
TMROUT1
INT0
NMI
TMRIN0 TMRIN1
DRQ0
DRQ1
CLKOUTB
DMA
Unit
Timer Control
Unit
X2
X1
0
1 (WDT)
2
0
1
Clock and
Power
Management
Unit
20-Bit Source
Pointers
20-Bit Destination
Max Count B
Registers
Interrupt
Control Unit
Execution
Unit
Max Count A
V
CC
Pointers
16-Bit Count
Registers
Registers
16-Bit Count
Registers
Control
GND
Control
Control
Control
Registers
Registers
Registers
Registers
PIO
Unit
PIO31–
RES
1
PIO0
Control
Registers
Refresh
Control
Unit
Control
Registers
Control
Registers
PSRAM
Control
Unit
ARDY
SRDY
S2
TXD
RXD
Asynchronous
Serial Port
S1/IMDIS
S0/SREN
DT/R
32 Kbyte
RAM
(32K x 8)
Bus
Interface
Unit
Chip-Select
Unit
Control
Registers
DEN
HOLD
HLDA
Synchronous Serial
Interface
S6/
CLKSEL1
UZI/
CLKSEL2
RD
SDATA
SCLK
A19–A0
SDEN0 SDEN1
LCS/ONCE0
PCS6/A2
PCS5/A1
PCS3–PCS0
AO15–AO8
WB
MCS3/RFSH
MCS2–MCS0
AD7–AD0
WR
RFSH2/ADEN
UCS/ONCE1
ALE
Notes:
1. All PIO signals are shared with other physical pins. See the pin descriptions in Chapter 3 and
Table 3-1 on page 3-10 for information on shared functions.
Features and Performance
1-5
Download from Www.Somanuals.com. All Manuals Search And Download.
1.3
APPLICATION CONSIDERATIONS
The integration enhancements of the Am186ER and Am188ER microcontrollers provide a
high-performance, low-system-cost solution for 16-bit embedded microcontroller designs.
The internal 32-Kbyte RAM allows the manufacture of a complete embedded system using
only one externalROM device and a low-costcrystal, plus any voltage conversion or current
drivers required for I/O. Internal RAM is enabled and configured by using the Internal
Memory Chip Select (IMCS) Register described in Chapter 6, “Internal Memory.”
The nonmultiplexed address bus (A19–A0) eliminates system-interface logic for external
memory, while the multiplexed address/data bus maintains the value of existing customer-
specific peripherals and circuits within the upgraded design.
The nonmultiplexed address bus is available in addition to the 80C186 and 80C188
microcontrollers’ multiplexed address/data bus (AD15–AD0). The two buses can operate
simultaneously, or the AD15–AD0 bus can be configured to operate only during the data
phase of a bus cycle. See the BHE/ADEN and RFSH2/ADEN pin descriptions in Chapter 3,
and see section 5.5.1 and section 5.5.2 for additional information regarding the AD15–AD0
address enabling and disabling.
Figure 1-3 illustrates a functional system design that uses the integrated peripheral set to
achieve high performance with reduced system cost.
Figure 1-3
Basic Functional System Design
Am29F400
Flash
Am186ER
Microcontroller
WR
WE
X2
10-MHz
Crystal
A19–A0
Address
X1
AD15–AD0
Data
OE
RD
CS
UCS
32 Kbyte
RAM
Timer 0–2
INT4–INT0
DMA 0–1
Serial Port
RS-232
Level
Converter
TXD
RXD
40 MHz
CLKOUTA
1.3.1
Clock Generation
The integrated PLL clock-generation circuitry of the Am186ER and Am188ER
microcontrollersallowsoperationatone timesorfourtimesthecrystalfrequency, inaddition
to the one-half frequency operation required by 80C186 and 80C188 microcontrollers. The
The integrated PLL lowers system cost by reducing the cost of the crystal and reduces
electromagnetic interference (EMI) in the system.
1-6
Features and Performance
Download from Www.Somanuals.com. All Manuals Search And Download.
1.3.2
Memory Interface
The integrated memory controller logic of the Am186ER and Am188ER microcontrollers
provides a direct address bus interface to memory devices. The use of an external address
latch controlled by the address latch enable (ALE) signal is not required.
Individual byte write-enable signals are provided to eliminate the need for external high/
low-byte, write-enable circuitry. The maximum bank size programmable for the memory
chip-select signals is increased to 512 Kbyte to facilitate the use of high-density memory
devices.
Improved memory timing specifications enable the use of zero-wait-state memories with
70-ns access times at 40-MHz CPU operation. This reduces overall system cost
significantly by allowing the use of commonly available memory devices. The integrated
32-Kbyte RAM operates at the same speed as zero-wait-state external memory.
Figure 1-3 illustrates an Am186ER microcontroller-based configuration with 512 Kbyte of
external Flash EPROM in addition to the internal 32-Kbyte memory. Additional external
RAM can also be added. The external memory interface requires the following:
n The processor A19–A0 bus connects to the memory address inputs.
n The AD bus connects directly to the data inputs/outputs.
n The UCS chip select connects to the memory chip-select input.
External read operations require that the RD output connects to the SRAM Output Enable
(OE) inputpin. Externalwriteoperationsrequirethat thebytewriteenables connecttotheSRAM
Write Enable (WE) input pin.
for application memory, mapped into the upper region of the microcontroller’s 1-Mbyte
address space at 80000h–FFFFFh. After a valid reset, the Am186ER or Am188ER
microcontroller will fetch the first instruction from address FFFF0h. The user application
can then enable and configure the location of the integrated 32-Kbyte RAM within the
remaining address space; in this example, it would be at address 00000h to accommodate
the interrupt vector table.
1.3.3
Serial Communications Port
The integrated universal asynchronous receiver/transmitter (UART) controller in the
Am186ER and Am188ER microcontrollers eliminates the need for external logic to
implement a communications interface. The integrated UART generates the serial clock
from the CPU clock so that no external time-base oscillator is required.
Figure 1-3 shows a minimal implementation of an RS-232 console or modem
communications port. The RS-232 to CMOS voltage-level converter is required for the
proper electrical interface with the external device.
The Am186ER and Am188ER microcontrollers also include a synchronous serial interface.
For more information, see Chapter 11.
Features and Performance
1-7
Download from Www.Somanuals.com. All Manuals Search And Download.
1.4
THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS
The FusionE86 Program of Partnerships for Application Solutions provides the customer with
an array of products designed to meet critical time-to-market needs. Products and solutions
available from the AMD FusionE86 partners include emulators, hardware and software
debuggers, board-level products, and software development tools.
In addition, mature development tools and applications for the x86 platform are widely
available in the general marketplace.
1-8
Features and Performance
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
PROGRAMMING
2
All members of the Am186 and Am188 family of microcontrollers, including the Am186ER
andAm188ER,containthesamebasicsetofregisters,instructions,andaddressingmodes,
and are compatible with the original industry-standard 186/188 parts.
2.1
REGISTER SET
The base architecture of the Am186ER and Am188ER microcontrollers has 14 registers,
n General Registers—Eight 16-bit general purpose registers can be used for arithmetic
and logicaloperands. Four of these (AX, BX, CX, and DX) can be used as 16-bit registers
or split into pairs of separate 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL). The
Destination Index (DI) and Source Index (SI) general-purpose registers are used for
data movement and string instructions. The Base Pointer (BP) and Stack Pointer (SP)
general-purpose registers are used for the stack segment and point to the bottom and
top of the stack, respectively.
– Base and Index Registers—Four of the general-purpose registers (BP, BX, DI, and
SI) can also be used to determine offset addresses of operands in memory. These
registers can contain base addresses or indexes to particular locations within a
segment. The addressing mode selects the specific registers for operand and address
calculations.
– Stack Pointer Register—All stack operations (POP, POPA, POPF, PUSH, PUSHA,
PUSHF) utilize the stack pointer. The Stack Pointer Register is always offset from the
Stack Segment (SS) Register, and no segment override is allowed.
n Segment Registers—Four 16-bit special-purpose registers (CS, DS, ES, and SS)
select, at any given time, the segments of memory that are immediately addressable
for code (CS), data (DS and ES), and stack (SS) memory. (For usage, refer to section
2.2.)
n Status and Control Registers—Two 16-bit special-purpose registers recordor alter certain
aspects of the processor state—the Instruction Pointer (IP) Register contains the offset
address of the next sequential instruction to be executed and the Processor Status Flags
Note that the Am186ER and Am188ER microcontrollers have additional on-chip peripheral
registers, which are external to the processor. These external registers are not accessible
by the instruction set. However, because the processor treats these peripheral registers
like memory, instructions that have operands that access memory can also access
peripheral registers. The above processor registers, as well as the additional on-chip
peripheral registers, are described in the chapters that follow.
Programming
2-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 2-1
Register Set
16-Bit
Register Name
16-Bit
Register Name
Special Register
Functions
15
0
7
0
7
0
Code Segment
Byte
Addressable
(8-Bit
Register
Names
AX
DX
CS
DS
SS
AH
DH
AL
DL
Multiply/Divide
I/O Instructions
Data Segment
Stack Segment
Extra Segment
Loop/Shift/Repeat/Count
CX
BX
CH
BH
CL
BL
ES
Shown)
Base Registers
Segment Registers
Base Pointer
Source Index
BP
SI
15
0
Index Registers
Destination Index
DI
Processor Status Flags
FLAGS
IP
SP
Stack Pointer
Instruction Pointer
15
0
General
Registers
Status and Control
Registers
2.1.1
Processor Status Flags Register
the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the
operation of the microcontroller within a given operating mode (bits 8, 9, and 10).
After an instruction is executed, the value of the flags may be set (to 1), cleared/reset (set
to 0), unchanged, or undefined. The term undefined means that the flag value prior to the
execution of the instruction is not preserved, and the value of the flag after the instruction is
executed cannot be predicted.
Figure 2-2
Processor Status Flags Register (FLAGS)
7
0
15
Reserved
OF
AF
PF
CF
DF
IF
Res Res Res
TF
SF
ZF
Bits 15–12—Reserved
Bit11:OverflowFlag(OF)—Setifthesignedresultcannotbeexpressedwithinthenumber
of bits in the destination operand; cleared otherwise.
Bit 10: Direction Flag (DF)—Causes string instructions to auto-decrement the appropriate
index registers when set. Clearing DF causes auto-increment.
2-2
Programming
Download from Www.Somanuals.com. All Manuals Search And Download.
Bit 9: Interrupt-Enable Flag (IF)—When set, enables maskable interrupts to cause the
CPU to transfer control to a location specified by an interrupt vector.
Bit 8: Trace Flag (TF)—When set, a trace interrupt occurs after instructions execute. TF
is cleared by the trace interrupt after the processor status flags are pushed onto the stack.
The trace service routine can continue tracing by popping the flags back with an interrupt
return (IRET) instruction.
Bit 7: Sign Flag (SF)—Set equal to high-order bit of result (0 if 0 or positive, 1 if negative).
Bit 6: Zero Flag (ZF)—Set if result is 0; cleared otherwise.
Bit 5: Reserved
Bit 4: Auxiliary Carry (AF)—Set on carry from or borrow to the low-order 4 bits of the AL
general-purpose register; cleared otherwise.
Bit 3: Reserved
Bit 2: Parity Flag (PF)—Set if low-order 8 bits of result contain an even number of 1 bits;
cleared otherwise.
Bit 1: Reserved
Bit 0: Carry Flag (CF)—Set on high-order bit carry or borrow; cleared otherwise.
2.2
MEMORY ORGANIZATION AND ADDRESS GENERATION
Memory is organized in sets of segments. Each segment is a linear contiguous sequence
16
of 64K (2 ) 8-bit bytes. Memory is addressed using a two-component address that consists
of a 16-bit segment value and a 16-bit offset. The offset is the number of bytes from the
beginning of the segment (the segment address) to the data or instruction that is being
accessed.
The processor forms the physical address of the target location by taking the segment
address, shifting it to the left 4 bits (multiplying by 16), and adding this to the 16-bit offset.
The result is the 20-bit address of the target data or instruction. This allows for a 1-Mbyte
physical address size.
For example, if the segment register is loaded with 12A4h and the offset is 0022h, the
1. The segment register contains 12A4h.
2. The segment register is shifted left 4 places and is now 12A40h.
3. The offset is 0022h.
4. The shifted segment address (12A40h) is added to the offset (00022h) to get 12A62h.
5. This address is placed on the pins of the controller.
All instructions that address operands in memory must specify (implicitly or explicitly) a
16-bit segment value and a 16-bit offset value. The 16-bit segment values are contained in
one of four internal segment registers (CS, DS, ES, and SS). See “Addressing Modes” on
2-8 for more information on CS, DS, ES, and SS.
In addition to memory space, all Am186 and Am188 family microcontrollers provide 64K
Programming
2-3
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 2-3
Physical Address Generation
Shift
Left
4 Bits
Segment
Base
1
2
A
4
Logical
15
0
Address
Offset
0
0
2
2
0
15
1
2
A
0
4
2
0
0
19
0
0
2
15
0
Physical Address
1
2
A
6
2
0
19
To Memory
2.3
I/O SPACE
TheI/Ospace consistsof64K8-bitor32K16-bitports. The INandOUTinstructionsaddress
the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port
address in the DX Register. Eight-bit port addresses are zero-extended so that A15–A8
are Low. I/O port addresses 00F8h through 00FFh are reserved. The Am186ER and
Am188ER microcontrollers provide specific instructions for addressing I/O space.
Figure 2-4
Memory and I/O Space
Memory
Space
1M
I/O
Space
64K
2.4
INSTRUCTION SET
The Am186ER and Am188ER microcontrollers use the same instruction set as the 80C186
microcontroller. An instruction can reference from zero to several operands. An operand
can reside in a register, in the instruction itself, or in memory. Specific operand addressing
modes are discussed on page 2-10.
Table 2-1 lists the instructions for the Am186ER and Am188ER microcontrollers in
alphabetical order. The Am186™ and Am188™ Family Instruction Set Manual, order
#21267, provides detailed information on the format and function of the following
instructions.
2-4
Programming
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 2-1
Instruction Set
Mnemonic
AAA
Instruction Name
ASCII adjust for addition
ASCII adjust for division
ASCII adjust for multiplication
ASCII adjust for subtraction
Add byte or word with carry
Add byte or word
AAD
AAM
AAS
ADC
ADD
AND
BOUND
CALL
CBW
CLC
Logical AND byte or word
Detects values outside prescribed range
Call procedure
Convert byte to word
Clear carry flag
CLD
Clear direction flag
CLI
Clear interrupt-enable flag
Complement carry flag
CMC
CMP
CMPS
CWD
DAA
Compare byte or word
Compare byte or word string
Convert word to doubleword
Decimal adjust for addition
Decimal adjust for subtraction
Decrement byte or word by 1
Divide byte or word unsigned
Format stack for procedure entry
Escape to extension processor
Halt until interrupt or reset
Integer divide byte or word
Integer multiply byte or word
Input byte or word
DAS
DEC
DIV
ENTER
ESC
HLT
IDIV
IMUL
IN
INC
Increment byte or word by 1
Input bytes or word string
Interrupt
INS
INT
INTO
IRET
JA/JNBE
JAE/JNB
Interrupt if overflow
Interrupt return
Jump if above/not below or equal
Jump if above or equal/not below
Programming
2-5
Download from Www.Somanuals.com. All Manuals Search And Download.
Mnemonic
JB/JNAE
JBE/JNA
JC
Instruction Name
Jump if below/not above or equal
Jump if below or equal/not above
Jump if carry
JCXZ
Jump if register CX = 0
Jump if equal/zero
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
Jump if greater/not less or equal
Jump if greater or equal/not less
Jump if less/not greater or equal
Jump if less or equal/not greater
Jump
JNC
Jump if not carry
JNE/JNZ
JNO
Jump if not equal/not zero
Jump if not overflow
JNP/JPO
JNS
Jump if not parity/parity odd
Jump if not sign
JO
Jump if overflow
JP/JPE
JS
Jump if parity/parity even
Jump if sign
LAHF
Load AH register from flags
Load pointer using DS
Load effective address
Restore stack for procedure exit
Load pointer using ES
Lock bus during next instruction
Load byte or word string
Loop
LDS
LEA
LEAVE
LES
LOCK
LODS
LOOP
LOOPE/
LOOPZ
Loop if equal/zero
LOOPNE/
LOOPNZ
Loop if not equal/not zero
MOV
MOVS
MUL
NEG
NOP
NOT
Move byte or word
Move byte or word string
Multiply byte or word unsigned
Negate byte or word
No operation
Logical NOT byte or word
2-6
Programming
Download from Www.Somanuals.com. All Manuals Search And Download.
Mnemonic
OR
Instruction Name
Logical inclusive OR byte or word
Output byte or word
OUT
POP
Pop word off stack
POPA
POPF
PUSH
PUSHA
PUSHF
RCL
Pop all general register off stack
Pop flags off stack
Push word onto stack
Push all general registers onto stack
Push flags onto stack
Rotate left through carry byte or word
Rotate right through carry byte or word
Repeat
RCR
REP
REPE/REPZ
Repeat while equal/zero
Repeat while not equal/not zero
REPNE/
REPNZ
RET0
ROL
ROR
SAHF
SAL
Return from procedure
Rotate left byte or word
Rotate right byte or word
Store AH register in flags SF, ZF, AF, PF, and CF
Shift left arithmetic byte or word
Shift right arithmetic byte or word
Subtract byte or word with borrow
Scan byte or word string
SAR
SBB
SCAS
SHL
Shift left logical byte or word
Shift right logical byte or word
Set carry flag
SHR
STC
STD
Set direction flag
STI
Set interrupt-enable flag
STOS
SUB
TEST
XCHG
XLAT
XOR
Store byte or word string
Subtract byte or word
Test (logical AND, flags only set) byte or word
Exchange byte or word
Translate byte
Logical exclusive OR byte or word
Programming
2-7
Download from Www.Somanuals.com. All Manuals Search And Download.
2.5
SEGMENTS
The Am186ER and Am188ER microcontrollers use four segment registers:
1. Data Segment (DS): The processor assumes that all accesses to the program’s
variables are from the 64K space pointed to by the DS Register. The data segment holds
data, operands, etc.
2. Code Segment (CS): This 64K space is the default location for all instructions. All code
must be executed from the code segment.
3. Stack Segment (SS): The processor uses the SS Register to perform operations that
involve the stack, such as pushes and pops. The stack segment is used for temporary
space.
4. Extra Segment (ES): Usually this segment is used for large string operations and for
large data structures. Certain string instructions assume the extra segment as the
segment portion of the address. The extra segment is also used (by using segment
override) as a spare data segment.
When a segment is not defined for a data movement instruction, it’s assumed to be a data
segment. An instruction prefix can be used to override the segment register. For speed
and compact instruction encoding, the segment register used for physical address
Table 2-2
Segment Register Selection Rules
Memory Reference
Segment Register
Implicit Segment Selection Rule
Needed
Used
Local Data
Instructions
Stack
Data (DS)
Code (CS)
Stack (SS)
All data references
Instructions (including immediate data)
All stack pushes and pops
Any memory references that use the BP Register
External Data (Global)
Extra (ES)
All string instruction references that use the DI Regis-
ter as an index
2.6
DATA TYPES
The Am186ER and Am188ER microcontrollers directly support the following data types:
n Integer—A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All
operations assume a two’s complement representation.
n Ordinal—An unsigned binary numeric value contained in an 8-bit byte or a 16-bit word.
n Double Word—A signed binary numeric value contained in two sequential 16-bit
addresses, or in a DX::AX register pair.
n Quad Word—A signed binary numeric value contained in four sequential 16-bit
addresses.
n Binary-Coded Decimal (BCD)—An unpacked byte representation of the decimal
digits 0–9.
n ASCII—A byte representation of alphanumeric and control characters using the ASCII
standard of character representation.
n Packed BCD—A packed byte representation of two decimal digits (0–9). One digit is
stored in each nibble (4 bits) of the byte.
2-8
Programming
Download from Www.Somanuals.com. All Manuals Search And Download.
n String—A contiguous sequence of bytes or words. A string can contain from 1 byte up
to 64 Kbyte.
n Pointer—A 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit
segment base component plus a 16-bit offset component.
In general, individual data elements must fit within defined segment limits. Figure 2-5
graphically represents the data types supported by the Am186ER and Am188ER
microcontrollers.
Figure 2-5
Supported Data Types
7
0
Signed
Byte
+N
+1
0
Binary
Coded
Decimal
(BCD)
7
0
7
0
7
0
. . .
Sign Bit
Magnitude
BCD
Digit N
BCD
Digit 1
BCD
Digit 0
7
0
Unsigned
Byte
+N
+1
0
MSB
7
0
7
0
7
0
. . .
Magnitude
ASCII
ASCII
Character
ASCII ASCII
+1
0
Signed
Word
1514
8 7
0
N
Character
Character
1
0
+N
+1
0
Sign Bit
MSB
Magnitude
7
0
7
0
7
0
Packed
BCD
. . .
Signed
Double
Word
+3
+1
0
+2
Most Significant
Digit
Least
31
1615
0
Significant Digit
+N
Sign Bit
+1
0
MSB
7
0
7
0
7
0
. . .
Magnitude
String
Signed
Quad
Word
Byte/WordN
+3
Byte/Word1 Byte/Word0
+7 +6 +5 +4 +3 +2 +1 +0
63
15
48 47
32 31
1615
0
+2
+1
0
Pointer
Sign Bit
MSB
Magnitude
Segment Base
Offset
+1
0
0
Unsigned
Word
MSB
Magnitude
Programming
2-9
Download from Www.Somanuals.com. All Manuals Search And Download.
2.7
ADDRESSING MODES
The Am186ER and Am188ER microcontrollers use eight categories of addressing modes
to specify operands. Two addressing modes are provided for instructions that operate on
register or immediate operands; six modes are provided to specify the location of an
operand in a memory segment.
Register and Immediate Operands
n Register Operand Mode—The operand is located in one of the 8- or 16-bit registers.
n Immediate Operand Mode—The operand is included in the instruction.
Memory Operands
A memory-operand address consists of two 16-bit components: a segment value and an
offset. The segment value is supplied by a 16-bit segment register either implicitly chosen
by the addressing mode or explicitly chosen by a segment override prefix. The offset, also
called the effective address, is calculated by summing any combination of the following
three address elements:
1. Displacement—an 8-bit or 16-bit immediate value contained in the instruction
2. Base—contents of either the BX or BP base registers
3. Index—contents of either the SI or DI index registers
Any carry from the 16-bit addition is ignored. Eight-bit displacements are sign-extended to
16-bit values.
Combinations of the above three address elements define the following six memory
1. Direct Mode—The operand offset is contained in the instruction as an 8- or 16-bit
displacement element.
2. Register Indirect Mode—The operand offset is in one of the registers: SI, DI, BX, or BP.
3. BasedMode—Theoperandoffsetisthesumofan8-or16-bitdisplacementandthecontents
of a base register (BX or BP).
4. Indexed Mode—The operand offset is the sum of an 8- or 16-bit displacement and the
contents of an index register (SI or DI).
5. Based Indexed Mode—The operand offset is the sum of the contents of a base register
(BX or BP) and an index register (SI or DI).
6. Based Indexed Mode with Displacement—The operand offset is the sum of a base
register’s contents, an index register’s contents, and an 8-bit or 16-bit displacement.
Table 2-3
Memory Addressing Mode Examples
Addressing Mode
Direct
Example
mov ax, ds:4
mov ax, [si]
mov ax, [bx]4
mov ax, [si]4
mov ax, [si][bx]
mov ax, [si][bx]4
Register Indirect
Based
Indexed
Based Indexed
Based Indexed with Displacement
2-10
Programming
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
SYSTEM OVERVIEW
3
This chapter contains descriptions of the Am186ER and Am188ER microcontroller pins,
the bus interface unit, the clock and power managementunit, and thepower-save operation.
3.1
PIN DESCRIPTIONS
Pin Terminology
The following terms are used to describe the pins:
Input—An input-only pin.
Output—An output-only pin.
Input/Output—A pin that can be either input or output.
Synchronous—Synchronous inputs must meet setup and hold times in relation to
CLKOUTA. Synchronous outputs are synchronous to CLKOUTA.
Asynchronous—Inputs or outputs that are asynchronous to CLKOUTA.
A19–A0
Address Bus (output, three-state, synchronous)
The A19–A0 pins supply nonmultiplexed memory or I/O addresses to
the system one-half of a CLKOUTA period earlier than the multiplexed
address and data bus (AD15–AD0 on the Am186ER microcontroller or
AO15–AO8 and AD7–AD0 on the Am188ER microcontroller). During a
bus hold or reset condition, the address bus is in a high-impedance
state.
AD7–AD0
Address and Data Bus
(input/output, three-state, synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or I/O addresses,
as well as data, to the system. AD7–AD0 supply the low-order 8 bits of
an address to the system during the first period of a bus cycle (t ). On
1
a write, these pins supply data to the system during the remaining
periods of that cycle (t , t , and t ). On a read, these pins latch data at
2
3
4
the end of t .
3
Also, if S0/SREN (show read enable) was pulled Low during reset or if
the SR bit is set in the Internal Memory Chip Select (IMCS) Register,
these pins supply the data read from internal memory during t and t .
3
4
On the Am186ER microcontroller, AD7–AD0 combine with AD15–AD8
to form a complete multiplexed address and 16-bit data bus.
On the Am188ER microcontroller, AD7–AD0 combine with AO15–AO8
to form a complete multiplexed address bus while AD7–AD0 is the 8-bit
data bus.
System Overview
3-1
Download from Www.Somanuals.com. All Manuals Search And Download.
The address phase of these pins can be disabled. See the ADEN
description with the BHE/ADEN pin. When WLB is not asserted, these
pins are three-stated during t , t , and t .
2
3
4
During a bus hold or reset condition, the address and data bus is in a
high-impedance state.
During a power-on reset, the address and data bus pins (AD15–AD0
for the Am186ER microcontroller, AO15–AO8 and AD7–AD0 for the
Am188ER microcontroller) can also be used to load system
configuration information into the internal Reset Configuration Register.
The system information is latched on the rising edge of RES.
AD15–AD8
Address and Data Bus, Am186ER Microcontroller Only
(input/output, three-state, synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or I/O addresses,
as well as data, to the system. AD15–AD8 supply the high-order 8 bits
of an address to the system during the first period of a bus cycle (t ).
1
On a write, these pins supply data to the system during the remaining
periods of that cycle (t , t , and t ). On a read, these pins latch data at
2
3
4
the end of t .
3
Also, if S0/SREN (show read enable) was pulled Low during reset or if
the SR bit is set in the Internal Memory Chip Select (IMCS) Register,
these pins supply the data read from internal memory during t and t .
3
4
On the Am186ER microcontroller, AD15–AD8 combine with AD7–AD0
to form a complete multiplexed address and 16-bit data bus.
The address phase of these pins can be disabled. See the ADEN
description with the BHE/ADEN pin. When WHB is not asserted, these
pins are three-stated during t , t , and t .
2
3
4
During a bus hold or reset condition, the address and data bus is in a
high-impedance state. During a power-on reset, the address and data
buspins(AD15–AD0fortheAm186ERmicrocontroller, AO15–AO8and
AD7–AD0 for the Am188ER microcontroller) can also be used to load
system configuration information into the internal Reset Configuration
Register. The system information is latched on the rising edge of RES.
AO15–AO8
Address-Only Bus, Am188ER Microcontroller Only
(output, three-state, synchronous, level-sensitive)
The address-only bus (AO15–AO8) contains valid high-order address
bits from bus cycles t –t . These outputs are three-stated during a bus
1
4
hold or reset.
On the Am188ER microcontroller, AO15–AO8 combine with AD7–AD0
to form a complete multiplexed address bus while AD7–AD0 is the 8-bit
data bus.
During a power-on reset on the Am188ER microcontroller, the AO15–
AO8 and AD7–AD0 pins can also be used to load system configuration
information into an internal register for later use.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address
and data bus (AD15–AD0 for the Am186ER microcontroller or AO15–
3-2
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
AO8 and AD7–AD0 for the Am188ER microcontroller). The address is
guaranteed to be valid on the trailing edge of ALE. This pin is three-
stated during ONCE mode.
ARDY
Asynchronous Ready (input, asynchronous, level-sensitive)
This pin indicates to the microcontroller that the addressed memory
space or I/O device will complete a data transfer. The ARDY pin accepts
a rising edge that is asynchronous to CLKOUTA and is active High. The
falling edge of ARDY must be synchronized to CLKOUTA. To always
assert the ready condition to the microcontroller, tie ARDY High. If the
system does not use ARDY, tie the pin Low to yield control to SRDY.
BHE/ADEN
Bus High Enable, Am186ER Microcontroller Only
(three-state, output, synchronous)
Address Enable, Am186ER Microcontroller Only
(input, internal pullup)
BHE—During a memory access, this pin and the least significant
address bit (AD0 and A0) indicate to the system which bytes of the data
bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN
and AD0 pins are encoded as shown in the following table.
BHE/ADEN
AD0
Type of Bus Cycle
Word Transfer
0
0
1
1
0
1
0
1
High Byte Transfer (Bits 15–8)
Low Byte Transfer (Bits 7–0)
Refresh
BHE is asserted during t and remains asserted through t and t . BHE
1
3
W
does not need to be latched. BHE is three-stated during bus hold and
reset conditions.
On the Am186ER microcontroller, WLB and WHB implement the
functionality of BHE and AD0 for high and low byte write enables.
BHE/ADEN also signals DRAM refresh cycles when using the
multiplexed address and data (AD) bus. A refresh cycle is indicated
when both BHE/ADEN and AD0 are High. During refresh cycles, the A
bus and the AD bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this reason, the A0
signal cannot be used in place of the AD0 signal to determine refresh
cycles. PSRAM refreshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description).
ADEN—If BHE/ADEN is held High or left three-stated during power-on
reset, the address portion of the AD bus (AD15–AD0) is enabled or
disabled during LCS and UCS bus cycles based on the DA bit in the
Upper Memory Chip Select (UMCS) and Low Memory Chip Select
(LMCS) registers. If the DA bit is set, the memory address is accessed
on the A19–A0 pins. This mode of operation reduces power
consumption.
If BHE/ADEN is held Low on power-on reset, the AD bus always drives
both addresses and data. (S6 and UZI also assume their normal
System Overview
3-3
Download from Www.Somanuals.com. All Manuals Search And Download.
sampled within three crystal clock cycles after the rising edge of RES.
BHE/ADEN is three-stated during bus holds and ONCE mode.
See section 5.5.1 and section 5.5.2 for additional information on
enabling and disabling the AD bus during the address phase of a bus
cycle.
CLKOUTA
CLKOUTB
Clock Output A (output, synchronous)
This pin supplies the internal clock to the system. Depending on the
value of the Power-Save Control (PDCON) Register, CLKOUTA
operates at either the CPU fundamental clock frequency (which varies
with the Divide By Two, Times One, and Times Four clocking modes),
the power-save frequency, or is three-stated. CLKOUTA remains active
during reset and bus hold conditions.
Clock Output B (output, synchronous)
This pin supplies an additional clock to the system. Depending on the
value of the Power-Save Control (PDCON) Register, CLKOUTB
operates at either the CPU fundamental clock frequency (which varies
with the Divide By Two, Times One, and Times Four clocking modes),
the power-save frequency, or is three-stated. CLKOUTB remains active
during reset and bus hold conditions.
DEN
Data Enable (output, three-state, synchronous)
This pin supplies an output enable to an external data-bus transceiver.
DEN is asserted during memory, I/O, and interrupt acknowledge cycles.
DEN is deasserted when DT/R changes state. DEN is three-stated
during a bus hold or reset condition.
DRQ1–DRQ0
DMA Requests (input, synchronous, level-sensitive)
These pins indicate to the microcontroller that an external device is
ready for DMA channel 1 or channel 0 to perform a transfer. DRQ1–
DRQ0 are level-triggered and internally synchronized.
The DRQ signals are not latched and must remain active until serviced.
DT/R
Data Transmit or Receive (output, three-state, synchronous)
This pin indicates which direction data should flow through an external
data-bus transceiver. When DT/R is asserted High, the microcontroller
transmits data. When this pin is deasserted Low, the microcontroller
receives data. DT/R is three-stated during a bus hold or reset condition.
GND
Ground
These pins connect the system ground to the microcontroller.
Bus Hold Acknowledge (output, synchronous)
HLDA
When an external bus master requests control of the local bus (by
asserting HOLD), the microcontroller completes the bus cycle in
progress and then relinquishes control of the bus to the external bus
master by asserting HLDA and three-stating DEN, RD, WR, S2–S0,
AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R, and then driving
the chip selects UCS, LCS, MCS3–MCS0, PCS6–PCS5, and PCS3–
PCS0 High.
3-4
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
When the external bus master has finished using the local bus, it
indicates this to the microcontroller by deasserting HOLD. The
microcontroller responds by deasserting HLDA.
If the microcontroller requires access to the bus (e.g., for refresh), it will
deassert HLDA before the external bus master deasserts HOLD. The
external bus master must be able to deassert HOLD and allow the
microcontroller access to the bus.
HOLD
Bus Hold Request (input, synchronous, level-sensitive)
This pin indicates to the microcontroller that an external bus master
needs control of the local bus. For more information, see the HLDA pin
description.
The Am186ER and Am188ER microcontrollers’ HOLD latency time, the
time between HOLD request and HOLD acknowledge, is a function of
the activity occurring in the processor when the HOLD request is
received. A HOLD request is second only to DRAM refresh requests in
priority of activity requests received by the processor. This implies that
if a HOLD request is received just as a DMA transfer begins, the HOLD
latency can be as great as four bus cycles. This occurs if a DMA word
transfer operation is taking place (Am186ER microcontroller only) from
an odd address to an odd address. This is a total of 16 clock cycles or
more if wait states are required. In addition, if locked transfers are
performed, the HOLD latency time is increased by the length of the
locked transfer.
INT0
Maskable Interrupt Request 0 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT0 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT0 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee the interrupt is recognized,
the device issuing the request must continue asserting INT0 until the
request is acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input, asynchronous)
Slave Select (input, asynchronous)
INT1—This pin indicates to the microcontroller that an interrupt request
hasoccurred.IftheINT1pinisnotmasked, themicrocontrollertransfers
program execution to the location specified by the INT1 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can be edge-
triggered or level-triggered. To guarantee the interrupt is recognized,
the device issuing the request must continue asserting INT1 until the
request is acknowledged.
SELECT—When the microcontroller interrupt control unit is operating
as a slave to an external master interrupt controller, this pin indicates
to the microcontroller that an interrupt type appears on the address and
data bus. The INT0 pin must indicate to the microcontroller that an
interrupt has occurred before the SELECT pin indicates to the
microcontroller that the interrupt type appears on the bus.
System Overview
3-5
Download from Www.Somanuals.com. All Manuals Search And Download.
INT2/INTA0
Maskable Interrupt Request 2 (input, asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
INT2—This pin indicates to the microcontroller that an interrupt request
hasoccurred.IftheINT2pinisnotmasked, themicrocontrollertransfers
program execution to the location specified by the INT2 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee the interrupt is recognized,
the device issuing the request must continue asserting INT2 until the
request is acknowledged. INT2 becomes INTA0 when INT0 is
configured in Cascade mode.
INTA0—When the microcontroller interrupt control unit is operating in
Cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT0. The
peripheral issuingtheinterruptrequestmust provide the microcontroller
with the corresponding interrupt type.
INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT3 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT3 vector
in the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee the interrupt is recognized,
the device issuing the request must continue asserting INT3 until the
request is acknowledged. INT3 becomes INTA1 when INT1 is
configured in Cascade mode.
INTA1—When the microcontroller interrupt control unit is operating in
Cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT1. The
peripheral issuingtheinterruptrequestmust provide the microcontroller
with the corresponding interrupt type.
IRQ—When the microcontroller interrupt control unit is operating as a
slave to an external master interrupt controller, this pin lets the
microcontroller issue an interrupt request to the external master
interrupt controller.
INT4
Maskable Interrupt Request 4 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT4 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT4 vector
in the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee the interrupt is recognized,
the device issuing the request must continue asserting INT4 until the
request is acknowledged.
3-6
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous, internal pullup)
ONCE Mode Request 0 (input)
LCS—This pin indicates to the system that a memory access is in
progress to the lower memory block. The size of the lower memory
block is programmable up to 512 Kbyte. LCS is held High during a bus
hold condition.
ONCE0—During reset, this pin and UCS/ONCE1 indicate to the
microcontroller the mode in which it should operate. ONCE0 and
ONCE1 are sampledon the rising edgeofRES. Ifboth pinsareasserted
Low, the microcontroller enters ONCE mode; otherwise, it operates
normally.
In ONCE mode, all pins assume a high-impedance state and remain in
that state until a subsequent reset occurs. To guarantee that the
microcontroller does not inadvertently enter ONCE mode, ONCE0 has
a weak internal pullup resistor that is active only during a reset.
MCS3/RFSH
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory access is in
progress to the fourth region of the midrange memory block. The base
address and size of the midrange memory block are programmable.
MCS3 is held High during a bus hold condition. In addition, this pin has
a weak internal pullup resistor that is active during reset.
RFSH—This pin provides a signal timed for auto refresh to PSRAM
devices. It is only enabled to function as a refresh pulse when the
PSRAM mode bit is set in the LMCS Register. An active Low pulse is
generated for 1.5 clock cycles with an adequate deassertion period to
ensure that overall auto refresh cycle time is met.
MCS2–MCS0
Midrange Memory Chip Selects
(output, synchronous, internal pullup)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the midrange memory block. The base
address and size of the midrange memory block are programmable.
MCS2–MCS0 are held High during a bus hold condition. In addition,
they have weak internal pullup resistors that are active during a reset.
Unlike the UCS and LCS chip selects, the MCS outputs assert with the
multiplexed AD address bus.
NMI
Nonmaskable Interrupt (input, synchronous, edge-sensitive)
This pin indicates to the microcontroller that an interrupt request has
occurred. The NMI signal is the highest priority hardware interrupt and,
unlike the INT4–INT0 pins, cannot be masked. The microcontroller
always transfers program execution to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt vector
table when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not
participate in the priority resolution process of the maskable interrupts.
There is no bit associated with NMI in the interrupt in-service or interrupt
request registers. This means that a new NMI request can interrupt an
System Overview
3-7
Download from Www.Somanuals.com. All Manuals Search And Download.
executing NMI interrupt service routine. As with all hardware interrupts,
the IF (interrupt flag) is cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if maskable
interruptsarere-enabledbysoftwareintheNMIinterruptserviceroutine
(via the STI instruction for example), the fact that an NMI is currently in
service will not have any effect on the priority resolution of maskable
interruptrequests.Forthisreason,itisstronglyadvisedthattheinterrupt
service routine for NMI does not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized
internally, and it initiates the interrupt at the next instruction boundary.
To guarantee that the interrupt is recognized, the NMI pin must be
asserted for at least one CLKOUTA period. Because NMI is rising edge
sensitive, holding the pin High during reset has no effect on program
execution.
PCS3–PCS0
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the peripheral memory block (either I/O
ormemory addressspace).The base address oftheperipheralmemory
block is programmable. PCS3–PCS0 are held High during a bus hold
or reset condition.
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus.
Note: PCS4 is not available on the Am186ER and Am188ER
microcontrollers. Note also that each peripheral chip select asserts over
a 256-byte address range, which is twice the address range covered by
peripheral chip selects in the 80C186 and 80C188 microcontrollers.
PCS5/A1
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory access is in
progress to the sixth region of the peripheral memory block (either I/O
ormemory addressspace).The base address oftheperipheralmemory
block is programmable. PCS5 is held High during a bus hold or reset
condition. It is also held High during reset.
Note: Unlike the UCS and LCS chip selects, the PCS outputs assert
with the multiplexed AD address bus. Note also that each peripheral
chip select asserts over a 256-byte address range, which is twice the
address range covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
A1—When the EX bit in the MCS and PCS Auxiliary Register is 0, this
pin supplies an internally latched address bit 1 to the system. During a
bus hold condition, A1 retains its previously latched value.
PCS6/A2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory access is in
progress to the seventh region of the peripheral memory block (either
I/O or memory address space). The base address of the peripheral
memory block is programmable. PCS6 is held High during a bus hold
or reset condition.
3-8
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
Note: Unlike the UCS and LCS chip selects, the PCS outputs assert
with the multiplexed AD address bus. Note also that each peripheral
chip select asserts over a 256-byte address range, which is twice the
addressrange covered byperipheralchip selects in theoriginal80C186
and 80C188 microcontrollers.
A2—When the EX bit in the MCS and PCS Auxiliary Register is 0, this
pin supplies an internally latched address bit 2 to the system. During a
bus hold condition, A2 retains its previously latched value.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output, asynchronous, open-drain)
The Am186ER and Am188ER microcontrollers provide 32 individually
programmable I/O pins. The pins that are multiplexed with PIO31–PIO0
with the following attributes: PIO function (enabled/disabled), direction
(input/output), and weak pullup or pulldown. See Chapter 12 for the PIO
control registers.
On the Am186ER and Am 188ER microcontrollers, the internal pullup
resistor has a value of approximately 100 kohms. The internal pulldown
resistor has a value of approximately 100 kohms.
Afterpower-onreset, thePIO pins default to various configurations. The
the defaults for the PIOs. The system initialization code must
reconfigure any PIOs as required.
If PIO29 (S6/CLKSEL1) is to be used in input mode, the input device
must not drive PIO29 Low during power-on reset. The pin defaults to a
PIO input with pullup, so it does not need to be driven High externally.
The A19–A17 address pins default to normal operation on power-on
reset, allowing the processor to correctly begin fetching instructions at
the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
System Overview
3-9
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 3-1
PIO Pin Assignments—Numeric Listing
PIO No.
Associated Pin
TMRIN1
Power-On Reset Status
Input with pullup
0
1
2
3
4
TMROUT1
PCS6/A2
PCS5/A1
DT/R
Input with pulldown
Input with pullup
Input with pullup
Normal operation(3)
Normal operation(3)
Normal operation(4)
Normal operation(3)
Normal operation(3)
5
6
DEN
SRDY
A17
7(1)
8(1)
A18
9(1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Normal operation(3)
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
A19
TMROUT0
TMRIN0
DRQ0
DRQ1
MCS0
MCS1
PCS0
PCS1
PCS2
PCS3
SCLK
SDATA
SDEN0
SDEN1
MCS2
MCS3/RFSH
UZI/CLKSEL2
TXD
26(1,2)
27
28
RXD
29(1,2)
30
S6/CLKSEL1
INT4
31
INT2
Notes:
1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE,
ALE, AD15–AD0, and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN (Am186ER microcontroller) or RFSH2/ADEN
(Am188ER microcontroller) is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
3-10
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 3-2
PIO Pin Assignments—Alphabetic Listing
Associated Pin
A17(1)
PIO No.
Power-On Reset Status
Normal operation(3)
Normal operation(3)
Normal operation(3)
7
A18(1)
8
9
5
A19(1)
DEN
Normal operation(3)
Input with pullup
Input with pullup
DRQ0
DRQ1
DT/R
12
13
4
Normal operation(3)
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
INT2
INT4
31
30
14
15
24
25
16
17
18
19
3
MCS0
MCS1
MCS2
MCS3/RFSH
PCS0
PCS1
PCS2
PCS3
PCS5/A1
PCS6/A2
RXD
2
28
29
S6/CLKSEL1(1,2)
SCLK
20
21
22
23
6
SDATA
SDEN0
SDEN1
Normal operation(4)
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
SRDY
TMRIN0
TMRIN1
TMROUT0
TMROUT1
TXD
11
0
10
1
27
26
UZI/CLKSEL2(1,2)
Notes:
1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE,
ALE, AD15–AD0, and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN (Am186ER microcontroller) or RFSH2/ADEN
(Am188ER microcontroller) is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
System Overview
3-11
Download from Www.Somanuals.com. All Manuals Search And Download.
RD
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD is guaranteed not to be
asserted before the address and data bus is three-stated during the
address-to-data transition. RD is three-stated during bus holds and
ONCE mode.
RES
Reset (input, asynchronous, level-sensitive)
This pin causes the microcontroller to perform a reset. When RES is
asserted,themicrocontrollerimmediatelyterminatesitspresentactivity,
clears its internal logic, and CPU control is transferred to the reset
address FFFF0h.
RES must be held Low for at least 1 ms. The assertion of RES can be
asynchronous to CLKOUTA because RES is synchronized internally.
For proper initialization, V must be within specifications, and
CC
CLKOUTA must be stable for more than four CLKOUTA periods during
which RES is asserted.
The microcontroller begins fetching instructions approximately
6.5 CLKOUTA periods after RES is deasserted. This input is provided
with a Schmitt trigger to facilitate power-on RES generation via an RC
network.
RFSH2/ADEN
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Available on the Am188ER microcontroller only, RFSH2/
ADEN is asserted Low to signify a DRAM refresh bus cycle. The use
of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is
selected. Instead, the MCS3/RFSH signal is provided to the PSRAM.
During reset, this pin is a pullup. This pin is three-stated during bus
holds and ONCE mode.
ADEN—If RFSH2/ADEN is held High or left floating on power-on reset,
the AD bus (AO15–AO8 and AD7–AD0) is enabled or disabled during
the address portion of LCS and UCS bus cycles based on the DA bit in
the LMCS and UMCS registers. If the DA bit is set, the memory address
is accessed on the A19–A0 pins. This mode of operation reduces power
consumption. There is a weak internal pullup resistor on RFSH2/ADEN,
so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both
addresses and data. (S6 and UZI also assume their normal functionality
three crystal clock cycles after the rising edge of RES. RFSH2/ADEN is
three-stated during bus holds and ONCE mode.
See section 5.5.1 and section 5.5.2 for additional information on
enabling and disabling the AD bus during the address phase of a bus
cycle.
RXD
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data from the system to
the internal UART of the microcontroller.
3-12
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
S2
Bus Cycle Status (output, three-state, synchronous)
S2—This pin indicates to the system the type of bus cycle in progress.
S2canbeusedasalogicalmemoryorI/Oindicator. S2–S0arethree-stated
during bus holds, hold acknowledges, and ONCE mode. During reset,
S1/IMDIS
Bus Cycle Status (output, three-state, synchronous)
Internal Memory Disable (input, internal pullup)
S1—This pin indicates to the system the type of bus cycle in progress.
S1 can be used as a data transmit or receive indicator. S2–S0 are three-
stated during bus holds, hold acknowledges, and ONCE mode. During
reset, these pins are pullups. The S2–S0 pins are encoded as shown in
IMDIS—If asserted during reset, this pin disables internal memory.
InternalMemoryDisable modeisprovidedforemulation anddebugging
purposes.
S0/SREN
Bus Cycle Status (output, three-state, synchronous)
Show Read Enable (input, internal pullup)
S0—This pin indicates to the system the type of bus cycle in progress.
S2–S0 are three-stated during bus holds, hold acknowledges, and ONCE
mode.During reset, these pins are pullups. TheS2–S0 pins are encoded
SREN—Ifasserted duringreset, thispinenablesdataread from internal
memory to be shown/driven on the AD15–AD0 bus. Note that if a byte
read is being shown, the unused byte will also be driven on the AD15–
AD0 bus.This mode is provided for emulation and debugging purposes.
Table 3-3
S2 S1
Bus Cycle Encoding
S0
Bus Cycle
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
S6/CLKSEL1
Bus Cycle Status Bit 6 (output, synchronous)
Clock Select 1 (input, internal pullup)
S6—During the second and remaining periods of a cycle (t , t , and t ),
2
3
4
this pin is asserted High to indicate a DMA-initiated bus cycle. During
a bus hold or reset condition, S6 is three-stated.
CLKSEL1—The clocking mode of the Am186ER and Am188ER
microcontrollers is controlled by UZI/CLKSEL2 and S6/CLKSEL1. Both
CLKSEL2 and CLKSEL1 are held High during power-on reset because
of an internal pullup resistor. The default clocking mode—Times Four—
is used if neither clock select is asserted Low during reset.
System Overview
3-13
Download from Www.Somanuals.com. All Manuals Search And Download.
If CLKSEL1 is held Low during power-on reset, the chip enters the
Divide by Two clocking mode where the fundamental clock is derived
by dividing the external clock input by two. If Divide by Two mode is
This pin is latched within three crystal clock cycles after the rising edge
of RES. Note that clock selection must be stable four clock cycles prior
to exiting reset (i.e., RES going High).
If S6/CLKSEL1 is to be used as a programmable interrupt (PIO29) in
input mode, the input device must not drive the pin Low during power-
on reset. S6/CLKSEL1 defaults to a PIO input with pullup, so it does
not need to be driven High externally.
SCLK
Serial Clock (output, synchronous, three-state)
This pin supplies the synchronous serial interface (SSI) clock to a slave
device, allowing transmit and receive operations to be synchronized
between the microcontroller and the slave. SCLK is derived from the
microcontroller internal clock and then divided by 2, 4, 8, or 16,
depending on register settings.
An access to any of the SSR or SSD registers activates SCLK for eight
SCLK cycles (see Figure 12-5 and Figure 12-6 on page 12-8). When
SCLK is inactive, it is held High by the microcontroller. SCLK is three-
stated during ONCE mode.
SDATA
Serial Data (input/output, synchronous)
This pin transmits and receives synchronous serial interface (SSI) data
to and from a slave device. When SDATA is inactive, a weak keeper
holds the last value of SDATA on the pin.
SDEN1–SDEN0 Serial Data Enables (output, synchronous)
These pins enable data transfers on ports 1 and 0 of the synchronous
serial interface (SSI). The microcontroller asserts either SDEN1 or
SDEN0 at the beginning of a transfer and deasserts it after the transfer
is complete. When SDEN1–SDEN0 are inactive, they are held Low by
the microcontroller. SDEN1–SDEN0 are three-stated during ONCE
mode.
SRDY
Synchronous Ready (input, synchronous, level-sensitive)
This pin indicates to the microcontroller that the addressed memory
space or I/O device will complete a data transfer. The SRDY pin accepts
an active High input synchronized to CLKOUTA.
Using SRDY instead of ARDY allows a relaxed system timing because
of the elimination of the one-half clock period required to internally
synchronize ARDY. To always assert the ready condition to the
microcontroller, tie SRDY High. If the system does not use SRDY, tie
the pin Low to yield control to ARDY.
TMRIN0
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal microcontroller
timer 0. After internally synchronizing a Low-to-High transition on
TMRIN0, the microcontroller increments the timer. TMRIN0 must be
tied High if not being used.
3-14
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
TMRIN1
Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal microcontroller
timer 1. After internally synchronizing a Low-to-High transition on
TMRIN1, the microcontroller increments the timer. TMRIN1 must be
tied High if not being used.
TMROUT0
TMROUT1
Timer Output 0 (output, synchronous)
This pin supplies the system with either a single pulse or a continuous
waveform with a programmable duty cycle.
Timer Output 1 (output, synchronous)
This pin supplies the system with either a single pulse or a continuous
waveform with a programmable duty cycle. It can also be programmed
as a watchdog timer.
TXD
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to the system from
the internal UART of the microcontroller.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the
upper memory block are programmable up to 512 Kbyte. UCS is held
High during a bus hold condition.
After power-on reset, UCS is asserted because the processor begins
executing at FFFF0h and the default configuration for the UCS chip
select is 64 Kbyte from F0000h to FFFFFh. See section 5.5.1.
ONCE1—During reset, this pin and ONCE0 indicate to the
microcontroller the mode in which it should operate. ONCE0 and
ONCE1 are sampledon the rising edgeofRES. Ifboth pinsareasserted
Low, the microcontroller enters ONCE mode; otherwise, it operates
normally. In ONCE mode, all pins assume a high-impedance state and
remain in that state until a subsequent reset occurs. To guarantee that
the microcontroller does not inadvertently enter ONCE mode, ONCE1
has a weak internal pullup resistor that is active only during a reset.
UZI/CLKSEL2
Upper Zero Indicate (output, synchronous)
UZI—This pin lets the designer determine whether an access to the
interrupt vector table is in progress by ORing it with bits 15–10 of the
address and data bus (AD15–AD10 on the Am186ER microcontroller
and AO15–AO10 on the Am188ER microcontroller). UZI/CLKSEL2 is
the logical AND of the inverted A19–A16 bits, and it asserts in the first
period of a bus cycle and is held throughout the cycle.
UZI/CLKSEL2 is three-stated during bus holds and ONCE mode.
CLKSEL2—The clocking mode of the Am186ER and Am188ER
microcontrollers is controlled by UZI/CLKSEL2 and S6/CLKSEL1
during reset. Both CLKSEL2 and CLKSEL1 are held High during power-
on reset because of an internal pullup resistor. The default clocking
mode—Times Four—is used if neither clock select is asserted Low
during reset.
System Overview
3-15
Download from Www.Somanuals.com. All Manuals Search And Download.
If CLKSEL2 is held Low during power-on reset, the processor enters
This pin is latched within three crystal clock cycles after the rising edge
of RES. Note that clock selection must be stable four clock cycles prior
to exiting reset (i.e., RES going High).
UZI/CLKSEL2 is three-stated during bus holds and ONCE mode.
Table 3-4
Clocking Modes
CLKSEL2
CLKSEL1
Clocking Mode
Times Four
H
H
L
H
L
Divide by Two
Times One
H
L
Reserved1
L
Notes:
1
The Reserved clocking mode should not be used. Entering the Reserved
clocking mode may cause unpredictable system behavior.
V
Power Supply (input)
CC
These pins supply power (+3.3 V) to the microcontroller.
WHB
Write High Byte, Am186ER Microcontroller Only
(output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of the data bus
(upper, lower, or both) participate in a write cycle. In 80C186 designs,
this information is provided by BHE, the least-significant address bit
(AD0), and by WR. However, by using WHB and WLB, the standard
system-interface logic and external address latch that were required
are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical OR of BHE and
WR. During reset, this pin is a pullup. This pin is three-stated during
bus holds and ONCE mode.
WLB/WB
Write Low Byte, Am186ER Microcontroller Only
(output, three-state, synchronous)
Write Byte, Am188ER Microcontroller Only
(output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which bytes of the data
bus (upper, lower, or both) participate in a write cycle. In 80C186
designs, this information is provided by BHE, the least-significant
address bit (AD0), and by WR. However, by using WHB and WLB, the
standard system interface logic and external address latch that were
required are eliminated.
WLB is asserted with AD7–AD0. WLB is the logical OR of AD0 and WR.
This pin is three-stated during bus holds and ONCE mode.
WB—On the Am188ER microcontroller, this pin indicates a write to the
bus. WB uses the same early timing as the nonmultiplexed address
bus. WB is associated with AD7–AD0. This pin is three-stated during
bus holds and ONCE mode.
3-16
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
WR
X1
Write Strobe (output, synchronous)
WR—This pin indicates to the system that the data on the bus is to be
written to a memory or I/O device. WR is three-stated during a bus hold
or reset condition.
Crystal Input (input)
This pin and the X2 pin provide connections for a fundamental mode
crystal used by the internal oscillator circuit. If providing an external
clock source, connect the source to X1 and ground X2. Unlike the rest
of the pins on the Am186ER and Am188ER microcontrollers, X1 is not
5-V tolerant and has a maximum input equal to V
.
CC
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a fundamental mode
crystal used by the internal oscillator circuit. If providing an external
clock source, connect the source to X1 and ground X2. Unlike the rest
of the pins on the Am186ER and Am188ER microcontrollers, X2 is not
5-V tolerant and has a maximum input equal to V
.
CC
3.1.1
Pins That Are Used by Emulators
The following pins are used by emulators: A19–A0, AO15–AO8, AD7–AD0, ALE, BHE/
ADEN (on the Am186ER microcontroller), CLKOUTA, RFSH2/ADEN (on the Am188ER
microcontroller), RD, S2, S1/IMDIS, S0/SREN, S6/CLKSEL1, and UZI/CLKSEL2.
Emulators require that S6/CLKSEL1 and UZI/CLKSEL2 be configured in their normal
functionality, that is, as S6 and UZI.
If BHE/ADEN (on the Am186ER microcontroller) or RFSH2/ADEN (on the Am188ER
microcontroller) is held Low during the rising edge of RES, S6 and UZI are configured in
their normal functionality, instead of as PIOs, at reset.
System Overview
3-17
Download from Www.Somanuals.com. All Manuals Search And Download.
3.2
BUS OPERATION
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address
and data (AD) bus. The address is present on the AD bus only during the t clock phase.
1
The Am186ER and Am188ER microcontrollers continue to provide the multiplexed AD bus and,
in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the
system for the complete bus cycle (t –t ).
1
4
For systems where power consumption is a concern, it is possible to disable the address
from being driven on the AD bus on the Am186ER microcontroller and on the AD and AO
buses on the Am188ER microcontroller during the normal address portion of the bus cycle
for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed
in a high-impedance state during the address portion of the bus cycle. This feature is
enabled through the DA bits in the UMCS and LMCS registers. When address disable is
in effect, the number of signals that assert on the bus during all normal bus cycles to the
associated address space is reduced, thus decreasing power consumption, reducing
processor switching noise, and preventing bus contention with memory devices and
peripherals when operating at high clock rates. On the Am188ER microcontroller, the
address is driven on A015–A08 during the data portion of the bus cycle, regardless of the
setting of the DA bits.
If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and
LMCS registers is ignored and the address is driven on the AD bus for all accesses, thus
preservingtheindustry-standard80C186and80C188microcontrollers’multiplexedaddressbus
and providing support for existing emulation tools.
Figure 3-1 on page 3-19 shows the affected signals during a normal read or write operation
for an Am186ER microcontroller. The address and data will be multiplexed onto the AD bus.
Figure 3-2 on page 3-19 shows an Am186ER microcontroller bus cycle when address bus
disable is in effect. This results in the AD bus operating in a nonmultiplexed data-only mode.
The A bus will provide the address during a read or write operation.
Figure 3-3 on page 3-20 shows the affected signals during a normal read or write operation
for an Am188ER microcontroller. The multiplexed address/data mode is compatible with
80C188 microcontrollers and might be used to take advantage of existing logic or
peripherals.
Figure 3-4 on page 3-20 shows an Am188ER microcontroller bus cycle when address bus
disable is in effect. The address and data are not multiplexed. The AD7–AD0 signals will
have only data on the bus, while the A bus will have the address during a read or write
operation. The AO bus will also have the address during t –t .
2
4
3-18
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 3-1
Am186ER Microcontroller Address Bus—Normal Read and Write Operation
t
t
t
t
4
1
2
3
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD15–AD0
(Read)
Address
Data
AD15–AD0
(Write)
Address
Data
LCS or UCS
MCSx, PCSx
Figure 3-2
Am186ER Microcontroller—Read and Write with Address Bus Disable In Effect
t
t
t
t
4
1
2
3
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Data
Data
AD15–AD8
(Read)
AD15–AD0
(Write)
Data
LCS, UCS
System Overview
3-19
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 3-3
Am188ER Microcontroller Address Bus—Normal Read and Write Operation
t
t
t
t
4
1
2
3
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Address
Data
AO15–AO8
(Read or Write)
Address
AD7–AD0
(Write)
Address
Data
LCS or UCS
MCSx, PCSx
Figure 3-4
Am188ER Microcontroller—Read and Write with Address Bus Disable In Effect
t
t
t
t
4
1
2
3
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Data
AO15–AO8
Address
Data
AD7–AD0
(Write)
LCS, UCS
3-20
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
3.3
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external peripherals and memory devices.
External accesses include those to memory devices, as well as those to memory-mapped
andI/O-mappedperipheralsandtheperipheralcontrolblock.TheAm186ERandAm188ER
microcontrollers provide an enhanced bus interface unit with the following features:
n A nonmultiplexed address bus
n Separate byte write enables for high and low bytes in the Am186ER microcontroller
n Pseudo-static RAM (PSRAM) support
The standard 80C186 multiplexed address and data bus requires system-interface logic
and an external address latch. On the Am186ER and Am188ER microcontrollers, new byte
write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce
design costs by eliminating external logic.
Timing diagrams for the operations described in this chapter appear in the Am186ER and
Am188ER Microcontrollers Data Sheet, order #20732.
3.3.1
3.3.2
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid one-half CLKOUTA cycle in advance
of the address on the AD bus. When used in conjunction with the modified UCS and LCS
outputs and the byte write enable signals, the A19–A0 bus provides a seamless interface
to SRAM, PSRAM, and Flash/EPROM memory systems.
Byte Write Enables
The Am186ER microcontroller provides two signals that act as byte write enables—WHB
(Write High Byte, AD15–AD8) and WLB (Write Low Byte, AD7–AD0). WHB is the logical
AND of BHE and WR (WHB is Low when both BHE and WR are Low). WLB is the logical
AND of AD0 and WR (WLB is Low when both AD0 and WR are both Low).
TheAm188ERmicrocontrollerprovidesonesignalforbyte writeenables—WB (WriteByte).
WB is the logical AND of WHB and WLB, which are not present on the Am188ER
microcontroller.
The byte write enables are driven in conjunction with the demultiplexed address bus as
required for the write timing requirements of common SRAMs.
3.3.3
Pseudo Static RAM (PSRAM) Support
The Am186ER and Am188ER microcontrollers support the use of PSRAM devices in low
memory chip select (LCS) space only. When PSRAM mode is enabled, the timing for the
LCS signal is modified by the chip select control unit to provide a CS precharge period
during PSRAM accesses. The 40-MHz timing of the Am186ER microcontroller is
appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled
through a bit in the Low Memory Chip Select (LMCS) Register. (See section 5.5.2 on page
5-6.) The PSRAM feature is disabled on CPU reset.
In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also
require periodic refresh of all internal row addresses to retain their data. Although refresh
of PSRAM can be accomplished several ways, the Am186ER and Am188ER
microcontrollers implement auto refresh only. The microcontroller generates a refresh
signal, RFSH, to the PSRAM devices when PSRAM mode is enabled. No refresh address
is required by the PSRAM when using the auto refresh mechanism. The RFSH signal is
multiplexed with the MCS3 signal pin. When PSRAM mode is enabled, MCS3 is not
available for use as a chip select signal.
System Overview
3-21
Download from Www.Somanuals.com. All Manuals Search And Download.
The refresh control unit must be programmed before accessing PSRAM in LCS space. The
refresh counter in the Clock Prescaler (CDRAM) Register must be configured with the
required refresh interval value. The ending address of LCS space and the ready and wait-
state generation in the LMCS Register must also be programmed.
The refresh counter reload value in the CDRAM Register should not be set to less than 18
(12h) in order to provide time for processor cycles within refresh. In PSRAM mode, the
refresh address counter must be set to 0000h to prevent another chip select from asserting.
LCS is held High during a refresh cycle. The A19–A0 bus is not used during refresh cycles.
The LMCS Register must be configured to external Ready ignored (R2=1) with one wait
state (R1–R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. See section
5.5.2 on page 5-6.
3-22
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
3.4
CLOCK AND POWER MANAGEMENT UNIT
The clock and power management unit of the Am186ER and Am188ER microcontrollers
includes a phase-locked loop (PLL) and a second programmable system clock output
(CLKOUTB).
3.4.1
Phase-Locked Loop (PLL)
In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal
clock. Because of the internal PLL on the Am186ER and Am188ER microcontrollers, the
internal clock generated by the microcontroller (CLKOUTA) can operate at up to four times
the frequency of the crystal. The Am186ER and Am188ER microcontrollers operate in the
following modes:
n Divide by Two—The frequency of the system clock is half the frequency of the crystal.
PLL is disabled.
n Times One—The frequency of the system clock is the same as the external crystal. PLL
is enabled.
n Times Four—The frequencyof the system clock is four timesthe frequency of the crystal.
PLL is enabled.
The default Times Four mode must be used for processor frequencies above 20 MHz.
minimum frequencies for X1, X2, and CLKOUTA according to clocking mode.
Table 3-5
Maximum and Minimum Clock Frequencies
X1/X2
Max
X1/X2
Min
CLKOUTA CLKOUTA
Mode
Max
Min
Divide by Two
Times One
20 MHz
—
10 MHz
20 MHz
40 MHz
—
20 MHz 16 MHz
10 MHz 5 MHz
16 MHz
20 MHz
Times Four
System Overview
3-23
Download from Www.Somanuals.com. All Manuals Search And Download.
3.4.2
Crystal-Driven Clock Source
The internal oscillator circuit of the microcontroller is designed to function with a parallel
resonant fundamental crystal. Because of the PLL, the crystal frequency can be twice,
equal to, or one quarter of the processor frequency. Do not replace a crystal with an LC or
RC equivalent.
The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) that
provides, along with the external feedback loading, the necessary phase shift (Figure 3-5).
In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180
degrees out of phase of the input signal (X1). The external feedback network provides an
additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero
degrees of phase shift.
The external feedback network is designed to be as close as possible to ideal. If the
feedback network is not providing necessary phase shift, negative feedback will dampen
the output of the amplifier and negatively affect the operation of the clock generator. Values
for the loading on X1 and X2 must be chosen to provide the necessary phase shift and
crystal operation.
Figure 3-5
Oscillator Configurations
C
C
1
X1
Crystal
X2
X1
X2
To PLL
To PLL
Oscillator
Oscillator
2
Am188ER/
Am186ER
Am188ER/
Am186ER
Microcontroller
Microcontroller
a. External Clock Configuration
b. Crystal Configuration
Note: X1 and X2 are not 5-V tolerant. The X1 maximum input is V
.
CC
3.4.3
External Source Clock
Alternately, the internal oscillator can be driven from an external clock source. This source
should be connected to the input of the inverting amplifier (X1) with the output (X2)
grounded. X1 and X2 are not 5-V tolerant and X1 has a maximum input equal to V
.
CC
3-24
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
3.4.4
System Clocks
Figure 3-6 shows the organization of the clocks. The 80C186 microcontroller system clock
has been renamed CLKOUTA. CLKOUTB is provided as an additional output.
Figure 3-6
Clock Organization
1
PSEN
Power-Save
1
CPU Clock
Divisor
Mux
CLKSEL2
(/1 to /128)
1
1
CAF
Mux
CAD
PLL
1x or 4x
CLKOUTA
CLKOUTB
Mux
Fundamental
Clock
X1, X2
Input Clock
1
CBF
Mux
1
CBD
÷2
Time
Delay
CLKSEL1
6 ±2.5ns
Notes:
1. Set via PDCON Register
CLKOUTA and CLKOUTB operate at either the CPU clock (power-save) frequency or the
fundamental clock (PLL or input divider) frequency. The output drivers for both clocks are
individually programmable for drive enable or disable.
The provision of two clock outputs lets the system designer configure one clock output to
run at the PLL frequency and the other to run at the CPU clock frequency. Individual drive
enable bits allow selective enabling of just one or both of these clock outputs.
3.4.5
Power-Save Operation
The power-save mode reduces power consumption and heat dissipation, which can reduce
power supply costs and size in all systems and extend battery life in portable systems. In
power-save mode, operation of the CPU and internal peripherals continues at a slower
clock frequency. When a hardware interrupt occurs, the CPU and internal peripheral clock
automatically returns to the fundamental clock frequency on the internal clock’s next rising
edge of t .
3
Note: Power-save operation requires that clock-dependent devices be reprogrammed for
clock frequency changes. Software drivers must be aware of clock frequency.
System Overview
3-25
Download from Www.Somanuals.com. All Manuals Search And Download.
3-26
System Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
PERIPHERAL CONTROL BLOCK
4
4.1
OVERVIEW
The Am186ER and Am188ER microcontroller integrated peripherals are controlled by
16-bit read/write registers. The peripheral registers are contained within an internal
256-bytecontrolblock—theperipheralcontrolblock(PCB).Registersarephysicallylocated
in the peripheral devices they control, but they are addressed as a single 256-byte block.
Figure 4-1 shows a map of the peripheral control block registers.
Code that is intended to execute on the Am188ER microcontroller should perform all writes
to the PCB registers as byte writes. These writes will transfer 16 bits of data to the PCB
register even if an 8-bit register is named in the instruction. For example, out dx, al
results in the value of axbeing written to the port address in dx. Reads to the PCB should be
done as word reads. Code written in this manner will run correctly on the Am188ER
microcontroller and on the Am186ER microcontroller. Unaligned reads and writes to the PCB
result in unpredictable behavior on both the Am186ER and Am188ER microcontrollers.
The peripheral control block can be mapped into either memory or I/O space. The base
address of the control block must be on an even 256-byte boundary (i.e., the lower eight
bits of the base address are 00h). Internal logic recognizes control block addresses and
responds to bus cycles. During bus cycles to internal registers, the bus controller signals
the operation externally (i.e., the RD, WR, status, address, and data lines are driven as in
a normal bus cycle), but the data bus, SRDY, and ARDY are ignored.
At reset, the Peripheral Control Block Relocation Register is set to 20FFh, which maps the
control block to start at FF00h in I/O space. An offset map of the 256-byte peripheral control
description of the Peripheral Control Block Relocation (RELREG) Register.
Peripheral Control Block
4-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 4-1
Peripheral Control Block Register Map
Offset
(Hexadecimal)
Register Name
FE
Peripheral Control Block Relocation Register
w
w
w
w
Reset Configuration Register
F6
F4
Chapter 4
Chapter 7
Processor Release Level Register
F0
PDCON Register
E4
E2
E0
Enable RCU Register
Clock Prescaler Register
Memory Partition Register
w
w
DA
D8
D6
D4
D2
D0
CA
DMA 1 Control Register
DMA 1 Transfer Count Register
DMA 1 Destination Address High Register
DMA 1 Destination Address Low Register
DMA 1 Source Address High Register
DMA 1 Source Address Low Register
Chapter 10
DMA 0 Control Register
DMA 0 Transfer Count Register
C8
C6
C4
C2
C0
DMA 0 Destination Address High Register
DMA 0 Destination Address Low Register
DMA 0 Source Address High Register
DMA 0 Source Address Low Register
w
w
w
w
Internal Memory Chip Select Register
AC
Chapter 6
Chapter 5
PCS and MCS Auxiliary Register
Midrange Memory Chip Select Register
Peripheral Chip Select Register
A8
A6
A4
A2
Low Memory Chip Select Register
A0
Upper Memory Chip Select Register
w
w
Serial Port Baud Rate Divisor Register
Serial Port Receive Register
Serial Port Transmit Register
Serial Port Status Register
88
86
84
82
80
Chapter 11
Serial Port Control Register
Notes:
Gaps in offset addresses indicate reserved registers.
Changed from 80C186
microcontroller.
4-2
Peripheral Control Block
Download from Www.Somanuals.com. All Manuals Search And Download.
Offset
(Hexadecimal)
Register Name
w
w
PIO Data 1 Register
7A
78
76
74
72
70
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
Chapter 13
PIO Direction 0 Register
PIO Mode 0 Register
w
w
Timer 2 Mode/Control Register
66
62
60
5E
5C
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
Chapter 9
5A
58
Timer 0 Mode/Control Register
56
54
52
50
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
w
w
Serial Port Interrupt Control Register
Watchdog Timer Control Register
INT4 Control Register
44
42
40
INT3 Control Register
3E
3C
3A
38
36
34
32
30
2E
2C
2A
INT2 Control Register
INT1 Control Register
INT0 Control Register
DMA 1 Interrupt Control Register
DMA 0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
Chapter 8
Priority Mask Register
Interrupt Mask Register
Poll Status Register
28
26
24
22
20
18
16
14
12
10
Poll Register
End-of-Interrupt Register
Interrupt Vector Register
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Transmit 1 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Chapter 12
Notes:
Gaps in offset addresses indicate reserved registers.
Changedfrom 80C186
microcontroller.
Peripheral Control Block
4-3
Download from Www.Somanuals.com. All Manuals Search And Download.
4.1.1
Peripheral Control Block Relocation Register (RELREG, Offset FEh)
The peripheral control block is mapped into either memory or I/O space by programming
is a 16-bit register at offset FEh from the control block base address. The RELREG Register
provides the upper 12 bits of the base address of the control block. The control block is
effectively an internal chip select range.
Other chip selects can overlap the control block only if they are programmed to zero wait
states and ignore external ready. If the control register block is mapped into I/O space, the
upper four bits of the base address must be programmed as 0000b (because I/O addresses
are only 16 bits wide).
In addition to providing relocation information for the control block, the RELREG Register
contains a bit that places the interrupt controller into either Slave mode or Master mode.
At reset, the RELREG Register is set to 20FFh, which maps the control block to start at
FF00h in I/O space. An offset map of the 256-byte peripheral control register block is shown
in Figure 4-1.
Figure 4-2
Peripheral Control Block Relocation Register (RELREG, offset FEh)
7
0
15
R19–R8
S/M M/IO
Res Res
The value of the RELREG Register is 20FFh at reset.
Bit 15: Reserved
Bit 14: Slave/Master (S/M)—Configures the interrupt controller for Slave mode when set
to 1 and for Master mode when set to 0.
Bit 13: Reserved
Bit 12: Memory/IO Space (M/IO)—When set to 1, the peripheral control block (PCB) is
located in memory space. When set to 0, the PCB is located in I/O space.
Bits 11–0: Relocation Address Bits (R19–R8)—R19–R8 define the upper address bits
ofthe PCB base address. The lowereight bits(R7–R0)defaultto 00h. R19–R16 are ignored
when the PCB is mapped to I/O space.
4-4
Peripheral Control Block
Download from Www.Somanuals.com. All Manuals Search And Download.
4.1.2
Reset Configuration Register (RESCON, Offset F6h)
block latches system-configuration information that is presented to the processor on the
address/data bus (AD15–AD0 for the Am186ER or AO15–AO8 and AD7–AD1 for the
Am188ER) during the rising edge of reset. The interpretation of this information is system
specific. The processor does not impose any predetermined interpretation, but simply
provides a means for communicating this information to software.
When the RES input is asserted Low, the contents of the address/data bus are written into
the RESCON Register. The system can place configuration information on the address/
data bus using weak external pullup or pulldown resistors, or using an external driver that
is enabled during reset. The processor does not drive the address/data bus during reset.
For example, the RESCON Register could be used to provide the software with the position
of a configuration switch in the system. Using weak external pullup and pulldown resistors
on the address and data bus, the system could provide the microcontroller with a value
corresponding to the position of a jumper during a reset.
Figure 4-3
Reset Configuration Register (RESCON, offset F6h)
7
0
15
RC
On reset, the RESCON Register is set to the value found on AD15–AD0.
Bits 15–0: Reset Configuration (RC)—There is a one-to-one correspondence between
address/data bus signals during the reset and the Reset Configuration Register’s bits. On
the Am186ER microcontroller, AD15 corresponds to bit 15 of the Reset Configuration
Register, and so on. On the Am188ER microcontroller, AO15 corresponds to register bit
15, and AD7 corresponds to bit 7. Once RES is deasserted, the RESCON Register holds
its value. This value can be read by software to determine the configuration information.
The contents of the RESCON Register are read-only and remain valid until the next
processor reset.
Peripheral Control Block
4-5
Download from Www.Somanuals.com. All Manuals Search And Download.
4.1.3
Processor Release Level Register (PRL, Offset F4h)
specifies the processor version. The format of the Processor Release Level Register is
shown in Figure 4-4.
Figure 4-4
Processor Release Level Register (PRL, offset F4h)
7
0
15
PRL
Reserved
186/188
Bits 15–9: Processor Release Level (PRL)—This field is a 7-bit, read-only identification
number that specifies the processor release level for either the Am186ER or Am188ER
microcontroller. Each release level is numbered one higher than the previous level.
Bit 8:—This bit is 0 in the Am186ER microcontroller. This bit is 1 in the Am188ER
microcontroller.
The values of bits 15–8 of the PRL Register for the Am186ER and Am188ER
microcontrollers are shown in Table 4-1.
Table 4-1
Processor Release Level (PRL) Register High-Order Byte Values
Bits 15–8
20h
Processor Release Level
Am186ER revision A
Am188ER revision A
21h
Bits 7–0: Reserved—Value is undefined
4-6
Peripheral Control Block
Download from Www.Somanuals.com. All Manuals Search And Download.
4.1.4
Power-Save Control Register (PDCON, Offset F0h)
Figure 4-5
Power-Save Control Register (PDCON, offset F0h)
7
0
15
0 0
0
0 0 0 0
0
F1
PSEN
CAF
CBF
CBD
F0
F2
CAD
The value of the PDCON Register is 0000h at reset.
Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables Power-Save mode
and divides the internal operating clock by the value in F2–F0. PSEN is automatically
cleared when an external interrupt occurs, including those generated by on-chip peripheral
devices. The value of the PSEN bit is not restored by the execution of an IRET instruction.
Software interrupts (INT instruction) and exceptions do not clear the PSEN bit, and interrupt
service routines for these conditions should do so if desired. This bit is 0 after processor
reset.
Bits 14–12: Reserved—Read back as 0.
Bit11:CLKOUTBOutputFrequency(CBF)—Whensetto1, CLKOUTBfollowsthecrystal
input (PLL) frequency. When set to 0, CLKOUTB follows the internal processor frequency
(after the clock divisor). Set to 0 on reset.
CLKOUTB can be used as a full-speed clock source in Power-Save mode.
Bit 10:CLKOUTB Drive Disable (CBD)—When setto 1, CBD three-states the clock output
driver for CLKOUTB. When set to 0, CLKOUTB is driven as an output. Set to 0 on reset.
Bit 9: CLKOUTA Output Frequency (CAF)—When set to 1, CLKOUTA follows the crystal
input (PLL) frequency. When set to 0, CLKOUTA follows the internal processor frequency
(after the clock divisor). Set to 0 on reset.
CLKOUTA can be used as a full-speed clock source in Power-Save mode.
Bit 8: CLKOUTA Drive Disable (CAD)—When set to 1, CAD three-states the clock output
driver for CLKOUTA. When set to 0, CLKOUTA is driven as an output. Set to 0 on reset.
Bits 7–3: Reserved—Read back as 0.
Peripheral Control Block
4-7
Download from Www.Somanuals.com. All Manuals Search And Download.
Bits 2–0: Clock Divisor Select (F2–F0)—Controls the division factor when Power-Save
mode is enabled. Allowable values are as follows:
F2
F1
F0
Divider Factor
Divide by 1 (20)
Divide by 2 (21)
Divide by 4 (22)
Divide by 8 (23)
Divide by 16 (24)
Divide by 32 (25)
Divide by 64 (26)
Divide by 128 (27)
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
4.2
INITIALIZATION AND PROCESSOR RESET
Processor initialization or startup is accomplished by driving the RES input pin Low. RES
must be Low during power-up to ensure proper device initialization. RES forces the
Am186ER and Am188ER microcontrollers to terminate all execution and local bus activity.
No instruction or bus activity occurs as long as RES is active.
After RES is deasserted and an internal processing interval elapses, the microcontroller
begins execution with the instruction at physical location FFFF0h. RES also sets some
registers to predefined values as shown in Table 4-2.
4-8
Peripheral Control Block
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 4-2
Initial Register State After Reset
Value at
Register Name
Mnemonic
Reset
Comments
Processor Status Flags
Instruction Pointer
Code Segment
F
F002h
Interrupts disabled
IP
0000h
FFFFh
0000h
0000h
0000h
XXxxh
20FFh
CS
Boot address is FFFF0h
DS = ES = SS = 0000h
Data Segment
DS
Extra Segment
ES
Stack Segment
SS
Processor Release Level
PRL
RELREG
PRL XX = Revision (lower half-word is undefined)
Peripheral Control Block
Relocation
Peripheral control block located at FF00h in I/O space
and interrupt controller in Master mode
Memory Partition
MDRAM
EDRAM
UMCS
0000h
0000h
F03Bh
Refresh base address is 00000h
Refresh disabled, counter = 0
Enable RCU
Upper Memory Chip Select
UCS active for 64K from F0000h to FFFFFh, 3 wait
states, external Ready signal required
Low Memory Chip Select
Serial Port Control
LMCS
SPCT
Undefined
0000h
Serial port interrupts disabled, no loopback, no break,
BRKVAL low, no parity, word length = 7, 1 stop bit,
transmitter and receiver disabled
PIO Direction 1
PIO Mode 1
PIODIR1
FFFFh
PIOMODE1 0000h
PIODIR0 FC0Fh
PIOMODE0 0000h
PIO Direction 0
PIO Mode 0
Serial Port Interrupt Control SPICON
001Fh
000Fh
Serial port interrupt masked, priority 7
Watchdog Timer Interrupt
Control
WDCON
Watchdog timer interrupt masked, priority 7
INT4 Control
I4CON
I3CON
I2CON
I1CON
I0CON
000Fh
000Fh
000Fh
000Fh
000Fh
Int4 interrupt masked, edge-triggered, priority 7
Int3 interrupt masked, edge-triggered, priority 7
Int2 interrupt masked, edge-triggered, priority 7
Int1 interrupt masked, edge-triggered, priority 7
Int0 interrupt masked, edge-triggered, priority 7
DMA1 interrupts masked, edge-triggered, priority 7
DMA0 interrupts masked, edge-triggered, priority 7
Timer interrupts masked, edge-triggered, priority 7
No interrupts are in-service
INT3 Control
INT2 Control
INT1 Control
INT0 Control
DMA1 Interrupt Control
DMA0 Interrupt Control
Timer Interrupt Control
In-Service
DMA1CON 000Fh
DMA0CON 000Fh
TCUCON
INSERV
PRIMSK
IMASK
000Fh
0000h
0007h
07FDh
0000h
0000h
Priority Mask
Allow all interrupts based on priority
Interrupt Mask
All interrupts masked (off)
Synchronous Serial Control SSC
SCLK = 1/2 CLKOUTA, no data enabled
Synchronous Serial Status
SSS
Synchronousserialportnotbusy, noerrors, notransmit
or receive completed.
DMA 1 Control
DMA 0 Control
D1CON
D0CON
FFF9h
FFF9h
Note:
Registers not listed in this table are undefined at reset.
Peripheral Control Block
4-9
Download from Www.Somanuals.com. All Manuals Search And Download.
4-10
Peripheral Control Block
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
CHIP SELECT UNIT
5
5.1
OVERVIEW
The Am186ER and Am188ER microcontrollers contain logic that provides programmable
chip select generation for both memories and peripherals. In addition, the logic can be
programmed to provide ready or wait-state generation and latched address bits A1 and A2.
The chip select lines are active for all memory and I/O cycles in their programmed areas,
whether they are generated by the CPU or by the integrated DMA unit.
The Am186ER and Am188ER microcontrollers provide six chip select outputs for use with
external memory devices and six more for use with peripherals in either memory space or
I/O space. The six memory chip selects can be used to address three memory ranges.
Each peripheral chip select addresses a 256-byte block offset from a programmable base
address (see section 4.1.1 on page 4-4).
The Am186ER and Am188ER microcontrollers also provide 32-Kbyte of internal memory,
describedin Chapter 6.The InternalMemoryChipSelectRegisterisdescribed on page 6-3.
The chip selects are programmed through the use of five 16-bit peripheral registers (Table
5-1). The UMCS Register, offset A0h, is used to program the Upper Memory Chip Select
(UCS). The LMCS Register, offset A2h, is used to program the Lower Memory Chip Select
(LCS). The Midrange Memory Chip Selects (MCS3–MCS0) are programmed through the
use of two registers—the Midrange Memory Chip Select (MMCS) Register, offset A6h and
the PCS and MCS Auxiliary (MPCS) Register, offsetA8h. In addition to its use in configuring
the MCS chip selects, the MPCS Register and the PACS Register are used to program the
Peripheral Chip Selects (PCS6–PCS5 and PCS3–PCS0).
Note: The PCS4 chip select is not implemented on the Am186ER and Am188ER
microcontrollers.
Table 5-1
Chip Select Register Summary
Register
Offset Mnemonic
Register Name
Affected Pins
UCS
Comments
A0h
UMCS
LMCS
Upper Memory Chip Select
Lower Memory Chip Select
Ending address is fixed at FFFFFh
Starting address is fixed at 00000h
A2h
A4h
LCS
PCS6–PCS5
PCS3–PCS0
PACS
Peripheral Chip Select
Block size is fixed at 256 bytes
Starting address and block size are
programmable
A6h
MMCS
Midrange Chip Select
MCS3–MCS0
PCS6–PCS5
PCS3–PCS0
MCS3–MCS0
Affects both PCS and MCS
chip selects
A8h
ACh
MPCS
IMCS
PCS and MCS Auxiliary
Internal Memory Chip Select None.
See Chapter 6, “Internal Memory.”
Note: A write will enable an external memory or peripheral chip select register.
Chip Select Unit
5-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Except for the UCS chip select, which is active on reset as discussed in section 5.5.1,
external memory chip selects are not activated until the associated registers have been
accessed by a write operation. The LCS chip select is activated when the LMCS Register
is written, the MCS chip selects are activated after both the MMCS and MPCS registers
have been written, and the PCS chip selects are activated after both the PACS and MPCS
registers have been written.
5.2
5.3
CHIP SELECT TIMING
The timing for the UCS and LCS outputs has been modified from the 80C186 and 80C188
microcontrollers. These outputs now assert in conjunction with the demultiplexed address
bus (A19–A0) for normal memory timing. To make these outputs available earlier in the
bus cycle, the number of programmable memory size selections has been reduced.
The MCS3–MCS0 and PCS chip selects assert with the AD bus.
READY AND WAIT-STATE PROGRAMMING
The Am186ER and Am188ER microcontrollers can be programmed to sense a ready signal
for each of the peripheral or memory chip select lines. The ready signal can be either the
ARDY or SRDY signal. Each external chip select control register (UMCS, LMCS, MMCS,
PACS, and MPCS) contains a single-bit field, R2, that determines whether the external
ready signal is required or ignored. When R2 is set to 1, external ready is ignored. When
R2 is set to 0, external ready is required.
The number of wait states to be inserted for each access to a peripheral or memory region
is programmable. Zero wait states to 15 wait states can be inserted for the PCS3–PCS0
peripheral chip selects. Zero wait states to three wait states can be inserted for all other
chip selects.
Each of the external chip select control registers other than the PACS Register (UMCS,
LMCS, MMCS, and MPCS) contains a two-bit field, R1–R0, whose value determines the
number of wait states from zero to three to be inserted. A value of 00b in this field specifies
no inserted wait states. A value of 11b specifies three inserted wait states.
The PCS3–PCS0 peripheral chip selects can be programmed for up to 15 wait states. The
PACS Register uses bits R3 and R1–R0 for the additional wait states.
When external ready is required (R2 is set to 0), internally programmed wait states will
always complete before external ready can terminate or extend a bus cycle. For example,
if the internal wait states are set to insert two wait states (R1–R0 = 10b), the processor
samples the external ready pin during the first wait-state cycle. If external ready is asserted
at that time, the access completes after six cycles (four cycles plus two wait states). If
external ready is not asserted during the first wait state, the access is extended until ready
is asserted, which is followed by one more wait state followed by t .
4
5.4
CHIP SELECT OVERLAP
Although programming the various chip selects on the Am186ER microcontroller so that
multiplechipselectsignalsareassertedforthesamephysicaladdressisnotrecommended,
it may be unavoidable in some systems. In such systems, the chip selects whose assertions
overlapmusthavethesameconfigurationforready(externalreadyrequiredornotrequired)
and the number of wait states to be inserted into the cycle by the processor.
Theperipheralcontrolblock(PCB)isaccessedusinginternalsignals.Theseinternalsignals
function as chip selects configured with zero wait states and no external ready. Therefore,
the PCB can be programmed to addresses that overlap external chip select signals if those
external chip selects are programmed to zero wait states with no external ready required.
5-2
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
When overlapping an additional chip select with either the LCS or UCS chip selects, it must
be noted that setting the Disable Address (DA) bit in the LMCS or UMCS Register will
disable the address from being driven on the AD bus for all accesses for which the
associated chip select is asserted, including any accesses for which multiple chip selects
assert.
The MCS and PCS chip select pins can be configured as either chip selects (normal
function) or as PIO inputs or outputs. It should be noted, however, that the ready and wait
state generation logic for these chip selects is in effect regardless of their configurations
as chip selects or PIOs. This means that if these chip selects are enabled (by a write to the
MMCS and MPCS registers for the MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects), the ready and wait state programming for these signals
must agree with the programming for any other chip selects with which their assertion would
overlap if they were configured as chip selects.
Although the PCS4 signal is not available on an external pin, the ready and wait state logic
for this signal still exists internal to the part. For this reason, the PCS4 address space must
follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6–PCS5
is disabled when these signals are configured as address bits A2–A1.
Failure to configure overlapping chip selects with the same ready and wait state
requirements may cause the processor to hang with the appearance of waiting for a ready
signal. This behavior may occur even in a system in which ready is always asserted (ARDY
or SRDY tied High).
Configuring PCS in I/O space with LCS or any other chip select configured for memory
address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers
to configurations where more than one chip select asserts for the same physical address.
5.5
CHIP SELECT REGISTERS
The following sections describe the chip select registers.
Chip Select Unit
5-3
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5.1
Upper Memory Chip Select Register (UMCS, Offset A0h)
The Am186ER and Am188ER microcontrollers provide the UCS chip select pin for the top
of memory. On reset, the microcontroller begins fetching and executing instructions starting
at memory location FFFF0h, so upper memory is usually used as instruction memory. To
facilitate this usage, UCS defaults to active on reset with a default memory range of 64
Kbyte from F0000h to FFFFFh, external ready required, and three wait states automatically
inserted.
The UCS memory range always ends at FFFFFh. The lower boundary is programmable.
Figure 5-1
Upper Memory Chip Select Register (UMCS, offset A0h)
7
0
15
1
0 0 0 0
0
1 1 1
A19
DA
R2 R1–R0
LB2–LB0
The value of the UMCS Register at reset is F03Bh.
Bit 15: Reserved—Set to 1.
Bits 14–12: Lower Boundary (LB2–LB0)—The LB2–LB0 bits define the lower bound of
the memory accessed through the UCS chip selects. The number of programmable bits
has been reduced from eight bits in the 80C186 and 80C188 microcontrollers to three bits
in the Am186ER and Am188ER microcontrollers.
The Am186ER and Am188ER microcontrollers provide an additional block size of 512K,
possible configurations and differences with the 80C186 and 80C188 microcontrollers.
Table 5-2
UMCS Block Size Programming Values
Memory
Block
Size
Starting
Address
LB2–LB0
Comments
64K
128K
256K
512K
F0000h
E0000h
C0000h
80000h
111b
Default
110b
100b
000b
Not available on the 80C186 or 80C188 microcontroller
5-4
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
Bits 11–8: Reserved
Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during
the address phase of a bus cycle when UCS is asserted. If DA is set to 1, AD15–AD0 is
not driven during the address phase of a bus cycle when UCS is asserted. If DA is set to
0, AD15–AD0 is driven during the address phase of a bus cycle. Disabling AD15–AD0
reduces power consumption. DA defaults to 0 at power-on reset.
Note: On the Am188ER microcontroller, the AO15–AO8 address pins are driven during
the data phase of the bus cycles, even when the DA bit is set to 1 in either the UMCS or
LMCS Register.
If BHE/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is held Low on the
rising edge of RES, then AD15–AD0 is always driven regardless of the DA setting. This
configures AD15–AD0 to be enabled regardless of the setting of DA.
If BHE/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is High on the rising
edge of RES, then DA in the Upper Memory Chip Select (UMCS) Register and DA in the
Lower Memory Chip Select (LMCS) Register control the AD15–AD0 disabling.
See the descriptions of the BHE/ADEN and RFSH2/ADEN pins in Chapter 3.
Bits 6: Reserved—Set to 0.
Bits 5–3: Reserved—Set to 1.
Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the UCS
chip select. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is
ignored. In each case, the processor also uses the value of the R1–R0 bits to determine
the number of wait states to insert. R2 defaults to 0 at reset.
Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait
states inserted into an access to the UCS memory area. From zero to three wait states can
be inserted (R1–R0 = 00b to 11b). R1–R0 default to 11b at reset.
Chip Select Unit
5-5
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5.2
Low Memory Chip Select Register (LMCS, Offset A2h)
The Am186ER and Am188ER microcontrollers provide the LCS chip select pin for the
bottom of memory. Because the interrupt vector table is located at 00000h at the bottom
of memory, the LCS pin has been provided to facilitate this usage. The LCS pin is not active
on reset, but any write access to the LMCS Register activates this pin.
Figure 5-2
Low Memory Chip Select Register (LMCS, offset A2h)
7
0
15
1 1 1 1
1 1
1
0
A19
R1–R0
R2
UB2–UB0
DA PSE
The value of the LMCS Register at reset is undefined.
Bit 15: Reserved—Set to 0.
Bits 14–12: Upper Boundary (UB2–UB0)—The UB2–UB0 bits define the upper boundary
of the memory accessed through the LCS chip select. Because of the timing requirements
of the LCS output and the nonmultiplexed address bus, the number of programmable
memory sizes for the LMCS Register is reduced compared to the 80C186 and 80C188
microcontrollers. Consequently, the number of programmable bits has been reduced from
eight bits in the 80C186 and 80C188 microcontrollers to three bits in the Am186ER and
Am188ER microcontrollers.
The Am186ER and Am188ER microcontrollers have a block size of 512 Kbyte, which is
configurations and the differences between the 80C186 and 80C188 microcontrollers and
the Am186ER and Am188ER microcontrollers.
Table 5-3
LMCS Block Size Programming Values
Memory
Block
Size
Ending
Address UB2–UB0
Comments
64K
0FFFFh
1FFFFh
3FFFFh
7FFFFh
000b
001b
011b
111b
128K
256K
512K
Not available on the 80C186 and 80C188 microcontrollers
5-6
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
Bits 11–8: Reserved—Set to 1.
Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during
the address phase of a bus cycle when LCS is asserted. If DA is set to 1, AD15–AD0 is
not driven during the address phase of a bus cycle when LCS is asserted. If DA is set to
0, AD15–AD0 is driven during the address phase of a bus cycle. Disabling AD15–AD0
reduces power consumption.
Note: On the Am188ER microcontroller, the AO15–AO8 address pins are driven during
the data phase of the bus cycles, even when the DA bit is set to 1 in either the Upper
Memory Chip Select Register (UMCS) or the Low Memory Chip Select Register (LMCS).
If BHE/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is held Low on the
rising edge of RES, then AD15–AD0 is always driven regardless of the DA setting. This
configures AD15–AD0 to be enabled regardless of the setting of DA.
If BHE/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is High on the rising
edge of RES, then the DA bit in the UMCS Register and the DA bit in the LMCS Register
control the AD15–AD0 disabling.
See the descriptions of the BHE/ADEN and RFSH2/ADEN pins in Chapter 3.
Bit 6: PSRAM Mode Enable (PSE)—The PSE bit is used to enable PSRAM support for
the LCS chip select memory space. When PSE is set to 1, PSRAM support is enabled.
When PSE is set to 0, PSRAM support is disabled. The refresh control unit registers
EDRAM, MDRAM, and CDRAM, must be configured for auto refresh before PSRAM
support is enabled.
Bits 5–3: Reserved—Set to 1.
Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the LCS
chip select. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is
ignored. In each case, the processor also uses the value of the R1–R0 bits to determine
the number of wait states to insert.
Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait
states inserted into an access to the LCS memory area. From zero to three wait states can
be inserted (R1–R0 =00b to 11b).
Chip Select Unit
5-7
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5.3
Figure 5-3
5-8
Midrange Memory Chip Select Register (MMCS, Offset A6h)
The Am186ER and Am188ER microcontrollers provide fourchip selectpins, MCS3–MCS0,
for use within a user-locatable memory block. The base address of the memory block can
be located anywhere within the 1-Mbyte memory address space, exclusive of the areas
associated with the UCS and LCS chip selects (and, if they are mapped to memory, the
address range of the Peripheral Chip Selects, PCS6–PCS5 and PCS3–PCS0). The MCS
address range can overlap the PCS address range if the PCS chip selects are mapped to
I/O space.
The Midrange Memory Chip Selects are programmed through two registers. The Midrange
the ready condition and wait states of the memory block accessed through the MCS pins.
The PCS and MCS Auxiliary (MPCS) Register is used to configure the block size. The
MCS3–MCS0 pins are not active on reset. Both the MMCS and MPCS registers must be
accessed with a write to activate these chip selects.
Unlike the UCS and LCS chip selects, the MCS3–MCS0 outputs assert with the multiplexed
AD address bus (AD15–AD0 or AO15–AO8 and AD7–AD0) rather than the earlier timing
of the A19–A0 bus. The A19–A0 bus can still be used for address selection, but the timing
is delayed for a half cycle later than that for UCS and LCS.
Note: The MCS3–MCS0 pins are multiplexed with programmable I/O pins. To enable the
MCS3–MCS0 pins to function as chip selects, the PIO mode and PIO direction settings for
the MCS3–MCS0 pins must be set to 0 for normal operation. For more information, see
Chapter 13, “Programmable I/O Pins.”
The Midrange Memory Chip Selects are configured by the MMCS Register (Figure 5-3).
Midrange Memory Chip Select Register (MMCS, offset A6h)
7
0
15
BA19–BA13
1 1 1 1 1
1
R2 R1–R0
The value of the MMCS Register at reset is undefined.
Bits 15–9: Base Address (BA19–BA13)—The base address of the memory block that is
addressed by the MCS chip select pins is determined by the value of BA19–BA13. These
bits correspond to bits A19–A13 of the 20-bit memory address. Bits A12–A0 of the base
address are always 0.
The base address can be set to any integer multiple of the size of the memory block size
selected in the MPCS Register. For example, if the midrange block is 32 Kbyte, the block
could be located at 10000h or 18000h but not at 14000h.
The base address of the midrange chip selects can be set to 00000h only if the LCS chip
select is not active. This is because the LCS base address is defined to be address 00000h
and chip select address ranges are not allowed to overlap. Because of the additional
restriction that the base address must be a multiple of the block size, a 512K MMCS block
size can only be used when located at address 00000h, and the LCS chip selects must not
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
be active in this case. Use of the MCS chip selects to access low memory allows the timing
of these accesses to follow the AD address bus rather than the A address bus. Locating a
512K MMCS block at 80000h always conflicts with the range of the UCS chip select and
is not allowed.
Bits 8–3: Reserved—Set to 1.
Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the MCS
chip selects. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is
ignored. In each case, the processor also uses the value of the R1–R0 bits to determine
the number of wait states to insert.
Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait
states inserted into an access to the MCS memory area. From zero to three wait states
can be inserted (R1–R0 = 00b to 11b).
Chip Select Unit
5-9
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5.4
PCS and MCS Auxiliary Register (MPCS, Offset A8h)
select control registers in that it contains fields that pertain to more than one type of chip
select. The MPCS Register fields provide program information for MCS3–MCS0 as well as
PCS6–PCS5 and PCS3–PCS0.
In addition to its function as a chip select control register, the MPCS Register contains a
field that configures the PCS6–PCS5 pins as either chip selects or as alternate sources for
the A2 and A1 address bits. When programmed to provide address bits A1 and A2, PCS6–
PCS5 cannot be used as peripheral chip selects. These outputs can be used to provide
latched address bits for A2 and A1.
On reset, PCS6–PCS5 are not active. If PCS6–PCS5 are configured as address pins, a
write access to the MPCS Register causes the pins to activate. No corresponding access
to the PACS Register is required to activate the PCS6–PCS5 pins as addresses.
Figure 5-4
PCS and MCS Auxiliary Register (MPCS, offset A8h)
7
0
15
1
M6–M0
1 1
1
R2 R1–R0
MS
EX
The value of the MPCS Register at reset is undefined.
Bit 15: Reserved—Set to 1.
Bits 14–8: MCS Block Size (M6–M0)—This field determines the total block size for the
MCS3–MCS0 chip selects. Each individual chip select is active for one quarter of the total
Only one of the M6–M0 bits can be set at any time. If more than one of the M6–M0 bits is
set, unpredictable operation of the MCS lines occurs.
Table 5-4
MCS Block Size Programming
Total Block
Size
Individual
Select Size
M6–M0
8K
2K
4K
0000001b
0000010b
0000100b
0001000b
0010000b
0100000b
1000000b
16K
32K
8K
64K
16K
32K
64K
128K
128K
256K
512K
5-10
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
Bit7:Pin Selector(EX)—Thisbitdetermineswhetherthe PCS6–PCS5pinsareconfigured
as chip selects or as alternate outputs for A2–A1. When this bit is set to 1, PCS6–PCS5
are configured as peripheral chip select pins. When EX is set to 0, PCS5 becomes address
bit A1 and PCS6 becomes address bit A2.
Bit 6: Memory/ I/O Space Selector (MS)—This bit determines whether the PCS pins are
active during memory bus cycles or I/O bus cycles. When MS is set to 1, the PCS outputs
are active for memory bus cycles. When MS is set to 0, the PCS outputs are active for I/O
bus cycles.
Bits 5–3: Reserved—Set to 1.
Bit 2: Ready Mode (R2)—This bit applies only to the PCS6–PCS5 chip selects. If R2 is
set to 0, external ready is required. If R2 is set to 1, external ready is ignored. In each case,
the processor also uses the value of the R1–R0 bits to determine the number of wait states
to insert.
Bits 1–0: Wait-State Value (R1–R0)—These bits apply only to the PCS6–PCS5 chip
selects. The value of R1–R0 determines the number of wait states inserted into an access
to the PCS memory or I/O area. From zero to three wait states can be inserted
(R1–R0 = 00b to 11b).
Chip Select Unit
5-11
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5.5
Peripheral Chip Select Register (PACS, Offset A4h)
Unlike the UCS and LCS chip selects, the PCS outputs assert with the same timing as the
multiplexed AD address bus. Also, each peripheral chip select asserts over a 256-byte
address range, which is twice the address range covered by peripheral chip selects in the
80C186 and 80C188 microcontrollers.
The Am186ER and Am188ER microcontrollers provide six chip selects, PCS6–PCS5 and
PCS3–PCS0, for use within a user-locatable memory or I/O block. (PCS4 is not
implemented on the Am186ER and Am 188ER microcontrollers.) The base address of the
memory block can be located anywhere within the 1-Mbyte memory address space,
exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can
be configured to access the 64-Kbyte I/O space.
The Peripheral Chip Selects are programmed through two registers—the Peripheral Chip
Select (PACS) Register and the PCS and MCS Auxiliary (MPCS) Register. The Peripheral
and the wait states for the PCS3–PCS0 outputs.
the PCS6–PCS5 pins as either chip selects or address pins A1 and A2. When the PCS6–
PCS5 pins are chip selects, the MPCS Register also determines whether PCS chip selects
are active during memory or I/O bus cycles and specifies the ready and wait states for the
PCS6–PCS5 outputs.
The PCS pins are not active on reset. The PCS pins are activated as chip selects by writing
to both the PACS and MPCS registers.
PCS6–PCS5 can be configured and activated as address pins by writing only the MPCS
Register. No corresponding access to the PACS Register is required in this case.
PCS3–PCS0 can be configured for zero wait states to 15 wait states. PCS6–PCS5 can be
configured for zero wait states to three wait states.
Note: The PCS3–PCS0 and PCS6–PCS5 pins are multiplexed with programmable I/O
pins. To enable the PCS3–PCS0 and PCS6–PCS5 pins to function as chip selects, the PIO
mode and PIO direction settings for the PCS3–PCS0 and PCS6–PCS5 pins must be set
to 0 for normal operation. For more information, see Chapter 13, “Programmable I/O Pins.”
Figure 5-5
Peripheral Chip Select Register (PACS, offset A4h)
7
0
15
BA19–BA11
1
1 1
R3
R1–R0
R2
The value of the PACS Register at reset is undefined.
Bits 15–7: Base Address (BA19–BA11)—The base address of the peripheral chip select
block is defined by BA19–BA11 of the PACS Register. BA19–BA11 correspond to bits
19–11 of the 20-bit programmable base address of the peripheral chip select block. Bit 6
of the PACS Register corresponds to bit 10 of the base address in the 80C186 and 80C188
microcontrollers, and is not implemented. Thus, code previously written for the 80C186
5-12
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
microcontrollerinwhich bit6wassetwitha meaningfulvaluewouldnotproducethe address
expected on the Am186ER.
When the PCS chip selects are mapped to I/O space, BA19–16 must be programmed to
0000b because the I/O address bus is only 16-bits wide.
Table 5-5
PCS Address Ranges
Range
PCS Line
Low
High
PCS0
PCS1
PCS2
PCS3
Base Address
Base Address+255
Base Address+256 Base Address+511
Base Address+512 Base Address+767
Base Address+768 Base Address+1023
Reserved N/A
N/A
PCS5
PCS6
Base Address+1280 Base Address+1535
Base Address+1536 Base Address+1791
Bits 6–4: Reserved—Set to 1.
Bit 3: Wait-State Value (R3)—If this bit is set to 0, the number of wait states from zero to
three is encoded in the R1–R0 bits. In this case, R1–R0 encodes from zero (00b) to three
(11b) wait states.
When R3 is set to 1, the four possible values of R1–R0 encode four additional wait-state
values as follows: 00b = 5 wait states, 01b = 7 wait states, 10b = 9 wait states, and
Table 5-6
PCS3–PCS0 Wait-State Encoding
R3
0
R1
0
R0
0
Wait States
0
1
0
0
1
0
1
0
2
0
1
1
3
1
0
0
5
1
0
1
7
1
1
0
9
1
1
1
15
Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the PCS3–
PCS0 chip selects. If R2 is set to 0, external ready is required. External ready is ignored
when R2 is set to 1. In each case, the processor also uses the value of the R3 and R1–R0
bits to determine the number of wait states to insert. The Ready mode for PCS6–PCS5 is
configured through the MPCS Register.
Bits 1–0: Wait-State Value (R1–R0)—The value of R3 and R1–R0 determines the number
of wait states inserted into a PCS3–PCS0 access. Up to 15 wait states can be inserted.
See the discussion of bit 3 (R3) for the wait-state encoding of R1–R0.
From zero to three wait states for the PCS6–PCS5 outputs are programmed through the
R1–R0 bits in the MPCS Register.
Chip Select Unit
5-13
Download from Www.Somanuals.com. All Manuals Search And Download.
5-14
Chip Select Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
INTERNAL MEMORY
6
6.1
OVERVIEW
The Am186ER and Am188ER microcontrollers provide 32 Kbyte of on-chip RAM. The
integration of memory helps reduce a system design’s overall cost, size, and power
consumption.
The internal RAM for the Am186ER microcontroller is a 16K x 16-bit-wide array, which
provides the same performance as 16-bit external zero-wait-state RAM. The internal RAM
for the Am188ER microcontroller is a 32K x 8-bit-wide array, which provides the same
performance as 8-bit external zero-wait-state RAM.
6.2
INTERACTION WITH EXTERNAL RAM
The Am186ER and Am188ER microcontrollers include an Internal Memory Chip Select
(IMCS) Register to enable and control the mapping of the internal RAM. For a detailed
description of the IMCS Register, see “Internal Memory Chip Select Register (IMCS, Offset
The IMCS Register can be configured to locate the internal address space at any 32-Kbyte
boundary within the 1-Mbyte memory address space. The base address is determined by
the value of bits BA19–BA15 in the IMCS Register.
If the internal memory overlaps with an external memory chip select, the external memory
chip select must be set to zero wait states with no external ready required. If internal and
external chip selects overlap, both will be active, but the internal memory data will be used
on reads. Writes, with all the corresponding external control signals, will occur to both
devices. Special system consideration must be made if the show read enable feature
internal memory read cycles.
If internal and external chip selects overlap and the external chip selects are not set to zero
wait states with no external ready required, the results are unpredictable. Note that because
of the many potential problems with overlapping chip selects, this practice is not
recommended.
A memory overlap might be unavoidable in some designs, however. Because the interrupt
vector table is located at 00000h, it is not unusual to store the interrupt vector table in the
internal RAM for faster access, and thus program the IMCS Register for a base address
of 0. This situation could lead to a memory address overlap between the IMCS and low
memory chip select (LMCS) registers, as the base address of the LMCS Register is always
0ifactivated. Formoreinformation aboutthe LMCS Register, see“LowMemoryChipSelect
Register (LMCS, Offset A2h)” on page 5-6.
Internal Memory
6-1
Download from Www.Somanuals.com. All Manuals Search And Download.
6.3
EMULATOR AND DEBUG MODES
There are two debug modes associated with the internal memory. One mode allows users
to disable the internal RAM, and the other mode makes it possible to drive data on the
external data bus during internal RAM read cycles.
Normal operation of internal RAM has all control signals for reads and writes and data for
writes visible externally. Accesses to internal memory can be detected externally by
comparing the address on A19–A0 with the address space of the internal memory.
6.3.1
6.3.2
Internal Memory Disable
When this mode is activated, the internal RAM is disabled and all accesses into the internal
memory space are made externally for debugging purposes. This mode is activated by
pulling the S1/IMDIS pin Low during reset. To use this debug mode, internal memory space
must first be activated via the IMCS Register as described on page 6-3.
Show Read Enable
When this mode is activated, the data from the internal RAM read cycles are driven on the
AD15–AD0 bus. Note that if a byte read is being shown, the unused byte will also be driven
on the AD15–AD0 bus. This mode can be activated externally by pulling the S0/SREN pin
Low during reset or by setting the SR bit in the IMCS Register. If this feature is activated
the SREN pin. For more details, see the IMCS Register information on page 6-3.
During an internal memory read with show read enabled, the address will be driven on the
AD bus during t and t . The data being read will be driven on the AD bus during t and t
1
2
3
4
by the Am186ER or Am188ER microcontrollers. Special system care must be taken to
avoid bus contention, since normal reads have the AD bus three-stated during t , t , and
2
3
t . It is best to ensure that no external device overlaps the internal memory space.
4
6-2
Internal Memory
Download from Www.Somanuals.com. All Manuals Search And Download.
6.4
INTERNAL MEMORY CHIP SELECT REGISTER (IMCS, OFFSET ACh)
The Internal Memory Chip Select (IMCS) Register provides programmable chip select
generation for the internal RAM. It allows the base address of the internal memory space
to be placed on any 32-Kbyte boundary. The register also contains a control bit to enable
the internal memory and another to enable data read from the internal memory to be driven
on the external data bus. Because the internal RAM always executes zero-wait-state
accesses, a ready bit and wait-state bits are not included. The format of the IMCS Register
Unlike the other Am186ER and Am188ER chip selects, writing to the IMCS will not activate
internal memory space. To activate the internal memory space, set a base address and
set the RE bit to 1.
Figure 6-1
Internal Memory Chip Select Register (IMCS, offset ACh)
7
0
15
BA19–BA13
1 1 1 1 1 1 1 1 1
SR
RE
Bits 15–11: Base Address (BA19–BA15)—The base address of the internal RAM is
determined by the value of BA19–BA15, which corresponds to bits A19–A15 of the 20-bit
memory address. The base address can only be set on a 32-Kbyte boundary. The value
of this field is undefined after processor reset.
Bit 10: Show Read (SR)—Setting the SR bit enables data to be driven on the AD15–AD0
bus during internal RAM cycles for debugging purposes. Note that if a byte read is being
shown, the corresponding unused byte will also be driven on the AD15–AD0 bus. This
mode can also be enabled externally by asserting the SREN pin which is sampled on the
rising edge of RES. If this mode is enabled via SREN, the value of the SR bit is ignored.
This bit is 0 after processor reset.
Bit 9: Internal RAM Enable (RE)—If the RE bit is set to 1, the internal RAM is enabled.
When this bit is 0, internal RAM is disabled. The internal RAM is enabled by setting a base
address and setting the RE bit to 1. This is different from the other chip selects on the
Am186ER and Am188ER microcontrollers, which are activated by a write to their
corresponding chip select register. This bit is 0 after processor reset.
Bits 8–0: Reserved—Set to 1.
Internal Memory
6-3
Download from Www.Somanuals.com. All Manuals Search And Download.
6-4
Internal Memory
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
REFRESH CONTROL UNIT
7
7.1
OVERVIEW
The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a
programmable period of time, the RCU generates a memory read request to the bus
interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode.
The Refresh Control Unit operates off the processor internal clock. If the Power-Save mode
is in effect, the Refresh Control Unit must be reprogrammed to reflect the new clock rate.
If the HLDA pin is active when a refresh request is generated (indicating a bus hold
condition), then the microcontroller deactivates the HLDA pin in order to perform a refresh
cycle. The circuit external bus master must remove the HOLD signal for at least one clock
to allow the refresh cycle to execute.
7.1.1
Memory Partition Register (MDRAM, Offset E0h)
Figure 7-1
Memory Partition Register (MDRAM, offset E0h)
7
0
15
0 0 0 0 0 0 0 0 0
M6–M0
RA19
RA13
The MDRAM Register is set to 0000h on reset.
Bits 15–9: Refresh Base (M6–M0)—Upper bits corresponding to address bits A19–A13
of the 20-bit memory refresh address. Because these bits are available only on the AD bus,
the AD bit must not be set in the LMCS Register if the refresh control unit is used. When
using PSRAM mode, M6–M0 must be programmed to 0000000b.
These bits are cleared to 0 at reset.
Bits 8–0: Reserved—Read back as 0.
Refresh Control Unit
7-1
Download from Www.Somanuals.com. All Manuals Search And Download.
7.1.2
Clock Prescaler Register (CDRAM, Offset E2h)
Figure 7-2
Clock Prescaler Register (CDRAM, offset E2h)
7
0
15
0 0 0 0 0 0 0
RC8–RC0
The CDRAM Register is undefined on reset.
Bits 15–9: Reserved—Read back as 0.
Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired
clock count interval between refresh cycles. The counter value should not be set to less
than 18 (12h), otherwise there would never be sufficient bus cycles available for the
processor to execute code.
In Power-Save mode, the refresh counter value must be adjusted to take into account the
reduced processor clock rate.
7.1.3
Enable RCU Register (EDRAM, Offset E4h)
Figure 7-3
Enable RCU Register (EDRAM, offset E4h)
7
0
15
0 0 0 0 0 0
T8–T0
E
The EDRAM Register is set to 0000h on reset.
Bit 15: Enable RCU (E)—Enables the refresh counter unit when set to 1. Clearing the E
bit at any time clears the refresh counter and stops refresh requests, but it does not reset
the refresh address. Set to 0 on reset.
Bits 14–9: Reserved—Read back as 0.
Bits 8–0: Refresh Count (T8–T0)—This read-only field contains the present value of the
down counter which triggers refresh requests.
7-2
Refresh Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
INTERRUPT CONTROL UNIT
8
8.1
OVERVIEW
TheAm186ER andAm188ER microcontrollers canreceive interruptrequestsfrom a variety
of sources, both internal and external. The internal interrupt controller arranges these
requests by priority and presents them one at a time to the CPU.
There are six external interrupt sources on the Am186ER and Am188ER microcontrollers—
five maskable interrupt pins (INT4–INT0) and the nonmaskable interrupt (NMI) pin. There
are six internal interrupt sources that are not connected to external pins—three timers, two
DMA channels, and the asynchronous serial port.
The Am186ER and Am188ER microcontrollers provide three interrupts that are not present
on the 80C186 and 80C188 microcontrollers:
n INT4, an additional external interrupt pin that operates like the INT3–INT0 pins
n An internal watchdog timer interrupt
n An internal interrupt from the serial port
The INT4–INT0 interrupt request pins can be used as direct interrupt requests, and can be
either edge triggered or level triggered. If more inputs are needed, INT1 and INT0 can be
configured in Cascade mode for use with an 82C59A-compatible external interrupt
controller, using INT2/INTA0 and INT3/INTA1 for the corresponding interrupt acknowledge
signals. An external interrupt controller can be used as the system master by programming
theinternalinterruptcontrollertooperateinSlavemode.Inallcases,nestingcanbeenabled
that allows high priority interrupts to interrupt lower-priority interrupt service routines.
8.1.1
Definitions of Interrupt Terms
The following definitions cover some of the terminology that is used in describing the
reserved interrupts.
8.1.1.1
Interrupt Type
An 8-bit interrupt type identifies each of the 256 possible interrupts.
Software exceptions, internal peripherals, and non-cascaded external interrupts supply the
interrupt type through the internal interrupt controller.
Cascaded external interrupts and slave-mode external interrupts get the interrupt type from
the external interrupt controller by means of interrupt acknowledge cycles on the bus.
8.1.1.2
Interrupt Vector Table
The interrupt vector table is a memory area of 1 Kbyte beginning at address 00000h that
holds up to 256 four-byte address pointers containing the address for the interrupt service
routine for each possible interrupt type. For each interrupt, an 8-bit interrupt type identifies
the appropriate interrupt vector table entry.
Interrupts 00h to 1Fh are reserved. See Table 8-1.
Interrupt Control Unit
8-1
Download from Www.Somanuals.com. All Manuals Search And Download.
The processor calculates the index to the interrupt vector table by shifting the interrupt type
left 2 bits (multiplying by 4).
8.1.1.3
Maskable and Nonmaskable Interrupts
Interrupt types 08h through 1Fh are maskable. Of these, only 08h through 14h are actually
enableflag(IF)intheprocessorstatusflags,buttheINTcommandcanexecuteanyinterrupt
regardless of the setting of IF.
Interrupt types 00h through 07h and all software interrupts (the INT instruction) are
nonmaskable. The nonmaskable interrupts are not affected by the setting of the IF flag.
The Am186ER and Am188ER microcontrollers provide two methods for masking and
unmasking the maskable interrupt sources. Each interrupt source has an interrupt control
register that contains a mask bit specific to that interrupt. In addition, the Interrupt Mask
Register is provided as a single source to access all of the mask bits.
If the Interrupt Mask Register is written while interrupts are enabled, it is possible that an
interrupt could occur while the register is in an undefined state. This can cause interrupts
tobeacceptedeventhoughtheyweremaskedbothbeforeandafterthewritetotheInterrupt
Mask Register. Therefore, the Interrupt Mask Register should only be written when
interrupts are disabled. Mask bits in the individual interrupt control registers can be written
while interrupts are enabled, and there will be no erroneous interrupt operation.
8.1.1.4
Interrupt Enable Flag (IF)
The interrupt enable flag (IF) is part of the processor status flags (see section 2.1.1 on page
2-2). If IF is set to 1, maskable interrupts are enabled and can cause processor interrupts.
(Individual maskable interrupts can still be disabled by means of the mask bit in each control
register.)
If IF is set to 0, all maskable interrupts are disabled.
The IF flag does not affect the NMI or software exception interrupts (interrupt types 00h to
07h), and it does not affect the execution of any interrupt through the INT instruction.
8.1.1.5
8.1.1.6
Interrupt Mask Bit
Each of the interruptcontrolregisters forthe maskable interrupts contains a mask bit (MSK).
If MSK is set to 1 for a particular interrupt, that interrupt is disabled regardless of the IF
setting.
Interrupt Priority
fortheinterruptsatpower-onreset.Thenonmaskableinterrupts00hthrough07harealways
prioritized ahead of the maskable interrupts.
The maskable interrupts can be reprioritized by reconfiguring the PR2–PR0 bits in the
interrupt control registers. The PR2–PR0 bits in all the maskable interrupts are set to priority
level 7 at power-on reset.
8.1.1.7
Software Interrupts
Software interrupts can be initiated by the INT instruction. Any of the 256 possible interrupts
can be initiated by the INT instruction. INT 21h causes an interrupt to the vector located at
00084h in the interrupt vector table. INT FFh causes an interrupt to the vector located at
003FCh in the interrupt vector table. Software interrupts are not maskable and are not
affected by the setting of the IF flag.
8-2
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.1.8
Software Exceptions
A software exception interrupt occurs when an instruction causes an interrupt due to some
condition in the processor. Interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are
software exception interrupts. Software exceptions are not maskable and are not affected
by the setting of the IF flag.
Table 8-1
Am186ER and Am188ER Microcontroller Interrupt Types
Interrupt Vector Table
EOI
Type
Overall
Priority
Related
Instructions
Interrupt Name
Type
Address
Notes
Maskable Interrupts
Divide Error Exception
Trace Interrupt
00h
01h
02h
03h
04h
05h
06h
00h
04h
08h
0Ch
10h
14h
18h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1A
1B
1
DIV, IDIV
All
1
2
Nonmaskable Interrupt (NMI)
Breakpoint Interrupt
INT 3
INTO
1
1
1
1
INTO Detected Overflow Exception
Array Bounds Exception
Unused Opcode Exception
1
1
BOUND
1
Undefined
Opcodes
ESC Opcode Exception
07h
1Ch
N/A
1
ESC Opcodes
1, 3
Maskable Interrupts
Timer 0 Interrupt
08h
12h
20h
48h
4Ch
08
08
08
2A
2B
2C
4, 5
4, 5
4, 5
Timer 1 Interrupt
Timer 2 Interrupt
13h
Reserved for AMD Use
DMA 0 Interrupt
09h
0Ah
28h
2Ch
30h
34h
38h
3Ch
40h
44h
50h
0A
0B
0C
0D
0E
0F
10
11
3
4
5
6
7
8
9
9
9
5
5
DMA 1 Interrupt
0Bh
INT0 Interrupt
0Ch
0Dh
0Eh
INT1 Interrupt
INT2 Interrupt
INT3 Interrupt
0Fh
INT4 Interrupt
10h
6
6
6
Watchdog Timer Interrupt
Asynchronous Serial Port Interrupt
Reserved for AMD Use
11h
14h
14
15h–1Fh
Notes:
1 Interrupts generated as a result of an instruction execution.
2 Trace is performed in the same manner as 80C186 and 80C188.
3 An ESC opcode causes a trap. This is part of the 80C186 and 80C188 co-processor interface, which is not
supported on the Am186ER.
4 All three timers constitute one source of request to the interrupt controller. As such, they share the same priority
level with respect to other interrupt sources. However, the timers have a defined priority order among themselves
(2A>2B>2C).
5 The interrupt types of these sources are programmable in Slave mode.
6 Not available in Slave mode.
Interrupt Control Unit
8-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.2
Interrupt Conditions and Sequence
Interrupts are generally serviced as follows.
8.1.2.1
Nonmaskable Interrupts
Nonmaskable interrupts—the trace interrupt, the NMI interrupt, and software interrupts
(including both user-defined INT statements and software exceptions)—are serviced
regardless of the setting of the interrupt enable flag (IF) in the processor status flags.
8.1.2.2
8.1.2.3
Maskable Hardware Interrupts
In order for maskable hardware interrupt requests to be serviced, the IF flag must be set
by the STI instruction, and the mask bit associated with each interrupt must be reset.
The Interrupt Request
When an interrupt is requested, the internal interrupt controller verifies that the interrupt is
enabled and that there are no higher priority interrupt requests being serviced or pending.
If the interrupt request is granted, the interrupt controller uses the interrupt type (see Table
8-1) to access a vector from the interrupt vector table.
Eachinterrupttypehasafour-bytevectoravailableintheinterruptvectortable.Theinterrupt
vector table is located in the 1024 bytes from 00000h to 003FFh. Each four-byte vector
consists of a 16-bit offset (IP) value and a 16-bit segment (CS) value. The 8-bit interrupt
type is shifted left 2 bit positions (multiplied by 4) to generate the index into the interrupt
vector table.
8.1.2.4
Interrupt Servicing
A valid interrupt transfers execution to a new program location based on the vector in the
interrupt vector table. The next instruction address (CS:IP) and the processor status flags
are pushed onto the stack.
The interrupt enable flag (IF) is cleared after the processor status flags are pushed on the
stack, disabling maskable interrupts during the interrupt service routine (ISR).
The segment:offset values from the interrupt vector table are loaded into the code segment
(CS) and the instruction pointer (IP), and execution of the ISR begins.
8.1.2.5
Returning from the Interrupt
The interrupt return (IRET) instruction pops the processor status flags and the return
address off the stack. Program execution resumes at the point where the interrupt occurred.
The interrupt enable flag (IF) is restored by the IRET instruction along with the rest of the
processor status flags. If the IF flag was set before the interrupt was serviced, interrupts
are re-enabled when the IRET is executed. If there are valid interrupts pending when the
IRET is executed, the instruction at the return address is not executed. Instead, the new
interrupt is serviced immediately.
If an ISR intends to permanently modify the value of any of the saved flags, it must modify
the copy of the Processor Status Flags Register that was pushed onto the stack.
8-4
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.3
Interrupt Priority
Table 8-1 shows the predefined types and overall priority structure for the Am186ER and
Am188ERmicrocontrollers.Nonmaskableinterrupts(interrupttypes0–7)arealwayshigher
priority than maskable interrupts. Maskable interrupts have a programmable priority that
can override the default priorities relative to one another.
The levels of interrupt priority are as follows:
n Interrupt priority for nonmaskable interrupts and software interrupts
n Interrupt priority for maskable hardware interrupts
8.1.3.1
8.1.3.2
Nonmaskable Interrupts and Software Interrupt Priority
The nonmaskable interrupts from 00h to 07h and software interrupts (INT instruction)
always take priority over the maskable hardware interrupts. Within the nonmaskable and
software interrupts, the trace interrupt has the highest priority, followed by the NMI interrupt,
followed by the remaining nonmaskable and software interrupts.
After the trace interrupt and the NMI interrupt, the remaining software exceptions are
mutually exclusive and can only occur one at a time, so there is no further priority
breakdown.
Maskable Hardware Interrupt Priority
Beginning with interrupt type 8 (the Timer 0 interrupt), the maskable hardware interrupts
programmable priority is the primary priority for maskable hardware interrupts. The overall
priority is the secondary priority for maskable hardware interrupts.
Because all maskable interrupts are set to a programmable priority of seven on reset, the
overall priority of the interrupts determines the priority in which each interrupt is granted by
the interrupt controller until programmable priorities are changed by reconfiguring the
control registers.
level that is associated with each maskable hardware interrupt. Each of the maskable
hardware interrupts has a programmable priority from zero to seven, with zero being the
highest priority (see Table 8-3, “Priority Level,” on page 8-15).
For example, if the INT4–INT0 interrupts are all changed to programmable priority six and
no other programmable priorities are changed from the reset value of seven, then the INT4–
INT0 interrupts take precedence over all other maskable interrupts. (Within INT4–INT0,
INT0 takes precedence over INT1, and INT1 takes precedence over INT2, etc., because
of the underlying hierarchy of the overall priority.)
Interrupt Control Unit
8-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.4
Software Exceptions, Traps, and NMI
The following predefined interrupts cannot be masked by programming.
8.1.4.1
Divide Error Exception (Interrupt Type 00h)
Generated when a DIV or IDIV instruction quotient cannot be expressed in the number of
destination bits.
8.1.4.2
Trace Interrupt (Interrupt Type 01h)
If the trace flag (TF) in the Processor Status Flags Register is set, the trace interrupt is
generated after most instructions. This interrupt allows programs to execute in single-step
mode. The interrupt is not generated after prefix instructions like REP, instructions that
modify segment registers like POP DS, or the WAIT instruction.
Taking the trace interrupt clears the TF bit after the processor status flags are pushed onto
the stack. The IRET instruction at the end ofthe single step interrupt service routine restores
the processor status flags (and the TF bit) and transfers control to the next instruction to
be traced.
Trace mode is initiated by pushing the processor status flags onto the stack, setting the TF
flag on the stack, and then popping the flags.
8.1.4.3
Nonmaskable Interrupt—NMI (Interrupt Type 02h)
This pin indicates to the microcontroller that an interrupt request has occurred. The NMI
signal is the highest priority hardware interrupt and, unlike the INT4–INT0 pins, cannot be
masked. The microcontroller always transfers program execution to the location specified
by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI
is asserted.
A Low to High transition is required to assert NMI. Pulling the pin High during reset has no
effect on program execution.
Although NMI is the highest priority interrupt source, it does not participate in the priority
resolution process of the maskable interrupts. There is no bit associated with NMI in the
interrupt in-service or interrupt request registers. This means that a new NMI request can
interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF
(interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable
interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI
interrupt service routine, via the STI instruction for example, the fact that an NMI is currently
in service does not have any effect on the priority resolution of maskable interrupt requests.
For this reason, it is strongly advised that the interrupt service routine for NMI not enable
the maskable interrupts.
8-6
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.4.4
8.1.4.5
Breakpoint Interrupt (Interrupt Type 03h)
An interrupt caused by the 1-byte version of the INT instruction (INT3).
INTO Detected Overflow Exception (Interrupt Type 04h)
Generated by an INTO instruction if the OF bit is set in the Processor Status Flags (FLAGS)
Register.
8.1.4.6
Array BOUNDS Exception (Interrupt Type 05h)
Generated by a BOUND instruction if the array index is outside the array bounds. The array
bounds are located in memory at a location indicated by one of the instruction operands.
The other operand indicates the value of the index to be checked.
8.1.4.7
8.1.4.8
Unused Opcode Exception (Interrupt Type 06h)
Generated if execution is attempted on undefined opcodes.
ESC Opcode Exception (Interrupt Type 07h)
Generated if execution of ESC opcodes (D8h–DFh) is attempted. The microcontrollers do
not check the escape opcode trap bit. The return address of this exception points to the
ESC instruction that caused the exception. If a segment override prefix preceded the ESC
instruction, the return address points to the segment override prefix.
Note: All numeric coprocessor opcodes cause a trap. The Am186ER and Am188ER
microcontrollers do not support the numeric coprocessor interface.
Interrupt Control Unit
8-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.5
Interrupt Acknowledge
Interrupts can be acknowledged in two different ways—the internal interrupt controller can
provide the interrupt type or an external interrupt controller can provide the interrupt type.
The processor requires the interrupt type as an index into the interrupt vector table.
When the internal interrupt controller is supplying the interrupt type and INT0 or INT1 is
programmed in Cascade mode, no interrupt acknowledge bus cycles are generated. The
only external indication that an interrupt is being serviced is the processor reading the
interrupt vector table.
When an external interrupt controller is supplying the interrupt type, the processor
written to the AD7–AD0 lines bythe external interruptcontroller during the second bus cycle.
When INT0 is the only pin configured in Cascade mode, it must be programmed to a higher
priority than INT1. When INT1 is the only pin configured in Cascade mode, it must be
programmed to a higher priority than any other maskable interrupt.
Interrupt acknowledge bus cycles have the following characteristics:
n The two interrupt acknowledge cycles are internally locked. (There is no LOCK pin on
the Am186ER and Am188ER microcontrollers.)
n Two idle states are always inserted between the two interrupt acknowledge cycles.
n Wait states are inserted if READY is not returned to the processor.
Figure 8-1
External Interrupt Acknowledge Bus Cycles
T1
T2
T3
T4
Ti
Ti
T1
T2
T3
T4
Interrupt
Acknowledge
Interrupt
Acknowledge
S0–S2
INTA
Internal lock
AD7–AD0
Interrupt
Type
Notes:
1. ALE is active for each INTA cycle.
2. RD is inactive.
8-8
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.1.6
Interrupt Controller Reset Conditions
On reset, the interrupt controller performs the following nine actions:
1. All special fully nested mode (SFNM) bits are reset, implying fully nested mode.
2. All priority (PR) bits in the various control registers are set to 1. This places all sources
at the lowest priority (level 7).
3. All level-triggered mode (LTM) bits are reset to 0, resulting in edge-triggered mode.
4. All interrupt in-service bits are reset to 0.
5. All interrupt request bits are reset to 0.
6. All mask (MSK) bits are set to 1. All interrupts are masked.
7. All cascade (C) bits are reset to 0 (non-cascade).
8. The interrupt priority mask is set to 7, allowing interrupts of all priorities.
9. The interrupt controller is initialized to Master mode.
Interrupt Control Unit
8-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8.2
MASTER MODE OPERATION
This section describes Master mode operation of the internal interrupt controller. See
section 8.4 on page 8-29 for a description of Slave mode operation.
Six pins are provided for external interrupt sources. One of these pins is NMI, the
nonmaskable interrupt. NMI is generally used for unusual events like power failure. The
other five pins can be configured in any of the following ways:
n Fully nested mode—five interrupt lines with internally-generated interrupt types
n Cascade mode one—aninterruptlineand interruptacknowledgeline pairwith externally-
generated interrupt types, plus three interrupt input lines with internally-generated types
n Cascade mode two—two pairs of interrupt and interrupt acknowledge lines with
externally-generated interrupt types, and one interrupt input line (INT4) with internally-
generated type
The basic modes of operation of the interrupt controller in Master mode are similar to the
82C59A. The interrupt controller responds identically to internal interrupts in all three
modes, the difference is only in the interpretation of function of the five external interrupt
pins. The interrupt controller is set into one of these modes by programming the correct
bits in the INT0 and INT1 control registers. The modes of interrupt controller operation are
fully nested mode, Cascade mode, special fully nested mode, and polled mode.
8.2.1
Fully Nested Mode
In fully nested mode, five pins are used as direct interrupt requests as in Figure 8-2. The
interrupt types for these five inputs are generated internally. An in-service bit is provided
for every interrupt source. If a lower-priority device requests an interrupt while the in-service
bit(IS)issetforahigherpriorityinterrupt,nointerruptisgeneratedbythe interruptcontroller.
In addition, if another interrupt request occurs from the same interrupt source while the in-
service bit is set, no interrupt is generated by the interrupt controller. This allows interrupt
service routines operating with interrupts enabled to be suspended only by interrupts of
equal or higher priority than the in-service interrupt.
When an interrupt service routine is completed, the proper IS bit must be reset by writing
the interrupt type to the EOI Register. This is required to allow subsequent interrupts from
this interrupt source and to allow servicing of lower-priority interrupts. A write to the EOI
Register should be executed at the end of the interrupt service routine just before the return
from interrupt instruction.
Figure 8-2
Fully Nested (Direct) Mode Interrupt Controller Connections
Interrupt Source
Interrupt Source
INT0
INT1
Am186ER
or Am188ER
Microcontroller
Interrupt Source
INT2
Interrupt Source
Interrupt Source
INT3
INT4
8-10
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.2.2
Cascade Mode
The Am186ER and Am188ER microcontrollers have five interrupt pins, two of which (INT2
and INT3) have dualfunctions. In fully nested mode, the five pins are used as direct interrupt
inputs and the corresponding interrupt types are generated internally. In Cascade mode,
four of the five pins can be configured into interrupt input and dedicated acknowledge signal
pairs. INT0 can be configured with interrupt acknowledge INTA0 (INT2). INT1 can be
configured with interrupt acknowledge INTA1 (INT3).
External sources in Cascade mode use externally generated interrupt types. When an
interrupt is acknowledged, two INTA cycles are initiated and the type is read into the
to one or two external 82C59A programmable interrupt controllers is provided when the inputs
are configured in Cascade mode.
When INT0 is the only pin configured in Cascade mode, it must be programmed to a higher
priority than INT1. When INT1 is the only pin configured in Cascade mode, it must be
programmed to a higher priority than any other maskable interrupt.
Figure 8-3 shows the interconnection for Cascade mode. INT0 is an interrupt input
interfaced to one 82C59A, and INT2/INTA0 serves as the dedicated interrupt acknowledge
signal to that peripheral. INT1 and INT3/INTA1 are also interfaced to an 82C59A. Each interrupt
and acknowledge pair can be selectively placed in the cascade or non-Cascade mode by
programming the proper value into the INT0 and INT1 control registers. The dedicated
acknowledge signals eliminate the need for external logic to generate INTA and device select
signals.
Cascade mode provides the capability to serve up to 128 external interrupt sources through
the use of externalmaster and slave 82C59As. Three levels of priority are created, requiring
priority resolution in the microcontroller interrupt controller, the master 82C59As, and the
slave 82C59As. If an external interrupt is serviced, one IS bit is set at each of these levels.
When the interrupt service routine is completed, up to three End-Of-Interrupt (EOI) Register
writes must be issued by the program.
Figure 8-3
Cascade Mode Interrupt Controller Connections
Interrupt Sources
INT0
V
CC
82C59A
82C59A
INTA0
Am186ER
or Am188ER
Microcontroller
INT1
V
CC
82C59A
INTA1
82C59A
INT4
Interrupt Sources
Interrupt Control Unit
8-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8.2.3
Special Fully Nested Mode
Special fully nested mode is entered by setting the SFNM bit in the INT0 or INT1 control
82C59A masters or multiple interrupts from the same external interrupt pin when not in
Cascade mode. In this case, the ISRs must be re-entrant.
In fully nested mode, an interrupt request from an interrupt source is not recognized when
the in-service bit for that source is set. In this case, if more than one interrupt source is
connected to an external interrupt controller, all of the interrupts go through the same
Am186ER or Am188ER microcontroller interrupt request pin. As a result, if the external
interrupt controller receives a higher-priority interrupt, its interrupt is not recognized by the
microcontroller until the in-service bit is reset.
In special fully nested mode, the microcontroller’s interrupt controller allows the processor
to take interrupts from an external pin regardless of the state of the in-service bit for an
interrupt source. This allows multiple interrupts from a single pin. An in-service bit continues
to be set, however, to inhibit interrupts from other lower-priority Am186ER or Am188ER
microcontroller interrupt sources.
In special fully nested mode with Cascade mode, when a write is issued to the EOI Register
at the end of the interrupt service routine, software polling of the IS Register in the external
master 82C59A must determine if there is more than one IS bit set. If so, the IS bit in the
microcontroller remains active and the next ISR is entered.
8.2.4
Operation in a Polled Environment
To allow reading of the Poll Register information without setting the indicated in-service bit,
the Am186ER and Am188ER microcontrollers provide a Poll Status Register (Figure 8-15)
in addition to the Poll Register. Poll Register information is duplicated in the Poll Status
Register, but the Poll Status Register can be read without setting the associated in-service
bit. These registers are located in two adjacent memory locations in the peripheral control
block.
The interrupt controller can be used in polled mode if interrupts are not desired. When
polling, interrupts are disabled and software polls the interrupt controller as required. The
Poll Status Register indicates to the processor that an interrupt of high enough priority is
requesting service. Bits4–0 indicatetotheprocessorthe interrupt typeofthehighestpriority
source requesting service. After determining that an interrupt is pending, software reads
the Poll Register (rather than the Poll Status Register), which causes the in-service bit of
the highest priority source to be set.
8.2.5
End-of-Interrupt Write to the EOI Register
A program must write to the EOI Register to reset the in-service (IS) bit when an interrupt
service routine is completed. There are two types of writes to the EOI Register—specific
Non-specific EOI does not specify which IS bit is to be reset. Instead, the interrupt controller
automatically resets the IS bit of the highest priority source with an active service routine.
Specific EOI requires the program to send the interrupt type to the interrupt controller to indicate
the source IS bit that is to be reset. Specific reset is applicable when interrupt nesting is possible
or when the highest priority IS bit that was set does not belong to the service routine in progress.
8-12
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3
MASTER MODE INTERRUPT CONTROLLER REGISTERS
can be read and written unless otherwise specified.
information regarding Slave mode register usage. On reset, the microcontroller is in Master
mode. Bit 14 of the Relocation Register (see Figure 4-2) must be set to initiate Slave mode
operation.
Table 8-2
Interrupt Controller Registers in Master Mode
Register
Mnemonic
Associated
Pins
Offset
3Ah
38h
3Eh
3Ch
40h
36h
34h
32h
Register Name
INT1 Control
INT0 Control
INT3 Control
INT2 Control
INT4 Control
Comments
I1CON
I0CON
I3CON
I2CON
I4CON
INT1
INT0
INT3
INT2
INT4
DRQ1
DRQ0
DMA1CON DMA1 Interrupt Control
DMA0CON DMA0 Interrupt Control
TCUCON
Timer Interrupt Control
TMRIN1
TMRIN0
TMROUT1
TMROUT0
42h
44h
30h
2Eh
WDCON
SPICON
INTSTS
REQST
Watchdog Timer Interrupt Control
Serial Port Interrupt Control
Interrupt Status
TXD, RXD
Interrupt Request
INT4–INT0
Read-only register
DRQ1–DRQ0
2Ch
INSERV
In-Service
INT4–INT0
DRQ1–DRQ0
2Ah
28h
PRIMSK
IMASK
Priority Mask
Interrupt Mask
INT4–INT0
DRQ1–DRQ0
26h
24h
22h
POLLST
POLL
EOI
Poll Status
Poll
Read-only register
Read-only register
Write-only register
End of Interrupt
Interrupt Control Unit
8-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.1
INT0 and INT1 Control Registers
(I0CON, Offset 38h, I1CON, Offset 3Ah)
(Master Mode)
The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to
interrupt type 0Dh.
When Cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin
becomes INTA0, the interrupt acknowledge for INT0.
When Cascade mode is enabled for INT1 by setting the C bit of I1CON to 1, the INT3 pin
becomes INTA1, the interrupt acknowledge for INT1.
When INT0 is the only pin configured in Cascade mode, it must be programmed to a higher
priority than INT1. When INT1 is the only pin configured in Cascade mode, it must be
programmed to a higher priority than any other maskable interrupt.
Figure 8-4
INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah)
7
0
15
Reserved
C
LTM
MSK
PR1
PR2
SFNM
PR0
The value of I0CON and I1CON at reset is 000Fh.
Bits 15–7: Reserved—Set to 0.
Bit 6: Special Fully Nested Mode (SFNM)—When set to 1, enables special fully nested
mode.
Bit 5: Cascade Mode (C)—When set to 1, this bit enables Cascade mode.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT0 or INT1 interrupt request as edge- or level-sensitive. A 1 in this bit
configures INT0 or INT1 as an active High, level-sensitive interrupt. A 0 in this bit configures
INT0 or INT1 as a Low-to-High, edge-triggered interrupt. In either case, INT0 or INT1 must
remain High until they are acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT0 or INT1 signal can cause an
interrupt. A 1 in this bit masks this interrupt source, preventing INT0 or INT1 from causing
an interrupt. A 0 in this bit enables INT0 or INT1 interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
8-14
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT0 or INT1
Table 8-3
Priority Level
Priority
PR2–PR0
0 0 0b
0 0 1b
0 1 0b
0 1 1b
1 0 0b
1 0 1b
1 1 0b
1 1 1b
(High) 0
1
2
3
4
5
6
(Low) 7
Interrupt Control Unit
8-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.2
INT2 and INT3 Control Registers
(I2CON, Offset 3Ch, I3CON, Offset 3Eh)
(Master Mode)
The INT2 interrupt is assigned to interrupt type OEh. The INT3 interrupt is assigned to
interrupt type 0Fh.
The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA0 and INTA1
when Cascade mode is implemented.
Figure 8-5
INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh)
7
0
15
Reserved
MSK
LTM
PR1
PR2
PR0
The value of I2CON and I3CON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT2 or INT3 interrupt request as edge- or level-sensitive. A 1 in this bit
configures INT2 or INT3 as an active High, level-sensitive interrupt. A 0 in this bit configures
INT2 or INT3 as a Low-to-High, edge-triggered interrupt. In either case, INT2 or INT3 must
remain High until it is acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT2 or INT3 signal can cause an
interrupt. A 1 in this bit masks this interrupt source, preventing INT2 or INT3 from causing
an interrupt. A 0 in this bit enables INT2 or INT3 interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT2 or INT3
Note: The INT2 pin is multiplexed with PIO 31. To enable the pin to function as an interrupt
or interrupt acknowledge, the PIO mode and PIO direction settings for the INT2 pin must
be set to 0 for normal operation. For more information, see Chapter 13, “Programmable I/
O Pins.”
8-16
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.3
INT4 Control Register (I4CON, Offset 40h)
(Master Mode)
The Am186ER and Am188ER microcontrollers provide INT4, an additional external
interrupt pin. This input behaves like INT3–INT0 on the 80C186/188 microcontroller with
the exception that INT4 is only intended for use as a nested-mode interrupt source.
This interrupt is assigned to interrupt type 10h. The Interrupt 4 Control Register (see Figure
8-6) controls the operation of the INT4 signal.
Figure 8-6
INT4 Control Register (I4CON, offset 40h)
7
0
15
Reserved
MSK PR1
LTM
PR2 PR0
The value of I4CON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT4 interrupt request as edge- or level-sensitive. A 1 in this bit configures
INT4 as an active High, level-sensitive interrupt. A 0 in this bit configures INT4 as a Low-
to-High, edge-triggered interrupt. In either case, INT4 must remain High until it is
acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT4 signal can cause an interrupt.
A 1 in this bit masks this interrupt source, preventing INT4 from causing an interrupt. A 0
in this bit enables INT4 interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority (PR)—This field determines the priority of INT4 relative to the other
interrupt signals, as shown in Table 8-3, “Priority Level,” on page 8-15.
Note: The INT4 pin is multiplexed with PIO 30. To enable the pin to function as an interrupt,
the PIO mode and PIO direction settings for the INT4 pin must be set to 0 for normal
operation. For more information, see Chapter 13, “Programmable I/O Pins.”
Interrupt Control Unit
8-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.4
Timer and DMA Interrupt Control Registers
(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,
Offset 36h)
(Master Mode)
The three timer interrupts are assigned to interrupt types 08h, 12h, and 13h. All three timer
interrupts are configured through TCUCON, offset 32h. The DMA0 interrupt is assigned to
interrupt type 0Ah. The DMA1 interrupt is assigned to interrupt type 0Bh. See Chapter 10,
“DMA Controller,” for information about using these pins for DMA requests.
Figure 8-7
Timer/DMA Interrupt Control Registers (TCUCON, DMA0CON, DMA1CON,
offsets 32h, 34h, and 36h)
7
0
15
0 0 0 0 0 0 0 0 0 0 0 0
MSK
PR2
PR1
PR0
The value of TCUCON, DMA0CON, and DMA1CON at reset is 000Fh.
Bits 15–4: Reserved—Set to 0.
Bit 3: Interrupt Mask (MSK)—This bit determines whether the corresponding signal can
generate an interrupt. A 1 masks this interrupt source. A 0 enables the corresponding
interrupt.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority Level (PR2–PR0)—Sets the priority level for its corresponding source.
Note: The DMA request pins DRQ0 and DRQ1 are multiplexed with PIO pins. To enable
the pins to function as DMA request, the PIO mode and PIO direction settings for the DRQ0
and DRQ1 pinsmustbesetto 0fornormaloperation. Formoreinformation, seeChapter 13,
“Programmable I/O Pins.”
8-18
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.5
Watchdog Timer Interrupt Control Register (WDCON, Offset 42h)
(Master Mode)
The watchdog timer is implemented by connecting the TMROUT1 output to an additional
internalinterrupttocreatethewatchdogtimerinterrupt.Thisinterruptisassignedtointerrupt
type 11h. The control register format is shown in Figure 8-8.
The systems programmer should program the timer (see section 9.2.2 on page 9-3) and
then program the interrupt control register.
Figure 8-8
Watchdog Timer Interrupt Control Register (WDCON, offset 42h)
7
0
15
Reserved
PR1
PR0
MSK
PR2
The value of WDCON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Reserved—Must be set to 0 to ensure proper operation of the Am186ER and
Am188ER microcontrollers.
Bit3:Mask(MSK)—Thisbitdetermineswhetherthewatchdogtimercancauseaninterrupt.
A 1 in this bit masks this interrupt source, preventing the watchdog timer from causing an
interrupt. A 0 in this bit enables watchdog timer interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority (PR)—This field determines the priority of the watchdog timer relative
Interrupt Control Unit
8-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.6
Serial Port Interrupt Control Register (SPICON, Offset 44h)
(Master Mode)
The Serial Port Interrupt Control (SPICON) Register controls the operation of the
asynchronous serial port interrupt source (SPI, bit 10 in the Interrupt Request Register).
This interrupt is assigned to interrupt type 14h. The control register format is shown in
Figure 8-9
Serial Port Interrupt Control Register (SPICON, offset 44h)
7
0
15
Reserved
1
MSK PR1
Res
PR2 PR0
The value of SPICON at reset is 001Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Reserved—Set to 1.
Bit 3: Mask (MSK)—This bit determines whether the serial port can cause an interrupt. A
1 in this bit masks this interrupt source, preventing the serial port from causing an interrupt.
A 0 in this bit enables serial port interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority (PR2–PR0)—This field determines the priority of the serial port relative to
the other interrupt signals. After a reset, the priority is 7. See Table 8-3, “Priority Level,” on
8-20
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.7
Interrupt Status Register (INTSTS, Offset 30h)
(Master Mode)
The Interrupt Status (INTSTS) Register indicates the interrupt request status of the three
timers.
Figure 8-10 Interrupt Status Register (INTSTS, offset 30h)
7
0
15
Reserved
DHLT
TMR2 TMR0
TMR1
Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This bit is automatically
set to 1 when nonmaskable interrupts occur and is reset when an IRET instruction is
executed. Time-critical software, such as interrupt handlers, can modify this bit directly to
inhibit DMA transfers. Because of the function of this registeras an interrupt requestregister
for the timers, the DHLT bit should not be modified by software when timer interrupts are
enabled.
Bits 14–3: Reserved
Bits 2–0: Timer Interrupt Request (TMR2–TMR0)—When set to 1, these bits indicate
that the corresponding timer has an interrupt request pending. (Note that the timer TMR
bit in the REQST Register is the logical OR of these timer interrupt requests.)
Interrupt Control Unit
8-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.8
Interrupt Request Register (REQST, Offset 2Eh)
(Master Mode)
The hardware interrupt sources have interrupt request bits inside the interrupt controller.
A read from this register yields the status of these bits. The Interrupt Request (REQST)
Register is a read-only register. The format of the Interrupt Request Register is shown in
For internal interrupts (watchdog, DMA, serial port, or timer interrupts) the corresponding
interrupt request bit (WD, D1, D0, TMR, or SPI) is set to 1 when the device requests an
interrupt.
Onceset, interruptrequestbitWD,D1,orD0isresetduringtheinternallygeneratedinterrupt
acknowledge. Bit TMR remains set as long as INTSTS Register bit TMR2, TMR1, or TMR0
is set. Bit SPI remains set until the serial port condition that caused the interrupt is cleared.
For INT4–INT0 external interrupts, the corresponding bit (I4–I0) reflects the current value
of the external signal. The device must hold this signal High until the interrupt is serviced.
Generally the interrupt service routine signals the external device to remove the interrupt
request.
Figure 8-11 Interrupt Request Register (REQST, offset 2Eh)
7
0
15
Reserved
SPI
WD
I4
I2
I0
D0 TMR
I3
I1
D1 Res
The REQST Register is undefined on reset.
Bits 15–11: Reserved
Bit 10: Serial Port Interrupt Request (SPI)—This bit indicates the interrupt state of the
serial port. If enabled, the SPI bit is the logical OR of all possible serial port interrupt sources
(THRE, RDR, BRKI, FER, PER, and OER status bits).
Bit 9: Watchdog Timer Interrupt Request (WD)—When this bit is set to 1, the Watchdog
Timer has an interrupt pending.
Bits 8–4: Interrupt Requests (I4–I0)—When set to 1, the corresponding INT pin has an
interrupt pending (i.e., when INT0 is pending, I0 is set). These bits reflect the status of the
external pin.
Bits 3–2: DMA Channel Interrupt Request (D1–D0)—When set to 1, the corresponding
DMA channel has an interrupt pending.
Bit 1: Reserved
Bit 0: Timer Interrupt Request (TMR)—This bit indicates the state of the timer interrupts.
This bit is the logical OR of the timer interrupt requests. When set to a 1, this bit indicates
that the timer control unit has an interrupt pending.
The Interrupt Status Register indicates the specific timer that is requesting an interrupt.
8-22
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.9
In-Service Register (INSERV, Offset 2Ch)
(Master Mode)
The bits in the In Service (INSERV) Register are set by the interrupt controller when the
interrupt is taken. Each bit in the register is cleared by writing the corresponding interrupt
type to the End-of-Interrupt (EOI) Register. See Table 8-1, “Am186ER and Am188ER
When an in-service bit is set, the microcontroller will not generate an interrupt request for
the associated source, preventing an interrupt from interrupting itself if interrupts are
enabled in the ISR. Special fully nested mode allows the INT1–INT0 requests to circumvent
this restriction for the INT0 and INT1 sources.
Figure 8-12 In-Service Register (INSERV, offset 2Ch)
7
0
15
Reserved
SPI
WD
I4
I2
I0
D0 TMR
I3
I1
D1 Res
The INSERV Register is set to 0000h on reset.
Bits 15–11: Reserved
Bit 10: Serial Port Interrupt In-Service (SPI)—This bit indicates the in-service state of
the asynchronous serial port.
Bit 9: Watchdog Timer Interrupt In-Service (WD)—This bit indicates the in-service state
of the Watchdog Timer.
Bits 8–4: Interrupt In-Service (I4–I0)—These bits indicate the in-service state of the
corresponding INT pin.
Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—These bits indicate the in-service
state of the corresponding DMA channel.
Bit 1: Reserved
Bit 0: Timer Interrupt In-Service (TMR)—This bit indicates the state of the in-service timer
interrupts. When set to a 1, this bit indicates that a timer interrupt request is in-service.
Interrupt Control Unit
8-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.10
Priority Mask Register (PRIMSK, Offset 2Ah)
(Master Mode)
The Priority Mask (PRIMSK) Register provides the value that determines the minimum
priority level at which maskable interrupts can generate an interrupt.
Figure 8-13 Priority Mask Register (PRIMSK, offset 2Ah)
7
0
15
0
0 0 0 0 0 0 0 0 0 0 0
0
PRM2
PRM1
PRM0
The value of PRIMSK at reset is 0007h.
Bits 15–3: Reserved—Set to 0.
Bits 2–0: Priority Field Mask (PRM2–PRM0)—This field determines the minimum priority
thatis required for a maskable interruptsource to generate an interrupt. Maskable interrupts
with programmable priority values that are numerically higher than this field are masked.
The possible values are zero (000b) to seven (111b).
A value of seven (111b) allows all interrupt sources that are not masked to generate
interrupts. A value of five (101b) allows only unmasked interrupt sources with a
programmable priority of zero to five (000b to 101b) to generate interrupts.
Table 8-4
Priority Field Mask (Master Mode)
Priority
PR2–PR0
0 0 0b
0 0 1b
0 1 0b
0 1 1b
1 0 0b
1 0 1b
1 1 0b
1 1 1b
(High) 0
1
2
3
4
5
6
(Low) 7
8-24
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.11
Interrupt Mask Register (IMASK, Offset 28h)
(Master Mode)
The Interrupt Mask (IMASK) Register is a read/write register. Programming a bit in the
IMASK Register has the effect of programming the MSK bit in the associated control
register. The format of the IMASK Register is shown in Figure 8-14.
Do not write to the Interrupt Mask Register while interrupts are enabled. To modify mask
bits while interrupts are enabled, use the individual interrupt control registers.
When a bit is set to 1 in this register, the corresponding interrupt source is masked off.
When the bit is set to 0, the interrupt source is enabled to generate an interrupt request.
Figure 8-14 Interrupt Mask Register (IMASK, offset 28h)
7
0
15
Reserved
SPI
WD
I4
I2
I0
D0 TMR
I3
I1
D1 Res
The IMASK Register is set to 07FDh on reset.
Bits 15–11: Reserved
Bit 10: Serial Port Interrupt Mask (SPI)— When set to 1, this bit indicates that the
asynchronous serial port interrupt is masked.
Bit 9: Virtual Watchdog Timer Interrupt Mask (WD)—When set to 1, this bit indicates
that the Watchdog Timer interrupt is masked.
Bits 8–4: Interrupt Mask (I4–I0)—When set to 1, an I4–I0 bit indicates that the
corresponding interrupt is masked.
Bits 3–2: DMA Channel Interrupt Masks (D1–D0)—When set to 1, a D1–D0 bit indicates
that the corresponding DMA channel interrupt is masked.
Bit 1: Reserved
Bit 0: Timer Interrupt Mask (TMR)—When set to 1, this bit indicates that interrupt requests
from the timer control unit are masked.
Interrupt Control Unit
8-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.12
Poll Status Register (POLLST, Offset 26h)
(Master Mode)
The Poll Status (POLLST) Register mirrors the current state of the Poll Register. The
POLLST Register can be read without affecting the current interrupt request. But when the
Poll Register is read, the current interrupt is acknowledged and the next interrupt takes its
place in the Poll Register.
Figure 8-15 Poll Status Register (POLLST, offset 26h)
7
0
15
Reserved
S4–S0
IREQ
Bit 15: Interrupt Request (IREQ)—Set to 1 if an interrupt is pending. When this bit is set
to 1, the S4–S0 field contains valid data.
Bits 14–5: Reserved—Set to 0.
Bits 4–0: Poll Status (S4–S0)—Indicates the interrupt type of the highest priority pending
interrupt.
8-26
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.13
Poll Register (POLL, Offset 24h)
(Master Mode)
When the Poll Register is read, the current interrupt is acknowledged and the next interrupt
takes its place in the Poll Register.
The Poll Status Register mirrors the current state of the Poll Register, but the Poll Status
Register can be read without affecting the current interrupt request.
Figure 8-16 Poll Register (POLL, offset 24h)
7
0
15
Reserved
S4–S0
IREQ
Bit 15: Interrupt Request (IREQ)—Set to 1 if an interrupt is pending. When this bit is set
to 1, the S4–S0 field contains valid data.
Bits 14–5: Reserved—Set to 0.
Bits 4–0: Poll Status (S4–S0)—Indicates the interrupt type of the highest priority pending
interrupt. Reading the Poll Register acknowledges the highest priority pending interrupt
and enables the next interrupt to advance into the register.
Although the IS bit is set, the interrupt service routine does not begin execution
automatically. The application software must execute the appropriate ISR.
Interrupt Control Unit
8-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3.14
End-of-Interrupt Register (EOI, Offset 22h)
(Master Mode)
The End-of-Interrupt (EOI) Register is a write-only register. The in-service flags in the In-
Before executing the IRET instruction that ends an interrupt service routine (ISR), the ISR
should write to the EOI Register to reset the IS bit for the interrupt.
The specific EOI reset is the most secure method to use for resetting IS bits. Figure 8-17
shows example code for a specific EOI reset. See Table 8-1, “Am186ER and Am188ER
Microcontroller Interrupt Types,” on page 8-3 for specific EOI values.
Figure 8-17 Example EOI Assembly Code
...
...
...
;ISR code
exit:
mov ax,int_type
mov dx, 0ff22h
out dx,ax
popa
;load the interrupt type in ax
;load default EOI location in dx
;write the interrupt type to EOI
iret
;return from interrupt
Figure 8-18 End-of-Interrupt Register (EOI, offset 22h)
7
0
15
Reserved
S4–S0
NSPEC
Bit15:Non-SpecificEOI(NSPEC)—TheNSPECbitdeterminesthetypeofEOIcommand.
When written as a 1, NSPEC indicates non-specific EOI. When written as a 0, NSPEC
indicates the specific EOI interrupt type is in S4–S0.
Bits 14–5: Reserved
Bits 4–0: Source Interrupt Type (S4–S0)—Specifies the type of the interrupt that is
currently being processed. See Table 8-1, “Am186ER and Am188ER Microcontroller
8-28
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4
SLAVE MODE OPERATION
When Slave mode is used, the microcontroller’s internal interrupt controller is used as a
slave controller to an external master interrupt controller. The internal interrupts are
monitored by the internal interrupt controller, while the external controller functions as the
system master interrupt controller.
On reset, the microcontroller is in Master mode. To activate Slave mode operation, bit 14
of the Relocation Register must be set (see Figure 4-2 on page 4-4).
Because of pin limitations caused by the need to interface to an external 82C59A master,
the internal interrupt controller does not accept external inputs. However, there are enough
interrupt controller inputs (internally) to dedicate one to each timer. In Slave mode, each
timer interrupt source has its own mask bit, IS bit, and control word.
The INT4, watchdog timer, and serial port interrupts are not available in Slave mode. In
Slave mode, each peripheral must be assigned a unique priority to ensure proper interrupt
controller operation. The programmer must assign correct priorities and initialize interrupt
control registers before enabling interrupts.
8.4.1
Slave Mode Interrupt Nesting
Slave mode operation allows nesting of interrupt requests. When an interrupt is
acknowledged, thepriority logicmasksoffallpriority levelsexceptthose with equalorhigher
priority.
8.4.2
Slave Mode Interrupt Controller Registers
be read and written, unless specified otherwise.
Table 8-5
Interrupt Controller Registers in Slave Mode
Register
Offset
3Ah
Mnemonic
Register Name
Affected Pins Comments
Interrupt Type XXXXX101
T2INTCON Timer 2 Interrupt Control
T1INTCON Timer 1 Interrupt Control
38h
TMRIN1
Interrupt Type XXXXX100
TMROUT1
36h
34h
32h
DMA1CON DMA 1 Interrupt Control
DMA0CON DMA 0 Interrupt Control
T0INTCON Timer 0 Interrupt Control
Interrupt Type XXXXX011
Interrupt Type XXXXX010
Interrupt Type XXXXX000
TMRIN0
TMROUT0
30h
2Eh
2Ch
2Ah
28h
22h
20h
INTSTS
REQST
INSERV
PRIMSK
IMASK
EOI
Interrupt Status
Interrupt Request
In-Service
Read Only
Read Only
Priority Mask
Interrupt Mask
Specific EOI
Write Only
INTVEC
Interrupt Vector
Interrupt Control Unit
8-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.3
Timer and DMA Interrupt Control Registers
(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset
3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h)
(Slave Mode)
In Slave mode, there are three separate registers for the three timers. In Master mode, all
three timers are masked and prioritized in one register, TCUCON.
In Slave mode, the two DMA control registers retain their functionality and addressing from
Master mode.
Figure 8-19 Timer and DMA Interrupt Control Registers
(T0INTCON, T1INTCON, T2INTCON, DMA0CON, DMA1CON,
offsets 32h, 38h, 3Ah, 34h, and 36h)
7
0
15
Reserved
MSK
PR2
PR1
PR0
These registers are set to 000Fh on reset.
Bits 15–4: Reserved—Set to 0.
Bit 3: Mask (MSK)—This bit determines whether the interrupt source can cause an
interrupt. A 1 in this bit masks the interrupt source, preventing the source from causing an
interrupt. A 0 in this bit enables interrupts from the source.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of the interrupt
source relative to the other interrupt signals, as shown in Table 8-3, “Priority Level,” on
8-30
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.4
Interrupt Status Register (INTSTS, Offset 30h)
(Slave Mode)
The Interrupt Status Register controls DMA activity when nonmaskable interrupts occur
and indicates the current interrupt status of the three timers.
Figure 8-20 Interrupt Status Register (INTSTS, offset 30h)
7
0
15
Reserved
DHLT
TMR1
TMR2
TMR0
The INTSTS Register is set to 0000h on reset.
Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. Automatically set to 1
when nonmaskable interrupts occur and reset when an IRET instruction is executed.
Bits 14–3: Reserved
Bits 2–0: Timer Interrupt Request (TMR2–TMR0)—When set to 1, indicates the
corresponding timer has an interrupt request pending.
Interrupt Control Unit
8-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.5
Interrupt Request Register (REQST, Offset 2Eh)
(Slave Mode)
The internal interrupt sources have interrupt request bits inside the interrupt controller. A
read from this register yields the status of these bits. The Interrupt Request Register is a
read-only register. The format of the Interrupt Request Register is shown in Figure 8-21.
For internal interrupts (D1, D0, TMR2, TMR1, and TMR0), the corresponding bit is set to
1 when the device requests an interrupt. The bit is reset during the internally generated
interrupt acknowledge.
Figure 8-21 Interrupt Request Register (REQST, offset 2Eh)
7
0
15
Reserved
TMR2 D1 Res
TMR1 D0
TMR0
The REQST Register is set to 0000h on reset.
Bits 15–6: Reserved
Bits 5–4: Timer 2/Timer 1 Interrupt Request (TMR2–TMR1)—When set to 1, these bits
indicate the state of any interrupt requests from the associated timer.
Bits 3–2: DMA Channel Interrupt Request (D1–D0)—When set to 1, D1–D0 indicate that
the corresponding DMA channel has an interrupt pending.
Bit 1: Reserved
Bit 0: Timer 0 Interrupt Request (TMR0)—When set to 1, this bit indicates the state of
an interrupt request from Timer 0.
8-32
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.6
In-Service Register (INSERV, Offset 2Ch)
(Slave Mode)
Register are set by the interrupt controller when the interrupt is taken. The in-service bits
are cleared by writing to the End-of-Interrupt (EOI) Register.
Figure 8-22 In-Service Register (INSERV, offset 2Ch)
7
0
15
Reserved
TMR2 D1 Res
TMR1 D0
TMR0
The INSERV Register is set to 0000h on reset.
Bits 15–6: Reserved
Bits 5–4: Timer 2/Timer 1 Interrupt In-Service (TMR2–TMR1)—When set to 1, these bits
indicate that the corresponding timer interrupt is currently being serviced.
Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—When set to 1, the corresponding
DMA channel is currently being serviced.
Bit 1: Reserved
Bit 0: Timer 0 Interrupt In-Service (TMR0)—When set to 1, this bit indicates Timer 0 is
currently being serviced.
Interrupt Control Unit
8-33
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.7
Priority Mask Register (PRIMSK, Offset 2Ah)
(Slave Mode)
provides the value that determines the minimum priority level at which maskable interrupts
can generate an interrupt.
Figure 8-23 Priority Mask Register (PRIMSK, offset 2Ah)
7
0
15
Reserved
PRM2
PRM1
PRM0
The value of the PRIMSK Register at reset is 0007h.
Bits 15–3: Reserved
Bits 2–0: Priority Field Mask (PRM2–PRM0)—This field determines the minimum priority
which is required for a maskable interrupt source to generate an interrupt.
A value of seven (111b) allows all interrupt sources that are not masked to generate
interrupts. A value of five (101b) allows only unmasked interrupt sources with a
programmable priority of zero to five (000b to 101b) to generate interrupts.
Table 8-6
Priority Field Mask (Slave Mode)
Priority
PR2–PR0
0 0 0b
0 0 1b
0 1 0b
0 1 1b
1 0 0b
1 0 1b
1 1 0b
1 1 1b
(High) 0
1
2
3
4
5
6
(Low) 7
8-34
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.8
Interrupt Mask Register (IMASK, Offset 28h)
(Slave Mode)
Register is a read/write register. Programming a bit in the Interrupt Mask Register has the
effect of programming the MSK bit in the associated control register.
Figure 8-24 Interrupt Mask Register (IMASK, offset 28h)
7
0
15
Reserved
TMR2 D1 Res
TMR1 D0
TMR0
The IMASK Register is set to 003Dh on reset.
Bits 15–6: Reserved
Bits 5–4: Timer 2/Timer 1 Interrupt Mask (TMR2–TMR1)—These bits indicate the state
of the mask bit of the Timer Interrupt Control Register and when set to a 1, indicate which
source has its interrupt requests masked.
Bits 3–2: DMA Channel Interrupt Mask (D1–D0)—These bits indicate the state of the
mask bits of the corresponding DMA control register.
Bit 1: Reserved
Bit 0: Timer 0 Interrupt Mask (TMR0)—This bit indicates the state of the mask bit of the
Timer Interrupt Control Register and when set to a 1, indicates Timer 0 has its interrupt
request masked.
Interrupt Control Unit
8-35
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.9
Specific End-of-Interrupt Register (EOI, Offset 22h)
(Slave Mode)
In Slave mode, a write to the EOI Register resets an in-service bit of a specific priority. The
user supplies a three-bit priority-level value that points to an in-service bit to be reset. The
command is executed by writing the correct value in the Specific EOI Register at offset 22h.
Figure 8-25 Specific End-of-Interrupt Register (EOI, offset 22h)
7
0
15
0 0 0 0 0 0 0 0 0 0
0
0 0 L2–L0
The EOI Register is undefined on reset.
Bits 15–3: Reserved—Write as 0.
Bits 2–0: Interrupt Type (L2–L0)—Encoded value indicating the priority of the IS (interrupt
service) bit to be reset. Writes to these bits cause an EOI to be issued for the interrupt type
in Slave mode. Write-only register.
8-36
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
8.4.10
Interrupt Vector Register (INTVEC, Offset 20h)
(Slave Mode)
Vector generation in Slave mode is exactly like that of an 8259A or 82C59A slave. The
interrupt controller generates an 8-bit interrupt type that the CPU shifts left two bits
(multiplies by four) to generate an offset into the interrupt vector table.
Figure 8-26 Interrupt Vector Register (INTVEC, offset 20h)
7
0
0
15
0
T4–T0
0 0 0 0 0 0
0
0 0
The INTVEC Register is undefined on reset.
Bits 15–8: Reserved—Read as 0.
Bits 7–3: Interrupt Type (T4–T0)—Sets the five most significant bits of the interrupt types
for the internal interrupt type. The interrupt controller itself provides the lower three bits of
Bits 2–0: Reserved—Read as 0.
Interrupt Control Unit
8-37
Download from Www.Somanuals.com. All Manuals Search And Download.
8-38
Interrupt Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
TIMER CONTROL UNIT
9
9.1
OVERVIEW
There are three 16-bit programmable timers in the Am186ER and Am188ER
microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external
pins (each one has an input and an output). These two timers can be used to count or time
external events, or they can be used to generate nonrepetitive or variable-duty-cycle
waveforms. Timer 1 can also be configured as a watchdog timer.
The watchdog timer provides a mechanism for detecting software crashes or hangs. The
TMROUT1 output is internally connected to the watchdog timer interrupt. Software
developers must first program the TIMER1 Mode/Control, Count, and Max Count registers,
and then program the Watchdog Timer Interrupt Control register (see Figure 8-8 on page
8-19). The TIMER1 Count register must be reloaded at intervals less than the TIMER1 max
count to assure the watchdog interrupt is not taken. If the code crashes or hangs, the
TIMER1 countdown can cause a watchdog interrupt.
Timer 2 is not connected to any external pins. It can be used for real-time coding and time-
delay applications. It can also be used as a prescale to timer 0 and timer 1 or as a DMA
request source.
9.2
PROGRAMMABLE REGISTERS
peripheral control block.
Table 9-1
Timer Control Unit Register Summary
Offsetfrom Register
PCB
56h
5Eh
66h
50h
58h
60h
52h
54h
5Ah
5Ch
62h
Mnemonic
Register Name
T0CON
Timer 0 Mode/Control
Timer 1 Mode/Control
Timer 2 Mode/Control
Timer 0 Count
T1CON
T2CON
T0CNT
T1CNT
Timer 1 Count
T2CNT
Timer 2 Count
T0CMPA
T0CMPB
T1CMPA
T0CMPB
T2CMPA
Timer 0 Maxcount Compare A
Timer 0 Maxcount Compare B
Timer 1 Maxcount Compare A
Timer 1 Maxcount Compare B
Timer 2 Maxcount Compare A
The timer-count registers contain the current value of a timer. The timer-count registers
can be read or written at any time, regardless of whether the corresponding timer is running.
The microcontroller increments the value of a timer-count register each time a timer event
occurs.
Timer Control Unit
9-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Each timer also has a corresponding maximum-count register that defines the maximum
value for the timer. When the timer reaches the maximum value, it resets to 0 during the
same clock cycle. (The value in the timer-count register never equals the maximum-count
register.) In addition, timers 0 and 1 have a secondary maximum-count register. Using both
the primary and secondary maximum-count registers lets the timer alternate between two
maximum values.
If the timer is programmed to use only the primary maximum-count register, the timer output
pin switches Low for one clock cycle, the clock cycle after the maximum value is reached.
Ifthe timerisprogrammed to use bothofitsmaximum-countregisters, the outputpincreates
a waveform by indicating which maximum-count register is currently in control. The duty
cycle and frequency of the waveform depend on the values in the alternating maximum-
count registers. For example, a 50% duty cycle waveform can be generated at 1/8 the
frequency of the system clock using a 1h value for maxcount A and maxcount B.
9.2.1
Timer Operating Frequency
Each timer is serviced on every fourth clock cycle. Therefore, a timer can operate at a
maximum speed of one-quarter of the internal clock frequency. A timer can be clocked
externally at the same maximum frequency of one-fourth of the internal clock frequency.
However, because of internal synchronization and pipelining of the timer circuitry, the timer
output takes up to six clock cycles to respond to the clock or gate input.
The timers are run by the processor’s internal clock. If power-save mode is in effect, the
timers operate at the reduced power-save clock rate.
9-2
Timer Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
9.2.2
Timer 0 and Timer 1 Mode and Control Registers
(T0CON, Offset 56h, T1CON, Offset 5Eh)
These registers control the functionality of timer 0 and timer 1. See Figure 9-1.
Figure 9-1
Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON,
offsets 56h and 5Eh)
7
0
15
0 0 0 0 0 0
MC
RTG
P
INH
INT
RIU
ALT
CONT
EN
EXT
The value of T0CON and T1CON at reset is 0000h.
Bit 15: Enable Bit (EN)—When set to 1, the timer is enabled. When set to 0, the timer is
inhibited from counting. This bit can only be written with the INH bit set at the same time.
Bit 14: Inhibit Bit (INH)—Allows selective updating of enable (EN) bit. When set to 1 during
a write, EN can also be modified. When set to 0 during a write, writes to EN are ignored.
This bit is not stored and is always read as 0.
Bit 13: Interrupt Bit (INT)—When set to 1, an interrupt request is generated when the
count register equals a maximum count. If the timer is configured in dual maxcount mode,
an interrupt is generated each time the count reaches maxcount A or maxcount B. When
INT is set to 0, the timer will not issue interrupt requests. If the enable bit is cleared after
an interrupt request has been generated but before the pending interrupt is serviced, the
interrupt request will still be present.
Bit 12: Register in Use Bit (RIU)—When the Maxcount Compare A register is being used
for comparison to the timer count value, this bit is set to 0. When the Maxcount Compare
B register is being used, this bit is set to 1.
Bits 11–6: Reserved—Set to 0.
Bit5:MaximumCountBit(MC)—TheMCbitissetto1whenthetimerreaches amaximum
count. In dual maxcount mode, the bit is set each time either the Maxcount Compare A or
B register is reached. This bit is set regardless of the timer interrupt-enable bit. The MC bit
can be used to monitor timer status through software polling instead of through interrupts.
Bit 4: Retrigger Bit (RTG)—Determines the control function provided by the timer input
pin. When set to 1, a 0 to 1 edge transition on TMRIN0 or TMRIN1 resets the count. When
set to 0, a High input enables counting and a Low input holds the timer value. This bit is
ignored when external clocking (EXT=1) is selected.
Bit 3: Prescaler Bit (P)—When set to 1, the timer is prescaled by timer 2. When set to 0,
the timer counts up every fourth CLKOUT period. This bit is ignored when external clocking
is enabled (EXT=1).
Timer Control Unit
9-3
Download from Www.Somanuals.com. All Manuals Search And Download.
Bit 2: External Clock Bit (EXT)—When set to 1, an external clock is used. When set to
0, the internal clock is used. When the internal clock is used, the timer input pin is available
for use as a programmable I/O pin.
Bit1:AlternateCompareBit(ALT)—Whensetto1,thetimercountstomaxcountcompare
A, then resets the count register to 0. Then the timer counts to maxcount compare B, resets
the count register to zero, and starts over with maxcount compare A.
If ALT is clear, the timer counts to maxcount compare A and then resets the count register
to zero and starts counting again against maxcount compare A. In this case, maxcount
compare B is not used.
Bit 0: Continuous Mode Bit (CONT)—When set to 1, CONT causes the associated timer
to run in the normal continuous mode.
When CONT is set to 0, EN is cleared after each timer count sequence and the timer clears
and then halts on reaching the maximum count. If CONT=0 and ALT=1, the timer counts
to the Maxcount Compare A register value and resets, then it counts to the B register value
and resets and halts.
Note: The TMRIN0, TMRIN1, TMROUT0, AND TMROUT1 pins are multiplexed with
programmable I/O pins. To enable the timer pin functionality, the PIO mode and PIO
direction settings for these pins must be set to 0 for normal operation. For more information,
see Chapter 13, “Programmable I/O Pins.”
9-4
Timer Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
9.2.3
Timer 2 Mode and Control Register
(T2CON, Offset 66h)
Figure 9-2
Timer 2 Mode and Control Register (T2CON, offset 66h)
7
0
15
0 0 0 0 0 0 0
0 0 0 0
CONT
INH
INT
MC
EN
The value of T2CON at reset is 0000h.
Bit 15: Enable Bit (EN)—When EN is set to 1, the timer is enabled. When set to 0, the
timer is inhibited from counting. This bit can only be written with the INH bit set at the same
time.
Bit 14: Inhibit Bit (INH)—Allows selective updating of enable (EN) bit. When INH is set to
1 during a write, EN can be modified on the same write. When INH is set to 0 during a write,
writes to EN are ignored. This bit is not stored and is always read as 0.
Bit 13: Interrupt Bit (INT)—When INT is set to 1, an interrupt request is generated when
the count register equals a maximum count. When INT is set to 0, the timer will not issue
interrupt requests. If the EN enable bit is cleared after an interrupt request has been
generated, but before the pending interrupt is serviced, the interrupt request remains active.
Bits 12–6: Reserved—Set to 0.
Bit 5: Maximum Count Bit (MC)—The MC bit is set to 1 when the timer reaches its
maximum count. This bit is set regardless of the timer interrupt-enable bit. The MC bit can
be used to monitor timer status through software polling instead of through interrupts.
Bits 4–1: Reserved—Set to 0.
Bit 0: Continuous Mode Bit (CONT)—When CONT is set to 1, it causes the associated
timer to run continuously. When set to 0, EN is cleared after each timer count sequence
and the timer halts on reaching the maximum count.
Timer Control Unit
9-5
Download from Www.Somanuals.com. All Manuals Search And Download.
9.2.4
Timer Count Registers
(T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h)
These registers can be incremented by one every four internal processor clocks. Timer 0
and timer1canalso beconfigured to incrementbasedontheTMRIN0andTMRIN1 external
signals, or they can be prescaled by timer 2. See Figure 9-3.
The count registers are compared to maximum count registers and various actions are
triggered based on reaching a maximum count.
Figure 9-3
Timer Count Registers (T0CNT, T1CNT, T2CNT, offsets 50h, 58h, and 60h)
7
0
15
TC15–TC0
The value of these registers at reset is undefined.
Bits 15–0: Timer Count Value (TC15–TC0)—This register contains the current count of
the associated timer. The count is incremented every fourth processor clock in internal
clocked mode, or each time the timer 2 maxcount is reached if prescaled by timer 2. Timer
0 and timer 1 can be configured for external clocking based on the TMRIN0 and TMRIN1
signals.
9-6
Timer Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
9.2.5
Timer Maxcount Compare Registers
(T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah,
T1CMPB, Offset 5Ch, T2CMPA, Offset 62h)
These registers serve as comparators for their associated count registers. Timer 0 and
Timer 0 and timer 1 can be configured to count and compare to register A and then count
and compare to register B. Using this method, the TMROUT0 or TMROUT1 signals can
be used to generate waveforms of various duty cycles.
Timer 2 has one compare register, T2CMPA.
Ifamaximum countcompare registerissetto0000h, the timerassociated withthatcompare
register will count from 0000h to FFFFh before requesting an interrupt. With a 40-MHz
clock, a timer configured this way interrupts every 6.5536 ms.
Figure 9-4
Timer Maxcount Compare Registers
(T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA,
offsets 52h, 54h, 5Ah, 5Ch, and 62h)
7
0
15
TC15–TC0
The value of these registers at reset is undefined.
Bits 15–0: Timer Compare Value (TC15–TC0)—This register contains the maximum
value a timer will count to before resetting its count register to 0.
Timer Control Unit
9-7
Download from Www.Somanuals.com. All Manuals Search And Download.
9-8
Timer Control Unit
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
DMA CONTROLLER
10
10.1
OVERVIEW
Direct memory access (DMA) permits transfer of data between memory and peripherals
without CPU involvement. The DMA unit in the Am186ER and Am188ER microcontrollers
provides two high-speed DMA channels. Data transfers can occur between memory and I/O
spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-to-I/O).
Two bus cycles (a minimum of eight clocks) are necessary for each data transfer.
Either bytes or words can be transferred to or from even or odd addresses on the Am186ER.
The Am186ER does not support word DMA transfers to or from memory configured for 8-bit
accesses. The Am188ER microcontroller does not support word transfers.
Each channel accepts a DMA request from one of two sources: the channel request pin
(DRQ1–DRQ0) or Timer 2. The two DMA channels can be programmed with different
priorities to resolve simultaneous DMA requests, and transfers on one channelcan interrupt
the other channel.
10.2
DMA OPERATION
control block define the operation of each channel. The DMA registers consist of a 20-bit
source address (2 registers), a 20-bit destination address (2 registers), a 16-bit transfer
count register, and a 16-bit control register.
Table 10-1 DMA Controller Register Summary
Offsetfrom Register
PCB
CAh
DAh
C8h
D8h
C6h
D6h
C4h
D4h
C2h
D2h
C0h
D0h
Mnemonic
D0CON
D1CON
D0TC
Register Name
DMA 0 Control
DMA 1 Control
DMA 0 Transfer Count
D1TC
DMA 1 Transfer Count
D0DSTH
D1DSTH
D0DSTL
D1DSTL
D0SRCH
D1SRCH
D0SRCL
D1SRCL
DMA 0 Destination Address High
DMA 1 Destination Address High
DMA 0 Destination Address Low
DMA 1 Destination Address Low
DMA 0 Source Address High
DMA 1 Source Address High
DMA 0 Source Address Low
DMA 1 Source Address Low
The DMA transfer count register (DTC) specifies the number of DMA transfers to be
performed. Up to 64 Kbytes or 64 Kwords can be transferred with automatic termination.
can be modified or altered during any DMA activity. Any changes made to these registers
are reflected immediately in DMA operation.
DMA Controller
10-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 10-1 DMA Unit Block Diagram
Adder Control
Logic
20-bit Adder/Subtractor
20
Timer Request
DRQ1
Request
Selection
Logic
DRQ0
Transfer Counter Ch. 1
Destination Address Ch. 1
DMA
Control
Logic
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
Interrupt
Request
Channel Control Register 1
Channel Control Register 0
20
16
Internal Address/Data Bus
10.3
PROGRAMMABLE DMA REGISTERS
The sections on the following pages describe the control registers that are used to configure
and operate the two DMA channels.
10-2
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.1
DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh)
channels. These registers specify the following options:
n Whether the destination address is memory or I/O space
n Whether the destination address is incremented, decremented, or maintained constant
after each transfer
n Whether the source address is memory or I/O space
n Whether the source address is incremented, decremented, or maintained constant after
each transfer
n If DMA activity ceases after a programmed number of DMA cycles
n If an interrupt is generated after the last transfer
n The mode of synchronization
n The relative priority of one DMA channel with respect to the other DMA channel
n Whether timer 2 DMA requests are enabled or disabled
n Whether bytes or words are transferred
The DMA channel control registers can be changed while the channel is operating. Any
changes made during DMA operations affect the current DMA transfer.
Figure 10-2 DMA Control Registers (D0CON, D1CON, offsets CAh and DAh)
7
0
15
DINC
DDEC
DM/IO
SINC
SDEC TC
INT
P
Res
B/W
ST
SYN TDRQ
SM/IO
CHG
The value of D0CON and D1CON at reset is FFF9h.
Bit 15: Destination Address Space Select (DM/IO)—Selects memory or I/O space for
the destination address. When DM/IO is set to 1, the destination address is in memory
space. When set to 0, the destination address is in I/O space.
Bit 14: Destination Decrement (DDEC)—When DDEC is set to 1, the destination address
is automatically decremented after each transfer. The address decrements by 1 or 2,
depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment
and decrement bits are set to the same value (00b or 11b).
Bit 13: Destination Increment (DINC)—When DINC is set to 1, the destination address
is automatically incremented after each transfer. The address increments by 1 or 2,
depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment
and decrement bits are set to the same value (00b or 11b).
Bit 12: Source Address Space Select (SM/IO)—When SM/IO is set to 1, the source
address is in memory space. When set to 0, the source address is in I/O space.
DMA Controller
10-3
Download from Www.Somanuals.com. All Manuals Search And Download.
Bit 11: Source Decrement (SDEC)—When SDEC is set to 1, the source address is
automatically decremented after each transfer. The address decrements by 1 or 2
depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment
and decrement bits are set to the same value (00b or 11b).
Bit 10: Source Increment (SINC)—When SINC is set to 1, the source address is
automatically incremented after each transfer. The address increments by 1 or 2 depending
on the byte/word bit (B/W, bit 0). The address remains constant if the increment and
decrement bits are set to the same value (00b or 11b).
Bit 9: Terminal Count (TC)—The DMA decrements the transfer count for each DMA
transfer. When TC is set to 1, source or destination synchronized DMA transfers terminate
when the count reaches 0. When TC is set to 0, source or destination synchronized DMA
transfers do not terminate when the count reaches 0. Unsynchronized DMA transfers
always terminate when the count reaches 0, regardless of the setting of this bit.
Bit 8: Interrupt (INT)—When INT is set to 1, the DMA channel generates an interrupt
request on completion of the transfer count. The TC bit must also be set to generate an
interrupt.
Bits 7–6: Synchronization Type (SYN1–SYN0)—The SYN1–SYN0 bits select channel
Table 10-2 Synchronization Type
SYN1 SYN0
Sync Type
0
0
Unsynchronized
Source Synch
Destination Synch
Reserved
0
1
1
1
0
1
Bit 5: Relative Priority (P)—When P is set to 1, it selects high priority for this channel
relative to the other channel during simultaneous transfers.
Bit 4: Timer Enable/Disable Request (TDRQ)—When TDRQ is set to 1, it enables DMA
requests from timer 2. When set to 0, TDRQ disables DMA requests from timer 2.
Bit 3: Reserved
Bit 2: Change Start Bit (CHG)—This bit must be set to 1 during a write to allow modification
of the ST bit. When CHG is set to 0 during a write, ST is not altered when writing the control
word.
Bit 1: Start/Stop DMA Channel (ST)—The DMA channel is started when the start bit is
set to 1. This bit can be modified only when the CHG bit is set to a 1 during the same
register write.
Bit 0: Byte/Word Select (B/W)—On the Am186ER microcontroller, when B/W is set to 1,
wordtransfersareselected.WhenB/Wissetto0,bytetransfersareselected.TheAm186ER
does not support word DMA transfers to or from memory configured for 8-bit accesses. Word
transfers are not supported on the Am188ER microcontroller.
Note: The DMA request pins DRQ0 and DRQ1 are multiplexed with programmable I/O
pins. To enable the pins to function as DMA requests, the PIO mode and PIO direction
settings for the DRQ0 and DRQ1 pins must be set to 0 for normal operation. For more
information, see Chapter 13, “Programmable I/O Pins.”
10-4
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.2
DMA Transfer Count Registers (D0TC, Offset C8h, D1TC,
Offset D8h)
Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register
is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA
Control register. However, if the TC bit in the DMA control word is set or if unsynchronized
transfers are programmed, DMA activity terminates when the Transfer Count register
reaches 0.
Figure 10-3 DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h)
7
0
15
TC15–TC0
The value of D0TC and D1TC at reset is undefined.
Bits 15–0: DMA Transfer Count (TC15–TC0)—Contains the transfer count for a DMA
channel. Value is decremented by 1 after each transfer.
DMA Controller
10-5
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.3
DMA Destination Address High Register
(High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h)
Each DMA channelmaintains a20-bitdestinationanda 20-bitsourceregister. Eachregister
takes up two full 16-bit registers (the high register and the low register) in the peripheral
control block. For each DMA channel to be used, all four registers must be initialized. These
registers can be individually incremented or decremented after each transfer. If word
transfers are performed, the address is incremented or decremented by 2 after each
transfer. If byte transfers are performed, the address is incremented or decremented by 1.
Each register can point into either memory or I/O space. The user must program the upper
four bits to 0000b in order to address the normal 64K I/O space. Because the DMA channels
can perform transfers to or from odd addresses, there is no restriction on values for the
destination and source address registers. Higher transfer rates can be achieved on the
Am186ER microcontroller if all word transfers are performed to or from even addresses so
that accesses occur in single, 16-bit bus cycles.
Figure 10-4 DMA Destination Address High Register (D0DSTH, D1DSTH, offsets C6h and D6h)
7
0
15
Reserved
DDA19–DDA16
The value of D0DSTH and D1DSTH at reset is undefined.
Bits 15–4: Reserved
Bits 3–0: DMA Destination Address High (DDA19–DDA16)—These bits are driven onto
A19–A16 during the write phase of a DMA transfer.
10-6
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.4
DMA Destination Address Low Register
(Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h)
Figure 10-5 shows the DMA Destination Address Low register. The sixteen bits of this
register are combined with the four bits of the DMA Destination Address High register (see
Figure 10-4) to produce a 20-bit destination address.
Figure 10-5 DMA Destination Address Low Register (D0DSTL, D1DSTL, offsets C4h and D4h)
7
0
15
DDA15–DDA0
The value of D0DSTL and D1DSTL at reset is undefined.
Bits 15–0: DMA Destination Address Low (DDA15–DDA0)—These bits are driven onto
A15–A0 during the write phase of a DMA transfer.
DMA Controller
10-7
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.5
DMA Source Address High Register
(High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h)
Each DMA channelmaintains a20-bitdestinationanda 20-bitsourceregister. Eachregister
takes up two full 16-bit registers (the high register and the low register) in the peripheral
control block. For each DMA channel to be used, all four registers must be initialized. These
registers can be individually incremented or decremented after each transfer. If word
transfers are performed, the address is incremented or decremented by 2 after each
transfer. If byte transfers are performed, the address is incremented or decremented by 1.
Each register can point into either memory or I/O space. The user must program the upper
four bits to 0000b in order to address the normal 64K I/O space. Because the DMA channels
can perform transfers to or from odd addresses, there is no restriction on values for the
destination and source address registers. Higher transfer rates can be achieved on the
Am186ER microcontroller if all word transfers are performed to or from even addresses so
that accesses occur in single, 16-bit bus cycles.
Figure 10-6 DMA Source Address High Register (D0SRCH, D1SRCH, offsets C2h and D2h)
7
0
15
Reserved
DSA19–DSA16
The value of D0SRCH and D1SRCH at reset is undefined.
Bits 15–4: Reserved
Bits 3–0: DMA Source Address High (DSA19–DSA16)—These bits are driven onto
A19–A16 during the read phase of a DMA transfer.
10-8
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
10.3.6
DMA Source Address Low Register
(Low Order Bits) (D0SRCL, Offset C0h, D1SRCL, Offset D0h)
Figure 10-7 shows the DMA Source Address Low register. The sixteen bits of this register
are combined with the four bits of the DMA Source Address High register (see Figure 10-
6) to produce a 20-bit source address.
Figure 10-7 DMA Source Address Low Register (D0SRCL, D1SRCL, offsets C0h and D0h)
7
0
15
DSA15–DSA0
The value of D0SRCL and D1SRCL at reset is undefined.
Bits 15–0: DMA Source Address Low (DSA15–DSA0)—These bits are driven onto
A15–A0 during the read phase of a DMA transfer.
DMA Controller
10-9
Download from Www.Somanuals.com. All Manuals Search And Download.
10.4
DMA REQUESTS
Data transfers can be either source or destination synchronized—either the source of the
data or the destination of the data can request the data transfer. DMA transfers can also
be unsynchronized (i.e., the transfer takes place continually until the correct number of
transfers has occurred).
During source synchronized or unsynchronized transfers, the DMA channel can begin a
transfer immediately after the end of the previous DMA transfer, and a complete transfer
can occur every two bus cycles or eight clock cycles (assuming no wait states).
When destination synchronization isperformed, data isnotfetchedfrom the sourceaddress
until the destination device signals that it is ready to receive it. When destination
synchronized transfers are requested, the DMA controller relinquishes control of the bus
after every transfer. If no other bus activity is initiated, another DMA cycle begins after two
processor clocks. This allows the destination device time to remove its request if another
transfer is not desired.
When the DMA controller relinquishes the bus during destination synchronized transfers,
the CPU can initiate a bus cycle. As a result, a complete bus cycle is often inserted between
based on the different synchronization strategies.
Table 10-3 Maximum DMA Transfer Rates
Maximum DMA
Transfer Rate (Mbyte/s)
Synchronization Type
40 MHz
33 MHz 25 MHz 20 MHz
Unsynchronized
Source Synch
10
10
8.25
8.25
5.5
6.25
6.25
4.16
5
5
Destination Synchronized
(CPU needs bus)
6.6
3.3
Destination Synchronized
(CPU does not need bus)
8
6.6
5
4
10-10
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
10.4.1
Synchronization Timing
DRQ1 or DRQ0 must be deasserted before the end of the DMA transfer to prevent another
DMA cycle from occurring. The timing for the required deassertion depends on whether
the transfer is source-synchronized or destination-synchronized.
10.4.1.1
Source Synchronization Timing
Figure 10-8 shows a typical source-synchronized DMA transfer. The DRQ signal must be
deasserted at least four clocks before the end of the transfer (at T1 of the deposit phase).
If more transfers are not required, a source-synchronized transfer allows the source device
at least three clock cycles from the time it is acknowledged to deassert its DRQ line.
Figure 10-8 Source-Synchronized DMA Transfers
Fetch Cycle
Fetch Cycle
T1
T2
T3
T4
T1
T2
T3
T4
CLKOUT
DRQ (First case)
1
DRQ (Second case)
2
Notes:
1. This source-synchronized transfer is not followed immediately by another DMA transfer.
2. This source-synchronized transfer is immediately followed by another DMA transfer because
DRQ is not deasserted soon enough.
10.4.1.2
Destination Synchronization Timing
Figure 10-9 shows a typical destination-synchronized DMA transfer. A destination-
synchronized transfer differs from a source-synchronized transfer in that two idle states are
added to the end of the deposit cycle. The two idle states allow the destination device to
deassert its DRQ signal four clocks before the end of the cycle. Without the two idle states,
the destination device would not have time to deassert its DRQ signal.
Because of the two extra idle states, a destination-synchronized DMA channel allows other
bus masters to take the bus during the idle states. The CPU, the refresh control unit, and
another DMA channel can all access the bus during the idle states.
DMA Controller
10-11
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 10-9 Destination Synchronized DMA Transfers
Fetch Cycle
Deposit Cycle
T1
T2
T3
T4
T1
T2
T3
T4
TI
TI
CLKOUT
DRQ
(First case)
1
DRQ
2
(Second case)
Notes:
1. This destination-synchronized transfer is not followed immediately by another DMA transfer.
2. This destination-synchronized transfer is immediately followed by another DMA transfer because
DRQ is not deasserted soon enough.
10.4.2
10.4.3
DMA Acknowledge
No explicit DMA acknowledge signal is provided. Because both source and destination
registers are maintained, a read from a requesting source or a write to a requesting
destination should be used as the DMA acknowledge signal. Because the chip-select lines
can be programmed to be active for a given block of memory or I/O space, and the DMA
source and destination address registers can be programmed to point to the same given
block, a chip-select line could be used to indicate a DMA acknowledge.
DMA Priority
The DMA channels can be programmed so that one channel is always given priority over
the other, or they can be programmed to alternate cycles when both have DMA requests
CPU cycles except between internally locked memory accesses or word accesses to odd
memory locations. However, an external bus hold takes priority over an internal DMA cycle.
Because an interrupt requestcannotsuspend a DMA operationand the CPU cannot access
memory during a DMA cycle, interrupt latency time suffers during sequences of continuous
DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows
the CPU to respond quickly to the NMI request.
10.4.4
DMA Programming
DMA cycles occur wheneverthe STbitofthe control register is set. If synchronized transfers
are programmed, a DRQ must also be generated. Therefore, the source and destination
transfer address registers and the transfer count register (if used) must be programmed
before the ST bit is set.
10-12
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
Each DMA register can be modified while the channel is operating. If the CHG bit is set to
0 when the control register is written, the ST bit of the control register will not be modified
by the write. If multiple channel registers are modified, an internally LOCKed string transfer
should be used to prevent a DMA transfer from occurring between updates to the channel
registers.
10.4.5
DMA Channels on Reset
On reset, the state of the DMA channels is as follows:
n The ST bit for each channel is reset.
n Any transfer in progress is aborted.
n The values of the transfer count registers, source address registers, and destination
address registers are undefined.
DMA Controller
10-13
Download from Www.Somanuals.com. All Manuals Search And Download.
10-14
DMA Controller
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
ASYNCHRONOUS SERIAL PORT
11
11.1
OVERVIEW
The Am186ER and Am188ER microcontrollers provide an asynchronous serial port. The
asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data
transfer. The asynchronous serial port supports the following features:
n Full-duplex operation
n 7-bit or 8-bit data transfers
n Odd parity, even parity, or no parity
n 1 or 2 stop bits
If additional RS-232 signals are required, they can be created with available PIO pins (see
section 13.1 on page 13-1). The asynchronous serial port transmit and receive sections
are double-buffered. Break character recognition, framing, parity, and overrun error
detection are provided. Exception interrupt generation is programmed by the user.
The transmit/receive clock is based on the internal processor clock internally divided down
to the serial port operating frequency. If power-save mode is in effect, the divide factor must
be reprogrammed. The serial port permits 7-bit and 8-bit data transfers. DMA transfers
through the serial port are not supported.
The serial port generates one interrupt for all serial port events (transmit complete, data
received, or error). The Serial Port Status register contains the reason for the serial port
interrupt. The interrupt type assigned to the serial port is 14h.
The serial port can be used in power-save mode, but the transfer rate must be adjusted to
correctly reflect the new internal operating frequency and the serial port must not receive
any information until the frequency is changed.
11.2
PROGRAMMABLE REGISTERS
The asynchronous serial port is programmed through the use of five, 16-bit peripheral
registers. See Table 11-1.
Table 11-1 Asynchronous Serial Port Register Summary
Offsetfrom Register
PCB
80h
82h
84h
86h
88h
Mnemonic
Register Name
SPCT
Serial Port Control
SPSTS
SPTD
Serial Port Status
Serial Port Transmit Data
Serial Port Receive Data
Serial Port Baud Rate Divisor
SPRD
SPBAUD
Asynchronous Serial Port
11-1
Download from Www.Somanuals.com. All Manuals Search And Download.
11.2.1
Serial Port Control Register (SPCT, Offset 80h)
The Serial Port Control register controls both the transmit and receive sections of the serial
Figure 11-1 Serial Port Control Register (SPCT, offset 80h)
7
0
15
Reserved
RMODE
TXIE
RXIE
PMODE
RSIE
TMODE
STP
WLGN
LOOP
BRK
BRKVAL
The value of SPCT at reset is 0000h.
Bits 15–12: Reserved—Set to 0.
Bit 11: Transmit Holding Register Empty Interrupt Enable (TXIE)—This bit enables the
serial port to generate an interrupt for the transmit holding register empty condition,
indicating that the serial port is ready to accept a new character for transmission. If this bit
is 1 and the Serial Port Transmit Holding register does not contain valid data, the serial
port generates an interrupt request. The value of TXIE after power-on reset is 0.
Bit 10: Receive Data Ready Interrupt Enable (RXIE)—This bit enables the serial port to
generate an interrupt for the receive data ready condition. If this bit is 1 and the Serial Port
Receive Buffer register contains data that has been received on the serial port, the serial
port generates an interrupt request. The value of RXIE after power-on reset is 0.
Bit 9: Loopback (LOOP)—Setting this bit to 1 places the serial port in the loopback mode.
In this mode, the TXD output is set High and the transmit shift register is connected to the
receive shift register. Data transmitted by the transmit section is immediately received by
the receive section. The loopback mode is provided for testing the serial port. The value of
LOOP after power-on reset is 0.
Bit 8: Send Break (BRK)—Setting this bit to 1 causes the serial port to send a continuous
level on the TXD output. A break is a continuous Low on the TXD output for a duration of
more than one frame transmission time. The level driven on the TXD output is determined
by the BRKVAL bit.
To use the transmitter to time the frame, set the BRK bit when the transmitter is empty
(indicated by the TEMT bit of the Serial Port Status register), write the serial port transmit
holding register, then wait until the TEMT bit is again set before resetting the BRK bit.
Because the TXD output is held constant while BRK is set, the data written to the transmit
holding register will not appear on the pin. The value of BRK after power-on reset is 0.
Bit 7: Break Value (BRKVAL)—This bit determines the output value transmitted on the
TXD pin during a send break operation. If BRKVAL is 1, a continuous High level is driven
on the TXD output. If BRKVAL is 0, a continuous Low level is driven on the TXD output.
Only a continuous Low value (BRKVAL=0) will result in a break being detected by the
receiver. The value of BRKVAL after power-on reset is 0.
11-2
Asynchronous Serial Port
Download from Www.Somanuals.com. All Manuals Search And Download.
Bits 6–5: Parity Mode (PMODE)—This field specifies how parity generation and checking
Table 11-2 Parity Mode Bit Settings
Parity
PMODE
0 X
None (No parity bit in frame)
Odd (Odd number of 1s in frame)
Even (Even number of 1s in frame)
1 0
1 1
If parity checking and generation is selected, a parity bit is received or sent in addition to
the specified number of data bits.
The value of PMODE after power-on reset is 00b.
Bit 4: Word Length (WLGN)—This bit determines the number of bits transmitted or
received in a frame. If WLGN is 0, the serial port sends and receives 7 bits of data per
frame. If WLGN is 1, the serial port sends and receives 8 bits of data per frame. The value
of WLGN after power-on reset is 0.
Bit 3: Stop Bits (STP)—A 0 in the STP bit specifies that one stop bit is used to signify the
end of a frame. A 1 in this bit specifies that two stop bits are used to signify the end of a
frame. The value of STP after power-on reset is 0.
Bit 2: Transmit Mode (TMODE)—The TMODE bit enables data transmission and controls
the operational mode of the serial port for the transmission of data. If TMODE is 0, the
transmit section and transmit interrupts of the serial port are disabled. If TMODE is 1, the
transmit section of the serial port is enabled. The value of TMODE after power-on reset is 0.
Bit1:ReceiveStatusInterruptEnable(RSIE)—Thisbitenablestheserialporttogenerate
an interrupt because of an exception during reception. If this bit is 1 and the serial port
receives a break, or experiences a framing error, parity error, or overrun error, the serial
port generates a serial port interrupt. The value of RSIE after power-on reset is 0.
Bit 0: Receive Mode (RMODE)—This field enables data reception and controls the
operational mode of the serial port for the reception of data. If RMODE is 0, the receive
section and receive interrupts of the serial port are disabled. If RMODE is 1, the receive
section of the serial port is enabled. The value of RMODE after power-on reset is 0.
Note: The asynchronous serial interface pins TXD and RXD are multiplexed with
programmable I/O pins. To enable the pins to function as asynchronous serial interface,
the PIO mode and PIO direction settings for the TXD and RXD pins must be set to 0 for
normal operation. For more information, see Chapter 13, “Programmable I/O Pins.”
Asynchronous Serial Port
11-3
Download from Www.Somanuals.com. All Manuals Search And Download.
11.2.2
Serial Port Status Register (SPSTS, Offset 82h)
The Serial Port Status register indicates the status of the transmit and receive sections of
the serial port. The format of the Serial Port Status register is shown in Figure 11-2.
Figure 11-2 Serial Port Status Register (SPSTS, offset 82h)
7
0
15
Reserved
FER OER
PER
TEMT
THRE
RDR
BRKI
Bits 15–7: Reserved—Set to 0.
Bit 6: Transmitter Empty (TEMT)—The TEMT bit is 1 when the transmitter has no data
to transmit and the transmit shift register is empty. This indicates to software that it is safe
to disable the transmit section. This bit is read-only.
Bit 5: Transmit Holding Register Empty (THRE)—When the THRE bit is 1, the transmit
holding register contains invalid data and can be written with data to be transmitted. When
the THRE bit is 0, the transmit holding register should not be written because it contains
valid data that has not yet been copied to the transmit shift register for transmission.
If transmit interrupts are enabled by the TMODE and TXIE fields, a serial port interrupt
request is generated when the THRE bit is 1. The THRE bit is reset automatically by writing
the transmit holding register. This bit is read-only, allowing other bits of the Serial Port
Status register to be written (i.e., resetting the BRKI bit) without interfering with the current
data request.
Bit 4: Receive Data Ready (RDR)—When the RDR bit is 1, the receive buffer register
contains data that can be read. When the RDR bit is 0, the receive buffer register does not
contain valid data. This bit is read-only.
If receive interrupts are enabled by the RMODE and RXIE fields, a serial port interrupt
request is generated when the THRE bit is 1. Reading the receive buffer register resets
the RDR bit.
Bit 3: Break Interrupt (BRKI)—The BRKI bit is set to indicate that a break has been
received. If the RSIE bit is 1, the BRKI bit being set causes a serial port interrupt request.
The BRKI bit should be reset by software.
Bit 2: Framing Error (FER)—The FER bit is set to indicate that a framing error occurred
during reception of data. If the RSIE bit is 1, the FER bit being set causes a serial port
interrupt request. The FER bit should be reset by software.
Bit 1: Parity Error (PER)—The PER bit is set to indicate that a parity error occurred during
reception of data. If the RSIE bit is 1, the PER bit being set causes a serial port interrupt
request. The PER bit should be reset by software.
Bit 0: Overrun Error (OER)—The OER bit is set when an overrun error occurs during
reception of data. If the RSIE bit is 1, the OER bit being set causes a serial port interrupt
request. The OER bit should be reset by software.
11-4
Asynchronous Serial Port
Download from Www.Somanuals.com. All Manuals Search And Download.
11.2.3
Serial Port Transmit Data Register (SPTD, Offset 84h)
The transmitter is double-buffered, and the transmit section copies data from the transmit
data register to the transmit shift register (which is not accessible to software) before
transmitting the data.
Figure 11-3 Serial Port Transmit Data Register (SPTD, offset 84h)
7
0
15
TDATA
Reserved
The value of SPTD at reset is undefined.
Bits 15–8: Reserved
Bit 7–0: Transmit Data (TDATA)—This field is written with data to be transmitted on the
serial port. The THRE bit in the Serial Port Status register indicates whether there is valid
data in the SPTD register. To avoid overwriting data in the SPTD register, the THRE bit
should be read as a 1 before writing this register. Writing this register causes the THRE bit
to be reset.
Asynchronous Serial Port
11-5
Download from Www.Somanuals.com. All Manuals Search And Download.
11.2.4
Serial Port Receive Data Register (SPRD, Offset 86h)
double-buffered, and the receive section can be receiving a subsequent frame of data in
the receive shift register (which is not accessible to software) while the receive data register
is being read by software.
Figure 11-4 Serial Port Receive Data Register (SPRD, offset 86h)
7
0
15
RDATA
Reserved
The value of SPRD at reset is undefined.
Bits 15–8: Reserved
Bits 7–0: Receive Data (RDATA)—This field contains data received on the serial port.
The RDR bit of the Serial Port Status register indicates valid data in the SPRD register. To
avoid reading invalid data, the RDR bit should be read as a 1 before the SPRD register is
read. Reading this register causes the RDR bit to be reset.
11-6
Asynchronous Serial Port
Download from Www.Somanuals.com. All Manuals Search And Download.
11.2.5
Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h)
that controls the serial port. The serial clock rate is 16 times the baud rate of transmission
orreceptionofdata. TheSPBAUDregisterspecifiesthenumberofinternalprocessorcycles
in one phase (half period) of the 16x serial clock.
If power-save mode is in effect, the baud rate divisor must be reprogrammed to reflect the
new processor clock frequency.
A general formula for the baud rate divisor is:
BAUDDIV=(Processor Frequency÷(32 Baud Rate))–1
The maximum baud rate is 1/32 of the internal processor clock and is achieved by setting
BAUDDIV=0000h. For a 40-MHz clock, a baud rate of 9600 can be achieved with
BAUDDIV=129 (81h). A 1% error applies.
Figure 11-5 Serial Port Baud Rate Divisor Register (SPBAUD, offset 88h)
7
0
15
BAUDDIV
The value of SPBAUD at reset is undefined.
Bits 15–0: Baud Rate Divisor (BAUDDIV)—This field specifies the divisor for the internal
processor clock that generates one phase (half period) of the serial clock. The serial clock
operates at 16 times the data transmission or reception baud rate.
Table 11-3 shows baud rate divisors for a range of common baud rates and processor clock
rates.
Table 11-3 Serial Port Baud Rate Table
Divisor Based on CPU Clock Rate
Baud Rate
20 MHz
2082
1040
519
259
129
64
25 MHz
2603
1301
650
324
161
80
33 MHz
3471
1735
867
433
216
107
71
40 MHz
4165
2082
1040
519
259
129
85
300
600
1200
2400
4800
9600
14,400
42
53
19,200
31
39
53
64
625 Kbaud
781.25 Kbaud
1.041 Mbaud
1.25 Mbaud
0
N/A
0
N/A
N/A
0
1
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
N/A
Asynchronous Serial Port
11-7
Download from Www.Somanuals.com. All Manuals Search And Download.
11-8
Asynchronous Serial Port
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
SYNCHRONOUS SERIAL INTERFACE
12
12.1
OVERVIEW
The synchronous serial interface enables the Am186ER and Am188ER microcontrollers
to communicate with application-specific integrated circuits (ASICs) that require
programmability but are short on pins. The four-pin interface permits half-duplex,
bidirectional data transfer at speeds of up to 20 Mbit/s with a 40-MHz CPU clock.
Unlike the asynchronous serial port, the SSI operates in a master/slave configuration. The
Am186ER and Am188ER microcontrollers operate as the master port.
The SSI interface provides four pins for communicating with system components: two
enables (SDEN0 and SDEN1), a clock (SCLK), and a data pin (SDATA). Five registers
n The Synchronous Serial Status register (SSS) reports the current port status.
n The Synchronous Serial Control register (SSC) sets the port clock rate and controls the
enable signals.
n There are two data transmit registers—the Synchronous Serial Transmit 0 register
(SSD0) and the Synchronous Serial Transmit 1 register (SSD1)—but data is transmitted
and received over a single pin (SDATA).
n The Synchronous Serial Receive Register (SSR) holds data received over the SSI.
Table 12-1 Synchronous Serial Interface Register Summary
Offset from Register
PCB
10h
12h
14h
16h
18h
Mnemonic
Register Name
SSS
Synchronous Serial Status
Synchronous Serial Control
Synchronous Serial Transmit 1
Synchronous Serial Transmit 0
Synchronous Serial Receive
SSC
SSD1
SSD0
SSR
Synchronous Serial Interface
12-1
Download from Www.Somanuals.com. All Manuals Search And Download.
12.1.1
Four-Pin Interface
The SDEN1–SDEN0 pins can be used to enable data transfer individually for as many as
two peripheral devices.
Transmit and receive operations are synchronized between the master (Am186ER or
Am188ER microcontroller) and slave (peripheral) by means of the SCLK output. SCLK is
derived from the processor internal clock divided by 2, 4, 8, or 16, as specified by the SSC
register. SCLK is only driven during data transmit or receive operations. The inactive state
of SCLK is High.
If power-save mode is in effect, the SCLK frequency is affected by the reduced processor
clock frequency.
Data is transferred across the SDATA input/output pin. Data is driven on the falling edge
of SCLK and latched on the rising edge of SCLK. The least-significant bit of the data is
shifted first for both transmit and receive operations. During write operations, the processor
holds data for one-half of an SCLK period following the transfer of the last data bit. SDATA
has a weak keeper that holds the last value of SDATA on the pin.
12.2
PROGRAMMABLE REGISTERS
Theregisters documentedon the followingpagesareaccessibletothesystem programmer.
12-2
Synchronous Serial Interface
Download from Www.Somanuals.com. All Manuals Search And Download.
12.2.1
Synchronous Serial Status Register (SSS, Offset 10h)
This read-only register indicates the state of the SSI port. The format of the Synchronous
Serial Status register is shown in Figure 12-1.
Figure 12-1 Synchronous Serial Status Register (SSS, offset 10h)
7
0
15
Reserved
RE/TE
DR/DT
PB
The value of the SSS register at reset is 0000h.
Bits 15–3: Reserved—Set to 0.
Bit 2: Receive/Transmit Error Detect (RE/TE)—This bit is set when the SSI detects either
a read of the Synchronous Serial Receive register or a write to one of the transmit registers
while the SSI is busy (PB=1). This bit is reset when the SDEN output is inactive (bits DE1–
DE0 in the SSC register are both 0).
Bit 1: Data Receive/Transmit Complete (DR/DT)—The DR/DT bit is set at the end of the
transfer of data bit 7 (SCLK rising edge) during a transmit or receive operation. This bit is
reset when the SSR register is read, when one of the SSD0 or SSD1 registers is written,
when the SSS register is read (unless the SSI completes an operation and sets the bit in
the same cycle), or when both SDEN0 and SDEN1 become inactive.
Bit 0: SSI Port Busy (PB)—When the PB bit is set, a transmit or receive operation is in
progress. When PB is reset, the port is ready to transmit or receive data.
Synchronous Serial Interface
12-3
Download from Www.Somanuals.com. All Manuals Search And Download.
12.2.2
Synchronous Serial Control Register (SSC, Offset 12h)
This read/write register controls the operation of the SDEN0–SDEN1 outputs and the
transfer rate of the SSI port. The SDEN0 and SDEN1 outputs are asserted when a 1 is
written to the corresponding bit. However, in the case when both DE0 and DE1 are set,
only SDEN0 will be asserted. The format of the Synchronous Serial Control register is
shown in Figure 12-2.
Figure 12-2 Synchronous Serial Control Register (SSC, offset 12h)
7
0
15
Res
Reserved
SCLKDIV
DE1
DE0
The value of the SSC register at reset is 0000h.
Bits 15–6: Reserved—Set to 1.
Bits 5–4: SCLK Divide (SCLKDIV)—These bits determine the SCLK frequency. SCLK is
the processor clock frequency divider values for the possible SCLKDIV settings.
If power-save mode is in effect, the SCLK frequency is affected by the reduced processor
clock frequency.
Table 12-2 SCLK Divider Values
SCLKDIV SCLK Frequency Divider
00b
01b
10b
11b
Processor clock / 2
Processor clock / 4
Processor clock / 8
Processor clock / 16
Bits 3–2: Reserved—Set to 0.
Bit 1: SDEN1 Enable (DE1)—When this bit is set to 1, the SDEN1 pin is held High. When
DE1 is set to 0, the SDEN1 pin is Low.
Bit 0: SDEN0 Enable (DE0)—When this bit is set to 1, the SDEN0 pin is held High. When
DE0 is set to 0, the SDEN0 pin is Low.
Note: The synchronous serial interface pins SDEN1–SDEN0, SCLK, and SDATA are
multiplexed with programmable I/O pins. To enable the pins to function as synchronous
serial interface, the PIO mode and PIO direction settings for the SDEN1–SDEN0, SCLK,
and SDATA pins must be set to 0 for normal operation. For more information, see
Chapter 13, “Programmable I/O Pins.”
12-4
Synchronous Serial Interface
Download from Www.Somanuals.com. All Manuals Search And Download.
12.2.3
Synchronous Serial Transmit 1 Register (SSD1, Offset 14h)
Synchronous Serial Transmit 0 Register (SSD0, Offset 16h)
The Synchronous Serial Transmit 1 and 0 registers contain data to be transferred from the
processor to the peripheral on a write operation. Only the least-significant 8 bits of the
register are used. The format of SSD1 and SSD0 is shown in Figure 12-3.
Writes to SSD1 or SSD0 cause the PB bit in the SSS register to be set and a transmission
while the port is busy sets the RE/TE (Receive/Transmit Error) bit in the SSS register and
does not generate additional data transfers.
Figure 12-3 Synchronous Serial Transmit Register (SSD1, SSD0, offsets 14h and 16h)
7
0
15
SD
Reserved
The value of these registers at reset is undefined.
Bits 15–8: Reserved—Set to 0.
Bits 7–0: Send Data (SD)—Data to transmit over the SDATA pin. Bit 0 is transmitted first,
bit 7 is transmitted last.
Synchronous Serial Interface
12-5
Download from Www.Somanuals.com. All Manuals Search And Download.
12.2.4
Synchronous Serial Receive Register (SSR, Offset 18h)
The Synchronous Serial Receive (SSR) register contains the data transferred from the
peripheral to the processor on a read operation. Only the least-significant 8 bits of the
register are used. The format of the SSR register is shown in Figure 12-4.
A receive data transmission is initiated by reading the SSR register while the port is not
busy (PB bit in SSS register is 0) and one or both of the enable bits (DE1–DE0 in the SSC
register) is set. A receive transmission is not initiated by reading the SSR register when
neither of the enable bits is set (DE1–DE0 = 00b). This allows the software to read the
received data without initiating another receive transmission.
A read of the Synchronous Serial Receive register while the port is busy (PB bit is set in
the SSS register) sets the RE/TE (Receive/Transmit Error) bit in the SSS register and
returns an indeterminate value. Such a read does not generate additional data transfers.
Figure 12-4 Synchronous Serial Receive Register (SSR, offset 18h)
7
0
15
SR
Reserved
The value of this register at reset is undefined.
Bits 15–8: Reserved—Set to 0.
Bits 7–0: Receive Data (SR)—Data received over the SDATA pin. Bit 0 is transmitted first,
bit 7 is transmitted last.
12-6
Synchronous Serial Interface
Download from Www.Somanuals.com. All Manuals Search And Download.
12.3
SSI PROGRAMMING
The SSI interface allows for a variety of software and hardware protocols.
n Signaling a read/write—In general, software uses the first write to the SSI to transmit
an address or count to the peripheral. This value can include a read/write flag in the
case where the device supports both reads and writes.
n Using SSD1 as an address register—The SSD1 register can be an address register
that holds the value of the last address accessed, and the SSD0 register can be the
data transmit register. In this case, the current value in the SSD1 register can be used
by software to generate the next address or to determine if the last transaction was a
read or a write.
n Using SSD1 and SSD0 as transmit registers for two peripheral devices—In some
systems, it may clarify the code and aid in debugging to view the two data transmit
registers as unique to different peripheral devices. This allows the last value transmitted
to each device to be examined by debug code.
Synchronous Serial Interface
12-7
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 12-5 Synchronous Serial Interface Multiple Write
PB=0
PB=1
PB=0
PB=1
PB=0
PB=1
PB=0
PB=0
DR/DT=0 DR/DT=0
DR/DT=1
DR/DT=0
DR/DT=1
DR/DT=0
DR/DT=1 DR/DT=0
SDEN
SCLK
SDATA
Poll SSS for
PB=0
Poll SSS for
PB=0
Poll SSS for
PB=0
Write to SSD
Write to SSC
bit DE=1
Write to SSD
Write to SSD
Write to SSC bit
DE=0
Figure 12-6 Synchronous Serial Interface Multiple Read
PB=0
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=0
DR/DT=0
SDEN
SCLK
SDATA
Poll SSS for
PB=0
Poll SSS for
PB=0
Poll SSS for
PB=0
Write to SSD
Read from SSR
(dummy)
Read from
SSR
Write to SSC
bit DE=0
Read from SSR
Write to SSC
bit DE=1
12-8
Synchronous Serial Interface
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER
PROGRAMMABLE I/O PINS
13
13.1
OVERVIEW
Thirty-two pins on the Am186ER and Am188ER microcontrollers are available as user-
programmable I/O signals (PIOs). Each of these pins can be used as a PIO if the normal
function of the pin is not needed. If a pin is enabled to function as a PIO signal, the normal
function is disabled and does not affect the pin. A PIO signal can be configured to operate
as an input or output with or without internal pullup or pulldown resistors, or as an open-
drain output.
After power-on reset, the PIO pins default to various configurations. The column titled
code must reconfigure PIOs as required.
The A19–A17 address pins default to normal operation on power-on reset, allowing the
processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R,
DEN, and SRDY pins also default to normal operation on power-on reset.
Figure 13-1 Programmable I/O Pin Operation
Mode
Dir.
VCC
PIO
Mode
PIO
Direction
Normal
Function
Int.
Bus
0
1
D
Q
Pin
WR
PDATA
Q
D
Data In
OE
40 MHz
(CLK)
RD
PDATA
Normal
Data In
PIOTRI
PIOPULL
PIODRV
Programmable I/O Pins
13-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 13-1 PIO Pin Assignments and Register Bits
PIO No. Register Bit Associated Pin
“0” Registers (PIOMODE0, 70h; PDIR0, 72h; PDATA0, 74h)
Power-On Reset Status
0
1
2
3
4
0
1
2
3
4
TMRIN1
TMROUT1
PCS6/A2
PCS5/A1
DT/R
Input with pullup
Input with pulldown
Input with pullup
Input with pullup
Normal operation(3)
Normal operation(3)
Normal operation(4)
Normal operation(3)
Normal operation(3)
5
5
6
7
8
DEN
SRDY
A17
6
7(1)
8(1)
A18
9(1)
10
11
Normal operation(3)
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
9
A19
10
11
12
13
14
15
TMROUT0
TMRIN0
DRQ0
12
13
14
15
DRQ1
MCS0
MCS1
“1” Registers (PIOMODE1, 76h; PDIR0, 78h; PDATA0, 7Ah)
16
17
18
19
20
21
22
23
24
25
0
1
PCS0
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
PCS1
2
PCS2
3
PCS3
4
SCLK
5
SDATA
SDEN0
SDEN1
MCS2
6
7
8
9
MCS3/RFSH
UZI/CLKSEL2
TXD
26(1,2)
27
10
11
12
13
14
15
28
RXD
29(1,2)
30
S6/CLKSEL1
INT4
31
INT2
Notes:
1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE,
ALE, AD15–AD0, and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN (Am186ER) or RFSH2/ADEN (Am188ER)
is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
13-2
Programmable I/O Pins
Download from Www.Somanuals.com. All Manuals Search And Download.
13.2
PIO MODE REGISTERS
Table 13-2 shows the possible settings for the PIO Mode and PIO Direction bits. The
Am186ER and Am188ER microcontrollers default the 32 PIO pins to either 00b (normal
operation) or 01b (PIO input with weak internal pullup or pulldown enabled).
Pins that default to active High outputs at reset are pulled down. All other pins are pulled
Table 13-1 lists the defaults for the PIOs.
The internal pullup resistor has a value of approximately 100 kohms. The internal pulldown
resistor has a value of approximately 100 kohms.
Table 13-2 PIO Mode and PIO Direction Settings
PIO Mode
PIO Direction
Pin Function
Normal operation
0
0
1
1
0
1
0
1
PIO input with pullup/pulldown
PIO output
PIO input without pullup/pulldown
Figure 13-2 PIO Mode 1 Register
(PIOMODE1, offset 76h)
Figure 13-3 PIO Mode 0 Register
(PIOMODE0, offset 70h)
15
7
0
15
7
0
PMODE (31–16)
PMODE (15–0)
13.2.1
PIO Mode 1 Register (PIOMODE1, Offset 76h)
The value of PIOMODE1 at reset is 0000h.
Bits 15–0: PIO Mode Bits (PMODE31–PMODE16)—This field with the PIO direction
registers determines whether each PIO pin performs its pre-assigned function or is enabled
as a custom PIO signal. The most significant bit of the PMODE field determines whether
PIO31 is enabled, the next bit determines whether PIO30 is enabled, and so on.
Table 13-2 shows the values that the PIO mode bits and the PIO direction bits can encode.
13.2.2
PIO Mode 0 Register (PIOMODE0, Offset 70h)
The value of PIOMODE0 at reset is 0000h.
Bits 15–0: PIO Mode Bits (PMODE15–PMODE0)—This field is a continuation of the
PMODE field in the PIO Mode 1 register.
Programmable I/O Pins
13-3
Download from Www.Somanuals.com. All Manuals Search And Download.
13.3
PIO DIRECTION REGISTERS
Each PIO isindividuallyprogrammed asan inputoroutputbyabitin one ofthe PIO Direction
Settings,” on page 3 shows the values that the PIO mode bits and the PIO direction bits
for the PIOs. Bits in the PIO Direction registers have the same correspondence to pins as bits
in the PIO Mode registers.
Figure 13-4 PIO Direction 1 Register
(PDIR1, offset 78h)
Figure 13-5 PIO Direction 0 Register
(PDIR0, offset 72h)
15
7
0
15
7
0
PDIR (31–16)
PDIR (15–0)
13.3.1
PIO Direction 1 Register (PDIR1, Offset 78h)
The value of PDIR1 at reset is FFFFh.
Bits 15–0: PIO Direction Bits (PDIR31–PDIR16)—This field determines whether each
PIO pin acts as an input or an output. The most significant bit of the PDIR field determines
the direction of PIO31, the next bit determines the direction of PIO30, and so on. A 1 in the
bit configures the PIO signal as an input, and a 0 in the bit configures it as an output or as
normal pin function.
13.3.2
PIO Direction 0 Register (PDIR0, Offset 72h)
The value of PDIR0 at reset is FC0Fh.
Bits 15–0: PIO Direction Bits (PDIR15–PDIR0)—This field is a continuation of the PDIR
field in the PIO Direction 1 register.
13-4
Programmable I/O Pins
Download from Www.Somanuals.com. All Manuals Search And Download.
13.4
PIO DATA REGISTERS
If a PIO pin is enabled as an output, the value in the corresponding bit in one of the PIO
(Low=0, High=1). If a PIO pin is enabled as an input, the value on the PIO pin is reflected
in the value of the corresponding bit in the PIO Data register, with no inversion. Bits in the
PIO Data registers have the same correspondence to pins as bits in the PIO Mode registers
and PIO Direction registers.
Figure 13-6 PIO Data 1 Register
(PDATA1, offset 7Ah)
Figure 13-7 PIO Data 0 Register
(PDATA0, offset 74h)
15
7
0
15
7
0
PDATA (15–0)
PDATA (31–16)
13.4.1
PIO Data Register 1 (PDATA1, Offset 7Ah)
Bits 7–0: PIO Data Bits (PDATA31–PDATA16)—This field determines the level driven on
each PIO pin or reflects the external level of the pin, depending upon whether the pin is
configured as an output or an input in the PIO Direction registers. The most significant bit
of the PDATA field indicates the level of PIO31, the next bit indicates the level of PIO30,
and so on.
The value of PDATA1 at reset is undefined.
13.4.2
13.5
PIO Data Register 0 (PDATA0, Offset 74h)
Bits 15–0: PIO Data Bits (PDATA15–PDATA0)—This field is a continuation of the PDATA
field in the PIO Data 1 register.
The value of PDATA0 at reset is undefined.
OPEN-DRAIN OUTPUTS
The PIO Data registers permit the PIO signals to be operated as open-drain outputs. This
is accomplished by keeping the appropriate PDATA bits constant in the PIO Data register
and writing the data value into its associated bit position in the PIO Direction register, so
the output is either driving Low or is disabled, depending on the data.
Programmable I/O Pins
13-5
Download from Www.Somanuals.com. All Manuals Search And Download.
13-6
Programmable I/O Pins
Download from Www.Somanuals.com. All Manuals Search And Download.
APPENDIX
REGISTER SUMMARY
A
This appendix summarizes the peripheral control block registers. Table A-1 lists all the
The column titled Comment in Table A-1 is used to identify the specific use of interrupt
registers when there is a mix of master mode and slave mode usage. The registers that
are marked as Slave & master can have different configurations for the different modes.
Register Summary
A-1
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1
Internal Register Summary
Hex Offset Mnemonic Register Description
Comment
FE
F6
F4
F0
E4
E2
E0
D8
D6
D4
D2
D0
CA
C8
C6
C4
C2
C0
AC
A8
A6
A4
A2
A0
88
86
84
82
80
7A
78
76
74
72
70
66
62
60
5E
RELREG
RESCON
PRL
Peripheral control block relocation register
Reset configuration register
Processor release level register
Power-save control register
PDCON
EDRAM
CDRAM
MDRAM
D1TC
Enable RCU register
Clock prescaler register
Memory partition register
DMA 1 transfer count register
DMA 1 destination address high register
DMA 1 destination address low register
DMA 1 source address high register
DMA 1 source address low register
DMA 0 control register
D1DSTH
D1DSTL
D1SRCH
D1SRCL
D0CON
D0TC
DMA 0 transfer count register
DMA 0 destination address high register
DMA 0 destination address low register
DMA 0 source address high register
DMA 0 source address low register
Internal memory chip select register
PCS and MCS auxiliary register
Midrange memory chip select register
Peripheral chip select register
Low memory chip select register
Upper memory chip select register
Serial port baud rate divisor register
Serial port receive data register
Serial port transmit data register
Serial port status register
D0DSTH
D0DSTL
D0SRCH
D0SRCL
IMCS
MPCS
MMCS
PACS
LMCS
UMCS
SPBAUD
SPRD
SPTD
SPSTS
SPCT
Serial port control register
PDATA1
PDIR1
PIO data 1 register
PIO direction 1 register
PIOMODE1 PIO mode 1 register
PDATA0
PDIR0
PIO data 0 register
PIO direction 0 register
PIOMODE0 PIO mode 0 register
T2CON
T2CMPA
T2CNT
Timer 2 mode/control register
Timer 2 maxcount compare A register
Timer 2 count register
T1CON
Timer 1 mode/control register
A-2
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1
Internal Register Summary (continued)
Hex Offset Mnemonic Register Description
Comment
5C
5A
58
56
54
52
50
44
42
40
3E
3C
3A
T1CMPB
T1CMPA
T1CNT
T0CON
T0CMPB
T0CMPA
T0CNT
SPICON
WDCON
I4CON
Timer 1 maxcount compare B register
Timer 1 maxcount compare A register
Timer 1 count register
Timer 0 mode/control register
Timer 0 maxcount compare B register
Timer 0 maxcount compare A register
Timer 0 count register
Serial port interrupt control register
Watchdog timer interrupt control register
INT4 control register
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
I3CON
INT3 control register
I2CON
INT2 control register
I1CON
INT1 control register
T2INTCON Timer 2 interrupt control register
I0CON INT0 control register
38
Master mode
Slave mode
T1INTCON Timer 1 interrupt control register
DMA1CON DMA 1 interrupt control register
DMA0CON DMA 0 interrupt control register
36
34
32
Slave & master
Slave & master
Master mode
Slave mode
TCUCON
Timer interrupt control register
T0INTCON Timer 0 interrupt control register
30
2E
2C
2A
28
26
24
22
INTSTS
REQST
INSERV
PRIMSK
IMASK
POLLST
POLL
Interrupt status register
Slave & master
Slave & master
Slave & master
Slave & master
Slave & master
Master mode
Master mode
Master mode
Slave mode
Interrupt request register
In-service register
Priority mask register
Interrupt mask register
Poll status register
Poll register
EOI
End-of-interrupt register
EOI
Specific end-of-interrupt register
Interrupt vector register
20
18
16
14
12
10
INTVEC
SSR
Slave mode
Synchronous serial receive register
Synchronous serial transmit 0 register
Synchronous serial transmit 1 register
Synchronous serial control register
Synchronous serial status register
SSD0
SSD1
SSC
SSS
Register Summary
A-3
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary
15
7
0
Offset
(Hexadecimal)
R19–R8
FE
Res S/M Res M/IO
Peripheral Control Block Relocation Register (RELREG)
Page 4-4
15
7
7
7
0
RC
F6
Reset Configuration Register (RESCON)
Page 4-5
15
0
Reserved
PRL
F4
Processor Release Level Register (PRL)
Page 4-6
15
0
F2–F0
0
0
0
0
0
0
0
0
F0
CAD
CAF
CBF CBD
PSEN
Power-Save Control Register (PDCON)
Page 4-7
7
0
15
E
0
0
0
0
0
0
T8–T0
E4
Enable RCU Register (EDRAM)
Page 7-2
7
0
15
RC8–RC0
E2
0
0
0
0
0
0
0
Clock Prescaler Register (CDRAM)
Page 7-2
A-4
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
15
7
0
E0
0
0
0
0
0
0
0
0
0
M6–M0
RA19
RA13
Memory Partition Register (MDRAM)
Page 7-1
15
7
0
TC INT
SYN
P
Res CHG ST B/W
DA
TDRQ
DM/IO
DINC
SDEC
DDEC
SINC
SM/IO
DMA 1 Control Register (D1CON)
Page 10-3
15
7
0
D8
D6
D4
TC15–TC0
DMA 1 Transfer Count Register (D1TC)
Page 10-5
15
7
0
Reserved
DDA19–DDA16
DMA 1 Destination Address High Register (D1DSTH)
Page 10-6
15
7
0
DDA15–DDA0
DMA 1 Destination Address Low Register (D1DSTL)
Page 10-7
7
0
15
Reserved
DSA19–DSA16
D2
DMA 1 Source Address High Register (D1SRCH)
Page 10-8
7
0
15
DSA15–DSA0
DMA 1 Source Address Low Register (D1SRCL)
D0
Page 10-9
Register Summary
A-5
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
15
7
0
TC INT
SYN
P
Res CHG ST B/W
CA
TDRQ
DM/IO
DINC
SDEC
DDEC
SINC
SM/IO
DMA 0 Control Register (D0CON)
Page 10-3
15
7
0
TC15–TC0
C8
DMA 0 Transfer Count Register (D0TC)
Page 10-5
15
7
0
Reserved
DDA19–DDA16
C6
DMA 0 Destination Address High Register (D0DSTH)
Page 10-6
15
7
0
DDA15–DDA0
C4
DMA 0 Destination Address Low Register (D0DSTL)
Page 10-7
7
0
15
DSA19–DSA16
Reserved
C2
DMA 0 Source Address High Register (D0SRCH)
Page 10-8
7
0
15
DSA15–DSA0
C0
DMA 0 Source Address Low Register (D0SRCL)
Page 10-9
A-6
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
15
7
0
Reserved
BA19–BA15
SR RE
AC
Internal Memory Chip Select Register (IMCS)
Page 6-3
15
7
0
1
M6–M0
EX MS
1
1
1
R2
R1–R0
A8
PCS and MCS Auxiliary Register (MPCS)
Page 5-10
15
7
0
BA19–BA13
1
1
1
1
1
1
R2
R1–R0
A6
Midrange Memory Chip Select Register (MMCS)
Page 5-8
7
0
15
BA19–BA11
1
1
1
R3 R2
R1–R0
A4
Peripheral Chip Select Register (PACS)
Page 5-12
15
7
0
0
UB2–UB0
1
1
1
1
R7 PSE
1
1
1
R2
R1–R0
A2
A19
Low Memory Chip Select Register (LMCS)
Page 5-6
15
7
R7
0
LB2–LB0
R2
R1–R0
1
0
0
0
0
0
1
1
1
A0
A19
Upper Memory Chip Select Register (UMCS)
Page 5-4
Register Summary
A-7
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
15
7
0
BAUDDIV
88
Serial Port Baud Rate Divisor Register (SPBAUD)
Page 11-7
15
7
0
RDATA
Reserved
86
84
82
Serial Port Receive Data Register (SPRD)
Page 11-6
7
0
15
TDATA
Reserved
Serial Port Transmit Data Register (SPTD)
Page 11-5
15
7
0
Reserved
FER PER OER
TEMT
THRE
RDR
BRKI
Serial Port Status Register (SPSTS)
Page 11-4
15
7
0
Reserved
BRK
PMODE
STP
RSIE
80
TXIE
RXIE
WLGN
TMODE
RMODE
LOOP
BRKVAL
Serial Port Control Register (SPCT)
Page 11-2
15
7
PDATA31–PDATA16
0
7A
PIO Data 1 Register (PDATA1)
Page 13-5
A-8
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
15
7
0
PDIR31–PDIR16
78
PIO Direction 1 Register (PDIR1)
Page 13-4
15
7
0
PMODE31–PMODE16
76
PIO Mode 1 Register (PIOMODE1)
Page 13-3
15
7
0
PDATA15–PDATA0
74
72
70
PIO Data 0 Register (PDATA0)
Page 13-5
15
7
0
PDIR15–PDIR0
PIO Direction 0 Register (PDIR0)
Page 13-4
15
7
0
PMODE15–PMODE0
PIO Mode 0 Register (PIOMODE0)
Page 13-3
7
0
15
EN INH INT
0
0
0
0
0
0
0
MC
0
0
0
0
66
CONT
Timer 2 Mode/Control Register (T2CON)
Page 9-5
Register Summary
A-9
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
62
TC15–TC0
Timer 2 Maxcount Compare A Register (T2CMPA)
Page 9-7
7
0
15
60
TC15–TC0
Timer 2 Count Register (T2CNT)
Page 9-6
15
7
0
EN INH INT RIU
0
0
0
0
0
0
MC RTG
P
EXT ALT
5E
Timer 1 Mode/Control Register (T1CON)
Page 9-3
CONT
0
15
7
TC15–TC0
5C
Timer 1 Maxcount Compare B Register (T1CMPB)
Page 9-7
7
0
15
5A
TC15–TC0
Timer 1 Maxcount Compare A Register (T1CMPA)
Page 9-7
7
0
15
58
TC15–TC0
Timer 1 Count Register (T1CNT)
Page 9-6
7
0
15
EN INH INT RIU
0
0
0
0
0
0
MC RTG
P
EXT ALT
56
Timer 0 Mode/Control Register (T0CON)
Page 9-3
CONT
A-10
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
0
0
15
54
TC15–TC0
Timer 0 Maxcount Compare B Register (T0CMPB)
Page 9-7
15
7
52
TC15–TC0
Timer 0 Maxcount Compare A Register (T0CMPA)
Page 9-7
7
15
TC15–TC0
50
Timer 0 Count Register (T0CNT)
Page 9-6
7
0
15
(1)
Reserved
Res MSK
PR2–PR0
44
Serial Port Interrupt Control Register (SPICON)
Master Mode
Page 8-20
7
0
15
Reserved
MSK
PR2–PR0
42
Watchdog Timer Interrupt Control Register (WDCON)
Master Mode
Page 8-19
15
7
0
Reserved
LTM MSK
PR2–PR0
40
INT4 Control Register (I4CON)
Master Mode
Page 8-17
Register Summary
A-11
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
MSK
Reserved
LTM
PR2–PR0
3E
INT3 Control Register (I3CON)
Master Mode
Page 8-16
7
0
15
Reserved
LTM MSK
PR2–PR0
3C
INT2 Control Register (I2CON)
Master Mode
Page 8-16
7
0
15
Reserved
C
LTM MSK
PR2–PR0
3A
SFNM
INT1 Control Register (I1CON)
Master Mode
Page 8-14
7
0
15
Reserved
MSK
PR2–PR0
3A
Timer 2 Interrupt Control Register (T2INTCON)
Slave Mode
Page 8-30
7
0
15
Reserved
C
LTM MSK
PR2–PR0
38
SFNM
INT0 Control Register (I0CON)
Master Mode
Page 8-14
7
0
15
Reserved
MSK
PR2–PR0
38
Timer 1 Interrupt Control Register (T1INTCON)
Slave Mode
Page 8-30
A-12
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
Reserved
36
MSK
PR2–PR0
DMA 1 Interrupt Control Register (DMA1CON)
Master Mode—Page 8-18
Slave Mode—Page 8-30
7
0
15
34
Reserved
MSK
PR2–PR0
DMA 0 Interrupt Control Register (DMA0CON)
Master Mode—Page 8-18
Slave Mode—Page 8-30
7
0
15
Reserved
32
MSK
PR2–PR0
Timer Interrupt Control Register (TCUCON)
Master Mode—Page 8-18
Timer 0 Interrupt Control Register (T0INTCON)
Slave Mode—Page 8-30
7
0
15
TMR2–TMR0
30
Reserved
DHLT
Interrupt Status Register (INTSTS)
Master Mode—Page 8-21
Slave Mode—Page 8-31
7
0
15
Reserved
SPI WD
I4
I3
I2
I1
I0
D1 D0 Res TMR
2E
Interrupt Request Register (REQST)
Master Mode
Page 8-22
Register Summary
A-13
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
Reserved
D1 D0 Res
TMR2 TMR1
2E
TMR0
Interrupt Request Register (REQST)
Slave Mode
Page 8-32
7
0
15
Reserved
SPI WD I4
I3
I2
I1
I0
D1 D0 Res TMR
2C
In-Service Register (INSERV)
Master Mode
Page 8-23
7
0
D1 D0 Res
TMR0
15
Reserved
2C
TMR2
TMR1
In-Service Register (INSERV)
Slave Mode
Page 8-33
7
0
15
Reserved
PRM2–PRM0
2A
Priority Mask Register (PRIMSK)
Master Mode—Page 8-24
Slave Mode—Page 8-34
7
0
15
28
Reserved
SPI WD I4
I3
I2
I1
I0
D1
D0 Res TMR
Interrupt Mask Register (IMASK)
Master Mode
Page 8-25
A-14
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
Reserved
D1 D0
TMR2 TMR1
Res
28
TMR0
Interrupt Mask Register (IMASK)
Slave Mode
Page 8-35
7
0
0
0
0
15
Reserved
S4–S0
26
24
22
22
IREQ
Poll Status Register (POLLST)
Master Mode
Page 8-26
7
7
7
15
Reserved
S4–S0
IREQ
Poll Register (POLL)
Master Mode
Page 8-27
15
Reserved
S4–S0
NSPEC
End-of-Interrupt Register (EOI)
Master Mode
Page 8-28
15
Reserved
L2–L0
Specific End-of-Interrupt Register (EOI)
Slave Mode
Page 8-36
Register Summary
A-15
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure A-1
Internal Register Summary (continued)
7
0
15
Reserved
T4–T0
0
0
0
20
Interrupt Vector Register (INTVEC)
Slave Mode
Page 8-37
7
0
15
SR
Reserved
18
Synchronous Serial Receive Register (SSR)
Page 12-6
7
7
7
0
0
0
15
SD
Reserved
16
Synchronous Serial Transmit 0 Register (SSD0)
Page 12-5
15
SD
Reserved
14
Synchronous Serial Transmit 1 Register (SSD1)
Page 12-5
15
Reserved
SCLKDIV
Res
DE1 DE0
12
Synchronous Serial Control Register (SSC)
Page 12-4
15
7
0
PB
Reserved
10
RE/TE
DR/DT
Synchronous Serial Status Register (SSS)
Page 12-3
A-16
Register Summary
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
A
B
A1 signal (Latched Address Bit 1), 3-8
A19-A0 signals (Address Bus), 3-1
A2 signal (Latched Address Bit 2), 3-9
AD15-AD8 signals (Address and Data Bus), 3-2
AD7-AD0 signals (Address and Data Bus), 3-1
Address generation, 2-3
B/W bit (Byte/Word Select), 10-4
BA19-BA11 field (Base Address)
Peripheral Chip Select Register, 5-12
BA19-BA13 field (Base Address)
Midrange Memory Chip Select Register, 5-8
BA19-BA15 field (Base Address)
Internal Memory Chip Select Register, 6-3
Addressing modes, 2-10
Base and index registers, 2-1
ADEN signal (Address Enable), 3-3, 3-12
Based Indexed mode addressing, 2-10
Based mode addressing, 2-10
AF bit (Auxiliary Carry)
Processor Status Flags Register, 2-3
Basic functional system, 1-6–1-7
BAUDDIV field (Baud Rate Divisor), 11-7
BHE signal (Bus High Enable), 3-3
Binary-coded decimal (BCD) data type, 2-8
ALE signal (Address Latch Enable), 3-2
ALT bit (Alternate Compare Bit)
Timer 0 Mode/Control Register, 9-4
Timer 1 Mode/Control Register, 9-4
Am186ER Microcontroller
address generation, 2-3
addressing modes, 2-10
application considerations, 1-6
block diagram, 1-4
Bits
AF (Auxiliary Carry), 2-3
ALT (Alternate Compare Bit), 9-4
B/W (Byte/Word Select), 10-4
BA19-BA11 (Base Address), 5-12
BA19-BA13 (Base Address), 5-8
BA19-BA15 (Base Address), 6-3
BAUDDIV (Baud Rate Divisor), 11-7
BRK (Send Break), 11-2
clock generation, 1-6
data types, 2-8
distinctive characteristics, 1-2
I/O space, 2-4
instruction set, 2-4
BRKI (Break Interrupt), 11-4
BRKVAL (Break Value), 11-2
C (Cascade Mode), 8-14
CAD (CLKOUTA Drive Disable), 4-7
CAF (CLKOUTA Output Frequency), 4-7
CBD (CLKOUTB Drive Disable), 4-7
CBF (CLKOUTB Output Frequency), 4-7
CF (Carry Flag), 2-3
key features and benefits, 1-1
memory interface, 1-7
memory operands, 2-10
memory organization, 2-3
product support, iii
register and immediate operands, 2-10
register set, 2-1
segment registers, 2-8
serial port, 1-7
signal descriptions, 3-1
CHG (Change Start Bit), 10-4
CONT (Continuous Mode Bit), 9-4–9-5
D1-D0 (DMA Channel Interrupt In-Service), 8-23, 8-
33, 8-35
D1-D0 (DMA Channel Interrupt Masks), 8-25
D1-D0 (DMA Channel Interrupt Request), 8-22, 8-32
DA (Address Disable), 5-5, 5-7
DDA15-DDA0 (DMA Destination Address Low), 10-
7
DDA19-DDA16 (DMA Destination Address High),
10-6
DDEC (Destination Decrement), 10-3
DE0 (SDEN0 Enable), 12-4
Am188ER Microcontroller
block diagram, 1-5
signal descriptions
RFSH2/ADEN (Refresh 2/Address Enable), 3-12
WB (Write Byte), 3-16
AO15-AO7 signals (Address-Only Bus), 3-2
Application considerations, 1-6
ARDY signal (Asynchronous Ready), 3-3
ASCII data type, 2-8
Auxiliary Carry bit, 2-3
DE1 (SDEN1 Enable), 12-4
DF (Direction Flag), 2-2
Index
I-1
Download from Www.Somanuals.com. All Manuals Search And Download.
DHLT (DMA Halt), 8-21, 8-31
RDATA (Receive Data), 11-6
DINC (Destination Increment), 10-3
DM/IO (Destination Address Space Select), 10-3
DR/DT (Data Receive/Transmit Complete), 12-3
DSA15-DSA0 (DMA Source Address Low), 10-9
DSA19-DSA16 (DMA Source Address High), 10-8
E (Enable RCU), 7-2
RDR (Receive Data Ready), 11-4
RE (Internal Ram Enable), 6-3
RE/TE (Receive/Transmit Error Detect), 12-3
RIU (Register in Use), 9-3
RMODE (Receive Mode), 11-3
RSIE (Receive Status Interrupt Enable), 11-3
RTG (Retrigger Bit), 9-3
EN (Enable Bit), 9-3, 9-5
EX (Pin Selector), 5-11
EXT (External Clock Bit), 9-4
RXIE (Receive Data Ready Interrupt Enable), 11-2
S/M (Slave/Master), 4-4
FER (Framing Error), 11-4
S4-S0 (Poll Status), 8-26–8-27
I4-I0 (Interrupt In-Service), 8-23
I4-I0 (Interrupt Mask), 8-25
S4-S0 (Source Interrupt Type), 8-28
SD (Send Data), 12-5
I4-I0 (Interrupt Requests), 8-22
IF (Interrupt-Enable Flag), 2-3
SDEC (Source Decrement), 10-4
SF (Sign Flag), 2-3
INH (Inhibit Bit), 9-3, 9-5
INT (Interrupt Bit), 9-3, 9-5
INT (Interrupt), 10-4
IREQ (Interrupt Request), 8-26–8-27
L2-L0 (Interrupt Type), 8-36
SFNM (Special Fully Nested Mode), 8-14
SINC (Source Increment), 10-4
SM/IO (Source Address Space Select), 10-3
SPI (Serial Port Interrupt In-Service), 8-23
SPI (Serial Port Interrupt Mask), 8-25
SPI (Serial Port Interrupt Request), 8-22
SR (Receive Data), 12-6
LB2-LB0 (Lower Boundary), 5-4
LOOP (Loopback), 11-2
LTM (Level-Triggered Mode), 8-14, 8-16–8-17
M/IO (Memory/I/O Space), 4-4
M6-M0 (MCS Block Size), 5-10
M6-M0 (Refresh Base), 7-1
MC (Maximum Count Bit), 9-3, 9-5
MS (Memory/I/O Space Selector), 5-11
MSK (Interrupt Mask), 8-18
SR (Show Read), 6-3
ST (Start/Stop DMA Channel), 10-4
STP (Stop Bits), 11-3
SYN1-SYN0 (Synchronization Type), 10-4
T4-T0 (Interrupt Type), 8-37
T8-T0 (Refresh Count), 7-2
TC (Terminal Count), 10-4
MSK (Mask), 8-14, 8-16–8-17, 8-19–8-20, 8-30
NSPEC (Non-Specific EOI), 8-28
OER (Overrun Error), 11-4
TC15-TC0 (Timer Compare Value), 9-7
TC15-TC0 (Timer Count Register), 10-5
TC15-TC0 (Timer Count Value), 9-6
TDATA (Transmit Data), 11-5
OF (Overflow Flag), 2-2
P (Prescaler Bit), 9-3
P (Relative Priority), 10-4
PB (SSI Port Busy), 12-3
TDRQ (Timer Enable/Disable Request), 10-4
TEMT (Transmitter Empty), 11-4
TF (Trace Flag), 2-3
PDATA15-PDATA0 (PIO Data BIts), 13-5
PDATA31-PDATA16 (PIO Data BIts), 13-5
PDIR15-PDIR0 (PIO Direction Bits), 13-4
PDIR31-PDIR16 (PIO Direction Bits), 13-4
PER (Parity Error), 11-4
PF (Parity Flag), 2-3
PMODE (Parity Mode), 11-3
PMODE15-PMODE0 (PIO Mode Bits), 13-3
PMODE31-PMODE16 (PIO Mode Bits), 13-3
PR2-PR0 (Priority Level), 8-30
PR2-PR0 (Priority), 8-15–8-20
THRE (Transmit Holding Register Empty), 11-4
TMODE (Transmit Mode), 11-3
TMR (Timer Interrupt In-Service), 8-23
TMR (Timer Interrupt Mask), 8-25
TMR (Timer Interrupt Request), 8-22
TMR0 (Timer 0 Interrupt In-Service), 8-33
TMR0 (Timer 0 Interrupt Mask), 8-35
TMR0 (Timer 0 Interrupt Request), 8-32
TMR2-TMR0 (Timer Interrupt Request), 8-21, 8-31
TMR2-TMR1 (Timer 2/Timer 1 Interrupt In-Service),
8-33
PRL (Processor Release Level), 4-6
PRM2-PRM0 (Priority Field Mask), 8-24, 8-34
PSE (PSRAM Mode Enable), 5-7
PSEN (Enable Power-Save Mode), 4-7
R19-R8 (Relocation Address Bits), 4-4
R1-R0 (Wait State Value), 5-5, 5-7, 5-9, 5-11, 5-13
R2 (Ready Mode), 5-5, 5-7, 5-9, 5-11, 5-13
R3 (Wait State Value), 5-13
TMR2-TMR1 (Timer 2/Timer 1 Interrupt Mask), 8-35
TRM2-TMR1 (Timer2/Timer1 Interrupt Request), 8-
32
TXIE (Transmit Holding Register Empty Interrupt
Enable), 11-2
WD (Virtual Watchdog Timer Interrupt Request), 8-
22
WD (Watchdog Timer Interrupt In-Service), 8-23
WD (Watchdog Timer Interrupt Mask), 8-25
WLGN (Word Length), 11-3
RC (Reset Configuration), 4-5
RC8-RC0 (Refresh Counter Reload Value), 7-2
I-2
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
ZF (Zero Flag), 2-3
Crystal-driven clock source, 3-24
Block diagram, 1-4–1-5
BRK bit (Send Break), 11-2
BRKI bit (Break Interrupt), 11-4
BRKVAL bit (Break Value), 11-2
D
D1-D0 field (DMA Channel Interrupt In-Service), 8-23,
8-33, 8-35
Bus
D1-D0 field (DMA Channel Interrupt Masks), 8-25
interface unit, 3-21
nonmultiplexed address, 3-21
operation, 3-18
D1-D0 field (DMA Channel Interrupt Request), 8-22, 8-
32
read and write timing, 3-19–3-20
DA field (Address Disable)
Byte write enables, 3-21
Upper Memory Chip Select Register, 5-5, 5-7
Data Segment (DS) Register, 2-8
Data sheet, xiv
C
Data types, 2-8
C bit (Cascade Mode), 8-14
DDA15-DDA0 field (DMA Destination Address Low),
10-7
CAD bit (CLKOUTA Drive Disable)
System Configuration Register, 4-7
DDA19-DDA16 field (DMA Destination Address High),
10-6
CAF bit (CLKOUTA Output Frequency)
System Configuration Register, 4-7
DDEC bit (Destination Decrement), 10-3
DE0 bit (SDEN0 Enable), 12-4
DE1 bit (SDEN1 Enable), 12-4
DEN signal (Data Enable), 3-4
Carry Flag bit, 2-3
Cascade mode, 8-11
Catalog, xiv
CBD bit (CLKOUTB Drive Disable)
System Configuration Register, 4-7
Development
support, 1-8
CBF bit (CLKOUTB Output Frequency)
System Configuration Register, 4-7
third-party products, xiv
tools, xiv
CD-ROM documentation, xiv
DF bit (Direction Flag)
Processor Status Flags Register, 2-2
CF bit (Carry Flag)
Processor Status Flags Register, 2-3
DHLT bit (DMA Halt), 8-21, 8-31
DINC bit (Destination Increment), 10-3
Direct mode addressing, 2-10
Characteristics, 1-2
CHG bit (Change Start Bit), 10-4
Chip select timing, 5-2
Direction Flag bit, 2-2
CLKOUTA signal (Clock Output A)
definition, 3-4
Displacement, Based Indexed mode, 2-10
Distinctive characteristics, 1-2
use, 3-25
Divide by Two mode, 3-23
CLKOUTB signal (Clock Output B)
definition, 3-4
DM/IO bit (Destination Address Space Select), 10-3
DMA
use, 3-25
operation, 10-1
requests, 10-10
timing, 10-11
CLKSEL1 signal (Clock Select 1), 3-13
CLKSEL2 signal (Clock Select 2), 3-15
Clock
transfer rates, 10-10
unit block diagram, 10-2
and power management unit, 3-23
frequency, 3-23
generation, 1-6
prescaler register, 7-2
source, 3-24
DMA 0 Control Register, 10-3
DMA 0 Destination Address High Register, 10-6
DMA 0 Destination Address Low Register, 10-7
DMA 0 Interrupt Control Register
Master mode, 8-18
Clocking modes, 3-16
Code Segment (CS) Register, 2-8
Slave mode, 8-30
CONT bit (Continuous Mode Bit)
Timer 0 Mode/Control Register, 9-4
Timer 1 Mode/Control Register, 9-4
Timer 2 Mode/Control Register, 9-5
DMA 0 Source Address High Register, 10-8
DMA 0 Source Address Low Register, 10-9
DMA 0 Transfer Count Register, 10-5
DMA 1 Control Register, 10-3
Index
I-3
Download from Www.Somanuals.com. All Manuals Search And Download.
DMA 1 Destination Address High Register, 10-6
DMA 1 Destination Address Low Register, 10-7
Read and write bus timing, 3-19–3-20
FLAGS Register, 2-2
DMA 1 Interrupt Control Register
Master mode, 8-18
Frequency, clock, 3-23
FTP site, xiv
Slave mode, 8-30
Fully nested mode, 8-10
DMA 1 Source Address High Register, 10-8
DMA 1 Source Address Low Register, 10-9
DMA 1 Transfer Count Register, 10-5
Fully nested mode interrupt controller connections, 8-10
Functional system design, 1-6–1-7
FusionE86 catalog, xiv
Documentation, iii, xiv
Double word data type, 2-8
DR/DT bit (Data Receive/Transmit Complete), 12-3
DRQ1-DRQ0 signals (DMA Requests), 3-4
DSA15-DSA0 field (DMA Source Address Low), 10-9
DSA19-DSA16 field (DMA Source Address High), 10-8
DT/R signal (Data Transmit or Receive), 3-4
G
General registers, 2-1
H
HLDA signal (Bus Hold Acknowledge), 3-4
HOLD signal (Bus Hold Request), 3-5
E
E bit (Enable RCU), 7-2
Effective address, 2-10
I
Emulators, pins used by, 3-17
I/O space, 2-4
EN bit (Enable Bit)
I4-I0 field (Interrupt In-Service), 8-23
I4-I0 field (Interrupt Mask), 8-25
I4-I0 field (Interrupt Requests), 8-22
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
IF bit (Interrupt-Enable Flag)
EN bit (Enable Power-Save Mode), 4-7
Enable RCU Register, 7-2
Processor Status Flags Register, 2-3
IF bit (Interrupt-Enable flag)
programming, 8-2
End-of-Interrupt (EOI) Register
description, 8-28
IMDIS signal (Internal Memory Disable), 3-13
Immediate operands, 2-10
End-of-interrupt (EOI) Register
programming, 8-12
Indexed mode addressing, 2-10
EX bit (Pin Selector), 5-11
Example system design, 1-6–1-7
Exceptions, instruction, 8-3
INH bit (Inhibit Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
EXT bit (External Clock Bit)
Timer 0 Mode/Control Register, 9-4
Timer 1 Mode/Control Register, 9-4
In-Service Register
Master mode, 8-23
Slave mode, 8-33
External clock source, 3-24
External interrupt acknowledge bus cycles table, 8-8
Extra Segment (ES) Register, 2-8
Instruction exceptions, 8-3
Instruction set, 2-4
INT bit (Interrupt Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
F
F2-F0 field (Clock Divisor Select)
System Configuration Register, 4-8
INT0 Control Register
Master mode, 8-14
FER bit (Framing Error), 11-4
INT0 signal (Maskable Interrupt Request 0), 3-5
Figure
INT1 Control Register
Master mode, 8-14
DMA Unit Block Diagram, 10-2
external interrupt acknowledge bus cycles, 8-8
Fully nested mode interrupt controller connections,
8-10
INT1 signal (Maskable Interrupt Request 1), 3-5
INT2 Control Register
I-4
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
Master mode, 8-16
polled, 8-12
Slave mode, 8-29
Slave mode nesting, 8-29
Special fully nested mode, 8-12
trace, 8-6
types, 8-1, 8-6
types, table of, 8-3
unused opcode, 8-7
INT2 signal (Maskable Interrupt Request 2), 3-6
INT3 Control Register
Master mode, 8-16
INT3 signal (Maskable Interrupt Request 3), 3-6
INT4 Control Register
Master mode, 8-17
INT4 signal (Maskable Interrupt Request 4), 3-6
INTA0 signal (Interrupt Acknowledge 0), 3-6
INTA1 signal (Interrupt Acknowledge 1), 3-6
Integer data type, 2-8
IREQ bit (Interrupt Request)
Poll Register, 8-27
Poll Status Register, 8-26
IRET, 8-4
Internal memory
IRQ signal (Slave Interrupt Request), 3-6
debug modes, 6-2
disable, 6-2
external RAM interaction, 6-1
show read enable, 6-2
K
Key features and benefits, 1-1
Interrupt acknowledge, 8-8
Interrupt conditions and sequence, 8-4
Interrupt control unit, 8-1
L
Interrupt controller registers
Master mode, 8-13
L2-L0 field (Interrupt Type), 8-36
LB2-LB0 field (Lower Boundary), 5-4
LCS signal (Low Memory Chip Select), 3-7
LOOP bit (Loopback), 11-2
Slave mode, 8-29
Interrupt controller reset conditions, 8-9
Interrupt enable flag (IF), 8-2
Interrupt mask bit, 8-2
Low Memory Chip Select Register, 5-6
LTM bit (Level-Triggered Mode)
INT0 Control Register, 8-14
INT1 Control Register, 8-14
INT2 Control Register, 8-16
INT3 Control Register, 8-16
INT4 Control Register, 8-17
Interrupt Mask Register
Master mode, 8-25
Slave mode, 8-35
Interrupt priority, 8-2, 8-5
Interrupt Request Register
Master mode, 8-22
Slave mode, 8-32
Interrupt return (IRET), 8-4
M
Interrupt Status Register
Master mode, 8-21
Slave mode, 8-31
M/IO bit (Memory/I/O Space), 4-4
M6-M0 field (MCS Block Size), 5-10
M6-M0 field (Refresh Base), 7-1
Maskable interrupts, 8-2
Interrupt Vector Register
Slave mode, 8-37
Master mode operation, 8-10
Interrupt vector table, 8-1
MC bit (Maximum Count Bit)
Interrupt-Enable Flag bit, 2-3
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
Interrupts
array BOUNDs exception, 8-7
breakpoint, 8-7
MCS2-MCS0 signals (Midrange Memory Chip Selects
2-0), 3-7
cascade mode, 8-11
divide error exception, 8-6
EOI, 8-12
MCS3 signal (Midrange Memory Chip Select 3), 3-7
ESC opcode exception, 8-7
fully nested mode, 8-10
Instruction exceptions, 8-3
INTO overflow detected, 8-7
Maskable and nonmaskable, 8-2
Master mode operation, 8-10
nonmaskable (NMI), 8-6
Memory
addressing modes, 2-10
interface, 1-7
operands, 2-10
organization, 2-3
Memory Partition Register, 7-1
Index
I-5
Download from Www.Somanuals.com. All Manuals Search And Download.
Midrange Memory Chip Select Register, 5-8
MS bit (Memory/I/O Space Selector), 5-11
PDATA31-PDATA16 field (PIO Data BIts), 13-5
PDIR15-PDIR0 field (PIO Direction Bits), 13-4
PDIR31-PDIR16 field (PIO Direction Bits), 13-4
PER bit (Parity Error), 11-4
MSK bit (Interrupt Mask)
description, 8-2
DMA Interrupt Control Registers, 8-18
Timer Interrupt Control Registers, 8-18
Peripheral Chip Select Register, 5-12
Peripheral Control Block Relocation Register, 4-4
MSK bit (Mask)
PF bit (Parity Flag)
DMA Interrupt Control Registers, 8-30
INT0 Control Register, 8-14
INT1 Control Register, 8-14
INT2 Control Register, 8-16
INT3 Control Register, 8-16
Processor Status Flags Register, 2-3
Phase-locked loop (PLL), 3-23
Physical address generation, 2-4
Physical dimensions, xiv
INT4 Control Register, 8-17
Pin Descriptions, 3-1
Serial Port Interrupt Control Register, 8-20
Timer Interrupt Control Registers, 8-30
Watchdog Timer Interrupt Control Register, 8-19
Pins used by emulators, 3-17
PIO Data 0 Register, 13-5
PIO Data 1 Register, 13-5
PIO Direction 0 Register, 13-4
PIO Direction 1 Register, 13-4
PIO Mode 0 Register, 13-3
N
NMI signal (Nonmaskable Interrupt), 3-7
Nonmaskable interrupts, 8-2, 8-6
Nonmultiplexed address bus, 3-21
NSPEC bit (Non-Specific EOI), 8-28
PIO Mode 1 Register, 13-3
PIO pullup/pulldown resistor, 13-3
PIO31-PIO0 signals (Programmable I/O Pins 31-0), 3-9
PMODE field (Parity Mode), 11-3
PMODE15-PMODE0 field (PIO Mode Bits), 13-3
PMODE31-PMODE16 field (PIO Mode Bits), 13-3
Pointer data type, 2-9
O
OER bit (Overrun Error), 11-4
Poll Register
OF bit (Overflow Flag)
Master mode, 8-27
Processor Status Flags Register, 2-2
Poll Status Register
Master mode, 8-26
Offset calculation, 2-10
ONCE0 signal (ONCE Mode Request 0), 3-7
ONCE1 signal (ONCE Mode Request 1), 3-15
On-line documentation, xiv
Polled interrupts, 8-12
Power management unit, 3-23
Power-Save Control Register, 4-7
Power-save operation, 3-25
Ordinal data type, 2-8
Overflow Flag bit, 2-2
PR2-PR0 field (Priority Level)
Overlap, chip select, 5-2
DMA Interrupt Control Register, 8-30
Timer Interrupt Control Register, 8-30
PR2-PR0 field (Priority)
P
DMA Interrupt Control Registers, 8-18
INT0 Control Register, 8-15
P bit (Prescaler Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
INT1 Control Register, 8-15
INT2 Control Register, 8-16
INT3 Control Register, 8-16
P bit (Relative Priority), 10-4
INT4 Control Register, 8-17
Packed BCD data type, 2-8
Serial Port Interrupt Control Register, 8-20
Timer Interrupt Control Registers, 8-18
Watchdog Timer Interrupt Control Register, 8-19
Parity Flag bit, 2-3
PB bit (SSI Port Busy), 12-3
PCS and MCS Auxiliary Register, 5-10
PCS3-PCS0 signals (Peripheral Chip Selects 3-0), 3-8
PCS5 signal (Peripheral Chip Select 5), 3-8
PCS6 signal (Peripheral Chip Select 6), 3-8
PDATA15-PDATA0 field (PIO Data BIts), 13-5
Priority Mask Register
Master mode, 8-24
Slave mode, 8-34
PRM2-PRM0 field (Priority Field Mask), 8-24, 8-34
Processor Release Level Register, 4-6
I-6
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
Processor Status Flags Register (FLAGS), 2-2
DMA 0 Source Address High (D0SRCH, Offset
C2h), 10-8
Product support
DMA 0 Source Address Low (D0SRCL, Offset C0h),
10-9
DMA 0 Transfer Count (D0TC, Offset C8h), 10-5
DMA 1 Control (D1CON, Offset DAh), 10-3
DMA 1 Destination Address High (D0DSTH, Offset
C6h), 10-6
bulletin board service, iii
documentation and literature, iii
technical support hotline, iii
PSE bit (PSRAM Mode Enable), 5-7
Pseudo Static RAM (PSRAM) support, 3-21
Pullup/pulldown resistor, 13-3
DMA 1 Destination Address High (D1DSTH, Offset
D6h), 10-6
DMA 1 Destination Address Low (D0DSTL, Offset
C4h), 10-7
DMA 1 Destination Address Low (D1DSTL, Offset
D4h), 10-7
Q
Quad word data type, 2-8
DMA 1 Interrupt Control (DMA1CON, Offset 36h), 8-
18, 8-30
DMA 1 Source Address High (D1SRCH, Offset
D2h), 10-8
R
R19-R8 field (Relocation Address Bits), 4-4
DMA 1 Source Address Low (D1SRCL, Offset D0h),
10-9
R1-R0 field (Wait State Value)
Low Memory Chip Select Register, 5-7
Midrange Memory Chip Select Register, 5-9
PCS and MCS Auxiliary Register, 5-11
Peripheral Chip Select Register, 5-13
Upper Memory Chip Select Register, 5-5
DMA 1 Transfer Count (D1TC, Offset D8h), 10-5
Enable RCU (EDRAM, Offset E4h), 7-2
End-of-Interrupt (EOI, Offset 22h), 8-28
In-Service (INSERV, Offset 2Ch), 8-23, 8-33
INT0 Control (I0CON, Offset 38h)
Master mode, 8-14
INT1 Control (I1CON, Offset 3Ah)
Master mode, 8-14
INT2 Control (I2CON, Offset 3Ch)
Master mode, 8-16
INT3 Control (I3CON, Offset 3Eh)
Master mode, 8-16
INT4 Control (I4CON, Offset 40h)
Master mode, 8-17
Internal Memory Chip Select (IMCS, Offset ACh), 6-
3
R2 bit (Ready Mode)
Low Memory Chip Select Register, 5-7
Midrange Memory Chip Select Register, 5-9
PCS and MCS Auxiliary Register, 5-11
Peripheral Chip Select Register, 5-13
Upper Memory Chip Select Register, 5-5
R3 bit (Wait-State Value)
Peripheral Chip Select Register, 5-13
RC field (Reset Configuration), 4-5
RC8-RC0 field (Refresh Counter Reload Value), 7-2
RD signal (Read Strobe), 3-12
Interrupt Mask (IMASK, Offset 28h), 8-25, 8-35
Interrupt Request (REQST, Offset 2Eh), 8-22, 8-32
Interrupt Status (INSTS, Offset 30h), 8-21
Interrupt Status (INTSTS, Offset 30h), 8-31
Interrupt Vector (INTVEC, Offset 20h), 8-37
Low Memory Chip Select (LMCS, Offset A2h), 5-6
Memory Partition (MDRAM, Offset E0h), 7-1
Midrange Memory Chip Select (MMCS, Offset A6h),
5-8
PCS and MCS Auxiliary (MPCS, Offset A8h), 5-10
Peripheral Chip Select (PACS, Offset A4h), 5-12
Peripheral Control Block Relocation (RELREG,
Offset FEh), 4-4
RDATA field (Receive Data), 11-6
RDR bit (Receive Data Ready), 11-4
RE field (Internal RAM Enable)
Internal Memory Chip Select Register, 6-3
RE/TE bit (Receive/Transmit Error Detect), 12-3
Read and write bus timing, 3-19–3-20
Ready signal programming, 5-2
Register Indirect mode addressing, 2-10
Register operands, 2-10
Register set
base and index registers, 2-1
general registers, 2-1
PIO Data 0 (PDATA0, Offset 74h), 13-5
PIO Data 1 (PDATA1, Offset 7Ah), 13-5
PIO Direction 0 (PDIR0, Offset 72h), 13-4
PIO Direction 1 (PDIR1, Offset 78h), 13-4
PIO Mode 0 (PIOMODE0, Offset 70h), 13-3
PIO Mode 1 (PIOMODE1, Offset 76h), 13-3
Poll (POLL, Offset 24h), 8-27
segment registers, 2-1
stack pointer register, 2-1
status and control registers, 2-1
Registers
Clock Prescaler (CDRAM, Offset E2h), 7-2
DMA 0 Control (D0CON, Offset CAh), 10-3
DMA 0 Interrupt Control (DMA0CON, Offset 34h), 8-
18, 8-30
Poll Status (POLLST, Offset 26h), 8-26
Index
I-7
Download from Www.Somanuals.com. All Manuals Search And Download.
Power-Save Control (PDCON, Offset F0h), 4-7
Priority Mask (PRIMSK, Offset 2Ah), 8-24, 8-34
Processor Release Level (PRL, Offset F4), 4-6
Reset Configuration (RESCON, Offset F6h), 4-5
Serial Port Baud Rate Divisor (SPBAUD, Offset
88h), 11-7
Serial Port Control (SPCT, Offset 80h), 11-2
Serial Port Interrupt Control (SPICON, Offset 44h)
Master mode, 8-20
RMODE bit (Receive Mode), 11-3
RSIE bit (Receive Status Interrupt Enable), 11-3
RTG bit (Retrigger Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
RXD signal (Receive Data), 3-12
RXIE bit (Receive Data Ready Interrupt Enable), 11-2
Serial Port Receive Data (SPRD, Offset 86h), 11-6
Serial Port Status (SPSTS, Offset 82h), 11-4
Serial Port Transmit (SPTD, Offset 84h), 11-5
Specific End-of-Interrupt (EOI, OFfset 22h), 8-36
Synchronous Serial Control (SSC, Offset 12h), 12-4
Synchronous Serial Receive (SSR, Offset 18h), 12-6
Synchronous Serial Status (SSS, Offset 10h), 12-3
Synchronous Serial Transmit 0 (SSD0, Offset 14h),
12-5
Synchronous Serial Transmit 1 (SSD1, Offset 14h),
12-5
Timer 0 Count (T0CNT, Offset 50h), 9-6
Timer 0 Interrupt Control (T0INTCON, Offset 32h),
8-30
Timer 0 Maxcount Compare A (T0CMPA, Offset
52h), 9-7
Timer 0 Maxcount Compare B (T0CMPB, Offset
54h), 9-7
Timer 0 Mode and Control (T0CON, Offset 56h), 9-3
Timer 1 Count (T1CNT, Offset 58h), 9-6
Timer 1 Interrupt Control (T1INTCON, Offset 38h),
8-30
Timer 1 Maxcount Compare A (T1CMPA, Offset
5Ah), 9-7
S
S/M bit (Slave/Master), 4-4
S2-S0 signals (Bus Cycle Status 2-0), 3-13
S4-S0 field (Poll Status)
Poll Register, 8-27
Poll Status Register, 8-26
S4-S0 field (Source Vector Type), 8-28
S6 signal (Bus Cycle Status 6), 3-13
SCLK signal (Serial Clock), 3-14
SD field (Send Data), 12-5
SDATA signal (Serial Data), 3-14
SDEC bit (Source Decrement), 10-4
SDEN1-SDEN0 signals (Serial Data Enables 1-0), 3-14
Segment registers, 2-1, 2-8
SELECT signal (Slave Select), 3-5
Serial port, 1-7
Serial Port Baud Rate Divisor Register, 11-7
Serial Port Control Register, 11-2
Serial Port Interrupt Control Register
Master mode, 8-20
Serial Port Receive Data Register, 11-6
Serial Port Status Register, 11-4
Timer 1 Maxcount Compare B (T1CMPB, Offset
5Ch), 9-7
Timer 1 Mode and Control (T1CON, Offset 5Eh), 9-3
Timer 2 Count (T2CNT, Offset 60h), 9-6
Timer 2 Interrupt Control (T2INTCON, Offset 3Ah),
8-30
Serial Port Transmit Data Register, 11-5
SF bit (Sign Flag)
Processor Status Flags Register, 2-3
SFNM bit (Special Fully Nested Mode), 8-14
Show read enable, 6-2
Timer 2 Maxcount Compare A (T2CMPA, Offset
62h), 9-7
Sign Flag bit, 2-3
Timer 2 Mode and Control (T2CON, Offset 66h), 9-5
Timer Interrupt Control (TCUCON, Offset 32h), 8-18
Upper Memory Chip Select (UMCS, Offset A0h), 5-4
Watchdog Timer Interrupt Control (WDCON, Offset
42h), 8-19
Signal description
A1 (Latched Address Bit 1), 3-8
A19-A0 (Address Bus), 3-1
A2 (Latched Address Bit 2), 3-9
AD15-AD8 (Address and Data Bus), 3-2
AD7-AD0 (Address and Data Bus), 3-1
ADEN (Address Enable), 3-3, 3-12
ALE (Address Latch Enable), 3-2
AO15-AO7 (Address-Only Bus), 3-2
ARDY (Asynchronous Ready), 3-3
BHE (Bus High Enable), 3-3
CLKOUTA (Clock Output A), 3-4
CLKOUTB (Clock Output B), 3-4
CLKSEL1 (Clock Select 1), 3-13
CLKSEL2 (Clock Select 2), 3-15
RES signal (Reset)
definition, 3-12
interrupt controller conditions, 8-9
Reset Configuration Register, 4-5
Return from interrupt, 8-4
RFSH signal (Automatic Refresh), 3-7
RFSH2 signal (Refresh 2), 3-12
RIU bit (Register in Use)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
I-8
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
DEN (Data Enable), 3-4
Special fully nested mode, 8-12
DRQ1-DRQ0 (DMA Requests), 3-4
DT/R (Data Transmit or Receive), 3-4
HLDA (Bus Hold Acknowledge), 3-4
HOLD (Bus Hold Request), 3-5
IMDIS (Internal Memory Disable), 3-13
INT0 (Maskable Interrupt Request 0), 3-5
INT1 (Maskable Interrupt Request 1), 3-5
INT2 (Maskable Interrupt Request 2), 3-6
INT3 (Maskable Interrupt Request 3), 3-6
INT4 (Maskable Interrupt Request 4), 3-6
INTA0 (Interrupt Acknowledge 0), 3-6
INTA1 (Interrupt Acknowledge 1), 3-6
IRQ (Slave Interrupt Request), 3-6
LCS (Lower Memory Chip Select), 3-7
MCS2-MCS0 (Midrange Memory Chip Selects 2-0),
3-7
MCS3 (Midrange Memory Chip Select 3), 3-7
NMI (Nonmaskable Interrupt), 3-7
ONCE0 (ONCE Mode Request 0), 3-7
ONCE1 (ONCE Mode Request 1), 3-15
PCS30-PCS0 (Peripheral Chip Selects 3-0), 3-8
PCS5 (Peripheral Chip Select 5), 3-8
PCS6 (Peripheral Chip Select 6), 3-8
PIO31-PIO0 (Programmable I/O Pins 31-0), 3-9
RD (Read Strobe), 3-12
Specific End-of-Interrupt Register
Slave mode, 8-36
SPI bit (Serial Port Interrupt In-Service), 8-23
SPI bit (Serial Port Interrupt Mask), 8-25
SPI bit (Serial Port Interrupt Request), 8-22
SR field (Receive Data), 12-6
SR field (Show Read)
Internal Memory Chip Select Register, 6-3
SRDY signal (Synchronous Ready), 3-14
SREN signal (Show Read Enable), 3-13
ST bit (Start/Stop DMA Channel), 10-4
Stack pointer register, 2-1
Stack Segment (SS) Register, 2-8
Status and control registers, 2-1
STP bit (Stop Bits), 11-3
String data type, 2-9
Support products, 1-8
SYN1-SYN0 field (Synchronization Type), 10-4
Synchronous Serial Control Register, 12-4
Synchronous Serial Receive Register, 12-6
Synchronous Serial Status Register, 12-3
Synchronous Serial Transmit 0 Register, 12-5
Synchronous Serial Transmit 1 Register, 12-5
System clocks, 3-25
RES (Reset), 3-12
RFSH (Automatic Refresh), 3-7
RFSH2/ADEN (Refresh 2/Address Enable), 3-12
RXD (Receive Data), 3-12
S2-S0 (Bus Cycle Status 2-0), 3-13
S6 (Bus Cycle Status 6), 3-13
SCLK (Serial Clock), 3-14
SDATA (Serial Data), 3-14
SDEN1-SDEN0 (Serial Data Enables 1-0), 3-14
SELECT (Slave Select), 3-5
T
T4-T0 field (Interrupt Type), 8-37
T8-T0 field (Refresh Count), 7-2
TC bit (Terminal Count), 10-4
TC15-TC0 field (Timer Compare Value), 9-7
TC15-TC0 field (Timer Count Register), 10-5
TC15-TC0 field (Timer Count Value), 9-6
TDATA field (Transmit Data), 11-5
SRDY (Synchronous Ready), 3-14
SREN (Show Read Enable), 3-13
TMRIN0 (Timer Input 0), 3-14
TMRIN1 (Timer Input 1), 3-15
TMROUT0 (Timer Output 0), 3-15
TMROUT1 (Timer Output 1), 3-15
TXD (Transmit Data), 3-15
UCS (Upper Memory Chip Select), 3-15
UZI (Upper Zero Indicate), 3-15
WB (Write Byte), 3-16
TDRQ bit (Timer Enable/Disable Request), 10-4
TEMT bit (Transmitter Empty), 11-4
TF bit (Trace Flag)
Processor Status Flags Register, 2-3
Thermal characteristics, xiv
WHB (Write High Byte), 3-16
Third-party
WLB (Write Low Byte), 3-16
WR (Write Strobe), 3-17
development, 1-8
products, xiv
X1 (Crystal Input), 3-17
X2 (Crystal Output), 3-17
THRE bit (Transmit Holding Register Empty), 11-4
Timer 0 Count Register, 9-6
SINC bit (Source Increment), 10-4
Timer 0 Interrupt Control Register
Slave mode, 8-30
Slave mode
interrupts, 8-29
nesting, 8-29
Timer 0 Maxcount Compare A Register, 9-7
Timer 0 Maxcount Compare B Register, 9-7
Timer 0 Mode and Control Register, 9-3
SM/IO bit (Source Address Space Select), 10-3
Software interrupt, 8-2
Index
I-9
Download from Www.Somanuals.com. All Manuals Search And Download.
Timer 1 Count Register, 9-6
W
Timer 1 Interrupt Control Register
Slave mode, 8-30
Wait-state programming, 5-2
Watchdog Timer Interrupt Control Register
Master mode, 8-19
Timer 1 Maxcount Compare A Register, 9-7
Timer 1 Maxcount Compare B Register, 9-7
Timer 1 Mode and Control Register, 9-3
Timer 2 Count Register, 9-6
WB signal (Write Byte), 3-16
WD bit (Watchdog Timer Interrupt In-Service), 8-23
WD bit (Watchdog Timer Interrupt Mask), 8-25
WD bit (Watchdog Timer Interrupt Request), 8-22
Website, xiv
Timer 2 Interrupt Control Register
Slave mode, 8-30
Timer 2 Maxcount Compare B Register, 9-7
Timer 2 Mode and Control Register, 9-5
WHB signal (Write High Byte), 3-16
WLB signal (Write Low Byte), 3-16
WLGN bit (Word Length), 11-3
TImer Interrupt Control Register
Master mode, 8-18
WR signal (Write Strobe), 3-17
Times Four mode, 3-23
Times One mode, 3-23
Timing characteristics, xiv
X
TMODE bit (Transmit Mode), 11-3
TMR bit (Timer Interrupt In-Service), 8-23
TMR bit (Timer Interrupt Mask), 8-25
TMR bit (Timer Interrupt Request), 8-22
TMR0 bit (Timer 0 Interrupt In-Service), 8-33
TMR0 bit (Timer 0 Interrupt Mask), 8-35
TMR0 bit (Timer 0 Interrupt Request), 8-32
TMR2-TMR0 field (Timer Interrupt Request), 8-21, 8-31
X1 signal (Crystal Input), 3-17
X2 signal (Crystal Output), 3-17
Z
ZF bit (Zero Flag)
Processor Status Flags Register, 2-3
TMR2-TMR1 field (Timer 2/Timer 1 Interrupt In-
Service), 8-33
TMR2-TMR1 field (Timer 2/Timer 1 Interrupt Mask), 8-
35
TMRIN0 signal (Timer Input 0), 3-14
TMRIN1 signal (Timer Input 1), 3-15
TMROUT0 signal (Timer Output 0), 3-15
TMROUT1 signal (Timer Output 1), 3-15
Trace Flag bit, 2-3
Trace interrupt, 8-6
TRM2-TMR1 field (Timer2/Timer1 Interrupt Request),
8-32
TXD signal (Transmit Data), 3-15
TXIE bit (Transmit Holding Register Empty Interrupt
Enable), 11-2
U
UB2-UB0 field (Upper Boundary)
Low Memory Chip Select Register, 5-6
UCS signal (Upper Memory Chip Select), 3-15
Upper Memory Chip Select Register, 5-4
UZI signal (Upper Zero Indicate), 3-15
I-10
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
|