INTEGRATED CIRCUITS
DATA SHEET
SAA7345
CMOS digital decoding IC with
RAM for Compact Disc
1998 Feb 16
Product specification
Supersedes data of 1996 Jan 09
File under Integrated Circuits, IC01
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
BLOCK DIAGRAM
V
V
V
V
V
V
DD1
DD2
DDA
SSA
SS1
16
SS2
43
11
12
15
44
HFIN
8
22
23
MOTO1
MOTO2
DIGITAL
PLL
MOTOR
CONTROL
HFREF
ISLICE
9
7
PLL
FRONT-
END
EFM
DEMODULATOR
IREF
10
ERROR
CORRECTOR
TEST1
TEST2
6
CFLG
33
FLAGS
5
SRAM
13
CRIN
AUDIO
PROCESSOR
CROUT 14
CL11
1
RAM
ADDRESSER
TIMING
SAA7345
EBU
INTER-
FACE
CLA 29
CL16 17
2
DOBM
Q - CHANNEL
CRC CHECK
21 SCLK
WCLK
PEAK
DETECT
Q - CHANNEL
REGISTER
CL 31
DA 30
SERIAL
DATA
INTER-
FACE
20
MICRO-
CONTROLLER
INTERFACE
19 DATA
18 MISC
RAB 32
VERSATILE PINS
INTERFACE
KILL
PORE 28
3
4
26
V3
25
V4
24
V5
27
KILL
MGA371 - 2
V1
V2
Fig.1 Block diagram.
1998 Feb 16
3
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
PINNING
SYMBOL
CL11
PIN
DESCRIPTION
1
11.2896 or 5.6448 MHz clock output (3-state); (divide-by-3)
bi-phase mark output (externally buffered; 3-state)
versatile input pin
DOBM
V1
2
3
V2
4
versatile input pin
TEST2
TEST1
ISLICE
HFIN
HFREF
IREF
VDDA
VSSA
CRIN
CROUT
VDD1
VSS1
5
test input; this pin should be tied LOW
test input; this pin should be tied LOW
current feedback output from data slicer
comparator signal input
6
7
8
9
comparator common-mode input
reference current pin (nominally 1⁄2VDD)
analog supply voltage; note 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
analog ground; note 1
crystal/resonator input
crystal/resonator output
digital supply to input and output buffers; note 1
digital ground to input and output buffers; note 1
16.9344 MHz system clock output
general purpose DAC output (3-state)
serial data output (3-state)
CL16
MISC
DATA
WCLK
SCLK
MOTO1
MOTO2
V5
word clock output (3-state)
serial bit clock output (3-state)
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
versatile output pin
V4
versatile output pin
V3
versatile output pin (open-drain)
kill output; programmable (open-drain)
power-on reset enable input (active LOW)
4.2336 MHz microcontroller clock output
interface data I/O line
KILL
PORE
CLA
DA
CL
interface clock input line
RAB
interface R/W and acknowledge input
correction flag output (open-drain)
CFLG
n.c.
34 to 42 no internal connection
VSS2
43
44
digital ground to internal logic; note 1
digital supply voltage to internal logic; note 1
VDD2
Note
1. All supply pins must be connected to the same external power supply.
1998 Feb 16
4
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Pins 34 to 42 (inclusive)
have no internal connection
CL11
DOBM
V1
1
2
3
4
5
6
7
8
9
33 CFLG
32
RAB
31 CL
30 DA
29 CLA
V2
TEST2
TEST1
ISLICE
HFIN
28
PORE
SAA7345
27 KILL
26 V3
25 V4
24 V5
HFREF
IREF 10
11
23
V
MOTO2
DDA
MGA359 - 1
Fig.2 Pin configuration.
1998 Feb 16
5
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two microcontroller
control registers (addresses 1000 and 1001) for
bandwidth and equalization.
FUNCTIONAL DESCRIPTION
Demodulator
FRAME SYNC PROTECTION
This circuit will detect the frame synchronization signals.
Two synchronization counters are used in the SAA7345:
For certain applications an off-track input is necessary. If
this flag is HIGH, the SAA7345 will assume that the servo
is following on the wrong track, and will flag all incoming
HF data as incorrect. The off-track is input via the V1 pin
when the versatile pins interface register (address 1100)
bit 0 is set to logic 1.
1. The coincidence counter which is used to detect the
coincidence of successive syncs. It generates a Sync
coincidence signal if 2 syncs are 588 ±1 EFM clocks
apart.
2. The main counter is used to partition the EFM signal
into 17-bit words. This counter is reset when:
EFM demodulation
a) A Sync coincidence is generated.
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
b) A sync is found within ±6 EFM clocks of its
expected position.
Subcode data processing
The Sync coincidence signal is also used to generate the
Lock signal which will go active HIGH when 1 Sync
coincidence is found. It will reset to LOW when, during 61
consecutive frames, no Sync coincidence is found. This
Lock signal is accessed via the status signal when the
status control register (address 0010) is set to X100. See
section on “Microcontroller interface” .
Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. Sixteen bits are used to perform a Cyclic
Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the status signal when the status control
register (address 0010) is set to X000 (normal reset
condition). Good Q-channel data may be read via the
microcontroller interface.
Data Slicer and Clock Regenerator
The SAA7345 has an integrated slice level comparator
which is clocked by the crystal frequency clock. The slice
level is controlled by an internal current source applied to
an external capacitor under the control of the digital
phase-locked loop (DPLL).
crystal
clock
2.2 kΩ
HFIN
HF
input
2.2 nF
47 pF
22 nF
D
Q
HFREF
DPLL
22 kΩ
1/2V
DD
I
ref
100 µA
V
V
SS
SSA
ISLICE
100 nF
V
DD
MGA368 - 1
100 µA
V
SSA
Fig.3 Data slicer showing typical application components.
6
1998 Feb 16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
OTHER SUBCODE CHANNELS
Write operation sequence
Data of the other subcode channels (Q-to-W) may be read
via the V4 pin if the versatile pins interface register
(address 1101) is set to XX01.
• RAB is held LOW by the microcontroller to hold the
SAA7345 DA pin at high-impedance.
• Microcontroller data is clocked into the internal shift
register on the LOW-to-HIGH clock transition CL.
The format is similar to RS232. The subcode sync word is
formed by a pause of 200 µs minimum. Each subcode byte
starts with a logic 1 followed by 7 bits (Q-to-W). The gap
between bytes is variable between 11.3 µs and 90 µs.
• Data D (3 : 0) is latched into the appropriate control
register [address bits A (3 : 0)] on the LOW-to-HIGH
transition of RAB with CL HIGH.
• If more data is clocked into SAA7345 before the
LOW-to-HIGH transition of RAB then only the last 8 bits
are used.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
Microcontroller interface
• If less data is clocked into SAA7345, unpredictable
operation will result.
The SAA7345 has a 3-line microcontroller interface which
is compatible with the digital servo IC TDA1301.
• If the LOW-to-HIGH transition of RAB occurs with CL
LOW, the command will be disregarded.
WRITING DATA TO SAA7345
The SAA7345 has thirteen 4-bit programmable
configuration registers as shown in Table 2. These can be
written to via the microcontroller interface using the
protocol shown in Fig.5.
200 µs
min
11.3
µs
11.3 µs min
90 µs max
W96
1
Q1
R1
S1
T1
U1
V1 W1
1
Q2
MGA369
Fig.4 Subcode format and timing at V4 pin.
RAB
(microcontroller)
CL
(microcontroller)
DA
A3
A2
A1
A0
D3
D2
D1
D0
(microcontroller)
DA (SAA7345)
high impedance
MGA379 - 1
Fig.5 Microcontroller WRITE timing.
7
1998 Feb 16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
WRITING DATA TO SAA7345; REPEAT MODE
The same command can be repeated several times (e.g. for fade function) by applying extra RAB pulses as shown in
Fig.6.
RAB
(microcontroller)
CL
(microcontroller)
DA
A3
A2
A1
A0
D3
D2
D1
D0
(microcontroller)
DA (SAA7345)
high impedance
MGA380 - 1
Note that CL must stay HIGH between RAB pulses.
Fig.6 Microcontroller WRITE timing; repeat mode.
READING STATUS INFORMATION FROM SAA7345
There are several internal status signals which can be made available on the DA line (Table 1).
Table 1 Internal status signals.
SIGNAL
DESCRIPTION
SUBQREADY-I LOW if new subcode word is ready in Q-channel register.
MOTSTART1
MOTSTART2
MOTSTOP
PLL Lock
V1
HIGH if motor is turning at 75% or more of nominal speed.
HIGH if motor is turning at 50% or more of nominal speed.
HIGH if motor is turning at 12% or less of nominal speed.
HIGH if Sync coincidence signals are found.
Follows input on V1 pin.
V2
Follows input on V2 pin.
MOTOR-OV
HIGH if the motor servo output stage saturates.
The status signal to be output is selected by status control register (address 0010). The timing for reading the status
signal is shown in Fig.7.
Status read operation sequence
• Write appropriate data to register 0010 to select required status signal.
• With RAB LOW; set CL LOW.
• Set RAB HIGH; this will instruct the SAA7345 to output status signal on DA.
1998 Feb 16
8
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
RAB
(microcontroller)
CL
(microcontroller)
DA
(microcontroller)
high impedance
DA (SAA7345)
STATUS
MGA381 - 1
Fig.7 SAA7345 status READ timing.
READING Q-CHANNEL SUBCODE FROM SAA7345
To read Q-channel subcode from SAA7345, the SUBQREADY-I signal should be selected as status signal. The subcode
read timing is shown in Fig.8.
Read subcode operation sequence
• Monitor SUBQREADY-I status signal.
• When this signal is LOW, and up to 2.3 ms after its LOW-to-HIGH transition, it is permitted to read subcode.
• Set CL LOW, SAA7345 will output first subcode bit (Q1).
• After subcode read starts, the microcontroller may take as long as it wants to terminate read operation.
• SAA7345 will output consecutive subcode bits after each HIGH-to-LOW transition of CL.
• When enough subcode has been read (1 to 96 bits), stop reading by pulling RAB LOW.
RAB
(microcontroller)
CL
(microcontroller)
CRC
OK
DA (SAA7345)
Q1
Q2
Q3
Qn–2 Qn–1 Qn
MGA382 - 1
STATUS
Fig.8 SAA7345 Q-channel subcode READ timing.
PEAK DETECTOR OUTPUT
In place of the CRC-bits (bits 81 to 96), the peak detector information is added to the Q-channel data. The peak
information corresponds to the highest audio level (absolute value) and is measured on positive peaks. Only the most
significant 8 bits of the peak level are given, in unsigned notation. Bits 81 to 88 contain the LEFT peak value
(bit 88 = MSB) and bits 89 to 96 contain the RIGHT channel (bit 96 = MSB). Value is reset after reading Q-channel data.
1998 Feb 16
9
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
BEHAVIOUR OF THE SUBQREADY-I SIGNAL
SHARING THE MICROCONTROLLER INTERFACE
When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I signal will react
as shown in Fig.9.
When the RAB pin is held LOW by the microcontroller, it is
permitted to put any signal on the DA and CL lines
(SAA7345 will set output DA to high-impedance). Under
this circumstance these lines may be used for another
purpose (e.g. TDA1301 microcontroller interface Data and
Clock line, see Fig.11).
When the CRC is good and subcode is being read, the
timing in Fig.10 applies.
If t1 (SUBQREADY-I LOW to end of subcode read) is
below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontroller
can read all subcode frames if it completes the read
operation within 2.6 ms after subcode ready).
If this criterion is not met, it is only possible to guarantee
that t3 will be below 26.2 ms (approximately).
If subcode frames with failed CRCs are present, the t2 and
t3 times will be increased by 13.1 ms for each defective
subcode frame.
RAB
(microcontroller)
CL
(microcontroller)
high
DA (SAA7345)
CRC OK
CRC OK
impedance
MGA373 - 1
10.8 ms
15.4 ms
2.3
ms
READ start allowed
Fig.9 SUBQREADY-I timing when no subcode is read.
t
2
t
t
1
3
RAB
(microcontroller)
CL
(microcontroller)
DA (SAA7345)
Q1
Q2
Q3
Qn
MGA374 - 1
Fig.10 SUBQREADY-I timing when subcode is being read.
1998 Feb 16
10
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
TDA1301
SAA7345
I/O
O
O
O
MICROCONTROLLER
MGA361 - 1
Fig.11 SAA7345 microcontroller interface application diagram.
Table 2 Command registers.
The ‘INITIAL’ column shows the power-on reset state
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
Fade and Attenuation
0 0 0 0
X 0 0 0
X 0 1 X
X 0 0 1
X 1 0 0
X 1 0 1
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1
X 1 0 0
X 1 0 1
Mute
Reset
Attenuate
Full Scale
Step Down
Step Up
Motor mode
0 0 0 1
Motor off mode
Reset
Motor brake mode 1
Motor brake mode 2
Motor start mode 1
Motor start mode 2
Motor jump mode
X 1 1 1 Motor play mode
X 1 1 0
1 X X X
0 X X X
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1
X 1 0 0
X 1 0 1
X 1 1 0
Motor jump mode 1
anti-windup active
anti-windup off
Reset
Reset
Status control
0 0 1 0
status = SUBQREADY-I
status = MOTSTART1
status = MOTSTART2
status = MOTSTOP
status = PLL Lock
status = V1
status = V2
X 1 1 1 status = MOTOR-OV
0 X X X
1 X X X
L channel first at DAC (WCLK normal)
R channel first at DAC (WCLK inverted)
Reset
1998 Feb 16
11
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
REGISTER
DAC output
ADDRESS
DATA
FUNCTION
I2S CD-ROM mode
INITIAL
0 0 1 1
1 0 1 0
1 0 1 1
1 1 0 X
1 1 1 1
1 1 1 0
0 0 0 X
0 0 1 1
0 0 1 0
0 1 0 X
0 1 1 1
0 1 1 0
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 1
X 1 0 0
X 1 0 1
X 1 1 0
EIAJ; CD-ROM mode
I2S; 4fs mode
I2S; 2fs mode
Reset
I2S; fs mode
EIAJ; 16-bit; 4fs
EIAJ; 16-bit; 2fs
EIAJ; 16-bit; fs
EIAJ; 18-bit; 4fs
EIAJ; 18-bit; 2fs
EIAJ; 18-bit; fs
Motor gain
0 1 0 0
Motor gain G = 3.2
Motor gain G = 4.0
Motor gain G = 6.4
Motor gain G = 8.0
Motor gain G = 12.8
Motor gain G = 16.0
Motor gain G = 25.6
Reset
X 1 1 1 Motor gain G = 32.0
Motor bandwidth
0 1 0 1
X X 0 0
X X 0 1
X X 1 0
Motor f4 = 0.5 Hz
Motor f4 = 0.7 Hz
Motor f4 = 1.4 Hz
Reset
X X 1 1 Motor f4 = 2.8 Hz
0 0 X X
0 1 X X
1 0 X X
X X 0 0
X X 0 1
X X 1 0
Motor f3 = 0.85 Hz
Reset
Reset
Motor f3 = 1.71 Hz
Motor f3 = 3.42 Hz
Motor output configuration
0 1 1 0
Motor power maximum 37%
Motor power maximum 50%
Motor power maximum 75%
X X 1 1 Motor power maximum 100%
0 0 X X
0 1 X X
1 0 X X
MOTO1, MOTO2 pins 3-state
Reset
Motor Pulse Width Modulation (PWM) mode
Motor Pulse Density Modulation (PDM) mode
1 1 X X Motor Compact Disc Video (CDV) mode
1998 Feb 16
12
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
REGISTER
ADDRESS
DATA
FUNCTION
INITIAL
Loop BW
(Hz)
Internal BW
(Hz)
Low-pass
BW (Hz)
PLL loop filter bandwidth
1 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 0 1
1 1 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
X X 0 0
X X 1 0
1640
3279
6560
1640
3279
6560
1640
3279
6560
1640
3279
6560
525
263
8400
16800
33600
8400
131
1050
525
16800
33600
8400
263
2101
1050
525
16800
33600
8400
Reset
4200
2101
1050
16800
33600
PLL loop filter equalization
1 0 0 1
PLL 30 ns over-equalization
PLL 15 ns over-equalization
PLL nominal equalization
Reset
PLL 15 ns under-equalization
PLL 30 ns under-equalization
EBU data before concealment
EBU output
1 0 1 0
EBU data after concealment and fade
Reset
Reset
Reset
X X 1 1 EBU off − output LOW
X 0 X X
X 1 X X
0 X X X
1 X X X
1 X X X
0 X X X
X 0 X X
X 1 X X
X X 0 0
X X 1 0
Level II clock accuracy (<1000 × 10−6)
Level III clock accuracy (>1000 × 10−6)
Flags in EBU off
Flags in EBU on
Speed control
1 0 1 1
double-speed mode
single-speed mode
Reset
Reset
33.869 MHz crystal present
16.934 MHz crystal present
standby 1: ‘CD-STOP’ mode (note 1)
standby 2: ‘CD-PAUSE’ mode (note 1)
Reset
X X 1 1 operating mode
Versatile pins interface
1 1 0 0
X X X 1
X X X 0
X X 0 X
X 0 1 X
off-track input at V1
no off-track input (V1 may be read via status)
Kill-L at KILL output, Kill-R at V3 output
V3 = 0; single Kill output
Reset
Reset
X 1 1 X V3 = 1; single Kill output
1998 Feb 16
13
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
REGISTER
ADDRESS
DATA
FUNCTION
4-line motor (using V4, V5)
INITIAL
Versatile pins interface
1 1 0 1
0 0 0 0
X X 0 1
X X 1 0
Q-to-W subcode at V4
V4 = 0
X X 1 1 V4 = 1
Reset
Reset
0 1 X X
1 0 X X
de-emphasis signal at V5
V5 = 0
1 1 X X V5 = 1
Note
1. Standby modes = CL, DA and RAB; normal operation.
a) MISC, SCLK, WCLK, DATA, CL11 and DOBM; 3-state.
b) CRIN, CROUT, CL16 and CLA; normal operation.
c) V1, V2, V3, V4 and V5; normal operation.
d) MOTO1 and MOTO2 - in standby 2 ‘CD-PAUSE’; normal operation.
e) MOTO1 and MOTO2 - in standby 1 ‘CD-STOP’; held LOW in PWM mode; 3-state in PDM mode.
Error corrector
Audio functions
The error corrector carries out t = 2, e = 0 error corrections
on both C1 (32 symbol) and C2 (28 symbol) frames. Four
symbols are used from each frame as parity symbols. The
strategy t = 2, e = 0 means that the error corrector can
correct two erroneous symbols per frame and detect all
erroneous frames.
DE-EMPHASIS AND PHASE LINEARITY
When de-emphasis is detected in the Q-channel subcode,
the digital filter automatically includes a de-emphasis filter
section. When de-emphasis is not required, a phase
compensation filter section controls the phase linearity of
the digital oversampling filter to ≤±1° within the band
0 to 16 kHz.
The error corrector also contains a flag controller. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read (after de-interleaving) by C2,
to help in the generation of C2 output flags.
DIGITAL OVERSAMPLING FILTER
The SAA7345 contains a 2 to 4 times oversampling filter.
The filter specification of the 4 × oversampling filter is
given in Table 2 and shown in Fig.12.
The C2 output flags are used by the interpolator for
concealment of non-correctable errors. They are also
output via the EBU signal (DOBM) and the MISC output
with I2S for CD-ROM applications.
These attenuations do not include the sample and hold at
the DAC output or the DAC post filter.
When using the oversampling filter, the output level is
scaled −0.5 dB down, to avoid overflow on full-scale
sinewave inputs (0 to 20 kHz).
The flags output pin CFLG provides information on the
state of all error correction and concealment flags.
1998 Feb 16
14
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Table 3 Digital filter passband characteristics
PASSBAND
ATTENUATION
0 to 19 kHz
≤ 0.001 dB
19 to 20 kHz
≤ 0.03 dB
Table 4 Digital filter stopband characteristics.
STOPBAND
24 kHz
ATTENUATION
≥ 25 dB
24 to 27 kHz
27 to 35 kHz
35 to 64 kHz
64 to 68 kHz
68 kHz
≥ 38 dB
≥ 40 dB
≥ 50 dB
≥ 31 dB
≥ 35 dB
69 to 88 kHz
≥ 40 dB
MGA385
20
magnitude
(dB)
0
20
40
60
0
10
20
30
40
50
frequency (kHz)
Fig.12 Digital filter characteristics.
CONCEALMENT
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The
erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels
have independent interpolators.
If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear
interpolation is then performed before the next good sample (see Fig.13).
1998 Feb 16
15
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
MGA372
Fig.13 Concealment mechanism.
To control the fade counter in a continuous way, the
step-up and step-down commands are available (fade
control register data X101 and X100). They will increment
or decrement the counter by 1 for each register write
operation.
MUTE, ATTENUATION AND FADE
A digital level controller is present on the SAA7345 which
performs the functions of soft mute, attenuation and fade.
Mute and Attenuation
• When issuing more than 1 step-up or step-down
command in sequence, the write repeat mode may be
used (see Fig.6).
Soft mute is activated by sending the Mute command to
the fade control register (address 0000, data X000). The
signal will reduced to zero in up to 128 steps (depending
on the current position of the fade control), taking a
maximum of 3 ms.
• A pause of at least 22 µs is necessary between any two
step-up or step-down commands.
• When a step-up command is given when the fade
counter is already at its full-scale value, the counter will
not increment.
Attenuation (−12 dB) is activated by sending the Attenuate
command to the fade control register (data X01X).
Attenuation and mute are cancelled by sending the Full
Scale command to the fade control register (data X001). It
will take 3 ms to ramp the output from mute to the full-scale
level.
DAC Interface
The SAA7345 is compatible with a wide range of
Digital-to-Analog Converters. Eleven formats are
supported and are shown in Table 5.
Fade
All formats are MSB first. fs is 44.1 kHz in single-speed
mode and 88.2 kHz in double-speed mode.
The audio output level is determined by the value of the
internal fade counter.
counter
Level =
× maximum level
----------------------
128
• The counter is preset to 128 by the Full Scale command
if no oversampling is required.
• The counter is preset to 120 (−0.5 dB scaling) by the Full
Scale command if either 2fs or 4fs oversampling is
programmed in the DAC output register (address 0011).
• The counter is preset to 32 by the Attenuate command.
• The counter is preset to 0 by the Mute command.
1998 Feb 16
16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Table 5 DAC interface formats
DAC CONTROL
REGISTER DATA FREQUENCY
SAMPLE
MODE
BITS
SCLK (MHz)
FORMAT
INTERPOLATION
1
2
1 0 1 0
1 0 1 1
1 1 1 0
0 0 1 0
0 1 1 0
0 0 0 X
0 1 0 X
1 1 0 X
0 0 1 1
0 1 1 1
1 1 1 1
fs
fs
16
16
16
16
18
16
18
18
16
18
18
2.1168 × n(1)
2.1168 × n(1)
2.1168 × n(1)
2.1168 × n(1)
2.1168 × n(1)
8.4672 × n(1) EIAJ − 16 bits
8.4672 × n(1) EIAJ − 18 bits
8.4672 × n(1) Philips I2S − 18 bits
4.2336 × n(1) EIAJ − 16 bits
4.2336 × n(1) EIAJ − 18 bits
4.2336 × n(1) Philips I2S − 18 bits
CD-ROM (I2S)
no
CD-ROM (EIAJ)(2)
Philips I2S − 16 bits
EIAJ − 16 bits
no
3
fs
yes
yes
yes
yes
yes
yes
yes
yes
yes
4
fs
5
fs
EIAJ − 18 bits
6
4fs
4fs
4fs
2fs
2fs
2fs
7
8
9
10
11
Note
1. n = disc speed.
2. EIAJ is the abbreviation for: Electronic Industries Associated of Japan.
1998 Feb 16
17
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SCLK
DATA
WCLK
0
15
0
15
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
MSB VALID
MISC
LSB VALID
LSB VALID
MSB VALID
CD-ROM
MGA383
MODE ONLY
Fig.14 Philips I2S data format (16-bit word length shown).
SCLK
DATA
0
17
0
17
LEFT CHANNEL DATA
WCLK
MISC
MGA384
Fig.15 EIAJ data format (18-bit word length shown).
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
EBU interface
The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the “IEC 958”
specification.
Three different modes can be selected via the EBU output control register (address 1010).
Table 6 EBU output modes
EBU CONTROL
REGISTER DATA
EBU OUTPUT AT DOBM PIN
DOBM pin held LOW
EBU VALIDITY FLAG (BIT 28)
X X 1 1
X X 0 0
−
data taken before concealment, mute and fade HIGH if data is non-correctable
(concealment flag)
X X 1 0
data taken after concealment, mute and fade
HIGH if data is non-correctable
(concealment flag)
FORMAT
The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (two transitions for a
logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 7).
Table 7 EBU word format
WORD
BITS
FUNCTION
Sync
0 to 3
4 to 7
4
−
Auxiliary
not used; normally zero
Error flags
CFLG error and interpolation flags when bit 3 of EBU control
register is set to logic 1
Audio sample
Validity flag
User data
8 to 27
28
first 4 bits not used (always zero)
valid = logic 0
29
used for subcode data (Q-to-W)
control bits and category code
even parity for bits 4 to 30
Channel status
Parity bit
30
31
SYNC
AUDIO SAMPLE
The sync word is formed by violation of the biphase rule
and therefore does not contain any data. Its length is
equivalent to 4 data bits. The three different sync patterns
indicate the following situations:
Left and right samples are transmitted alternately.
VALIDITY FLAG
Audio samples are flagged (bit 28 = logic 1) if an error has
been detected but was non-correctable. This flag remains
the same even if data is taken after concealment.
• Sync B:
– Start of a block (384 words), word contains left
sample.
USER DATA
• Sync M:
Subcode bits Q-to-W from the subcode section are
transmitted via the user data bit. This data is asynchronous
with the block rate.
– Word contains left sample (no block start).
• Sync W:
– Word contains right sample.
1998 Feb 16
19
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
CHANNEL STATUS
The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status
bits. The category code is always CD. The bit assignment is shown in Table 8.
Table 8 EBU channel status
WORD
BITS
FUNCTION
Control
0 to 3
copy of CRC checked Q-channel control bits 0 to 3;
bit 2 is logic 1 when copy permitted;
bit 3 is logic 1 when recording has pre-emphasis
Reserved mode
Category code
Clock accuracy
4 to 7
8 to 15
28 to 29
always zero
CD: bit 8 = logic 1; all other bits = logic 0
set by EBU control register:
00 = Level II
01 = Level III
Remaining
16 to 27 and 30 to 191 always zero
Several output modes are supported:
KILL circuit
1. Pulse Density, 2-line (true complement output), 1 MHz
sample frequency.
The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
before the digital filter. The output is switched active LOW
when silence has been detected for at least 200 ms. Two
modes are available, selected by the versatile pins register
(address 1100):
2. PWM output, 2-line, 22.05 kHz modulation frequency.
3. PWM-output, 4-line, 22.05 kHz modulation frequency.
4. CDV motor mode.
The modes are selected via the motor output configuration
register (address 0110).
1-PIN KILL MODE
Active LOW signal on KILL pin when digital silence has
been detected on both LEFT and RIGHT channels for
200 ms.
PULSE DENSITY MODE
In the Pulse Density mode the motor output pin MOTO1 is
the pulse density modulated motor output signal. A 50%
duty cycle corresponds with the motor not actuated, higher
duty cycles mean acceleration, lower mean braking.
2-PIN KILL MODE
Independent digital silence detection for left and right
channels. The KILL pin is active LOW when digital silence
has been detected in the LEFT channel for 200 ms, and V3
is active LOW when digital silence has been detected in
the RIGHT channel for 200 ms.
In this mode, the MOTO2 signal is the inverse of the
MOTO1 signal. Both signals change state only on the
edges of a 1 MHz internal clock signal.
Possible application diagrams are shown in Fig.16.
When MUTE is active then the KILL output is forced LOW.
Spindle motor control
The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±8 frame FIFO and disc speed information are used to
calculate the motor control output signals.
1998 Feb 16
20
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
22 kΩ
22 kΩ
MOTO1
+
MOTO2
+
–
M
–
10 nF
10 nF
V
SS
V
SS
V
DD
22 kΩ
22 kΩ
MOTO1
+
–
V
M
SS
22 kΩ
10 nF
22 kΩ
V
V
SS
SS
22 kΩ
V
DD
MGA363 - 1
Fig.16 Motor pulse density application diagrams.
PWM MODE, 2-LINE
In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the
motor braking signal is pulse-width modulated on the MOTO2 output.
Figure 17 shows the timing and Fig.18 a typical application diagram.
t
240 ns
t
= 45 µs
dead
rep
MOTO1
MOTO2
MGA366
Accelerate
Brake
Fig.17 Motor 2-line PWM mode timing.
+
M
10 Ω
100 nF
MOTO1
MOTO2
V
MGA365 - 2
SS
Fig.18 Motor 2-line PWM mode application diagram.
1998 Feb 16
21
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
PWM MODE, 4-LINE
Using two extra outputs from the Versatile Pins Interface, it is possible to use the SAA7345 with a 4-input motor bridge.
Figure 19 shows the timing and Fig.20 a typical application diagram.
t
= 45 µs
t
240 ns
rep
dead
MOTO1
MOTO2
V4
V5
MGA367 - 1
t
= 240 ns
ovl
Accelerate
Brake
Fig.19 Motor 4-line PWM mode timing.
+
V4
V5
M
10 Ω
100 nF
MOTO1
MOTO2
V
SS
MGA364 - 2
Fig.20 Motor 4-line PWM mode application diagram.
CDV MODE
In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency
300 Hz) and the PLL frequency signal will be put in pulse-density modulated form on the MOTO2 pin (carrier frequency
4.23 MHz). The integrated motor servo is disabled in this mode.
Remark:
The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position
(half-full) will result in a PWM output of 60%.
1998 Feb 16
22
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
OPERATION MODES
The motor servo has the operation modes as shown in Table 9 and is controlled by the motor mode register
(address 0001).
Table 9 Operation modes.
MODE
DESCRIPTION
Start mode 1
Disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved
and the PLL is reset. No disc speed information is available for the microcontroller.
Start mode 2
Jump mode
The disc is accelerated as in Start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to Jump mode. The motor status
signals are valid (register 0010).
Motor servo enabled but FIFO kept reset at 50%. The audio is muted but it is possible to read the
subcode.
Jump mode 1 Similar to Jump mode but motor integrator is kept at zero. Used for long jumps.
Play mode
FIFO released after resetting to 50%. Audio mute released.
Stop mode 1
Stop mode 2
Disc is braked by applying a negative voltage to the motor. No decisions are involved.
The disc is braked as in Stop mode 1, but the PLL will monitor the disc speed. As soon as the disc
reaches 12% of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor
servo to off mode.
Off mode
Motor not steered.
POWER LIMIT
FIFO OVERFLOW
In Start mode 1, Start mode 2, Stop mode 1 and Stop
mode 2, a fixed positive or negative voltage is applied to
the motor. This voltage can be programmed as a
percentage of the maximum possible voltage via the motor
output configuration register (address 0110) to limit
current drain during start and stop. The following power
limits are possible:
If FIFO overflow occurs during Play mode (e.g. as a result
of motor shock), the FIFO will be automatically reset
to 50% and the audio interpolator is activated to minimize
the effect of data loss.
• 100% of maximum (no power limit)
• 75% of maximum
• 50% of maximum
• 37% of maximum.
LOOP CHARACTERISTICS
The gain and cross-over frequencies of the motor control
loop can be programmed via the motor gain and bandwidth
registers (addresses 0100 and 0101). The possible
parameter values are as follows:
Gain: 3.2, 4.0, 6.4, 8.0 12.8, 16, 26.6 or 32.
Cross-over frequency, f4: −0.5, −0.7, −1.4 or −2.8 Hz.
Cross-over frequency, f3: −0.85, −1.71 or −3.42 Hz.
1998 Feb 16
23
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
MGA362 - 2
G
f
f
BW
f
4
3
Fig.21 Motor servo mode diagram.
Versatile pins interface
The SAA7345 has five pins that can be reconfigured for different applications as shown in Table 10.
Table 10 Versatile pins
CONTROL
REGISTER
ADDRESS
CONTROL
REGISTER
DATA
SYMBOL
PIN
TYPE
FUNCTION
V1
3
input
1 1 0 0
X X X 1
X X X 0
off-track input (from digital servo)
input may be read via status register
(address 0010 data X101)
V2
V3
4
input
−
−
input may be read via status register
(address 0010 data X110)
26
output
1 1 0 0
X X 0 X
X 0 1 X
X 1 1 X
0 0 0 0
X X 0 1
X X 1 0
X X 1 1
0 1 X X
1 0 X X
1 1 X X
kill output for right channel
output = logic 0
output = logic 1
V4
V5
25
24
output
output
1 1 0 1
1 1 0 1
4-line motor drive (using V4 and V5)
Q-to-W subcode output
output = logic 0
output = logic 1
de-emphasis output (active HIGH)
output = logic 0
output = logic 1
1998 Feb 16
24
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
Flags Output (CFLG) (open drain output)
A 1-bit flag signal is available at the CFLG pin. This signal shows the status of the error corrector and interpolator and is
updated every frame (7.35 kHz).
11.3
µs
45.4 µs
CFLG
F1
F2
F3
F4
F5
F6
F7
F1
MGA370
Fig.22 Flags output timing.
Table 11 Meaning of flag bits.
F1
F2
F3
F4
F5
F6
F7
MEANING
0
1
X
X
0
X
X
0
X
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
no absolute time sync
absolute time sync
X
X
X
X
X
X
X
X
X
X
X
X
C1 frame contained no errors
C1 frame contained 1 error
C1 frame contained 2 errors
C1 frame non-correctable
C2 frame contained no errors
C2 frame contained 1 error
C2 frame contained 2 errors
C2 frame non-correctable
no interpolations
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
0
1
1
X
X
X
X
X
X
X
X
0
1
at least one 1-sample interpolation
1
0
at least one hold and no interpolations
at least one hold and one 1-sample interpolation
1
1
ABSOLUTE TIME SYNC
Double speed mode
The first flag bit (F1) is the absolute time sync signal. It is
the FIFO-passed subcode-sync and relates the position of
the subcode-sync to the audio data (DAC output).
Double speed mode is programmed via the Speed control
register (address 1011). It is possible to program double
speed independent of clock frequency, but optimum
performance is achieved with a 33.8688 MHz crystal or a
ceramic resonator.
The flag may be used for special purposes such as
synchronization of different players.
FLAGS AT EBU OUTPUT
The CFLG flags are available on bit 4 of the EBU data
format when bit 3 of the EBU output control register
(address 1010) is set to logic 1.
1998 Feb 16
25
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
note 1
MIN.
−0.5
−0.5
−0.5
−
−40
−55
−2000
−200
MAX.
+6.5
UNIT
VDD
VI(max)
VO
supply voltage
V
V
V
maximum input voltage
output voltage
VDD + 0.5
+6.5
IO
output current (continuous)
operating ambient temperature
storage temperature
±20
+85
mA
°C
°C
V
Tamb
Tstg
Ves1
Ves2
+125
+2000
+200
electrostatic handling
electrostatic handling
note 2
note 3
V
Notes
1. All VDD and VSS connections must be made externally to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
IDD
supply voltage
supply current
3.4
5.0
5.5
V
VDD = 5 V
−
22
50
mA
Analog Front End (VDD = 4.5 to 5.5 V); comparator inputs HFIN and HFREF
fclk
Vth
clock frequency
8
−
−
35
MHz
V
switching thresholds
1.2
VDD − 0.4
Analog Front End (VDD = 3.4 to 5.5 V); comparator inputs HFIN and HFREF
fclk
clock frequency
8
−
1.0
20
MHz
V
Vtpt
HFIN input voltage level
−
−
Digital inputs CL and RAB
VIL
VIH
ILI
LOW level input voltage
−0.3
0.7VDD
−10
−
−
−
−
0.3VDD
VDD + 0.3
+10
V
HIGH level input voltage
input leakage current
input capacitance
V
VI = 0 to VDD
µA
pF
CI
−
10
1998 Feb 16
26
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs PORE, V1 and V2
Vthr
Vthf
Vhys
RPU
CI
switching threshold voltage rising
−
−
−
0.8VDD
V
V
V
switching threshold voltage falling
hysteresis voltage
0.2VDD
−
−
−
10
−
−
−
−
1
0.33VDD
input pull-up resistance
input capacitance
VI = 0 V
50
−
−
kΩ
pF
µs
trw
reset pulse width
PORE only
Digital outputs CL16 and CLA
VOL
VOH
CL
tr
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 1 mA
0
−
−
−
−
−
0.4
VDD
50
V
IOH = −1 mA
VDD − 0.4
V
−
−
−
pF
ns
ns
output rise time
CL = 20 pF; note 1
CL = 20 pF; note 1
15
tf
output fall time
15
Digital outputs V4 and V5
VOL LOW level output voltage
VDD = 4.5 to 5.5 V;
IOL = 10 mA
0
−
−
−
−
1.0
V
V
V
V
VDD = 3.4 to 5.5 V;
0
1.0
IOL = 5 mA
VOH
HIGH level output voltage
VDD = 4.5 to 5.5 V;
IOH = −10 mA
VDD − 1
VDD
VDD
V
DD = 3.4 V to 5.5 V; VDD − 1
IOH = −5 mA
CL
tr
load capacitance
output rise time
output fall time
−
−
−
−
−
−
50
15
15
pF
ns
ns
CL = 20 pF; note 1
CL = 20 pF; note 1
tf
Open-drain output CFLG
VOL
IOL
CL
tf
LOW level output voltage
IOL = 1 mA
0
−
−
−
−
0.4
2
V
LOW level output current
load capacitance
−
−
−
mA
pF
ns
50
30
output fall time
CL = 20 pF; note 1
IOL = 1 mA
Open-drain outputs KILL and V3
VOL
IOL
CL
tf
LOW level output voltage
LOW level output current
load capacitance
0
−
−
−
−
0.4
2
V
−
−
−
mA
pF
ns
50
15
output fall time
CL = 20 pF; note 1
1998 Feb 16
27
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
3-state outputs MISC, SCLK, WCLK, DATA and CL11
VOL
VOH
CL
tr
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 1 mA
0
−
−
−
−
−
−
0.4
V
V
IOH = −1 mA
VDD − 0.4
−
−
−
VDD
50
pF
ns
ns
µA
output rise time
CL = 20 pF; note 1
CL = 20 pF; note 1
VI = 0 to VDD
15
tf
output fall time
15
ILI
3-state leakage current
−10
+10
3-state outputs MOTO1, MOTO2 and DOBM
VOL
LOW level output voltage
HIGH level output voltage
VDD = 4.5 to 5.5 V;
IOL = 10 mA
0
−
−
−
−
1.0
V
V
V
V
VDD = 3.4 to 5.5 V;
0
1.0
IOL = 5 mA
VOH
VDD = 4.5 to 5.5 V;
IOH = −10 mA
VDD = 3.4 to 5.5 V;
VDD − 1
VDD − 1
VDD
VDD
I
OH = −5 mA
CL
tr
load capacitance
output rise time
−
−
−
−10
−
−
−
−
50
pF
ns
ns
µA
CL = 20 pF; note 1
CL = 20 pF; note 1
VI = 0 to VDD
10
tf
output fall time
10
ILI
3-state leakage current
+10
Digital input/output DA
VIL
VIH
ILI
LOW level input voltage
−0.3
0.7VDD
−
−
−
−
−
−
−
−
−
0.3VDD
VDD + 0.3
+10
10
V
HIGH level input voltage
3-state leakage current
input capacitance
V
VI = 0 to VDD
−10
−
µA
pF
V
CI
VOL
VOH
CL
tr
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 1 mA
0
0.4
IOH = −1 mA
VDD − 0.4
VDD
50
V
−
−
−
pF
ns
ns
output rise time
CL = 20 pF; note 1
CL = 20 pF; note 1
15
tf
output fall time
15
Crystal oscillator input CRIN (external clock)
gm
RO
CI
mutual conductance at start-up
output resistance at start-up
input capacitance
−
−
−
−10
4
−
−
10
+10
mS
kΩ
pF
11
−
−
ILI
input leakage current
µA
Crystal oscillator output CROUT (see Fig.26)
fxtal
Cfb
CO
crystal frequency
8
16.9344
35
5
MHz
pF
feedback capacitance
output capacitance
−
−
−
−
10
pF
1998 Feb 16
28
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
SYMBOL
I2S timing
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CLOCK OUTPUT SCLK (see Fig.23)
tcy
tH
tL
output clock period
clock HIGH time
clock LOW time
set-up time
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
−
−
−
472.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
236.2
118.1
−
−
−
−
−
−
−
−
−
−
−
−
166
83
42
166
83
42
95
48
24
95
48
24
tsu
th
hold time
I2S timing (double speed)
CLOCK OUTPUT SCLK (see Fig.23)
tcy
tH
tL
output clock period
clock HIGH time
clock LOW time
set-up time
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
sample rate = fs
sample rate = 2fs
sample rate = 4fs
−
−
−
236.2
118.1
59.1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83
42
21
83
42
21
48
24
12
48
24
12
tsu
−
−
−
−
th
hold time
−
1998 Feb 16
29
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Microcontroller interface timing (see Figs 24 and 25)
INPUTS CL AND RAB
tL
input LOW time
single speed
double speed
single speed
double speed
single speed
double speed
500
−
−
−
−
−
−
−
−
−
−
480
240
ns
ns
ns
ns
ns
ns
260
500
260
−
tH
input HIGH time
tr
tf
rise time
fall time
−
READ MODE
tdRD
delay time RAB to DA valid
0
0
−
−
50
50
ns
ns
tdRZ
delay time RAB to DA
high-impedance
tpd
propagation delay CL to DA
single speed
double speed
700
340
−
−
980
500
ns
ns
WRITE MODE
tsuD
set-up time DA to CL
hold time CL to DA
set-up time CL to RAB
single speed; note 2
−700
−
−
−
−
−
−
−
−
−
980
500
−
ns
ns
ns
ns
ns
ns
ns
double speed; note 2 −340
thD
single speed
double speed
single speed
double speed
−
−
260
140
50
tsuCR
−
−
tdWZ
delay time DA high-impedance
to RAB
Notes
1. Timing reference voltage levels are 0.8 V and VDD − 0.8 V.
2. Negative set-up time means that data may change after clock transition.
clock period t
cy
t
t
L
H
V
– 0.8 V
DD
SCLK
0.8 V
t
su
t
h
V
– 0.8 V
WCLK
DATA
MISC
DD
0.8 V
MGA376 - 1
Fig.23 I2S timing.
30
1998 Feb 16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
t
t
r
f
V
– 0.8 V
DD
RAB
CL
t
t
r
f
0.8 V
t
H
V
– 0.8 V
DD
t
dRD
0.8 V
t
dRZ
t
L
t
pd
V
– 0.8 V
DD
DA (SAA7345)
high impedance
0.8 V
MGA377 - 1
Fig.24 Microcontroller timing; READ mode.
t
t
t
r
H
f
V
– 0.8 V
t
DD
suCR
RAB
0.8 V
t
t
t
t
L
r
f
H
V
– 0.8 V
DD
0.8 V
CL
t
t
t
dWZ
L
hD
t
suD
V
– 0.8 V
DD
DA
(microcontroller)
MGA378 - 1
high impedance
0.8 V
Fig.25 Microcontroller timing; WRITE mode.
31
1998 Feb 16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
APPLICATION INFORMATION
CRIN
33.8688 MHz
(3rd overtone)
CRYSTAL
100
kΩ
3.3
µH
CROUT
2.2
kΩ
1 nF
10 pF
10 pF
33 pF
5 pF
V
DDA
V
SSA
CRIN
16.9344 MHz
CRYSTAL
100
kΩ
CROUT
2.2
kΩ
33 pF
V
DDA
V
SSA
CRIN
33.8688
CERAMIC
GENERATOR
100
kΩ
CROUT
2.2
kΩ
5 pF
V
DDA
V
SSA
MGA360 - 1
Fig.26 Application circuits for crystal oscillator.
1998 Feb 16
32
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
V
V
DD
R6
2.2 Ω
C12
4.7 µF
(63 V)
C13
100 nF
X8
44 43 42 41 40 39 38 37 36 35 34
11 MHz
clock output
V
DD2
CL11
1
2
3
33
32
31
CFLG
RAB
CL
to DOBM transformer
DOBM
V1
micro-
controller
interface
4
5
30
29
V2
DA
TEST2
CLA
6
7
8
9
28
27
26
25
24
23
TEST1
ISLICE
PORE
KILL
SAA7345
HFIN
V3
V4
R2
22 kΩ
HFREF
C2 47 pF
C3
10
11
IREF
V5
V
R3
2.2 kΩ
MOTO2
MOTOR
DDA
C4
100 nF
INTERFACE
X6
V
22 nF
(1)
SSA
MOTO1
HFIN
12 13 14 15 16 17 18 19 20 21 22
C1
2.2 nF
V
V
R4
2.2 Ω
DD
C6
4.7 µF
(63 V)
C11
100
nF
C7
100 nF
to DAC
X9
16 MHz
clock output
(2)
MGA375 - 1
(1) Diagram is for a 5 V application. For 3.4 V applications an additional resistor of 150 kΩ should be added between IREF (pin 10) and ground.
(2) For crystal oscillator circuit see Fig.26.
Fig.27 Typical SAA7345 application diagram.
1998 Feb 16
33
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
y
X
A
33
23
Z
34
22
E
e
A
H
2
E
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
44
12
detail X
1
11
Z
v
M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.25 2.3
0.05 2.1
0.50 0.25 14.1 14.1
0.35 0.14 13.9 13.9
19.2 19.2
18.2 18.2
2.0
1.2
2.4
1.8
2.4
1.8
mm
1
2.60
0.25
2.35
0.3 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT205-1
133E01A
1998 Feb 16
34
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering techniques are suitable for all QFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Feb 16
35
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Feb 16
36
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
NOTES
1998 Feb 16
37
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
NOTES
1998 Feb 16
38
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for
Compact Disc
SAA7345
NOTES
1998 Feb 16
39
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/00/05/pp40
Date of release: 1998 Feb 16
Document order number: 9397 750 03314
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