USER GUIDE
Tegra™ 200 Series Developer Board
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NVIDIA CONFIDENTIAL
January 2010 | DG-04927-001_v01
Tegra 200 Series Developer Board User Guide
Table of Contents
1.0 INTRODUCTION ....................................................................................................................................................................5
2.0 DEVELOPER BOARD OVERVIEW........................................................................................................................................6
2.1 Feature List ........................................................................................................................................................................6
2.2 NVIDIA® Tegra™ 250........................................................................................................................................................8
2.3 System DRAM....................................................................................................................................................................8
2.4 Boot Device........................................................................................................................................................................8
2.5 LCD Interface .....................................................................................................................................................................9
2.6 External Display Support....................................................................................................................................................9
2.7 Audio ..................................................................................................................................................................................9
2.8 USB....................................................................................................................................................................................9
2.9 Storage.............................................................................................................................................................................10
2.10 Camera (optional)...........................................................................................................................................................10
2.11 Wireless..........................................................................................................................................................................10
2.12 User Interface.................................................................................................................................................................11
2.13 Miscellaneous.................................................................................................................................................................11
2.14 Power .............................................................................................................................................................................11
3.0 SATELLITE BOARD HEADERS...........................................................................................................................................12
3.1 Satellite Board Headers....................................................................................................................................................13
3.2 I2C Map............................................................................................................................................................................14
4.0 CONNECTION EXAMPLES .................................................................................................................................................15
4.1 Power ...............................................................................................................................................................................15
4.1.1 Major Components ...................................................................................................................................................................... 16
4.1.2 Power Supplies............................................................................................................................................................................ 17
4.1.3 Power Sequencing ...................................................................................................................................................................... 18
4.1.4 Bypass Capacitor Recommendations ......................................................................................................................................... 19
4.1.5 Unused Interface Power Rails..................................................................................................................................................... 19
4.1.6 Unused Power Management Signals.......................................................................................................................................... 19
4.2 Clocks...............................................................................................................................................................................20
4.2.1 32.768KHz Clock......................................................................................................................................................................... 20
4.2.2 Oscillator Clock............................................................................................................................................................................ 20
4.3 DRAM Memory Configurations.........................................................................................................................................22
4.3.1 Four, 8-bit DDR2 devices ............................................................................................................................................................ 22
4.3.2 Eight, 8-bit DDR2 devices ........................................................................................................................................................... 22
4.3.3 Unused Pins ................................................................................................................................................................................ 23
4.4 NAND ...............................................................................................................................................................................24
4.5 USB..................................................................................................................................................................................24
4.5.1 Force Recovery ........................................................................................................................................................................... 25
4.5.2 ULPI............................................................................................................................................................................................. 25
4.5.3 PCIe............................................................................................................................................................................................. 26
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4.6 Display..............................................................................................................................................................................27
4.6.1 LCD Displays............................................................................................................................................................................... 27
4.6.2 HDMI ........................................................................................................................................................................................... 29
4.6.3 VGA (CRT) Out ........................................................................................................................................................................... 30
4.7 Camera.............................................................................................................................................................................31
4.7.1 Unused Pins ................................................................................................................................................................................ 31
4.8 SD/SDIO/MMC.................................................................................................................................................................32
4.8.1 SD/MMC Card Connections........................................................................................................................................................ 32
4.8.2 eMMC Device Connections......................................................................................................................................................... 33
4.8.3 SDIO Device Connections........................................................................................................................................................... 34
4.8.4 Unused Pins ................................................................................................................................................................................ 34
4.9 Miscellaneous...................................................................................................................................................................35
4.9.1 Thermal Diode (Temperature Sensor) ........................................................................................................................................ 35
4.9.2 Debug Interfaces ......................................................................................................................................................................... 35
4.9.3 EFUSE......................................................................................................................................................................................... 36
4.9.4 Strapping Pins ............................................................................................................................................................................. 37
5.0 THERMAL ............................................................................................................................................................................38
5.1 Major Component Thermal Specifications........................................................................................................................38
5.2 Thermal Considerations for Components.........................................................................................................................38
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Tegra 200 Series Developer Board User Guide
1.0 INTRODUCTION
The Smartbook Development System is an example of a development platform built around the Tegra™ 200 Series Developer
Board. This example provides a starting point for continued development; it outlines a fairly typical Smartbook configuration
based on the NVIDIA® Tegra™ 250 Computer-on-a-Chip.
This document:
ƒ
Provides recommendations and integration guidelines for engineers to follow when designing a Smartbook or similar
product that is optimized for high performance and low power consumption.
ƒ
Details a generic Smartbook Development System: development system consists of the NVIDIA® Tegra™ 200 Series
Developer Kit plus a satellite board containing most of the user input devices and some features for test and
development; can be used for evaluation and/or software development.
Figure 1. Example Smartbook Development System Block Diagram
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Tegra 200 Series Developer Board User Guide
2.0 DEVELOPER BOARD OVERVIEW
2.1 Feature List
Applications Processor
SD/SDIO and HSMMC
Standard SD/SDIO/MMC socket
ƒ
NVIDIA Tegra 250, 23x23mm ,0.8mm pitch
ƒ
DRAM and Flash Memory
USB and Ethernet
ƒ
ƒ
ƒ
ƒ
8, 128Mx8, DDR2 @ 333MHz
TPS51116RGET DDR2 Buck Regulator
Hynix 8-bit NAND on board
ƒ
SMSC LAN 9514 USB Hub and Ethernet
-
-
-
3 USB Type A Host ports
USB for PCIE MiniCard Slot 2
Ethernet RJ-45 Jack
Internal SD/MMC socket supports eMMC module
ƒ
ƒ
SMSC USB3315 ULPI PHY
USB for PCIE MiniCard Slot 1
USB Mini Type B connector for Recovery Mode
Baseband
-
ƒ
ƒ
USB based PCIe Mini Card Modules
USIM Card Connector
Buttons, Switches
Display
ƒ
Power-On, Reset and Force-Recovery Buttons
ƒ
ƒ
ƒ
LVDS Bridge: TI SN75LVDS83B
HDMI (Type A connector)
Slim 15-pin VGA Connector
Miscellaneous Devices
ƒ
ƒ
EC: SMSC MEC1308
Temperature Sensor: ADT7461AARMZ_RL7
Audio
ƒ
ƒ
ƒ
ƒ
Wolfson WM8903L Codec
Stereo Headphones
External and Internal Mics
Left/Right Speaker Amps.
Power
ƒ
ƒ
ƒ
PMIC: TI TPS658621AZGUR
Battery Charge Controller: TI BQ24745RHDR
Main system regulators
-
3.3V, 5V, 1.8V and 1.05V
Imaging
ƒ
ƒ
Other, lower power regulators
3.3V (standby), 1.2V and 1.5V
ƒ
Dual-lane MIPI CSI connection for camera module
Murata WiFi and Bluetooth module
Wireless
Debug / Test Features
22-pin Debug Connector
JTAG, UART and SPI
ƒ
ƒ
-
Bluetooth: CSR BC6
-
-
-
802.11b/g WiFi: Atheros 6002
Tegra Debug Module (optional)
This is an optional module that may have been shipped with
your Tegra 200 Series Developer Board depending on the
version of the development kit that was ordered.
ƒ
ƒ
ƒ
Power, Reset and Force-Recovery Buttons
Lid Open/Close slider switch
UART4 (4-pin UART) brought to RS232 DB9 serial
connector (intended for software test and debug)
Adds a coin cell battery for uninterrupted Real-Time
Clock operation when the developer board is
powered off
ƒ
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Tegra 200 Series Developer Board User Guide
Figure 2. Tegra 200 Series Developer Board (Top View)
VGA Conn
(J12)
HDMI
Conn
(J18)
LCD (J7)
AC/DC
Jack
(J15)
Camera (J9)
PCIE
Mini-
Mini-B
USB
WiFi Ant
(J24)
Card 0
(J27)
SIM Card
(J19)
SD/MMC
(J5)
Battery
Con
(J14)
PCIE
Mini-
Card 1
(J27)
PMU
(U7)
Tegra T20
(U4)
Ethernet
Jack (J4)
DDR2
(Rank 0)
USB Host
Port (J25)
Dual USB
Host Ports
(J6)
MMC VCORE (J20)
Headphn
Jack (J1)
Debug
Conn
(J10)
Internal
SD/MMC
(J26)
Mic Jack
(J2)
Right
Spkr
(J21)
Satellite
Headers
(J16, J17)
Force Rec
Button
(S2)
Int
Mic
(J8)
On
Button
(S1)
Reset
Button
(S3)
Left
Spkr
(J11)
Figure 3. Tegra 200 Series Developer Board (Bottom View)
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Tegra 200 Series Developer Board User Guide
2.2 NVIDIA® Tegra™ 250
The NVIDIA Tegra 250 computer-on-a-chip is suited for handheld and mobile applications. It’s primary purpose is to control all
system peripherals and provide computing power.
Table 1 Features (Available / Used on Tegra 200 Series Developer Board)
ƒ
Dual-core ARM® Cortex-A9 MPCore™ processor
CPU
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
32-bit 333MHz DDR2 SDRAM (to 1GB)
2 chip selects
Dynamic voltage and frequency scaling
Multiple clock and power domains
Independent gating of power domains
Integrated Open GLES 2.0 3D core
External Memory Support
Advanced Power Management
2D/3D acceleration
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
SPI (Qty 1), I2C (Qty 3), UART (Qty 2)
I2S/PCM (Qty 2)
ULPI HS
USB 2.0 HS (Qty 3)
SDIO (Qty 3)
Internal 4-bit SD/8-bit MMC
Connectivity and Expansion
Storage
o
eMMC compatible module available
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
External 4-bit MMC/SD
Dual Display (Integrated LCD + external)
18-bit LVDS LCD
HDMI to 1080p and VGA
Camera (CSI)
Multimedia Support
Pre/Post Processing Acceleration with ISP
MPEG-4/H264/JPEG Encoder
For more information on Tegra 250, refer to the Tegra 200 Series Datasheet (Electrical, Mechanical and
Thermal Specifications and the Design Guide.
Note:
2.3 System DRAM
The Tegra 200 Series Developer Board has 8 DDR2 128M x 8 devices for 1GB total system DRAM. The DDR2 will operate up
to 333MHz for a peak bandwidth of 2.7GB/s. The memory is arranged as one or two 32-bit Ranks. Each Rank uses a different
Chip Select and Clock Enable. For low power operation with memory retention, self refresh is supported.
2.4 Boot Device
A 4Gb (512MB) Hynix HY27UF084G2BTPCB 8-bit NAND is available for use as the boot device. In addition, an internal 4-bit
SD, 8-bit MMC socket (J26) is provided to support other flash memories.
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2.5 LCD Interface
The Smartbook Development System routes an 18-bit parallel RGB interface from the Tegra 250 to a Texas Instruments
SN75LVDS83B LVDS Transmitter which goes to an LVDS panel connector (J7). The connector is a Foxconn GS13307-11230-
7F.
The controls available for the panel and backlight include:
ƒ
Panel power provided by main 3.3V Buck regulator and enabled by the Tegra 250 GPIO on LCD_PWR2
(EN_VDD_PNL)
ƒ
ƒ
ƒ
Backlight enable controlled by the Tegra 250 GPIO on pin SDIO3_DAT2 (SDIO block)
Backlight PWM controlled by PM3_PWM0 on SDIO3_DAT3 (SDIO block)
Backlight power provided from VDD_VBAT (battery or AC/DC adapter) and enabled by the Tegra 250 GPIO on
LCD_CS1_N
ƒ
LVDS Transmitter shutdown enabled by Tegra 250 GPIO on pin LCD_PWR0
2.6 External Display Support
A standard HDMI Type A connector (J18) is provided and supports up to 1080p60Hz operation. The Tegra 200 Series
Developer Board supports Hot Plug Detect by routing the HP_DET line on the HDMI connector to the Tegra 250 HDMI_INT_N
interrupt pin. The DDC interface is shared between HDMI and the VGA interface, so only one of these displays can be
connected at a time.
A standard 15-pin VGA connector (J12) is also provided and supports resolutions up to 1600x1200. The Tegra 200 Series
Developer Board also supports detection of a VGA device connection. This uses the Tegra 250 pin SPI2_SCK on the Audio
block.
2.7 Audio
The Tegra 200 Series Developer Board integrates the Wolfson Microelectronics WM8903 Ultra Low Power CODEC for Portable
Audio Applications. The Tegra 250 DAP1 interface supporting I2S protocol communicates audio data to/from the CODEC.
GEN1_I2C is used for CODEC configuration. The audio subsystem features:
ƒ
Left and Right amplified speaker output via two Wolfson WM9001 amplifiers
Headers for connecting Left (J11)/Right (J21) speakers
-
ƒ
ƒ
Stereo headphone jack (J1)
Both internal Microphone (J8) and external microphone jack (J2)
2.8 USB
The Tegra 250 has three available USB controllers. Controllers #1 and #3 come out on the USB PHYs on the USB1 and USB3
pins. Controller #2 can be used for either ULPI or HSIC (only one at a time). All three USB controllers are used on the Tegra
200 Series Developer Board.
Controller #1
USB1 (PHY) is required for Recovery mode and so is brought out to a USB Mini B connector (J3). USB1 is configured as a
device to allow connection to a host PC, typically for flashing images at the factory or possibly in the field.
Controller #2
USB2 provides a ULPI interface on the Tegra 200 Series Developer Board and connects to an external USB3315 ULPI PHY.
The PHY then connects to PCIe Mini-Card 0 (J27) which is intended for a 3G baseband module.
Controller #3
USB3 (PHY) is routed to an SMSC LAN9514 USB Hub and Ethernet controller. This controller provides one Ethernet interface
and four USB Host ports. The Tegra 200 Series Developer Board routes the Ethernet signals to a standard RJ-45 jack. Three
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Tegra 200 Series Developer Board User Guide
of the USB ports are brought to standard Type A connectors (J6 – Dual host port connector and J25 – Single host port). The
forth USB is routed to PCIe Mini-Card #1 (J28).
2.9 Storage
There are two SD/MMC sockets on the Tegra 200 Series Developer Board. Both sockets support High Speed operation
(52MHz for MMC, 50MHz for SD/SDIO)
SD/MMC Socket 1 (J26)
The J26 SD/MMC socket is a combination 8-bit MMC and 4-bit SD/MMC socket intended to be for internal storage, most likely
an eMMC module. Although this device is in a socket, it is not meant to be used as removable storage in a real design. 3.3V is
supplied to the socket. There is also a 2-pin header (J5) to supply a core rail at 2.85V. This header is used when the eMMC
module is installed in this socket.
SD/MMC Socket 2 (J5)
The J5 SD/MMC Socket is a removable storage is a standard 4-bit SD/MMC socket. This would normally be located to allow
SD/MMC/SDIO cards to be inserted and removed by the user. 3.3V is supplied to this socket.
2.10 Camera (optional)
A socket for a camera module is provided on the Tegra 200 Series Developer Board (J9).
2.11 Wireless
Bluetooth and Wifi
The Tegra 200 Series Developer Board integrates a MuRata BT/WF Module using the CSR-BC6 and Atheros AR6002
controllers.
The Bluetooth 2.0 transceiver sends and receives on a 2.4GHz line, including Enhanced Data Rates (EDR) up to 3Mbps and
scatter-net support. USB and Dual UART Ports with rates up to 3MBaud are supported. It operates at full speed Bluetooth
operation with full piconet support and co-exists with 802.11. The CSR device will act as a serial peripheral when connected to
the Tegra 250 via a serial port. This interface, as with WiFi below, will be implemented on a substrate (typically LTCC) supplied
by MuRata containing all components required for operation, to minimize tuning and testing. An external antenna for 2.4GHz
(available off the shelf) is also required
The 802.11b/g transceiver sends and receives on a 2.4GHz line at 54Mbps max. It provides full QoS for 802.11e and security
support 802.11i and co-exists with the Bluetooth device. The interface of choice is SDIO. This interface will be implemented on
a LTCC substrate supplied by MuRata and soldered down to our board to minimize tuning and testing.
An external antenna supporting both Bluetooth and WiFi for 2.4GHz (available off the shelf) is required and available from a
variety of suppliers.
PCIe Mini-Card (3G Modem support and more)
The Tegra 200 Series Developer Board provides two PCIe Mini-Card slots. Both slots support PCIe operation as well as USB
2.0 High Speed. Slot #0 (J27) also routes to a UIM SIM socket (J19) and is intended to support compatible 3G Modem
modules. PCIe Mini-Card slot #1 (J28) could be used for other peripherals such as Solid-State drives or a different WiFi
solution.
Note:
Contact NVIDIA for list of certified PCI express peripherals
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2.12 User Interface
Attach your USB keyboard and mouse to any of the available USB Type-A Host ports (J6, J25).
2.13 Miscellaneous
Temperature Sensor
ƒ
ƒ
ƒ
ƒ
On Semiconductor Model ADT7461AARMZ_RL7
0.25°C resolution/1°C accuracy (remote channel used)
Interfaces to PWR_I2C
Programmable over/under temperature limits
Debug Options
The Tegra 200 Series Developer Board provides development/debugging interfaces including JTAG, UART and Ethernet.
The Tegra Debug Module [E1173] interfaces to the Tegra 200 Series Developer Board using the expansion headers. This
board provides:
ƒ
ƒ
ƒ
A UART interface through a RS232 DB9 serial connector (intended for software test and debug)
Remote POWER, RESET and FORCE RECOVERY buttons
Adds a coin cell battery for uninterrupted Real-Time Clock operation when the developer board is powered off
2.14 Power
Power Source
ƒ
ƒ
Battery: 3-Cell, Li Ion, 24WHr, 11.1V Nominal
AC/DC Adapter: TopMagnetics HK-HW30-A15, 15/30W
100V – 240V operation
-
Battery Charge Controller
ƒ
Texas Instruments BQ24745RHDR
PMU
ƒ
Texas Instruments TPS658621AZGUR
Dedicated DC/DCs
ƒ
ƒ
ƒ
Main system 3.3V and 5V rails: Texas Instruments TPS51220ARTVT
Main system 1.8V: Texas Instruments TPS51116RGER
PCIe 1.05V for the Tegra 250: Texas Instruments TPS62290DRVR
External LDOs
ƒ
1.2V: Texas Instruments TPS72012YZUT
ƒ
1.5V: Texas Instruments TPS74201RGWR
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3.0 SATELLITE BOARD HEADERS
Two dual row 50-pin expansion headers enable the ability to connect a satellite board to the Tegra 200 Series Developer Board
and are used to extend developer board functionality.
Figure 4. Example Satellite Board Block Diagram
Tegra 200 Series Developer
Board (E1162)
Additional Functionality
Wireless
Modules
LEDs (WPAN, WWAN, WLAN)
Coin
Cell
PMU
RESET
Button
LEDs (PWR, CHG, NUM,
CAPS, SCROLL, RF)
ONKEY
ONKEY
Button
RESET
I2C
PWR_I2C
ID
PROG
HDR
EEPROM
Tegra 2
PWR_I2C
UART4
RS-232
TRCV
DB9
CON
Tx, Rx, RTS, CTS
LID_Status
Switch
GPIO
GPIO
RF On/Off
Switch
ForceRecovery
Button
GMI_RE_N
CAM_I2C
16x8
18x8
KBC
Res
16x8
Mux
EC
KBC
C
GPIO
GPIO
HeartBeat
LED
or
I2C
Touchpad
PS/2
Touchpad
PS/2
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3.1 Satellite Board Headers
All the interface connections between a satellite board and the Tegra 200 Series Developer Board are through two sets of
Samtec FTS series 50-pin Micro Strips connectors.
Table 2. Satellite Connectors Pinout
Dir
Dir
Dir
Pin #
Signal Name
Signal Name
Pin #
Dir
Pin #
Signal Name
Signal Name
Pin #
In
1
KB_COL7
EC_KSO17
2
Out
Out
1
LED_WPAN*
VDD_CELL_RMT
2
In
In
3
KB_COL6
KB_COL5
EC_KSO16
EC_KSO15
EC_KSO14
EC_KSO13
EC_KSO12
EC_KSO11
EC_KSO10
EC_KSO9
EC_KSO8
EC_KSO7
EC_KSO6
EC_KSO5
EC_KSO4
EC_KSO3
EC_KSO2
EC_KSO1
EC_KSO0
EC_KSI7
4
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
Out
Out
In
3
5
LED_WLAN*
LED_WWAN*
W_DISABLE *
LED_WIFI_BT *
LED_CHARGE*
LED_POWER*
UART4_TXD
VDDIO_NAND_MB
UART4_RXD
UART4_CTS*
UART4_RTS*
NO CONNECT
FORCE_ACOK
VDDIO_SYS_MB
PWR_I2C_SCL
PWR_I2C_SDA
VDD_3V3_MB
VDD_3V3_MB
GND
4
Out
Out
In
In
5
6
6
In
7
KB_COL4
8
7
8
In
9
KB_COL3
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Out
Out
Out
Out
Out
Out
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
In
In
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
KB_COL2
11
13
Out
In
KB_COL1
In
KB_COL0
15 LED_SCROLL_LOCK*
In
Out
Bi
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
KB_ROW15
KB_ROW14
KB_ROW13
KB_ROW12
KB_ROW11
KB_ROW10
KB_ROW9
KB_ROW8
KB_ROW7
KB_ROW6
KB_ROW5
KB_ROW4
KB_ROW3
KB_ROW2
KB_ROW1
KB_ROW0
EC_KSI0
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
LED_CAPS_LOCK*
LED_NUM_LOCK*
GND
Bi
In
SPDIF_IN
Out
Out
Out
SPDIF_OUT
GND
Out
In
IR_TXD
PS2_TS_CLOCK
PS2_TS_DATA
GND
Bi
Bi
IR_RXD
In
LID_OPEN*
VDD_5V0_MB
VDD_5V0_MB
TP_IRQ*
Out
Out
In
CAM_I2C_SDA
CAM_I2C_SCL
GND
Bi
Bi
EC_KSI6
In
EC_KSI5
In
In
TS_IRQ*
PS2_TP_CLOCK
PS2_TP_DATA
Bi
EC_KSI4
In
NO CONNECT
ONKEY*
Bi
EC_KSI3
In
In
In
In
LED_HEARTBEAT* 46
Out
Out
Out
EC_KSI2
In
47 FORCE_RECOVERY*
49 RESET*
SYS_RESET_B*
48
50
EC_KSI1
In
VDD_3V3_EC_MB
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3.2 I2C Map
The I2C interface can be used to connect a touch screen, touch pad and other devices.
There are two options for the Touch devices. I2C versions of these devices (recommended) interface to the Tegra 250, while
PS/2 versions connect to the EC controller.
Table 3. Tegra 200 Series Developer Board I2C Map
Domain
VDDIO_VI
Contrlr
Pins
Volt.
Device
ID / I2C Addr
Location
Tegra 250 Slave addr:
0x45
I2C3
CAM_I2C_SCL/SDA
3.3V
MEC1308 (I2C Master)
Main Board
VDDIO_VI
I2C3
I2C3
I2C1
I2C1
CAM_I2C_SCL/SDA
CAM_I2C_SCL/SDA
GEN1_I2C_SCL/SDA
GEN1_I2C_SCL/SDA
3.3V
3.3V
1.8V
1.8V
Touchpad
0x28
TBD
Remote Location
Remote Location
Main Board
VDDIO_VI
Touchscreen
Camera
VDDIO_UART
VDDIO_UART
0x36
0x0C
Autofocus DAC
Main Board
Pack is Master or Slave
Slave addr: 0x0B
VDDIO_UART
I2C1
GEN1_I2C_SCL/SDA
3.3V
Option for SMB to Battery Pack
Main Board
VDDIO_UART
VDDIO_LCD
VDDIO_SYS
VDDIO_UART
VDDIO_SYS
VDDIO_SYS
VDDIO_SYS
I2C1
I2C2
GEN1_I2C_SCL/SDA
DDC_SCL/SDA
3.3V
5.0V
1.8V
1.8V
1.8V
1.8V
1.8V
Option for SMB to Charger
Mini VGA or HDMI Display
TI TPS658621 PMU
WM8903 Audio Codec
ID EEPROM
0x09
Main Board
Main Board
Main Board
Main Board
Main Board
Remote Location
Main Board
0x30, 0x50, 0x52
PWR_I2C PWR_I2C_SCL/SDA
0x34
0x1A
0x50
0x51
0x4C
I2C1
PWR_I2C
PWR_I2C
PWR_I2C
ID EEPROM
Temperature Sensor
Figure 5. I2C Diagram
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Tegra 200 Series Developer Board User Guide
4.1.1 Major Components
4.1.1.1 PMU
The Tegra 200 Series Developer Board includes a multi-channel power management unit for embedded processors (TI
TPS658621).
Feature List
ƒ
Host Interface
-
-
-
-
-
I2C Control I/F
Core/CPU power request signals
32.768KHz Clock
Reset input
Reset output
ƒ
ƒ
RTC LDO
-
-
-
1.0V-1.2V nominal voltage range with 25mV steps
Separate LDO for RTC domain allowing Deep Sleep mode support – the Tegra 250 lowest power mode
Switch RTC domain automatically back to 1.2V when wake-up event detected (w/CORE_PWR_REQ)
CORE switcher
-
-
-
-
-
1.0V-1.2V nominal voltage range with 25mV steps
CORE and RTC domains must track each other within 170mV
Tracking can be ensured in software
Optimized DVS handled by NVIDIA BSP (DVFS architecture)
Turned off if CORE_PWR_REQ is de-asserted – on at 1.2V when CORE_PWR_REQ asserted
ƒ
CPU switcher
-
-
-
0.85-1.0V nominal voltage range with 25mV steps
Optimized DVS handled by NVIDIA BSP (DVFS architecture)
Turned off if CPU_PWR_REQ is de-asserted – on at 1.0V when CPU_PWR_REQ asserted
ƒ
ƒ
PLL LDO
-
-
Use 1.1V LDO
Very good line regulation ensured using DC/DC switcher as LDO source
STDBY input
-
-
Standby mode: Only the minimum rails are kept powered (RTC and SYSTEM domains, DDR2 in self-refresh)
The Tegra 250 indicates Standby mode by de-asserting CORE_PWR_REQ (polarity programmable)
4.1.1.2 Battery Charge Controller
The Tegra 200 Series Developer Board includes a battery charger with input current detect comparator and charge enable pin
(TI bq24745). For a detailed description and list of device features, see http://focus.ti.com/lit/ds/symlink/bq24745.pdf.
4.1.1.3 Battery Pack (Not Included)
The Tegra 200 Series Developer Board can be used with a 3 cell (3S1P) Lithium ion battery pack that has a nominal voltage of
10.8 volts and a total capacity of 2200mAh. The 3S1P is ideal for applications that can operate on lower voltages.
4.1.1.4 External Switchers, LDOs, Power Switches
The Tegra 200 Series Developer Board includes the following components:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Notebook System Power Controller (TI TPS51220): a dual synchronous buck regulator controller with 2 LDOs. For a
detailed description and list of device features, see http://focus.ti.com/lit/ds/symlink/tps51220.pdf.
DDR2 Memory Power Supply (TI TPS51116): provides a power supply for the DDR2memory system. For a detailed
350mA Low-Dropout Linear Regulator (TI TPS72012): for a detailed description and list of device features, see
Step Down Converter (TI TPS62290): synchronous step down dc-dc converter optimized for battery powered portable
devices. For a detailed description and list of device features, see http://focus.ti.com/lit/ds/symlink/tps62290.pdf.
135-mΩ Dual Power-Distribution Switch (TI TPS2052): for a detailed description and list of device features, see
135-mΩ Power Distribution Switch (TI TPS2051): for a detailed description and list of device features, see
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Tegra 200 Series Developer Board User Guide
4.1.2 Power Supplies
The Tegra 250 has 29 power rails (3 cores, 14 analog and 12 digital I/O). Depending on system design, many of the rails can
share a power supply, and some are not needed for all designs. The example shown in Table 4 is based on the Smartbook
Development System design and should be representative of these types of designs. This table mainly lists the supplies
required by the Tegra 250. Others are required to support some of the peripherals typically seen in a Smartbook.
Table 4 Tegra 250 Power Supply Allocation Example
Voltage (V)
Supported
Power Rails
Power Supply
Enable
(Tegra 200
Series DB)
Voltages (V)
VDD_RTC
1.0 – 1.2
1.0 – 1.2
0.9 – 1.0
1.1
Up to 1.2
Up to 1.2
Up to 1.0
1.1
PMU LDO2
PMU SM0
PMU SM0
PMU LDO1
PMU LD04
PMU SM2 (3.7V) + Internal Trigger
CORE_PWR_REQ + Internal Trigger
CPU_PWR_REQ + Internal Trigger
PMU SM2 (3.7V) + Internal Trigger
PMU SM2 (3.7V) + Internal Trigger
VDD_CORE
VDD_CPU
AVDD_PLLx
VDDIO_SYS, AVDD_OSC
1.8
1.8
VDDIO_LCD,VDDIO_BB,VDDIO_AUDIO,VDDIO_UART
VDDIO_DDR
1.8,2.8,3.3
1.8
EN_VDD_1V8
1.8
TPS51116, DC/DC
(PG_VDDIO_SYS – PMU LDO4PG)
AVDD_USB, AVDD_USB_PLL
VDD_DDR_RX
3.3
3.3
PMU LDO3
PMU SM2 (3.7V) + Internal Trigger
PMU SM2 (3.7V) + Internal Trigger
EN_VDD_3V3 (Output of SR)
PMU SM2 (3.7V)
2.8
2.8
PMU LDO9
VDDIO_NAND (if 3.3V), VDDIO_SDIO, VDDIO_VI
AVDD_VDAC
1.8,2.8,3.3
2.7 – 3.3
3.3
3.3
TPS51220, DC/DC
PMU LDO6
2.85
3.3
AVDD_HDMI
PMU LDO7
PMU SM2 (3.7V)
AVDD_HDMI_PLL
1.8, 2.5
3.3
1.8
PMU LDO8
PMU SM2 (3.7V)
VDDIO_PEX_CLK
3.3
PMU LDO0
PMU SM2 (3.7V)
AVDD_DSI_CSI
1.2
1.2
TPS72012, LDO2
TPS62290, DC/DC
PMU LD05
EN_VDD_1V2 (PMU GPIO)
EN_VDD_1V05 (PMU GPIO)
AVDD_PCIE, AVDD_PEX, AVDD_PEX_PLL, VDD_PEX
VCORE_MMC
1.05
1.05
2.85
2.7 – 3.6
Note:
1: This includes pins AVDD_PLLA_C_P (powers PLLA, PLLC and PLLP), AVDD_PLLM, AVDD_PLLU (powers
PLLU and PLLD) and AVDD_PLLX. If PCIE not supported in a design, AVDD_PCIE should be left
unpowered as the leakage is significant.
2: Supplies must meet maximum rate requirement in AP20 EMT of 165mV/us
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Tegra 200 Series Developer Board User Guide
4.1.3 Power Sequencing
The Power solution, including the PMU and any external supplies/logic, must be able to meet the Tegra 250 power sequence
requirements. These requirements are detailed in the Tegra 200 Series datasheet (Electrical, Mechanical and Thermal
Specifications). Figure 7 shows the sequence used for the Smartbook Development System.
Figure 7. Power-up Sequence Example
VBAT (10.2-12.6V, 15V)
VDD_5V0 (5V, DC/DC TPS51220A)
VDD_3V3_SBY (3.3V, DC/DC TPS51220A)
BATTERY or AC/DC
VDDIO_ONKEY (2.2V, PMU LDO)
ONKEY (VDD_2V2)
VDD_SM2 (3.7V, PMU SM2)
PMU SUPPLY
EXTERNAL SUPPLY
Signals
VDD_RTC (1.2V, PMU LDO2)
VDD_CORE (1.2V, PMU SM0)
AVDD_PLL (1.1V, PMU LDO1)
VDDIO_SYS/AVDD_OSC (1.8V, PMU LDO4)
CLK_32K_IN (PMU)
32KHz Ramp Time
System Clock (External Source or XTAL)
VDD_1V8 (1.8V, DC/DC TPS51116)
V2REF_DDR2 (0.9V, DC/DC TPS51116)
AVDD_USB / USB_PLL (3.3V, PMU LDO3)
VCORE_MMC (2.85V, PMU LDO5)
VDD_DDR_RX (2.85V, PMU LDO9)
VDD_3V3 (3.3V, DC/DC TPS51220A)
VDD_CPU (1.0V, PMU SM1)
Oscillator Ramp Time
SYS_RESET_N (PMU)
AVDD_VDAC (2.85V, PMU LDO6)
AVDD_HDMI (3.3V, PMU LDO7)
AVDD_HDM_PLL (1.8V, PMU LDO8)
VDDIO_PEX_CLK (3.3V, PMU LDO0)
Misc. 1.5V, 3.3V, 5.0V, Backlight
AVDD_DSI_CSI (1.2V, LDO TPS72012)
VDD_1V05 (1.05V, DC/DC TPS62290)
Off by
Default
GPIO
Enabled
VDD_3V3: VDDIO_NAND_3V3, VDDIO_SDIO,VDDIO_VI
VDD_1V8: VDDIO_NAND_1V8, VDDIO_LCD, VDDIO_BB, VDDIO_AUDIO, VDDIO_UART, VDDIO_DDR
VDD_1V05: AVDD_PLLE, AVDD_PEX, AVDD_PEX_PLL, VDD_PEX
Note:
1: VDD_RTC, VDD_CORE, Critical PLLs, AVDD_OSC, VDDIO_SYS, VDDIO_DDR, VDDIO_NAND, 32.768KHz
and System clocks required before SYS_RESET_N goes high
2: Recommended Power-down sequence is reverse of Power-up.
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Tegra 200 Series Developer Board User Guide
4.1.4 Bypass Capacitor Recommendations
Table 5 lists the basic recommendations for bypass capacitors near the Tegra 250. In general, one 0.1uf per power pin (or
group for cores) is desirable. These should be placed as close as possible to the respective power pins. In addition, for the
higher power/higher frequency I/O rails one or more 4.7uf bulk capacitor is recommended and should be placed in the general
area of the power and interface pins.
Table 5 Power Supply Capacitor Recommendations for Tegra 250 Supplies
Power Rail
0.1uF Bypass
Capacitors
4.7uF Bulk
Capacitors
Power Rail
0.1uF Bypass
Capacitors
4.7uF Bulk
Capacitors
Cores
VDD_CORE
VDD_RTC
3
1
2
VDD_CPU
1
3
Analog
AVDD_PLLn1
AVDD_DSI_CSI
AVDD_OSC
AVDD_VDAC
AVDD_HDMI_PLL
AVDD_PEX_PLL
Digital
1 each
1
AVDD_HDMI
AVDD_USB_PLL
AVDD_USB
1
1
1
1
1
1
1
1
AVDD_IC_USB
AVDD_PEX
1
1
1
AVDD_PLLE
VDDIO_DDR
VDDIO_NAND
VDDIO_HSIC
VDDIO_BB
6
1
1
1
VDDIO_DDR_RX
VDDIO_VI
1
1
1
1
1
1
1
1
0
1
1
1
1
1
VDDIO_SDIO
VDDIO_SYS
VDDIO_LCD
VDDIO_AUDIO
VDD_PEX
VDDIO_UART
VDDIO_PEX_CLK
1
Note:
1: AVDD_PLLA_P_C, AVDD_PLLM, AVDD_PLLU, AVDD_PLLX
4.1.5 Unused Interface Power Rails
The example also assumes that all the interfaces are to be used. If a design does not use any functions on one or more of the
interface blocks, the associated power rail does not need to be powered. For the correct handling of each of the rails in this
case, check the Unused Pin section under for the interface in this document. Generally, unused digital power rails can be left
unconnected or tied to ground while unused analog rails should be left unconnected.
4.1.6 Unused Power Management Signals
A few of the signals related to power management may not be required in some designs. This includes SYS_CLK_REQ and
CLK_32K_OUT. If not required, these pins can be configured as GPIOs instead. CORE_PWR_REQ may also not be needed in
all designs, but this pin does not have a GPIO option. If any of these pins are not used, either as their primary function or as a
GPIO (if available), they can be left unconnected.
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Tegra 200 Series Developer Board User Guide
4.2 Clocks
The Tegra 250 has a large number of internal functional blocks supporting a broad range of interfaces. Each of these has its
own clocking requirements. The RTC (Real Time Clock) and PMC (Power Management Controller) require a 32.768KHz clock,
to be provided externally. In addition, a higher frequency reference clock (OSC) is required. This can come from a crystal or an
external source, and feeds several integrated PLLs that provide a variety of clocking options for the core and I/O blocks. The
Tegra 250 clocking scheme is shown in Figure 8.
Figure 8. Tegra 250 Clocking Block Diagram
4.2.1 32.768KHz Clock
The 32.768KHz clock is provided externally by the PMU. This clock is input on the CLK_32K_IN pin which is referenced to the
VDDIO_SYS rail. See the Tegra 200 Series Datasheet (Electrical, Mechanical and Thermal Specifications) for details on the
requirements for this clock.
4.2.2 Oscillator Clock
The Tegra 200 Series Developer Board utilizes a 12MHz crystal connected to the Tegra 250 XTAL_IN, XTAL_OUT pins to
generate the reference clock internally. A reference circuit is shown in Figure 9.
Table 6 contains the requirements for the crystal used, the value of the parallel bias resistor and information to calculate the
values of the two external load capacitors (CL1 and CL2) shown in the circuit.
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Figure 9. Crystal Connection Example
Table 6 Crystal and Circuit Requirements
Symbol
FP
Parameter
Min
Typ
12
Max
Unit
MHz
ppm
pf
Parallel resonance crystal Frequency
Frequency Tolerance
FTOL
CL
±50
7
Load Capacitance for crystal parallel resonance
Crystal Drive Level
5
10
DL
300
uW
MΩ
Ω
RBIAS
ESR
External Bias Resistor
2
Equivalent Series Resistance
80
Note:
FP, FTOL, CL and DL are found in the Xtal Datasheet
ESR = RM * (1 + C0/CL)/2 where RM = Motional Resistance, C0 =Shunt Capacitance from Xtal datasheet.
Datasheets may specify ESR directly – consult manufacturer if unclear whether ESR or RM are specified.
Load capacitor values (CLx) can be found with formula CL = [(CL1xCL2)/(CL1+CL2)]+CPCB
Or since CL1 and CL2 are typically of equal value, CL = (CLx/2)+CPCB. or CLx = (CL – CPCB) x 2
CL = Load capacitance (Xtal datasheet). CPCB is PCB capacitance (trace, via, pad, etc.)
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Tegra 200 Series Developer Board User Guide
4.3 DRAM Memory Configurations
Tegra 250 supports standard DDR2 SDRAM. Up to 1GB total memory, two chip selects and two Clock Enables are supported.
A full 8-device configurations using x8 DDR2 devices is shown. A 4 device configuration is possible and is a subset of the 8
device configuration. Only Rank 0 would be used in this case.
4.3.1 Four, 8-bit DDR2 devices
ƒ
ƒ
ƒ
Four Devices are routed in parallel to form single 32-bit memory Rank (1 Chip Select, 1 Clock Enable)
CLK+/-, Address, BA, RAS/CAS/WR, CKE0, CS0 and ODT0 are routed to all devices (4 loads)
DQ[31:0], DQS[3:0]+/-, DQM[3:0] are routed to one device each (1 load)
4.3.2 Eight, 8-bit DDR2 devices
ƒ
ƒ
ƒ
ƒ
Two Ranks of four devices each form two 32-bit memory Ranks (2 Chip Selects, 2 Clock Enables)
CLK+/-, Address, BA, RAS/CAS/WR and ODT0 are routed to all devices (8 loads)
CKE[1:0] and CS0[1:0]_N are routed to 4 devices each (4 loads)
DQ[31:0], DQS[3:0]+/-, DQM[3:0] are routed to 2 devices each (2 loads)
Figure 10. Eight, 8-bit DDR2 Configuration
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Tegra 200 Series Developer Board User Guide
Table 7. DDR Pinout
Signal
Pin
A20
C24
D20
B20
F26
C26
C27
F28
A26
A23
D23
C20
C18
E28
C28
E26
E27
H26
A21
C21
E25
C23
B26
A24
B24
G15
G17
A18
B18
B23
F27
E20
D19
F15
F14
F24
E24
D10
E11
Signal
Pin
F19
E15
G23
D9
DDR_A0
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_A1
DDR_A2
DDR_A3
DDR_A4
F20
E18
D18
F18
F17
E21
D21
F21
E17
D15
F16
E14
F13
D16
D12
D13
F23
F25
H22
G25
F22
D24
H24
E23
F9
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_CLK
DDR_CLK_N
DDR_CAS_N
DDR_CKE0
DDR_CKE1
DDR_CS0_N
DDR_CS1_N
DDR_BA0
DDR_BA1
DDR_BA2
DDR_QUSE0
DDR_QUSE1
DDR_QUSE2
DDR_QUSE3
DDR_RAS_N
DDR_WE_N
DDR_DQS0P
DDR_DQS0N
DDR_DQS1p
DDR_DQS1N
DDR_DQS2p
DDR_DQS2N
DDR_DQS3p
DDR_DQS3N
F12
E12
E9
F10
G8
F11
G9
4.3.3 Unused Pins
Any unused signal pins can be left unconnected.
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Tegra 200 Series Developer Board User Guide
4.4 NAND
The Tegra 250 GMI interface supports a broad range of devices including a variety of NAND devices and configurations.
ƒ
ƒ
Works with SLC and MLC devices
Supports up to 8 devices with up to 8 chip selects
Figure 11. Single 8-bit NAND Connection Example
4.5 USB
The Tegra 250 has three available USB controllers. Controllers #1 and #3 come out on the USB PHYs on the USB1 and USB3
pins. Controller #2 can be used for either ULPI or HSIC (only one at a time).
Controller #1
This USB controller is routed to an integrated PHY (USB1) and supports low-, full- and high-speed mode. Both Host and Device
modes are supported. VBUS and Device ID are available to support Type A, B or A/B connector types. USB1 is required for
Recovery mode and must be configurable as a USB Device when the Force Recovery strap (on pin GMI_OE_N is held low. In
this case, USB1 is connected to a host, typically for flashing images at the factory or possibly in the field.
Controller #2
Controller #2 can be used for either ULPI or HSIC. Only one can be used in a design.
ULPI is a 12-pin I/F used to connect to compatible external USB PHYs, baseband or other compatible devices. An example of
the ULPI interface being used to connect to an SMSC USB3315 ULPI to USB PHY is shown in the ULPI section.
HSIC is a 2-pin I/F for high-speed chip-to-chip communications to compatible external PHYs, hubs, basebands, etc.
Controller #3
Controller #3 can be routed to a second integrated USB PHY (USB3) or to the IC_USB interface. Only one of these functions
can be used in a design.
USB3 also supports low, full and high speed modes and can be configured as Host or Device. VBUS and Device ID are
provided on this interface. Typically, in a Smartbook design, USB3 would be used as a Host to interface to a Type A host port,
or more likely, a USB Hub. An example of USB3 interfacing to an SMSC LAN9514 USB Hub and Ethernet controller is provided
in section 3.7 .
The IC_USB interface is used to connect to compatible SIM Cards.
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4.5.1 Force Recovery
The Tegra 250 requires USB1 to be available as a Device for Force Recovery mode which is used to download new firmware.
This is shown in Figure 12 where a USB Mini B connector is available to connect to a Host system. Force Recovery mode is
entered by keeping the FORCE_RECOVERY pin low when the system is first powered up (until SYS_RESET_N goes high.
This is accomplished by pressing the momentary push button shown during power-on.
Figure 12 Force Recovery Connections
4.5.2 ULPI
The Tegra 250 optionally supports ULPI (UMTI+ Low Pin Interface) as an option to connect to external USB PHYs, or other
compatible devices.
ƒ
ƒ
ƒ
12 bit interface including ULPI_CLK, ULPI_DIR, ULPI_NXT, ULPI_STP and ULPI_DAT[7:0]
Operates from 60 MHz clock
8-bit SDR data interface - 4-bit DDR data I/F not supported
Figure 13 shows the Tegra 250 interfacing with an external ULPI-USB PHY. The USB PHY can be used to interface to a
compatible Baseband, a USB Hub, etc.
Figure 13. Example ULPI connection to External SMSC USB3317 USB PHY
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Table 8. ULPI Pinout
Signal
Pin
M2
M3
M1
P3
Signal
Pin
N4
L3
ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
L4
L6
P4
P5
N6
P6
4.5.3 PCIe
The remaining two downstream USB interfaces on the Tegra 200 Series Developer Board are each routed to one of the Mini-
PCIe connectors shown. One use for Mini-PCIe is to support compatible Baseband modules (currently using the USB interface
portion of Mini-PCIe). A SIM socket is provided off one of the PCIe Mini Card connectors for this purpose. Other peripherals
such as Solid-State drives or Wi-Fi may also take advantage of the high performance PCIe interfaces on the PCIe Mini Card
connectors.
Contact NVIDIA for a list of certified PCI express peripherals.
Figure 14. Example LAN9514 USB/Ethernet Hub and Dual Mini-PCIe Connectors
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Table 9. PCIe Pinout
Signal
Pin
AC4
AD4
Y4
Signal
Pin
AC2
AC1
V4
PEX_CLK_OUT1_N
PEX_CLK_OUT1_P
PEX_CLK_OUT2_N
PEX_CLK_OUT2_P
PEX_L0_RXN
PEX_L1_TXN
PEX_L1_TXP
PEX_L2_RXN
PEX_L2_RXP
PEX_L2_TXN
PEX_L2_TXP
PEX_L3_RXN
PEX_L3_RXP
PEX_L3_TXN
PEX_L3_TXP
Y5
V3
AA5
AA4
AD1
AD2
AA7
AA6
AA1
AA2
V6
PEX_L0_RXP
PEX_L0_TXN
PEX_L0_TXP
V5
PEX_L1_RXN
Y3
PEX_L1_RXP
Y2
4.6 Display
ƒ
ƒ
ƒ
ƒ
LCD Displays
HDMI
VGA (CRT)
SDTV / HDTV Out
4.6.1 LCD Displays
The Tegra 250 supports a broad range of interfaces for connecting to LCD displays. Two separate display controllers can drive
up to two displays. One of the displays can be an LCD while the other an HDMI display, standard NTSC/PAL TV or CRT.
Alternately, a number of dual LCD combinations are supported. An 18-bit interface to an external LVDS Transmitter to connect
to common Smartbook panels is described. Other interface options are possible. The example assumes an SPWG 18BPP
single channel LVDS panel interface.
Figure 15. Single Channel LVDS Signal Mapping
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Figure 16. Example LVDS Connections
Table 10. LVDS Pinout
Signal
Pin
Signal
Pin
Signal
Pin
LCD_D0
LCD_D1
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_D8
LCD_D13
AA26
AC26
AC27
AC28
AD25
AD28
Y26
LCD_D9
Y25
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
LCD_DE
AA23
AB23
AA22
V25
LCD_D10
LCD_D11
LCD_D12
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_VSYNC
AA28
AA27
U25
U27
U26
V27
AC22
U23
LCD_HSYNC
LCD_PCLK
AD27
V28
Y27
V26
Y28
AB25
AD26
U28
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4.6.2 HDMI
ƒ
ƒ
ƒ
HDMI_RSET on the Tegra 250 is tied to ground through a 1KΩ, 1% resistor
DDC_SCL/SDA pins are 5V tolerant (no level shifter required). I2C pull-ups connect to 5V supply.
HP_DET drives HDMI_INT (interrupt pin) on the Tegra 250 (Also 5V tolerant - no level shifter required).
Figure 17: HDMI Connection Example
Table 11. HDMI Pinout
Signal
Pin
Signal
Pin
HDMI_TXCN
HDMI_TXCP
HDMI_TXD0N
HDMI_TXD0P
AF17
AG17
AE16
AE17
HDMI_TXD1N
HDMI_TXD1P
HDMI_TXD2N
HDMI_TXD2P
AC18
AD18
AH18
AG18
4.6.2.1 Unused Pins
Any unused signal lines can be left unconnected. If HDMI is not implemented, AVDD_HDMI/HDMI_PLL rails and all signal pins
can be left unconnected.
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4.6.3 VGA (CRT) Out
Figure 18. VGA Output Connection Example
4.6.3.1 Unused Pins
Any unused VDAC pins (VDAC_R, VDAC_G, VDAC_B) can be left unconnected. If the TV/CRT Output function will not be
supported, AVDD_VDAC, VDAC_R/G/B, VDAC_RSET and VDAC_VREF should be left unconnected.
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4.7 Camera
The Tegra 200 Series Developer Board supports a dual lane MIPI CSI connection. The Smartbook Development System uses
an OmniVision Camera module.
Figure 19: Tegra 200 Series Developer Board CSI Camera Connections
Table 12. CSI Pinout
Signal
Pin
Signal
Pin
CSI_CLKAN
CSI_CLKAP
CSI_D1AN
CSI_D1AP
CSI_D2AN
AH26
AG26
AD20
AE20
AH23
CSI_D2AP
CSI_CLKBN
CSI_CLKBP
CSI_D1BN
CSI_D1BP
AG23
AB20
AC20
AH24
AG24
4.7.1 Unused Pins
Any unused signal lines can be left unconnected. If neither DSI nor CSI are implemented, the AVDD_DSI_CSI power rail, all
data/clock lines and the DSI_CSI_RUP, DSI_CSI_RND pins should be left unconnected.
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Tegra 200 Series Developer Board User Guide
4.8 SD/SDIO/MMC
The Tegra 250 has four SD/MMC controllers, capable of supporting a variety of devices and protocols including SD Memory,
SDIO, eSD, MMC and eMMC. SD/eSD/SDIO can support up to 4-bits and at Standard or High Speed. MMC/eMMC supports 4
or 8-bit devices Standard or High Speed.
4.8.1 SD/MMC Card Connections
The SD/MMC socket uses the controller mapped to the SDIO2 controller pins on the VI interface domain.
Figure 20. Tegra 200 Series Developer Board Reference design 4-bit SD/MMC Card Socket Connection Example
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4.8.2 eMMC Device Connections
The SD/MMC interface can support a variety of flash memory devices. The Tegra 200 Series Developer Board uses a
combination 4-bit SD/MMC and 8-bit MMC socket to support either standard SD/MMC cards, or proprietary modules with eMMC
(embedded MMC) or other compatible devices for storage and possibly boot options. One available module that can be used
with this socket supports eMMC. The example in Figure 21 shows a connection example that will work with the eMMC module
as both the boot and mass storage device.
Figure 21. Tegra 200 Series Developer Board Reference design 4/8-bit “Captive” SD/MMC Card Socket Connection Example
VDDIO_NAND
0.1uf
Tegra
GND_EMI2
HSMMC_DAT4
HSMMC_DAT5
HSMMC_DAT2
HSMMC_DAT3
HSMMC_CMD
D4
GMI_AD24
GMI_AD25
GMI_AD22
GMI_AD23
GMI_DPD
D5
D2
D3
CMD
GND
VDD
CLK
GND
D0
HSMMC_CLK
GMI_CS5_N
HSMMC_DAT0
HSMMC_DAT1
HSMMC_DAT6
HSMMC_DAT7
GMI_AD20
GMI_AD21
GMI_AD26
GMI_AD27
D1
D6
D7
The Tegra 200 Series Developer Board uses this
socket to as an internal means to support assorted
boot/storage devices including eMMC. This
header is included to provide a core supply to an
eMMC module. Not needed if eMMC or other
device directly on-board
D2
D3
CMD
GND
VDD
CLK
GND
D0
0.1uf
eMMC Core (2.85V)
D1
GPIO_PH2 (HSMMC_CD_N)
GPIO_PH3 (HSMMC_WP)
C_DETECT_N
WP_N
GMI_AD10
GMI_AD11
GND_EMI2
VDDIO_NAND
3.3V
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4.8.3 SDIO Device Connections
An SDIO controller is often used to interface to medium bandwidth peripherals such as a Wi-Fi controller. The connection
example in Figure 22 is from the Smartbook Development System. This shows a Wi-Fi/BT module interfacing to the Tegra 250
SDIO1, UART3 and DAP4 interfaces as well as several GPIO pins for control. Only the signals between the Tegra 250 and the
module are shown.
Figure 22. Tegra 250 SDIO WiFi Connection Example
4.8.4 Unused Pins
Any unused data pins can be left unconnected. If the HSMMC or SD/SDIO interfaces will not be supported at all, then any
unused signal pin can be left unconnected or configured for another function or GPIO. If none of the signals are used on one of
the digital power domains (except VDDIO_DDR and VDDIO_SYS which must be powered for normal operation), then the
associated power rail can be left unconnected or tied to GND.
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4.9 Miscellaneous
4.9.1 Thermal Diode (Temperature Sensor)
Figure 23: Thermal Diode Connection Example
Table 13. Thermal Diode Pinout
Signal
Pin
E6
THERMD_N
THERMD_P
F7
4.9.2 Debug Interfaces
An optional debug connector providing access to several debugging interfaces can be added to a design, possibly in the early
stages and removed for production. One option is the Debug connector shown in Figure 24. This connector is used with the
E1137 Combo Debug Board. This board interfaces to the Tegra 200 Series Developer Board Debug connector (J10) using a
flex cable. The Combo board provides:
ƒ
ƒ
RS-232 interface on a DB-9 connector which uses UART1 on the Tegra 250
Standard 20-pin, 0.1” JTAG header
-
-
Can be used with standard ARM software development/debugging hardware
Provides low level access to the CPUs and AVP
ƒ
Ethernet RJ-45 jack by means of a SPI-Ethernet controller (using the Tegra 250 SPI1 interface)
Note that in the circuit in Figure 24, there is an optional resistor on JTAG_TRST_N. For normal JTAG operation, this resistor
should not be present. The JTAG_TRST_N pin on the Tegra 250 selects whether the JTAG interface is to be used for
communicating with the Tegra 250 CPU complex, or for Test/Scan purposes. When JTAG_TRST_N is pulled low, the JTAG
interface is enabled for access to the CPU complex. When high, it is in Test/Scan mode.
When used in the normal operating mode to access the internal CPUs, in order to reset the Tegra 250 JTAG block, a reset
command is used rather than toggling the JTAG_TRST_N pin.
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Figure 24. Debug Interface Connection
VDDIO_SYS
VDDIO_SYS
ONKEY_N
10KΩ
Tegra
DEBUG
CONNECTOR
10KΩ
SPI1_SCK
SPI1_CS0_N
SPI1_MOSI
SPI1_MISO
AUDIO
11
10
12
13
14
15
16
1.8V
1.8V
VDDIO_AUDIO
DBG_RESET_N
9
8
7
6
5
4
3
2
1
UART1_TXD
UART1_RXD
UART
VDDIO_UART
17
18
19
20
21
22
JTAG_RTCK
JTAG_TCK
SYSTEM
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
1.8V
1.8V
VDDIO_SYS
No Stuff
100KΩ
LCD_PWR1
LCD
VDDIO_LCD
DBG_IRQ_N
Unused Pins
If JTAG is not implemented, then JTAG_RTCK and JTAG_TDO can be left unconnected. The JTAG_TDI and JTAG_TMS pins
still need to be pulled up, and JTAG_TRST_N and JTAG_TCK must be pulled down. The rail the JTAG pins reside on
(VDDIO_SYS) must be powered for any mode including Deep Sleep.
4.9.3 EFUSE
The Tegra 250 design must provide a way to supply a 3.3V power source to the FUSE_SRC pin. This can be accomplished
using one of the following mechanisms:
ƒ
ƒ
ƒ
ƒ
Test point to connect external 3.3V supply
3.3V Output of on-board LDO controlled by the Tegra 250 GPIO
3.3V Output of PMU, controlled by PWR_I2C from the Tegra 250
Permanently connected to always-on 3.3V supply
The power source must provide a nominal voltage of 3.3V and be able to supply a minimum of 100mA. When not powered, a
10K Ω pull-down resistor each on FUSE_SRC is required. A 0.1uf bypass capacitor is also recommended on FUSE_SRC. The
KFUSE_SRC pin must be pulled down with a 10KΩ resistor only..
Figure 25. EFUSE Connections
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4.9.4 Strapping Pins
Straps must be stable from the rising edge of SYS_RESET_N until 12.5us afterward.
Figure 26. Power-on Strapping Connections
Table 14. Power-on Strapping Breakdown
Strap Options
Strap Pins
Description
USB_RECOVERY
GMI_OE_N
0: USB Recovery Mode
1: Boot from secondary device
JTAG_ARM[1:0]
GMI_CLK, GMI_ADV_N
GMI_AD[7:4]
00: Serial JTAG chain, MPCORE and AVP
RAM_CODE[3:0]
SW uses to determine which BCT table to use for DRAM, NAND timing
Selects Boot device - depends on how Boot fuses are burned
BOOT_SELECT_CODE[3:0]
GMI_AD[15:12]
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5.0 THERMAL
5.1 Major Component Thermal Specifications
Most of the major components used in Tegra 200 series Developer Board are listed in Table 39 along with the temperature
range they are able to operate across.
Note:
The specifications noted in Table 16 may change and other versions with wider or
narrower temperature ranges may be available from the manufacturers
Any design using these components must ensure each of these devices do not exceed the maximum temperature. This may
require careful board and mechanical design practices to accommodate various contributors to heat generation.
Table 15. Major Component Thermal Specifications
Device
Definition
Min
0
Max
50
85
85
70
85
85
70
70
85
70
Units
°C
Notes
Overall System
Operating temperature (ambient)
Operating Case Temperature
Operating Case Temperature
Operating Case Temperature
Operating Case Temperature
Operating Case temperature
Operating Case Temperature
Operating Case Temperature
Operating Case Temperature
Operating Case Temperature
1
Tegra 250
-25
-30
0
°C
Hynix HY5PS1G831CLFP DDR2
Hynix HY27UF084G2B-TPCB NAND
Wolfson WM8903 Audio Codec
TI TPS658621AZGUR PMU
SMSC MEC1308 Embedded Controller
SMSC LAN9514 USB Hub and Ethernet
SMSC USB3315 ULPI Phy
TI SN75LVDS83B LVDS Transmitter
°C
°C
-40
-40
0
°C
°C
°C
0
°C
-40
-10
°C
°C
Note:
1. Design specific. Rating shown is typical for many mobile computing designs
5.2 Thermal Considerations for Components
Figure 27 and Figure 28 show the top and bottom of the Tegra 200 Series Developer Board. The components that either
generate heat, or may be very sensitive to temperature are highlighted with different colors:
ƒ
ƒ
ƒ
ƒ
Green: Adversely sensitive to heat
Yellow: Mild contributor to heat generation
Lt Orange: Medium contributor to heat generation
Dark Orange: Significant contributor to heat generation
The Green coded devices may be significantly affected by temperature. Typically these have more analog circuitry and may not
perform as well hot such as the Camera Module. The other highlighted parts contribute additional heat to the system which can
be problematic to deal with in an enclosed mobile device.
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Figure 27. Top View – Heat Generating and Thermal Sensitive Components
Figure 28. Bottom View – Heat Generating and Thermal Sensitive Components
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The Tegra 200 Series Developer Board does not represent an actual layout for use in a Smartbook design. It does show the
various components typically found in a Smartbook and aids in describing some useful thermal guidelines:
ƒ
Keep hotter or more sensitive components from being in close proximity to each other
-
This may include keeping them from being directly opposite each other on each side of the PCB. The exception is
the DDR2 devices which need to be located opposite each other in an 8 device design for signal integrity reasons.
ƒ
ƒ
Provide airflow to help remove trapped heat for either side of the PCB where hot components are located
Possibly providing extra room (x, y and z) around hot components to help with airflow
Use some type of metal heat spreader to help dissipate some of the heat from especially hot components.
-
-
This could be an additional piece of metal, or having the case (bottom of PCB) or keyboard plate (top of PCB)
contact the hotter components.
Figure 29. Considerations for resolving for thermal “hot spots”
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