Motorola Computer Hardware MVME162LX User Manual

700/800-Series  
MVME162LX  
Embedded Controller  
Installation and Use  
V162-7A/IH1  
Preface  
This document provides general information and basic installation instructions for  
the 700/800-series MVME162LX VME Embedded Controller, which is available in  
the versions listed below.  
Assembly  
Item  
Board  
Description  
Assembly Item  
Board Description  
MVME162-723  
32MHz, 4MB DRAM  
MVME162-813 32MHz, 8MB  
DRAM  
MVME162-743  
MVME162-763  
32MHz, 4MB ECC  
DRAM  
MVME162-833 32MHz, 8MB  
ECC DRAM  
32MHz, 16MB ECC  
DRAM  
MVME162-853 32MHz, 32MB  
ECC DRAM  
MVME162-863 32MHz, 16MB  
ECC DRAM  
In 700/800-Series MVME162LX Embedded Controller Installation and Use you will  
Þnd a general board-level hardware description, hardware preparation and  
installation instructions, a description of the debugger Þrmware, and information  
on using the Þrmware on the MVME162LX VME Embedded Controller.  
This manual is intended for anyone who wants to design OEM systems, supply  
additional capability to an existing compatible system, or work in a lab  
environment for experimental purposes. A basic knowledge of computers and  
digital logic is assumed.  
Companion publications are listed beginning on page 1-3.  
Safety Summary  
Safety Depends OnYou  
The following general safety precautions must be observed during all phases of operation, service, and  
repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in  
this manual violates safety standards of design, manufacture, and intended use of the equipment.  
Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.  
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You,  
as the user of the product, should follow these warnings and all other safety precautions necessary for the  
safe operation of the equipment in your operating environment.  
Ground the Instrument.  
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground.  
The equipment is supplied with a three-conductor AC power cable. The power cable must be plugged into  
an approved three-contact electrical outlet. The power jack and mating plug of the power cable must meet  
International Electrotechnical Commission (IEC) safety standards.  
Do Not Operate in an Explosive Atmosphere.  
Do not operate the equipment in the presence of ßammable gases or fumes. Operation of any electrical  
equipment in such an environment constitutes a deÞnite safety hazard.  
Keep Away From Live Circuits.  
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or  
other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or  
component replacement or any internal adjustment. Do not replace components with the power cable  
connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To  
avoid injuries, always disconnect power and discharge circuits before touching them.  
Do Not Service or Adjust Alone.  
Do not attempt internal service or adjustment unless another person capable of rendering Þrst aid and  
resuscitation is present.  
Use Caution When Exposing or Handling the CRT.  
Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion).  
To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should  
be done only by qualiÞed maintenance personnel using approved safety mask and gloves.  
Do Not Substitute Parts or Modify Equipment.  
Because of the danger of introducing additional hazards, do not install substitute parts or perform any  
unauthorized modiÞcation of the equipment. Contact your local Motorola representative for service and  
repair to ensure that safety features are maintained.  
Dangerous Procedure Warnings.  
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.  
Instructions contained in the warnings must be followed. You should also employ all other safety  
precautions which you deem necessary for the operation of the equipment in your operating environment.  
Dangerous voltages, capable of causing death, are  
!
present in this equipment. Use extreme caution when  
handling, testing, and adjusting.  
WARNING  
Lithium Battery Caution  
The board contains a lithium battery to power the clock and  
calendar circuitry.  
Danger of explosion if battery is replaced incorrectly.  
Replace only with the same or equivalent type  
recommended by the equipment manufacturer. Dispose  
of used batteries according to the manufacturerÕs  
instructions.  
!
CAUTION  
Il y a danger dÕexplosion sÕil y a remplacement incorrect  
de la batterie. Remplacer uniquement avec une batterie  
du m•me type ou dÕun type Žquivalent recommandŽ  
par le constructeur. Mettre au rebut les batteries usagŽes  
conformŽment aux instructions du fabricant.  
!
Attention  
Explosionsgefahr bei unsachgemŠ§em Austausch der  
Batterie. Ersatz nur durch denselben oder einen vom  
Hersteller empfohlenen Typ. Entsorgung gebrauchter  
Batterien nach Angaben des Herstellers.  
!
Vorsicht  
All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized  
manufacturers, with a ßammability rating of 94V-0.  
This equipment generates, uses, and can radiate electro-  
!
magnetic energy. It may cause or be susceptible to  
electro-magnetic interference (EMI) if not installed and  
used in a cabinet with adequate EMI protection.  
WARNING  
European Notice: Board products with the CE marking comply with the  
EMC Directive (89/336/EEC). Compliance with this directive implies  
conformity to the following European Norms:  
EN55022 (CISPR 22) Radio Frequency Interference  
EN50082-1 (IEC801-2, IEC801-3, IEC801-4) Electromagnetic Immunity  
The product also fulÞlls EN60950 (product safety), which is essentially  
the requirement for the Low Voltage Directive (73/23/EEC).  
This board product was tested in a representative system to show  
compliance with the above mentioned requirements. A proper  
installation in a CE-marked system will maintain the required  
EMC/safety performance.  
The computer programs stored in the Read Only Memory of this device contain  
material copyrighted by Motorola Inc., 1995, and may be used only under a license  
such as those contained in MotorolaÕs software licenses.  
¨
Motorola and the Motorola symbol are registered trademarks of Motorola, Inc.  
All other products mentioned in this document are trademarks or registered  
trademarks of their respective holders.  
©Copyright Motorola 1997  
All Rights Reserved  
Printed in the United States of America  
October 1997  
Contents  
Lithium Battery Caution 5  
Introduction 1-1  
Overview 1-1  
Related Documentation 1-3  
Documents for the MVME162LX 1-4  
Other Applicable Motorola Publications 1-4  
Applicable Non-Motorola Publications 1-5  
Requirements 1-6  
Features 1-6  
SpeciÞcations 1-9  
Cooling Requirements 1-10  
Special Considerations for Elevated-Temperature Operation 1-10  
FCC Compliance 1-12  
Manual Terminology 1-12  
Block Diagram 1-14  
Functional Description 1-14  
Front Panel Switches and Indicators 1-14  
Data Bus Structure 1-16  
Microprocessor 1-16  
MC68040 Cache 1-16  
No-VMEbus-Interface Option 1-17  
Memory Options 1-17  
DRAM Options 1-17  
SRAM Options 1-18  
About the Battery 1-19  
EPROM and Flash Memory 1-21  
Battery Backed Up RAM and Clock 1-21  
VMEbus Interface and VMEchip2 1-21  
I/O Interfaces 1-22  
Serial Communications Interface 1-22  
IndustryPack (IP) Interfaces 1-23  
Optional Ethernet Interface 1-23  
Optional SCSI Interface 1-24  
SCSI Termination 1-24  
Local Resources 1-25  
Programmable Tick Timers 1-25  
Watchdog Timer 1-25  
Software-Programmable Hardware Interrupts 1-26  
Local Bus Timeout 1-26  
Local Bus Arbiter 1-27  
Connectors 1-27  
Memory Maps 1-28  
Local Bus Memory Map 1-28  
Normal Address Range 1-28  
VMEbus Memory Map 1-34  
VMEbus Accesses to the Local Bus 1-34  
VMEbus Short I/O Memory Map 1-34  
Introduction 2-1  
Unpacking Instructions 2-1  
Hardware Preparation 2-1  
System Controller Select Header (J1) 2-3  
IP Bus Clock Header (J11) 2-5  
SCSI Terminator Enable Header (J12) 2-6  
SRAM Backup Power Source Select Header (J14) 2-6  
Flash Write Protect Header (J16) 2-7  
IP Bus Strobe Select Header (J18) 2-8  
IP DMA Snoop Control Header (J19) 2-8  
EPROM/Flash ConÞguration Header (J20) 2-9  
Overview of M68000 Firmware 3-1  
Description of 162Bug 3-1  
162Bug Implementation 3-3  
Installation and Startup 3-3  
Restarting the System 3-10  
Reset 3-11  
Abort 3-11  
Break 3-12  
SYSFAIL* Assertion/Negation 3-12  
MPU Clock Speed Calculation 3-13  
Network I/O Error Codes 3-22  
Multiprocessor Support 3-22  
Multiprocessor Control Register (MPCR) Method 3-22  
GCSR Method 3-24  
Diagnostic Facilities 3-25  
Manufacturing Test Process 3-25  
In This Chapter 4-1  
Entering Debugger Command Lines 4-1  
Terminal Input/Output Control 4-1  
Debugger Command Syntax 4-3  
Syntactic Variables 4-3  
Expression as a Parameter 4-3  
Address as a Parameter 4-5  
Address Formats 4-6  
Offset Registers 4-7  
Port Numbers 4-9  
Entering and Debugging Programs 4-9  
Creating a Program with the Assembler/Disassembler 4-10  
Downloading an S-Record Object File 4-10  
Read the Program from Disk 4-10  
Calling System Utilities from User Programs 4-11  
Preserving the Debugger Operating Environment 4-11  
162Bug Vector Table and Workspace 4-12  
Examples 4-12  
Hardware Functions 4-13  
Exception Vectors Used by 162Bug 4-13  
Exception Vector Tables 4-15  
Using 162Bug Target Vector Table 4-15  
Creating a New Vector Table 4-16  
Floating Point Support 4-18  
Single Precision Real 4-19  
Double Precision Real 4-19  
ScientiÞc Notation 4-20  
The 162Bug Debugger Command Set 4-20  
ConÞgure Board Information Block A-1  
Set Environment to Bug/Operating System A-3  
ConÞguring the IndustryPacks A-14  
Disk/Tape Controller Modules Supported B-1  
Disk/Tape Controller Default ConÞgurations B-2  
IOT Command Parameters for Supported Floppy Types B-4  
Network Controller Modules Supported C-1  
Solving Startup Problems D-1  
1Board Level Hardware  
Description  
1
Introduction  
This chapter describes the board level hardware features of the  
700/800-series MVME162LX VME Embedded Controller. The  
chapter is organized with a board level overview and features list  
in this introduction, followed by a more detailed hardware  
functional description. Front panel switches and indicators are  
included in the detailed hardware functional description. The  
chapter closes with some general memory maps.  
All MVME162LX programmable registers that reside in ASICs are  
covered in the MVME162LX Embedded Controller ProgrammerÕs  
Reference Guide.  
Overview  
The MVME162LX is based on the MC68040 microprocessor.  
Various versions of the MVME162LX have parity-protected DRAM  
(4MB, 8M, or 16MB); or ECC-protected DRAM (4MB, 8MB, 16MB,  
or 32MB); 128KB of SRAM (with battery backup); a time-of-day  
clock (with battery backup); an optional LAN Ethernet transceiver  
interface; four serial ports with EIA-232-D interface; six tick timers  
with watchdog timer(s); two EPROM sockets; 2MB Flash memory  
(one Flash device); two IndustryPack (IP) interfaces with DMA;  
optional SCSI bus interface with DMA; and an optional VMEbus  
interface (local bus to VMEbus/VMEbus to local bus, with  
A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system  
controller).  
Input/Output (I/O) signals are routed through industry-standard  
connectors on the MVME162LX front panel; no adapter boards or  
transition modules are required. I/O connections include an  
optional 68-pin SCSI connector, an optional DB-15 Ethernet  
1-1  
Board Level Hardware Description  
1
connector, and four 8-pin RJ-45 serial connectors on the front panel.  
In addition, the panel has cutouts for routing of flat cables to the  
optional IndustryPack modules.  
The following ASICs are used on the MVME162LX:  
VMEchip2. (VMEbus interface). Provides two tick timers, a  
watchdog timer, programmable map decoders for the master  
and slave interfaces, and a VMEbus to/from local bus DMA  
controller, a VMEbus to/from local bus non-DMA  
programmed access interface, a VMEbus interrupter, a  
VMEbus system controller, a VMEbus interrupt handler, and  
a VMEbus requester.  
Processor-to-VMEbus transfers are D8, D16, or D32.  
VMEchip2 DMA transfers to the VMEbus, however, are D16,  
D32, D16/BLT, D32/BLT, or D64/MBLT.  
MC2chip. Provides four tick timers, the interface to the LAN  
chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash,  
parity DRAM and SRAM.  
MCECC memory controller. Provides the programmable  
interface for the ECC-protected DRAM mezzanine board.  
IndustryPack Interface Controller (IP2). The IP2 provides  
control and status information for up to two single-wide  
IndustryPacks (IPs) or one double-wide IP that can be  
plugged into the MVME162LX main board.  
1-2  
Introduction  
1
Related Documentation  
The MVME162LX ships with an installation and use manual (the  
document you are presently reading, Motorola publications  
number VME162-7A/IH) which includes installation instructions,  
jumper configuration information, memory maps, debugger/  
monitor commands, and any other information needed to start up  
the board.  
If you plan to develop your own applications or need more detailed  
information about your MVME162LX VME Embedded Controller,  
you may wish to order the additional documentation listed on the  
following pages. You can contact Motorola for this purpose in  
several ways:  
Through your local Motorola sales office  
Through the World Wide Web site listed on the back cover of  
this and other MCG manuals  
(USA and Canada only) Ñ By contacting the Literature  
Center via phone or fax at the numbers listed under Product  
Literature at MCGÕs World Wide Web site  
If any supplements have been issued for a manual or guide, they  
will be furnished along with that document. Each Motorola  
Computer Group manual publication number is suffixed with  
characters which represent the revision level of the document, such  
as Ò/IH2Ó (the second revision of a manual); a supplement bears  
the same number as a manual but has a suffix such as Ò/IH2A1Ó  
(the first supplement to the second edition of the manual).  
1-3  
Board Level Hardware Description  
1
Documents for the MVME162LX  
The following MCG publications are applicable to the 700/800-  
series MVME162LX and may provide additional helpful  
information. If they are not shipped with this product, you can  
obtain them by contacting your local Motorola sales office.  
Motorola  
Publication Number  
Description  
MVME162LXPG/D  
MVME162LX Embedded Controller ProgrammerÕs Reference  
Guide  
MVME162BUG/D  
MVME162Bug Debugging Package User's Manual  
68KBUG1/D  
68KBUG2/D  
Debugging Package for Motorola 68K CISC CPUs UserÕs  
Manual (Parts 1 and 2)  
SBCSCSI/D  
Single Board Computers SCSI Software UserÕs Manual  
Other Applicable Motorola Publications  
The following publications are also applicable to the 700/800-series  
MVME162LX and may provide additional helpful information.  
They may be purchased through your local Motorola sales office.  
Motorola  
Publication Number  
Description  
M68000FR  
M68000 Family Reference Manual  
M68040UM  
MC68040 Microprocessors User's Manual  
1-4  
Introduction  
1
Applicable Non-Motorola Publications  
The following non-Motorola publications are also available from  
the sources indicated.  
Document Title  
Source  
VME64 SpeciÞcation, order number  
ANSI/VITA 1-1994  
VITA (VMEbus International  
Trade Association)  
7825 E. Gelding Dr., Ste. 104  
Scottsdale, AZ 85260-3415  
Note: An earlier version of the VME  
speciÞcation is available as Versatile Backplane  
Bus: VMEbus, ANSI/IEEE Std 1014-1987  
(VMEbus SpeciÞcation). This is also available as  
Microprocessor System Bus for 1 to 4 Byte Data  
(IEC 821 BUS).  
ANSI Small Computer System Interface-2  
(SCSI-2), Draft Document X3.131-198X,  
Revision 10c  
Global Engineering Documents  
15 Inverness Way East  
Englewood, CO 80112-5704  
82596CA Local Area Network Coprocessor  
Data Sheet, order number 290218; and  
82596 User's Manual, order number 296853  
Intel Corporation  
Literature Sales  
P.O. Box 58130  
Santa Clara, CA 95052-8130  
28F016SA Flash Memory Data Sheet,  
order number 290435  
Intel Corporation  
Literature Sales  
P.O. Box 7641, Mt. Prospect, IL  
60056-7641  
1-5  
Board Level Hardware Description  
1
Document Title  
Source  
NCR Corporation  
NCR 53C710 SCSI I/O Processor Data Manual,  
order number NCR53C710DM  
Microelectronics Products Division  
1635 Aeroplaza Dr.  
Colorado Springs, CO 80916  
NCR 53C710 SCSI I/O Processor ProgrammerÕs  
Guide, order number NCR53C710PG  
SGS-THOMSON 64K (8K x 8) Timekeeper¨  
SRAM Data Sheet, order number M48T08/18  
SGS-THOMSON Microelectronics  
Group  
Marketing Headquarters  
1000 East Bell Rd.  
Phoenix, AZ 85022-2699  
IndustryPack Logic Interface SpeciÞcation,  
VITA (VMEbus International  
Revision 1.0, order number ANSI/VITA 4-1995 Trade Association)  
7825 E. Gelding Dr., Ste. 104  
Scottsdale, AZ 85260-3415  
Z85230 Serial Communications Controller Data Zilog Inc.  
Sheet  
210 Hacienda Ave.  
Campbell, CA 95008-6609  
Requirements  
These boards are designed to conform to the requirements of the  
following documents:  
VME64 Specification, VITA  
EIA-232-D Serial Interface Specification, EIA  
SCSI Specification, ANSI  
IndustryPack Specification, VITA  
Features  
The following table summarizes the features of the 700/800-series  
MVME162LX VMEmodule.  
1-6  
Introduction  
1
Table 1-1. 700/800-Series MVME162LX: Features  
Feature  
Description  
Microprocessor  
DRAM mezzanine  
32MHz MC68040  
4/8/16MB with parity protection, or 4/8/16/32MB with  
ECC protection  
SRAM  
128KB static RAM (SRAM) with battery backup  
Two JEDEC standard 32-pin DIP PROM sockets  
EPROM  
Flash memory  
One Intel 28F016SA 2M x 8 Flash memory device with  
write protection (optional)  
NVRAM  
8K by 8 Non-Volatile RAM (NVRAM) and time-of-day  
(TOD) clock with battery backup  
Switches  
RESET and ABORT switches  
Status LEDs  
Tick Timers  
Status LEDs for FAIL, RUN, SCON, and FUSES  
Four 32-bit tick timers (in the MC2chip ASIC); two 32-bit  
tick timers (in the VMEchip2 ASIC) for periodic interrupts  
Watchdog timers  
Interrupts  
Two 32-bit watchdog timers (one each in the MC2chip and  
VMEchip2 ASICs)  
Eight software interrupts (for MVME162LX versions that  
have the VMEchip2)  
Serial I/O  
Four serial ports with EIA-232-D interface (serial port  
controllers are the Z85230 chips)  
SCSI I/O  
Optional SCSI Bus interface with DMA  
Ethernet I/O  
IndustryPack I/O  
Optional Ethernet transceiver interface with DMA  
Two IP interfaces with two-channel DMA  
1-7  
Board Level Hardware Description  
1
Table 1-1. 700/800-Series MVME162LX: Features (Continued)  
Feature  
Description  
VMEbus system controller functions  
VMEbus interface to local bus (A24/A32,  
D8/D16/D32/block transfer [D8/D16/D32/D64])  
Local-bus-to-VMEbus interface (A16/A24/A32,  
D8/D16/D32)  
VMEbus interface  
VMEbus interrupter  
VMEbus interrupt handler  
Global control/status register for interprocessor  
communications  
DMA for fast local memory - VMEbus transfers  
(A16/A24/A32, D16/D32/block transfer)  
1-8  
Introduction  
1
Specifications  
Table 1-2 lists the specifications for a 700/800-series MVME162LX  
without IPs.  
Table 1-2. 700/800-Series MVME162LX: Specifications  
Characteristics  
Power requirements  
(with EPROMs; without IPs) +12 Vdc (± 5%), 100 mA maximum  
SpeciÞcations  
+5Vdc (± 5%), 3.5 A typical, 4.5 A maximum  
-12 Vdc (± 5%), 100 mA maximum  
Operating temperature  
0û to 70û C exit air with forced air cooling*  
(see Note)  
Storage temperature  
Relative humidity  
Physical dimensions  
-40û to +85û C  
5% to 90% (noncondensing)  
Double-high VMEboard  
PC board with mezzanine  
module only  
Height  
Depth  
Thickness  
9.2 inches (233 mm)  
6.3 inches (160 mm)  
0.66 inch (17 mm)  
Height  
Depth  
Thickness  
10.3 inches (262 mm)  
7.4 inches (188 mm)  
0.80 inch (20 mm)  
*Refer to Cooling Requirements on page 1-10 and Special Considerations for Elevated-  
Temperature Operation on page 1-10.  
1-9  
 
Board Level Hardware Description  
1
Cooling Requirements  
The Motorola MVME162LX VME Embedded Controller is  
specified, designed, and tested to operate reliably with an incoming  
air temperature range from 0û to 55û C (32û to 131û F) with forced air  
cooling at a velocity typically achievable by using a 100 CFM axial  
fan. Temperature qualification is performed in a standard Motorola  
VME system chassis. Load boards are inserted adjacent to the board  
under test, to simulate a high power density system configuration.  
An assembly of three axial fans, rated at 100 CFM per fan, is placed  
directly under the VME card cage. The incoming air temperature is  
measured between the fan assembly and the card cage, where the  
incoming airstream first encounters the controller under test. Test  
software is executed as the controller is subjected to ambient  
temperature variations. Case temperatures of critical, high power  
density integrated circuits are monitored to ensure that component  
vendorsÕ specifications are not exceeded.  
While the exact amount of airflow required for cooling depends on  
the ambient air temperature and the type, number, and location of  
boards and other heat sources, adequate cooling can usually be  
achieved with 10 CFM and 490 LFM flowing over the controller.  
Less airflow is required to cool the controller in environments  
having lower maximum ambients. Under more favorable thermal  
conditions (refer to Elevated-Temperature Operation below), it may be  
possible to operate the controller reliably at higher than 55û C with  
increased airflow. It is important to note that there are several  
factors, in addition to the rated CFM of the air mover, which  
determine the actual volume and speed of air flowing over the  
controller.  
Special Considerations for Elevated-Temperature Operation  
The following information is for users whose applications for the  
MVME162LX may subject it to high temperatures.  
1-10  
   
Introduction  
1
The MVME162LX uses commercial-grade devices. Therefore, it can  
operate in an environment with ambient air temperatures from 0û C  
to 70û C. Several factors influence the ambient temperature seen by  
components on the MVME162LX. Among them are inlet air  
temperature; airflow characteristics; number, types, and locations  
of IP modules; power dissipation of adjacent boards in the system,  
etc.  
A temperature profile of a comparable board (the MVME172  
embedded controller) was developed in an MVME954A six-slot  
VME chassis. Two such boards, each loaded with one 4MB memory  
mezzanine and two GreenSpring IndustryPack modules, were  
placed in the chassis with one 36W load board installed between  
them. The chassis was placed in a thermal chamber that maintained  
an ambient temperature of 55û C. Measurements showed that the  
fans in the chassis supplied an airflow of approximately 65 LFM  
over the MVME172 boards. Under these conditions, a rise in  
temperature of approximately 10û C between the inlet and exit air  
was observed. The junction temperatures of selected high-power  
devices on the MVME172 were calculated (from case temperature  
measurements) and were found to be within manufacturersÕ  
specified tolerances.  
For elevated-temperature operation, perform similar  
measurements and calculations to determine the actual  
operating margin for your specific environment.  
!
Caution  
To facilitate elevated-temperature operation:  
1. Position the MVME162LX in the chassis to permit maximum  
airflow over the component side of the board.  
2. Do not place boards with high power dissipation next to the  
MVME162LX.  
3. Use low-power IP modules only.  
1-11  
Board Level Hardware Description  
1
FCC Compliance  
The MVME162LX is a board-level product and is meant to be used  
in standard VME applications. As such, it is the responsibility of  
system integrators to to meet the regulatory guidelines pertaining  
to a given application. The MVME162LX has been tested in a  
representative chassis for CE class B EMC certification. Compliance  
was achieved under the following conditions:  
1. Shielded cables on all external I/O ports.  
2. Cable shields connected to earth ground via metal shell  
connectors bonded to a conductive module front panel.  
3. Conductive chassis rails connected to earth ground. This  
provides the path for connecting shields to earth ground.  
4. Front panel screws properly tightened.  
For minimum RF emissions, it is essential that the conditions above  
be implemented. Failure to do so could compromise the FCC  
compliance of the equipment containing the module.  
Manual Terminology  
Throughout this manual, a convention is used which precedes data  
and address parameters by a character identifying the numeric  
format as follows:  
$
dollar  
speciÞes a hexadecimal character  
speciÞes a binary number  
%
&
percent  
ampersand  
speciÞes a decimal number  
For example, Ò12Ó is the decimal number twelve, and ÔÔ$12ÕÕ is the  
decimal number eighteen.  
Unless otherwise specified, all address references are in  
hexadecimal.  
1-12  
Introduction  
1
An asterisk (*) following the signal name for signals which are level  
significant denotes that the signal is true or valid when the signal is  
low.  
An asterisk (*) following the signal name for signals which are edge  
significant denotes that the actions initiated by that signal occur on  
high-to-low transition.  
In this manual, assertion and negation are used to specify forcing a  
signal to a particular state. In particular, assertion and assert refer  
to a signal that is active or true; negation and negate indicate a  
signal that is inactive or false. These terms are used independently  
of the voltage level (high or low) that they represent.  
Data and address sizes are defined as follows:  
A byte is eight bits, numbered 0 through 7, with bit 0 being the  
least significant.  
A two-byte is 16 bits, numbered 0 through 15, with bit 0 being  
the least significant. For the MVME162LX and other CISC  
modules, this is called a word.  
A four-byte is 32 bits, numbered 0 through 31, with bit 0 being  
the least significant. For the MVME162LX and other CISC  
modules, this is called a longword.  
The terms control bit, status bit, true and false are used extensively in  
this document.  
The term control bit describes a bit in a register that can be set and  
cleared under software control. The term true indicates that a bit is  
in the state that enables the function it controls. The term false  
indicates that the bit is in the state which disables the function it  
controls. In all tables, the terms 0 and 1 describe the actual value  
that should be written to the bit, or the value that it yields when  
read.  
The term status bit describes a bit in a register that reflects a specific  
condition. The status bit is read by software to determine  
operational or exception conditions.  
1-13  
Board Level Hardware Description  
1
Block Diagram  
Refer to Figure 1-1 on page 1-15 for a block diagram of the 700/800-  
series MVME162LX.  
Functional Description  
This section contains a functional description of the major blocks on  
the MVME162LX.  
Front Panel Switches and Indicators  
There are two switches and four LEDs on the front panel of the  
MVME162LX.  
RESET switch. Resets all onboard devices (including IP  
modules, if installed) and drives SYSRESET* if the board is  
system controller. The RESET switch may be disabled by  
software.  
ABORT switch. When enabled by software, the ABORT switch  
generates an interrupt at a user-programmable level. It is  
normally used to abort program execution and return to the  
162Bug debugger.  
FAIL LED (red). Lights when the BRDFAIL* signal line is  
active or when the processor is halted. Part of DS1.  
RUN LED (green or amber). Lights when the local bus TIP*  
signal line is low. This indicates one of the local bus masters  
is executing a local bus cycle. Part of DS1.  
SCON LED (green). Lights when the VMEchip2 in the  
MVME162LX is the VMEbus system controller. Part of DS2.  
FUSES LED (green). Lights when +5Vdc, +12Vdc, and -12Vdc  
power is available to the LAN and SCSI interfaces and IP  
connectors. Part of DS2.  
1-14  
Functional Description  
1
Figure 1-1. MVME162LX Block Diagram  
1-15  
 
Board Level Hardware Description  
1
Data Bus Structure  
The local bus on the MVME162LX is a 32-bit synchronous bus that  
is based on the MC68040 bus, and which supports burst transfers  
and snooping. The various local bus master and slave devices use  
the local bus to communicate. The local bus is arbitrated by priority  
type arbiter and the priority of the local bus masters from highest to  
lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU. In the  
general case, any master can access any slave; however, not all  
combinations pass the common sense test. Refer to the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide and  
to the user's guide for each device to determine its port size, data  
bus connection, and any restrictions that apply when accessing the  
device.  
Microprocessor  
The MVME162LX is built with a 32MHz MC68040 microprocessor.  
The MC68040 has on-chip instruction and data caches, optional  
high drive I/O buffers, and a floating point processor. The  
MC68040 supports cache coherency in multi-master applications  
with dedicated on-chip bus snooping logic. Refer to the M68040  
reference manual for detailed information.  
MC68040 Cache  
The MVME162LX local bus masters (VMEchip2, MC68040, 53C710  
SCSI controller, and 82596CA Ethernet controller) have  
programmable control of the snoop/caching mode. The IP DMA  
local bus masterÕs snoop control function is controlled by jumper  
settings at J19. J19 controls the state of the snoop control signals for  
all IP DMA transfers (including the IP DMA which is executed  
when the DMA control registers are updated during IP DMA  
operation in the command chaining mode). The MVME162LX local  
bus slaves that support MC68040 bus snooping are defined in the  
Local Bus Memory Map table later in this chapter.  
1-16  
Functional Description  
1
No-VMEbus-Interface Option  
The 700/800-series MVME162LX may be operated as an embedded  
controller without the VMEbus interface. For this option, the  
VMEchip2 ASIC and the VMEbus buffers are not populated. Also,  
the bus grant daisy chain and the interrupt acknowledge daisy  
chain have zero-ohm bypass resistors installed.  
To support this feature, certain logic in the VMEchip2 has been  
duplicated in the MC2chip. This logic is inhibited in the MC2chip  
when the VMEchip2 is present. The enables for these functions are  
controlled by software and MC2chip hardware initialization.  
Note that MVME162LX models ordered without the VMEbus  
interface are shipped with Flash memory blank (the factory uses the  
VMEbus to program the Flash memory with debugger code). To  
use the 162Bug package, MVME162Bug, be sure that jumper header  
J21 is configured for the EPROM memory map. Refer to Chapters 2  
and 3 for further details.  
Contact your local Motorola sales office for ordering information.  
Memory Options  
The following memory options are used on the different versions of  
700/800-series MVME162LX boards.  
DRAM Options  
The MVME162LX offers the following DRAM options:  
4, 8, or 16MB shared DRAM with programmable parity on a  
mezzanine module  
4, 8, 16, or 32MB ECC DRAM on a mezzanine module  
The DRAM architecture for non-ECC memory is non-interleaved  
for 4 or 8MB and interleaved for 16MB. Parity protection is enabled  
with interrupts or bus exception when a parity error is detected.  
1-17  
Board Level Hardware Description  
1
DRAM performance is specified in the section on the DRAM  
Memory Controller in the MC2chip Programming Model in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide.  
The DRAM map decoder may be programmed to accommodate  
different base address(es) and sizes of mezzanine boards. The  
onboard DRAM is disabled by a local bus reset and must be  
programmed before the DRAM may be accessed. Refer to the  
MC2chip and MCECC descriptions in the MVME162LX Embedded  
Controller ProgrammerÕs Reference Guide for detailed programming  
information.  
Most DRAM devices require some number of access cycles before  
the DRAMs are fully operational. Normally this requirement is met  
by the onboard refresh circuitry and normal DRAM initialization.  
However, software should insure a minimum of 10 initialization  
cycles are performed to each bank of RAM.  
SRAM Options  
The MVME162LX provides 128KB of 32-bit-wide onboard static  
RAM in a single non-interleaved architecture with onboard battery  
backup. The SRAM arrays are not parity protected.  
The SRAM battery backup function is provided by a Dallas  
DS1210S device. The DS1210S supports primary and secondary  
power sources. When the main board power fails, the DS1210S  
selects the source with the higher voltage. If one source should fail,  
the DS1210S switches to the redundant source. Each time the board  
is powered up, the DS1210S checks power sources and if the voltage  
of the backup source is less than two volts, the second memory  
cycle is blocked. This allows software to provide an early warning  
to avoid data loss. Because the DS1210S may block the second  
access, software should do at least two accesses before relying on  
the data.  
The MVME162LX provides jumpers (on J14) that allow either  
power source of the DS1210S to be connected to the VMEbus +5V  
STDBY pin or to one cell of the onboard battery. For example, the  
primary system backup source may be a battery connected to the  
1-18  
Functional Description  
1
VMEbus +5V STDBY pin and the secondary source may be the  
onboard battery. If the system source should fail or the board is  
removed from the chassis, the onboard battery takes over. Refer to  
Chapter 2 for the jumper configurations.  
For proper operation of the SRAM, some jumper  
combination must be installed on the respective Backup  
Power Source Select Header (J14). If one of the jumpers  
is used to select the battery, the battery must be installed  
on the MVME162LX. The SRAM may malfunction if  
inputs to the DS1210S are left unconnected.  
!
Caution  
The SRAM is controlled by the MC2chip, and the access time is  
programmable. Refer to the MC2chip description in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for  
more detail.  
About the Battery  
The power source for the onboard SRAM is a RAYOVAC FB1225  
battery with two BR1225-type lithium cells which is socketed for  
easy removal and replacement. A small capacitor is provided to  
allow the battery to be quickly replaced without data loss.  
The lifetime of the battery is very dependent on the ambient  
temperature of the board and the power-on duty cycle. The lithium  
battery supplied on the MVME162LX should provide at least two  
years of backup time with the board powered off and with an  
ambient temperature of 40° C. If the power-on duty cycle is 50% (the  
board is powered on half of the time), the battery lifetime is four  
years. At lower ambient temperatures, the backup time is greatly  
extended.  
When a board is stored, the battery should be disconnected to  
prolong battery life. This is especially important at high ambient  
temperatures. The MVME162LX is shipped with the batteries  
disconnected (i.e., with VMEbus +5V standby voltage selected as  
both primary and secondary power source). If you intend to use the  
1-19  
Board Level Hardware Description  
1
battery as a power source, whether primary or secondary, it is  
necessary to reconfigure the jumpers on J14 before installing the  
board. Refer to SRAM Backup Power Source Select Header (J14) on  
page 2-6 for available jumper configurations  
The power leads from the battery are exposed on the solder side of  
the board. The board should not be placed on a conductive surface  
or stored in a conductive bag unless the battery is removed.  
Lithium batteries incorporate inflammable materials  
such as lithium and organic solvents. If lithium batteries  
are mistreated or handled incorrectly, they may burst  
open and ignite, possible resulting in injury and/or fire.  
When dealing with lithium batteries, carefully follow  
the precautions listed below in order to prevent  
accidents.  
!
Warning  
Do not short circuit.  
Do not disassemble, deform, or apply excessive pressure.  
Do not heat or incinerate.  
Do not apply solder directly.  
Do not use different models, or new and old batteries  
together.  
Do not charge.  
Always check proper polarity.  
To remove the battery from the module, carefully pull the battery  
from the socket (BT1, shown in Figure 2-1).  
Before installing a new battery, ensure that the battery pins are  
clean. Note the battery polarity and press the battery into the  
socket. No soldering is required.  
1-20  
Functional Description  
1
EPROM and Flash Memory  
The MVME162LX may be ordered with 2MB of Flash memory and  
two EPROM sockets ready for the installation of the EPROMs,  
which may be ordered separately. Flash memory is a single Intel  
28F016SA device organized in a 2Mbit x 8 configuration. The  
EPROM locations are standard JEDEC 32-pin DIP sockets that  
accommodate three jumper-selectable densities (256 Kbit x 8;  
512 Kbit x 8, the factory default; 1 Mbit x8). A jumper setting (GPI3,  
pins 7-8 on J21), allows reset code to be fetched either from Flash  
memory (GPI3 installed) or from EPROMs (GPI3 removed).  
Battery Backed Up RAM and Clock  
An M48T58 RAM and clock chip is used on the MVME162LX. This  
chip provides a time-of-day clock, oscillator, crystal, power fail  
detection, memory write protection, 8KB of RAM, and a battery in  
one 28-pin package. The clock provides seconds, minutes, hours,  
day, date, month, and year in BCD 24-hour format. Corrections for  
28-, 29- (leap year), and 30-day months are automatically made. No  
interrupts are generated by the clock. Although the M48T58 is an 8  
bit device, the interface provided by the MC2chip supports  
8-, 16-, and 32-bit accesses to the M48T58. Refer to the MC2chip in  
the MVME162LX Embedded Controller ProgrammerÕs Reference Guide  
and to the M48T58 data sheet for detailed programming and  
battery life information.  
VMEbus Interface and VMEchip2  
The optional VMEchip2 provides the local-bus-to-VMEbus  
interface, the VMEbus-to-local-bus interface, and the DMA  
controller functions of the local VMEbus. The VMEchip2 also  
provides the VMEbus system controller functions. Refer to the  
VMEchip2 description in the MVME162LX Embedded Controller  
ProgrammerÕs Reference Guide for detailed programming  
information.  
1-21  
Board Level Hardware Description  
1
Note that the ABORT switch logic in the VMEchip2 is not used. The  
GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-  
0 are not used. The ABORT switch interrupt is integrated into the  
MC2chip ASIC at location $FFF42043. The GPI inputs are  
integrated into the MC2chip ASIC at location $FFF4202C bits 23-16.  
I/O Interfaces  
The MVME162LX provides onboard I/O for many system  
applications. The I/O functions include serial ports, IndustryPack  
(IP) interfaces, an optional LAN Ethernet transceiver interface, and  
an optional SCSI mass storage interface.  
Serial Communications Interface  
The MVME162LX uses two Zilog Z85230 serial port controllers to  
implement the four serial communications interfaces. Each  
interface supports CTS, DCD, RTS, and DTR control signals, as well  
as the TXD and RXD transmit/receive data signals. Because the  
serial clocks are omitted in the MVME162LX implementation, serial  
communications are strictly asynchronous. The MVME162LX  
hardware supports serial baud rates of 110b/s to 38.4Kb/s.  
The Z85230 supplies an interrupt vector during interrupt  
acknowledge cycles. The vector is modified based upon the  
interrupt source within the Z85230. Interrupt request levels are  
programmed via the MC2chip. Refer to the Z85230 data sheet listed  
in this chapter, and to the MC2chip Programming Model in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide, for  
information.  
The Z85230s are interfaced as DTE (data terminal equipment) with  
EIA-232-D signal levels. The four serial ports are routed to four RJ-  
45 connectors on the MVME162LX front panel.  
1-22  
Functional Description  
1
IndustryPack (IP) Interfaces  
Up to two IP modules may be installed on the 700/800-series  
MVME162LX as an option. The interface between the IPs and  
MVME162LX is the IndustryPack Interface Controller (IP2) ASIC.  
Access to the IPs is provided by two 3M connectors located behind  
the MVME162LX front panel. Refer to the chapter on the IP2 in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for  
detailed features of the IP interface.  
Optional Ethernet Interface  
The MVME162LX uses the 82596CA to implement the Ethernet  
transceiver interface. The 82596CA accesses local RAM using DMA  
operations to perform its normal functions. Because the 82596CA  
has small internal buffers and the VMEbus has an undefined  
latency period, buffer overrun may occur if the DMA is  
programmed to access the VMEbus. Therefore, the 82596CA should  
not be programmed to access the VMEbus.  
Every MVME162LX that has the Ethernet interface is assigned an  
Ethernet Station Address. The address is $08003E2XXXXX where  
XXXXX is the unique 5-nibble number assigned to the board (i.e.,  
every MVME162LX has a different value for XXXXX).  
Each board has an Ethernet Station Address displayed on a label  
attached to the VMEbus P2 connector. In addition, the six bytes  
including the Ethernet address are stored in the configuration area  
of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM.  
The upper four bytes (08003E2X) are read at $FFFC1F2C; the lower  
two bytes (XXXX) are read at $FFFC1F30. The debugger firmware  
has the capability to retrieve or set the Ethernet address.  
If the data in the BBRAM is lost, use the number on the label on  
backplane connector P2 to restore it.  
The Ethernet transceiver interface is located on the MVME162LX  
main board, and the industry standard connector is located on its  
front panel.  
1-23  
Board Level Hardware Description  
1
Support functions for the 82596CA are provided by the MC2chip.  
Refer to the 82596CA user's guide and to the MC2chip description  
in the MVME162LX Embedded Controller ProgrammerÕs Reference  
Guide for detailed programming information.  
Optional SCSI Interface  
The MVME162LX supports mass storage subsystems through the  
industry-standard SCSI bus. These subsystems may include hard  
and floppy disk drives, streaming tape drives, and other mass  
storage devices. The SCSI interface is implemented using the NCR  
53C710 SCSI I/O controller.  
Support functions for the 53C710 are provided by the MC2chip.  
Refer to the NCR 53C710 user's guide and to the MC2chip  
description in the MVME162LX Embedded Controller ProgrammerÕs  
Reference Guide for detailed programming information.  
SCSI Termination  
It is important that the SCSI bus be properly terminated at both  
ends.  
The MVME162LX main board provides terminators for the SCSI  
bus. The SCSI terminators are enabled/disabled by a jumper on  
header J12. If the SCSI bus ends at the MVME162LX, a jumper must  
be installed between J12 pins 1 and 2.  
The FUSES LED (part of DS2) on the MVME162LX front panel  
monitors the SCSI bus TERMPWR signal in addition to LAN power  
and IndustryPack power; the FUSES LED lights when all fuses are  
operational. The fuses are solid-state devices that reset when the  
short is removed.  
Because any device on the SCSI bus can provide TERMPWR, the  
FUSES LED does not directly indicate the condition of the fuse.  
1-24  
Functional Description  
1
Local Resources  
The MVME162LX includes many resources for the local processor.  
These include tick timers, software-programmable hardware  
interrupts, watchdog timer, and local bus timeout.  
Programmable Tick Timers  
Six 32-bit programmable tick timers with 1µs resolution are  
provided, four in the MC2chip and two in the optional VMEchip2.  
The tick timers may be programmed to generate periodic interrupts  
to the processor. Refer to the VMEchip2 and MC2chip descriptions  
in the MVME162LX Embedded Controller ProgrammerÕs Reference  
Guide for detailed programming information.  
Watchdog Timer  
A watchdog timer function is provided in both the MC2chip and  
the optional VMEchip2. The timers operate independently but in  
parallel. When the watchdog timers are enabled, they must be reset  
by software within the programmed time or they will time out. The  
watchdog timers may be programmed to generate a SYSRESET  
signal, local reset signal, or board fail signal if they time out. Refer  
to the VMEchip2 and MC2chip descriptions in the MVME162LX  
Embedded Controller ProgrammerÕs Reference Guide for detailed  
programming information.  
The watchdog timer logic is duplicated in the VMEchip2 and  
MC2chip ASICs. Because the watchdog timer function in the  
VMEchip2 is a superset of that function in the MC2chip (system  
reset function), the timer in the VMEchip2 is used in all cases except  
for the version of the MVME162LX which does not include the  
VMEbus interface ( described under ÒNo-VMEbus-Interface  
optionÓ).  
1-25  
Board Level Hardware Description  
1
Software-Programmable Hardware Interrupts  
Eight software-programmable hardware interrupts are provided  
by the VMEchip2. These interrupts allow software to create a  
hardware interrupt. Refer to the VMEchip2 description in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for  
detailed programming information.  
Local Bus Timeout  
The MVME162LX provides a timeout function in the VMEchip2  
and the MC2chip for the local bus. When the timer is enabled and a  
local bus access times out, a Transfer Error Acknowledge (TEA)  
signal is sent to the local bus master. The timeout value is software-  
selectable for 8 µsec, 64 µsec, 256 µsec, or infinity. The local bus  
timer does not operate during VMEbus bound cycles. VMEbus  
bound cycles are timed by the VMEbus access timer and the  
VMEbus global timer. Refer to the VMEchip2 and the MC2chip  
descriptions in the MVME162LX Embedded Controller ProgrammerÕs  
Reference Guide for detailed programming information.  
The MC2chip also provides local bus timeout logic for  
MVME162LXs without the optional VMEbus interface (i.e., without  
the VMEchip2 ASIC).  
The access timer logic is duplicated in the VMEchip2 and MC2chip  
ASICs. Because the local bus timer in the VMEchip2 can detect an  
offboard access and the MC2chip local bus timer cannot, the timer  
in the VMEchip2 is used in all cases except for the version of the  
MVME162LX which does not include the VMEbus interface  
(described under ÔÔNo-VMEbus-Interface optionÓ).  
1-26  
Functional Description  
1
Local Bus Arbiter  
The local bus arbiter implements a fixed priority, which is  
described in the following table.  
Table 1-3. Local Bus Arbitration Priority  
Device  
Priority  
Note  
LAN  
0
1
2
3
Highest  
IndustryPack DMA  
SCSI  
. . .  
VMEbus  
Next lowest  
MC68040  
Connectors  
The MVME162LX has two 96-position DIN connectors: P1 and P2.  
P1 rows A, B, C, and P2 row B provide the VMEbus  
interconnection. P2 rows A and C are not used.  
The MVME162LX has a 20-pin connector J2 mounted behind the  
front panel. When the MVME162LX board is enclosed in a chassis  
and the front panel is not visible, this connector allows the reset,  
abort and LED functions to be extended to the control panel of the  
system, where they are visible.  
The serial ports on the MVME162LX are connected to four 8-pin RJ-  
45 female connectors (J17) on the front panel. The two IPs connect  
to the MVME162LX by two pairs of 50-pin connectors. Two 50-pin  
connectors behind the front panel are for external connections to IP  
signals. The memory mezzanine board is plugged into two 100-pin  
connectors. The Ethernet LAN connector (J9) is a 15-pin socket  
connector mounted on the front panel. The SCSI connector (J23) is  
a 68-pin socket connector mounted on the front panel.  
1-27  
Board Level Hardware Description  
1
Memory Maps  
There are two points of view for memory maps: 1) the mapping of  
all resources as viewed by local bus masters (local bus memory  
map), and 2) the mapping of onboard resources as viewed by  
external masters (VMEbus memory map).  
The memory and I/O maps that are described in the next three  
tables are correct for all local bus masters. There is some address  
translation capability in the VMEchip2. This allows multiple  
MVME162LXs on the same VMEbus with different virtual local bus  
maps as viewed by different VMEbus masters.  
Local Bus Memory Map  
The local bus memory map is split into different address spaces by  
the transfer type (TT) signals. The local resources respond to the  
normal access and interrupt acknowledge codes.  
Normal Address Range  
The memory map of devices that respond to the normal address  
range is shown in the following tables. The normal address range is  
defined by the Transfer Type (TT) signals on the local bus. On the  
MVME162LX, Transfer Types 0, 1, and 2 define the normal address  
range. Table 1-4 is the entire map from $00000000 to $FFFFFFFF.  
Many areas of the map are user-programmable, and suggested uses  
are shown in the table. The cache inhibit function is programmable  
in the MC68040 MMU (memory management unit). The onboard  
1-28  
Memory Maps  
1
I/O space must be marked cache inhibit and serialized in its page  
table. Table 1-5 on page 1-31 further defines the map for the local  
I/O devices.  
Table 1-4. Local Bus Memory Map  
Software  
Cache  
Inhibit  
Devices  
Accessed  
Port  
Width  
Address Range  
Programmable  
Size  
Notes  
DRAM on parity  
mezzanine  
D32  
D32  
4MB-16MB  
4MB-32MB  
N
N
2
2
Programmable  
DRAM on ECC  
mezzanine  
Programmable  
Programmable  
Onboard SRAM  
D32  
128KB  
--  
N
?
2
4
VMEbus  
A32/A24  
D32-D16  
Programmable  
IP_a memory  
IP_b memory  
Flash/EPROM  
EPROM/Flash  
Not decoded  
D32-D8  
D32-D8  
D32  
64KB-8MB  
64KB-8MB  
2MB  
?
2, 4  
2, 4  
1, 5  
5
Programmable  
?
$FF800000-$FF9FFFFF  
$FFA00000-$FFBFFFFF  
$FFC00000-$FFDFFFFF  
$FFE00000-$FFE1FFFF  
N
N
N
N
D32  
2MB  
D32  
2MB  
Onboard SRAM  
default  
D32  
128KB  
1-29  
 
Board Level Hardware Description  
1
Table 1-4. Local Bus Memory Map (Continued)  
Software  
Cache  
Inhibit  
Devices  
Accessed  
Port  
Width  
Address Range  
Size  
Notes  
$FFE80000-$FFEFFFFF  
$FFF00000-$FFFEFFFF  
Not decoded  
--  
512KB  
878KB  
N
Y
6
3
Local I/O  
devices  
D32-D8  
(see next table)  
$FFFF0000-$FFFFFFFF  
VMEbus A16  
D32/D1  
6
64KB  
?
2, 4  
Notes  
1. Devices mapped at $FFF80000-$FFF9FFFF also appear at $00000000- $001FFFFF when the  
ROM0 bit in the MC2chip EPROM control register is high (ROM0=1). ROM0 is set to 1 after  
each reset. The ROM0 bit must be cleared before other resources (DRAM or SRAM) can be  
mapped in this range ($00000000 - $001FFFFF).  
The EPROM/Flash memory map is also controlled by the EPROM size and by control bit  
V19 in the MC2chip ASIC. Refer to the EPROM/Flash configuration tables in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for further details.  
2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the  
MC2chip, the local-to-VMEbus decoders are programmed in the VMEchip2, and the IP  
memory space is programmed in the IP2.  
3. Size is approximate.  
4. Cache inhibit depends on the devices in the area mapped.  
5. The EPROM and Flash are dynamically sized by the MC2chip ASIC from an 8-bit private  
bus to the 32-bit MPU local bus.  
6. These areas are not decoded unless one of the programmable decoders is initialized to  
decode this space. If they are not decoded and the local timer is enabled, an access to this  
address range will generate a local bus timeout.  
The next table describes the ÔÔLocal I/O DevicesÕÕ portion of the  
local bus main memory map.  
1-30  
Memory Maps  
1
Note The IP2 chip on the MVME162LX supports up to four  
IP interfaces, designated IP_a through IP_d. The  
700/800-series MVME162LX itself accommodates two  
IPs: IP_a and IP_b. In the following map, the segments  
applicable to IP_c and IP_d are not used in the 700/800-  
series MVME162LX.  
Table 1-5. Local I/O Devices Memory Map  
Address Range  
Devices Accessed  
Port  
Size Notes  
Width  
$FFF00000 - $FFF3FFFF  
$FFF40000 - $FFF400FF  
$FFF40100 - $FFF401FF  
$FFF40200 - $FFF40FFF  
$FFF41000 - $FFF41FFF  
$FFF42000 - $FFF42FFF  
$FFF43000 - $FFF430FF  
$FFF43100 - $FFF431FF  
$FFF43200 - $FFF43FFF  
$FFF44000 - $FFF44FFF  
$FFF45000 - $FFF457FF  
$FFF45800 - $FFF45FFF  
$FFF46000 - $FFF46FFF  
$FFF47000 - $FFF47FFF  
$FFF48000 - $FFF57FFF  
$FFF58000 - $FFF5807F  
$FFF58080 - $FFF580FF  
$FFF58100 - $FFF5817F  
$FFF58180 - $FFF581FF  
Reserved  
- -  
D32  
D32-D8  
- -  
256KB  
256B  
256B  
3.5KB  
4KB  
4
VMEchip2 (LCSR)  
VMEchip2 (GCSR)  
Reserved  
1, 3  
1, 3  
4, 5  
4
Reserved  
- -  
MC2chip  
D32-D8  
D8  
4KB  
1
MCECC #1  
256B  
256B  
1, 8  
1, 8  
MCECC #2  
D8  
MCECCs (repeated)  
Reserved  
- -  
3.5KB 1, 5, 8  
- -  
8KB  
2KB  
4
1, 2  
1, 2  
1, 6  
1
SCC #1 (Z85230)  
SCC #2 (Z85230)  
LAN (82596CA)  
SCSI (53C710)  
Reserved  
D8  
D8  
2KB  
D32  
D32-D8  
- -  
4KB  
4KB  
64KB  
128B  
128B  
128B  
128B  
4
IP2 IP_a I/O  
IP2 IP_a ID  
D16  
D16  
D16  
D16  
1
1
IP2 IP_b I/O  
IP2 IP_b ID Read  
1
1
1-31  
 
Board Level Hardware Description  
1
Table 1-5. Local I/O Devices Memory Map (Continued)  
Address Range  
Devices Accessed  
Port  
Size Notes  
Width  
$FFF58200 - $FFF5827F  
$FFF58280 - $FFF582FF  
$FFF58300 - $FFF5837F  
$FFF58380 - $FFF583FF  
$FFF58400 - $FFF584FF  
$FFF58500 - $FFF585FF  
$FFF58600 - $FFF586FF  
$FFF58700 - $FFF587FF  
$FFF58800 - $FFF5887F  
$FFF58880 - $FFF588FF  
$FFF58900 - $FFF5897F  
$FFF58980 - $FFF589FF  
IP2 IP_c I/O  
D16  
D16  
D16  
D16  
128B  
128B  
128B  
128B  
7
7
7
7
1
7
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IP2 IP_c ID  
IP2 IP_d I/O  
IP2 IP_d ID Read  
IP2 IP_ab I/O  
IP2 IP_cd I/O  
IP2 IP_ab I/O Repeated  
IP2 IP_cd I/O Repeated  
Reserved  
D32-D16 256B  
D32-D16 256B  
D32-D16 256B  
D32-D16 256B  
- -  
- -  
128B  
128B  
128B  
128B  
128B  
128B  
128B  
128B  
256B  
256B  
256B  
256B  
2KB  
Reserved  
Reserved  
- -  
Reserved  
- -  
$FFF58A00 - $FFF58A7F Reserved  
$FFF58A80 - $FFF58AFF Reserved  
- -  
- -  
$FFF58B00 - $FFF58B7F  
$FFF58B80 - $FFF58BFF  
Reserved  
Reserved  
- -  
- -  
$FFF58C00 - $FFF58CFF Reserved  
$FFF58D00 - $FFF58DFF Reserved  
- -  
- -  
$FFF58E00 - $FFF58EFF  
$FFF58F00 - $FFF58FFF  
Reserved  
Reserved  
- -  
- -  
$FFFBC000 - $FFFBC01F IP2 Registers  
$FFFBC800 - $FFFBC81F Reserved  
D32-D8  
- -  
2KB  
1-32  
Memory Maps  
1
Table 1-5. Local I/O Devices Memory Map (Continued)  
Address Range  
Devices Accessed  
Port  
Size Notes  
Width  
$FFFBD000 - $FFFBFFFF Reserved  
- -  
12KB  
4
1, 9  
4
$FFFC0000 - $FFFCFFFF M48T58 (BBRAM, TOD Clock) D32-D8 64KB  
$FFFD0000 - $FFFEFFFF Reserved  
Notes  
- -  
128KB  
1. For a complete description of the register bits, refer to the data sheet for the specific chip.  
For a more detailed memory map, refer to the MVME162LX Embedded Controller  
ProgrammerÕs Reference Guide.  
2. The SCC is an 8-bit device located on an MC2chip private data bus. Byte access is required.  
3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate  
with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR  
may be 8, 16 or 32 bits. Byte reads should be used to read the interrupt vector.  
4. This area does not return an acknowledge signal. If the local bus timer is enabled, the  
access times out and is terminated by a TEA signal.  
5. Size is approximate.  
6. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and  
lower word second.  
7. Not used.  
8. To use this area, the ECC mezzanine board must be installed. If it is not installed, no  
acknowledge signal is returned; if the local bus timer is enabled, the access times out and  
is terminated by a TEA signal.  
9. Repeats on 8KB boundaries.  
1-33  
Board Level Hardware Description  
1
VMEbus Memory Map  
This section describes the mapping of local resources as viewed by  
VMEbus masters. Default addresses for the slave, master, and  
GCSR address decoders are provided by the ENV command. Refer  
to Appendix A.  
VMEbus Accesses to the Local Bus  
The VMEchip2 includes a user-programmable map decoder for the  
VMEbus-to-local-bus interface. The map decoder allows you to  
program the starting and ending address and the modifiers that the  
MVME162LX responds to.  
VMEbus Short I/O Memory Map  
The VMEchip2 includes a user-programmable map decoder for the  
GCSR. The GCSR map decoder allows you to program the starting  
address of the GCSR in the VMEbus short I/O space.  
1-34  
2Hardware Preparation and  
Installation  
2
Introduction  
This chapter provides unpacking instructions, hardware  
preparation guidelines, and installation instructions for the  
700/800-series MVME162LX VME Embedded Controller.  
Unpacking Instructions  
Note If the shipping carton is damaged upon receipt, request  
that the carrier's agent be present during the unpacking  
and inspection of the equipment.  
Unpack the equipment from the shipping carton. Refer to the  
packing list and verify that all items are present. Save the packing  
material for storing and reshipping of equipment.  
Avoid touching areas of integrated circuitry; static  
discharge can damage circuits.  
!
Caution  
Hardware Preparation  
To select the desired configuration and ensure proper operation of  
the MVME162LX, certain option modifications may be necessary  
before installation. The MVME162LX provides software control for  
most of these options. Some options cannot be modified in  
software, and consequently are set by installing or removing  
jumpers on headers. Most other modifications are performed by  
setting bits in control registers after the MVME162LX has been  
installed in a system. (The MVME162LX registers are described in  
2-1  
Hardware Preparation and Installation  
Chapter 4, and/or in the MVME162FX Embedded Controller  
Programmer's Reference Guide as listed in Related Documentation in  
2
Chapter 1.)  
Figure 2-1 illustrates the placement of the switches, jumper  
headers, connectors, and LED indicators on the MVME162LX.  
Manually configurable items on the board are listed in the  
following table. Default settings are enclosed in brackets.  
Table 2-1. Jumper Settings  
Jumper  
Function  
Settings  
Not system controller.  
System controller.  
System  
controller  
selection  
No jumper  
[1-2]  
J1  
2-3  
Auto system controller.  
IP bus clock  
selection  
[1-2]  
2-3  
8MHz clock.  
32MHz clock.  
J11  
J12  
SCSI  
termination  
No jumper  
[1-2]  
Onboard terminators disabled.  
Onboard terminators enabled.  
No jumper  
[1-3, 2-4]  
3-5, 4-6  
1-3, 4-6  
3-5, 2-4  
Backup power disabled.  
SRAM backup  
power source  
selection  
Primary : VMEbus +5V STBY Ñ secondary : VMEbus +5V STBY.  
Primary : onboard battery Ñ secondary : onboard battery.  
Primary : VMEbus +5V STBY Ñ secondary : onboard battery.  
Primary : onboard battery Ñ secondary : VMEbus +5V STBY.  
J14  
Flash write  
protection  
[No jumper] Flash write protection on (writes disabled).  
J16  
J18  
J19  
1-2  
Flash write protection off (writes enabled).  
IP bus strobe  
selection  
No jumper  
[1-2]  
Strobe disconnected.  
Strobe connected.  
IP DMA snoop  
selection  
1-2, no jumper Snoop enabled (pins 1-2 = donÕt care).  
[1-2, 3-4] Snoop inhibited.  
3-4, 9-11, 10-12 256K x 8 EPROMs.  
[5-6, 9-11, 8-10] 512K x 8 EPROMs.  
EPROM/Flash  
conÞguration  
J20  
J21  
7-9, 8-10  
1M x 8 EPROMs.  
1-2, 7-9, 8-10 1M x 8 EPROMs (on-board Flash disabled).  
General-  
purpose  
readable jumper  
conÞguration  
[No jumper] EPROM selected.  
7-8  
Flash selected.  
Other headers are user-deÞnable (see description).  
2-2  
Hardware Preparation  
MVME162LX embedded controllers are factory tested and shipped  
with the default configurations listed above and described in the  
following sections. The MVME162LXÕs required and factory-  
installed debug monitor, MVME162Bug (162Bug), operates with  
those factory settings.  
2
System Controller Select Header (J1)  
The MVME162LX is factory-configured as a VMEbus system  
controller by a jumper across J1 pins 1 and 2. If you select the  
ÔÔautomaticÕÕ system controller function by moving the jumper to J1  
pins 2 and 3, the MVME162LX determines whether it is the system  
controller by its position on the bus. If the board is in the first slot  
from the left, it configures itself as the system controller. If the  
MVME162LX is not to be system controller under any  
circumstances, remove the jumper from J1. When the board is  
functioning as system controller, the SCON LED is turned on.  
Note For MVME162LXs without the optional VMEbus  
interface (i.e., with no VMEchip2), the jumper may be  
installed or removed without affecting normal  
operation.  
J1  
J1  
J1  
1
2
3
1
2
3
1
2
3
Not system controller  
System Controller  
(Factory  
Auto system controller  
Configuration)  
2-3  
Hardware Preparation and Installation  
2
MVME  
162-7XX  
FAIL  
RUN  
DS1  
DS2  
FUSES  
SCON  
ABORT  
RESET  
Figure 2-1. MVME162LX Board Layout  
2-4  
Hardware Preparation  
IP Bus Clock Header (J11)  
2
J11 selects the speed of the IP bus clock. You can either set the IP bus  
clock to 8MHz or allow it to match the the local bus clock, which is  
32MHz for the MC68040. The factory configuration has a jumper  
between J11 pins 1 and 2 for an 8MHz clock.  
If the jumper is installed between J11 pins 2 and 3, the IP bus clock  
speed is the same as that of the MC68040 bus clock, that is 32MHz,  
allowing the IP module to run with a 32MHz MPU. Regardless of  
the IP bus clock setting, all IP ports operate at the same speed.  
The IP32 CSR bit (IP2 chip, register at offset $1D, bit 0)  
must be set to correspond to the jumper setting. This is  
cleared (0) for 8MHz, or set (1) for 32MHz. If the jumper  
and the bit are not configured the same, the board may  
not run properly.  
!
Caution  
J11  
J11  
1
2
3
1
2
3
8MHz IP Bus Clock  
(Factory configuration)  
32MHz IP Bus Clock  
(from MPU Bus Clock)  
2-5  
Hardware Preparation and Installation  
SCSI Terminator Enable Header (J12)  
2
The MVME162LX provides terminators for the SCSI bus. The SCSI  
terminators are enabled/disabled by a jumper on header J12. The  
SCSI terminators may be configured as follows.  
J12  
J12  
1
2
1
2
Onboard SCSI Bus Terminator Enabled  
(Factory Configuration)  
Onboard SCSI Bus Terminator Disabled  
Note If the MVME162LX is to be used at one end of the SCSI  
bus, the SCSI bus terminators must be enabled.  
SRAM Backup Power Source Select Header (J14)  
Header J14 determines the source for onboard static RAM backup  
power on the MVME162LX.  
The following backup power configurations are available for  
onboard SRAM through header J14. In the factory configuration,  
the VMEbus +5V standby voltage serves as primary and secondary  
power source (the onboard battery is disconnected).  
Note For MVME162LXs without the optional VMEbus  
interface (i.e., without the VMEchip2 ASIC), you must  
select the onboard battery as the backup power source.  
2-6  
Hardware Preparation  
Removing all jumpers may temporarily disable the  
SRAM. Do not remove all jumpers from J14, except for  
storage.  
2
!
Caution  
J14  
J14  
J14  
5
6
5
5
1
1
2
1
6
6
2
2
Primary Source VMEbus +5V STBY  
Secondary Source VMEbus +5V STBY  
(Factory configuration)  
Backup Power Disabled  
(For storage only)  
Primary Source Onboard Battery  
Secondary Source Onboard Battery  
J14  
J14  
5
6
5
1
1
2
6
2
Primary Source VMEbus +5V STBY  
Secondary Source Onboard Battery  
Primary Source Onboard Battery  
Secondary Source VMEbus +5V STBY  
Flash Write Protect Header (J16)  
The firmware resident in Flash memory is originally loaded at the  
factory, but the Flash contents can be reprogrammed if necessary.  
To prevent inadvertent overwriting of the Flash memory, header  
J16 provides write protection. With a jumper installed on J16, the  
Flash memory can be written to via normal software routines.  
When the jumper is removed (the factory configuration), Flash  
memory cannot be written to.  
J16  
2
1
Flash write-protected  
(Factory configuration)  
2-7  
Hardware Preparation and Installation  
IP Bus Strobe Select Header (J18)  
2
Some IP bus implementations make use of the Strobesignal (pin  
46) as an input to the IP modules from the IP2 chip. Other IP  
interfaces require that the strobe be disconnected.  
With a jumper installed between J18 pins 1 and 2, a programmable  
frequency source is connected to the Strobesignal on the IP bus  
(for details, refer to the IP2 chip programming model in the  
MVME162LX Embedded Controller ProgrammerÕs Reference Guide).  
If the jumper is removed from J18, the strobe line is available for a  
sideband type of messaging between IP modules. The Strobe∗  
signal is not connected to any active devices on the board, but it  
may be connected to a pull-up resistor.  
J18  
J18  
2
1
2
1
IP Strobe disconnected  
IP Strobe connected  
(Factory configuration)  
IP DMA Snoop Control Header (J19)  
The jumpers on header J19 define the state of the snoop control bus  
when an IP DMA controller is local bus master. Placing a jumper on  
J19 pins 3 to 4 inhibits snooping (the snoop signal to the MC68040  
is driven low during IP DMA). Leaving pins 3 and 4 unconnected  
enables snooping. Pins 1 and 2 are not used for the MC68040.  
J19  
4
3
2
1
Snoop Inhibited  
(Factory configuration)  
2-8  
Hardware Preparation  
The following table lists the snoop operations represented by the  
setting of J19.  
2
Table 2-2. J19 Snoop Control Encoding  
Pins  
1-2  
Pins  
3-4  
Snoop Operation  
X
X
0
1
Snoop disabled  
Snoop enabled  
X = donÕt care  
Jumper installed = logic 0  
Jumper removed = logic 1  
EPROM/Flash Configuration Header (J20)  
The MVME162LX can be ordered with 2MB of Flash memory and  
two EPROM sockets ready for the installation of the EPROMs,  
which may be ordered separately. The EPROM locations are  
standard JEDEC 32-pin DIP sockets. The EPROM sockets  
accommodate three jumper-selectable densities (256 Kbit x 8; 512  
Kbit x 8 Ñ the default configuration; 1 Mbit x 8) and permit  
disabling of the Flash memory.  
Header J20 provides eight jumper locations to configure the  
EPROM sockets.  
2-9  
Hardware Preparation and Installation  
2
J20  
J20  
15  
16  
15  
16  
1
2
1
2
CONFIGURATION 2: 512K x 8 EPROMs  
(FACTORY DEFAULT)  
CONFIGURATION 1: 256K x 8 EPROMs  
J20  
J20  
15  
16  
15  
16  
1
2
1
2
CONFIGURATION 3: 1M x 8 EPROMs  
CONFIGURATION 4: 1M x 8 EPROMs  
ONBOARD FLASH DISABLED  
The next four tables show the address range for each EPROM  
socket in all four configurations. GPI3 (J21 pins 7-8) is a control bit  
in the MC2chip ASIC that determines whether reset code is fetched  
from Flash memory or from EPROMs.  
2-10  
Hardware Preparation  
.
2
Table 2-3. EPROM/Flash Mapping — 256K x 8 EPROMs  
GPI3  
Address Range  
Device Accessed  
Removed  
1
0
$FF800000 - $FF83FFFF EPROM A (XU1)  
$FF840000 - $FF87FFFF EPROM B (XU2)  
$FFA00000 - $FFBFFFFF Onboard Flash  
$FF800000 - $FF9FFFFF Onboard Flash  
$FFA00000 - $FFA3FFFF EPROM A (XU1)  
$FFA40000 - $FFA7FFFF EPROM B (XU2)  
Installed  
Table 2-4. EPROM/Flash Mapping — 512K x 8 EPROMs  
GPI3  
Address Range  
Device Accessed  
Removed  
1
0
$FF800000 - $FF87FFFF EPROM A (XU1)  
$FF880000 - $FF8FFFFF EPROM B (XU2)  
$FFA00000 - $FFBFFFFF Onboard Flash  
$FF800000 - $FF9FFFFF Onboard Flash  
$FFA00000 - $FFA7FFFF EPROM A (XU1)  
$FFA80000 - $FFAFFFFF EPROM B (XU2)  
Installed  
Table 2-5. EPROM/Flash Mapping — 1M x 8 EPROMs  
GPI3  
Address Range  
Device Accessed  
Removed  
1
0
$FF800000 - $FF8FFFFF EPROM A (XU1)  
$FF900000 - $FF9FFFFF EPROM B (XU2)  
$FFA00000 - $FFBFFFFF Onboard Flash  
$FF800000 - $FF9FFFFF Onboard Flash  
$FFA00000 - $FFAFFFFF EPROM A (XU1)  
$FFB00000 - $FFBFFFFF EPROM B (XU2)  
Installed  
2-11  
Hardware Preparation and Installation  
Table 2-6. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash  
Disabled  
2
GPI3  
Address Range  
Device Accessed  
Removed  
1
0
$FF800000 - $FF8FFFFF EPROM A (XU1)  
$FF900000 - $FF9FFFFF EPROM B (XU2)  
Not used  
Not used  
Onboard Flash  
Onboard Flash  
Installed  
$FF800000 - $FF8FFFFF EPROM A (XU1)  
$FF900000 - $FF9FFFFF EPROM B (XU2)  
General-Purpose Readable Jumpers Header (J21)  
Header J21 provides eight readable jumpers. These jumpers are  
read as a register (at $FFF4202D) in the MC2chip LCSR (local  
control/status register). The bit values are read as a 0 when the  
jumper is installed, and as a 1 when the jumper is removed.  
With the factory-installed MVME162BUG firmware in place, four  
jumpers are user-definable (pins 9-10, 11-12, 13-14, 15-16). If the  
MVME162BUG firmware is removed, seven jumpers are user-  
definable (i.e., pins 1-2, 3-4, 5-6, 9-10, 11-12, 13-14, 15-16).  
Note Pins 7-8 (GPI3) are reserved to select either the Flash  
memory map (jumper installed) or the EPROM  
memory map (jumper removed). They are not user-  
definable. The address ranges for the various  
EPROM/Flash configurations appear in the section on  
header J20.  
In most cases, the MVME162LX is shipped from the factory with J21  
set to all zeros (jumpers on all pins) except for GPI3 (pins 7-8). On  
boards built with the no-VMEbus option, however, GPI3 is jumpered  
as well.  
2-12  
Hardware Preparation  
2
162BUG INSTALLED  
USER CODE INSTALLED  
J21  
GPI7 15  
GPI6  
16  
USER-DEFINABLE  
USER-DEFINABLE  
USER-DEFINABLE  
USER-DEFINABLE  
USER-DEFINABLE  
IN=FLASH; OUT=EPROM  
USER-DEFINABLE  
USER-DEFINABLE  
USER-DEFINABLE  
USER-DEFINABLE  
GPI5  
USER-DEFINABLE  
GPI4  
USER-DEFINABLE  
GPI3  
GPI2  
GPI1  
GPI0  
7
1
8
2
IN=FLASH; OUT=EPROM  
REFER TO 162BUG MANUAL  
REFER TO 162BUG MANUAL  
REFER TO 162BUG MANUAL  
EPROMs Selected (factory configuration except on no-VMEbus models)  
Memory Mezzanine Options  
The 700/800-series MVME162LX has two 100-pin connectors (J15  
and J22) to accommodate optional memory mezzanine boards. Two  
memory mezzanine options are available:  
4/8/16MB parity DRAM  
4/8/16/32MB ECC DRAM  
The mezzanine boards may either be used individually or be  
combined in a stack (not more than two deep). The following  
connector options govern stacking arrangements:  
The 4/8/16MB parity DRAM board has connectors on the  
bottom only; it must be either the only mezzanine or the top  
mezzanine.  
All ECC DRAM boards have two connector options:  
Ð Connectors top and bottom for stackability  
Ð Connectors on the bottom only; must be either the only  
mezzanine or the top mezzanine  
2-13  
Hardware Preparation and Installation  
When the mezzanines are stacked, the following combinations are  
possible:  
2
Table 2-7. Memory Mezzanine Stacking Options  
Upper  
Mezzanine  
Parity  
DRAM  
ECC  
DRAM  
None  
None  
Lower  
Parity  
ECC  
ECC  
ECC  
Mezzanine  
DRAM  
DRAM  
DRAM  
DRAM  
Note When equipped with a single memory mezzanine,  
MVME162LX VMEmodules maintain a single VME  
slot width. With two memory mezzanines, the  
MVME162LX extends into the adjacent VME slot. The  
latter versions have double-wide front panels.  
Installation Instructions  
This section covers:  
Installation of IndustryPacks (IPs) on the MVME162LX  
Installation of the MVME162LX in a VME chassis  
System considerations relevant to the installation.  
Before installing IndustryPacks, ensure that EPROM devices are  
installed as needed and that all header jumpers are configured as  
desired.  
2-14  
Installation Instructions  
IP Installation on the MVME162LX  
2
Up to two IPs may be installed on the 700/800-series MVME162LX.  
Install the IPs on the board as follows:  
1. Each IP has two 50-pin connectors that plug into two  
corresponding 50-pin connectors on the MVME162LX: J5/J6,  
J7/J8. See Figure 2-1 for the MVME162LX connector  
locations.  
Ð Orient the IP(s) so that the tapered connector shells mate  
properly. Plug IP_a into connectors J5 and J6; plug IP_b  
into J7 and J8. If a double-sized IP is used, plug IP_ab into  
J5, J6, J7, and J8.  
2. Two additional 50-pin connectors (J3 and J4) are provided  
behind the MVME162LX front panel for external cabling  
connections to the IP modules. There is a one-to-one  
correspondence between the signals on the cabling  
connectors and the signals on the associated IP connectors  
(i.e., J4 has the same IP_a signals as J5; J3 has the same IP_b  
signals as J7).  
Ð Connect user-supplied 50-pin cables to J3 and J4 as  
needed. Because of the varying requirements for each  
different kind of IP, Motorola does not supply these  
cables.  
Ð Bring the IP cables out the narrow slot in the MVME162LX  
front panel and attach them to the appropriate external  
equipment, depending on the nature of the particular  
IP(s).  
2-15  
Hardware Preparation and Installation  
MVME162LX Installation  
2
With EPROMs and IPs installed and headers properly configured,  
proceed as follows to install the MVME162LX in the VME chassis:  
1. Turn all equipment power OFF and disconnect the power  
cable from the AC power source.  
Inserting or removing modules while power is applied  
could result in damage to module components.  
!
Caution  
Dangerous voltages, capable of causing death, are  
present in this equipment. Use extreme caution when  
handling, testing, and adjusting.  
!
Warning  
2. Remove the chassis cover as instructed in the user's manual  
for the equipment.  
3. Remove the filler panel from the card slot where you are  
going to install the MVME162LX.  
Ð If you intend to use the MVME162LX as system controller,  
it must occupy the leftmost card slot (slot 1). The system  
controller must be in slot 1 to correctly initiate the bus-  
grant daisy-chain and to ensure proper operation of the  
IACK daisy-chain driver.  
Ð If you do not intend to use the MVME162LX as system  
controller, it can occupy any unused double-height card  
slot.  
4. Slide the MVME162LX into the selected card slot. Be sure the  
module is seated properly in the P1 and P2 connectors on the  
backplane. Do not damage or bend connector pins.  
5. Secure the MVME162LX in the chassis with the screws  
provided, making good contact with the transverse mounting  
rails to minimize RF emissions.  
2-16  
Installation Instructions  
6. On the chassis backplane, remove the INTERRUPT  
2
ACKNOWLEDGE (IACK) and BUS GRANT (BG) jumpers from  
the header for the card slot occupied by the MVME162LX.  
Note Some VME backplanes (e.g., those used in Motorola  
ÔÔModular ChassisÕÕ systems) have an autojumpering  
feature for automatic propagation of the IACK and BG  
signals. Step 6 does not apply to such backplane  
designs.  
7. Connect the appropriate cable(s) to the MVME162LX panel  
connectors for the EIA-232-D serial ports, SCSI port, and LAN  
Ethernet port.  
Ð Note that some cables are not provided with the  
MVME162LX and must be made or purchased by the user.  
(Motorola recommends shielded cable for all peripheral  
connections to minimize radiation.)  
8. Connect the peripheral(s) to the cable(s).  
9. Install any other required VMEmodules in the system.  
10. Replace the chassis cover.  
11. Connect the power cable to the AC power source and turn the  
equipment power ON.  
2-17  
Hardware Preparation and Installation  
System Considerations  
2
The 700/800-series MVME162LX draws power from both the P1  
and the P2 connectors on the VMEbus backplane. P2 is also used for  
the upper 16 bits of data in 32-bit transfers, and for the upper 8  
address lines in extended addressing mode. The MVME162LX may  
not operate properly without its main board connected to VMEbus  
backplane connectors P1 and P2.  
Whether the MVME162LX operates as VMEbus master or as  
VMEbus slave, it is configured for 32 bits of address and 32 bits of  
data (A32/D32). However, it handles A16 or A24 devices in the  
address ranges indicated in Chapter 3. D8 and/or D16 devices in  
the system must be handled by the MC68040 software. Refer to the  
memory maps in the MVME162LX Embedded Controller  
ProgrammerÕs Reference Guide.  
The MVME162LX contains shared onboard DRAM whose base  
address is software-selectable. Both the onboard processor and  
offboard VMEbus devices see this local DRAM at base physical  
address $00000000, as programmed by the MVME162Bug  
firmware. This may be changed via software to any other base  
address. Refer to the MVME162LX Embedded Controller  
ProgrammerÕs Reference Guide for more information.  
If the MVME162LX tries to access offboard resources in a  
nonexistent location and is not system controller, and if the system  
does not have a global bus timeout, the MVME162LX waits forever  
for the VMEbus cycle to complete. This will cause the system to lock  
up. There is only one situation in which the system might lack this  
global bus timeout: when the MVME162LX is not the system  
controller and there is no global bus timeout elsewhere in the  
system.  
Multiple MVME162LXs may be installed in a single VME chassis. In  
general, hardware multiprocessor features are supported.  
2-18  
Installation Instructions  
Note If you are installing multiple MVME162LXs in an  
2
MVME945 chassis, do not install one in slot 12. The  
height of the IP modules may cause clearance  
difficulties in that slot position.  
Other MPUs on the VMEbus can interrupt, disable, communicate  
with, and determine the operational status of the processor(s). One  
register of the GCSR (global control/status register) set includes  
four bits that function as location monitors to allow one  
MVME162LX processor to broadcast a signal to any other  
MVME162LX processors. All eight registers are accessible from any  
local processor as well as from the VMEbus.  
The following circuits are protected by solid-state fuses that open  
during overload conditions: LAN/AUI, SCSI terminator, remote  
reset connector, IndustryPack 5V, and ±12V.  
The FUSES LED illuminates to indicate that all fuses are functioning  
correctly. If a fuse opens, you will have to remove power for several  
minutes to let the fuse reset to a closed or shorted condition.  
The MVME162LX uses two Zilog Z85230 serial port controllers to  
implement the four serial communications interfaces. Each  
interface supports CTS, DCD, RTS, and DTR control signals as well  
as the TXD and RXD transmit/receive data signals. Because the  
serial clocks are omitted in the MVME162LX implementation, serial  
communications are strictly asynchronous. The Z85230 is  
interfaced as DTE (data terminal equipment) with EIA-232-D signal  
levels. The serial ports are routed to four RJ-45 connectors on the  
front panel  
.
The figures on the following pages supply connection diagrams for  
the four serial ports on the MVME162LX. These ports are connected  
to external devices through cables connected to the front panel.  
2-19  
Hardware Preparation and Installation  
Figure 2-2 diagrams the pin assignments required in a cable to  
adapt a DB-25 DTE device to the RJ-45 connectors.  
2
DB-25 DTE DEVICE  
RJ-45 JACK  
DSR  
DCD  
RTS  
6
8
4
1
2
3
4
5
6
7
8
TXD  
RXD  
SG  
2
3
7
5
CTS  
DTR 20  
Figure 2-2. DB-25 DTE-to-RJ-45 Adapter  
Figure 2-3 diagrams the pin assignments required in a cable to  
adapt a DB-25 DCE device to a RJ-45 connector.  
DB-25 DCE DEVICE  
RJ-45 JACK  
DTR 20  
1
2
3
4
5
6
7
8
CTS  
5
RXD  
TXD  
SG  
3
2
7
4
8
RTS  
DCD  
Figure 2-3. DB-25 DCE-to-RJ-45 Adapter  
2-20  
Installation Instructions  
Figure 2-4 diagrams the pin assignments required in a typical 8-  
conductor serial cable having RJ-45 connectors at both ends. Note  
that all wires are crossed.  
2
RJ-45 CONNECTOR  
RJ-45 CONNECTOR  
DCD  
RTS  
SG  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TXD  
RXD  
SG  
CTS  
DTR  
Figure 2-4. Typical RJ-45 Serial Cable  
2-21  
Hardware Preparation and Installation  
2
2-22  
3Debugger General Information  
3
Overview of M68000 Firmware  
The firmware for the M68000-based (68K) series of board and  
system level products has a common genealogy, deriving from the  
debugger firmware currently used on all Motorola M68000-based  
CPU modules. The M68000 firmware family provides a high degree  
of functionality and user friendliness, and yet stresses portability  
and ease of maintenance. The M68000 firmware implementation on  
the 700/800-series MVME162LX MC68040-based Embedded  
Controller is known as the MVME162Bug, or 162Bug. It includes  
diagnostics for testing and configuring IndustryPack modules.  
Description of 162Bug  
The 162Bug package, MVME162Bug, is a powerful evaluation and  
debugging tool for systems built around the MVME162LX CISC-  
based microcomputers. Facilities are available for loading and  
executing user programs under complete operator control for  
system evaluation. 162Bug includes commands for display and  
modification of memory, breakpoint and tracing capabilities, a  
powerful assembler/disassembler useful for patching programs,  
and a power-up self test which verifies the integrity of the system.  
Various 162Bug routines that handle I/O, data conversion, and  
string functions are available to user programs through the TRAP  
#15 system calls.  
162Bug consists of three parts:  
A command-driven user-interactive software debugger,  
described in Chapter 4 and hereinafter referred to as ÔÔthe  
debuggerÕÕ or ÔÔ162BugÕÕ.  
3-1  
         
Debugger General Information  
A command-driven diagnostic package for the MVME162LX  
hardware, described in the MVME162Bug Diagnostics Manual  
and hereinafter referred to as ÔÔthe diagnosticsÕÕ.  
3
A user interface that accepts commands from the system  
console terminal.  
When using 162Bug, you operate out of either the debugger  
directory or the diagnostic directory. If you are in the debugger  
directory, the debugger prompt  
162-Bug>  
is displayed and you have all of the debugger commands at your  
disposal. If you are in the diagnostic directory, the diagnostic  
prompt  
162-Diag>  
is displayed and you have all of the diagnostic commands at your  
disposal as well as all of the debugger commands. You may switch  
between directories by using the Switch Directories (SD) command,  
or you may examine the commands in your current directory by  
using the Help (HE) command.  
Because 162Bug is command-driven, it performs its various  
operations in response to user commands entered at the keyboard.  
When you enter a command, 162Bug executes the command and  
the prompt reappears. However, if you enter a command that  
causes execution of user target code (for example, GO), then control  
may or may not return to 162Bug, depending on the outcome of the  
user program.  
If you have used one or more of Motorola's other debugging  
packages, you will find the CISC 162Bug very similar. Some effort  
has also been made to make the interactive commands more  
consistent. For example, delimiters between commands and  
arguments may now be commas or spaces interchangeably.  
3-2  
 
162Bug Implementation  
162Bug Implementation  
MVME162Bug is written largely in the ÔÔCÕÕ programming  
language, providing benefits of portability and maintainability.  
Where necessary, assembler has been used in the form of separately  
compiled modules containing only assembler code Ñ no mixed  
language modules are used.  
3
Physically, 162Bug is contained in a single 27C040 DIP EPROM  
installed in socket XU2, providing 512KB (128K longwords) of  
storage. As an option, the 162Bug firmware can be loaded and  
executed in a single Flash memory chip. The executable code is  
checksummed at every power-on or reset firmware entry, and the  
result (which includes a pre-calculated checksum contained in the  
memory devices), is tested for an expected zero. Thus, users are  
cautioned against modification of the memory devices unless re-  
checksum precautions are taken.  
Installation and Startup  
Follow the steps below to operate 162Bug with the MVME162LX  
module. 162Bug is factory-installed in EPROM, except in the no-  
VMEbus case.  
Inserting or removing boards while power is applied  
could damage board components.  
!
Caution  
1. Turn all equipment power OFF. Refer to the Hardware  
Preparation section in Chapter 2 and install/remove jumpers  
on headers as required for your particular application.  
Jumpers on header J21 affect 162Bug operation as described  
below. The default condition for the MVME162LX is with  
seven jumpers installed, between pins 1-2, 3-4, 5-6, 9-10, 11-  
12, 13-14, and 15-16 (no jumper between pins 7-8).  
3-3  
                 
Debugger General Information  
Models with no VMEbus interface have a jumper between  
pins 7-8 as well.  
These readable jumpers are read as a register (at $FFF4202D)  
on the Memory Controller (MC2chip) ASIC. The bit values  
are read as a zero when the jumper is installed, and as a one  
when the jumper is removed. This jumper block (header J21)  
contains eight bits. Refer also to the MVME162LX Embedded  
Controller Programmer's Reference Guide for more information  
on the MC2chip.  
3
The MVME162Bug reserves/defines the four lower order bits  
(GPI3 to GPI0). The following is the description for the bits  
reserved/defined by the debugger:  
Bit  
J21 Pins Description  
Bit #0 (GPI0)  
1-2  
3-4  
When set to 1 (high), instructs the debugger to  
use local Static RAM for its work page (i.e.,  
variables, stack, vector tables, etc.).  
Bit #1 (GPI1)  
When set to 1 (high), instructs the debugger to  
use the default setup/operation parameters in  
Flash or ROM versus the user setup/operation  
parameters in Non-Volatile RAM (NVRAM).  
This is the same as depressing the RESET and  
ABORT switches at the same time. This feature  
can be used in the event the user setup is  
corrupted or does not meet a sanity check. Refer  
to the ENV command (Appendix A) for the  
Flash/ROM defaults.  
Bit #2 (GPI2)  
Bit #3 (GPI3)  
5-6  
7-8  
Reserved for future use.  
When this bit is a zero (low), it informs the  
debugger that it is executing out of the Flash  
memories. When this bit is a one (high), it  
informs the debugger that it is executing out of  
the PROM.  
Bit #4 (GPI4)  
Bit #5 (GPI5)  
Bit #6 (GPI6)  
Bit #7 (GPI7)  
9-10  
11-12  
13-14  
15-16  
Open to your application.  
Open to your application.  
Open to your application.  
Open to your application.  
3-4  
 
Installation and Startup  
Note that when the MVME162LX comes up in a cold reset,  
162Bug runs in Board Mode. Using the Environment (ENV) or  
MENU commands can make 162Bug run in System Mode.  
Refer to Appendix A for details.  
3
2. Configure header J1 by installing/removing a jumper  
between pins 1 and 2. A jumper installed/removed  
enables/disables the system controller function of the  
MVME162LX.  
3. The jumper on header J11 configures the IP bus clock for  
either 8MHz or 32MHz. The factory configuration puts a  
jumper between J11 pins 1 and 2 for an 8MHz clock. Verify  
that this setting is appropriate for your application.  
4. The jumper on header J18 enables/disables the IP bus strobe  
function on the MVME162LX. The factory configuration puts  
a jumper between J18 pins 1 and 2 to connect the Strobe∗  
signal to the IP2 chip. Verify that the strobe line should be  
connected in your application.  
5. The jumpers on header J19 enable/disable the IP DMA snoop  
function on the MVME162LX. The factory configuration has  
J19 fully jumpered to inhibit the snoop function. Verify that  
snooping should be disabled in your IP DMA application.  
6. Refer to the setup procedure for your particular chassis or  
system for details concerning the installation of the  
MVME162LX.  
7. Connect the terminal that is to be used as the 162Bug system  
console to the default debug EIA-232-D port at serial port 1 on  
the front panel of the MVME162LX. Refer to Chapter 2 for  
other connection options. Set up the terminal as follows:  
Ð eight bits per character  
Ð one stop bit per character  
Ð parity disabled (no parity)  
Ð baud rate 9600 baud (default baud rate of MVME162LX  
ports at powerup)  
3-5  
             
Debugger General Information  
After power-up, you can reconfigure the baud rate of the  
debug port if necessary by using the 162Bug firmwareÕs Port  
Format (PF) command.  
3
Note In order for high-baud rate serial communication  
between 162Bug and the terminal to work, the terminal  
must do some form of handshaking. If the terminal  
being used does not do hardware handshaking via the  
CTS line, then it must do XON/XOFF handshaking. If  
you get garbled messages and missing characters, then  
you should check the terminal to make sure  
XON/XOFF handshaking is enabled.  
8. If you want to connect devices (such as a host computer  
system and/or a serial printer) to the other EIA-232-D port  
connectors, connect the appropriate cables and configure the  
port(s) as detailed in step 4 above. After power-up, you can  
reconfigure this (these) port(s) by programming the  
MVME162LX Z85230 Serial Communications Controllers  
(SCCs), or by using the 162Bug PF command.  
9. EPROM/Flash configuration header J20 should be set to  
configuration 2, with jumpers between J20 pins 5 and 6, 8 and  
10, and 9 and 11. This sets it up for 512K x 8 EPROMs.  
10. Power up the system. 162Bug executes some self-checks and  
displays the debugger prompt  
162-Bug>  
(if 162Bug is in Board Mode). However, if the ENV command  
(Appendix A) has put 162Bug in System Mode, the system  
performs a selftest and tries to autoboot. Refer to the ENV and  
MENU commands (Table 4-3).  
If the confidence test fails, the test is aborted when the first  
fault is encountered. If possible, an appropriate message is  
displayed, and control then returns to the menu.  
3-6  
   
Autoboot  
11. Before using the MVME162LX after the initial installation, set  
the date and time using the following command line  
structure:  
162-Bug>SET [mmddyyhhmm]|[<+/-CAL>;C]  
3
For example, the following command line starts the real-time  
clock and sets the date and time to 10:37 a.m., November 7,  
1997:  
162-Bug>SET 1107971037  
The boardÕs self-tests and operating systems require that the  
real-time clock be running.  
Prom Versions  
When you are using a PROM version of the 162Bug (e.g., in the case  
of the 700/800-series MVME162LX) and you wish to execute the  
debugger out of Flash memory rather than from PROM in  
subsequent sessions, proceed as follows after the board is up and  
running:  
1. Install a jumper across J16 pins 1-2 to enable Flash writes.  
2. Copy the PROM contents to Flash memory with the PFLASH  
command as follows:  
162-Bug> PFLASH FF800000:80000 FFA00000  
3. Remove the jumper from J16 pins 1-2 to disable subsequent  
Flash writes.  
4. Install a jumper at J21 pins 7 and 8. (162Bug always executes  
from memory location FF800000; the state of J21 determines  
whether that location is in PROM or Flash.)  
Autoboot  
Autoboot is a software routine that is contained in the 162Bug  
Flash/PROM to provide an independent mechanism for booting an  
operating system. This autoboot routine automatically scans for  
3-7  
           
Debugger General Information  
controllers and devices in a specified sequence until a valid  
bootable device containing a boot media is found or the list is  
exhausted. If a valid bootable device is found, a boot from that  
device is started. The controller scanning sequence goes from the  
lowest controller Logical Unit Number (LUN) detected to the  
highest LUN detected. Controllers, devices, and their LUNs are  
listed in Appendix B.  
3
At powerup, Autoboot is enabled, and providing the drive and  
controller numbers encountered are valid, the following message is  
displayed upon the system console:  
Autoboot in progress... To abort hit <BREAK>  
Following this message there is a delay to allow you an opportunity  
to abort the Autoboot process if you wish. Then the actual I/O is  
begun: the program pointed to within the volume ID of the media  
specified is loaded into RAM and control passed to it. If, however,  
during this time you want to gain control without Autoboot, you  
can press the <BREAK> key or the software ABORT or RESET  
switches.  
Autoboot is controlled by parameters contained in the ENV  
command. These parameters allow the selection of specific boot  
devices and files, and allow programming of the Boot delay. Refer  
to the ENV command in Appendix A for more details.  
Although streaming tape can be used to autoboot, the  
same power supply must be connected to the streaming  
tape drive, the controller, and the MVME162LX. At  
powerup, the tape controller will position the streaming  
tape to load point where the volume ID can correctly be  
read and used.  
!
Caution  
If, however, the MVME162LX loses power but the  
controller does not, and the tape happens to be at load  
point, the sequences of commands required (attach and  
rewind) cannot be given to the controller and autoboot  
will not be successful.  
3-8  
ROMboot  
ROMboot  
As shipped from the factory, 162Bug occupies an EPROM installed  
in socket XU2. This leaves one socket (XU1) and the Flash memory  
available for your use. Contact your Motorola sales office for  
assistance. This function is configured/enabled by the  
3
Environment (ENV) command (refer to Appendix A) and executed  
at powerup (optionally also at reset) or by the RB command  
assuming there is valid code in the memory devices (or optionally  
elsewhere on the board or VMEbus) to support it. If ROMboot code  
is installed, a user-written routine is given control (if the routine  
meets the format requirements). One use of ROMboot might be  
resetting SYSFAIL* on an unintelligent controller module. The  
NORB command disables the function.  
For a user's ROMboot module to gain control through the  
ROMboot linkage, four requirements must be met:  
Power must have just been applied (but the ENV command  
can change this to also respond to any reset).  
Your routine must be located within the MVME162LX  
Flash/PROM memory map (but the ENV command can  
change this to any other portion of the onboard memory, or  
even offboard VMEbus memory).  
The ASCII string ÔÔBOOTÕÕ must be located within the  
specified memory range.  
Your routine must pass a checksum test, which ensures that  
this routine was really intended to receive control at  
powerup.  
For complete details on how to use ROMboot, refer to the  
Debugging Package for Motorola 68K CISC CPUs User's Manual.  
3-9  
     
Debugger General Information  
Network Boot  
Network Auto Boot is a software routine contained in the 162Bug  
Flash/PROM that provides a mechanism for booting an operating  
system using a network (local Ethernet interface) as the boot device.  
If enabled (via ENV Ñ refer to Appendix A), the Network Auto  
Boot routine automatically scans for controllers and devices in a  
specified sequence until a valid bootable device containing a boot  
media is found or the list is exhausted. If a valid bootable device is  
found, a boot from that device is started. The controller scanning  
sequence goes from the lowest controller Logical Unit Number  
(LUN) detected to the highest LUN detected. (Refer to Appendix C  
for default LUNs.)  
3
At powerup, if Network Boot is enabled and the controller and  
device LUNs are valid, the following message is displayed at the  
system console:  
Network Boot in progress... To abort hit <BREAK>  
Following this message there is a delay to let you abort the autoboot  
process if you wish. Then the actual I/O is begun: the program  
pointed to within the volume ID of the media specified is loaded  
into RAM and control passed to it. If, however, during this time you  
want to gain control without Network Boot, you can press the  
<BREAK> key or the software ABORT or RESET switches.  
Network Auto Boot is controlled by parameters contained in the  
NIOT and ENV commands. These parameters allow the selection of  
specific boot devices, systems, and files, and allow programming of  
the Boot delay. Refer to the ENV command in Appendix A for more  
details.  
Restarting the System  
You can initialize the system to a known state in three different  
ways: reset, abort, and break. Each has characteristics which make  
it more appropriate than the others in certain situations.  
3-10  
       
Restarting the System  
The debugger has a special feature available for reset conditions.  
You activate it by pressing the RESET and ABORT switches at the  
same time, releasing RESET first, then releasing ABORT seven  
seconds later.  
3
This ÔÔdouble-button resetÕÕ feature instructs the debugger to use  
the default setup/operation parameters in ROM versus your  
setup/operation parameters in NVRAM. You can use this feature  
in the event your setup/operation parameters are corrupted or do  
not meet a sanity check. Refer to the ENV command (Appendix A)  
for the ROM defaults.  
Reset  
Pressing and releasing the MVME162LX front panel RESET switch  
initiates a system reset. COLD and WARM reset modes are  
available. By default, 162Bug is in COLD mode. During COLD  
resets, a total system initialization takes place, as if the  
MVME162LX had just been powered up. All static variables  
(including disk device and controller parameters) are restored to  
their default states. The breakpoint table and offset registers are  
cleared. The target registers are invalidated. Input and output  
character queues are cleared. Onboard devices (timer, serial ports,  
etc.) are reset, and the two serial ports are reconfigured to their  
default state.  
During WARM resets, the 162Bug variables and tables are  
preserved, as well as the target state registers and breakpoints.  
Reset must be used if the processor ever halts, or if the 162Bug  
environment is ever lost (vector table is destroyed, stack corrupted,  
etc.).  
Abort  
The Abort function is invoked by pressing and releasing the ABORT  
switch on the MVME162LX front panel. Whenever abort is invoked  
when executing a user program (running target code), a snapshot  
of the processor state is captured and stored in the target registers.  
3-11  
         
Debugger General Information  
For this reason, abort is most appropriate when terminating a user  
program that is being debugged. Abort should be used to regain  
control if the program gets caught in a loop, etc. The target PC,  
register contents, etc., help to pinpoint the malfunction.  
3
Pressing and releasing the ABORT switch generates a local board  
condition which may interrupt the processor if enabled. The target  
registers, reflecting the machine state at the time the ABORT switch  
was pressed, are displayed on the screen. Any breakpoints installed  
in your code are removed and the breakpoint table remains intact.  
Control is returned to the debugger.  
Break  
A ÔÔpower-breakÕÕ is generated by pressing and releasing the  
<BREAK> key on the terminal keyboard. Break does not generate  
an interrupt. The only time break is recognized is when characters  
are sent or received by the console port. Break removes any  
breakpoints in your code and keeps the breakpoint table intact.  
Break also takes a snapshot of the machine state if the function was  
entered using SYSCALL. This machine state is then accessible to  
you for diagnostic purposes.  
Many times it may be desirable to terminate a debugger command  
before its completion Ñ during the display of a large block of  
memory, for example. Break allows you to terminate the command.  
SYSFAIL* Assertion/Negation  
Upon entering a reset/powerup condition, the debugger asserts the  
VMEbus SYSFAILline (refer to the VMEbus specification).  
SYSFAILstays asserted if any of the following has occurred:  
Confidence test failure  
NVRAM checksum error  
NVRAM low battery condition  
Local memory configuration status  
3-12  
         
Memory Requirements  
self test (if system mode) has completed with error  
MPU clock speed calculation failure  
After debugger initialization is done and none of the above  
situations have occurred, the SYSFAILline is negated. This  
indicates to the user or VMEbus masters the state of the debugger.  
In a multi-computer configuration, other VMEbus masters could  
view the pertinent control and status registers to determine which  
CPU is asserting SYSFAIL. SYSFAILassertion/negation is also  
affected by the ENV command. Refer to Appendix A.  
3
MPU Clock Speed Calculation  
The clock speed of the microprocessor is calculated and checked  
against a user definable parameter housed in NVRAM (refer to the  
CNFG command description in Appendix A). If the check fails, a  
warning message is displayed. The calculated clock speed is also  
checked against known clock speeds and tolerances.  
Memory Requirements  
The program portion of 162Bug is approximately 512KB of code,  
consisting of download, debugger, and diagnostic packages and  
contained entirely in Flash or PROM.  
The 162Bug executes from $FF800000 whether in Flash or PROM. If  
you remove the jumper at J21 pins 7 and 8, the address spaces of the  
Flash and PROM are swapped. For 700/800-series MVME162LX  
boards, the factory shipping configuration is with jumper J21 pins  
7-8 removed (so that 162Bug operates out of EPROM).  
The 162Bug initial stack completely changes 8KB of SRAM memory  
at addresses offset $C000 from the SRAM base address, at power-  
up or reset.  
3-13  
       
Debugger General Information  
Type of Memory Present  
A single DRAM mezzanine  
A single SRAM mezzanine  
Default  
DRAM Base  
Address  
Default SRAM  
Base Address  
3
$00000000  
$FFE00000  
(onboard  
SRAM)  
N/A  
$00000000  
$E1000000  
A DRAM mezzanine stacked with an SRAM  
mezzanine  
$00000000  
Two DRAM mezzanines stacked  
$00000000  
$FFE00000  
(onboard  
SRAM)  
DRAM can be ECC or parity type. DRAM mezzanines are mapped  
in contiguously starting at zero ($00000000), largest first. With two  
mezzanines of the same size but different type, parity DRAM is  
mapped to the selected base address and the ECC mezzanine will  
follow. If both are ECC type, the bottom one is first.  
The 162Bug requires 2KB of NVRAM for storage of board  
configuration, communication, and booting parameters. This  
storage area begins at $FFFC16F8 and ends at $FFFC1EF7 (for  
details, refer to the maps in the MVME162LX Embedded Controller  
ProgrammerÕs Reference Guide).  
162Bug requires a minimum of 64KB of contiguous read/write  
memory to operate. The ENV command controls where this block  
of memory is located. Regardless of where the onboard RAM is  
located, the first 64KB is used for 162Bug stack and static variable  
space and the rest is reserved as user space. Whenever the  
MVME162LX is reset, the target PC is initialized to the address  
corresponding to the beginning of the user space, and the target  
stack pointers are initialized to addresses within the user space,  
with the target Interrupt Stack Pointer (ISP) set to the top of the user  
space.  
3-14  
   
Disk I/O Support  
Disk I/O Support  
162Bug can initiate disk input/output by communicating with  
intelligent disk controller modules over the VMEbus. Disk support  
facilities built into 162Bug consist of command-level disk  
operations, disk I/O system calls (only via one of the TRAP #15  
instructions) for use by user programs, and defined data structures  
for disk parameters.  
3
Parameters such as the address where the module is mapped and  
the type and number of devices attached to the controller module  
are kept in tables by 162Bug. Default values for these parameters  
are assigned at powerup and cold-start reset, but may be altered as  
described in the section on default parameters, later in this chapter.  
Appendix B contains a list of the controllers presently supported, as  
well as a list of the default configurations for each controller.  
Blocks Versus Sectors  
The logical block defines the unit of information for disk devices. A  
disk is viewed by 162Bug as a storage area divided into logical  
blocks. By default, the logical block size is set to 256 bytes for every  
block device in the system. The block size can be changed on a per  
device basis with the IOT command.  
The sector defines the unit of information for the media itself, as  
viewed by the controller. The sector size varies for different  
controllers, and the value for a specific device can be displayed and  
changed with the IOT command.  
When a disk transfer is requested, the start and size of the transfer  
is specified in blocks. 162Bug translates this into an equivalent  
sector specification, which is then passed on to the controller to  
initiate the transfer. If the conversion from blocks to sectors yields  
a fractional sector count, an error is returned and no data is  
transferred.  
3-15  
       
Debugger General Information  
Device Probe Function  
A device probe with entry into the device descriptor table is done  
whenever a specified device is accessed; i.e., when system calls  
.DSKRD, .DSKWR, .DSKCFIG, .DSKFMT, and .DSKCTRL, and  
debugger commands BH, BO, IOC, IOP, IOT, MAR, and MAW are  
used.  
3
The device probe mechanism utilizes the SCSI commands Inquiry  
and Mode Sense. If the specified controller is non-SCSI, the probe  
simply returns a status of ÔÔdevice present and unknownÕÕ. The  
device probe makes an entry into the device descriptor table with  
the pertinent data. After an entry has been made, the next time a  
probe is done it simply returns with ÔÔdevice presentÕÕ status  
(pointer to the device descriptor).  
Disk I/O via 162Bug Commands  
These following 162Bug commands are provided for disk I/O.  
Detailed instructions for their use are found in the Debugging  
Package for Motorola 68K CISC CPUs User's Manual. When a  
command is issued to a particular controller LUN and device LUN,  
these LUNs are remembered by 162Bug so that the next disk  
command defaults to use the same controller and device.  
IOI (Input/Output Inquiry)  
This command is used to probe the system for all possible  
CLUN/DLUN combinations and display inquiry data for devices  
which support it. The device descriptor table only has space for 16  
device descriptors; with the IOI command, you can view the table  
and clear it if necessary.  
IOP (Physical I/O to Disk)  
IOP allows you to read or write blocks of data, or to format the  
specified device in a certain way. IOP creates a command packet  
from the arguments you have specified, and then invokes the  
proper system call function to carry out the operation.  
3-16  
               
Disk I/O Support  
IOT (I/O Teach)  
IOT allows you to change any configurable parameters and  
attributes of the device. In addition, it allows you to see the  
controllers available in the system.  
3
IOC (I/O Control)  
IOC allows you to send command packets as defined by the  
particular controller directly. IOC can also be used to look at the  
resultant device packet after using the IOP command.  
BO (Bootstrap Operating System)  
BO reads an operating system or control program from the  
specified device into memory, and then transfers control to it.  
BH (Bootstrap and Halt)  
BH reads an operating system or control program from a specified  
device into memory, and then returns control to 162Bug. It is used  
as a debugging tool.  
Disk I/O via 162Bug System Calls  
All operations that actually access the disk are done directly or  
indirectly by 162Bug TRAP #15 system calls. (The command-level  
disk operations provide a convenient way of using these system  
calls without writing and executing a program.)  
3-17  
                   
Debugger General Information  
The following system calls are provided to allow user programs to  
do disk I/O:  
.DSKRD  
Disk read. System call to read blocks from a disk into  
memory.  
3
.DSKWR  
Disk write. System call to write blocks from memory onto  
a disk.  
.DSKCFIG Disk conÞgure. This function allows you to change the  
conÞguration of the speciÞed device.  
.DSKFMT Disk format. This function allows you to send a format  
command to the speciÞed device.  
.DSKCTRL Disk control. This function is used to implement any  
special device control functions that cannot be  
accommodated easily with any of the other disk  
functions.  
Refer to the Debugging Package for Motorola 68K CISC CPUs User's  
Manual for information on using these and other system calls.  
To perform a disk operation, 162Bug must eventually present a  
particular disk controller module with a controller command  
packet which has been especially prepared for that type of  
controller module. (This is accomplished in the respective  
controller driver module.) A command packet for one type of  
controller module usually does not have the same format as a  
command packet for a different type of module. The system call  
facilities which do disk I/O accept a generalized (controller-  
independent) packet format as an argument, and translate it into a  
controller-specific packet, which is then sent to the specified device.  
Refer to the system call descriptions in the Debugging Package for  
Motorola 68K CISC CPUs User's Manual for details on the format and  
construction of these standardized user packets.  
The packets which a controller module expects to be given vary  
from controller to controller. The disk driver module for the  
particular hardware module (board) must take the standardized  
packet given to a trap function and create a new packet which is  
3-18  
Network I/O Support  
specifically tailored for the disk drive controller it is sent to. Refer  
to documentation on the particular controller module for the  
format of its packets, and for using the IOC command.  
3
Default 162Bug Controller and Device Parameters  
162Bug initializes the parameter tables for a default configuration  
of controllers and devices (refer to Appendix B). If the system needs  
to be configured differently than this default configuration (for  
example, to use a 70MB Winchester drive where the default is a  
40MB Winchester drive), then these tables must be changed.  
There are two ways to change the parameter tables:  
Using BO or BH. When you invoke one of these commands,  
the configuration area of the disk is read and the parameters  
corresponding to that device are rewritten according to the  
parameter information contained in the configuration area.  
This is a temporary change. If a cold-start reset occurs, then  
the default parameter information is written back into the  
tables.  
Using the IOT. You can use this command to reconfigure the  
parameter table manually for any controller and/or device  
that is different from the default. This is also a temporary  
change and is overwritten if a cold-start reset occurs.  
Disk I/O Error Codes  
162Bug returns an error code if an attempted disk operation is  
unsuccessful.  
Network I/O Support  
The Network Boot Firmware provides the capability to boot the  
CPU through the Flash/PROM debugger using a network (local  
Ethernet interface) as the boot device.  
3-19  
             
Debugger General Information  
The booting process is executed in two distinct phases.  
The first phase allows the diskless remote node to discover its  
network identify and the name of the file to be booted.  
3
The second phase has the diskless remote node reading the  
boot file across the network into its memory.  
The various modules (capabilities) and the dependencies of these  
modules that support the overall network boot function are  
described in the following paragraphs.  
Intel 82596 LAN Coprocessor Ethernet Driver  
This driver manages/surrounds the Intel 82596 LAN Coprocessor.  
Management is in the scope of the reception of packets, the  
transmission of packets, receive buffer flushing, and interface  
initialization.  
This module ensures that the packaging and unpackaging of  
Ethernet packets is done correctly in the Boot PROM.  
UDP/IP Protocol Modules  
The Internet Protocol (IP) is designed for use in interconnected  
systems of packet-switched computer communication networks.  
The Internet protocol provides for transmitting of blocks of data  
called datagrams (hence User Datagram Protocol, or UDP) from  
sources to destinations, where sources and destinations are hosts  
identified by fixed length addresses.  
The UDP/IP protocols are necessary for the TFTP and BOOTP  
protocols; TFTP and BOOTP require a UDP/IP connection.  
3-20  
         
Network I/O Support  
RARP/ARP Protocol Modules  
The Reverse Address Resolution Protocol (RARP) basically consists  
of an identity-less node broadcasting a ÔÔwhoamiÕÕ packet onto the  
Ethernet, and waiting for an answer. The RARP server fills an  
Ethernet reply packet up with the target's Internet Address and  
sends it.  
3
The Address Resolution Protocol (ARP) basically provides a  
method of converting protocol addresses (e.g., IP addresses) to  
local area network addresses (e.g., Ethernet addresses). The RARP  
protocol module supports systems which do not support the  
BOOTP protocol (next paragraph).  
BOOTP Protocol Module  
The Bootstrap Protocol (BOOTP) basically allows a diskless client  
machine to discover its own IP address, the address of a server host,  
and the name of a file to be loaded into memory and executed.  
TFTP Protocol Module  
The Trivial File Transfer Protocol (TFTP) is a simple protocol to  
transfer files. It is implemented on top of the Internet User  
Datagram Protocol (UDP or Datagram) so it may be used to move  
files between machines on different networks implementing UDP.  
The only thing it can do is read and write files from/to a remote  
server.  
Network Boot Control Module  
The control capability of the Network Boot Control Module is  
needed to tie together all the necessary modules (capabilities) and  
to sequence the booting process. The booting sequence consists of  
two phases: the first phase is labeled ÔÔaddress determination and  
bootfile selectionÕÕ and the second phase is labeled ÔÔfile transferÕÕ.  
The first phase will utilize the RARP/BOOTP capability and the  
second phase will utilize the TFTP capability.  
3-21  
               
Debugger General Information  
Network I/O Error Codes  
162Bug returns an error code if an attempted network operation is  
unsuccessful.  
3
Multiprocessor Support  
The MVME162LX dual-port RAM feature makes the shared RAM  
available to remote processors as well as to the local processor. This  
can be done by either of the following two methods. Either method  
can be enabled/disabled by the ENV command as its Remote Start  
Switch Method (refer to Appendix A).  
Multiprocessor Control Register (MPCR) Method  
A remote processor can initiate program execution in the local  
MVME162LX dual-port RAM by issuing a remote GO command  
using the Multiprocessor Control Register (MPCR). The MPCR,  
located at shared RAM location of $800 offset from the base address  
the debugger loads it at, contains one of two longwords used to  
control communication between processors. The MPCR contents  
are organized as follows:  
$800  
*
N/A N/A N/A (MPCR)  
The status codes stored in the MPCR are of two types:  
Status returned (from the monitor)  
Status set (by the bus master)  
The status codes that may be returned from the monitor are:  
ASCII 0 (HEX 00) - Wait. Initialization not yet complete.  
ASCII E (HEX 45) - Code pointed to by the MPAR address is executing.  
ASCII P (HEX 50) - Program Flash Memory. The MPAR is set to the  
address of the Flash memory program control packet.  
ASCII R (HEX 52) - Ready. The Þrmware monitor is watching for a change.  
3-22  
               
Multiprocessor Support  
You can only program Flash memory by the MPCR method. Refer  
to the .PFLASH system call in the Debugging Package for Motorola  
68K CISC CPUs User's Manual for a description of the Flash memory  
program control packet structure.  
3
The status codes that may be set by the bus master are:  
ASCII G (HEX 47) - Use Go Direct (GD) logic specifying the MPAR address.  
ASCII B (HEX 42) - Install breakpoints using the Go (G) logic.  
The Multiprocessor Address Register (MPAR), located in shared  
RAM location of $804 offset from the base address the debugger  
loads it at, contains the second of two longwords used to control  
communication between processors. The MPAR contents specify  
the address at which execution for the remote processor is to begin  
if the MPCR contains a G or B. The MPAR is organized as follows:  
$804  
*
*
*
*
(MPAR)  
At power-up, the debug monitorÕs self-test routines initialize RAM,  
including the memory locations used for multi-processor support  
($800 through $807).  
The MPCR contains $00 at powerup, indicating that initialization is  
not yet complete. As the initialization proceeds, the execution path  
comes to the ÔÔpromptÕÕ routine. Before sending the prompt, this  
routine places an R in the MPCR to indicate that initialization is  
complete. Then the prompt is sent.  
If no terminal is connected to the port, the MPCR is still polled to  
see whether an external processor requires control to be passed to  
the dual-port RAM. If a terminal does respond, the MPCR is polled  
for the same purpose while the serial port is being polled for user  
input.  
An ASCII G placed in the MPCR by a remote processor indicates  
that the Go Direct type of transfer is requested. An ASCII B in the  
MPCR indicates that breakpoints are to be armed before control is  
transferred (as with the GO command).  
3-23  
Debugger General Information  
In either sequence, an E is placed in the MPCR to indicate that  
execution is underway just before control is passed to RAM. (Any  
remote processor could examine the MPCR contents.)  
3
If the code being executed in dual-port RAM is to reenter the debug  
monitor, a TRAP #15 call using function $0063 (SYSCALL  
.RETURN) returns control to the monitor with a new display  
prompt. Note that every time the debug monitor returns to the  
prompt, an R is moved into the MPCR to indicate that control can  
be transferred once again to a specified RAM location.  
GCSR Method  
A remote processor can initiate program execution in the local  
MVME162LX dual-port RAM by issuing a remote GO command  
using the VMEchip2 Global Control and Status Registers (GCSR).  
The remote processor places the MVME162LX execution address in  
general purpose registers 0 and 1 (GPCSR0 and GPCSR1). The  
remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG  
register. This causes the MVME162LX to install breakpoints and  
begin execution. The result is identical to the MPCR method (with  
status code B) described in the previous section.  
The GCSR registers are accessed in the VMEbus short I/O space.  
Each general purpose register is two bytes wide, occurring at an  
even address. The general purpose register number 0 is at an offset  
of $8 (local bus) or $4 (VMEbus) from the start of the GCSR  
registers. The local bus base address for the GCSR is $FFF40100. The  
VMEbus base address for the GCSR depends on the group select  
value and the board select value programmed in the Local Control  
and Status Registers (LCSR) of the MVME162LX. The execution  
address is formed by reading the GCSR general purpose registers  
in the following manner:  
GPCSR0 used as the upper 16 bits of the address  
GPCSR1 used as the lower 16 bits of the address  
3-24  
   
Diagnostic Facilities  
The address appears as:  
GPCSR0 GPCSR1  
3
Diagnostic Facilities  
The 162Bug package includes a set of hardware diagnostics for  
testing and troubleshooting the MVME162LX. To use the  
diagnostics, switch directories to the diagnostic directory. If you are  
in the debugger directory, you can switch to the diagnostic  
directory with the debugger command Switch Directories (SD). The  
diagnostic prompt  
162-Diag>  
appears. Refer to the Debugging Package for Motorola 68K CISC CPUs  
User's Manual for complete descriptions of the diagnostic routines  
available and instructions on how to invoke them. Note that some  
diagnostics depend on restart defaults that are set up only in a  
particular restart mode. The documentation for such diagnostics  
includes restart information.  
Manufacturing Test Process  
During the manufacturing process for MVME162LXs, the  
manufacturing test parameters and testing state flags are stored in  
NVRAM. These strings are installed during the manufacturing  
process and result in the product performing manufacturing tests.  
None of these tests harm the product or system into which a board  
is installed. Entering an ASCII break on the console port from a  
terminal terminates these tests.  
The two state flags that start the test processes are:  
FLASH EMPTY$00122984  
and  
Burnin test$00000000  
3-25  
         
Debugger General Information  
If either string is in the first location of NVRAM ($FFFC0000), the  
test process starts.  
3
3-26  
4Using the 162Bug Debugger  
4
In This Chapter  
This chapter covers the following subjects:  
Entering debugger command lines  
Entering and debugging programs  
Calling system utilities from user programs  
Preserving the debugger operating environment  
Floating point support  
The 162Bug debugger command set  
Entering Debugger Command Lines  
162Bug is command-driven and performs its various operations in  
response to user commands entered at the keyboard. When the  
debugger prompt  
162-Bug>  
appears on the terminal screen, then the debugger is ready to accept  
commands.  
Terminal Input/Output Control  
As the command line is entered, it is stored in an internal buffer.  
Execution begins only after the carriage return is entered, so that  
you can correct entry errors, if necessary, using the control  
characters described below.  
4-1  
Using the 162Bug Debugger  
Note The presence of the upward caret ( ^ ) before a  
character indicates that the Control (CTRL) key must  
be held down while striking the character key.  
^X  
(cancel line)  
The cursor is backspaced to the beginning of the line.  
The cursor is moved back one position.  
Performs the same function as ^H.  
^H  
(backspace)  
(delete)  
4
Delete  
key  
^D  
(redisplay)  
(repeat)  
The entire command line as entered so far is redisplayed on  
the following line.  
^A  
Repeats the previous line. This happens only at the  
command line. The last line entered is redisplayed but not  
executed. The cursor is positioned at the end of the line. You  
may enter the line as is or you can add more characters to it.  
You can edit the line by backspacing and typing over old  
characters.  
When observing output from any 162Bug command, the XON and  
XOFF characters which are in effect for the terminal port may be  
entered to control the output, if the XON/XOFF protocol is enabled  
(default). These characters are initialized to ^S and ^Q respectively  
by 162Bug, but you may change them with the PF command. In the  
initialized (default) mode, operation is as follows:  
^S  
(wait)  
Console output is halted.  
Console output is resumed.  
^Q  
(resume)  
When a command is entered, the debugger executes the command  
and the prompt reappears. However, if the command entered  
causes execution of user target code, for example GO, then control  
may or may not return to the debugger, depending on what the  
user program does.  
For example, if a breakpoint has been specified, then control returns  
to the debugger when the breakpoint is encountered during  
execution of the user program. Alternately, the user program could  
return to the debugger by means of the TRAP #15 ÔÔ.RETURNÕÕ  
function.  
4-2  
Entering Debugger Command Lines  
Debugger Command Syntax  
In general, a debugger command is made up of the following parts:  
The command identifier (i.e., MD or md for the Memory  
Display command). Note that either upper- or lowercase  
characters are allowed.  
4
A port number if the command is set up to work with more  
than one port.  
At least one intervening space before the first argument.  
Any required arguments, as specified by the command.  
An option field, set off by a semicolon (;) to specify conditions  
other than the default conditions of the command.  
The commands are shown using a modified Backus-Naur form  
syntax. The metasymbols used are:  
Syntactic Variables  
The following syntactic variables are encountered in the command  
descriptions which follow. In addition, other syntactic variables  
may be used and are defined in the particular command  
description in which they occur.  
exp  
Expression (described in detail in a following section).  
addr  
Address (described in detail in a following section).  
count  
range  
Count; the syntax is the same as for exp.  
A range of memory addresses which may be speciÞed either  
by addr addr or by addr: count.  
text  
An ASCII string of up to 255 characters, delimited at each end  
by the single quote mark (').  
Expression as a Parameter  
An expression can be one or more numeric values separated by one  
of the arithmetic operators: plus (+), minus (-), multiplied by (*),  
divided by (/), logical AND (&), shift left (<<), or shift right (>>).  
4-3  
Using the 162Bug Debugger  
Numeric values may be expressed in either hexadecimal, decimal,  
octal, or binary notation by immediately preceding them with the  
proper base identifier.  
Base  
Hexadecimal  
Decimal  
Octal  
IdentiÞer  
Examples  
$FFFFFFFF  
$
4
&1974, &10-&4  
@456  
&
@
%
Binary  
%1000110  
If no base identifier is specified, then the numeric value is assumed  
to be hexadecimal.  
A numeric value may also be expressed as a string literal of up to  
four characters. The string literal must begin and end with the  
single quote mark ('). The numeric value is interpreted as the  
concatenation of the ASCII values of the characters. This value is  
right-justified, as any other numeric value would be.  
String  
Numeric Value  
Literal (In Hexadecimal)  
'A'  
41  
'ABC'  
'TEST'  
414243  
54455354  
Evaluation of an expression is always from left to right unless  
parentheses are used to group part of the expression. There is no  
operator precedence. Subexpressions within parentheses are  
evaluated first. Nested parenthetical subexpressions are evaluated  
from the inside out.  
4-4  
Entering Debugger Command Lines  
Valid expression examples:  
Expression  
FF0011  
Result (In Hex)  
Notes  
FF0011  
DE  
45+99  
4
&45+&99  
90  
@35+@67+@10  
%10011110+%1001  
88<<4  
5C  
A7  
880  
A0  
shift left  
logical AND  
AA&F0  
The total value of the expression must be between 0 and  
$FFFFFFFF.  
Address as a Parameter  
Many commands use addr as a parameter. The syntax accepted by  
162Bug is similar to the one accepted by the MC68040 one-line  
assembler. All control addressing modes are allowed. An ÔÔaddress  
+ offset registerÕÕ mode is also provided.  
4-5  
Using the 162Bug Debugger  
Address Formats  
Table 4-1 summarizes the address formats that are acceptable for  
address parameters in debugger command lines.  
Table 4-1. Debugger Address Parameter Formats  
4
Format  
Example  
Description  
N
140  
Absolute address+contents of automatic offset register.  
N+Rn  
130+R5  
Absolute address+contents of the speciÞed offset  
register (not an assembler-accepted syntax).  
(An)  
(A1)  
Address register indirect. (Also post-increment, pre-  
decrement)  
(d,An) or  
d(An)  
(120,A1)  
120(A1)  
Address register indirect with displacement (two  
formats accepted).  
(d,An,Xn) or  
d(An,Xn)  
(&120,A1,D2)  
&120(A1,D2)  
Address register indirect with index and displacement  
(two formats accepted).  
([bd,An,Xn],od)  
([C,A2,A3],&100)  
([12,A3],D2,&10)  
Memory indirect preindexed.  
Memory indirect postindexed.  
([bd,An],Xn,od)  
For the memory indirect modes, Þelds can be omitted.  
For example, three of many permutations are as follows:  
([,An],od)  
([bd])  
([,A1],4)  
([FC1E])  
([8,,D2])  
([bd,,Xn])  
Notes  
N
Ñ
Absolute address (any valid expression).  
An Ñ Address register n.  
Xn Ñ Index register n (An or Dn).  
d
Ñ
Ñ
Ñ
Ñ
Displacement (any valid expression).  
Base displacement (any valid expression).  
Outer displacement (any valid expression).  
Register number (0 to 7).  
bd  
od  
n
Rn Ñ Offset register n.  
4-6  
 
Entering Debugger Command Lines  
Note In commands with range specified as addr addr, and  
with size option W or L chosen, data at the second  
(ending) address is acted on only if the second address  
is a proper boundary for a word or longword,  
respectively.  
4
Offset Registers  
Eight pseudo-registers (R0 through R7) called offset registers are  
used to simplify the debugging of relocatable and position-  
independent modules. The listing files in these types of programs  
usually start at an address (normally 0) that is not the one at which  
they are loaded, so it is harder to correlate addresses in the listing  
with addresses in the loaded program. The offset registers solve  
this problem by taking into account this difference and forcing the  
display of addresses in a relative address+offset format. Offset  
registers have adjustable ranges and may even have overlapping  
ranges. The range for each offset register is set by two addresses:  
base and top. Specifying the base and top addresses for an offset  
register sets its range. In the event that an address falls in two or  
more offset registers' ranges, the one that yields the least offset is  
chosen.  
Note Relative addresses are limited to 1MB (5 digits),  
regardless of the range of the closest offset register.  
Example:  
A portion of the listing file of an assembled, relocatable module is  
shown below:  
1
2
3
4
5
6
7
*
*
*
MOVE STRING SUBROUTINE  
0 00000000 48E78080  
0 00000004 4280  
MOVESTR  
MOVEM.LD0/A0,Ñ(A7)  
CLR.LD0  
0 00000006 1018  
MOVE.B(A0)+,D0  
4-7  
Using the 162Bug Debugger  
8
0 00000008 5340  
SUBQ.W#1,D0  
9
0 0000000A 12D8  
LOOP  
MOVS  
MOVE.B(A0)+,(A1)+  
DBRA D0,LOOP  
MOVEM.L(A7)+,D0/A0  
RTS  
10  
11  
12  
13  
14  
0 0000000C 51C8FFFC  
0 00000010 4CDF0101  
0 00000014 4E75  
4
END  
END  
****** TOTAL ERRORS 0ÑÑ  
****** TOTAL WARNINGS 0ÑÑ  
The above program was loaded at address $0001327C.  
The disassembled code is shown next:  
162-Bug>MD 1327C;DI  
0001327C 48E78080  
00013280 4280  
00013282 1018  
00013284 5340  
00013286 12D8  
00013288 51C8FFFC  
0001328C 4CDF0101  
00013290 4E75  
162-Bug>  
MOVEM.L D0/A0,—(A7)  
CLR.L D0  
MOVE.B (A0)+,D0  
SUBQ.W #1,D0  
MOVE.B (A0)+,(A1)+  
DBF  
D0,$13286  
MOVEM.L (A7)+,D0/A0  
RTS  
By using one of the offset registers, the disassembled code  
addresses can be made to match the listing file addresses as follows:  
162-Bug>OF R0  
R0 =00000000 00000000? 1327C. <CR>  
162Bug>MD 0+R0;DI <CR>  
00000+R0 48E78080  
00004+R0 4280  
00006+R0 1018  
00008+R0 5340  
0000A+R0 12D8  
0000C+R0 51C8FFFC  
00010+R0 4CDF0101  
00014+R0 4E75  
162-Bug>  
MOVEM.L D0/A0,—(A7)  
CLR.L D0  
MOVE.B (A0)+,D0  
SUBQ.W #1,D0  
MOVE.B (A0)+,(A1)+  
DBF  
D0,$A+R0  
MOVEM.L (A7)+,D0/A0  
RTS  
4-8  
Entering and Debugging Programs  
For additional information about the offset registers, refer to the  
Debugging Package for Motorola 68K CISC CPUs User's Manual.  
Port Numbers  
Some 162Bug commands give you the option to choose the port to  
be used to input or output. Valid port numbers which may be used  
for these commands are as follows:  
4
1. MVME162 EIA-232-D Debug (Terminal Port 0 or 00) (Port 1  
on the MVME162LX J17 front panel connector). Sometimes  
known as the ÔÔconsole portÕÕ, it is used for interactive user  
input/output by default.  
2. MVME162 EIA-232-D (Terminal Port 1 or 01) (Port 2 on the  
MVME162LX J17 front panel connector). Sometimes known  
as the ÔÔhost portÕÕ, this is the default for downloading,  
uploading, concurrent mode, and transparent modes.  
3. MVME162 EIA-232-D (Terminal Ports 2 or 02 and 3 or 03)  
(Port 3 and Port 4 on the MVME162LX J17 front panel  
connector). Additional serial ports available.  
Note These logical port numbers (0, 1, 2, and 3) are shown in  
the pinouts of the MVME162LX module as SERIAL  
PORT 1, SERIAL PORT 2, SERIAL PORT 3, and  
SERIAL PORT 4, respectively. Physically, they are all  
part of the front panel 8-pin RJ-45 connectors on J17.  
Entering and Debugging Programs  
There are various ways to enter a user program into system  
memory for execution:  
Create the program with the assembler/disassembler  
Download an S-record object file  
Read the program from disk  
4-9  
Using the 162Bug Debugger  
Creating a Program with the Assembler/Disassembler  
You can create a program using the Memory Modify (MM)  
command with the assembler/disassembler option.  
1. Enter the program one source line at a time.  
2. After each source line is entered, it is assembled and the  
object code is loaded to memory.  
4
Refer to the Debugging Package for Motorola 68K CISC CPUs User's  
Manual for details on the 162Bug Assembler/Disassembler.  
Downloading an S-Record Object File  
Another way to enter a program is to download an object file from  
a host system.  
The program must be in S-record format (described in the  
Debugging Package for Motorola 68K CISC CPUs User's Manual) and  
may have been assembled or compiled on the host system.  
the 162Bug MM command as outlined above and stored to the host  
using the Dump (DU) command.  
A communication link must exist between the host system and port  
2 on the MVME162LX. (Hardware configuration details are  
provided in Installation and Startup on page 3-3.) The file is  
downloaded from the host to MVME162LX memory by the Load  
(LO) command.  
Read the Program from Disk  
Another way to enter a program is by reading the program from  
disk, using one of the disk commands (BO, BH, IOP). Once the  
object code has been loaded into memory, you can set breakpoints  
if desired and run the code or trace through it.  
4-10  
Calling System Utilities from User Programs  
Calling System Utilities from User Programs  
A convenient way of doing character input/output and many other  
useful operations has been provided so that you do not have to  
write these routines into the target code. You can access various  
162Bug routines via one of the MC68040 TRAP instructions, using  
vector #15. Refer to the Debugging Package for Motorola 68K CISC  
CPUs User's Manual for details on the various TRAP #15 utilities  
available and how to invoke them from within a user program.  
4
Preserving the Debugger Operating  
Environment  
This section explains how to avoid contaminating the operating  
environment of the debugger. Topics covered include:  
162Bug Vector Table and workspace  
Hardware functions  
Exception vectors used by 162Bug  
162Bug uses certain of the MVME162LX onboard resources and  
may also use offboard system memory to contain temporary  
variables, exception vectors, etc. If you disturb resources upon  
which 162Bug depends, then the debugger may function unreliably  
or not at all.  
If your application enables translation through the Memory  
Management Units (MMUs), and if your application utilizes  
resources of the debugger (e.g., system calls), your application must  
create the necessary translation tables for the debugger to have  
access to its various resources. The debugger honors the enabling of  
the MMUs; it does not disable translation.  
4-11  
Using the 162Bug Debugger  
162Bug Vector Table and Workspace  
As described in the Memory Requirements section of Chapter 3, the  
162Bug firmware needs 64KB of read/write memory to operate.  
162Bug  
For ...  
reserves ...  
4
1024-byte area  
1024-byte area  
A user program vector table area  
An exception vector table for the debugger itself to use  
Space for static variables, and initializes these static variables to  
predeÞned default values.  
Space for the system stack, and initializes the system stack pointer to  
the top of this area.  
With the exception of the first 1024-byte vector table area, you must  
be extremely careful not to use the above-mentioned memory areas  
for other purposes.  
Refer to the Memory Requirements section of Chapter 3 to determine  
how to dictate the location of the reserved memory areas.  
Examples  
If, for example, your program inadvertently wrote over the  
static variable area containing the serial communication  
parameters, these parameters would be lost, resulting in a  
loss of communication with the system console terminal.  
If your program corrupts the system stack, then an incorrect  
value may be loaded into the processor Program Counter  
(PC), causing a system crash.  
4-12  
Preserving the Debugger Operating Environment  
Hardware Functions  
The only hardware resources used by the debugger are the EIA-  
232-D ports, which are initialized to interface to the debug terminal  
and a host. If these ports are reprogrammed, the terminal  
characteristics must be modified to suit, or the ports should be  
restored to the debugger-set characteristics prior to reinvoking the  
debugger.  
4
Exception Vectors Used by 162Bug  
The exception vectors used by the debugger are listed below. These  
vectors must reside at the specified offsets in the target program's  
vector table for the associated debugger facilities (breakpoints,  
trace mode, etc.) to operate.  
Table 4-2. Exception Vectors Used by 162Bug  
Vector  
Offset  
Exception  
162Bug Facility  
Illegal instruction  
Breakpoints (used by GO, GN, GT)  
Trace operations (such as T, TC, TT)  
Used internally  
$10  
$24  
Trace  
TRAP #0 - #14  
TRAP #15  
$80-$B8  
$BC  
System calls  
Level 7 interrupt  
Level 7 interrupt  
FP Unimplemented Data Type  
ABORT pushbutton  
AC Fail  
$ Note 1  
$ Note 2  
$DC  
Software emulation and data type  
conversion of ßoating point data.  
Notes  
1. This depends on what the Vector Base Register (VBR) is set to in the MC2chip.  
2. This depends on what the Vector Base Register (VBR) is set to in the VMEchip2.  
When the debugger handles one of the exceptions listed in Table  
4-2, the target stack pointer is left pointing past the bottom of the  
exception stack frame created; that is, it reflects the system stack  
4-13  
 
Using the 162Bug Debugger  
pointer values just before the exception occurred. In this way, the  
operation of the debugger facility (through an exception) is  
transparent to users.  
Example: Trace one instruction using the debugger firmware.  
172-Bug>rd  
4
PC  
=00010000  
=0000FFFC  
SR  
=2708=TR:OFF_S._7_N..  
VBR  
DFC  
PCR  
D3  
=00000000  
=1=UD  
SSP  
CACR  
D0  
USP  
=00010000  
SFC  
=1=UD  
=00000000=D: ....._B:..._I:...  
=04310402  
=00000000  
=00000000  
=00000000  
=0000FFFC  
=FFFFFFFF  
=00000000  
=00000000  
=00000000  
=00000007  
D1  
D5  
A1  
A5  
=00000000  
=00000000  
=00000000  
=00000000  
=00000000  
D2  
D6  
A2  
A6  
=00000000  
=00000000  
=00000000  
=00000000  
=00000003  
D4  
D7  
A0  
A3  
A4  
A7  
IPLR  
IML  
R
MMIE  
N
VIEN =C0000000  
VIST  
=00000000  
PIEN =00002000  
PIST  
=00000000  
00010000 203C0000 0001MOVE.L#$1,D0  
172-Bug>t  
PC  
=00010006  
=0000FFFC  
SR  
=2700=TR:OFF_S._7_.....  
VBR  
DFC  
PCR  
D3  
=00000000  
=1=UD  
SSP*  
CACR  
D0  
USP  
=00010000  
SFC  
=1=UD  
=00000000=D: ....._B:..._I:...  
=04310402  
=00000000  
=00000000  
=00000000  
=0000FFFC  
=00000001  
=00000000  
=00000000  
=00000000  
=00000007  
D1  
D5  
A1  
A5  
=00000000  
=00000000  
=00000000  
=00000000  
=00000000  
D2  
D6  
A2  
A6  
=00000000  
=00000000  
=00000000  
=00000000  
=00000003  
D4  
D7  
A0  
A3  
A4  
A7  
IPLR  
IML  
R
MMIE  
N
VIEN =C0000000  
VIST  
=00000000  
PIEN =00002000  
PIST  
=00000000  
00010006 D280 0001ADD.LD0,D1  
172-Bug>  
4-14  
Preserving the Debugger Operating Environment  
Exception Vector Tables  
Notice in the preceding example that the value of the target stack  
pointer register (A7) has not changed even though a trace exception  
has taken place. Your program may either use the exception vector  
table provided by 162Bug or it may create a separate exception  
vector table of its own. The two following sections detail these two  
methods.  
4
Using 162Bug Target Vector Table  
The 162Bug initializes and maintains a vector table area for target  
programs. A target program is any program started by the bug:  
Manually with the GO command  
Manually with trace commands (T, TC, or TT)  
Automatically with the BO command.  
The start address of this target vector table area is the base address  
target-state VBR at power-up and cold-start reset and can be  
observed by using the RD command to display the target-state  
registers immediately after power-up.  
The 162Bug initializes the target vector table with the debugger  
vectors listed in Table 4-2 on page 4-13 and fills the other vector  
locations with the address of a generalized exception handler. The  
target program may take over as many vectors as desired by simply  
writing its own exception vectors into the table. If the vector  
locations listed in Table 4-2 are overwritten, then the accompanying  
debugger functions are lost.  
The 162Bug maintains a separate vector table for its own use. In  
general, you do not have to be aware of the existence of the  
debugger vector table. It is completely transparent and you should  
never make any modifications to the vectors that it contains.  
4-15  
Using the 162Bug Debugger  
Creating a New Vector Table  
Your program may create a separate vector table in memory to  
contain its exception vectors. If this is done, the program must  
change the value of the VBR to point at the new vector table. In  
order to use the debugger facilities you can copy the proper vectors  
from the 162Bug vector table into the corresponding vector  
locations in your program vector table.  
4
The vector for the 162Bug generalized exception handler may be  
copied from offset $08 (bus error vector) in the target vector table to  
all locations in your program vector table where a separate  
exception handler is not used. This provides diagnostic support in  
the event that your program is stopped by an unexpected  
exception. The generalized exception handler gives a formatted  
display of the target registers and identifies the type of the  
exception.  
The following is an example of a routine which builds a separate  
vector table and then moves the VBR to point at it:  
*
*** BUILDX - Build exception vector table ****  
*
BUILDX MOVEC.L VBR,A0  
Get copy of VBR.  
LEA  
$10000,A1  
New vectors at $10000.  
MOVE.L  
MOVE.W  
MOVE.L  
SUBQ.W  
BNE.B  
MOVE.L  
MOVE.L  
MOVE.L  
LEA.L  
$80(A0),D0  
$3FC,D1  
D0,(A1,D1)  
#4,D1  
Get generalized exception vector.  
Load count (all vectors).  
Store generalized exception vector.  
LOOP  
LOOP  
Initialize entire vector table.  
Copy breakpoints vector.  
Copy trace vector.  
Copy system call vector.  
Get your exception vector.  
Install as F-Line handler.  
Change VBR to new table.  
$10(A0),$10(A1)  
$24(A0),$24(A1)  
$BC(A0),$BC(A1)  
COPROCC(PC),A2  
A2,$2C(A1)  
MOVE.L  
MOVEC.L A1,VBR  
RTS  
END  
4-16  
Preserving the Debugger Operating Environment  
It may turn out that your program uses one or more of the exception  
vectors that are required for debugger operation. Debugger  
facilities may still be used, however, if your exception handler can  
determine when to handle the exception itself and when to pass the  
exception to the debugger.  
When an exception occurs which you want to pass on to the  
debugger (i.e., ABORT), your exception handler must read the  
vector offset from the format word of the exception stack frame.  
This offset is added to the address of the 162Bug target program  
vector table (which your program saved), yielding the address of  
the 162Bug exception vector. The program then jumps to the  
address stored at this vector location, which is the address of the  
162Bug exception handler.  
4
Your program must make sure that there is an exception stack  
frame in the stack and that it is exactly the same as the processor  
would have created for the particular exception before jumping to  
the address of the exception handler.  
The following is an example of an exception handler which can pass  
an exception along to the debugger:  
*
*** EXCEPT - Exception handler ****  
*
EXCEPT SUBQ.L  
LINK  
#4,A7  
A6,#0  
Save space in stack for a PC value.  
Frame pointer for accessing PC space.  
MOVEM.L A0-A5/D0-D7,-(SP) Save registers.  
:
: decide here if your code handles exception, if so, branch...  
:
MOVE.L  
MOVE.W  
AND.W  
BUFVBR,A0  
14(A6),D0  
#$0FFF,D0  
Pass exception to debugger; Get saved VBR.  
Get the vector offset from stack frame.  
Mask off the format information.  
MOVE.L  
(A0,D0.W),4(A6)  
Store address of debugger exc handler.  
MOVEM.L (SP)+,A0-A5/D0-D7 Restore registers.  
UNLK  
RTS  
A6  
Put addr of exc handler into PC and go.  
4-17  
Using the 162Bug Debugger  
Floating Point Support  
The floating point unit (FPU) of the MC68040 microprocessor chip  
is supported in 162Bug. The MD, MM, RM, and RS commands have  
been extended to allow display and modification of floating point  
data in registers and in memory. Floating point instructions can be  
assembled and disassembled with the DI option of the MD and MM  
commands.  
4
RM and RS for floating point registers accept the floating point  
value in Double Precision Real Format or Scientific Notation.  
Valid data types that can be used when modifying a floating point  
data register or a floating point memory location:  
Integer Data Types  
12  
Byte  
1234  
Word  
12345678  
Longword  
Floating Point Data Types  
1_FF_7FFFFF  
Single Precision Real Format  
1_7FF_FFFFFFFFFFFFF  
-3.12345678901234501_E+123  
Double Precision Real Format  
ScientiÞc Notation Format (decimal)  
When entering data in single or double precision, you must observe  
the following rules:  
1. The sign field is the first field and is a binary field.  
2. The exponent field is the second field and is a hexadecimal  
field.  
3. The mantissa field is the last field and is a hexadecimal field.  
4-18  
Floating Point Support  
4. The sign field, the exponent field, and at least the first digit of  
the mantissa field must be present (any unspecified digits in  
the mantissa field are set to zero).  
5. Each field must be separated from adjacent fields by an  
underscore.  
4
6. All the digit positions in the sign and exponent fields must be  
present.  
Single Precision Real  
This format would appear in memory as:  
1-bit sign Þeld  
(1 binary digit)  
8-bit biased exponent Þeld  
23-bit fraction Þeld  
(2 hex digits. Bias = $7F)  
(6 hex digits)  
A single precision number takes 4 bytes in memory.  
Double Precision Real  
This format would appear in memory as:  
1-bit sign Þeld  
(1 binary digit)  
11-bit biased exponent Þeld  
52-bit fraction Þeld  
(3 hex digits. Bias = $3FF)  
(13 hex digits)  
A double precision number takes 8 bytes in memory.  
Note The single and double precision formats have an  
implied integer bit (always 1).  
4-19  
Using the 162Bug Debugger  
Scientific Notation  
This format provides a convenient way to enter and display a  
floating point decimal number. Internally, the number is assembled  
into a packed decimal number and then converted into a number of  
the specified data type.  
4
Entering data in this format requires the following fields:  
An optional sign bit (+ or -).  
One decimal digit followed by a decimal point.  
Up to 17 decimal digits (at least one must be entered).  
An optional Exponent field that consists of:  
Ð An optional underscore.  
Ð The Exponent field identifier, letter ÒEÓ.  
Ð An optional Exponent sign (+, -).  
Ð From 1 to 3 decimal digits.  
For more information about the MC68040 floating point unit, refer  
to the MC68040 Microprocessor User's Manual.  
The 162Bug Debugger Command Set  
The 162Bug debugger commands are summarized in Table 4-3. The  
command syntax is shown using the symbols explained earlier in  
this chapter. The CNFG and ENV commands are explained in  
Appendix A. Controllers, devices, and their LUNs are listed in  
Appendix B or Appendix C. All other command details are  
explained in the Debugging Package for Motorola 68K CISC CPUs  
User's Manual.  
4-20  
The 162Bug Debugger Command Set  
Table 4-3. Debugger Commands  
Command  
Mnemonic  
Title  
Command Line Syntax  
AB  
Automatic Bootstrap  
Operating System  
AB [;V]  
NOAB  
AS  
No Autoboot  
NOAB  
4
One Line Assembler  
Block of Memory Compare  
Block of Memory Fill  
AS addr  
BC  
BC range addr [; B|W|L]  
BF  
BF range data [increment]  
[; B|W|L]  
BH  
Bootstrap Operating  
System and Halt  
BH [controller LUN] [device LUN] [string]  
BI  
Block of Memory Initialize  
Block of Memory Move  
Bootstrap Operating System  
Breakpoint Insert  
BI range [; B|W|L]  
BM  
BO  
BR  
BM range addr [; B|W|L]  
BO [ controller LUN] [device LUN] [string]  
BR [addr [:count]]  
NOBR  
BS  
Breakpoint Delete  
NOBR [addr]  
Block of Memory Search  
BS range text [; B|W|L]  
or BS range data [mask] [; B|W|L [,N] [,V]]  
BV  
Block of Memory Verify  
Concurrent Mode  
BV range data [increment] [; B|W|L]  
CM  
CM [[port] [ID-string] [baud]  
[phone-number]]|[; A]|[; H]  
NOCM  
CNFG  
No Concurrent Mode  
NOCM  
ConÞgure Board  
Information Block  
CNFG [; [I][M]]  
CS  
Checksum  
CS range [; B|W|L]  
DC  
Data Conversion  
DC exp | addr [; [B][O][A]]  
DMA  
DMA Block of Memory  
Move  
DMA range addr vdir am blk  
[; B|W|L]  
DS  
One Line Disassembler  
Dump S-records  
DS addr [:count | addr]  
DU  
DU [port] range [text]  
[addr] [offset] [; B|W|L]  
4-21  
Using the 162Bug Debugger  
Table 4-3. Debugger Commands (Continued)  
Command  
Mnemonic  
Title  
Command Line Syntax  
ECHO  
ENV  
Echo String  
ECHO [port] {hexadecimal number} {'string'}  
Set Environment to  
ENV [; [D]]  
Bug/Operating System  
4
GD  
Go Direct (Ignore  
Breakpoints)  
GD [addr]  
GN  
GO  
GT  
Go to Next Instruction  
GN  
Go Execute User Program  
GO [addr]  
Go to Temporary Breakpoint GT addr  
HE  
IOC  
IOI  
IOP  
Help  
HE [command]  
I/O Control for Disk  
I/O Inquiry  
IOC  
IOI [; [C|L]]  
IOP  
I/O Physical (Direct Disk  
Access)  
IOT  
I/O ÔÔTEACHÕÕ for  
IOT [; [A|F|H|T]]  
ConÞguring Disk Controller  
IRQM  
LO  
Interrupt Request Mask  
Load S-records from Host  
Macro DeÞne/Display  
Macro Delete  
IRQM [mask]  
LO [port] [addr] [; [X] [C] [T]] [=text]  
MA [name|; L]  
MA  
NOMA  
MAE  
MAL  
NOMA [name]  
Macro Edit  
MAE name line# [string]  
MAL  
Enable Macro Expansion  
Listing  
NOMAL  
MAW  
MAR  
Disable Macro Expansion  
Listing  
NOMAL  
Save Macros  
MAW [controller LUN] [device LUN]  
[del block #]  
Load Macros  
Memory Display  
MAR [controller LUN] [device LUN]  
[del block #]  
MD  
MD [S] addr [:count | addr]  
[; [B|W|L|S|D|DI]]  
4-22  
The 162Bug Debugger Command Set  
Table 4-3. Debugger Commands (Continued)  
Command  
Mnemonic  
Title  
Command Line Syntax  
MENU  
MM  
Menu  
MENU  
Memory Modify  
Memory Map Diagnostic  
Memory Set  
MM addr [; [[B|W|L|S|D] [A] [N]]|[DI]]  
MMD range increment [; B|W|L]  
MS addr {hexadecimal number} {'string'}  
MW addr data [; B|W|L]  
4
MMD  
MS  
MW  
Memory Write  
NAB  
Automatic Network Boot  
Operating System  
NAB  
NBH  
NBO  
Network Boot Operating  
System and Halt  
NBH [controller LUN] [device LUN]  
[client IP Address] [server IP Address] [string]  
Network Boot Operating  
System  
NBO [controller LUN] [device LUN]  
[client IP Address] [server IP Address] [string]  
NIOC  
NIOP  
NIOT  
NPING  
Network I/O Control  
Network I/O Physical  
Network I/O Teach  
Network Ping  
NIOC  
NIOP  
NIOT [; [H]|[A]]  
NPING controller-LUN device-LUN  
source-IP destination-IP [n-packets]  
OF  
Offset Registers  
Display/Modify  
OF [Rn [; A]]  
PA  
Printer Attach  
PA [port]  
NOPA  
PF  
Printer Detach  
Port Format  
NOPA [port]  
PF [port]  
NOPF  
PFLASH  
Port Detach  
NOPF [port]  
Program FLASH Memory  
PFLASH SSADDR SEADDR DSADDR  
[IEADDR]  
[;[A|R][X]]  
or PFLASH SSADDR:COUNT DSADDR  
[IEADDR]  
[;[B|W|L] [A|R] [X]]  
PS  
Put RTC Into Power Save  
Mode for Storage  
PS  
4-23  
Using the 162Bug Debugger  
Table 4-3. Debugger Commands (Continued)  
Command  
Mnemonic  
Title  
Command Line Syntax  
RB  
ROMboot Enable  
ROMboot Disable  
Register Display  
RB [; V]  
NORB  
RD  
NORB  
4
RD {[+|-|=] [dname] [/]} {[+|-|=]  
[reg1[-reg2]] [/]} [; E]  
REMOTE  
Connect the Remote Modem REMOTE  
to CSO  
RESET  
RL  
Cold/Warm Reset  
Read Loop  
RESET  
RL addr; [B|W|L]  
RM [reg]  
RM  
Register Modify  
Register Set  
RS  
RS reg [exp|addr]  
SD  
SD  
Switch Directories  
Set Time and Date  
Symbol Table Attach  
Symbol Table Detach  
SET  
SET mmddyyhhmm | n; C  
SYM [addr]  
SYM  
NOSYM  
SYMS  
NOSYM  
Symbol Table  
SYMS [symbol-name]|[; S]  
Display/Search  
T
Trace  
T [count]  
TA [port]  
TC [count]  
TA  
TC  
Terminal Attach  
Trace on Change of Control  
Flow  
TIME  
TM  
Display Time and Date  
Transparent Mode  
TIME [; [C|L|O]]  
TM [port] [ESCAPE]  
TT addr  
TT  
Trace to Temporary  
Breakpoint  
VE  
Verify S-Records Against  
Memory  
VE [port] [addr] [; [X][C]] [=text]  
VER  
WL  
Display Revision/Version  
Write Loop  
VER [; E]  
WL addr data [; B|W|L]  
4-24  
AConfigure and Environment  
Commands  
A
Configure Board Information Block  
CNFG [;[I][M]]  
This command is used to display and configure the board  
information block. This block is resident within the Non-Volatile  
RAM (NVRAM). Refer to the Debugging Package for Motorola 68K  
CISC CPUs User's Manual for the actual location. The information  
block contains various elements detailing specific operation  
parameters of the hardware. The Debugging Package for Motorola 68K  
CISC CPUs User's Manual describes the elements within the board  
information block, and lists the size and logical offset of each  
element. The CNFG command does not describe the elements and  
their use. The board information block contents are checksummed  
for validation purposes. This checksum is the last element of the  
block.  
Although the factory fills all fields except the IndustryPack fields,  
only these fields MUST contain correct information:  
MPU clock speed  
Ethernet address  
Local SCSI identifier  
The board structure for the 700/800-series MVME162LX is as  
follows:  
162-Bug>cnfg  
Board (PWA) Serial Number = "  
"
Board Identifier = "  
"
Artwork (PWA) Identifier = "  
MPU Clock Speed = "3200 "  
"
Ethernet Address = 08003E200000  
Local SCSI Identifier = "07 "  
Parity Memory Mezzanine Artwork (PWA) Identifier = "  
"
A-1  
Configure and Environment Commands  
A
Parity Memory Mezzanine (PWA) Serial Number = "  
"
Static Memory Mezzanine Artwork (PWA) Identifier = "  
"
"
"
Static Memory Mezzanine (PWA) Serial Number = "  
"
ECC Memory Mezzanine #1 Artwork (PWA) Identifier = "  
ECC Memory Mezzanine #1 (PWA) Serial Number = "  
"
ECC Memory Mezzanine #2 Artwork (PWA) Identifier = "  
ECC Memory Mezzanine #2 (PWA) Serial Number = "  
"
Serial Port 2 Personality Artwork (PWA) Identifier = "  
Serial Port 2 Personality Module (PWA) Serial Number = "  
"
"
IndustryPack A Board Identifier = "  
IndustryPack A (PWA) Serial Number = "  
"
"
IndustryPack A Artwork (PWA) Identifier = "  
"
"
"
"
IndustryPack B Board Identifier = "  
IndustryPack B (PWA) Serial Number = "  
"
"
IndustryPack B Artwork (PWA) Identifier = "  
IndustryPack C Board Identifier = "  
IndustryPack C (PWA) Serial Number = "  
"
"
IndustryPack C Artwork (PWA) Identifier = "  
IndustryPack D Board Identifier = "  
IndustryPack D (PWA) Serial Number = "  
"
"
IndustryPack D Artwork (PWA) Identifier = "  
162-Bug>  
Note that the parameters that are quoted are left-justified character  
(ASCII) strings padded with space characters, and the quotes (") are  
displayed to indicate the size of the string. Parameters that are not  
quoted are considered data strings, and data strings are right-  
justified. The data strings are padded with zeros if the length is not  
met.  
In the event of corruption of the board information block, the  
command displays a question mark ( ? ) for nondisplayable  
characters. A warning message (WARNING: Board Information Block  
Checksum Error) is also displayed in the event of a checksum failure.  
Using the I option initializes the unused area of the board  
information block to zero.  
A-2  
Set Environment to Bug/Operating System  
A
Modification is possible through use of the commandÕs M option.  
At the end of the modification session, you are prompted for the  
update to Non-Volatile RAM (NVRAM). A Yresponse must be  
made for the update to occur; any other response terminates the  
update (disregards all changes). The update also recalculates the  
checksum.  
Be cautious when modifying parameters. Some of these parameters  
are set up by the factory, and correct board operation relies upon  
these parameters.  
Once modification/update is complete, you can display the current  
contents as described earlier.  
Set Environment to Bug/Operating System  
ENV [;[D]]  
The ENV command allows you to interactively view/configure all  
Bug operational parameters that are kept in battery-backed-up  
RAM (BBRAM), also known as non-volatile RAM (NVRAM). The  
operational parameters are saved in NVRAM and used whenever  
power is lost.  
Whenever the Bug uses a parameter from NVRAM, the NVRAM  
contents are first tested by checksum to insure the integrity of the  
NVRAM contents. In the instance of BBRAM checksum failure,  
certain default values are assumed as stated below.  
The bug operational parameters (which are kept in NVRAM) are  
not initialized automatically on power up/warm reset. It is up to  
the Bug user to invoke the ENV command. Once the ENV command  
is invoked and executed without error, Bug default and/or user  
parameters are loaded into NVRAM along with checksum data. If  
any of the operational parameters have been modified, the new  
parameters do not go into effect until a reset/powerup condition  
occurs. Should you determine that the NVRAM contents have been  
corrupted, use a double-button reset (described under Restarting the  
System in Chapter 3) to reinitialize the system.  
A-3  
Configure and Environment Commands  
A
If the ENV command is invoked with no options on the command  
line, you are prompted to configure all operational parameters. If  
the ENV command is invoked with the option D, ROM defaults will  
be loaded into NVRAM.  
The parameters to be configured are listed in the following table.  
Table A-1. ENV Command Parameters  
ENV Parameter and Options Default  
Meaning of Default  
Bug or System environment  
[B/S]  
B
N
B
Bug mode  
Field Service Menu Enable  
[Y/N]  
Do not display Þeld service menu.  
Remote Start Method Switch  
[G/M/B/N]  
Use both the Global Control and Status  
Register (GCSR) in the VMEchip2, and  
the Multiprocessor Control Register  
(MPCR) in shared RAM, methods to pass  
and start execution of cross-loaded  
programs.  
Probe System for Supported  
I/O Controllers [Y/N]  
Y
Accesses will be made to the appropriate  
system busses (e.g., VMEbus, local MPU  
bus) to determine presence of supported  
controllers.  
Negate VMEbus SYSFAIL*  
Always [Y/N]  
N
Negate VMEbus SYSFAIL after successful  
completion or entrance into the bug  
command monitor.  
Local SCSI Bus Reset on  
Debugger Startup [Y/N]  
N
A
Y
Local SCSI bus is not reset on debugger  
startup.  
Local SCSI Bus Negotiations  
Type [A/S/N]  
Asynchronous negotiations.  
Industry Pack Reset on  
Debugger Startup [Y/N]  
Industry Pack(s) is/are reset on debugger  
startup.  
Ignore CFGA Block on a Hard  
Disk Boot [Y/N]  
Y
Enable the ignorance of the ConÞguration  
Area (CFGA) Block (hard disk only).  
Auto Boot Enable [Y/N]  
N
Auto Boot function is disabled.  
A-4  
Set Environment to Bug/Operating System  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Auto Boot at power-up only  
[Y/N]  
Y
Auto Boot is attempted at power-up reset  
only.  
Auto Boot Controller LUN  
00  
LUN of a disk/tape controller module  
currently supported by the Bug. Default  
is $0.  
Auto Boot Device LUN  
Auto Boot Abort Delay  
00  
15  
LUN of a disk/tape device currently  
supported by the Bug. Default is $0.  
The time in seconds that the Auto Boot  
sequence will delay before starting the  
boot. The purpose for the delay is to allow  
you the option of stopping the boot by  
use of the Break key. The time value is  
from 0 through 255 seconds.  
Auto Boot Default String  
[Y(NULL String)/(String)]  
You may specify a string (Þlename) which  
is passed on to the code being booted.  
Maximum length is 16 characters. Default  
is the null string.  
ROM Boot Enable [Y/N]  
N
Y
ROMboot function is disabled.  
ROM Boot at power-up only  
[Y/N]  
ROMboot is attempted at power up only.  
ROM Boot Enable search of  
VMEbus [Y/N]  
N
VMEbus address space will not be  
accessed by ROMboot.  
ROM Boot Abort Delay  
00  
The time in seconds that the ROMboot  
sequence will delay before starting the  
boot. The purpose for the delay is to allow  
you the option of stopping the boot by  
use of the Break key. The time value is  
from 0 through 255 seconds.  
ROM Boot Direct Starting  
Address  
FF800000 First location tested when the Bug  
searches for a ROMboot Module.  
ROM Boot Direct Ending  
Address  
FFDFFFFC Last location tested when the Bug  
searches for a ROMboot Module.  
A-5  
Configure and Environment Commands  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Network Auto Boot Enable  
[Y/N]  
N
Network Auto Boot function is disabled.  
Network Auto Boot at power-  
up only [Y/N]  
Y
Network Auto Boot is attempted at  
power up reset only.  
Network Auto Boot  
Controller LUN  
00  
LUN of a disk/tape controller module  
currently supported by the Bug. Default  
is $0.  
Network Auto Boot Device  
LUN  
00  
5
LUN of a disk/tape device currently  
supported by the Bug. Default is $0.  
Network Auto Boot Abort  
Delay  
The time in seconds that the Network  
Boot sequence will delay before starting  
the boot. The purpose for the delay is to  
allow you the option of stopping the boot  
by use of the Break key. The time value is  
from 0 through 255 seconds.  
Network Autoboot  
ConÞguration Parameters  
Pointer (NVRAM)  
00000000 The address where the network interface  
conÞguration parameters are to be  
saved/retained in NVRAM; these  
parameters are the necessary parameters  
to perform an unattended network boot.  
Memory Search Starting  
Address  
00000000 Where the Bug begins to search for a  
work page (a 64KB block of memory) to  
use for vector table, stack, and variables.  
This must be a multiple of the debugger  
work page, modulo $10000 (64KB). In a  
multi-162 environment, each  
MVME162LX board could be set to start  
its work page at a unique address to  
allow multiple debuggers to operate  
simultaneously.  
A-6  
Set Environment to Bug/Operating System  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Memory Search Ending  
Address  
00100000 Top limit of the Bug's search for a work  
page. If a contiguous block of memory,  
64KB in size, is not found in the range  
speciÞed by Memory Search Starting  
Address and Memory Search Ending  
Address parameters, then the bug will  
place its work page in the onboard static  
RAM on the MVME162LX. Default  
Memory Search Ending Address is the  
calculated size of local memory.  
Memory Search Increment  
Size  
00010000 A multi-CPU feature used to offset the  
location of the Bug work page. This must  
be a multiple of the debugger work page,  
modulo $10000 (64KB). Typically,  
Memory Search Increment Size is the  
product of CPU number and size of the  
Bug work page. Example: Þrst CPU $0 (0  
x $10000), second CPU $10000 (1 x  
$10000), etc.  
Memory Search Delay Enable  
[Y/N]  
N
No delay before the Bug begins its search  
for a work page.  
A-7  
Configure and Environment Commands  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Memory Search Delay  
Address  
FFFFD20F Default address is $FFFFD20F. This is the  
MVME162LX GCSR (global  
control/status register) GPCSR0 as  
accessed through VMEbus A16 space. It is  
assumed that the MVME162LX GRPAD  
(group address) and BDAD (board  
address within group) switches are set to  
ÔÔonÕÕ. This byte-wide value is initialized  
to $FF by MVME162LX hardware after a  
System or Power-on Reset. In a multi-162  
environment, where the work pages of  
several Bugs will reside in the memory of  
the primary (Þrst) MVME162LX, the non-  
primary CPUs will wait for the data at the  
Memory Search Delay Address to be set  
to $00, $01, or $02 (refer to the Memory  
Requirements section in Chapter 3 for the  
deÞnition of these values) before  
attempting to locate their work page in  
the memory of the primary CPU.  
Memory Size Enable [Y/N]  
Y
Memory will be sized for Self Test  
diagnostics.  
Memory Size Starting  
Address  
00000000 Default Starting Address is $0.  
Memory Size Ending Address  
00100000 Default Ending Address is the calculated  
size of local memory.  
A-8  
Set Environment to Bug/Operating System  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Memory ConÞguration Defaults:  
The default conÞguration for Dynamic RAM mezzanine boards will position the  
mezzanine with the largest memory size to start at the address selected with the ENV  
parameter ÔÔBase Address of Dynamic MemoryÕÕ. The Base Address parameter defaults  
to 0. The smaller sized mezzanine will follow immediately above the larger in the  
memory map. If mezzanines of the same size and type are present, the Þrst (closest to  
the board) is mapped to the selected base address. If mezzanines of same size but with  
different type (parity and ECC) are present, the parity type will be mapped to the  
selected base address and the ECC type mezzanine will follow. The SRAM does not  
default to a location in the memory map that is contiguous with Dynamic RAM.  
Base Address of Dynamic  
Memory  
00000000 Beginning address of Dynamic Memory  
(Parity and/or ECC type memory). It  
must be a multiple of the Dynamic  
Memory board size, starting with 0.  
Default is $0.  
Size of Parity Memory  
00100000 This is the size of the Parity type dynamic  
RAM mezzanine, if any. The default is the  
calculated size of the Dynamic memory  
mezzanine board.  
Size of ECC Memory Board 0  
Size of ECC Memory Board 1  
00000000 This is the size of the Þrst ECC type  
memory mezzanine. The default is the  
calculated size of the memory mezzanine.  
00000000 This is the size of the second ECC type  
memory mezzanine. The default is the  
calculated size of the memory mezzanine.  
Base Address of Static  
Memory  
FFE00000 This is the beginning address of SRAM.  
The default is FFE00000 for the onboard  
128KB SRAM, or E1000000 for the 2MB  
SRAM mezzanine. If only 2MB SRAM is  
present, it defaults to address 00000000.  
Size of Static Memory  
00080000 This is the size of the SRAM type memory  
present. The default is the calculated size  
of the onboard SRAM or an SRAM type  
mezzanine.  
A-9  
Configure and Environment Commands  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
ENV asks the following series of questions to set up the VMEbus interface for the  
MVME162LX modules. You should have a working knowledge of the VMEchip2 as  
given in the MVME162LX Embedded Controller Programmer's Reference Guide in order to  
perform this conÞguration. Also included in this series are questions for setting ROM  
and Flash access time.  
The slave address decoders are used to allow another VMEbus master to access a local  
resource of the MVME162LX. There are two slave address decoders set. They are set up  
as follows:  
Slave Enable #1 [Y/N]  
Y
Yes, set up and enable Slave Address  
Decoder #1.  
Slave Starting Address #1  
00000000 Base address of the local resource that is  
accessible by the VMEbus. Default is the  
base of local memory, $0.  
Slave Ending Address #1  
000FFFFF Ending address of the local resource that  
is accessible by the VMEbus. Default is  
the end of calculated memory.  
Slave Address Translation  
Address #1  
00000000 Register that allows the VMEbus address  
and the local address to be different. The  
value in this register is the base address of  
local resource that is associated with the  
starting and ending address selection  
from the previous questions. Default is 0.  
Slave Address Translation  
Select #1  
00000000 Register that deÞnes which bits of the  
address are signiÞcant. A logical one ÔÔ1ÕÕ  
denotes signiÞcant address bits, a logical  
zero ÔÔ0ÕÕ non-signiÞcant bits. Default is 0.  
Slave Control #1  
03FF  
DeÞnes the access restriction for the  
address space deÞned with this slave  
address decoder. Default is $03FF.  
Slave Enable #2 [Y/N]  
N
Do not set up and enable Slave Address  
Decoder #2.  
Slave Starting Address #2  
00000000 Base address of the local resource that is  
accessible by the VMEbus. Default is 0.  
A-10  
Set Environment to Bug/Operating System  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Slave Ending Address #2  
00000000 Ending address of the local resource that  
is accessible by the VMEbus. Default is 0.  
Slave Address Translation  
Address #2  
00000000 Works the same as Slave Address  
Translation Address #1. Default is 0.  
Slave Address Translation  
Select #2  
00000000 Works the same as Slave Address  
Translation Select #1. Default is 0.  
Slave Control #2  
0000  
DeÞnes the access restriction for the  
address space deÞned with this slave  
address decoder. Default is $0000.  
Master Enable #1 [Y/N]  
Y
Yes, set up and enable the Master Address  
Decoder #1.  
Master Starting Address #1  
02000000 Base address of the VMEbus resource that  
is accessible from the local bus. Default is  
the end of calculated local memory,  
unless memory is less than 16MB, then  
this register will always be set to  
01000000.  
Master Ending Address #1  
Master Control #1  
EFFFFFFF Ending address of the VMEbus resource  
that is accessible from the local bus.  
Default is the end of calculated memory.  
0D  
N
DeÞnes the access characteristics for the  
address space deÞned with this master  
address decoder. Default is $0D.  
Master Enable #2 [Y/N]  
Do not set up and enable the Master  
Address Decoder #2.  
Master Starting Address #2  
00000000 Base address of the VMEbus resource that  
is accessible from the local bus. Default is  
$00000000.  
Master Ending Address #2  
00000000 Ending address of the VMEbus resource  
that is accessible from the local bus.  
Default is $00000000.  
A-11  
Configure and Environment Commands  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Master Control #2  
00  
DeÞnes the access characteristics for the  
address space deÞned with this master  
address decoder. Default is $00.  
Master Enable #3 [Y/N]  
Y/N  
Yes, set up and enable the Master Address  
(Depends Decoder #3. This is the default if the  
on board contains less than 16MB of  
calculated calculated RAM.  
size of  
local  
RAM)  
Do not set up and enable the Master  
Address Decoder #3. This is the default  
for boards containing at least 16MB of  
calculated RAM.  
Master Starting Address #3  
00000000 Base address of the VMEbus resource that  
is accessible from the local bus. If enabled,  
the value is calculated as one more than  
the calculated size of memory. If not  
enabled, the default is $00000000.  
Master Ending Address #3  
Master Control #3  
00000000 Ending address of the VMEbus resource  
that is accessible from the local bus. If  
enabled, the default is $00FFFFFF,  
otherwise $00000000.  
00  
DeÞnes the access characteristics for the  
address space deÞned with this master  
address decoder. If enabled, the default is  
$3D, otherwise $00.  
Master Enable #4 [Y/N]  
N
Do not set up and enable the Master  
Address Decoder #4.  
Master Starting Address #4  
00000000 Base address of the VMEbus resource that  
is accessible from the local bus. Default is  
$0.  
Master Ending Address #4  
00000000 Ending address of the VMEbus resource  
that is accessible from the local bus.  
Default is $0.  
A-12  
Set Environment to Bug/Operating System  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
Master Address Translation  
Address #4  
00000000 Allows the VMEbus address and the local  
address to differ. The value in this register  
is the base address of the VMEbus  
resource that is associated with the  
starting and ending address selection  
from the previous questions. Default is 0.  
Master Address Translation  
Select #4  
00000000 DeÞnes which bits of the address are  
signiÞcant. A logical 1 indicates  
signiÞcant address bits, logical 0 is non-  
signiÞcant. Default is 0.  
Master Control #4  
00  
DeÞnes the access characteristics for the  
address space deÞned with this master  
address decoder. Default is $00.  
Short I/O (VMEbus A16)  
Enable [Y/N]  
Y
Yes, enable the Short I/O Address  
Decoder.  
Short I/O (VMEbus A16)  
Control  
01  
DeÞnes the access characteristics for the  
address space deÞned with the Short I/O  
address decoder. Default is $01.  
F-Page (VMEbus A24) Enable  
[Y/N]  
Y
Yes, enable the F-Page Address Decoder.  
F-Page (VMEbus A24) Control  
ROM Access Time Code  
Flash Access Time Code  
02  
DeÞnes the access characteristics for the  
address space deÞned with the F-Page  
address decoder. Default is $02.  
04  
03  
DeÞnes the ROM access time. The default  
is $04, which sets an access time of Þve  
clock cycles of the local bus.  
DeÞnes the Flash access time. The default  
is $03, which sets an access time of four  
clock cycles of the local bus.  
MCC Vector Base  
VMEC2 Vector Base #1  
VMEC2 Vector Base #2  
05  
06  
07  
Base interrupt vector for the component  
speciÞed. Default: MC2chip = $05,  
VMEchip2 Vector 1 = $06, VMEchip2  
Vector 2 = $07.  
A-13  
Configure and Environment Commands  
A
Table A-1. ENV Command Parameters (Continued)  
ENV Parameter and Options Default  
Meaning of Default  
VMEC2 GCSR Group Base  
Address  
D2  
00  
01  
SpeciÞes the group address ($FFFFXX00)  
in Short I/O for this board. Default = $D2.  
VMEC2 GCSR Board Base  
Address  
SpeciÞes the base address ($FFFFD2XX)  
in Short I/O for this board. Default = $00.  
VMEbus Global Time Out  
Code  
Controls the VMEbus timeout when the  
MVME162LX is operating as system  
controller. Default $01 = 64 µs.  
Local Bus Time Out Code  
02  
02  
Controls the local bus timeout. Default  
$02 = 256 µs.  
VMEbus Access Time Out  
Code  
Controls the local bus to VMEbus access  
timeout. Default $02 = 32 ms.  
Configuring the IndustryPacks  
ENV asks the following series of questions to set up IndustryPacks  
(IPs) on MVME162LX VMEmodules.  
The MVME162LX Embedded Controller Programmer's Reference Guide  
describes the base addresses and the IP register settings. Refer to  
that manual for information on setting base addresses and register  
bits.  
Note The IP2 ASIC on the MVME162LX supports up to four  
IndustryPack (IP) interfaces, designated IP_a through  
IP_d. The 700/800-series MVME162LX itself  
accommodates two IPs: IP_a and IP_b. In the following  
discussion, the segments applicable to IP_c and IP_d  
are not used in the 700/800-series MVME162LX.  
IP A Base Address  
IP B Base Address  
IP C Base Address  
IP D Base Address  
= 00000000?  
= 00000000?  
= 00000000?  
= 00000000?  
A-14  
Set Environment to Bug/Operating System  
A
Base address for mapping IP modules. Only the upper 16 bits are  
significant.  
IP D/C/B/A Memory Size  
= 00000000?  
Define the memory size requirements for the IP modules:  
Bits  
IP  
Register  
Address  
31-24  
23-16  
15-08  
07-00  
D
C
B
FFFBC00F  
FFFBC00E  
FFFBC00D  
FFFBC00C  
A
IP D/C/B/A General Control  
= 00000000?  
Define the general control requirements for the IP modules:  
Bits  
IP  
Register  
Address  
31-24  
23-16  
15-08  
07-00  
D
C
B
FFFBC01B  
FFFBC01A  
FFFBC019  
FFFBC018  
A
A-15  
Configure and Environment Commands  
A
IP D/C/B/A Interrupt 0 Control = 00000000?  
Define the interrupt control requirements for the IP modules  
channel 0:  
Bits  
IP  
Register  
Address  
31-24  
23-16  
15-08  
07-00  
D
C
B
FFFBC016  
FFFBC014  
FFFBC012  
FFFBC010  
A
IP D/C/B/A Interrupt 1 Control = 00000000?  
Define the interrupt control requirements for the IP modules  
channel 1:  
Bits  
IP  
Register  
Address  
31-24  
23-16  
15-08  
07-00  
D
C
B
FFFBC017  
FFFBC015  
FFFBC013  
FFFBC011  
A
Before environment parameters are saved in the  
NVRAM, a warning message will appear if you have  
specified environment parameters that will cause an  
overlap condition. The important information about  
each configurable element in the memory map is  
displayed, showing where any overlap conditions exist.  
This will allow you to quickly identify and correct an  
undesirable configuration before it is saved.  
!
Caution  
A-16  
Set Environment to Bug/Operating System  
A
ENV warning example:  
WARNING: Memory MAP Overlap Condition Exists  
S-Address  
$00000000  
$FFE00000  
$01000000  
$00000000  
$00000000  
$00000000  
$F0000000  
$FFFF0000  
$FF800000  
$FFF00000  
$00000000  
$00000000  
$00000000  
$00000000  
$00000000  
$00000000  
E-Address Enable Overlap M-Type  
Memory-MAP-Name  
Local Memory (Dynamic RAM)  
Static RAM  
VMEbus Master #1  
VMEbus Master #2  
VMEbus Master #3  
VMEbus Master #4  
VMEbus F Pages (A24/A32)  
VMEbus Short I/O (A16)  
Flash/PROM  
$FFFFFFFF Yes  
$FFE7FFFF Yes  
$EFFFFFFF Yes  
$00000000 No  
$00FFFFFF Yes  
$00000000 No  
$FF7FFFFF Yes  
$FFFFFFFF Yes  
$FFBFFFFF Yes  
$FFFEFFFF Yes  
$00000000 No  
$00000000 No  
$00000000 No  
$00000000 No  
$00000000 No  
$00000000 No  
Yes  
Yes  
Yes  
No  
Yes  
No  
Yes  
Yes  
Yes  
Yes  
No  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Master  
Slave  
Local I/O  
Industry Pack A  
Industry Pack B  
Industry Pack C  
Industry Pack D  
VMEbus Slave #1  
VMEbus Slave #2  
No  
No  
No  
No  
No  
Slave  
A-17  
Configure and Environment Commands  
A
A-18  
BDisk/Tape Controller Data  
B
Disk/Tape Controller Modules Supported  
The following VMEbus disk/tape controller modules are  
supported by the 162Bug. The default address for each controller  
type is First Address and the controller can be addressed by First  
CLUN during commands BH, BO, or IOP, or during TRAP #15  
calls .DSKRD or .DSKWR. Note that if another controller of the  
same type is used, the second one must have its address changed by  
its onboard jumpers and/or switches, so that it matches the  
ÔÔSecond AddressÕÕ value and can be called up by the ÔÔSecond  
CLUNÕÕ value.  
First  
CLUN  
First  
Address  
Second  
CLUN  
Second  
Address  
Controller Type  
CISC Embedded Controller  
MVME328 - SCSI Controller 1  
MVME328 - SCSI Controller 2  
MVME328 - SCSI Controller 3  
$00*  
$06  
$16  
$18  
--  
--  
--  
$FFFF9000  
$FFFF4800  
$FFFF7000  
$07  
$17  
$19  
$FFFF9800  
$FFFF5800  
$FFFF7800  
*If an MVME162LX with an SCSI port is used, that board has CLUN 0.  
B-1  
Disk/Tape Controller Data  
B
B
Disk/Tape Controller Default Configurations  
Note SCSI Common Command Set (CCS) devices are the  
only ones tested by Motorola Computer Group.  
CISC Embedded Controllers -- 7 Devices  
Controller LUN  
Address  
Device LUN  
Device Type  
0
$XXXXXXXX  
00  
10  
20  
30  
40  
50  
60  
SCSI Common Command Set  
(CCS), which may be any of these:  
- Fixed direct access  
- Removable ßexible direct access  
(TEAC style)  
- CD-ROM  
- Sequential access  
B-2  
Disk/Tape Controller Default Configurations  
B
B
MVME328 -- 14 Devices  
Controller LUN  
Address  
Device LUN  
Device Type  
6
$FFFF9000  
00  
08  
10  
18  
20  
28  
30  
SCSI Common Command Set  
(CCS), which may be any of these:  
- Removable ßexible direct access  
(TEAC style)  
7
$FFFF9800  
$FFFF4800  
- CD-ROM  
16  
- Sequential access  
17  
18  
19  
$FFFF5800  
$FFFF7000  
$FFFF7800  
40  
48  
50  
58  
60  
68  
70  
Same as above, but these are only  
available if the daughter card for the  
second SCSI channel is present.  
B-3  
Disk/Tape Controller Data  
B
B
IOT Command Parameters for Supported  
Floppy Types  
The following table lists the proper IOT command parameters for  
floppies used with boards such as the MVME328 and  
MVME162LX.  
Floppy Types and Formats  
IOT Parameter  
DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT  
PS2  
SHD  
Sector Size  
0- 128 1- 256 2- 512  
3-1024 4-2048 5-4096 =  
1
2
2
2
2
2
2
Block Size:  
0- 128 1- 256 2- 512  
3-1024 4-2048 5-4096 =  
1
1
8
1
9
1
9
1
F
1
1
Sectors/Track  
10  
2
12  
2
24  
2
Number of Heads =  
Number of Cylinders =  
Precomp. Cylinder =  
2
2
2
2
50  
50  
50  
28  
28  
28  
28  
28  
28  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
Reduced Write Current  
Cylinder =  
Step Rate Code =  
0
0
0
0
0
0
0
Single/Double DATA  
Density =  
D
D
D
D
D
D
D
Single/Double TRACK  
Density =  
D
S
D
E
S
D
E
S
D
E
S
D
E
F
D
E
F
D
E
F
Single/Equal_in_all Track  
Zero Density =  
Slow/Fast Data Rate =  
Other Characteristics  
S
Number of Physical Sectors  
0A00  
0280  
02D0  
05A0  
0960  
0B40  
1680  
B-4  
IOT Command Parameters for Supported Floppy Types  
B
B
Floppy Types and Formats  
IOT Parameter  
DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT  
PS2  
SHD  
Number of Logical Blocks  
(100 in size)  
09F8  
0500  
05A0  
0B40  
12C0  
1680  
2D00  
Number of Bytes in Decimal 653312  
327680  
368460  
737280 1228800 1474560 2949120  
Media Size/Density  
5.25/DD 5.25/DD 5.25/DD 3.5/DD 5.25/HD 3.5/HD 3.5/ED  
Notes  
1. All numerical parameters are in hexadecimal format unless otherwise noted.  
2. The DSDD5 type ßoppy is the default setting for the debugger.  
B-5  
Disk/Tape Controller Data  
B
B
B-6  
CNetwork Controller Data  
C
Network Controller Modules Supported  
The following VMEbus network controller modules are supported  
by the MVME162BUG firmware. The default address for each type  
and position is showed to indicate where the controller must reside  
to be supported by MVME162BUG. The controllers are accessed via  
the specified CLUN and DLUNs listed here. The CLUN and DLUN  
are used in conjunction with the debugger commands NBH, NBO,  
NIOP, NIOC, NIOT, NPING, and NAB, and also with the debugger  
system calls .NETRD, .NETWR, .NETFOPN, .NETFRD, .NETCFIG,  
and .NETCTRL.  
Controller  
Type  
Interface  
Type  
CLUN DLUN  
Address  
MVME162  
$00  
$02  
$03  
$04  
$05  
$06  
$07  
$10  
$11  
$12  
$13  
$14  
$15  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$00  
$FFF46000  
$FFFF1200  
$FFFF1400  
$FFFF1600  
$FFFF5400  
$FFFF5600  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
MVME376 #1  
MVME376 #2  
MVME376 #3  
MVME376 #4  
MVME376 #5  
MVME376 #6  
MVME374 #1  
MVME374 #2  
MVME374 #3  
MVME374 #4  
MVME374 #5  
MVME374 #6  
$FFFFA400 Ethernet  
$FF000000  
$FF100000  
$FF200000  
$FF300000  
$FF400000  
$FF500000  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
Ethernet  
C-1  
Network Controller Data  
C
C-2  
DTroubleshooting CPU Boards  
D
Solving Startup Problems  
In the event of difficulty with your CPU board, try the simple  
troubleshooting steps on the following pages before calling for help  
or sending the board back for repair. Some of the procedures will  
return the board to the factory debugger environment. (The board  
was tested under those conditions before it left the factory.) The  
self-tests may not run in all user-customized environments.  
Table D-1. Troubleshooting MVME162LX Boards  
Condition  
Possible Problem  
Try This:  
I. Nothing works,  
no display on  
the terminal.  
A. If the FUSES  
LED is not lit,  
the board may  
not be getting  
correct power.  
1. Make sure the system is plugged in.  
2. Check that the board is securely installed in its backplane  
or chassis.  
3. Check that all necessary cables are connected to the board,  
per this manual.  
4. Check for compliance with System Considerations, per  
this manual.  
5. Review the Installation and Startup procedures, per this  
manual. They include a step-by-step powerup routine. Try  
it.  
B. If the LEDs are  
lit, the board  
may be in the  
wrong slot.  
1. For VMEmodules, the CPU board should be in the Þrst  
(leftmost) slot.  
2. Also check that the Òsystem controllerÓ function on the  
board is enabled, per this manual.  
C. The Òsystem  
consoleÓ  
ConÞgure the system console terminal per this manual.  
terminal may  
be conÞgured  
incorrectly.  
D-1  
   
Troubleshooting CPU Boards  
Table D-1. Troubleshooting MVME162LX Boards (Continued)  
Condition  
Possible Problem  
Try This:  
II. There is a  
display on the  
terminal, but  
input from the  
keyboard  
A. The keyboard or Recheck the keyboard and/or mouse connections and  
mouse may be  
connected  
power.  
incorrectly.  
D
B. Board jumpers  
may be  
Check the board jumpers per this manual.  
and/or mouse  
has no effect.  
conÞgured  
incorrectly.  
C. You may have  
invoked ßow  
control by  
Press the HOLD or PAUSE key again.  
If this does not free up the keyboard, type in:  
<CTRL>-Q  
pressing a  
HOLD or PAUSE  
key, or by  
typing:  
<CTRL>-S  
III. Debug prompt  
162-Bug>  
A. Debugger  
1. Disconnect all power from your system.  
EPROM/Flash  
may be missing  
2. Check that the proper debugger EPROM or debugger  
Flash memory is installed per this manual.  
does not  
appear at  
power-up, and  
the board does  
not autoboot.  
3. Reconnect power.  
B. The board may  
need to be reset. 4. Restart the system by Òdouble-button resetÓ: press the  
RESET and ABORT switches at the same time; release  
RESET Þrst, wait seven seconds, then release ABORT.  
5. If the debug prompt appears, go to step IV or step V, as  
indicated. If the debug prompt does not appear, go to step  
VI.  
IV. Debug prompt  
162-Bug>  
A. The initial  
debugger  
1. Start the onboard calendar clock and timer. Type:  
set mmddyyhhmm <CR>  
appears at  
environment  
parameters  
may be set  
incorrectly.  
where the characters indicate the month, day, year, hour,  
and minute. The date and time will be displayed.  
powerup, but  
the board does  
not autoboot.  
Performing the next step  
(env;d) will change some  
parameters that may affect  
your systemÕs operation.  
B. There may be  
some fault in the  
board hardware.  
!
Caution  
(continues>)  
D-2  
 
Solving Startup Problems  
Table D-1. Troubleshooting MVME162LX Boards (Continued)  
Condition  
Possible Problem  
Try This:  
IV. Continued  
2. At the command line prompt, type in:  
env;d <CR>  
This sets up the default parameters for the debugger  
environment.  
D
3. When prompted to Update Non-Volatile RAM, type in:  
y <CR>  
4. When prompted to Reset Local System, type in:  
y <CR>  
5. After clock speed is displayed, immediately (within Þve  
seconds) press the Return key:  
<CR>  
or  
BREAK  
to exit to the System Menu. Then enter a 3 for ÒGo to  
System DebuggerÓ and Return:  
3 <CR>  
Now the prompt should be:  
162-Diag>  
6. You may need to use the cnfg command (see your board  
Debugger Manual) to change clock speed and/or Ethernet  
Address, and then later return to:  
env <CR>  
and step 3.  
7. Run the selftests by typing in:  
st <CR>  
The tests take as much as 10 minutes, depending on RAM  
size. They are complete when the prompt returns. (The  
onboard selftest is a valuable tool in isolating defects.)  
8. The system may indicate that it has passed all the selftests.  
Or, it may indicate a test that failed. If neither happens,  
enter:  
de <CR>  
Any errors should now be displayed. If there are any  
errors, go to step VI. If there are no errors, go to step V.  
D-3  
Troubleshooting CPU Boards  
Table D-1. Troubleshooting MVME162LX Boards (Continued)  
Condition  
Possible Problem  
Try This:  
V. The debugger is A. No apparent  
No further troubleshooting steps are required.  
in system mode  
and the board  
autoboots, or  
the board has  
passed  
problems Ñ  
troubleshooting  
is done.  
D
selftests.  
VI. The board has  
failed one or  
more of the  
A. There may be  
some fault in  
the board  
1. Document the problem and return the board for service.  
2. Phone 1-800-222-5640.  
tests listed  
above, and  
hardware or the  
on-board  
cannot be  
corrected using  
the steps given.  
debugging and  
diagnostic  
Þrmware.  
TROUBLESHOOTING PROCEDURE COMPLETE.  
D-4  
Index  
162Bug 4-1  
gram with 4-10  
autoboot function 3-7  
162Bug default controller and device pa-  
rameters 3-19  
autojumpering function 2-17  
162Bug stack space 3-14  
162Bug static variable space 3-14  
162Bug vector table and workspace 4-13  
172Bug  
backplane jumpers 2-17  
Backus-Naur syntax, debugger com-  
mands and 4-3  
base and top addresses 4-7  
battery 1-19  
battery-backed-up RAM (BBRAM) and  
BBRAM (battery-backed-up RAM) 1-21  
BH (bootstrap and halt) command 3-17  
binary numbers 1-12  
implementation of 3-3  
27C040 EPROM 3-3  
82596CA 1-23  
A
Abort function 3-11  
ABORT switch 1-14  
address (command syntax) 4-3  
address formats 4-6, 4-7  
address range 1-28  
block diagram 1-14  
board layout 2-2  
address ranges, EPROM 2-10  
address/data configurations 2-18  
addresses as command parameters 4-5  
addressing disk/tape controllers B-1  
addressing mode, extended 2-18  
arguments, command line 4-3  
arithmetic operators 4-3  
ASCII string (command syntax) 4-3  
ASICs  
boot functions  
autoboot 3-7  
network boot 3-10  
ROMboot 3-9  
BOOTP protocol module 3-21  
MC2chip 2-10, 2-12  
IN-5  
Index  
BREAK key 3-12  
bus grant (BG) signal 2-17  
byte, definition of 1-13  
debugger command set 4-20  
Configure Board Information Block  
(CNFG) A-1  
Set Environment (ENV) A-3  
C
C programming language 3-3  
cable(s) 2-17  
debugger prompt 4-1  
checksum, testing NVRAM contents  
with A-3  
CLUN (controller LUN) B-2, C-1  
command identifier, debugger 4-3  
command syntax, debugger 4-3  
commands  
defaul configuration, disk/tape control-  
ler B-2  
directories  
switching 3-25  
disk I/O error codes 3-19  
disk I/O support 3-15  
Disk I/O via 172Bug Commands 3-16  
disk/tape controller data B-1  
DLUN (device LUN) B-2, C-1  
Configure Board Information Block  
(CNFG) A-1  
Set Environment (ENV) A-3  
configuration, hardware 3-4  
configuring IndustryPacks A-14  
configuring the board 2-1  
connections, serial cable 2-20  
connectors, MVME162LX 1-27  
console port 4-9  
control bit, definition of 1-13  
control module, network boot 3-21  
controller and device parameters,  
162Bug 3-19  
non-Motorola 1-5  
other applicable Motorola publica-  
tions 1-4  
controller LUN (CLUN) B-2, C-1  
cooling requirements 1-10  
creating a program 4-10  
double precision real (floating point for-  
mat) 4-19  
downloading S-record object files 4-10  
DRAM (dynamic RAM)  
D
I
data bus structure 1-16  
data terminal equipment (DTE) 1-22  
date and time, setting 3-7  
debug monitor 2-3  
debug port 4-9  
DRAM base address 2-18  
DTE (data terminal equipment) 1-22  
N
D
E
X
E
ECC DRAM 2-13  
debugger  
EIA-232-D ports 3-5, 4-13  
IN-6  
elevated-temperature operation 1-10  
entering and debugging programs 4-9  
entering debugger command lines 4-1  
ENV command parameters A-4  
EPROM and Flash memory 1-21  
EPROM sockets 2-9  
G
GCSR (global control/status register)  
GPCSR0 bit A-8  
GCSR (global control/status registers)  
global control/status registers (GCSR)  
2-19  
EPROM/Flash selection 2-12  
error codes, disk I/O 3-19  
error codes, network I/O 3-22  
Ethernet C-1  
station address 1-23  
Ethernet driver 3-20  
Ethernet interface 1-23  
exception vectors, 162Bug 4-13  
exponent field (floating point support)  
4-18  
expression (command syntax) 4-3  
expressions as parameters 4-3  
extended addressing mode 2-18  
H
handshaking, forms of 3-6  
hardware configuration 3-4  
hardware features, description of 1-1  
hardware functions, 162Bug 4-13  
hardware interrupts 1-26  
hexadecimal characters 1-12  
host port 4-9  
host systems, downloading object files  
from 4-10  
I
2-17  
F
FCC compliance 1-12  
features 1-6  
firmware 2-3  
IndustryPacks  
firmware console 3-5  
defining general control require-  
ments A-15  
defining interrupt control require-  
ments A-16  
defining memory size requirements  
A-15  
firmware implementation 3-3  
firmware overview 3-1  
Flash memory 2-9, 3-3, 3-7  
initializing 3-7  
flexible diskettes, accessing B-2  
floating point instructions 4-18  
floating point unit (FPU) 4-18, 4-20  
floppy disk command parameters B-4  
format, S-record 4-10  
input/output control, terminal 4-1  
installation  
I
N
D
E
X
considerations 2-18  
FPU (floating point unit) 4-18, 4-20  
front panel switches and indicators 1-14  
functional description 1-14  
IP (IndustryPack) 2-15  
MVME162LX 2-16, 2-18  
installation and startup 3-3  
instructions, floating point 4-18  
IN-7  
Index  
Intel 82596 LAN coprocessor Ethernet  
driver 3-20  
J20 (EPROM/Flash configuration)  
interface  
J21 (general-purpose readable jump-  
ers) 2-12  
IndustryPack (IP) 1-23  
SCSI 1-24  
serial communications 2-19  
user-definable 2-12  
LAN driver 3-20  
LEDs 1-14  
local bus timeout function 1-26  
local processor resources 1-25  
longword, definition of 1-13  
interprocessor communication 3-22  
interrupts, hardware 1-26  
IOC (I/O control) command 3-17  
IOI (input/output inquiry) command  
3-16  
IOT (I/O teach) command 3-17  
IOT command parameters for supported  
IP (IndustryPack) installation 2-15  
IP32 CSR bit 2-5  
mantissa field (floating point support)  
4-18  
manufacturing test process 3-25  
mapping, EPROM/Flash 2-11  
MC2chip 2-10, 2-12  
MC68040 cache 1-16  
MC68040 MPU 1-16  
MC68040 TRAP instructions 4-11  
memory  
memory boards 2-13  
memory map  
ISP (Interrupt Stack Pointer) 3-14  
J
jumper headers 3-3  
J21 (general-purpose readable jump-  
ers) 1-17  
jumper headers, setting 2-3  
jumper settings 2-2  
local bus 1-28  
jumpers  
local I/O devices 1-31  
backplane 2-17  
J1 (system controller selection) 2-3  
J12 (SCSI terminator configuration)  
2-6  
J14 (SRAM backup power source) 2-6  
J16 (Flash write protection) 2-7  
J18 (IP bus strobe selection) 2-8  
J18 (IP bus strobe) 3-5  
J19 (IP DMA snoop control) 2-8, 3-5  
memory mezzanines  
stacking options 2-14  
memory options 1-17  
memory requirements, 162Bug 3-13  
metasymbols, command syntax and 4-3  
mezzanine boards 2-13  
I
N
D
E
X
IN-8  
microprocessor, description of 1-16  
Multiprocessor Control Register (MPCR)  
3-22  
Multiprocessor Control Register (MPCR)  
method 3-22  
multiprocessor support 3-22  
MVME162Bug 1-17, 3-1  
MVME162Bug (162Bug) 2-3  
MVME162LX block diagram 1-15  
MVME162LX features 1-6  
MVME162LX installation 2-16  
MVME162LX specifications 1-9  
MVME172 C-1  
overview 1-1  
parity DRAM 2-13  
port 1 or 01 4-9  
port 2 or 02 4-9  
port 3 or 03 4-9  
prompt, debugger 4-1  
protocol modules  
BOOTP 3-21  
protocol modules, TFTP 3-21  
MVME376 C-1  
N
network boot control module 3-21  
network boot function 3-10  
network controller modules supported  
C-1  
R
reading a program from disk 4-10  
network I/O error codes 3-22  
network I/O support 3-19  
non-volatile RAM (NVRAM) A-3  
normal address range 1-28  
no-VMEbus-interface option 1-17, 3-7  
numeric values and base identifiers 4-4  
NVRAM (non-volatile RAM) A-3  
related documentation 1-3  
remote program execution 3-22  
Reset function 3-11  
RESET switch 1-14  
RF emissions 1-12, 2-16  
ROMboot function 3-9  
O
object code 4-10  
I
offset registers 4-7  
N
D
E
X
S
operating environment, debugger 4-11  
operating temperature 1-10  
operating the board 3-3  
operational parameters, 162Bug A-3  
option field, command line 4-3  
scientific notation (floating point format)  
4-20  
SCSI controllers B-1, B-2, B-3  
SCSI interface 1-24  
IN-9  
terminal input/output control 4-1  
TFTP protocol module 3-21  
tick timers 1-25  
serial cable connections 2-20  
serial communications 2-19  
serial  
communications  
(Z85230s) 3-6  
Controllers  
timeout function  
serial ports 3-5, 4-13  
default baud rate 3-5  
serial ports 1-4 4-9  
shielded cables 2-17  
sign field (floating point support) 4-18  
single precision real 4-19  
single precision real (floating point for-  
mat) 4-19  
timeout, global bus 2-18  
timers, programmable 1-25  
transfer type (TT) signals 1-28  
TRAP instructions 4-11  
troubleshooting procedures D-1  
true, definition of 1-13  
U
slave address decoders, VMEbus inter-  
face A-10  
UDP/IP protocol modules 3-20  
unpacking the equipment 2-1  
user-definable jumpers 2-12  
using the 162Bug debugger 4-1  
utilities, TRAP #15 4-11  
software-programmable hardware inter-  
rupts 1-26  
source lines, entering 4-10  
specifications 1-9  
V
options 1-18  
vector table, 162Bug 4-12  
vector tables, creating 4-16  
SRAM battery 1-19  
S-record files, downloading 4-10  
specification 1-5  
stacking mezzanine boards 2-13  
startup, MVME162LX 3-3  
status bit, definition of 1-13  
4-3  
VMEbus access to local bus 1-34  
VMEbus interface 1-21  
Registers)ASICs  
SYSFAIL* signal  
I
VMEchip2 3-24  
assertion/negation 3-12  
system calls, 162Bug 3-17  
system console 3-5  
system controller function 3-5  
System Fail (SYSFAIL*) signal 3-9  
system utilities, calling from user pro-  
grams 4-11  
N
D
E
X
W
watchdog timer 1-25  
IN-10  
Z
Z85230 serial communications control-  
lers (SCCs) 3-6  
I
N
D
E
X
IN-11  

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