Motorola Computer Hardware MC68HC05RC16 User Manual

HC05RC16GRS/D  
REV. 3.0  
MC68HC05RC8  
MC68HC05RC16  
Ge ne ra l Re le a se Sp e c ific a tion  
Oc to b e r 24, 1996  
CSIC MCU De sig n Ce nte r  
Austin, Te xa s  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
List of Se c tions  
Se c tion 1. Ge ne ra l De sc rip tion . . . . . . . . . . . . . . . . . . . 15  
Se c tion 2. Me m ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Se c tion 3. Ce ntra l Proc e ssor Unit . . . . . . . . . . . . . . . . . 33  
Se c tion 4. Inte rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Se c tion 5. Re se ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Se c tion 6. Low-Powe r Mod e s . . . . . . . . . . . . . . . . . . . . 53  
Se c tion 7. Pa ra lle l Inp ut/ Outp ut (I/ O) . . . . . . . . . . . . . . 57  
Se c tion 8. Core Tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Se c tion 9. Ca rrie r Mod ula tor Tra nsm itte r (CMT) . . . . . . 67  
Se c tion 10. Instruc tion Se t . . . . . . . . . . . . . . . . . . . . . . . 85  
Se c tion 11. Ele c tric a l Sp e c ific a tions . . . . . . . . . . . . . . 103  
Se c tion 12. Me c ha nic a l Sp e c ific a tions . . . . . . . . . . . 111  
Se c tion 13. Ord e ring Inform a tion . . . . . . . . . . . . . . . . 115  
Ap p e nd ix A. MC68HC05RC8 . . . . . . . . . . . . . . . . . . . . 119  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
List of Sections  
3
List of Se c tions  
General Release Specification  
4
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
List of Sections  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Ta b le of Conte nts  
Se c tion 1. Ge ne ra l De sc rip tion  
1.1  
1.2  
1.3  
1.4  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19  
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
1.5  
1.5.1  
1.5.2  
1.5.3  
1.5.4  
1.5.5  
1.5.6  
1.5.7  
1.5.8  
1.5.9  
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
DD SS  
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .23  
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
PC0–PC3 (PC4–PC7). . . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
Se c tion 2. Me m ory  
2.1  
2.2  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
2.3  
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30  
ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30  
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31  
2.3.1  
2.3.2  
2.3.3  
2.4  
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .31  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Table of Contents  
5
Ta b le of Conte nts  
Se c tion 3. Ce ntra l Proc e ssor Unit  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35  
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36  
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36  
Se c tion 4. Inte rrup ts  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
4.9  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  
CPU Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41  
External Interrupt (IRQ/Port B Keyscan). . . . . . . . . . . . . . . . . .41  
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42  
Carrier Modulator Transmitter Interrupt (CMT). . . . . . . . . . . . .42  
4.10 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43  
Se c tion 5. Re se ts  
5.1  
5.2  
5.3  
5.4  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45  
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46  
Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .48  
General Release Specification  
6
MC68HC05RC16 — Rev. 3.0  
Table of Contents  
MOTOROLA  
Table of Contents  
5.5  
5.5.1  
5.5.2  
5.5.2.1  
5.5.2.2  
5.5.2.3  
5.5.2.4  
5.5.2.5  
5.5.3  
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48  
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48  
Computer Operating Properly Reset (COPR) . . . . . . . . . . .49  
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49  
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49  
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49  
COP Watchdog Timer Considerations. . . . . . . . . . . . . . .50  
COP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51  
Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51  
Se c tion 6. Low-Powe r Mod e s  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53  
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53  
Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54  
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54  
Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55  
Se c tion 7. Pa ra lle l Inp ut/ Outp ut (I/ O)  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .59  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Table of Contents  
7
Ta b le of Conte nts  
Se c tion 8. Core Tim e r  
8.1  
8.2  
8.3  
8.4  
8.5  
8.6  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61  
Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .63  
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .65  
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .66  
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66  
Se c tion 9. Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67  
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67  
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68  
9.1  
9.2  
9.3  
9.4  
9.4.1  
9.4.2  
Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70  
Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71  
Carrier Generator Data Registers  
(CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . .72  
9.5  
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74  
Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76  
FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77  
Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .78  
9.5.1  
9.5.2  
9.5.3  
9.5.3.1  
9.5.3.2  
9.5.4  
End Of Cycle (EOC) Interrupt . . . . . . . . . . . . . . . . . . . . .79  
Modulator Control and Status Register . . . . . . . . . . . . . .80  
Modulator Period Data Registers  
(MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .83  
General Release Specification  
8
MC68HC05RC16 — Rev. 3.0  
Table of Contents  
MOTOROLA  
Table of Contents  
Se c tion 10. Instruc tion Se t  
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85  
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86  
10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86  
10.3.1  
10.3.2  
10.3.3  
10.3.4  
10.3.5  
10.3.6  
10.3.7  
10.3.8  
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87  
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87  
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87  
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87  
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88  
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88  
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88  
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89  
10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89  
10.4.1  
10.4.2  
10.4.3  
10.4.4  
10.4.5  
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .90  
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . . .91  
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .92  
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .94  
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95  
10.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96  
Se c tion 11. Ele c tric a l Sp e c ific a tions  
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103  
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103  
11.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104  
11.4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105  
11.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105  
11.6 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .106  
11.7 DC Electrical Characteristics (2.2 Vdc). . . . . . . . . . . . . . . . . .107  
11.8 Control Timing (5.0 Vdc and 2.2 V ) . . . . . . . . . . . . . . . . . . .109  
dc  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
9
Table of Contents  
Ta b le of Conte nts  
Se c tion 12. Me c ha nic a l Sp e c ific a tions  
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111  
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111  
12.3 28-Pin Plastic Dual In-Line Package  
(Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112  
12.4 28-Pin Small Outline Integrated Circuit Package  
(Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112  
12.5 44-Pin Plastic Leaded Chip Carrier Package  
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113  
Se c tion 13. Ord e ring Inform a tion  
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115  
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115  
13.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115  
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .116  
13.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .117  
13.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .118  
13.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118  
Ap p e nd ix A. MC68HC05RC8  
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119  
A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119  
A.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119  
General Release Specification  
10  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Table of Contents  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
List of Fig ure s  
Figure  
Title  
Page  
1-1  
1-2  
1-3  
1-4  
1-5  
MC68HC05RC16 Block Diagram. . . . . . . . . . . . . . . . . . . . .18  
28-Pin DIP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22  
44-Pin PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22  
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
2-1  
2-2  
MC68HC05RC16 Memory Map . . . . . . . . . . . . . . . . . . . . . .28  
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29  
3-1  
3-2  
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
4-1  
4-2  
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .40  
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .41  
5-1  
5-2  
5-3  
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46  
Reset and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . .47  
COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .51  
6-1  
6-2  
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .54  
Stop/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56  
7-1  
7-2  
Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60  
8-1  
8-2  
8-3  
Core Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .62  
Core Timer Control and Status Register (CTCSR) . . . . . . .63  
Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .65  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
List of Figures  
11  
List of Fig ure s  
Figure  
Title  
Page  
9-1  
9-2  
9-3  
9-4  
9-5  
9-6  
9-7  
9-8  
Carrier Modulator Transmitter Module Block Diagram. . . . .69  
Carrier Generator Block Diagram. . . . . . . . . . . . . . . . . . . . .70  
Carrier Generator Data Register CHR1 . . . . . . . . . . . . . . . .72  
Carrier Generator Data Register CLR1 . . . . . . . . . . . . . . . .72  
Carrier Generator Data Register CHR2 . . . . . . . . . . . . . . . .72  
Carrier Generator Data Register CLR2 . . . . . . . . . . . . . . . .73  
Modulator Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .75  
CMT Operation in Time Mode . . . . . . . . . . . . . . . . . . . . . . .77  
Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .79  
Modulator Control and Status Register (MCSR) . . . . . . . . .80  
Modulator Period Data Register MDR1 . . . . . . . . . . . . . . . .83  
Modulator Period Data Register MDR2 . . . . . . . . . . . . . . . .83  
Modulator Period Data Register MDR3 . . . . . . . . . . . . . . . .83  
9-9  
9-10  
9-11  
9-12  
9-13  
11-1  
A-1  
Maximum Supply Current versus Internal  
Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108  
MC68HC05RC8 Memory Map . . . . . . . . . . . . . . . . . . . . .120  
General Release Specification  
12  
MC68HC05RC16 — Rev. 3.0  
List of Figures  
MOTOROLA  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
List of Ta b le s  
Table  
4-1  
Title  
Page  
Vector Address for Interrupts and Reset ................................38  
COP Watchdog Timer Recommendations .............................50  
I/O Pin Functions....................................................................59  
RTI and COP Rates at 4.096 MHz Oscillator .........................64  
5-1  
7-1  
8-1  
10-1  
10-2  
10-3  
10-4  
10-5  
10-6  
10-7  
Register/Memory Instructions.................................................90  
Read-Modify-Write Instructions ..............................................91  
Jump and Branch Instructions................................................93  
Bit Manipulation Instructions...................................................94  
Control Instructions.................................................................95  
Instruction Set Summary ........................................................96  
Opcode Map.........................................................................102  
13-1  
MC Order Numbers ..............................................................118  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
List of Tables  
13  
List of Ta b le s  
General Release Specification  
14  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
List of Tables  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 1. Ge ne ra l De sc rip tion  
1.1 Conte nts  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
General Description  
15  
Ge ne ra l De sc rip tion  
1.2 Introd uc tion  
The MC68HC05RC16 is a low-cost addition to the M68HC05 Family of  
microcontrollers (MCUs) and is suitable for remote control applications.  
This device contains the HC05 central processing unit (CPU) core,  
including the 14-stage core timer with real-time interrupt (RTI) and  
computer operating properly (COP) watchdog systems. On-chip  
peripherals include a carrier modulator transmitter. The 16-kbyte  
memory map has 15,936 bytes of user ROM and 352 bytes of RAM.  
There are 20 input/output (I/O) lines (eight having keyscan  
pullups/interrupts) and a low-power reset pin. This device is available in  
28-pin small outline integrated circuit (SOIC), 28-pin dual in-line (DIP),  
and 44-pin plastic leaded chip carrier (PLCC) packages. Four additional  
I/O lines are available for bond out on the higher pin count package.  
1.3 Fe a ture s  
Features for the MC68HC05RC16 include:  
• Low Cost  
• HC05 Core  
Circuit (SOIC), or Plastic Leaded Chip Carrier (PLCC) Packages  
• On-Chip Oscillator with Crystal/Ceramic Resonator  
• 4-MHz Maximum Oscillator Frequency at 5 V and 2.2 V Supply  
• Fully Static Operation  
• 15,936 Bytes of User ROM  
• 64 Bytes of Burn-In ROM  
• 352 Bytes of On-Chip RAM  
• 14-Stage Core Timer with Real-Time Interrupt (RTI) and  
Computer Operating Properly (COP) Watchdog Circuits  
• Carrier Modulator Transmitter Supporting Baseband, Pulse  
Length Modulator (PLM), and Frequency Shift Keying (FSK)  
Protocols  
General Release Specification  
16  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
   
General Description  
Features  
• Low-Power Reset Pin  
• 20 Bidirectional I/O Lines (Four Additional I/O Lines Available for  
Bond Out in 44-Lead PLCC Package)  
• Mask Programmable Pullups and Interrupts on Eight Port Pins  
(PB0–PB7)  
• High-Current Infrared (IR) Drive Pin  
• High-Current Port Pin (PC0)  
• Power-Saving Stop and Wait Modes  
• Mask Selectable Options:  
– COP Watchdog Timer  
– STOP Instruction Disable  
– Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger  
– Port B Pullups for Keyscan  
• Illegal Address Reset  
• ROM Security Feature  
NOTE: A line over a signal name indicates an active low signal. For example,  
RESET is active low.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
17  
General Description  
Ge ne ra l De sc rip tion  
OSC2  
CARRIER  
MODULATOR  
TRANSMITTER  
OSCILLATOR  
OSC1  
IRO  
IRQEN  
÷ 2  
V
DD  
INTERNAL  
PROCESSOR  
CLOCK  
PC0  
PC1  
PC2  
PC3  
PC4*  
PC5*  
PC6*  
PC7*  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
PA7  
PB0  
PB1  
PB2  
PB3  
PB4  
PB5  
PB6  
PB7  
V
SS  
CORE TIMER  
SYSTEM  
COP  
SYSTEM  
RTI  
SYSTEM  
RESET  
LPRST  
CPU  
ALU  
CONTROL  
M68HC05 CPU  
CPU REGISTERS  
ACCUMULATOR  
IRQEN  
INDEX REGISTER  
STACK POINTER  
0
1
0
1
0
0
0
0
PROGRAM COUNTER  
CONDITION CODE REGISTER  
0
IRQ  
I
Z
N
H
C
1
1
1
SRAM — 352 BYTES  
ROM — 15,936 BYTES  
BURN-IN ROM — 64 BYTES  
* Marked pins are available only 44-lead PLCC package.  
Figure 1-1. MC68HC05RC16 Block Diagram  
General Release Specification  
18  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
General Description  
Mask Options  
1.4 Ma sk Op tions  
There are 11 total mask options on the MC68HC05RC16 including:  
• Eight port B pullups  
• IRQ sensitivity  
• COP enable/disable  
• STOP enable/disable  
These are nonprogrammable options in that they are selected at the time  
of code submission (when masks are made). These options are as  
follows:  
PB7PU — Port B7 Pullup/Interrupt  
This bit enables or disables the pullup/interrupt on port B, bit 7.  
1 = Enables the pullup/interrupt  
0 = Disables the pullup/interrupt  
PB6PU — Port B6 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 6.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
PB5PU — Port B5 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 5.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
PB4PU — Port B4 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 4.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
PB3PU — Port B3 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 3.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
19  
General Description  
 
Ge ne ra l De sc rip tion  
PB2PU — Port B2 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 2.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
PB1PU — Port B1 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 1.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
PB0PU — Port B0 Pullup/Interrupt  
This option enables or disables the pullup/interrupt on port B, bit 0.  
1 = Enables pullup/interrupt  
0 = Disables pullup/interrupt  
COPEN — COP Enable  
When the COP option is selected (COPEN = 1), the COP watchdog  
timer is enabled.  
When the COP option is deselected (COPEN = 0), the COP watchdog  
timer is disabled.  
STOPEN — STOP Instruction Enable  
When the STOP option is selected (STOPEN = 1), the STOP  
instruction is enabled.  
When the STOP option is deselected (STOPEN = 0), the STOP  
instruction is equivalent to a WAIT instruction.  
IRQ — IRQ sensitivity  
When the IRQ option is selected (IRQ = 1), edge- and level-sensitive  
IRQ is enabled.  
When the IRQ option is deselected (IRQ = 0), edge-only sensitive IRQ  
is enabled.  
NOTE: The port B keyscan interrupt sensitivity will match that of the IRQ  
sensitivity. (See 4.7 External Interrupt (IRQ/Port B Keyscan) for more  
information.)  
General Release Specification  
20  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
General Description  
Signal Description  
1.5 Sig na l De sc rip tion  
The MC68HC05RC16 is available in  
1. 28-pin dual-in-line package (DIP) see Figure 1-2  
2. 28-pin small outline integrated circuit (SOIC) package  
3. 44-pin plastic leaded chip carrier (PLCC) package see Figure 1-4  
The signals are described in the following subsections.  
PB0  
PB1  
1
2
28  
27  
OSC1  
OSC2  
PB2  
3
26  
V
DD  
PB3  
PB4  
PB5  
PB6  
PB7  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
4
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
IRQ  
5
RESET  
IRO  
6
7
V
SS  
8
LPRST  
PC3  
9
10  
11  
12  
13  
14  
PC2  
PC1  
PC0  
PA7  
PA6  
Figure 1-2. 28-Pin DIP Pinout  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
21  
General Description  
   
Ge ne ra l De sc rip tion  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
PB0  
PB1  
PB2  
PB3  
OSC1  
OSC2  
2
3
V
DD  
4
IRQ  
5
PB4  
PB5  
RESET  
IRO  
6
7
PB6  
PB7  
PA0  
PA1  
V
SS  
8
LPRST  
PC3  
PC2  
PC1  
PC0  
PA7  
9
10  
11  
12  
13  
14  
PA2  
PA3  
PA4  
PA5  
PA6  
Figure 1-3. 28-Pin SOIC Pinout  
NC  
PB4  
PB5  
PB6  
PB7  
NC  
NC  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
RESET  
IRO  
8
9
V
10  
11  
12  
13  
14  
15  
16  
17  
SS  
LPRST  
NC  
PC5  
PC6  
PC7  
PA0  
PA1  
NC  
PC4  
PC3  
PC2  
NC  
NOTE: NC = No Connect  
All no connects should be tied to an appropriate logic  
level (either V or V ).  
DD  
SS  
Figure 1-4. 44-Pin PLCC Pinout  
General Release Specification  
22  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
   
General Description  
Signal Description  
1.5.1 V a nd V  
DD  
SS  
Power is supplied to the microcontroller’s digital circuits using these two  
pins. V is the positive supply and V is ground.  
SS  
DD  
1.5.2 IRQ (Ma ska b le Inte rrup t Re q ue st)  
In addition to suppling the EPROM with the required programming  
voltage, this pin has a mask option as specified by the user that provides  
one of two different choices of interrupt triggering sensitivity. The options  
are:  
1. Negative edge-sensitive triggering only  
2. Both negative edge-sensitive and level-sensitive triggering.  
The MCU completes the current instruction before it responds to the  
interrupt request. When IRQ goes low for at least one t  
(see 11.8  
ILIH  
Control Timing (5.0 Vdc and 2.2 Vdc)), a logic 1 is latched internally to  
signify that an interrupt has been requested. When the MCU completes  
its current instruction, the interrupt latch is tested. If the interrupt latch  
contains a logic 1 and the interrupt mask bit (I bit) in the condition code  
register is clear, the MCU then begins the interrupt sequence.  
If the option is selected to include level-sensitive triggering, the IRQ input  
requires an external resistor to V for wired-OR operation.  
DD  
The IRQ pin contains an internal Schmitt trigger as part of its input to  
improve noise immunity.  
Refer to Section 4. Interrupts for more detail.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
23  
General Description  
   
Ge ne ra l De sc rip tion  
1.5.3 OSC1 a nd OSC2  
These pins provide control input for an on-chip clock oscillator circuit. A  
crystal, a ceramic resonator, or an external signal connects to these pins  
to provide a system clock. The oscillator frequency is two times the  
internal bus rate.  
Figure 1-5 shows the recommended circuit when using a crystal. The  
crystal and components should be mounted as close as possible to the  
input pins to minimize output distortion and startup stabilization time.  
A ceramic resonator may be used in place of the crystal in cost-sensitive  
applications. Figure 1-5 (a) shows the recommended circuit for using a  
ceramic resonator. The manufacturer of the particular ceramic resonator  
being considered should be consulted for specific information.  
An external clock should be applied to the OSC1 input with the OSC2 pin  
not connected (see Figure 1-5 (b)). This setup can be used if the user  
does not want to run the CPU with a crystal.  
MCU  
MCU  
OSC1  
OSC2  
OSC1  
OSC2  
10 MΩ  
UNCONNECTED  
<
EXTERNAL CLOCK  
30 pF  
30 pF  
(a) Crystal/Ceramic Resonator  
Oscillator Connections  
(b) External Clock Source  
Connections  
Figure 1-5. Oscillator Connections  
General Release Specification  
24  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
   
General Description  
Signal Description  
1.5.4 RESET  
1.5.5 LPRST  
1.5.6 IRO  
This active-low pin is used to reset the MCU to a known startup state by  
pulling RESET low. The RESET pin contains an internal Schmitt trigger  
as part of its input to improve noise immunity. See Section 5. Resets.  
The LPRST pin is an active-low pin and is used to put the MCU into  
low-power reset mode. In low-power reset mode the MCU is held in reset  
with all processor clocks halted. See Section 5. Resets.  
The IRO pin is the high-current source and sink output of the carrier  
modulator transmitter subsystem which is suitable for driving infrared  
(IR) LED biasing logic. See Section 9. Carrier Modulator Transmitter  
(CMT).  
1.5.7 PA0–PA7  
These eight I/O lines comprise port A. The state of any pin is software  
programmable and all port A lines are configured as inputs during  
power-on or reset. For detailed information on I/O programming, see 2.4  
Input/Output Programming.  
1.5.8 PB0–PB7  
These eight I/O lines comprise port B. The state of any pin is software  
programmable and all port B lines are configured as inputs during  
power-on or reset. Each port B I/O line has a mask optionable  
pullup/interrupt for keyscan. For detailed information on I/O  
programming, see 2.4 Input/Output Programming.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
25  
General Description  
         
Ge ne ra l De sc rip tion  
1.5.9 PC0–PC3 (PC4–PC7)  
These eight I/O lines comprise port C. PC0 is a high-current pin.  
PC4–PC7 are available only in the 44-lead PLCC package. The state of  
any pin is software programmable and all port C lines are configured as  
input during power-on or reset. For detailed information on I/O  
programming, see 2.4 Input/Output Programming.  
NOTE: Only four bits of port C are bonded out in 28-pin packages for the  
MC68HC05RC16, although port C is truly an 8-bit port. Since pins  
PC4–PC7 are unbonded, software should include the code to set their  
respective data direction register locations to outputs to avoid floating  
inputs.  
NOTE: Any unused inputs, I/O ports, and no connects should be tied to an  
appropriate logic level (either V or V ). Although the I/O ports of the  
DD  
SS  
do not require termination, termination is recommended to reduce the  
possibility of static damage.  
General Release Specification  
26  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Description  
 
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 2. Me m ory  
2.1 Conte nts  
2.2 Introd uc tion  
2.3 Me m ory Ma p  
This section describes the organization of the on-chip memory.  
The MC68HC05RC16 has a 16-Kbyte memory map consisting of user  
ROM, RAM, burn-in ROM, and input/output (I/O).  
Figure 2-1 shows the MC68HC05RC16 memory map in user mode.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Memory  
27  
   
Me m ory  
$0000  
0000  
PORT A DATA REGISTER  
PORT B DATA REGISTER  
PORT C DATA REGISTER  
RESERVED  
$00  
$01  
$02  
$03  
$04  
$05  
I/O  
32 BYTES  
$001F  
$0020  
0031  
0032  
RAM  
160 BYTES  
PORT A DATA DIRECTION REGISTER  
PORT B DATA DIRECTION REGISTER  
$00BF  
$00C0  
0191  
0192  
STACK  
64 BYTES  
PORT C DATA DIRECTION REGISTER $06  
RESERVED  
CORE TIMER CONTROL & STATUS REG. $08  
$00FF  
$0100  
0255  
0256  
$07  
RAM  
128 BYTES  
$017F  
$0180  
0383  
0384  
CORE TIMER COUNTER REGISTER  
RESERVED  
$09  
$0A  
USER ROM  
15,920 BYTES  
$0F  
RESERVED  
$3FAF  
$3FB0  
16303  
16304  
$10  
$11  
IR TIMER CHR1  
IR TIMER CLR1  
BURN-IN ROM  
& VECTORS  
64 BYTES  
IR TIMER CHR2  
IR TIMER CLR2  
IR TIMER MCSR  
$12  
$3FEF  
$3FF0  
16367  
16368  
$13  
$14  
USER VECTORS  
16 BYTES  
$15  
IR TIMER MDR1  
IR TIMER MDR2  
IR TIMER MDR3  
RESERVED  
$3FFF  
16383  
$16  
$17  
$18  
RESERVED  
RESERVED  
$1E  
$1F  
$3FF0  
UNUSED  
UNUSED  
$3FF5  
$3FF6  
CORE TIMER VECTOR (HIGH BYTE)  
CORE TIMER VECTOR (LOW BYTE)  
IR TIMER VECTOR (HIGH BYTE)  
$3FF7  
$3FF8  
IR TIMER VECTOR (LOW BYTE)  
$3FF9  
$3FFA  
IRQ/PTB KEYSCAN PULLUPS  
VECTOR (HIGH BYTE)  
IRQ/PTB KEYSCAN PULLUPS  
VECTOR (LOW BYTE)  
$3FFB  
SWI VECTOR (HIGH BYTE)  
SWI VECTOR (LOW BYTE)  
RESET VECTOR (HIGH BYTE)  
RESET VECTOR (LOW BYTE)  
$3FFC  
$3FFD  
$3FFE  
$3FFF  
Figure 2-1. MC68HC05RC16 Memory Map  
General Release Specification  
28  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Memory  
 
Memory  
Memory Map  
Addr.  
$0000  
$0001  
$0002  
$0003  
Register  
Bit 7  
6
5
4
3
2
1
Bit 0  
Port A Data Register  
Port B Data Register  
Port C Data Register  
Reserved  
R
R
R
R
R
R
R
R
$0004 Port A Data Direction Register  
$0005 Port B Data Direction Register  
$0006 Port C Data Direction Register  
$0007  
Reserved  
R
R
R
R
R
R
R
R
$0008 Timer Control and Status Reg. CTOF  
RTIF  
TOFE  
RTIE  
TOFC  
RTFC  
RT1  
RT0  
$0009  
$000A  
$000B  
$000C  
$000D  
$000E  
$000F  
$0010  
$0011  
$0012  
$0013  
$0014  
$0015  
$0016  
$0017  
$0018  
$0019  
Timer Counter Register  
Reserved  
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reserved  
Reserved  
R
R
R
R
R
R
R
Reserved  
R
R
R
R
R
R
R
Reserved  
R
R
R
R
R
R
R
Reserved  
R
R
R
R
R
R
R
IR Timer CHR1 IROLN  
IR Timer CLR1 IROLP  
0
PH5  
PL5  
SH5  
SL5  
PH4  
PL4  
SH4  
SL4  
PH3  
PL3  
SH3  
SL3  
BASE  
SB11  
MB3  
SB3  
R
PH2  
PL2  
SH2  
SL2  
MODE  
SB10  
MB2  
SB2  
R
PH1  
PL1  
SH1  
SL1  
PH0  
PL0  
SH0  
SL0  
0
IR Timer CHR2  
IR Timer CLR2  
0
0
0
0
IR Timer MCSR EOC  
IR Timer MDR1 MB11  
IR Timer MDR2 MB7  
IR Timer MDR3 SB7  
0
EIMSK EXMRK  
EOCIE MCGEN  
MB10  
MB6  
SB6  
R
MB9  
MB5  
SB5  
R
MB8  
MB4  
SB4  
R
SB9  
MB1  
SB1  
R
SB8  
MB0  
SB0  
R
Reserved  
Reserved  
R
R
R
R
R
R
R
R
R
R
= Reserved  
Figure 2-2. I/O Registers  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
29  
Memory  
Me m ory  
Addr.  
$001A  
$001B  
$001C  
$001D  
$001E  
$001F  
Register  
Bit 7  
R
6
R
R
R
R
R
R
5
R
R
R
R
R
R
4
R
R
R
R
R
R
3
R
R
R
R
R
R
2
R
R
R
R
R
R
1
R
R
R
R
R
R
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
R
R
R
R
R
R
R
R
R
R
R
R
= Reserved  
Figure 2-2. I/O Registers (Continued)  
2.3.1 ROM  
The user ROM consists of 15,920 bytes of ROM located from $0180 to  
$3FAF and 16 bytes of user vectors located from $3FF0 to $3FFF.  
The burn-in ROM is located from $3FB0 to $3FEF.  
Ten of the user vectors, $3FF6–$3FFF, are dedicated to reset and  
interrupt vectors. The six remaining locations — $3FF0, $3FF1, $3FF2,  
$3FF3, $3FF4, and $3FF5 — are general-purpose user ROM locations.  
2.3.2 ROM Se c urity  
Security has been incorporated into the MC68HC05RC16 to prevent  
external viewing of the ROM contents. This feature ensures that  
1
customer-developed software remains proprietary.  
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or  
copying the ROM difficult for unauthorized users.  
General Release Specification  
30  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Memory  
   
Memory  
Input/Output Programming  
2.3.3 RAM  
The user RAM consists of 352 bytes of a shared stack area. The RAM  
starts at address $0020 and ends at address $017F. The stack begins  
at address $00FF. The stack pointer can access 64 bytes of RAM in the  
range $00FF to $00C0.  
NOTE: Using the stack area for data storage or temporary work locations  
requires care to prevent it from being overwritten due to stacking from an  
interrupt or subroutine call.  
2.4 Inp ut/ Outp ut Prog ra m m ing  
In user mode, 20 lines (28-pin PDIP or 28-pin SOIC) or 24 lines (44-lead  
PLCC) are arranged as three 8-bit I/O ports. These ports are  
programmable as either inputs or outputs under software control of the  
data direction registers. For detailed information, refer to Section 7.  
Parallel Input/Output (I/O).  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
31  
Memory  
   
Me m ory  
General Release Specification  
32  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Memory  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 3. Ce ntra l Proc e ssor Unit  
3.1 Conte nts  
3.2 Introd uc tion  
This section describes the registers of the MC68HC05RC16 central  
processor unit (CPU). The MCU contains five registers as shown in  
Figure 3-1. The interrupt stacking order is shown in Figure 3-2.  
7
0
A
X
ACCUMULATOR  
7
0
0
0
INDEX REGISTER  
13  
PC  
PROGRAM COUNTER  
STACK POINTER  
13  
0
7
1
0
0
0
0
0
1
SP  
CCR  
H
I
N
Z
C
CONDITION CODE REGISTER  
Figure 3-1. Programming Model  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
33  
Central Processor Unit  
   
Ce ntra l Proc e ssor Unit  
7
0
CONDITION CODE REGISTER  
ACCUMULATOR  
INDEX REGISTER  
PCH  
STACK  
1
1
1
I
N
T
R
E
T
U
R
N
INCREASING  
MEMORY  
ADDRESSES  
E
R
R
U
P
T
DECREASING  
MEMORY  
ADDRESSES  
PCL  
UNSTACK  
NOTE:  
Since the stack pointer decrements during pushes, the PCL is stacked first,  
followed by PCH, etc. Pulling from the stack is in the reverse order.  
Figure 3-2. Stacking Order  
3.3 Ac c um ula tor  
The accumulator (A) is a general-purpose 8-bit register used to hold  
operands and results of arithmetic calculations or data manipulations.  
7
0
A
3.4 Ind e x Re g iste r  
The index register (X) is an 8-bit register used for the indexed  
addressing value to create an effective address. The index register also  
may be used as a temporary storage area.  
7
0
X
General Release Specification  
34  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Central Processor Unit  
     
Central Processor Unit  
Condition Code Register  
3.5 Cond ition Cod e Re g iste r  
The condition code register (CCR) is a 5-bit register in which four bits are  
used to indicate the results of the instruction just executed, and the fifth  
bit indicates whether interrupts are masked. These bits can be tested  
individually by a program, and specific actions can be taken as a result  
of their state. Each bit is explained in the following paragraphs.  
CCR  
H
I
N
Z
C
H — Half Carry  
This bit is set during ADD and ADC operations to indicate that a carry  
occurred between bits 3 and 4.  
I — Interrupt  
When this bit is set, timer and external interrupts are masked  
(disabled). If an interrupt occurs while this bit is set, the interrupt is  
latched and processed as soon as the interrupt bit is cleared.  
N — Negative  
When set, this bit indicates that the result of the last arithmetic, logical,  
or data manipulation was negative.  
Z — Zero  
When set, this bit indicates that the result of the last arithmetic, logical,  
or data manipulation was zero.  
C — Carry/Borrow  
When set, this bit indicates that a carry or borrow out of the arithmetic  
logical unit (ALU) occurred during the last arithmetic operation. This  
bit is also affected during bit test and branch instructions and during  
shifts and rotates.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
35  
Central Processor Unit  
 
Ce ntra l Proc e ssor Unit  
3.6 Sta c k Pointe r  
The stack pointer (SP) contains the address of the next free location on  
the stack. During an MCU reset or the reset stack pointer (RSP)  
instruction, the stack pointer is set to location $00FF. The stack pointer  
is then decremented as data is pushed onto the stack and incremented  
as data is pulled from the stack.  
When accessing memory, the seven most significant bits are  
permanently set to 0000011. These seven bits are appended to the six  
least significant register bits to produce an address within the range of  
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)  
locations. If 64 locations are exceeded, the stack pointer wraps around  
and loses the previously stored information. A subroutine call occupies  
two locations on the stack; an interrupt uses five locations.  
13  
7
0
0
0
0
0
0
1
1
SP  
3.7 Prog ra m Counte r  
The program counter (PC) is a 13-bit register that contains the address  
of the next byte to be fetched.  
13  
0
PC  
NOTE: The HC05 CPU core is capable of addressing a 64-Kbyte memory map.  
For this implementation, however, the addressing registers are limited to  
an 16-Kbyte memory map.  
General Release Specification  
36  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Central Processor Unit  
   
Inte rrup ts  
4.3 CPU Inte rrup t Proc e ssing  
Interrupts cause the processor to save register contents on the stack  
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike  
reset, hardware interrupts do not cause the current instruction execution  
to be halted, but are considered pending until the current instruction is  
complete.  
If interrupts are not masked (I bit in the CCR is clear) and the  
corresponding interrupt enable bit is set, the processor will proceed with  
interrupt processing. Otherwise, the next instruction is fetched and  
executed. If an interrupt occurs, the processor completes the current  
instruction, stacks the current CPU register state, sets the I bit to inhibit  
further interrupts, and finally checks the pending hardware interrupts. If  
more than one interrupt is pending after the stacking operation, the  
interrupt with the highest vector location shown in Table 4-1 will be  
serviced first. The SWI is executed the same as any other instruction,  
regardless of the I-bit state.  
When an interrupt is to be processed, the CPU fetches the address of  
the appropriate interrupt software service routine from the vector table at  
locations $3FF6–$3FFF as defined in Table 4-1.  
Table 4-1. Vector Address for Interrupts and Reset  
CPU  
Register Flag Name  
Interrupt  
Reset  
Vector Address  
Interrupt  
RESET  
SWI  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
$3FFE–$3FFF  
$3FFC–$3FFD  
$3FFA–$3FFB  
Software Interrupt  
External Interrupts*  
IRQ  
End of Cycle  
Interrupt  
MCSR  
EOC  
CMT  
$3FF8–$3FF9  
$3FF6–$3FF7  
Real-Time Interrupt  
Core Timer  
Overflow  
CTOF,  
RTIF  
CORE  
TIMER  
CTCSR  
*External interrupts include IRQ and port B keyscan sources.  
General Release Specification  
38  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Interrupts  
   
Interrupts  
Reset Interrupt Sequence  
The M68HC05 CPU does not support interruptible instructions. The  
maximum latency to the first instruction of the interrupt service routine  
must include the longest instruction execution time plus stacking  
overhead.  
Latency = (Longest instruction execution time + 10) x t seconds  
cyc  
An RTI instruction is used to signify when the interrupt software service  
routine is completed. The RTI instruction causes the register contents to  
be recovered from the stack and normal processing to resume at the  
next instruction that was to be executed when the interrupt took place.  
Figure 4-1 shows the sequence of events that occurs during interrupt  
processing.  
4.4 Re se t Inte rrup t Se q ue nc e  
The reset function is not in the strictest sense an interrupt; however, it is  
on the RESET pin or an internally generated RST signal causes the  
program to vector to its starting address, which is specified by the  
contents of memory locations $3FFE and $3FFF. The I bit in the  
condition code register is also set. The MCU is configured to a known  
state during this type of reset.  
4.5 Softwa re Inte rrup t (SWI)  
The SWI is an executable instruction and a nonmaskable interrupt since  
it is executed regardless of the state of the I bit in the CCR. If the I bit is  
zero (interrupts enabled), the SWI instruction executes after interrupts  
that were pending before the SWI was fetched or before interrupts  
generated after the SWI was fetched. The interrupt service routine  
address is specified by the contents of memory locations $3FFC and  
$3FFD.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
39  
Interrupts  
   
Inte rrup ts  
FROM  
RESET  
I BIT  
IN CCR  
SET?  
Y
N
IRQ/PORT B  
KEYSCAN  
CLEAR IRQ  
REQUEST  
LATCH.  
Y
Y
EIMSK  
CLEAR?  
EXTERNAL  
INTERRUPTS  
N
N
Y
INTERNAL  
CMT  
INTERRUPT  
N
Y
INTERNAL  
CORE TIMER  
INTERRUPT  
N
STACK  
PC, X, A, CCR.  
FETCH NEXT  
INSTRUCTION.  
SET I BIT IN  
CC REGISTER.  
LOAD PC FROM  
APPROPRIATE  
VECTOR.  
Y
SWI  
INSTRUCTION  
?
N
Y
RTI  
INSTRUCTION  
?
N
EXECUTE  
INSTRUCTION.  
RESTORE REGISTERS  
FROM STACK: CCR, A, X, PC.  
Figure 4-1. Interrupt Processing Flowchart  
General Release Specification  
40  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Interrupts  
 
Interrupts  
Hardware Interrupts  
4.6 Ha rd wa re Inte rrup ts  
All hardware interrupts except RESET are maskable by the I bit in the  
CCR. If the I bit is set, all hardware interrupts (internal and external) are  
disabled. Clearing the I bit enables the hardware interrupts. The three  
types of hardware interrupts are explained in the following sections.  
4.7 Exte rna l Inte rrup t (IRQ/ Port B Ke ysc a n)  
The IRQ pin provides an asynchronous interrupt to the CPU. A block  
diagram of the IRQ function is shown in Figure 4-2.  
NOTE: The BIH and BIL instructions will apply to the level on the IRQ pin itself  
and to the output of the logic OR function with the port B IRQ interrupts.  
The states of the individual port B pins can be checked by reading the  
appropriate port B pins as inputs.  
The IRQ pin is one source of an external interrupt. All port B pins  
(PB0–PB7) act as other external interrupt sources if the pullup feature is  
enabled as specified by the user.  
TO BIH & BIL  
INSTRUCTION  
SENSING  
V
DD  
EIMSK  
IRQ PIN  
IRQ  
PORT B KEYSCAN  
INTERRUPT  
LATCH  
TO IRQ  
PROCESSING  
IN CPU  
IRQ VECTOR FETCH  
R
RST  
LEVEL  
(MASK OPTION)  
Figure 4-2. IRQ Function Block Diagram  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
41  
Interrupts  
     
Inte rrup ts  
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to  
these cases:  
1. Falling edge on the IRQ pin  
2. Falling edge on any port B pin with pullup enabled  
When edge and level sensitivity is selected for the IRQ interrupt, it is  
sensitive to these cases:  
1. Low level on the IRQ pin  
2. Falling edge on the IRQ pin  
3. Falling edge or low level on any port B pin with pullup enabled  
External interrupts also can be masked by setting the EIMSK bit in the  
MSCR register of the IR remote timer. See 9.5.4 Modulator Period  
Data Registers (MDR1, MDR2, and MDR3) for details.  
4.8 Exte rna l Inte rrup t Tim ing  
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts  
(internal and external) are disabled. Clearing the I bit enables interrupts.  
The interrupt request is latched immediately following the falling edge of  
the IRQ source. It is then synchronized internally and serviced as  
specified by the contents of $3FFA and $3FFB.  
Either a level-sensitive and edge-sensitive trigger or an  
edge-sensitive-only trigger is available via the mask programmable  
option for the IRQ pin.  
4.9 Ca rrie r Mod ula tor Tra nsm itte r Inte rrup t (CMT)  
A CMT interrupt occurs when the end of cycle flag (EOC) and the end of  
cycle interrupt enable (EOCIE) bits are set in the modulator control and  
status register (MCSR). This interrupt will vector to the interrupt service  
routine located at the address specified by the contents of memory  
locations $3FF8 and $3FF9.  
General Release Specification  
42  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Interrupts  
   
Interrupts  
Core Timer Interrupt  
4.10 Core Tim e r Inte rrup t  
This timer can create two types of interrupts. A timer overflow interrupt  
occurs whenever the 8-bit timer rolls over from $FF to $00 and the  
enable bit TOFE is set. A real-time interrupt occurs whenever the  
programmed time elapses and the enable bit RTIE is set. Either of these  
interrupts vectors to the same interrupt service routine, located at the  
address specified by the contents of memory locations $3FF6 and  
$3FF7.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
43  
Interrupts  
 
Inte rrup ts  
General Release Specification  
44  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Interrupts  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 5. Re se ts  
5.1 Conte nts  
5.2 Introd uc tion  
The MCU can be reset from five sources: two external inputs and three  
internal restart conditions. The RESET and LPRST pins are inputs as  
shown in Figure 5-1. All the internal peripheral modules will be reset by  
the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Resets  
45  
 
Re se ts  
5.3 Exte rna l Re se t (RESET)  
The RESET pin is one of the two external sources of a reset. This pin is  
connected to a Schmitt trigger input gate to provide an upper and lower  
threshold voltage separated by a minimum amount of hysteresis. This  
external reset occurs whenever the RESET pin is pulled below the lower  
threshold and remains in reset until the RESET pin rises above the  
upper threshold. This active-low input will generate the RST signal and  
reset the CPU and peripherals. Termination of the external RESET input  
or the internal COP watchdog reset are the only reset sources that can  
alter the operating mode of the MCU.  
NOTE: Activation of the RST signal is generally referred to as reset of the  
device, unless otherwise specified.  
TO IRQ  
LOGIC  
IRQ  
D
MODE  
LATCH  
SELECT  
RESET  
R
CLOCKED  
OSC  
DATA  
ADDRESS  
COP WATCHDOG  
(COPR)  
CPU  
LPRST  
S
D
TO OTHER  
PERIPHERALS  
POWER-ON RESET  
LATCH  
V
DD  
(POR)  
RST  
PH2  
ILLEGAL ADDRESS  
(ILLADDR)  
ADDRESS  
Figure 5-1. Reset Block Diagram  
General Release Specification  
46  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Resets  
   
V
DD  
0 V  
> V  
4
POR  
2
OSC1  
4064 t  
CYC  
t
CYC  
INTERNAL  
PROCESSOR  
1
CLOCK  
INTERNAL  
ADDRESS  
3FFE  
3FFF  
NEW PC NEW PC  
3FFE  
3FFE  
3FFE  
3FFE  
PCH  
3FFF  
PCL  
NEW PC NEW PC  
1
BUS  
INTERNAL  
DATA  
NEW  
PCH  
NEW  
PCL  
OP  
CODE  
OP  
CODE  
1
BUS  
t
RL  
5
3
RESET  
NOTES:  
1. Internal timing signal and bus information are not available externally.  
2. OSC1 line is not meant to represent frequency. It is only used to represent time.  
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.  
4. V must fall to a level lower than V to be recognized as a power-on reset.  
DD  
POR  
5. The LPRST pin resets the CPU like RESET. However, 4064 POR cycles are executed first, before the reset vector address appears on the  
internal address bus. (See 5.4 Low-Power External Reset (LPRST).)  
Figure 5-2. Reset and POR Timing Diagram  
Re se ts  
5.4 Low-Powe r Exte rna l Re se t (LPRST)  
The LPRST pin is one of the two external sources of a reset. This  
external reset occurs whenever the LPRST pin is pulled below the lower  
threshold and remains in reset until the LPRST pin rises. This active low  
input will, in addition to generating the RST signal and resetting the CPU  
and peripherals, halt all internal processor clocks. The MCU will remain  
in this low-power reset condition as long as a logic 0 remains on LPRST.  
When a logic 1 is applied to LPRST, processor clocks will be re-enabled  
with the MCU remaining in reset until the 4064 internal processor clock  
cycle (t ) oscillator stabilization delay is completed. If any other reset  
cyc  
function is active at the end of this 4064-cycle delay, the RST signal  
remains in the reset condition until the other reset condition(s) end.  
5.5 Inte rna l Re se ts  
The three internally generated resets are the initial power-on reset  
function, the COP watchdog timer reset, and the illegal address detector.  
Termination of the external reset input, external LPRST input, or the  
internal COP watchdog timer are the only reset sources that can alter the  
operating mode of the MCU. The other internal resets do not have any  
effect on the mode of operation when their reset state ends.  
5.5.1 Powe r-On Re se t (POR)  
The internal POR is generated on power-up to allow the clock oscillator  
to stabilize. The POR is strictly for power turn-on conditions and is not  
able to detect a drop in the power supply voltage (brown-out). There is  
an oscillator stabilization delay of 4064 internal processor bus clock  
cycles (PH2) after the oscillator becomes active.  
The POR generates the RST signal that resets the CPU. If any other  
reset function is active at the end of this 4064-cycle delay, the RST  
signal remains in the reset condition until the other reset condition(s)  
ends.  
General Release Specification  
48  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Resets  
     
Resets  
Internal Resets  
5.5.2 Com p ute r Op e ra ting Prop e rly Re se t (COPR)  
The MCU contains a watchdog timer that automatically times out if not  
reset (cleared) within a specific time by a program reset sequence. If the  
COP watchdog timer is allowed to time out, an internal reset is  
generated to reset the MCU.  
The COP reset function is enabled or disabled by a mask option and is  
verified during production testing.  
5.5.2.1 Re se tting the COP  
Writing a zero to the COPF bit prevents a COP reset. This action resets  
the counter and begins the time-out period again. The COPF bit is bit 0  
of address $3FF0. A read of address $3FF0 returns user data  
programmed at that location.  
5.5.2.2 COP During Wa it Mo d e  
The COP continues to operate normally during wait mode. The software  
should pull the device out of wait mode periodically and reset the COP  
by writing to the COPF bit to prevent a COP reset.  
5.5.2.3 COP During Sto p Mo d e  
When the stop enable mask option is selected, stop mode disables the  
oscillator circuit and thereby turns the clock off for the entire device.  
When stop is executed, the COP counter will hold its current state. If a  
reset is used to exit stop mode, the COP counter is reset and held until  
4064 POR cycles are completed at this time, counting will begin. If an  
external IRQ is used to exit stop mode, the COP counter does not wait  
for the completion of the 4064 POR cycles but does count these cycles.  
It is, therefore, recommended that the COP is fed before executing the  
STOP instruction.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
49  
Resets  
       
Re se ts  
5.5.2.4 COP Wa tc hd o g Tim e r Co nsid e ra tio ns  
The COP watchdog timer is active in all modes of operation if enabled  
by a mask option. If the COP watchdog timer is selected by a mask  
option, any execution of the STOP instruction (either intentionally or  
inadvertently due to the CPU being disturbed) causes the oscillator to  
halt and prevents the COP watchdog timer from timing out. If the COP  
watchdog timer is selected by a mask option, the COP resets the MCU  
when it times out. Therefore, it is recommended that the COP watchdog  
be disabled for a system that must have intentional uses of the wait  
mode for periods longer than the COP time out period.  
The recommended interactions and considerations for the COP  
watchdog timer, STOP instruction, and WAIT instruction are  
summarized in Table 5-1.  
Table 5-1. COP Watchdog Timer Recommendations  
IF the Following Conditions Exist:  
THEN the COP Watchdog Timer  
Should Be as Follows:  
Wait Time  
Wait Time Less than COP Time-Out  
Wait Time More than COP Time-Out  
Any Length Wait Time  
Enable or Disable COP by Mask Option  
Disable COP by Mask Option  
Disable COP by Mask Option  
General Release Specification  
50  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Resets  
   
Resets  
Internal Resets  
5.5.2.5 COP Re g iste r  
The COP register is shared with the LSB of an unimplemented user  
interrupt vector as shown in Figure 5-3. Reading this location returns  
whatever user data has been programmed at this location. Writing a zero  
to the COPR bit in this location clears the COP watchdog timer.  
Address: $3FF0  
BIt 7  
X
6
5
4
3
2
1
Bit 0  
X
Read:  
Write:  
Reset:  
X
X
X
X
X
X
COPR  
0
= Unimplemented  
Figure 5-3. COP Watchdog Timer Location  
5.5.3 Ille g a l Ad d re ss  
An illegal address reset is generated when the CPU attempts to fetch an  
instruction from I/O address space ($0000 to $001F).  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
51  
Resets  
     
Re se ts  
General Release Specification  
52  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Resets  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 6. Low-Powe r Mod e s  
6.1 Conte nts  
6.2 Introd uc tion  
6.3 Stop Mod e  
This section describes the low-power modes.  
The STOP instruction places the MCU in its lowest power-consumption  
mode. In stop mode, the internal oscillator is turned off, halting all  
internal processing, including timer operation.  
During stop mode, the CTCSR ($08) bits are altered to remove any  
pending timer interrupt request and to disable any further timer  
interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared  
to enable external interrupts. All other registers and memory remain  
unaltered. All input/output lines remain unchanged.  
NOTE: The EIMSK bit is not cleared automatically by the execution of a STOP  
instruction. Care should be taken to clear this bit before entering stop  
mode.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
53  
Low-Power Modes  
   
Low-Powe r Mod e s  
1
OSC1  
t
t
RL  
RESET  
LIH  
2
IRQ  
t
4064 t  
CYC  
ILCH  
3
IRQ  
INTERNAL  
CLOCK  
INTERNAL  
ADDRESS  
BUS  
3FFE  
3FFE  
3FFE  
3FFE  
3FFF  
NOTES:  
RESET OR INTERRUPT  
VECTOR FETCH  
1. Represents the internal gating of the OSC1 pin  
2. IRQ pin edge-sensitive mask option  
3. IRQ pin level and edge-sensitive mask option  
Figure 6-1. Stop Recovery Timing Diagram  
6.4 Stop Re c ove ry  
The processor can be brought out of stop mode only by an external  
interrupt, LPRST, or RESET. Refer to Figure 6-1.  
NOTE: If an external interrupt is pending when stop mode is entered, then stop  
mode will be exited immediately.  
6.5 Wa it Mod e  
The WAIT instruction places the MCU in a low power-consumption  
mode, but wait mode consumes more power than stop mode. All CPU  
action is suspended, but the core timer, the oscillator, and any enabled  
module remain active. Any interrupt or reset will cause the MCU to exit  
wait mode. The user must shut off subsystems to reduce power  
General Release Specification  
54  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Low-Power Modes  
     
Low-Power Modes  
Low-Power Reset  
consumption. Wait current specifications assume CPU operation only  
and do not include current consumption by any other subsystems.  
During wait mode, the I bit in the CCR is cleared to enable interrupts. All  
other registers, memory, and input/output lines remain in their previous  
states. The timer may be enabled to allow a periodic exit from wait mode.  
6.6 Low-Powe r Re se t  
Low-power reset mode is entered when a logic 0 is detected on the  
LPRST pin. When in this mode (as long as LPRST is held low), the MCU  
is held in reset and all internal clocks are halted. Applying a logic 1 to  
LPRST will cause the part to exit low-power reset mode and begin  
counting out the 4064-cycle oscillator stabilization period. Once this time  
has elapsed, the MCU will begin operation from the reset vectors  
($3FFE–$3FFF).  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
55  
Low-Power Modes  
 
Low-Powe r Mod e s  
WAIT  
STOP  
OSCILLATOR ACTIVE.  
STOP OSCILLATOR  
AND ALL CLOCKS.  
IR TIMER CLOCK ACTIVE.  
CORE TIMER CLOCK ACTIVE.  
PROCESSOR CLOCKS  
STOPPED.  
CLEAR I BIT.  
RESET  
OR  
LPRST  
RESET  
OR  
LPRST  
N
N
Y
EXTERNAL  
INTERRUPT  
EXTERNAL  
INTERRUPT  
Y
N
(PTB KEYSCAN PULLUPS)  
(IRQ)  
(PTB KEYSCAN PULLUPS)  
N
(IRQ)  
Y
Y
IR TIMER  
N
INTERNAL  
INTERRUPT  
Y
TURN ON OSCILLATOR.  
WAIT FOR TIME  
DELAY TO STABILIZE.  
RESTART  
PROCESSOR CLOCK.  
CORE TIMER  
INTERNAL  
INTERRUPT  
N
Y
1. FETCH RESET  
VECTOR OR  
2. SERVICE  
INTERRUPT  
A. STACK  
1. FETCH RESET  
VECTOR OR  
2. SERVICE  
INTERRUPT  
A. STACK  
B. SET I BIT  
C. VECTOR TO  
INTERRUPT  
ROUTINE  
B. SET I BIT  
C. VECTOR TO  
INTERRUPT  
ROUTINE  
Figure 6-2. Stop/Wait Flowchart  
General Release Specification  
56  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Low-Power Modes  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 7. Pa ra lle l Inp ut/ Outp ut (I/ O)  
7.1 Conte nts  
7.2 Introd uc tion  
In user mode, 20 lines (in 28-pin PDIP or SOIC) or 24 lines (in 44-lead  
PLCC) are arranged as three 8-bit I/O ports. These ports are  
programmable as either inputs or outputs under software control of the  
data direction registers.  
NOTE: To avoid a glitch on the output pins, write data to the I/O port data  
register before writing a one to the corresponding data direction register.  
7.3 Port A  
Port A is an 8-bit bidirectional port which does not share any of its pins  
with other subsystems. The port A data register is at $0000 and the data  
direction register (DDR) is at $0004. Reset does not affect the data  
register, but clears the data direction register, thereby returning the ports  
to inputs. Writing a one to a DDR bit sets the corresponding port bit to  
output mode.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
57  
Parallel Input/Output (I/O)  
   
Pa ra lle l Inp ut/ Outp ut (I/ O)  
7.4 Port B  
Port B is an 8-bit bidirectional port which does not share any of its pins  
with other subsystems. The address of the port B data register is $0001  
and the data direction register (DDR) is at address $0005. Reset does  
not affect the data register, but clears the data direction register, thereby  
returning the ports to inputs. Writing a one to a DDR bit sets the  
corresponding port bit to output mode. Each of the port B pins has a  
mask programmable pullup device that can be enabled. When the pullup  
device is enabled, this pin will become an interrupt pin also. The edge or  
edge and level sensitivity of the IRQ pin also will pertain to the enabled  
port B pins. Care needs to be taken when using port B pins that have the  
pullup enabled. Before switching from an output to an input, the data  
should be preconditioned to a logic one or the I bit should be set in the  
condition code register to prevent an interrupt from occurring. The  
EIMSK bit in the CMT MCSR register can be used to mask port B  
keyscan and external interrupts (IRQ).  
NOTE: When a port B pin is configured as an output, it’s corresponding keyscan  
interrupt is disabled, regardless of it’s mask option.  
V
V
DD  
DD  
DISABLED  
MASK OPTION (PB7PU)  
DDR BIT  
ENABLED  
PB7  
IRQEN  
TO INTERRUPT  
LOGIC  
NORMAL PORT CIRCUITRY  
AS SHOWN IN FIGURE 7-2  
IRQ  
FROM ALL OTHER PORT B PINS  
Figure 7-1. Port B Pullup Option  
7.5 Port C  
Port C is an 8-bit bidirectional port (PC0–PC7) which does not share any  
of its pins with other subsystems. The port C data register is at $0003  
and the data direction register (DDR) is at $0006. Reset does not affect  
the data register, but clears the data direction register, thereby returning  
General Release Specification  
58  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Parallel Input/Output (I/O)  
   
Parallel Input/Output (I/O)  
Input/Output Programming  
the ports to inputs. Writing a one to a DDR bit sets the corresponding  
port bit to output mode. Port C pins PC4–PC7 are available only with the  
44-lead PLCC package.  
NOTE: Only four bits of port C are bonded out in 28-pin packages for the  
MC68HC05RC16, although port C is truly an 8-bit port. Since pins  
PC4–PC7 are unbonded, software should include the code to set their  
respective data direction register locations to outputs to avoid floating  
inputs.  
7.6 Inp ut/ Outp ut Prog ra m m ing  
Port pins may be programmed as inputs or outputs under software  
control. The direction of the pins is determined by the state of the  
corresponding bit in the port data direction register (DDR). Each I/O port  
has an associated DDR. Any I/O port pin is configured as an output if its  
corresponding DDR bit is set to a logic 1. A pin is configured as an input  
if its corresponding DDR bit is cleared to a logic 0.  
At power-on or reset, all DDRs are cleared, which configures all pins as  
inputs. The data direction registers are capable of being written to or  
read by the processor. During the programmed output state, a read of  
the data register actually reads the value of the output data latch and not  
the I/O pin.  
Table 7-1. I/O Pin Functions  
Access  
DDR  
I/O Pin Functions  
The I/O pin is in input mode. Data is written into the output  
data latch.  
Write  
0
Data is written into the output data latch and output to the  
I/O pin.  
Write  
1
Read  
Read  
0
1
The state of the I/O pin is read.  
The I/O pin is in an output mode. The output data latch is read.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Parallel Input/Output (I/O)  
59  
 
Pa ra lle l Inp ut/ Outp ut (I/ O)  
DATA DIRECTION  
REGISTER BIT  
INTERNAL  
HC05  
LATCHED  
OUTPUT  
DATA BIT  
I/O  
OUTPUT  
PIN  
CONNECTIONS  
INPUT  
REG  
BIT  
INPUT  
I/O  
Figure 7-2. I/O Circuitry  
General Release Specification  
60  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Parallel Input/Output (I/O)  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 8. Core Tim e r  
8.1 Conte nts  
8.2 Introd uc tion  
The core timer for this device is a 14-stage multifunctional ripple counter.  
Features include timer overflow, power-on reset (POR), real-time  
interrupt (RTI), and COP watchdog timer.  
As seen in Figure 8-1, the internal peripheral clock is divided by four,  
and then drives an 8-bit ripple counter. The value of this 8-bit ripple  
counter can be read by the CPU at any time by accessing the core timer  
counter register (CTCR) at address $09. A timer overflow function is  
implemented on the last stage of this counter, giving a possible interrupt  
rate of the internal peripheral clock (E)/1024. This point is then followed  
by three more stages, with the resulting clock (E/4096) driving the  
real-time interrupt circuit (RTI). The RTI circuit consists of three divider  
stages with a one-of-four selector. The output of the RTI circuit is further  
divided by eight to drive the mask optional COP watchdog timer circuit.  
The RTI rate selector bits and the RTI and CTOF enable bits and flags  
are located in the timer control and status register at location $08.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Core Timer  
61  
 
Core Tim e r  
INTERNAL BUS  
COP  
CLEAR  
INTERNAL PERIPHERAL CLOCK (E)  
8
8
CTCR  
2
E ÷ 2  
$09 CORE TIMER COUNTER REGISTER (CTCR)  
12  
10  
E ÷ 2  
E ÷ 2  
÷ 4  
POR  
5-BIT COUNTER  
TCBP  
15  
E ÷ 2  
14  
E ÷ 2  
13  
E ÷ 2  
12  
E ÷ 2  
RTI SELECT CIRCUIT  
OVERFLOW  
DETECT  
CIRCUIT  
RTI  
OUT  
CTCSR  
TIMER CONTROL &  
STATUS REGISTER  
CTOF RTIF TOFE RTIE TOFC RTFC  
RT1  
RT0  
$08  
COP WATCHDOG  
TIMER (÷8)  
INTERRUPT CIRCUIT  
3
2
TO INTERRUPT  
LOGIC  
TO RESET  
LOGIC  
Figure 8-1. Core Timer Block Diagram  
General Release Specification  
62  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Core Timer  
 
Core Timer  
Core Timer Control and Status Register  
8.3 Core Tim e r Control a nd Sta tus Re g iste r  
The CTCSR contains the timer interrupt flag, the timer interrupt enable  
bits, and the real-time interrupt rate select bits. Figure 8-2 shows the  
value of each bit in the CTCSR when coming out of reset.  
Address:  
$08  
Read: CTOF  
Write:  
RTIF  
0
0
TOFC  
0
0
RTFC  
0
TOFE  
0
RTIE  
0
RT1  
1
RT0  
1
Reset:  
0
= Unimplemented  
Figure 8-2. Core Timer Control and Status Register (CTCSR)  
CTOF — Core Timer Overflow  
CTOF is a read-only status bit set when the 8-bit ripple counter rolls  
over from $FF to $00. Clearing the CTOF is done by writing a one to  
TOFC. Writing to this bit has no effect. Reset clears CTOF.  
RTIF — Real-Time Interrupt Flag  
The real-time interrupt circuit consists of a 3-stage divider and a  
one-of-four selector. The clock frequency that drives the RTI circuit is  
12  
E/2 (or E ÷ 4096 with three additional divider stages giving a  
maximum interrupt period of 16 milliseconds at a bus rate of 2.024  
MHz. RTIF is a clearable, read-only status bit and is set when the  
output of the chosen (one-of-four selection) stage goes active.  
Clearing the RTIF is done by writing a one to RTFC. Writing has no  
effect on this bit. Reset clears RTIF.  
TOFE — Timer Overflow Enable  
When this bit is set, a CPU interrupt request is generated when the  
CTOF bit is set. Reset clears this bit.  
RTIE — Real-Time Interrupt Enable  
When this bit is set, a CPU interrupt request is generated when the  
RTIF bit is set. Reset clears this bit.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
63  
Core Timer  
   
Core Tim e r  
TOFC — Timer Overflow Flag Clear  
When a one is written to this bit, CTOF is cleared. Writing a zero has  
no effect on the CTOF bit. This bit always reads as zero.  
RTFC — Real-Time Interrupt Flag Clear  
When a one is written to this bit, RTIF is cleared. Writing a zero has  
no effect on the RTIF bit. This bit always reads as zero.  
RT1–RT0 — Real-Time Interrupt Rate Select  
These two bits select one of four taps from the real-time interrupt  
circuit. Refer to Table 8-1. Reset sets these two bits which selects the  
lowest periodic rate and gives the maximum time in which to alter  
these bits if necessary. Care should be taken when altering RT0 and  
RT1 if the timeout period is imminent or uncertain. If the selected tap  
is modified during a cycle in which the counter is switching, an RTIF  
could be missed or an additional one could be generated. To avoid  
problems, the COP should be cleared before changing RTI taps.  
Table 8-1. RTI and COP Rates at 4.096 MHz Oscillator  
RTI RATE  
2.048-MHz Bus  
MINIMUM COP RATES  
2.048-MHz Bus  
RT1:RT0  
12  
15 12  
14 ms  
2 ms  
00  
01  
10  
11  
2
2
2
2
÷ E  
÷ E  
÷ E  
÷ E  
(2 –2 )/E  
13  
14  
15  
16 13  
28 ms  
4 ms  
8 ms  
(2 –2 )/E  
17 14  
56 ms  
(2 –2 )/E  
18 15  
16 ms  
112 ms  
(2 –2 )/E  
General Release Specification  
64  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Core Timer  
 
Core Timer  
Core Timer Counter Register  
8.4 Core Tim e r Counte r Re g iste r  
The timer counter register is a read-only register that contains the  
current value of the 8-bit ripple counter at the beginning of the timer  
chain. This counter is clocked by the CPU clock (E/4) and can be used  
for various functions, including a software input capture. Extended time  
periods can be attained using the TOF function to increment a temporary  
RAM storage location, thereby simulating a 16-bit (or more) counter.  
Address:  
Read:  
$09  
D7  
D6  
0
D5  
0
D4  
0
D3  
0
D2  
0
D1  
1
D0  
1
Write:  
Reset:  
0
= Unimplemented  
Figure 8-3. Core Timer Counter Register (CTCR)  
The power-on cycle clears the entire counter chain and begins clocking  
the counter. After 4064 cycles, the power-on reset circuit is released,  
which again clears the counter chain and allows the device to come out  
of reset. At this point, if RESET is not asserted, the timer starts counting  
up from zero and normal device operation begins. When RESET is  
asserted any time during operation (other than POR and low-power  
reset), the counter chain is cleared.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
65  
Core Timer  
 
Core Tim e r  
8.5 Com p ute r Op e ra ting Prop e rly (COP) Re se t  
The COP watchdog timer function is implemented on this device by  
using the output of the RTI circuit and further dividing it by eight. The  
out, an internal reset is generated and the normal reset vector is fetched.  
Preventing a COP timeout, or clearing the COP is accomplished by  
writing a zero to bit 0 of address $3FF0. When the COP is cleared, only  
the final divide-by-eight stage (output of the RTI) is cleared.  
If the COP watchdog timer is allowed to time out, an internal reset is  
generated to reset the MCU.  
The COP remains enabled after execution of the WAIT instruction and  
all associated operations apply. If the STOP instruction is disabled,  
execution of STOP instruction causes the CPU to execute a WAIT  
instruction. In addition, the COP is prohibited from being held in reset.  
This prevents a device lock-up condition.  
This COP’s objective is to make it impossible for this device to become  
stuck or locked-up and to be sure the COP is able to rescue the part from  
any situation where it might entrap itself in abnormal or unintended  
behavior. This function is a mask option.  
8.6 Tim e r During Wa it Mod e  
The CPU clock halts during wait mode, but the timer remains active. If  
interrupts are enabled, a timer interrupt will cause the processor to exit  
wait mode. The COP is always enabled while in user mode.  
General Release Specification  
66  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Core Timer  
   
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 9. Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
9.1 Conte nts  
9.4.2  
Carrier Generator Data Registers (CHR1, CLR1,  
Modulator Period Data Registers  
9.5.4  
(MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .83  
9.2 Introd uc tion  
The carrier modulator transmitter (CMT) module provides a means to  
generate the protocol timing and carrier signals for a wide variety of  
encoding schemes. It incorporates hardware to off-load the critical  
and/or lengthy timing requirements associated with code generation  
from the CPU, releasing much of its bandwidth to handle other tasks  
such as code data generation, data decompression, or keyboard  
scanning. The CMT does not include dedicated hardware configurations  
for specific protocols, but is intended to be sufficiently programmable in  
its function to handle the timing requirements of most protocols with  
minimal CPU intervention. When disabled, certain CMT registers can be  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Carrier Modulator Transmitter (CMT)  
67  
 
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
used to change the state of the infrared out pin (IRO) directly. This  
feature allows for the generation of future protocols not readily  
producible by the current architecture.  
9.3 Ove rvie w  
The module consists of carrier generator, modulator, and transmitter  
output blocks. The block diagram is shown in Figure 9-1.  
The carrier generator has a resolution of 500 ns with a 2-MHz oscillator.  
The user may independently define the high and low times of the carrier  
signal to determine both period and duty cycle. The carrier generator can  
generate signals with periods between 1 µs (1 MHz) and 64 µs (15.6  
kHz) in steps of 500 ns. The possible duty cycle options will depend  
upon the number of counts required to complete the carrier period. For  
example, a 400-kHz signal has a period of 2.5 µs and will therefore  
require 5 x 500 ns counts to generate. These counts may be split  
between high and low times so the duty cycles available will be 20% (one  
high, four low), 40% (two high, three low), 60% (three high, two low) and  
80% (four high, one low). For lower frequency signals with larger  
periods, higher resolution (as a percentage of the total period) duty  
cycles are possible. The carrier generator may select between two sets  
of high and low times. When operating in normal mode (subsequently  
referred to as time mode), just one set will be used. When operating in  
FSK (frequency shift key) mode, the generator will toggle between the  
two sets when instructed to do so by the modulator, allowing the user to  
dynamically switch between two carrier frequencies without CPU  
intervention. When the BASE bit in the modulator control and status  
register (MCSR) is set, the carrier output to the modulator is held high  
continuously to allow for the generation of baseband protocols. See 9.4  
General Release Specification  
68  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
 
Carrier Modulator Transmitter (CMT)  
Overview  
PRIMARY/SECONDARY SELECT  
MODE  
BASE  
MODULATOR  
CARRIER  
OUT  
OUT  
IRO  
PIN  
TRANSMITTER  
OUTPUT  
CARRIER  
GENERATOR  
MODULATOR  
f
.
OSC  
MODULATOR/  
CARRIER  
ENABLE  
CPU INTERFACE  
EOC INTERRUPT  
f
÷ 2  
OSC  
DB  
AB  
Figure 9-1. Carrier Modulator Transmitter Module Block Diagram  
The modulator provides a simple method to control protocol timing. The  
modulator has a resolution of 4 µs with a 2-MHz oscillator. It can count  
system clocks to provide real-time control or it can count carrier clocks  
for self-clocked protocols. It can either gate the carrier onto the  
modulator output (TIME), control the logic level of the modulator output  
(baseband) or directly route the carrier to the modulator output while  
providing a signal to switch the carrier generator between high/low time  
register buffers (FSK). See 9.5 Modulator.  
The transmitter output block controls the state of the infrared out pin  
(IRO). The modulator output is gated on to the IRO pin when the  
modulator/carrier generator is enabled. Otherwise, the IRO pin is  
controlled by the state of the IRO latch, which is directly accessible to the  
CPU by means of bit 7 of the carrier generator data registers CHR1 and  
CLR1. The IRO latch can be written to on either edge of the internal bus  
clock (f /2), allowing for IR waveforms which have a resolution of twice  
osc  
the bus clock frequency (f ). See 9.4.2 Carrier Generator Data  
osc  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
69  
Carrier Modulator Transmitter (CMT)  
 
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
9.4 Ca rrie r Ge ne ra tor  
The carrier signal is generated by counting a predetermined number of  
input clocks (500 ns for a 2-MHz oscillator) for both the carrier high time  
and the carrier low time. The period is determined by the total number of  
clocks counted. The duty cycle is determined by the ratio of high time  
clocks to total clocks counted. The high and low time values are user  
programmable and are held in two registers. An alternate set of high/low  
count values is held in another set of registers to allow the generation of  
dual frequency FSK (frequency shift keying) protocols without CPU  
intervention. The MCGEN bit in the MCSR must be set and the BASE bit  
in the MCSR must be cleared to enable carrier generator clocks. The  
block diagram is shown in Figure 9-2.  
SECONDARY HIGH COUNT REGISTER  
PRIMARY HIGH COUNT REGISTER  
=?  
MODE  
f
OSC  
BASE  
CLK  
6-BIT UP COUNTER  
MODULATOR/  
CARRIER GENERATOR  
ENABLE  
PRIMARY/  
SECONDARY  
SELECT  
CLR  
CARRIER OUT  
=?  
SECONDARY LOW COUNT REGISTER  
PRIMARY LOW COUNT REGISTER  
Figure 9-2. Carrier Generator Block Diagram  
General Release Specification  
70  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
   
Carrier Modulator Transmitter (CMT)  
Carrier Generator  
9.4.1 Tim e Counte r  
The high/low time counter is a 6-bit up counter. After each increment, the  
contents of the counter are compared with the appropriate high or low  
count value register. When this value is reached, the counter is reset and  
the compare is redirected to the other count value register. Assuming  
that the high time count compare register is currently active, a valid  
compare will cause the carrier output to be driven low. The counter will  
continue to increment and when reaching the value stored in the  
selected low count value register, it will be cleared and will cause the  
carrier output to be driven high. The cycle repeats, automatically  
generating a periodic signal which is directed to the modulator. The  
lowest frequency (maximum period) and highest frequency (minimum  
period) which can be generated are defined below.  
6
f
f
= f ÷ (2 x (2 – 1)) Hz  
min  
osc  
= f ÷ (2 x 1) Hz  
max  
osc  
In the general case, the carrier generator output frequency is:  
f
= f ÷ (Highcount + Lowcount) Hz  
osc  
out  
Where:  
0 < Highcount < 64 and  
0 < Lowcount < 64  
NOTE: These equations assume the DIV2 bit (bit 6) of the MCSR is clear. When  
the DIV2 bit is set, the carrier generator frequency will be half of what is  
shown in these equations.  
The duty cycle of the carrier signal is controlled by varying the ratio of  
high time to low + high time. As the input clock period is fixed, the duty  
cycle resolution will be proportional to the number of counts required to  
generate the desired carrier period.  
Highcount  
Duty Cycle = ---------------------------------------------------------------  
Highcount + Lowcount  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
71  
Carrier Modulator Transmitter (CMT)  
 
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
9.4.2 Ca rrie r Ge ne ra tor Da ta Re g iste rs (CHR1, CLR1, CHR2, a nd CLR2)  
The carrier generator contains two, 7-bit data registers: primary high  
time (CHR1), primary low time (CLR1); and two, 6-bit data registers:  
secondary high time (CHR2) and secondary low time (CLR2). Bit 7 of  
CHR1 and CHR2 is used to read and write the IRO latch.  
Address: $0010  
Bit 7  
6
0
0
5
PH5  
U
4
PH4  
U
3
PH3  
U
2
PH2  
U
1
PH1  
U
Bit 0  
PH0  
U
Read:  
Write:  
Reset:  
IROLN  
0
U = Unaffected  
Figure 9-3. Carrier Generator Data Register CHR1  
Address: $0011  
Bit 7  
6
0
0
5
PL5  
U
4
PL4  
U
3
PL3  
U
2
PL2  
U
1
PL1  
U
Bit 0  
PL0  
U
Read:  
IROLP  
Write:  
Reset:  
0
U = Unaffected  
Figure 9-4. Carrier Generator Data Register CLR1  
Address: $0012  
Bit 7  
6
0
0
5
SH5  
U
4
SH4  
U
3
SH3  
U
2
SH2  
U
1
SH1  
U
Bit 0  
SH0  
U
Read:  
0
Write:  
Reset:  
0
U = Unaffected  
Figure 9-5. Carrier Generator Data Register CHR2  
General Release Specification  
72  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
 
Carrier Modulator Transmitter (CMT)  
Carrier Generator  
Address: $0013  
Bit 7  
6
0
0
5
SL5  
U
4
SL4  
U
3
SL3  
U
2
SL2  
U
1
SL1  
U
Bit 0  
SL0  
U
Read:  
0
Write:  
Reset:  
0
U = Unaffected  
Figure 9-6. Carrier Generator Data Register CLR2  
PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data  
Values  
When selected, these bits contain the number of input clocks required  
to generate the carrier high and low time periods. When operating in  
time mode (see 9.5.1 Time Mode), this register pair is always  
selected. When operating in FSK mode (see 9.5.2 FSK Mode), this  
register pair and the secondary register pair are alternately selected  
under control of the modulator. The primary carrier high and low time  
values are undefined out of reset. These bits must be written to  
nonzero values before the carrier generator is enabled to avoid  
spurious results.  
NOTE: Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will  
also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear,  
the IRO latch value appears on the IRO output pin. Care should be taken  
that bit 7 of the data to be written to CHR1 or CHL1 should contain the  
desired state of the IRO latch.  
SH0–SH5 and SL0–SL5 — Secondary Carrier High and Low Time Data  
Values  
When selected, these bits contain the number of input clocks required  
to generate the carrier high and low time periods. When operating in  
time mode (see 9.5.1 Time Mode), this register pair is never selected.  
and the secondary register pair are alternately selected under control  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
73  
Carrier Modulator Transmitter (CMT)  
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
of the modulator. The secondary carrier high and low time values are  
undefined out of reset. These bits must be written to nonzero values  
before the carrier generator is enabled when operating in FSK mode.  
IROLN and IROLP — IRO Latch Control  
Reading IROLN or IROLP reads the state of the IRO latch. Writing  
IROLN updates the IRO latch with the data being written on the  
negative edge of the internal processor clock (f /2). Writing IROLP  
osc  
updates the IRO latch on the positive edge of the internal processor  
clock; for example, one f period later. The IRO latch is clear out of  
osc  
reset.  
NOTE: Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also  
update the primary carrier high and low data values. Care should be  
taken that bits 5–0 of the data to be written to CHR1 or CHL1 should  
contain the desired values for the primary carrier high or low data.  
9.5 Mod ula tor  
The modulator consists of a 12-bit down counter with underflow  
detection which is loaded from the modulation mark period from the  
mark buffer register, MBUFF. When this counter underflows, the  
modulator gate is closed and a 12-bit comparator is enabled which  
continually compares the logical complement of the contents of the (still)  
decrementing counter with the contents of the modulation space period  
register, SREG. When a match is obtained, the modulator control gate  
is opened again. Should SREG = 0, the match will be immediate and no  
space period will be generated (for instance, for FSK protocols which  
require successive bursts of different frequencies). When the match  
occurs, the counter is reloaded with the contents of MBUFF, SREG is  
reloaded with the contents of its buffer, SBUFF, and the cycle repeats.  
The MCGEN bit in the MCSR must be set to enable the modulator timer.  
The 12-bit MBUFF and SBUFF registers are accessed through three  
8-bit modulator period registers, MDR1, MDR2, and MDR3.  
General Release Specification  
74  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
 
Carrier Modulator Transmitter (CMT)  
Modulator  
The modulator can operate in two modes, time or FSK. In time mode the  
modulator counts clocks derived from the system oscillator and  
modulates a single-carrier frequency or no carrier (baseband). In FSK  
mode, the modulator counts carrier periods and instructs the carrier  
generator to alternate between two carrier frequencies whenever a  
modulation period (mark + space counts) expires.  
12 BITS  
MBUFF  
0
f
8
OSC  
CLOCK CONTROL  
.
13-BIT DOWN COUNTER *  
12  
CARRIER OUT  
LOAD MBUFF/SBUFF  
MODULATOR  
OUT  
MODULATOR GATE  
.
=?  
SYSTEM CONTROL  
PRIMARY/SECONDARY SELECT  
12  
SREG *  
MODULATOR/  
CARRIER GENERATOR.  
ENABLE  
SBUFF  
EOC FLAG  
MODULATOR  
CONTROL/STATUS REGISTER  
12 BITS  
EOC INTERRUPT ENABLE  
MODE  
BASE  
DIV2  
* DENOTES HIDDEN REGISTER  
Figure 9-7. Modulator Block Diagram  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
75  
Carrier Modulator Transmitter (CMT)  
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
9.5.1 Tim e Mod e  
When the modulator operates in time mode, the modulation mark and  
space periods consist of zero or an integer number of f ÷ 8 clocks  
osc  
(= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs  
and a maximum mark and space periods of about 16 ms (each).  
However, to prevent carrier glitches which could affect carrier spectral  
purity, the modulator control gate and carrier clock are synchronized.  
The carrier signal is activated when the modulator gate opens. The  
modulator gate can only close when the carrier signal is low (the output  
logic level during space periods is low). If the carrier generator is in  
baseband mode (BASE bit in MCSR is high), the modulator output will  
be at a logic one for the duration of the mark period and at a logic zero  
for the duration of a space period. See Figure 9-8.  
The mark and space time equations are:  
(MBUFF + 1) ×8  
t
= ---------------------------------------------secs  
mark  
t
f
osc  
SBUFF × 8  
= ------------------------------ secs  
space  
f
osc  
Setting the DIV2 bit in the MCSR will double mark and space times.  
General Release Specification  
76  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
 
Carrier Modulator Transmitter (CMT)  
Modulator  
f
÷ 8  
OSC  
CARRIER FREQUENCY  
MODULATOR GATE  
MARK  
SPACE  
MARK  
SPACE  
MARK  
TIME MODE OUTPUT  
BASEBAND OUTPUT  
Figure 9-8. CMT Operation in Time Mode  
9.5.2 FSK Mod e  
When the modulator operates in FSK mode, the modulation mark and  
space periods consist of an integer number of carrier clocks (space  
period can be zero). When the mark period expires, the space period is  
transparently started (as in time mode); however, in FSK mode the  
carrier switches between data registers in preparation for the next mark  
period. The carrier generator toggles between primary and secondary  
data register values whenever the modulator mark period expires. The  
space period provides an interpulse gap (no carrier), but if SBUFF = 0,  
then the modulator and carrier generator will switch between carrier  
frequencies without a gap or any carrier glitches (zero space).  
Using timing data for carrier burst and interpulse gap length calculated  
by the CPU, FSK mode can automatically generate a phase-coherent,  
dual-frequency FSK signal with programmable burst and interburst  
gaps.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
77  
Carrier Modulator Transmitter (CMT)  
   
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
The mark and space time equations for FSK mode are:  
MBUFF + 1  
t
= ------------------------------- sec s  
mark  
f
g
c
SBUFF  
= --------------------secs  
t
space  
f
cg  
Where f is the frequency output from the carrier generator, setting the  
cg  
DIV2 bit in the MCSR will double mark and space times.  
9.5.3 Exte nd e d Sp a c e Op e ra tion  
In either time or FSK mode, the space period can be made longer than  
the maximum possible value of SBUFF. Setting the EXSPC bit in the  
MCSR will force the modulator to treat the next modulation period  
(beginning with the next load of MBUFF/SBUFF) as a space period  
equal in length to the mark and space counts combined. Subsequent  
modulation periods will consist entirely of these extended space periods  
with no mark periods. Clearing EXSPC will return the modulator to  
standard operation at the beginning of the next modulation period. To  
calculate the length of an extended space in time mode, use the  
equation:  
((SBUFF )+(MBUFF +1+SBUFF ) +... (MBUFF +1+SBUFF )) x 8  
1
2
2
n
n
t
=
secs  
exspace  
f
osc  
Where:  
the subscripts 1, 2, ... n refer to the modulation periods that elapsed  
while the EXSPC bit was set.  
Similarly, to calculate the length of an extended space in FSK mode, use  
the equation:  
((SBUFF )+(MBUFF +1+SBUFF )+... (MBUFF +1+SBUFF ))  
1
2
2
n
n
secs  
t
=
exspace  
f
cg  
General Release Specification  
78  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
 
Carrier Modulator Transmitter (CMT)  
Modulator  
Where f is the frequency output from the carrier generator. For an  
cg  
example of extended space operation, see Figure 9-9.  
NOTE: The EXSPC feature can be used to emulate a zero mark event.  
SET EXSPC  
CLEAR EXSPC  
Figure 9-9. Extended Space Operation  
9.5.3.1 End Of Cyc le (EOC) Inte rrup t  
At the end of each cycle (when the counter is reloaded from MBUFF),  
the end of cycle (EOC) flag is set. If the interrupt enable bit was  
previously set, an interrupt also will be issued to the CPU. The EOC  
interrupt provides a means for the user to reload new mark/space values  
into the MBUFF and SBUFF registers. As the EOC interrupt is coincident  
with reloading the counter, MBUFF does not require additional buffering  
and may be updated with a new value for the next period from within the  
EOC interrupt service routine (ISR). To allow both mark and space  
period values to be updated from within the same ISR, SREG is buffered  
by SBUFF. The contents written to SBUFF are transferred to the active  
register SREG at the end of every cycle regardless of the state of the  
EOC flag. The EOC flag is cleared by a read of the modulator control and  
status register (MCSR) followed by an access of MDR2 or MDR3. The  
EOC flag must be cleared within the ISR to prevent another interrupt  
being generated after exiting the ISR. If the EOC interrupt is not being  
used (IE = 0), the EOC flag need not be cleared.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
79  
Carrier Modulator Transmitter (CMT)  
   
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
9.5.3.2 Mo d ula to r Co ntro l a nd Sta tus Re g iste r  
The modulator control and status register (MCSR) contains the  
modulator and carrier generator enable (MCGEN), interrupt enable (IE),  
mode select (MODE), baseband enable (BASE), extended space  
(EXSPC), and external interrupt mask (EIMSK) control bits,  
divide-by-two prescaler (DIV2) bit, and the end of cycle (EOC) status  
bit.  
Address: $0014  
Bit 7  
EOC  
6
DIV2  
0
5
EIMSK  
0
4
EXSPC  
0
3
BASE  
0
2
MODE  
0
1
IE  
0
Bit 0  
MCGEN  
0
Read:  
Write:  
Reset:  
0
Unimplemented  
Figure 9-10. Modulator Control and Status Register (MCSR)  
EOC — End Of Cycle Status Flag  
EOC is set when a match occurs between the contents of the space  
period register, SREG, and the down counter. This is recognized as  
the end of the modulation cycle. At this time, the counter is initialized  
with the (possibly new) contents of the mark period buffer, MBUFF,  
and the space period register, SREG, is loaded with the (possibly  
new) contents of the space period buffer, SBUFF. This flag is cleared  
by a read of the MCSR followed by an access of MDR2 or MDR3. The  
EOC flag is cleared by reset.  
1 = End of modulator cycle (counter = SBUFF) has occurred  
0 = Current modulation cycle in progress  
DIV2 — Divide-by-two prescaler  
The divide-by-two prescaler causes the CMT to be clocked at the bus  
rate when enabled; 2 x the bus rate when disabled (f ). This bit is  
osc  
not double buffered and so should not be set during a transmission.  
1 = Divide-by-two prescaler enabled  
0 = Divide-by-two prescaler disabled  
General Release Specification  
80  
MC68HC05RC16 — Rev. 3.0  
Carrier Modulator Transmitter (CMT)  
MOTOROLA  
 
Carrier Modulator Transmitter (CMT)  
Modulator  
EIMSK — External Interrupt Mask  
The external interrupt mask bit is used to mask IRQ and keyscan  
interrupts. This bit is cleared by reset.  
1 = IRQ and keyscan interrupts masked  
0 = IRQ and keyscan interrupts enabled  
EXSPC — Extended Space Enable  
For a description of the extended space enable bit, see 9.5.3  
Extended Space Operation. This bit is cleared by reset.  
1 = Extended space enabled  
0 = Extended space disabled  
BASE — Baseband Enable  
When set, the BASE bit disables the carrier generator and forces the  
carrier output high for generation of baseband protocols. When BASE  
is clear, the carrier generator is enabled and the carrier output toggles  
at the frequency determined by values stored in the carrier data  
registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit  
is not double buffered and should not be written to during a  
transmission.  
1 = Baseband enabled  
0 = Baseband disabled  
MODE — Mode Select  
For a description of CMT operation in time mode, see 9.5.1 Time  
Mode. For a description of CMT operation in FSK mode, see 9.5.2  
FSK Mode. This bit is cleared by reset. This bit is not double buffered  
and should not be written to during a transmission.  
1 = CMT operates in FSK mode.  
0 = CMT operates in time mode.  
IE — Interrupt Enable  
A CPU interrupt will be requested when EOC is set if IE was  
previously set. If IE is clear, EOC will not request a CPU interrupt.  
1 = CPU interrupt enabled  
0 = CPU interrupt disabled  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
81  
Carrier Modulator Transmitter (CMT)  
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
MCGEN — Modulator and Carrier Generator Enable  
Setting MCGEN will initialize the carrier generator and modulator and  
will enable all clocks. Once enabled, the carrier generator and  
modulator will function continuously. When MCGEN is cleared, the  
current modulator cycle will be allowed to expire before all carrier and  
modulator clocks are disabled (to save power) and the modulator  
output is forced low. The user should initialize all data and control  
registers before enabling the system to prevent spurious operation.  
This bit is cleared by reset.  
1 = Modulator and carrier generator enabled  
0 = Modulator and carrier generator disabled  
General Release Specification  
82  
MC68HC05RC16 — Rev. 3.0  
Carrier Modulator Transmitter (CMT)  
MOTOROLA  
Carrier Modulator Transmitter (CMT)  
Modulator  
9.5.4 Mod ula tor Pe riod Da ta Re g iste rs (MDR1, MDR2, a nd MDR3)  
The 12-bit MBUFF and SBUFF registers are accessed through three  
8-bit registers: MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the  
least significant eight bits of MBUFF and SBUFF respectively. MDR1  
contains the two most significant nibbles of MBUFF and SBUFF. In  
many applications, periods greater than those obtained by eight bits will  
not be required. Dividing the registers in this manner allows the user to  
clear MDR1 and generate 8-bit periods with just two data writes.  
Address: $0015  
Bit 7  
6
5
4
3
2
1
Bit 0  
SB8  
Read:  
Write:  
Reset:  
MB11  
MB10  
MB9  
MB8  
SB11  
SB10  
SB9  
Unaffected by Reset  
Figure 9-11. Modulator Period Data Register MDR1  
Address: $0016  
Bit 7  
6
5
4
3
2
1
Bit 0  
MB0  
Read:  
MB7  
Write:  
MB6  
MB5  
MB4  
MB3  
MB2  
MB1  
Reset:  
Unaffected by Reset  
Figure 9-12. Modulator Period Data Register MDR2  
Address: $0017  
Bit 7  
6
5
4
3
2
1
Bit 0  
SB0  
Read:  
Write:  
Reset:  
SB7  
SB6  
SB5  
SB4  
SB3  
SB2  
SB1  
Unaffected by Reset  
Figure 9-13. Modulator Period Data Register MDR3  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
83  
Carrier Modulator Transmitter (CMT)  
 
Ca rrie r Mod ula tor Tra nsm itte r (CMT)  
General Release Specification  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
84  
Carrier Modulator Transmitter (CMT)  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 10. Instruc tion Se t  
10.1 Conte nts  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Instruction Set  
85  
Instruc tion Se t  
10.2 Introd uc tion  
The MCU instruction set has 62 instructions and uses eight addressing  
modes. The instructions include all those of the M146805 CMOS Family  
plus one more: the unsigned multiply (MUL) instruction. The MUL  
instruction allows unsigned multiplication of the contents of the  
accumulator (A) and the index register (X). The high-order product is  
stored in the index register, and the low-order product is stored in the  
accumulator.  
10.3 Ad d re ssing Mod e s  
The CPU uses eight addressing modes for flexibility in accessing data.  
The addressing modes provide eight different ways for the CPU to find  
the data required to execute an instruction. The eight addressing modes  
are:  
• Inherent  
• Immediate  
• Direct  
• Extended  
• Indexed, no offset  
• Indexed, 8-bit offset  
• Indexed, 16-bit offset  
• Relative  
General Release Specification  
86  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
   
Instruction Set  
Addressing Modes  
10.3.1 Inhe re nt  
Inherent instructions are those that have no operand, such as return  
from interrupt (RTI) and stop (STOP). Some of the inherent instructions  
act on data in the CPU registers, such as set carry flag (SEC) and  
increment accumulator (INCA). Inherent instructions require no operand  
address and are one byte long.  
10.3.2 Im m e d ia te  
Immediate instructions are those that contain a value to be used in an  
operation with the value in the accumulator or index register. Immediate  
instructions require no operand address and are two bytes long. The  
opcode is the first byte, and the immediate data value is the second byte.  
10.3.3 Dire c t  
Direct instructions can access any of the first 256 memory locations with  
two bytes. The first byte is the opcode, and the second is the low byte of  
the operand address. In direct addressing, the CPU automatically uses  
$00 as the high byte of the operand address.  
10.3.4 Exte nd e d  
Extended instructions use three bytes and can access any address in  
memory. The first byte is the opcode; the second and third bytes are the  
high and low bytes of the operand address.  
When using the Motorola assembler, the programmer does not need to  
specify whether an instruction is direct or extended. The assembler  
automatically selects the shortest form of the instruction.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
87  
Instruction Set  
       
Instruc tion Se t  
10.3.5 Ind e xe d , No Offse t  
Indexed instructions with no offset are 1-byte instructions that can  
access data with variable addresses within the first 256 memory  
locations. The index register contains the low byte of the effective  
address of the operand. The CPU automatically uses $00 as the high  
byte, so these instructions can address locations $0000–$00FF.  
Indexed, no offset instructions are often used to move a pointer through  
a table or to hold the address of a frequently used RAM or I/O location.  
10.3.6 Ind e xe d , 8-Bit Offse t  
Indexed, 8-bit offset instructions are 2-byte instructions that can access  
data with variable addresses within the first 511 memory locations. The  
CPU adds the unsigned byte in the index register to the unsigned byte  
following the opcode. The sum is the effective address of the operand.  
These instructions can access locations $0000–$01FE.  
Indexed 8-bit offset instructions are useful for selecting the kth element  
in an n-element table. The table can begin anywhere within the first 256  
memory locations and could extend as far as location 510 ($01FE). The  
k value is typically in the index register, and the address of the beginning  
of the table is in the byte following the opcode.  
10.3.7 Ind e xe d ,16-Bit Offse t  
Indexed, 16-bit offset instructions are 3-byte instructions that can access  
data with variable addresses at any location in memory. The CPU adds  
the unsigned byte in the index register to the two unsigned bytes  
following the opcode. The sum is the effective address of the operand.  
The first byte after the opcode is the high byte of the 16-bit offset; the  
second byte is the low byte of the offset.  
Indexed, 16-bit offset instructions are useful for selecting the kth element  
in an n-element table anywhere in memory.  
As with direct and extended addressing, the Motorola assembler  
determines the shortest form of indexed addressing.  
General Release Specification  
88  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
     
Instruction Set  
Instruction Types  
10.3.8 Re la tive  
Relative addressing is only for branch instructions. If the branch  
condition is true, the CPU finds the effective branch destination by  
adding the signed byte following the opcode to the contents of the  
program counter. If the branch condition is not true, the CPU goes to the  
next instruction. The offset is a signed, two’s complement byte that gives  
a branching range of –128 to +127 bytes from the address of the next  
location after the branch instruction.  
When using the Motorola assembler, the programmer does not need to  
calculate the offset, because the assembler determines the proper offset  
and verifies that it is within the span of the branch.  
10.4 Instruc tion Typ e s  
The MCU instructions fall into the following five categories:  
• Register/Memory Instructions  
• Read-Modify-Write Instructions  
• Jump/Branch Instructions  
• Bit Manipulation Instructions  
• Control Instructions  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
89  
Instruction Set  
   
Instruc tion Se t  
10.4.1 Re g iste r/ Me m ory Instruc tions  
These instructions operate on CPU registers and memory locations.  
Most of them use two operands. One operand is in either the  
accumulator or the index register. The CPU finds the other operand in  
memory.  
Table 10-1. Register/Memory Instructions  
Instruction  
Add Memory Byte and Carry Bit to Accumulator  
Add Memory Byte to Accumulator  
AND Memory Byte with Accumulator  
Bit Test Accumulator  
Mnemonic  
ADC  
ADD  
AND  
BIT  
Compare Accumulator  
CMP  
CPX  
EOR  
LDA  
Compare Index Register with Memory Byte  
EXCLUSIVE OR Accumulator with Memory Byte  
Load Accumulator with Memory Byte  
Load Index Register with Memory Byte  
Multiply  
LDX  
MUL  
ORA  
SBC  
STA  
OR Accumulator with Memory Byte  
Subtract Memory Byte and Carry Bit from Accumulator  
Store Accumulator in Memory  
Store Index Register in Memory  
STX  
Subtract Memory Byte from Accumulator  
SUB  
General Release Specification  
90  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
 
Instruction Set  
Instruction Types  
10.4.2 Re a d -Mod ify-Write Instruc tions  
These instructions read a memory location or a register, modify its  
contents, and write the modified value back to the memory location or to  
the register.  
NOTE: Do not use read-modify-write operations on write-only registers.  
Table 10-2. Read-Modify-Write Instructions  
Instruction  
Arithmetic Shift Left (Same as LSL)  
Arithmetic Shift Right  
Bit Clear  
Mnemonic  
ASL  
ASR  
(1)  
BCLR  
(1)  
Bit Set  
BSET  
Clear Register  
CLR  
COM  
DEC  
INC  
Complement (One’s Complement)  
Decrement  
Increment  
Logical Shift Left (Same as ASL)  
Logical Shift Right  
LSL  
LSR  
NEG  
ROL  
ROR  
Negate (Two’s Complement)  
Rotate Left through Carry Bit  
Rotate Right through Carry Bit  
Test for Negative or Zero  
(2)  
TST  
1. Unlike other read-modify-write instructions, BCLR and  
BSET use only direct addressing.  
2. TST is an exception to the read-modify-write sequence  
because it does not write a replacement value.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
91  
Instruction Set  
 
Instruc tion Se t  
10.4.3 Jum p / Bra nc h Instruc tions  
Jump instructions allow the CPU to interrupt the normal sequence of the  
program counter. The unconditional jump instruction (JMP) and the  
jump-to-subroutine instruction (JSR) have no register operand. Branch  
instructions allow the CPU to interrupt the normal sequence of the  
program counter when a test condition is met. If the test condition is not  
met, the branch is not performed.  
The BRCLR and BRSET instructions cause a branch based on the state  
of any readable bit in the first 256 memory locations. These 3-byte  
instructions use a combination of direct addressing and relative  
addressing. The direct address of the byte to be tested is in the byte  
following the opcode. The third byte is the signed offset byte. The CPU  
finds the effective branch destination by adding the third byte to the  
program counter if the specified bit tests true. The bit to be tested and its  
condition (set or clear) is part of the opcode. The span of branching is  
from –128 to +127 from the address of the next location after the branch  
instruction. The CPU also transfers the tested bit to the carry/borrow bit  
of the condition code register.  
General Release Specification  
92  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
 
Instruction Set  
Instruction Types  
Table 10-3. Jump and Branch Instructions  
Instruction  
Branch if Carry Bit Clear  
Branch if Carry Bit Set  
Branch if Equal  
Mnemonic  
BCC  
BCS  
BEQ  
BHCC  
BHCS  
BHI  
Branch if Half-Carry Bit Clear  
Branch if Half-Carry Bit Set  
Branch if Higher  
Branch if Higher or Same  
Branch if IRQ Pin High  
Branch if IRQ Pin Low  
Branch if Lower  
BHS  
BIH  
BIL  
BLO  
Branch if Lower or Same  
Branch if Interrupt Mask Clear  
Branch if Minus  
BLS  
BMC  
BMI  
Branch if Interrupt Mask Set  
Branch if Not Equal  
Branch if Plus  
BMS  
BNE  
BPL  
Branch Always  
BRA  
Branch if Bit Clear  
BRCLR  
BRN  
BRSET  
BSR  
Branch Never  
Branch if Bit Set  
Branch to Subroutine  
Unconditional Jump  
Jump to Subroutine  
JMP  
JSR  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
93  
Instruction Set  
Instruc tion Se t  
10.4.4 Bit Ma nip ula tion Instruc tions  
The CPU can set or clear any writable bit in the first 256 bytes of  
memory, which includes I/O registers and on-chip RAM locations. The  
CPU can also test and branch based on the state of any bit in any of the  
first 256 memory locations.  
Table 10-4. Bit Manipulation Instructions  
Instruction  
Mnemonic  
BCLR  
Bit Clear  
Branch if Bit Clear  
Branch if Bit Set  
Bit Set  
BRCLR  
BRSET  
BSET  
General Release Specification  
94  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
 
Instruction Set  
Instruction Types  
10.4.5 Control Instruc tions  
These instructions act on CPU registers and control CPU operation  
during program execution.  
Table 10-5. Control Instructions  
Instruction  
Clear Carry Bit  
Mnemonic  
CLC  
CLI  
Clear Interrupt Mask  
No Operation  
NOP  
RSP  
RTI  
Reset Stack Pointer  
Return from Interrupt  
Return from Subroutine  
Set Carry Bit  
RTS  
SEC  
SEI  
Set Interrupt Mask  
Stop Oscillator and Enable IRQ Pin  
Software Interrupt  
STOP  
SWI  
Transfer Accumulator to Index Register  
Transfer Index Register to Accumulator  
Stop CPU Clock and Enable Interrupts  
TAX  
TXA  
WAIT  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
95  
Instruction Set  
 
Instruc tion Se t  
10.5 Instruc tion Se t Sum m a ry  
Table 10-6. Instruction Set Summary  
Effect on  
CCR  
Source  
Form  
Operation  
Description  
H I N Z C  
ii  
dd  
hh ll  
ee ff  
ff  
ADC #opr  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A9  
B9  
C9  
D9  
E9  
F9  
2
3
4
5
4
3
ADC opr  
ADC opr  
ADC opr,X  
ADC opr,X  
ADC ,X  
Add with Carry  
A (A) + (M) + (C)  
↕ ↕ ↕  
ii  
dd  
hh ll  
ee ff  
ff  
ADD #opr  
ADD opr  
ADD opr  
ADD opr,X  
ADD opr,X  
ADD ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
AB  
BB  
CB  
DB  
EB  
FB  
2
3
4
5
4
3
Add without Carry  
A (A) + (M)  
↕ ↕ ↕  
ii  
dd  
hh ll  
ee ff  
ff  
AND #opr  
AND opr  
AND opr  
AND opr,X  
AND opr,X  
AND ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A4  
B4  
C4  
D4  
E4  
F4  
2
3
4
5
4
3
Logical AND  
A (A) (M)  
— — ↕ ↕ —  
dd  
ASL opr  
ASLA  
ASLX  
ASL opr,X  
ASL ,X  
DIR  
INH  
INH  
IX1  
IX  
38  
48  
58  
68  
78  
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)  
— — ↕ ↕ ↕  
C
0
ff  
b7  
b7  
b0  
b0  
dd  
ASR opr  
ASRA  
ASRX  
ASR opr,X  
ASR ,X  
DIR  
INH  
INH  
IX1  
IX  
37  
47  
57  
67  
77  
5
3
3
6
5
C
Arithmetic Shift Right  
— — ↕ ↕ ↕  
ff  
BCC rel  
Branch if Carry Bit Clear  
PC (PC) + 2 + rel ? C = 0  
— — — — — REL  
24 rr  
3
DIR (b0) 11 dd  
DIR (b1) 13 dd  
DIR (b2) 15 dd  
DIR (b3) 17 dd  
DIR (b4) 19 dd  
DIR (b5) 1B dd  
DIR (b6) 1D dd  
DIR (b7) 1F dd  
5
5
5
5
5
5
5
5
BCLR n opr  
Clear Bit n  
Mn 0  
— — — — —  
BCS rel  
BEQ rel  
BHCC rel  
BHCS rel  
BHI rel  
Branch if Carry Bit Set (Same as BLO)  
Branch if Equal  
PC (PC) + 2 + rel ? C = 1  
PC (PC) + 2 + rel ? Z = 1  
PC (PC) + 2 + rel ? H = 0  
PC (PC) + 2 + rel ? H = 1  
— — — — — REL  
— — — — — REL  
— — — — — REL  
— — — — — REL  
25 rr  
27 rr  
28 rr  
29 rr  
22 rr  
24 rr  
3
3
3
3
3
3
Branch if Half-Carry Bit Clear  
Branch if Half-Carry Bit Set  
Branch if Higher  
PC (PC) + 2 + rel ? C Z = 0 — — — — — REL  
PC (PC) + 2 + rel ? C = 0 — — — — — REL  
BHS rel  
Branch if Higher or Same  
General Release Specification  
96  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
 
Instruction Set  
Instruction Set Summary  
Table 10-6. Instruction Set Summary (Continued)  
Effect on  
Source  
Form  
CCR  
Operation  
Description  
H I N Z C  
BIH rel  
Branch if IRQ Pin High  
PC (PC) + 2 + rel ? IRQ = 1 — — — — — REL  
2F rr  
2E rr  
3
3
BIL rel  
Branch if IRQ Pin Low  
PC (PC) + 2 + rel ? IRQ = 0 — — — — — REL  
ii  
dd  
hh ll  
ee ff  
ff  
BIT #opr  
BIT opr  
BIT opr  
BIT opr,X  
BIT opr,X  
BIT ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A5  
B5  
C5  
D5  
E5  
F5  
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte  
(A) (M)  
— — ↕ ↕ —  
BLO rel  
BLS rel  
BMC rel  
BMI rel  
BMS rel  
BNE rel  
BPL rel  
BRA rel  
Branch if Lower (Same as BCS)  
Branch if Lower or Same  
Branch if Interrupt Mask Clear  
Branch if Minus  
PC (PC) + 2 + rel ? C = 1  
— — — — — REL  
25 rr  
23 rr  
2C rr  
2B rr  
2D rr  
26 rr  
2A rr  
20 rr  
3
3
3
3
3
3
3
3
PC (PC) + 2 + rel ? C Z = 1 — — — — — REL  
PC (PC) + 2 + rel ? I = 0  
PC (PC) + 2 + rel ? N = 1  
PC (PC) + 2 + rel ? I = 1  
PC (PC) + 2 + rel ? Z = 0  
PC (PC) + 2 + rel ? N = 0  
PC (PC) + 2 + rel ? 1 = 1  
— — — — — REL  
— — — — — REL  
— — — — — REL  
— — — — — REL  
— — — — — REL  
— — — — — REL  
Branch if Interrupt Mask Set  
Branch if Not Equal  
Branch if Plus  
Branch Always  
DIR (b0) 01 dd rr  
DIR (b1) 03 dd rr  
DIR (b2) 05 dd rr  
DIR (b3) 07 dd rr  
DIR (b4) 09 dd rr  
DIR (b5) 0B dd rr  
DIR (b6) 0D dd rr  
DIR (b7) 0F dd rr  
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear  
PC (PC) + 2 + rel ? Mn = 0  
PC (PC) + 2 + rel ? 1 = 0  
PC (PC) + 2 + rel ? Mn = 1  
— — — —  
BRN rel  
Branch Never  
— — — — — REL  
21 rr  
3
DIR (b0) 00 dd rr  
DIR (b1) 02 dd rr  
DIR (b2) 04 dd rr  
DIR (b3) 06 dd rr  
DIR (b4) 08 dd rr  
DIR (b5) 0A dd rr  
DIR (b6) 0C dd rr  
DIR (b7) 0E dd rr  
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set  
— — — —  
DIR (b0) 10 dd  
DIR (b1) 12 dd  
DIR (b2) 14 dd  
DIR (b3) 16 dd  
DIR (b4) 18 dd  
DIR (b5) 1A dd  
DIR (b6) 1C dd  
DIR (b7) 1E dd  
5
5
5
5
5
5
5
5
BSET n opr  
Set Bit n  
Mn 1  
— — — — —  
PC (PC) + 2; push (PCL)  
SP (SP) – 1; push (PCH)  
SP (SP) – 1  
BSR rel  
Branch to Subroutine  
— — — — — REL  
AD rr  
6
PC (PC) + rel  
CLC  
CLI  
Clear Carry Bit  
C 0  
— — — — 0  
— 0 — — —  
INH  
INH  
98  
9A  
2
2
Clear Interrupt Mask  
I 0  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
97  
Instruction Set  
Instruc tion Se t  
Table 10-6. Instruction Set Summary (Continued)  
Effect on  
Source  
Form  
CCR  
Operation  
Description  
H I N Z C  
dd  
ff  
CLR opr  
CLRA  
CLRX  
CLR opr,X  
CLR ,X  
M $00  
A $00  
X $00  
M $00  
M $00  
DIR  
INH  
INH  
IX1  
IX  
3F  
4F  
5F  
6F  
7F  
5
3
3
6
5
Clear Byte  
— — 0 1 —  
ii  
dd  
hh ll  
ee ff  
ff  
CMP #opr  
CMP opr  
CMP opr  
CMP opr,X  
CMP opr,X  
CMP ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A1  
B1  
C1  
D1  
E1  
F1  
2
3
4
5
4
3
Compare Accumulator with Memory Byte  
Complement Byte (One’s Complement)  
Compare Index Register with Memory Byte  
Decrement Byte  
(A) – (M)  
— — ↕ ↕ ↕  
dd  
ff  
COM opr  
COMA  
COMX  
COM opr,X  
COM ,X  
M (M) = $FF – (M)  
A (A) = $FF – (A)  
X (X) = $FF – (X)  
M (M) = $FF – (M)  
M (M) = $FF – (M)  
DIR  
INH  
INH  
IX1  
IX  
33  
43  
53  
63  
73  
5
3
3
6
5
— — ↕ ↕  
1
ii  
dd  
hh ll  
ee ff  
ff  
CPX #opr  
CPX opr  
CPX opr  
CPX opr,X  
CPX opr,X  
CPX ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A3  
B3  
C3  
D3  
E3  
F3  
2
3
4
5
4
3
(X) – (M)  
— — ↕ ↕ ↕  
— — ↕ ↕ —  
— — ↕ ↕ —  
dd  
ff  
DEC opr  
DECA  
DECX  
DEC opr,X  
DEC ,X  
M (M) – 1  
A (A) – 1  
X (X) – 1  
M (M) – 1  
M (M) – 1  
DIR  
INH  
INH  
IX1  
IX  
3A  
4A  
5A  
6A  
7A  
5
3
3
6
5
ii  
dd  
hh ll  
ee ff  
ff  
EOR #opr  
EOR opr  
EOR opr  
EOR opr,X  
EOR opr,X  
EOR ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A8  
B8  
C8  
D8  
E8  
F8  
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory  
Byte  
A (A) (M)  
dd  
ff  
INC opr  
INCA  
INCX  
INC opr,X  
INC ,X  
M (M) + 1  
A (A) + 1  
X (X) + 1  
M (M) + 1  
M (M) + 1  
DIR  
INH  
INH  
IX1  
IX  
3C  
4C  
5C  
6C  
7C  
5
3
3
6
5
Increment Byte  
— — ↕ ↕ —  
dd  
hh ll  
ee ff  
ff  
JMP opr  
JMP opr  
JMP opr,X  
JMP opr,X  
JMP ,X  
DIR  
EXT  
IX2  
IX1  
IX  
BC  
CC  
DC  
EC  
FC  
2
3
4
3
2
Unconditional Jump  
PC Jump Address  
— — — — —  
General Release Specification  
98  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
Instruction Set  
Instruction Set Summary  
Table 10-6. Instruction Set Summary (Continued)  
Effect on  
Source  
Form  
CCR  
Operation  
Description  
H I N Z C  
dd  
hh ll  
ee ff  
ff  
JSR opr  
DIR  
EXT  
IX2  
IX1  
IX  
BD  
CD  
DD  
ED  
FD  
5
6
7
6
5
PC (PC) + n (n = 1, 2, or 3)  
Push (PCL); SP (SP) – 1  
Push (PCH); SP (SP) – 1  
PC Effective Address  
JSR opr  
JSR opr,X  
JSR opr,X  
JSR ,X  
Jump to Subroutine  
— — — — —  
ii  
dd  
hh ll  
ee ff  
ff  
LDA #opr  
LDA opr  
LDA opr  
LDA opr,X  
LDA opr,X  
LDA ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A6  
B6  
C6  
D6  
E6  
F6  
2
3
4
5
4
3
Load Accumulator with Memory Byte  
A (M)  
— — ↕ ↕ —  
ii  
dd  
hh ll  
ee ff  
ff  
LDX #opr  
LDX opr  
LDX opr  
LDX opr,X  
LDX opr,X  
LDX ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
AE  
BE  
CE  
DE  
EE  
FE  
2
3
4
5
4
3
Load Index Register with Memory Byte  
Logical Shift Left (Same as ASL)  
X (M)  
— — ↕ ↕ —  
dd  
LSL opr  
LSLA  
LSLX  
LSL opr,X  
LSL ,X  
DIR  
INH  
INH  
IX1  
IX  
38  
48  
58  
68  
78  
5
3
3
6
5
C
0
— — ↕ ↕ ↕  
b7  
b0  
ff  
dd  
LSR opr  
LSRA  
LSRX  
LSR opr,X  
LSR ,X  
DIR  
INH  
INH  
IX1  
IX  
34  
44  
54  
64  
74  
5
3
3
6
5
0
C
Logical Shift Right  
— — 0 ↕ ↕  
0 — — — 0  
— — ↕ ↕ ↕  
— — — — —  
b7  
b0  
ff  
MUL  
Unsigned Multiply  
X : A (X) × (A)  
INH  
42  
11  
dd  
ff  
NEG opr  
NEGA  
NEGX  
NEG opr,X  
NEG ,X  
M –(M) = $00 – (M)  
A –(A) = $00 – (A)  
X –(X) = $00 – (X)  
M –(M) = $00 – (M)  
M –(M) = $00 – (M)  
DIR  
INH  
INH  
IX1  
IX  
30  
40  
50  
60  
70  
5
3
3
6
5
Negate Byte (Two’s Complement)  
No Operation  
NOP  
INH  
9D  
2
ii  
dd  
hh ll  
ee ff  
ff  
ORA #opr  
ORA opr  
ORA opr  
ORA opr,X  
ORA opr,X  
ORA ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
AA  
BA  
CA  
DA  
EA  
FA  
2
3
4
5
4
3
Logical OR Accumulator with Memory  
Rotate Byte Left through Carry Bit  
A (A) (M)  
— — ↕ ↕ —  
dd  
ff  
ROL opr  
ROLA  
ROLX  
ROL opr,X  
ROL ,X  
DIR  
INH  
INH  
IX1  
IX  
39  
49  
59  
69  
79  
5
3
3
6
5
C
— — ↕ ↕ ↕  
b7  
b0  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
99  
Instruction Set  
Instruc tion Se t  
Table 10-6. Instruction Set Summary (Continued)  
Effect on  
Source  
Form  
CCR  
Operation  
Description  
H I N Z C  
dd  
ff  
ROR opr  
RORA  
RORX  
ROR opr,X  
ROR ,X  
DIR  
INH  
INH  
IX1  
IX  
36  
46  
56  
66  
76  
5
3
3
6
5
C
Rotate Byte Right through Carry Bit  
— — ↕ ↕ ↕  
b7  
b0  
RSP  
Reset Stack Pointer  
Return from Interrupt  
SP $00FF  
— — — — —  
INH  
9C  
2
SP (SP) + 1; Pull (CCR)  
SP (SP) + 1; Pull (A)  
SP (SP) + 1; Pull (X)  
SP (SP) + 1; Pull (PCH)  
SP (SP) + 1; Pull (PCL)  
RTI  
↕ ↕ ↕ ↕ ↕  
INH  
80  
9
SP (SP) + 1; Pull (PCH)  
SP (SP) + 1; Pull (PCL)  
RTS  
Return from Subroutine  
— — — — —  
INH  
81  
6
ii  
dd  
hh ll  
ee ff  
ff  
SBC #opr  
SBC opr  
SBC opr  
SBC opr,X  
SBC opr,X  
SBC ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A2  
B2  
C2  
D2  
E2  
F2  
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from  
Accumulator  
A (A) – (M) – (C)  
— — ↕ ↕ ↕  
SEC  
SEI  
Set Carry Bit  
C 1  
— — — — 1  
— 1 — — —  
INH  
INH  
99  
9B  
2
2
Set Interrupt Mask  
I 1  
dd  
hh ll  
ee ff  
ff  
STA opr  
STA opr  
STA opr,X  
STA opr,X  
STA ,X  
DIR  
EXT  
IX2  
IX1  
IX  
B7  
C7  
D7  
E7  
F7  
4
5
6
5
4
Store Accumulator in Memory  
Stop Oscillator and Enable IRQ Pin  
Store Index Register In Memory  
M (A)  
— — ↕ ↕ —  
— 0 — — —  
— — ↕ ↕ —  
STOP  
INH  
8E  
2
dd  
hh ll  
ee ff  
ff  
STX opr  
STX opr  
STX opr,X  
STX opr,X  
STX ,X  
DIR  
EXT  
IX2  
IX1  
IX  
BF  
CF  
DF  
EF  
FF  
4
5
6
5
4
M (X)  
ii  
dd  
hh ll  
ee ff  
ff  
SUB #opr  
SUB opr  
SUB opr  
SUB opr,X  
SUB opr,X  
SUB ,X  
IMM  
DIR  
EXT  
IX2  
IX1  
IX  
A0  
B0  
C0  
D0  
E0  
F0  
2
3
4
5
4
3
Subtract Memory Byte from Accumulator  
A (A) – (M)  
— — ↕ ↕ ↕  
PC (PC) + 1; Push (PCL)  
SP (SP) – 1; Push (PCH)  
SP (SP) – 1; Push (X)  
SP (SP) – 1; Push (A)  
SP (SP) – 1; Push (CCR)  
SP (SP) – 1; I 1  
SWI  
TAX  
Software Interrupt  
— 1 — — —  
— — — — —  
INH  
INH  
83  
97  
10  
2
PCH Interrupt Vector High Byte  
PCL Interrupt Vector Low Byte  
Transfer Accumulator to Index Register  
X (A)  
General Release Specification  
100  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Instruction Set  
Instruction Set  
Instruction Set Summary  
Table 10-6. Instruction Set Summary (Continued)  
Effect on  
Source  
Form  
CCR  
Operation  
Description  
H I N Z C  
dd  
ff  
TST opr  
TSTA  
TSTX  
TST opr,X  
TST ,X  
DIR  
INH  
INH  
IX1  
IX  
3D  
4D  
5D  
6D  
7D  
4
3
3
5
4
Test Memory Byte for Negative or Zero  
(M) – $00  
— — ↕ ↕ —  
TXA  
Transfer Index Register to Accumulator  
Stop CPU Clock and Enable Interrupts  
A (X)  
— — — — —  
— 0 — — —  
INH  
INH  
9F  
8F  
2
2
WAIT  
A
C
Accumulator  
Carry/borrow flag  
opr  
PC  
Operand (one or two bytes)  
Program counter  
CCR  
dd  
Condition code register  
Direct address of operand  
Direct address of operand and relative offset of branch instruction  
Direct addressing mode  
High and low bytes of offset in indexed, 16-bit offset addressing  
Extended addressing mode  
PCH Program counter high byte  
PCL  
REL  
rel  
rr  
SP  
X
Program counter low byte  
Relative addressing mode  
Relative program counter offset byte  
Relative program counter offset byte  
Stack pointer  
dd rr  
DIR  
ee ff  
EXT  
ff  
Offset byte in indexed, 8-bit offset addressing  
Half-carry flag  
Index register  
H
Z
Zero flag  
hh ll  
I
ii  
IMM  
INH  
IX  
IX1  
IX2  
M
High and low bytes of operand address in extended addressing  
Interrupt mask  
Immediate operand byte  
Immediate addressing mode  
Inherent addressing mode  
Indexed, no offset addressing mode  
Indexed, 8-bit offset addressing mode  
Indexed, 16-bit offset addressing mode  
Memory location  
#
Immediate value  
Logical AND  
Logical OR  
Logical EXCLUSIVE OR  
Contents of  
Negation (two’s complement)  
Loaded with  
( )  
–( )  
?
:
If  
Concatenated with  
Set or cleared  
N
Negative flag  
n
Any bit  
Not affected  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
101  
Instruction Set  
Table 10-7. Opcode Map  
Bit Manipulation Branch  
Read-Modify-Write  
Control  
Register/Memory  
DIR  
DIR  
REL  
DIR  
3
INH  
INH  
IX1  
IX  
7
INH  
INH  
IMM  
A
DIR  
B
EXT  
IX2  
IX1  
E
IX  
F
MSB  
LSB  
MSB  
LSB  
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0  
BSET0  
BRA  
NEG  
NEGA  
NEGX  
NEG  
NEG  
RTI  
SUB  
SUB  
SUB  
SUB  
SUB  
SUB  
CMP  
SBC  
CPX  
AND  
BIT  
0
1
0
3
DIR 2  
5
BRCLR0  
DIR 2  
5
BRSET1  
DIR 2  
5
BRCLR1  
DIR 2  
5
BRSET2  
DIR 2  
5
BRCLR2  
DIR 2  
5
BRSET3  
DIR 2  
5
BRCLR3  
DIR 2  
5
BRSET4  
DIR 2  
5
BRCLR4  
DIR 2  
5
BRSET5  
DIR 2  
5
BRCLR5  
DIR 2  
5
BRSET6  
DIR 2  
5
BRCLR6  
DIR 2  
5
BRSET7  
DIR 2  
5
REL 2  
3
DIR 1  
INH 1  
INH 2  
IX1 1  
IX 1  
INH  
6
RTS  
INH  
2
2
2
2
2
2
2
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
CMP  
IX2 2  
IX1 1  
4
CMP  
IX1 1  
IX  
3
BCLR0  
BRN  
CMP  
CMP  
CMP  
1
2
3
3
DIR 2  
5
REL  
3
1
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX  
3
11  
5
4
BSET1  
BHI  
MUL  
SBC  
SBC  
SBC  
SBC  
CPX  
AND  
BIT  
SBC  
CPX  
AND  
BIT  
2
DIR 2  
5
REL  
3
1
5
INH  
3
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
3
6
5
10  
SWI  
INH  
BCLR1  
BLS  
COM  
COMA  
COMX  
COM  
COM  
LSR  
CPX  
CPX  
CPX  
3
3
3
3
DIR 2  
5
REL 2  
3
DIR 1  
5
INH 1  
3
INH 2  
3
IX1 1  
6
IX 1  
5
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BSET2  
BCC  
LSR  
LSRA  
LSRX  
LSR  
AND  
AND  
AND  
4
4
DIR 2  
5
BCLR2 BCS/BLO  
REL 2  
3
DIR 1  
INH 1  
INH 2  
IX1 1  
6
IX  
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BIT  
BIT  
BIT  
5
5
3
3
DIR 2  
5
REL  
3
IMM 2  
2
DIR 3  
3
LDA  
DIR 3  
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
5
3
3
5
BSET3  
BNE  
ROR  
RORA  
RORX  
ROR  
IX1 1  
ROR  
ASR  
LDA  
LDA  
LDA  
STA  
EOR  
ADC  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
LDA  
STA  
EOR  
ADC  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
LDA  
STA  
6
6
DIR 2  
5
REL 2  
3
DIR 1  
5
INH 1  
3
INH 2  
3
IX  
5
IMM 2  
EXT 3  
5
IX2 2  
6
IX1 1  
5
IX  
4
6
2
4
BCLR3  
BEQ  
ASR  
ASRA  
ASRX  
ASR  
TAX  
STA  
STA  
7
7
3
3
DIR 2  
5
REL 2  
3
DIR 1  
5
INH 1  
3
INH 2  
3
IX1 1  
6
IX  
5
1
1
1
1
1
1
1
INH  
2
2
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BSET4  
BHCC  
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL  
CLC  
EOR  
EOR  
EOR  
EOR  
ADC  
ORA  
ADD  
JMP  
JSR  
LDX  
STX  
8
8
DIR 2  
5
REL 2  
3
DIR 1  
5
INH 1  
3
INH 2  
3
IX1 1  
6
IX  
5
INH 2  
2
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BCLR4  
BHCS  
ROL  
ROLA  
ROLX  
ROL  
ROL  
DEC  
SEC  
ADC  
ADC  
ADC  
9
9
3
3
DIR 2  
5
REL 2  
3
DIR 1  
5
INH 1  
3
INH 2  
3
IX1 1  
6
IX  
5
INH 2  
2
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BSET5  
BPL  
DEC  
DECA  
DECX  
DEC  
CLI  
SEI  
ORA  
ORA  
ORA  
A
B
C
D
E
F
A
B
C
D
E
F
DIR 2  
5
REL 2  
3
DIR 1  
INH 1  
INH 2  
IX1 1  
IX  
INH 2  
2
IMM 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
BCLR5  
BMI  
ADD  
ADD  
ADD  
3
3
DIR 2  
5
REL  
3
INH 2  
2
IMM 2  
DIR 3  
2
EXT 3  
3
IX2 2  
4
IX1 1  
3
IX  
2
5
3
3
6
5
BSET6  
BMC  
INC  
INCA  
INCX  
INC  
TST  
INC  
TST  
RSP  
INH  
JMP  
JMP  
DIR 2  
5
REL 2  
3
DIR 1  
4
INH 1  
3
INH 2  
3
IX1 1  
5
IX  
4
2
6
DIR 3  
5
EXT 3  
6
IX2 2  
7
IX1 1  
6
IX  
5
2
BCLR6  
BMS  
TST  
TSTA  
TSTX  
NOP  
BSR  
JSR  
JSR  
3
3
DIR 2  
5
REL 2  
3
DIR 1  
INH 1  
INH 2  
IX1 1  
IX  
INH 2  
REL 2  
2
DIR 3  
3
EXT 3  
4
IX2 2  
5
IX1 1  
4
IX  
3
2
BSET7  
BIL  
STOP  
LDX  
LDX  
LDX  
DIR 2  
5
DIR 2  
5
BCLR7  
DIR 2  
REL  
3
BIH  
REL 2  
1
INH  
2
WAIT  
INH 1  
2
2
IMM 2  
DIR 3  
4
EXT 3  
5
STX  
EXT 3  
IX2 2  
6
IX1 1  
5
IX  
4
5
3
3
6
5
BRCLR7  
CLR  
DIR 1  
CLRA  
INH 1  
CLRX  
INH 2  
CLR  
CLR  
TXA  
INH  
STX  
3
DIR 2  
IX1 1  
IX 1  
2
DIR 3  
IX2 2  
IX1 1  
IX  
MSB  
INH = Inherent  
IMM = Immediate  
DIR = Direct  
REL = Relative  
IX = Indexed, No Offset  
IX1 = Indexed, 8-Bit Offset  
IX2 = Indexed, 16-Bit Offset  
MSB of Opcode in Hexadecimal  
Number of Cycles  
0
LSB  
5
BRSET0 Opcode Mnemonic  
DIR Number of Bytes/Addressing Mode  
LSB of Opcode in Hexadecimal  
0
EXT = Extended  
3
Ele c tric a l Sp e c ific a tions  
11.3 Ma xim um Ra ting s  
Maximum ratings are the extreme limits to which the MCU can be  
exposed without permanently damaging it.  
The MCU contains circuitry to protect the inputs against damage from  
high static voltages; however, do not apply voltages higher than those  
shown in the table below. Keep VIN and VOUT within the range  
VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate  
voltage level, either VSS or VDD.  
Rating  
Symbol  
Value  
Unit  
Supply Voltage  
V
–0.3 to +7.0  
V
DD  
V
–0.3  
SS  
Burn-In Mode (IRQ Pin Only)  
V
to  
V
IN  
2 x V + 0.3  
DD  
Current Drain Per Pin Excluding V and V  
I
25  
mA  
°C  
DD  
SS  
Operating Junction Temperature  
Storage Temperature Range  
T
+150  
J
T
–65 to +150  
°C  
stg  
NOTE: This device is not guaranteed to operate properly at the maximum  
DC Electrical Characteristics (2.2 Vdc) for guaranteed operating  
conditions.  
General Release Specification  
104  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Electrical Specifications  
 
Electrical Specifications  
Operating Range  
11.4 Op e ra ting Ra ng e  
Characteristic  
Symbol  
Value  
T to T  
Unit  
Operating Temperature Range  
MC68HC05RC16 (Standard)  
L
H
T
°C  
A
0 to +70  
11.5 The rm a l Cha ra c te ristic s  
Characteristic  
Thermal Resistance  
Symbol  
Value  
Unit  
Plastic Dual In-Line Package  
Small Outline Intergrated Circuit Package  
Plastic Leaded Chip Carrier Package  
60  
60  
60  
θ
°C/W  
JA  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
105  
Electrical Specifications  
   
Ele c tric a l Sp e c ific a tions  
11.6 DC Ele c tric a l Cha ra c te ristic s (5.0 Vd c )  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
Output Voltage  
ILOAD = 10.0 µA  
ILOAD = –10.0 µA  
VOL  
VOH  
VDD– 0.1  
0.1  
V
Output High Voltage  
(ILOAD –2.0 mA) Port A, Port B, Port C (1–7)  
(ILOAD –20 mA) IRO  
(ILOAD –4.0 mA) Port C (Bit 0)  
VDD –0.8  
VDD –0.8  
VDD –0.8  
VDD –0.2  
VDD –0.2  
VDD –0.2  
VOH  
V
V
Output Low Voltage  
(ILOAD = 3.0 mA) Port A, Port B, Port C (1–7)  
(ILOAD = 25.0 mA) IRO  
0.2  
0.2  
0.2  
0.4  
0.4  
0.4  
VOL  
(ILOAD = 20.0 mA) Port C (Bit 0)  
Input High Voltage  
Port A, Port B, Port C, IRQ, RESET,  
LPRST, OSC1  
VIH  
VIL  
0.7 x VDD  
VDD  
V
V
Input Low Voltage  
Port A, Port B, Port C, IRQ, RESET,  
LPRST, OSC1  
VSS  
0.2 x VDD  
Supply Current (see Notes)  
Run  
Wait  
Stop  
25 C  
0 to +70 C  
2.3  
0.5  
4.0  
1.0  
mA  
mA  
IDD  
IOZ  
IIN  
o
0.3  
0.3  
10.0  
20.0  
µA  
µA  
o
I/O Ports Hi-Z Leakage Current  
Port A, Port B, Port C  
–10  
10  
µA  
Input Current  
RESET, LPRST, IRQ, OSC1  
PB0–PB7 with Pullups Enabled  
(V = 0.2 x V  
PB0–PB7 with Pullups Enabled  
(V = 0.7 x V  
–1  
1
µA  
8
)
–100  
–50  
–330  
–120  
–700  
–300  
IN  
DD  
)
DD  
IN  
Capacitance  
Ports (as Input or Output)  
RESET, LPRST, IRQ  
COUT  
CINT  
12  
8
pF  
NOTES:  
1.  
2. Typical values at midpoint of voltage range, 25 °C only, represent average measurements.  
3. Wait I : only core timer active  
V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = 0 °C to +70 °C, unless otherwise noted  
DD SS  
A
DD  
4. Run (Operating) I , wait I : Measured using external square wave clock source (fOsc = 4.2 MHz); all inputs 0.2 V  
DD  
DD  
from rail; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2  
L
5. Wait, Stop I : Port A and port C configured as inputs, port B configured as outputs, V = 0.2 V, V = V –0.2 V  
DD  
IL  
IH  
DD  
6. Stop I is measured with OSC1 = V  
.
SS  
DD  
7. Wait I is affected linearly by the OSC2 capacitance.  
DD  
8. Pullups are designed to be capable of pulling to V within 1 µs for a 100 pF, 4-kload.  
IH  
General Release Specification  
106  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Electrical Specifications  
 
Electrical Specifications  
DC Electrical Characteristics (2.2 Vdc)  
11.7 DC Ele c tric a l Cha ra c te ristic s (2.2 Vd c )  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
Output Voltage  
ILOAD = 10.0 µA  
ILOAD = –10.0 µA  
VOL  
VOH  
VDD– 0.1  
0.1  
V
Output High Voltage  
(ILOAD –0.6 mA) Port A, Port B, Port C (1–7)  
(ILOAD –8.0 mA) IRO  
(ILOAD –1.2 mA) Port C (Bit 0)  
VDD– 0.3  
VDD– 0.3  
VDD– 0.3  
VDD– 0.1  
VDD– 0.1  
VDD– 0.1  
VOH  
V
V
Output Low Voltage  
(ILOAD = 1.0 mA) Port A, Port B, Port C (1–7)  
(ILOAD = 8.0 mA) IRO  
0.1  
0.1  
0.1  
0.3  
0.3  
0.3  
VOL  
(ILOAD = 7.0 mA) Port C (Bit 0)  
Input High Voltage  
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1  
0.7 x  
VDD  
VIH  
VIL  
VDD  
V
V
Input Low Voltage  
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1  
VSS  
0.4 x VDD  
Supply Current (see Notes)  
Run  
Wait  
Stop  
25 C  
0 to +70 C  
0.3  
0.15  
1.0  
0.3  
mA  
mA  
IDD  
IOZ  
IIN  
o
0.1  
0.1  
1.0  
4.0  
µA  
µA  
o
I/O Ports Hi-Z Leakage Current  
Port A, Port B, Port C  
–4  
4
µA  
Input Current  
RESET, LPRST, IRQ, OSC1  
PB0–PB7 with Pullups Enabled  
–0.4  
–25  
–15  
0.4  
–105  
–65  
µA  
8
(V = 0.4 x V  
)
–50  
–34  
IN  
DD  
PB0–PB7 with Pullups Enabled  
(V = 0.7 x V  
)
DD  
IN  
Capacitance  
Ports (as Input or Output)  
RESET, LPRST, IRQ  
COUT  
CINT  
12  
8
pF  
NOTES:  
1.  
2. Typical values at midpoint of voltage range, 25 °C only, represent average measurements.  
3. Wait I : only core timer active  
V
= 2.2 Vdc ± 10%, V = 0 Vdc, T = 0 °C to +70 °C, unless otherwise noted  
DD SS  
A
DD  
4. Run (Operating) I , wait I : Measured using external square wave clock source (fOsc = 4.2 MHz); all inputs 0.2 V  
DD  
DD  
from rail; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2  
L
5. Wait, Stop I : Port A and port C configured as inputs, port B configured as outputs, V = 0.2 V, V = V –0.2 V  
DD  
IL  
IH  
DD  
6. Stop I is measured with OSC1 = V  
.
DD  
SS  
7. Wait I is affected linearly by the OSC2 capacitance.  
DD  
8. Pullups are designed to be capable of pulling to V within 25 µs for a 100 pF, 4-kload.  
IH  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
107  
Electrical Specifications  
 
Ele c tric a l Sp e c ific a tions  
4.0  
3.0  
2.0  
1.0  
V
= 5.5 V  
DD  
T = –0 °C to 70 °C  
A
STOP I (20 µA)  
DD  
0
0
0.5  
1.0  
1.5  
2.0  
2.1  
2.5  
INTERNAL CLOCK FREQUENCY (MHz)  
XTAL ÷ 2  
1.0  
0.8  
0.6  
V
= 2.4 V  
DD  
T = –0 °C to 70 °C  
A
0.4  
0.3  
0.2  
STOP I (4 µA)  
DD  
0
0
0.5  
1.0  
1.5  
2.0  
2.1  
2.5  
INTERNAL CLOCK FREQUENCY (MHz)  
XTAL ÷ 2  
Figure 11-1. Maximum Supply Current versus Internal Clock Frequency  
General Release Specification  
108  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Electrical Specifications  
Electrical Specifications  
Control Timing (5.0 Vdc and 2.2 Vdc)  
11.8 Control Tim ing (5.0 Vd c a nd 2.2 Vd c )  
Characteristic  
Symbol  
Min  
Max  
Unit  
Frequency of Operation  
Crystal  
External Clock  
f
dc  
4.2  
4.2  
MHz  
osc  
Internal Operating Frequency  
Crystal (fOSC /2)  
External Clock (fOSC /2)  
f
dc  
2.1  
2.1  
MHz  
op  
Cycle Time  
t
480  
100  
100  
ns  
ms  
ms  
cyc  
Crystal Oscillator Startup Time  
Stop Recovery Startup Time (Crystal Oscillator)  
RESET Pulse Width  
t
OXOV  
t
ILCH  
t
1.5  
t
cyc  
RL  
Interrupt Pulse Width Low (Edge-Triggered)  
Interrupt Pulse Period  
t
125  
Note 2  
90  
ns  
ILIH  
t
t
cyc  
ILIL  
OSC1 Pulse Width  
t
, t  
ns  
OH OL  
NOTES:  
o
o
1. VDD = 2.0 to 5.5 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted  
2. The minimum period, tILI, should not be less than the number of cycle times it takes to execute the interrupt service  
routine plus 19 tCYC  
.
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
109  
Electrical Specifications  
 
Ele c tric a l Sp e c ific a tions  
General Release Specification  
110  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Electrical Specifications  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 12. Me c ha nic a l Sp e c ific a tions  
12.1 Conte nts  
12.3 28-Pin Plastic Dual-In-Line Package  
12.4 28-Pin Small Outline Integrated Circuit Package  
12.5 44-Pin Plastic Leaded Chip Carrier Package  
12.2 Introd uc tion  
This section describes the dimensions of the dual-in-line package (DIP),  
small outline integrated circuit (SOIC), and plastic leaded chip carrier  
(PLCC) MCU packages.  
The following figures show the latest packages at the time of this  
publication. To make sure that you have the latest package  
specifications, contact one of the following:  
• Local Motorola Sales Office  
• Motorola Mfax  
– Phone 602-244-6609  
– EMAIL [email protected]  
• Worldwide Web (wwweb) at http://design-net.com  
Follow Mfax or wwweb on-line instructions to retrieve the current  
mechanical specifications.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Mechanical Specifications  
111  
 
Me c ha nic a l Sp e c ific a tions  
12.3 28-Pin Pla stic Dua l In-Line Pa c ka g e (Ca se 710-02)  
NOTES:  
1. POSITIONAL TOLERANCE OF LEADS (D),  
SHALL BE WITHIN 0.25mm (0.010) AT  
MAXIMUM MATERIAL CONDITION, IN  
RELATION TO SEATING PLANE AND  
EACH OTHER.  
28  
1
15  
14  
2. DIMENSION  
WHEN FORMED PARALLEL.  
3. DIMENSION DOES NOT INCLUDE  
MOLD FLASH.  
L
TO CENTER OF LEADS  
B
B
MILLIMETERS  
MIN MAX  
INCHES  
MIN MAX  
DIM  
A
B
C
D
F
36.45 37.21  
13.72 14.22  
1.435 1.465  
0.540 0.560  
0.155 0.200  
0.014 0.022  
0.040 0.060  
L
A
C
3.94  
0.36  
1.02  
5.08  
0.56  
1.52  
N
G
H
J
2.54 BSC  
0.100 BSC  
0.065 0.085  
0.008 0.015  
0.115 0.135  
1.65  
0.20  
2.92  
2.16  
0.38  
3.43  
J
H
G
K
L
M
K
SEATING  
PLANE  
15.24 BSC  
0.600 BSC  
F
D
0°  
0.51  
15°  
1.02  
0°  
0.020 0.040  
15°  
M
N
12.4 28-Pin Sm a ll Outline Inte g ra te d Circ uit Pa c ka g e (Ca se 751F-04)  
-A-  
NOTES:  
28  
1
15  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION  
PROTRUSION.  
14X P  
M
-B-  
0.010 (0.25M)  
B
A
AND  
B
DO NOT INCLUDE MOLD  
4. MAXIMUM MOLD PROTRUSION 0.15  
(0.006) PER SIDE.  
14  
5. DIMENSION  
DAMBAR PROTRUSIONA. LLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.13  
(0.005) TOTAL IN EXCESS OF  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
D
DOES NOT INCLUDE  
28X D  
D
M
0.010 (0.25M)  
T
S
A
S
B
R X 45°  
MILLIMETERS  
MIN MAX  
17.80 18.05  
INCHES  
MIN MAX  
C
DIM  
A
-T-  
0.701 0.711  
0.292 0.299  
0.093 0.104  
0.014 0.019  
0.016 0.035  
0.050 BSC  
-T-  
SEATING  
PLANE  
B
7.40  
2.35  
0.35  
0.41  
7.60  
2.65  
0.49  
0.90  
26X G  
C
D
K
F
F
G
J
1.27 BSC  
0.23  
0.13  
0.32  
0.29  
8°  
0.009 0.013  
0.005 0.011  
J
K
M
P
0°  
0°  
0.395 0.415  
8°  
10.05 10.55  
R
0.25  
0.75  
0.010 0.029  
General Release Specification  
112  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Mechanical Specifications  
   
Mechanical Specifications  
44-Pin Plastic Leaded Chip Carrier Package (Case 777-02)  
12.5 44-Pin Pla stic Le a d e d Chip Ca rrie r Pa c ka g e (Ca se 777-02)  
M
S
S
0.007(0.180)  
T
L-M  
N
B
D
-N-  
YBRK  
-M-  
M
S
S
0.007(0.180)  
T
L-M  
N
U
Z
-L-  
V
X
G1  
W
D
44  
1
S
S
S
0.010 (0.25)  
T
L-M  
N
VIEW D-D  
M
M
S
S
S
S
A
R
0.007(0.180)  
0.007(0.180)  
T
T
L-M  
L-M  
N
N
M
S
S
0.007(0.180)  
T
L-M  
N
H
Z
J
K1  
E
0.004 (0.10)  
G
K
C
SEATING  
PLANE  
-T-  
G1  
F
VIEW S  
S
S
S
M
S
S
0.010 (0.25)  
T
L-M  
N
0.007(0.180)  
T
L-M  
N
VIEW S  
NOTES:  
INCHES  
MILLIMETERS  
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED  
WHERE TOP OF LEAD SHOLDERS EXITS  
PLASTIC BODY AT MOLD PARTING LINE.  
2. DIMENSION G1, TRUE POSITION TO BE  
MEASURED AT DATUM -T-, SEATING PLANE.  
3. DIMENSION R AND U DO NOT INCLUDE MOLD  
FLASH. ALLOWABLE MOLD FLASH IS 0.010  
(0.25) PER SIDE.  
DIM  
MIN  
MAX  
MIN  
17.40  
17.40  
4.20  
MAX  
17.65  
17.65  
4.57  
A
B
C
E
0.685  
0.685  
0.165  
0.090  
0.013  
0.695  
0.695  
0.180  
0.110  
0.019  
2.29  
2.79  
F
0.33  
0.48  
4. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
5. CONTROLLING DIMENSION: INCH.  
G
H
J
K
R
U
V
W
X
Y
0.050 BSC  
1.27 BSC  
0.026  
0.020  
0.025  
0.650  
0.650  
0.042  
0.042  
0.042  
0.032  
0.66  
0.51  
0.81  
6. THE PACKAGE TOP MAY BE SMALLER THAN  
THE PACKAGE BOTTOM BY UP TO 0.012  
(0.300). DIMENSIONS R AND U ARE DETERMINED  
AT THE OUTERMOST EXTREMES OF THE  
PLASTIC BODY EXCLUSIVE OF THE MOLD  
FLASH, TIE BAR BURRS, GATE BURRS AND  
INTERLEAD FLASH, BUT INCLUDING ANY  
MISMATCH BETWEEN THE TOP AND BOTTOM  
OF THE PLASTIC BODY.  
7. DIMINSION H DOES NOT INCLUDE DAMBAR  
PROTRUSION OR INTRUSION. THE DAMBAR  
PROTUSION(S) SHALL NOT CAUSE THE H  
DIMINSION TO BE GREATER THAN 0.037  
(0.940114). THE DAMBAR INTRUSION(S) SHALL  
NOT CAUSE THE H DIMINISION TO SMALLER  
THAN 0.025 (0.635).  
0.64  
0.656  
0.656  
0.048  
0.048  
0.056  
0.020  
10°  
16.51  
16.51  
1.07  
1.07  
1.07  
16.66  
16.66  
1.21  
1.21  
1.42  
0.50  
10°  
2°  
2°  
15.50  
1.02  
Z
G1  
K1  
0.610  
0.630  
16.00  
0.040  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
113  
Mechanical Specifications  
 
Me c ha nic a l Sp e c ific a tions  
General Release Specification  
114  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Mechanical Specifications  
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Se c tion 13. Ord e ring Inform a tion  
13.1 Conte nts  
13.2 Introd uc tion  
This section contains ordering instructions for the MC68HC705RC16.  
13.3 MCU Ord e ring Form s  
To initiate an order for a ROM-based MCU, first obtain the current  
ordering form for the MCU from a Motorola representative. Submit the  
following items when ordering MCUs:  
• A current MCU ordering form that is completely filled out  
(Contact your Motorola sales office for assistance.)  
• A copy of the customer specification if the customer specification  
deviates from the Motorola specification for the MCU  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
Ordering Information  
115  
   
Ord e ring Inform a tion  
The current MCU ordering form is also available through the Motorola  
Freeware Bulletin Board Service (BBS). The telephone number is (512)  
891-FREE. After making the connection, type bbs in lower-case letters.  
Then press the return key to start the BBS software.  
13.4 Ap p lic a tion Prog ra m Me d ia  
Please deliver the application program to Motorola in one of the following  
media:  
1
• Macintosh 3 1/2-inch diskette (double-sided 800K or  
double-sided high-density 1.4 M)  
2
• MS-DOS or PC-DOSTM3 3 1/2-inch diskette (double-sided  
720 K or double-sided high-density 1.44 M)  
• MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided double-  
density 360 K or double-sided high-density 1.2 M)  
Use positive logic for data and addresses.  
When submitting the application program on a diskette, clearly label the  
diskette with the following information:  
• Customer name  
• Customer part number  
• Project or product name  
• File name of object code  
• Date  
• Name of operating system that formatted diskette  
• Formatted capacity of diskette  
On diskettes, the application program must be in Motorola’s S-record  
format (S1 and S9 records), a character-based object file format  
generated by M6805 cross assemblers and linkers.  
1. Macintosh is a registered trademark of Apple Computer, Inc.  
2. MS-DOS is a registered trademark of Microsoft Corporation.  
3. PC-DOS is a trademark of International Business Machines Corporation.  
General Release Specification  
116  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Ordering Information  
 
Ordering Information  
ROM Program Verification  
NOTE: Begin the application program at the first user ROM location. Program  
addresses must correspond exactly to the available on-chip user ROM  
addresses as shown in the memory map. Write $00 in all nonuser ROM  
locations or leave all nonuser ROM locations blank. Refer to the current  
MCU ordering form for additional requirements. Motorola may request  
pattern re-submission if nonuser areas contain any nonzero code.  
If the memory map has two user ROM areas with the same address,  
then write the two areas in separate files on the diskette. Label the  
diskette with both file names.  
In addition to the object code, a file containing the source code can be  
included. Motorola keeps this code confidential and uses it only to  
expedite ROM pattern generation in case of any difficulty with the object  
code. Label the diskette with the file name of the source code.  
13.5 ROM Prog ra m Ve rific a tion  
The primary use for the on-chip ROM is to hold the customer’s  
application program. The customer develops and debugs the application  
program and then submits the MCU order along with the application  
program.  
Motorola inputs the customer’s application program code into a  
computer program that generates a listing verify file. The listing verify file  
represents the memory map of the MCU. The listing verify file contains  
the user ROM code and may also contain nonuser ROM code, such as  
self-check code. Motorola sends the customer a computer printout of the  
listing verify file along with a listing verify form.  
To aid the customer in checking the listing verify file, Motorola will  
program the listing verify file into customer-supplied blank preformatted  
Macintosh or DOS disks. All original pattern media are filed for  
contractual purposes and are not returned.  
Check the listing verify file thoroughly, then complete and sign the listing  
verify form and return the listing verify form to Motorola. The signed  
listing verify form constitutes the contractual agreement for the creation  
of the custom mask.  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
General Release Specification  
117  
Ordering Information  
 
Ord e ring Inform a tion  
13.6 ROM Ve rific a tion Units (RVUs)  
After receiving the signed listing verify form, Motorola manufactures a  
custom photographic mask. The mask contains the customer’s  
application program and is used to process silicon wafers. The  
application program cannot be changed after the manufacture of the  
mask begins. Motorola then produces 10 MCUs, called RVUs, and  
sends the RVUs to the customer. RVUs are usually packaged in  
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are  
not tested to environmental extremes because their sole purpose is to  
demonstrate that the customer’s user ROM pattern was properly  
implemented. The 10 RVUs are free of charge with the minimum order  
quantity. These units are not to be used for qualification or production.  
RVUs are not guaranteed by Motorola Quality Assurance.  
13.7 MC Ord e r Num b e rs  
Table 13-1 provides information in determing order numbers.  
Table 13-1. MC Order Numbers  
Operating  
Temperature  
Range  
Package Type  
MC Order Number  
28-Pin Plastic Dual In-Line  
Package (DIP)  
MC68HC05RC8P  
MC68HC05RC16P  
0 to 70 °C  
0 to 70 °C  
0 to 70 °C  
28-Pin Small Outline Integrated Circuit  
Package (SOIC)  
MC68HC05RC8DW  
MC68HC05RC16DW  
44-Pin Plastic Leaded Chip  
Carrier (PLCC)  
MC68HC05RC8FN  
MC68HC05RC16FN  
General Release Specification  
118  
MC68HC05RC16 — Rev. 3.0  
MOTOROLA  
Ordering Information  
     
Ge ne ra l Re le a se Sp e c ific a tion MC68HC05RC16  
Ap p e nd ix A. MC68HC05RC8  
A.1 Conte nts  
A.2 Introd uc tion  
Appendix A introduces the MC68HC05RC8. The technical data applying  
to the MC68HC05RC16 applies to the MC68HC05RC8 with the  
exceptions given in this appendix.  
A.3 Me m ory Ma p  
Both the MC68HC05RC8 and the MC68HC05RC16 have 16-Kbyte  
memory maps consisting of user ROM, RAM, burn-in ROM, and  
input/output (I/O). However, the user ROM for the MC68HC05RC8  
consists of only 8112 bytes of ROM.  
Figure A-1 shows the MC68HC05RC8 memory map in user mode.  
MC68HC05RC16 Rev. 3.0  
MOTOROLA  
General Release Specification  
MC68HC05RC8  
119  
   
MC68HC05RC8  
$0000  
0000  
PORT A DATA REGISTER  
PORT B DATA REGISTER  
PORT C DATA REGISTER  
RESERVED  
$00  
$01  
$02  
$03  
$04  
$05  
I/O  
32 BYTES  
$001F  
$0020  
0031  
0032  
RAM  
160 BYTES  
PORT A DATA DIRECTION REGISTER  
PORT B DATA DIRECTION REGISTER  
$00BF  
$00C0  
0191  
0192  
STACK  
64 BYTES  
PORT C DATA DIRECTION REGISTER $06  
RESERVED  
CORE TIMER CONTROL & STATUS REG. $08  
$00FF  
$0100  
0255  
0256  
$07  
RAM  
128 BYTES  
$017F  
$0180  
0383  
0384  
CORE TIMER COUNTER REGISTER  
RESERVED  
$09  
$0A  
UNUSED  
$1FFF  
$2000  
USER ROM  
8112 BYTES  
$0F  
RESERVED  
$3FAF  
$3FB0  
16303  
16304  
$10  
$11  
IR TIMER CHR1  
IR TIMER CLR1  
BURN-IN ROM  
& VECTORS  
64 BYTES  
IR TIMER CHR2  
IR TIMER CLR2  
IR TIMER MCSR  
$12  
$3FEF  
$3FF0  
16367  
16368  
$13  
$14  
USER VECTORS  
16 BYTES  
$15  
IR TIMER MDR1  
IR TIMER MDR2  
IR TIMER MDR3  
RESERVED  
$3FFF  
16383  
$16  
$17  
$18  
RESERVED  
RESERVED  
$1E  
$1F  
$3FF0  
UNUSED  
UNUSED  
$3FF5  
$3FF6  
CORE TIMER VECTOR (HIGH BYTE)  
CORE TIMER VECTOR (LOW BYTE)  
IR TIMER VECTOR (HIGH BYTE)  
$3FF7  
$3FF8  
IR TIMER VECTOR (LOW BYTE)  
$3FF9  
$3FFA  
IRQ/PTB KEYSCAN PULLUPS  
VECTOR (HIGH BYTE)  
IRQ/PTB KEYSCAN PULLUPS  
VECTOR (LOW BYTE)  
$3FFB  
SWI VECTOR (HIGH BYTE)  
SWI VECTOR (LOW BYTE)  
RESET VECTOR (HIGH BYTE)  
RESET VECTOR (LOW BYTE)  
$3FFC  
$3FFD  
$3FFE  
$3FFF  
Figure A-1. MC68HC05RC8 Memory Map  
General Release Specification  
120  
MC68HC05RC16 Rev. 3.0  
MOTOROLA  
MC68HC05RC8  
 
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its  
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,  
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different  
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.  
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems  
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a  
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,  
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the  
design or manufacture of the part. Motorola and  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.  
How to reach us:  
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.1-800-441-2447 or  
602-303-5454  
MFAX: [email protected] – TOUCHTONE 602-244-6609  
INTERNET: http://Design-NET.com  
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan.  
03-81-3521-8315  
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298  
HC05RC16GRS/D  

Jenn Air JED8430BDS User Manual
Jenn Air PRO STYLE JGCP636ADP User Manual
JVC AV 21JT5EU User Manual
KitchenAid KECC507GWH1 User Manual
Logitech Logicool Compact Keyboard K300 User Manual
Magnavox 27MT5005D User Manual
NEC XV29 Plus User Manual
Panasonic CT 27D20 User Manual
Panasonic CT 32SL13 CT 32SC13 CT 36SC13 CT 3653 User Manual
Philips DVP3588X User Manual