Intel E7520 User Manual

®
®
Dual-Core Intel Xeon processor LV  
®
®
with Intel E7520 Chipset and Intel  
6300ESB ICH Development Kit  
User’s Manual  
April 2007  
Order Number: 311274-009  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Contents  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
3
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figures  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
4
April 2007  
Order Number: 311274-009  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Tables  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
5
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Revision History  
Date  
Revision  
Description  
Section 2.6.9 updated to clarify that video card is not included in the kit.  
Section 2.3 updated to remove the reference to the Blue stand and add the standoffs.  
Section 2.6.11 added safety warning.  
April 2007  
009  
Section 3 updated with correct part number for CPU heat sink fan.  
March 2007  
February 2007  
December 2006  
December 2006  
October 2006  
May 2006  
008  
007  
006  
005  
004  
003  
001  
Updates to Chapter 2.0, “Getting Started” to include safety warnings.  
Minor updates.  
Update for Intel® Celeron® 1.83 GHz processor launch.  
Update for Dual-Core Intel® Xeon® processor LV 2.16 GHz (dual-processor capable) launch.  
Update for product launch.  
Chapter 6: changed jumper descriptions/comments  
Initial public release.  
March 2006  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
6
April 2007  
Order Number: 311274-009  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
1.0  
About This Manual  
This manual describes how to set up and use the evaluation board and other  
®
®
®
components included in your Dual-Core Intel Xeon processor LV with Intel E7520  
®
Chipset and Intel 6300ESB ICH Development Kit.  
1.1  
Content Overview  
Chapter 1.0, “About This Manual” – Description of conventions used in this manual and  
instructions for obtaining literature and contacting customer support.  
Chapter 2.0, “Getting Started” – Complete instructions on how to configure the  
evaluation board and processor assembly by setting jumpers, connecting peripherals,  
providing power, and configuring the BIOS.  
Chapter 3.0, “Theory of Operation” – Information on the system design.  
Chapter 4.0, “Platform Management” – Description of jumper settings and functions,  
and pinout information for each connector.  
Chapter 5.0, “Driver and OS Support” – List of supported drivers and operating  
systems.  
Chapter 6.0, “Hardware Reference” – Reference information on the hardware, including  
locations of evaluation board components, connector pinout information, and jumper  
settings.  
Chapter 7.0, “Board Setup Checklist” – Checklist of items to ensure proper functionality  
of the evaluation board.  
Chapter 8.0, “Debug Procedure” – Debug procedure to determine baseline functionality  
for the Development Kit.  
1.2  
Text Conventions  
The following notations may be used throughout this manual:  
# - The pound symbol (#) appended to a signal name indicates that the signal is active  
low.  
Variables - Variables are shown in italics. Variables must be replaced with correct  
values.  
Instructions - Instruction mnemonics are shown in uppercase. When you are  
programming, instructions are not case-sensitive. You may use either upper- or  
lowercase.  
Numbers - Hexadecimal numbers are represented by a string of hexadecimal digits  
followed by the character “h”. A zero prefix is added to numbers that begin with A  
through F. For example, FF is shown as 0FFh. Decimal and binary numbers are  
represented by their customary notations. That is, 255 is a decimal number and 1111  
1111 is a binary number. In some cases, the character “b” is added for clarity.  
Signal Names - Signal names are shown in uppercase. When several signals share a  
common name, an individual signal is represented by the signal name followed by a  
number, while the group is represented by the signal name followed by a variable (n).  
For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on;  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
7
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
they are collectively called CSn#. A pound symbol (#) appended to a signal name  
identifies an active-low signal. Port pins are represented by the port abbreviation, a  
period, and the pin number (e.g., P1.0).  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
8
April 2007  
Order Number: 311274-009  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Units of Measure The following abbreviations are used to represent units of measure:  
A
amps, amperes  
GByte, gigabytes  
gigahertz  
GB  
GHz  
KB  
ΚΩ  
mA  
MB  
MHz  
ms  
mW  
ns  
KByte, kilobytes  
kilo-ohms  
milliamps, milliamperes  
MByte, megabytes  
megahertz  
milliseconds  
milliwatts  
nanoseconds  
picofarads  
pF  
W
watts  
V
volts  
μA  
μF  
microamps, microamperes  
microfarads  
μs  
microseconds  
microwatts  
μW  
1.3  
Technical Support  
Support Services for your hardware and software are provided through the secure  
®
Intel Premier Support Web site at https://premier.intel.com. After you log on, you can  
obtain technical support, review “What’s New,and download any items required to  
maintain the platform.  
1.3.1  
1.3.2  
Electronic Support Systems  
Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date  
technical information and product support.  
Online Documents  
Product documentation is provided online in a variety of web-friendly formats at:  
1.3.3  
Additional Technical Support  
If you require additional technical support, please contact your field sales  
representative or local distributor.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
9
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
1.4  
Product Literature  
You can order product literature from the following Intel literature centers.  
U.S. and Canada  
U.S. (from overseas)  
Europe (U.K.)  
Germany  
1-800-548-4725  
708-296-9333  
44(0)1793-431155  
44(0)1793-421333  
44(0)1793-421777  
81(0)120-47-88-32  
France  
Japan (fax only)  
1.5  
Related Documents  
Table 1 is a partial list of the available collateral. For the full lists, contact your local  
Intel representative.  
Table 1.  
Related Documents  
Document  
Document Number  
Intel® 6300ESB I/O Controller Hub (ICH) Datasheet  
Intel® E7520 Memory Controller Hub (MCH) Datasheet  
Dual-Core Intel® Xeon® Processor LV and ULV Datasheet  
Intel® E7520 Memory Controller Hub (MCH) Specification  
Intel® E7520 Memory Controller Hub (MCH) Specifications Addendum  
Contact your Intel field  
representative for access.  
Intel® E7520 Memory Controller Hub (MCH) Specifications Embedded  
Addendum  
Embedded Voltage Regulator-Down (EmVRD) 11.0  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
10  
April 2007  
Order Number: 311274-009  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
2.0  
Getting Started  
®
®
®
This chapter identifies the Dual-Core Intel Xeon processor LV with Intel E7520  
®
Chipset and Intel 6300ESB ICH Development Kit’s key components, features and  
specifications. It also describes how to set up the board for operation.  
Note:  
This manual assumes you are familiar with basic concepts involved with installing and  
configuring hardware for a PC or server system.  
2.1  
Overview  
The Development Kit contains a baseboard with two Dual-Core Intel Xeon processors  
®
LV, Intel E7520 MCH, 6300ESB, and other system board components and peripheral  
connectors. Various software and documentation are also included in the kit.  
®
®
In addition to the included Dual-Core Intel Xeon processors LV 2.0 GHz processors,  
the following processors are also supported with this Development Kit:  
®
®
• Dual-Core Intel Xeon processor LV 1.66 GHz (dual-processor capable)  
®
®
• Dual-Core Intel Xeon processor ULV 1.66 GHz (dual-processor capable)  
®
• Celeron processor 1.66 GHz (uni-processor only)  
®
• Celeron processor 1.83 GHz (uni-processor only)  
If you wish to use one of these options instead of the included processors, please  
contact your Intel sales representative. You will be sent new processor(s) and will need  
to download the latest microcode updates and BIOS revision specific to your new  
processor(s). There are currently two versions of BIOS. One version supports the LV  
and ULV versions, while the other version supports Celeron version.  
Note:  
The evaluation board is shipped as an open system with standoffs allowing for  
maximum flexibility in changing hardware configuration and peripherals in a lab  
environment. Since the board is not in a protective chassis, the user is required to  
observe extra precautions when handling and operating the system. Some assembly is  
required before use.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
11  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
2.2  
Evaluation Board Features  
The evaluation board features are summarized below:  
• CPU  
Two Dual-Core Intel Xeon processors LV capable of 667 MHz Front Side Bus  
— On-board processor voltage regulators compatible with EmVRM11 Design Guide  
®
®
• Intel E7520 MCH and Intel 6300ESB ICH  
— Supports three PCI Express x8 slots  
— Four DDR2–400 DIMMs on two channels (8 slots total)  
• System I/O  
— From 6300ESB  
1 PCI 2.2 32/33 Slot  
2 PCI-X 66 MHz slots  
1 IDE connector  
2 Serial ATA connectors  
2 Serial ports  
4 USB 2.0 ports  
— Super I/O via LPC bus from the 6300ESB  
1 Floppy port  
1 Parallel port  
1 Serial port  
1 PS/2 port  
• ITP-XDP debug port  
• Port 80 7-segment LEDs  
• Board Form Factor - 13.3” x 14” for benchtop use  
2.3  
Included Hardware  
The following hardware is included in the Development Kit:  
Two Dual-Core Intel Xeon processors LV capable of 667 MHz Front Side Bus  
Two CPU heatsinks (pre-installed)  
• One ATX Power Supply  
• Pre-installed jumpers  
Two 512 Mbytes DDR2-400 DIMMs  
• Unformatted SATA Hard Drive  
• SATA cable  
• Intel Network Interface Card  
• Standoffs for board  
• FWH mounted and flashed with the BIOS  
2.4  
Software Key Features  
The software in the Development Kit was chosen to facilitate development of real-time  
applications based on the components used in the evaluation board. The software tools  
included are described in this section.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
12  
April 2007  
Order Number: 311274-009  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Drivers included:  
Windows  
Chipset INF Install Utility version 7.0.0.1019  
Optional Intel 6300ESB ICH chipset driver updates  
Linux Driver Packages  
RedHat* Enterprise Linux 3.0 Server driver updates  
Note:  
Software in the kit is provided free by the vendor and is only licensed for evaluation  
purposes.  
Refer to the documentation in your Development Kit for further details on any terms  
and conditions that may be applicable to the granted licenses. Customers using tools  
that work with other third party products must have licensed those products. Any  
targets created by those tools should also have appropriate licenses. Software included  
in the kit is subject to change.  
Refer to http://developer.intel.com/design/intarch/devkits for details on additional  
software from other third party vendors.  
2.4.1  
2.5  
AMIBIOS* for the Development Kit  
The evaluation board is pre-installed and licensed with a copy of AMIBIOS* from  
American Megatrends*.  
Before You Begin  
Table 2 presents the additional hardware you may need for your Development Kit.  
Warning:  
Do not install the power supply until all other installation steps have been completed.  
Table 2.  
Additional Hardware  
VGA Card and Monitor You can use any standard VGA or greater resolution monitor using a VGA card.  
Keyboard  
Mouse  
You can use a keyboard with a PS/2 style connector or adapter as well as USB.  
You can use a mouse with a PS/2 style connector or adapter as well as USB.  
You can connect up to two IDE and two SATA devices to the evaluation board.  
Hard Drives  
Floppy Drive  
(optional)  
You can connect a floppy drive to the connector on the evaluation board. No floppy  
drives or cables are included in the Development Kit.  
The evaluation board behaves much like a standard PC motherboard. Many PC-  
compatible peripherals can be attached and configured to work with the evaluation  
board. For example, you may want to install a sound card or additional network  
adapters. You are responsible for procuring and installing any drivers required for  
additional devices.  
Other Devices and  
Adapters  
2.6  
Setting up the Evaluation Board  
Once you have gathered the hardware described in Section 2.5, follow the steps below  
to set up your Development Kit. This manual assumes you are familiar with basic  
concepts involved with installing and configuring hardware for a PC or server system.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
13  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 1.  
Board before Installing Additional Hardware  
2.6.1  
Safety  
Ensure a safe work environment. Make sure you are in a static-free environment  
before removing any components from their anti-static packaging. The evaluation  
board is susceptible to electrostatic discharge, which may cause product failure or  
unpredictable operation.  
Caution:  
Connecting the wrong cable or reversing a cable may damage the evaluation board and  
may damage the device being connected. Since the board is not in a protective chassis,  
use caution when connecting cables to this product.  
Note:  
Review the document provided with the Development Kit titled “Important Safety and  
Regulatory Information. This document contains addition safety warnings and cautions  
that must be observed when using this development kit.  
2.6.2  
Package Contents  
Verify kit contents. Inspect the contents of your kit, and ensure that everything listed  
in Section 2.3 is included. Check for damage that may have occurred during shipment.  
Contact your sales representative if any items are missing or damaged.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
14  
April 2007  
Order Number: 311274-009  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Check jumper settings. Verify that the jumpers are set in their default state. Refer to  
Section 6.4 for detailed descriptions of all jumpers and their default settings indicated  
in bold.  
2.6.3  
Installed Hardware  
Verify installed hardware. Make sure the following hardware is populated on your  
evaluation board:  
Two Dual-Core Intel Xeon processors LV with heatsinks  
• BIOS FWH  
• Battery in holder  
Note:  
The CPU sockets have a screw locking mechanism. The socket has an indication to  
show if the CPU is locked in place.  
Caution:  
The above hardware should have been correctly installed at the factory. If components  
are not installed correctly, DO NOT power on the board. Correctly re-install the  
components before proceeding. If you suspect that any of the kit components have  
been damaged, contact your Intel field sales representative or local distributor for  
assistance.  
2.6.4  
Installing the Heatsinks for CPU(s) and MCH  
Heatsink Installation: In order for the board to operate properly, a heatsink must be  
installed on the processors and on the E7520 MCH. DO NOT power on board without a  
CPU thermal solution. Heatsinks may already come pre-installed on both CPU(s) and  
MCH. Please refer to this section if you need to remove or re-install the heatsinks.  
Tools Needed: Flat head screwdriver and Phillips head screwdriver  
Consumable Items Needed: Disposable towels and isopropyl alcohol  
Note:  
CPU heatsinks may be silver or copper in color.  
Table 3.  
Heatsink Information  
Quantity Per  
Board  
Heatsink  
Manufacturer  
Component  
Part Number  
Comments  
Dual-Core Intel®  
Active heatsink +  
back plate  
2
Cooler Master*  
Cooler Master  
P/N EEP-N41CS-I1-GP  
ECB-000208-01  
Xeon® processor LV  
E7520 MCH  
1
Active heatsink  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
15  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 2.  
Location for the CPU and MCH for Heatsink Installation  
Caution:  
Applying excess pressure may cause damage to the CPU.  
Note:  
Do not turn power on until the CPU thermal solution has been installed.  
2.6.5  
CPU Heatsink Installation  
This section details how to install the CPU heatsink. This section may not apply if the  
CPU heatsink is pre-installed on the board.  
Note:  
If the Thermal Interface Material (TIM) is scratched, scrape it off and replace with new  
material. If a replacement is needed, use a TIM with high thermal conductivity such as  
thermal grease or a phase change material. The gasket ensures the heatsink is sitting  
flat on the package.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
16  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 3.  
CPU Heatsink Top and Bottom View  
1. Make certain that the processor is firmly seated in the socket, and the package is  
secured using a flathead screwdriver. Note: This shows CPU1 populated. However  
for single CPU operation socket 0 should be populated.  
Figure 4.  
Processor in Socket and Package Secured  
z
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
17  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
2. Clean the top surface of the processor die with a clean towel and isopropyl alcohol  
(IPA).  
Figure 5.  
Clean Top of Processor Die  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
18  
April 2007  
Order Number: 311274-009  
 
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
3. Install the back plate to the bottom side of the PCB at the CPU location. Align the  
standoffs to the four mounting holes in the board.  
Note:  
There is a non-electrically conductive tape to hold the back plate in place until the  
heatsink is completely installed.  
Figure 6.  
Back Plate in Place  
4. Mount the heatsink to the CPU. Ensure the TIM and die have contact.  
Figure 7.  
Heatsink Mounted on CPU  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
19  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
5. Align the screws (4x at corners) to the threaded holes of the standoffs on the back  
plate. Using the Phillips head screwdriver, tighten the four screws in a diagonal  
manner (as shown in the diagram). Tighten each screw half of the screw length for  
A to B and follow by ¼ for C to D. Then tighten A to B until the screw hard stops  
and repeat for C to D. The screws are designed to compress the springs a  
predetermined amount.  
Figure 8.  
Screw Tightening Order  
6. Plug the fan connector to the fan pin header on the board.  
7. Repeat steps 1-6 for the second CPU heatsink (if applicable).  
Note:  
The heatsink removal process is the reverse of the installation procedure.  
2.6.6  
MCH Heatsink Installation  
This section may not apply if the MCH heatsink is pre-installed on the board. However,  
you may want to briefly look over the procedure to verify that the heatsink is properly  
installed and it has not been damaged in the packaging.  
Note:  
If the Thermal Interface Material (TIM) is scratched, scrape it off and replace with new  
material. Use a TIM with high thermal conductivity, such as thermal grease or phase  
change material.  
Figure 9.  
MCH Heatsink Top View  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
20  
April 2007  
Order Number: 311274-009  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
1. Clean the top surface of the MCH die with a clean towel and isopropyl alcohol (IPA).  
Clean Top of MCH Die  
Figure 10.  
2. Hook one end of the heatsink clip to one of the anchors located near the corner of  
the MCH. Securely hold the other end of the heatsink clip.  
Figure 11.  
Hook Heatsink Clip to First Anchor  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
21  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
3. Hold the clip firmly to the anchor to prevent the heatsink from moving. Attach the  
other end of the clip to the other anchor. Ensure that the heatsink is level with the  
MCH package.  
Figure 12.  
Hook Heatsink Clip to Second Anchor  
4. Plug the fan connector to the fan pin header on the board.  
Note:  
The heatsink removal process is the reverse of the installation procedure.  
2.6.7  
Installing Memory  
Your kit includes two 512 MByte registered ECC DIMMs. To install, ensure the tabs on  
the slot are open, or rotated outward from the slot. Line up the DIMM above the slot  
(the DIMM is keyed so that it only fits in the slot in one orientation). Firmly but carefully  
insert the DIMM into the slot until the tabs close. Repeat for all other DIMM and slots.  
Note:  
When populating both channels, always place identical DIMMs in sockets that have the  
same position on channel A and channel B (i.e., DIMM A2 should be identical to DIMM  
B2).  
Note:  
Populate DIMMs starting with the sockets farthest away from the MCH (DIMM slots A4  
and B4).  
Caution:  
Do NOT bend the board when installing memory. There are a large number of  
components near the memory slots and excessive board flex can lead to solder joint  
failure.  
Note:  
Refer to Section 3.3.3.  
2.6.8  
Installing Storage Devices  
There is one IDE connector on the evaluation board, which supports an IDE device. For  
a correct boot-up of the system, ensure that a hard drive is installed as the primary  
master. (Master/slave settings are determined by a jumper on each IDE device. Consult  
the device label/documentation to verify that the jumper is set correctly for any  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
22  
April 2007  
Order Number: 311274-009  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
configuration you choose.) A CD-ROM drive or additional hard drive may be installed as  
a primary slave device. Follow this procedure to install a hard drive on the evaluation  
board:  
1. Verify that the jumper on the hard drive is set correctly for single or master,  
depending on your configuration.  
2. Install the hard drive. This can be done using either the IDE or SATA.  
IDE Installation:  
a. Connect the short end of the IDE cable to the IDE connector J1K2 on the board.  
Ensure that the red line (pin one on the cable) is aligned with pin one of the  
connector indicated by an arrow.  
b. Connect the middle connector of the cable to the hard drive. Again, ensure that  
the red line, pin one on the cable, is aligned with pin one on the hard drive.  
Note:  
Failure to properly align the IDE cable may damage the evaluation board and/or the  
hard drive.  
SATA Installation:  
a. Connect one end of the SATA cable to the hard drive connection. Connect the  
other end to the SATA1 or SATA2 connector (J1F4 or J1G1, respectively) on the  
board.  
3. Connect a power connector from the power supply to the hard drive. The power  
connector on the SATA drive may have a plastic cover that will need to be removed.  
(Old style power connector is supported.)  
4. Install the CD-ROM drive (optional). A CD-ROM drive is not included in the kit and  
is not required, but you may find it useful in loading additional software. To install it  
on the evaluation board:  
a. Verify that the jumper on the CD-ROM drive is set for slave.  
b. Connect the unused end of the IDE cable to the CD-ROM drive. Ensure that the  
red line, pin one on the cable, is aligned with pin one of the CD-ROM drive  
connector, indicated by an arrow.  
c. Connect a large 4-pin power connector from the power supply to the CD-ROM  
drive.  
5. Install the floppy drive (optional). A floppy disk drive is not included in your kit and  
is not required, but you may find it useful in loading additional software. To install a  
floppy drive on the evaluation board:  
a. Connect the floppy cable to the floppy connector J1K1. Ensure that the red line  
(pin one on the cable) is aligned with pin one of the connector, indicated by an  
arrow.  
b. Connect the other end of the floppy cable to the floppy drive.  
c. Connect a power cable to the floppy drive. Ensure that the red line (pin one on  
the cable) is aligned with pin one on the floppy drive.  
2.6.9  
Connect the Video Card and Monitor  
Insert a video card into the appropriate slot. Connect the monitor cable and power to  
the video card port.  
Note:  
Monitor and video card are not included in this Development Kit.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
23  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
2.6.10  
Connect the Keyboard and Mouse  
Connect a PS/2 mouse and keyboard to the stacked PS/2 connector on the evaluation  
board. The bottom connector, often purple, is the keyboard connector and the top,  
often green, is the mouse connector. Alternatively, you may plug a USB keyboard and a  
USB mouse into the USB connectors on the evaluation board.  
Note:  
Keyboard and mouse are not included in this Development Kit.  
2.6.11  
Connect the Power Supply  
Caution:  
Measures must be taken to protect the unused DC connectors of the power supply from  
accidental contact to objects in the work area.  
Make sure the power supply is turned off and unplugged. Connect the two ATX power  
supply cables to connectors J2K2 and J6K2 on the evaluation board. Next, plug the  
power cord into the power supply and the wall. Then turn on the switch on the back of  
the power supply.  
2.6.12  
Power up the System  
Turn on the monitor and then turn on the evaluation board.  
Do not turn power on until both CPU thermal solutions have been installed.  
Note:  
Caution:  
Ensure that fan heatsink on the both processors are operational. If not, turn off the  
power immediately and verify that both fan heatsinks are connected to the board  
correctly (see Section 2.6.4). If the fan heatsink is not operating, contact your Intel  
field sales representative or local distributor.  
2.7  
Configuring the BIOS  
An AMI* BIOS is pre-loaded on the evaluation board. You may need to make changes  
to the BIOS to enable hard disks, floppy disks and other supported features. You may  
use the setup program to modify BIOS settings and control the special features of the  
system. Setup options are configured through a menu-driven user interface.  
On first boot-up of the system, you may want to use the BIOS setup program to verify  
the date/time and boot device. BIOS updates may periodically be posted to the Intel  
Developer web site at http://developer.intel.com/design/intarch. Pressing the Delete  
key during boot causes the system to enter into the BIOS setup program.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
24  
April 2007  
Order Number: 311274-009  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
3.0  
Theory of Operation  
Block Diagram  
3.1  
Figure 13.  
Block Diagram of Layout  
Dual-Core  
Intel® Xeon®  
processor LV  
Dual-Core  
Intel® Xeon®  
processor LV  
167 MHz/667 MT/s  
X8 PCIe  
C
Intel®  
DDR2 400  
Single or dual  
channel support  
X8 PCIe  
B
E7520  
X8 PCIe  
(MCH)  
}A  
HL 1.5 Interface  
Two SATA  
PCI-X 66 MHz  
PCI 32/33  
R
Intel®  
6300ESB  
Four USB (2.0) Ports  
Two IDE  
R
LPC Bus  
SIO  
VGA  
TPM  
FWH  
3.2  
Thermal Management  
The objective of thermal management is to ensure that the temperature of each  
component is maintained within specified functional limits. The functional temperature  
limit is the range within which the electrical circuits may be expected to meet their  
specified performance requirements. Operation outside the functional limit may  
degrade system performance and cause reliability problems. The Development Kit is  
shipped with heatsink thermal solutions to be installed on the processor. This thermal  
solution has been tested in an open air environment at room temperature and is  
sufficient for evaluation purposes. The designer must ensure that adequate thermal  
management is provided for any customer-derived designs.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
25  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
3.3  
System Features  
Processor  
• Supports two Dual-Core Intel Xeon processors LV  
• On-board processor voltage regulators compatible with EmVRD11 Design Guide.  
Chipset  
®
• Intel E7520 MCH  
®
• Intel 6300ESB ICH  
Clocking  
• CK409B clock synthesizer that generates all host clock and the PCI Express  
interface clock for the MCH PHY layer  
• DB800 generates the PCI Express differential pair clocks to the onboard PCI  
Express components and the dedicated PCI Express slots  
Memory  
• Registered ECC DDR2-400 DIMMs  
®
• Each of the two memory channels on the Intel E7520 MCH on this CRB supports a  
maximum of four DDR2-400 DIMMs per channel  
• 3.2 Gbytes/s bus per channel bandwidth with DDR2-400  
Graphics  
• ATI Sapphire PCI Radeon* 700 64 MB graphics card  
I/O  
®
• From Intel 6300ESB ICH  
— One PCI 2.2 32/33 Slot  
Two PCI-X 66 MHz slots  
— One IDE connector  
Two Serial ATA connectors  
Two Serial ports  
— Four USB 2.0 ports  
Two on rear panel I/O  
Two on front panel header  
— Super I/O via LPC bus from the 6300ESB  
One Floppy port  
One Parallel port  
One Serial port (10-pin header)  
Two PS2 port  
Low Pin Count Bus  
• National LPC 47M172 Super I/O residing on LPC bus  
• Firmware hub  
Board Form Factor  
• 13.3” x 14” for bench top use  
• Common ATX 12V Power supply  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
26  
April 2007  
Order Number: 311274-009  
 
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
®
®
3.3.1  
3.3.2  
3.3.2.1  
Dual-Core Intel Xeon processor LV  
• 667 MHz FSB  
®
®
Intel E7520 MCH and Intel 6300ESB ICH Chipset  
The features of the chipsets are detailed below.  
®
Intel E7520 MCH Memory Controller Hub (MCH)  
The architecture of the MCH provides the performance and feature set required for dual  
processor-based volume to performance servers. Configuration options facilitate  
optimization of the platform for workloads characteristic of communication,  
presentation, storage, performance computation, or database applications. Coverage  
includes the MCH interface units (system bus, system memory, PCI Express, Hub  
Interface (HI), SMBus, power management, MCH clocking, MCH system reset and  
power sequencing) as well as RASUM (Reliability, Availability, Serviceability, Usability,  
and Manageability) features.  
Features:  
• Registered ECC DIMM support  
• Integrated four-channel DMA engine with IOxAPIC functionality  
• High speed serial PCI Express interface  
• Hub interface to 6300ESB ICH  
®
3.3.2.2  
Intel 6300ESB I/O Controller Hub (ICH)  
®
The Intel 6300ESB ICH is designed for a variety of processors/memory controller  
hubs. The 6300ESB provides the data buffering and interface arbitration required to  
ensure that system interfaces operate efficiently and provide the bandwidth necessary  
to enable the system to obtain peak performance.  
Features:  
• Upstream HI for access to the MCH  
Two port Serial ATA controllers  
• IDE connector  
• PCI-X 1.0 Interface  
• PCI 2.2 Interface  
Two serial I/O ports  
Two-stage WDT (Watch Dog Timer)  
• LPC Interface  
• EPLD for Port 80 decode and display  
• FWH Interface  
• SMBus 2.0 controller  
• I/O APIC  
• Four USB 2.0 Ports  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
27  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
3.3.3  
3.3.4  
Memory Subsystem  
The memory subsystem is designed to support Double Data Rate 2 (DDR2)  
Synchronous Dynamic Random Access Memory (SDRAM) using the Intel E7520 MCH.  
The MCH provides two independent DDR channels, which support DDR2-400 DIMMs.  
The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s)  
with DDR2-400. The two DDR2 channels from the MCH operate in lock step; the  
effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for  
DDR2-400.  
®
Supported DIMM Module Types  
Table 4 shows all DIMM technology validated by Intel on the CRB.  
Table 4.  
Supported DIMM Module Types  
512M  
SR  
1G  
SR  
2G  
SR  
A1  
512M  
SR  
1G  
SR  
1G  
SR  
1G  
SR  
2G  
SR  
A2  
A3  
A4  
B1  
B2  
B3  
B4  
1G  
SR  
512M  
SR  
1G  
SR  
1G  
SR  
2G  
DR  
2G  
SR  
1G  
SR  
4G  
DR  
2G  
SR  
1G  
SR  
1G  
SR  
512M  
SR  
512M  
DR  
1G  
SR  
2G  
DR  
2G  
SR  
1G  
SR  
4G  
DR  
2G  
SR  
1G  
SR  
512M  
SR  
1G  
SR  
2G  
SR  
1G  
SR  
512M  
SR  
1G  
SR  
1G  
SR  
1G  
SR  
2G  
SR  
1G  
SR  
1G  
SR  
512M  
SR  
1G  
SR  
1G  
SR  
2G  
DR  
2G  
SR  
1G  
SR  
4G  
DR  
2G  
SR  
512M  
SR  
512M  
DR  
1G  
SR  
1G  
SR  
1G  
SR  
512M  
SR  
512M  
DR  
1G  
SR  
2G  
DR  
2G  
SR  
1G  
SR  
4G  
DR  
2G  
SR  
Size  
512M  
512M  
2G  
4G  
4G  
4G  
5G  
6G  
8G  
8G  
8G  
16G  
16G  
Channels  
Single  
Single  
Dual  
Dual  
Single  
Dual  
Dual  
Dual  
Dual  
Dual  
Dual  
Dual  
Dual  
Note: SR = Single Rank; DR = Dual Rank  
3.3.5  
Memory Population Rules and Configurations  
The system supports four DDR2-400 DIMM slots for Channel A and four DDR2-400  
DIMM slots for Channel B. The eight slots are interleaved and placed in a row in the  
following order: A1, B1, A2, B2, A3, B3, A4, B4 with A1 being closest to the MCH. This  
design supports only registered ECC-enabled DIMMs.  
When populating both channels, always place identical DIMMs in sockets that have the  
same position on Channel A and Channel B (i.e., DIMM A2 should be identical to DIMM  
B2).  
In addition, single-rank DIMMs should be populated furthest from the MCH when a  
combination of single-rank and double-rank DIMMs are used. This recommendation is  
based on the signal integrity requirements of the DDR2 interface.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
28  
April 2007  
Order Number: 311274-009  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 14.  
DDR2-400 Memory—DIMM Ordering  
®
3.3.6  
Intel 82802AC Firmware Hub (FWH)  
A socketed FLASH device is used to store system BIOS as well as an Intel® Random  
Number Generator (RNG). A bootblock locking jumper is provided to allow a mechanical  
means of protecting the bootblock BIOS firmware. All BIOS programming is controlled  
via software.  
FWH Features:  
• 32-pin PLCC package  
• Symmetrically-blocked flash memory array (64 Kbyte)  
• Pin and register-based block locking  
• Integrated hardware RNG  
• Single-byte read/write  
• Five GPIs  
3.3.7  
3.3.8  
Boot ROM  
The system boot ROM is installed on the Intel 82802AC FWH device. The FWH is  
addressable on the LPC bus off the Intel 6300ESB ICH.  
®
In-Target Probe (ITP)  
The evaluation board contains an in-target probe (ITP) connector for an ITP-XDP  
connector. You must use an ITPFlex specific to the Dual-Core Intel Xeon processor LV.  
Other ITPs will not work and if installed, could damage the platform and/or the ITP.  
Figure 15 shows the ITP connector which is located between the DIMM B4 connector  
and the edge of the board. For more information refer to ITP700 Debug Port Design  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
29  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 15.  
ITP location  
3.3.9  
Power Diagram  
Figure 16 shows the power distribution for the CRB. Refer to the CRB schematics for  
details on the power distribution logic (contact your Intel field sales representative to  
obtain the schematics).  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
30  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 16.  
Power Distribution Block Diagram  
DDR  
1.8 V  
50 A  
DIMMS  
12V  
18A  
DDR  
S3  
S3_CNTRL  
Switch  
-12V  
1A  
VCCP 0  
0.8375-1.6000 V  
50 A  
VCCP 1  
0.8375-1.6000 V  
50 A  
VRM 11  
5.0V  
50A  
1.5V  
13 A  
VCCP  
1.05 V  
6.0 A  
-5.0V  
0.5A  
1.8VDDRSB  
3 A  
5.0VSTBY  
2.5A  
3.3VSTBY  
1.5VSTBY  
3.0 A  
0.8 A  
3.3V  
28A  
3.3 AUX  
1.7 A  
450W ATX  
3.3.10  
Clock Generation  
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair  
clocks and the 100MHz differential clock to the DB800. The DB800 then generates the  
100 MHz differential pair clock for the PCI Express devices. Figure 17 shows the CRB  
clock configuration.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
31  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 17.  
Clock Block Diagram  
CPU0_BCLK  
CPU0  
CPU1_BCLK  
CPU1  
ITP_BCLK  
DDRA  
DDRA_CMDCLK[0..3]  
ITP  
MCH_BCLK  
DDRB  
MCH_66MHZ_CLK  
DDRB_CMDCLK[0.3]  
MCH  
ICH_USB_48MHZ_CLK  
LPC_14MHZ_CLK  
ICH_33MHZ_CLK  
ICH_PX_PCLK0[0..1]  
PCI-X  
ICH  
ICH_HI66MHZ_CLK  
ICH_PX66MHZ_CLK  
32.786 kHz  
SIO_33MHZ_CLK  
LPC_14MHZ_CLK  
SIO  
MIDBUS_100MHZ_CLK  
PCI Express  
Midbus Probe  
LAI_HI66MHZ_CLK  
HI LAI  
DB800_SRC_100MHZ_CLK  
EXP_SLOT3_100MHZ_CLK  
EXP_SLOT4_100MHZ_CLK  
EXP_SLOT5_100MHZ_CLK  
29.499 MHz  
PCI Express  
Slot  
VIDEO_33MHZ_CLK  
FWH_33MHZ_CLK  
Video  
FWH  
PCI Express  
Slot  
PORT80_33MHZ_CLK  
PCI_SLOT6_33MHZ_CLK  
TPM_33MHZ_CLK  
PCI Express  
Slot  
Port 80  
PCI 2.2  
TPM  
DB800  
CK-409B  
3.3.11  
Platform Resets  
Figure 18 depicts the reset logic for the CRB. The 6300ESB provides most of the reset,  
following assertion of power good and system reset.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
32  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 18.  
Platform Reset Diagram  
FWH  
TPM  
PCI 32  
PCIRST2#  
VGA  
Port 80  
IDERST#  
PCIRST1#  
IDE  
SIO  
PCI-X  
PCI-X  
LPC  
Debug  
CPU 0  
CPU 1  
ITP  
SYS_RESET#  
VRM_PWRGD  
CPURST#  
MCH  
ICH  
SYS_PWRGD_3V3  
PCI-E  
Slots  
3.3.12  
SMBus  
Figure 19 below illustrates the routing of the SMBus signal among the components.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
33  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 19.  
SMBus Block Diagram  
3.3VSBY  
ICH-S  
0-ohm  
HECETA  
7
3.3VSBY  
SMBus  
Repeater  
TPM  
SMBus  
Repeater  
SMBus  
Repeater  
ID  
PCI Express Slot  
(Slot # 3)  
EEPROM  
ITP -  
XDP  
0-ohm  
PCI Express Slot  
(Slot # 4)  
SMBus  
3.3V  
0-ohm  
Master Only  
3.3V  
SMBus  
Repeater  
PCI Express Slot  
(Slot #5)  
Intel® E7520-  
PF  
DIMM #B1  
Addr 0xA8  
DIMM #A1  
Addr 0xA0  
PCI 32-bit/33MHz  
(Slot #6)  
CK409B  
DB800  
DIMM #A2  
Addr 0xA2  
DIMM #B2  
Addr 0xAA  
PCI-X 66MHz Slot  
(Slot #7)  
DIMM #B3  
Addr 0xAC  
DIMM #A3  
Addr 0xA4  
PCI-X 66MHz Slot  
(Slot #8)  
DIMM #B4  
Addr 0xAE  
DIMM #A4  
Addr 0xA6  
DDR CH A  
DDR CH B  
3.3.13  
Platform IRQ Routing  
Figure 20 shows how the 6300ESB uses these segments:  
• IRQ 14 for IDE segment  
• SERIRQ for SIOPIXRQ segment  
• PCRIRQ for the PCI-X segment  
• PIRQ for the PCI 32/33 segment  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
34  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 20.  
IRQ Routing Diagram  
PCI-E  
8x  
PCI-E  
8x  
PCI-E  
8x  
MSI  
MSI  
MSI  
CPU0  
MCH  
PCI Slot  
Video  
REQ/GNT: 1  
IDSEL: AD17  
A
REQ/GNT: 0  
IDSEL: AD16  
IDE  
A
B
C
D
A
B
C
D
E
F
IRQ14/15  
CPU0  
PCI-X Slot  
REQ/GNT: 0  
IDSEL: AD17  
PCI-X Slot  
REQ/GNT: 1  
IDSEL: AD18  
ICH  
G
H
A
B
C
D
A
B
C
D
A
B
C
D
SERIRQ  
SIO  
3.3.14  
VRD VID Headers  
VID headers provide for manual control of the processor core voltage regulator output  
level(s). Normally, the processor should be run at its default VID (voltage  
identification) value as set during manufacturing. However, in the event the user needs  
to set a different VID value from the default value, it can be accomplished through a  
jumper block found on the board.  
Note:  
These headers are not populated by default. EmVRD11 Controller VID input 0 and 7 are  
tied low. Initial boards will not have the VID Header populated, CPU1 must have VID  
override enabled for the initial Dual-Core Intel Xeon processor LV samples. The, VID  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
35  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
override enable, jumper controls whether or not the VID header jumpers control the  
1
VID to the regulator or not.  
Table 5.  
Processor VRD Settings  
VR6 VR5 VR4 VR3 VR2 VR1 Vccmax  
VR6 VR5 VR4 VR3 VR2 VR1 Vccmax  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60000  
1.58750  
1.57500  
1.56250  
1.55000  
1.53750  
1.52500  
1.51250  
1.50000  
1.48750  
1.47500  
1.46250  
1.45000  
1.43750  
1.42500  
1.41250  
1.40000  
1.38750  
1.37500  
1.36250  
1.35000  
1.33750  
1.32500  
1.31250  
1.30000  
1.28750  
1.27500  
1.26250  
1.25000  
1.23750  
1.22500  
1.21250  
1.20000  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.18750  
1.17500  
1.16250  
1.15000  
1.13750  
1.12500  
1.11250  
1.10000  
1.08750  
1.07500  
1.06250  
1.05000  
1.03750  
1.02500  
1.01250  
1.00000  
0.98750  
0.97500  
0.96250  
0.95000  
0.93750  
0.92500  
0.91250  
0.90000  
0.88750  
0.87500  
0.86250  
0.85000  
0.83750  
0.82500  
3.4  
Battery Requirements  
A type 2032 3 V lithium coin cell battery is required and included in the evaluation  
board kit.  
1. For the table above 1 means the jumper is installed.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
36  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
4.0  
4.1  
4.2  
Platform Management  
The following sections describe how the system power management operates, and how  
the different ACPI states are implemented. Platform management involves:  
• ACPI implementation-specific details  
• System monitoring, control, and response to thermal, voltage, and intrusion events  
• BIOS security  
Power Button  
The system power button is connected to the I/O controller component. When the  
button is pressed, the I/O controller receives the signal and transitions the system to  
the proper sleep state as determined by the operating system and software. If the  
power button is pressed and held for four seconds, the system powers off (S5 state).  
This feature is called power button override and is particularly helpful in case of system  
hang and system lock. The power button is located next to the SATA connectors on the  
board.  
Sleep States Supported  
The I/O controller controls the system sleep states. States S0, S1, S3, and S5 are  
supported. The platform enters sleep states in response to BIOS, operating system, or  
user actions. Normally the operating system determines which sleep state to transition  
into. However, a four second power button override event places the system  
immediately into S5. When transitioning into a software-invoked sleep state, the I/O  
controller attempts to gracefully put the system to sleep by first going into the  
processor C2 state.  
4.2.1  
4.2.2  
S0 State  
This is the normal operating state, even though there are some power savings modes  
in this state using processor Halt and Stop Clock (processor C1 and C2 states). S0  
affords the fastest wake-up response time of any sleep state because the system  
remains fully powered and memory is intact.  
S1 State  
This state is entered via a processor Sleep signal from the I/O controller (processor C3  
state). The system remains fully powered with memory contents intact but the  
processors enter their lowest power state. The operating system disables bus masters  
for uniprocessor configurations while flushing and invalidating caches before entering  
this state in multiprocessor configurations. Wake-up latency is slightly longer in this  
state than in S0; however, power savings are improved from S0.  
4.2.3  
4.2.4  
S2 State  
This state is not supported.  
S3 State  
This state is called Suspend to RAM (STR). The system context is maintained in system  
DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes  
continue. All clocks stop except the RTC. S3 is entered when the I/O controller asserts  
the SLP_S3# signal to downstream circuitry to control 1.8 V power plane switching.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
37  
               
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Power must be switched from the normal 1.8 V rail to standby 1.8 V, because the ATX  
12v 450 W power supply does not directly supply a standby 1.8 V rail. The sequence to  
enter Suspend to RAM is as follows:  
1. The OS and BIOS prepare for S3 sleep state.  
2. The OS sets the appropriate sleep bits in the I/O controller.  
3. The I/O controller drives STPCLK to the processors.  
4. The processors respond with a Stop-Grant cycle, passed over hub interface by  
MCH.  
5. The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface  
A.  
6. The MCH puts DDR memory into the self-refresh mode.  
7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.  
8. The MCH drives a completion message via Hub Interface A to the I/O controller.  
9. The I/O controller turns off all voltage rails (except Standby 5V) from the main  
power supply by asserting the SLP_S3_N signal.  
When in the S3 state, only the standby 5 V rail is available from the power supply. The  
board uses this standby source to generate 1.8 V standby rail to power the DIMMs.  
The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source  
from main 1.8 V to standby 1.8 V.  
4.2.5  
4.2.6  
S4 State  
This state is not supported.  
S5 State  
This state is the normal off state whether entered through the power button or soft off.  
All power is shut off except for the logic required to restart. The system remains in the  
S5 state only while the power supply is plugged into the electrical outlet. If the power  
supply is unplugged, this is considered a mechanical off or G3.  
4.2.7  
Wake-Up Events  
The types of wake-up events and wake-up latencies are related to the actual power  
rails available to the system in a particular sleep state, as well as to the location in  
which the system context is stored. Regardless of the sleep state, wake on the power  
button is always supported except in a mechanical off situation. When in a sleep state,  
the system complies with the PCI specification by supplying the optional 3.3 V standby  
voltage to each PCI slot as well as the PME# signal. This enables any compliant PCI  
card to wake up the system from any supported sleep state except mechanical off.  
4.2.8  
4.2.9  
Wake from S1 Sleep State  
During S1 the system is fully powered, permitting support for PCI Express Wake and  
Wake on PCI PME#.  
Wake from S3 State  
Keyboard press or mouse movement is used to wake from S3.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
38  
April 2007  
Order Number: 311274-009  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
4.2.10  
4.3  
Wake from S5 State  
The power button is used to wake from S5.  
PCI PM Support  
This design holds the system reset signal low when in a sleep state. The system  
supports the PCI PME# signal and provides 3.3 V standby to the PCI and PCI Express  
slots. This support allows any compliant PCI or PCI Express card to wake up the system  
from any sleep state except mechanical off. Because of the limited amount of power  
available on 3.3 V standby, the user and the operating system must configure the  
system carefully following the PCI power management interface specification.  
4.4  
Platform Management  
The LM 93 monitors the majority of the system voltages. The VID signals from the  
processors are also monitored by LM 93. All voltage levels can be read via the SMBus.  
4.4.1  
Processor Thermal Management  
Each processor monitors its own core temperature and thermally manages itself when  
it reaches a certain temperature. The system also uses the internal processor diode to  
monitor the die temperature. The diode pins are routed to the diode input pins in the  
LM 93. The LM 93 can be programmed to force the processor fans to full speed  
operation when it senses the processor core temperature exceeding a specific value. In  
addition, the LM 93 has an on-chip thermal monitor which allows it to monitor the  
incoming ambient temperature. Additional processor thermal management requires the  
system to communicate to the processors when the VRD reaches a critical  
temperature. The VR thermal monitor asserts FORCEPR_N signal to the processor.  
4.5  
System Fan Operation  
The system uses both the LM 93 and SMSC LPC47M172 to monitor and control the fans  
in the system.The LM93 uses pulse width modulated (PWM) outputs that can modulate  
the voltage across the fans, providing a variable duty cycle to effect a reduced DC  
voltage from nominal 12V DC.  
By default, the CPU fans are jumpered to run at full speed all the time. The fan  
headers are the standard 12 V, three-pin type used in previous servers, which support  
tachometer out. The LM 93 also has four tachometer inputs that it can use to monitor  
the fans it controls. All fan tachometer data can be extracted from the controllers via  
the SMBus. The system fan speed control circuit does not control the power supply fan.  
Each PWM output has a bypass jumper that causes all fans to run at full speed and  
ignore the PWM control. Each processor fan has its own dedicated PWM output and  
tachometer input, so each fan is controlled and monitored independently, depending on  
the core temperature.  
The LM 93 is dedicated to processor fan speed control and monitor, and can be  
programmed with temperature limit values that allow it to speed up or idle the  
processor fans, depending upon the input temperature.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
39  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
5.0  
Driver and OS Support  
The CRB supports the following operating systems:  
• Red Hat* EL 3.0 AS and WS  
• QNX Neutrino*  
• Windows* Server 2003  
• Microsoft* Windows XP and embedded XP  
Note:  
Operating systems are not included in the Development Kit.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
40  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.0  
Hardware Reference  
This section provides reference information on the hardware, including locations of  
evaluation board components, connector pinout information, and jumper settings.  
Figure 21 shows the evaluation board.  
Figure 21.  
Evaluation Board  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
April 2007  
Order Number: 311274-009  
41  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.1  
Chipset Components  
Table 6 lists the chipset and other major components on the evaluation board.  
Table 6.  
Chipset Components  
Component Designator  
U5E1  
Component Description  
Intel® E7520 Memory Controller Hub (MCH)  
Intel® 6300ESB I/O Controller Hub (ICH)  
Intel® 82802AC Firmware Hub (FWH)  
U3F1  
U1H1  
6.2  
Expansion Slots and Sockets  
Table 7 lists the expansion slots and sockets on the evaluation board.  
Table 7.  
Expansion Slots and Socket  
Slot/Socket Reference Designator  
Slot/Socket Description  
PCI Express Port A  
J2B2  
J3B2  
J3B1  
J2B1  
J1B1  
J1B2  
U5H1  
U7H1  
U1H1  
XB4G1  
PCI Express Port B  
PCI Express Port C  
PCI Slot  
PCI-X Slot 1  
PCI-X Slot 2  
CPU1  
CPU0  
Firmware Hub (FWH) BIOS Socket  
Battery  
6.2.1  
PCI Express* Connector  
Table 8 lists the signals assigned to the PCI Express* port A, B, and C slot connectors  
found at J2B2, J3B2, and J3B1 respectively.  
Table 8.  
PCI Express* Connector Pinout (Sheet 1 of 2)  
Pin  
A1  
Signal  
PRSNT1#  
Pin  
B1  
Signal  
12 V  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
12 V  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
B11  
12 V  
12 V  
12 V  
GND  
GND  
JTAG2  
JTAG3  
JTAG4  
JTAG5  
3.3 V  
3.3 V  
PWRGD  
SMCLK  
SMDAT  
GND  
3.3 V  
JTAG1  
3.3 VAUX  
WAKE#  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
42  
April 2007  
Order Number: 311274-009  
           
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 8.  
PCI Express* Connector Pinout (Sheet 2 of 2)  
Pin  
A12  
Signal  
Pin  
B12  
Signal  
Reserved  
GND  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
Refclk+  
Refclk -  
GND  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
GND  
HSOP_0  
HSON_0  
GND  
HSIP_0  
HSIN_0  
GND  
PRSNT2_1#  
GND  
Reserved  
GND  
HSOP_1  
HSON_1  
GND  
HSIP_1  
HSIN_1  
GND  
GND  
HSOP_2  
HSON_2  
GND  
GND  
HSIP_2  
HSIN_2  
GND  
GND  
HSOP_3  
HSON_3  
GND  
GND  
HSIP_3  
HSIN_3  
GND  
Reserved  
PRSNT2_2#  
Reserved  
HSOP_4  
HSON_4  
GND  
Reserved  
Reserved  
GND  
HSIP_4  
HSIN_4  
GND  
GND  
HSOP_5  
HSON_5  
GND  
GND  
HSIP_5  
HSIN_5  
GND  
GND  
HSOP_6  
HSON_6  
GND  
GND  
HSIP_6  
HSIN_6  
GND  
GND  
HSOP_7  
HSON_7  
GND  
GND  
HSIP_7  
HSIN_7  
GND  
PRSNT2_3#  
GND  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
43  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.2.2  
32-Bit PCI Connector  
Table 9 presents the signals assigned to the 32-bit PCI slot connector found at J2B1.  
Table 9.  
32-Bit 5 V PCI Connector Pinout (Sheet 1 of 2)  
Pin  
Signal  
TRST#  
Pin  
B1  
Signal  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
-12 V  
TCK  
GND  
TDO  
5 V  
+12 V  
TMS  
B2  
B3  
TDI  
B4  
5 V  
B5  
INTA#  
INTC#  
5 V  
B6  
5 V  
B7  
INTB#  
INTD#  
PRSNT1#  
Reserved  
PRSNT2#  
GND  
B8  
RSVD1  
5 V  
B9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
RSVD3  
GND  
GND  
GND  
3.3 VAUX  
RST#  
5 V  
Reserved  
GND  
CLK  
GNT#  
GND  
GND  
REQ#  
5 V  
PME#  
AD30  
3.3 V  
AD28  
AD26  
GND  
AD31  
AD29  
GND  
AD27  
AD25  
AD24  
IDSEL  
3.3 V  
AD22  
AD20  
GND  
3.3 V  
C/BE3#  
AD23  
GND  
AD21  
AD19  
AD18  
AD16  
3.3 V  
FRAME#  
GND  
3.3 V  
AD17  
C/BE2#  
GND  
IRDY#  
3.3 V  
TRDY#  
GND  
DEVSEL#  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
44  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 9.  
32-Bit 5 V PCI Connector Pinout (Sheet 2 of 2)  
Pin  
A38  
Signal  
STOP#  
Pin  
B38  
Signal  
GND  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
3.3 V  
SDONE  
SBO#  
GND  
PAR  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
LOCK#  
PERR#  
3.3 V  
SERR#  
3.3 V  
C/BE1#  
AD14  
GND  
AD15  
3.3 V  
AD13  
AD11  
GND  
AD9  
AD12  
AD10  
GND  
KEY  
KEY  
KEY  
KEY  
CBEO#  
3.3 V  
AD6  
AD8  
AD7  
3.3 V  
AD5  
AD4  
GND  
AD2  
AD3  
GND  
AD0  
AD1  
5 V  
5 V  
REQ64#  
5 V  
ACK64#  
5 V  
5 V  
5 V  
6.2.3  
PCI-X Connector  
Table 10 presents the PCI-X connector pinout for J1B1 and J1B2.  
Table 10.  
PCI-X Connector Pinout (Sheet 1 of 4)  
Pin  
Signal  
TRST#  
Pin  
B1  
Signal  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
-12 V  
TCK  
GND  
TDO  
5 V  
+12 V  
TMS  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
TDI  
5 V  
INTA#  
INTC#  
5 V  
5 V  
INTB#  
INTD#  
Reserved  
PRSNT1#  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
45  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 10.  
PCI-X Connector Pinout (Sheet 2 of 4)  
Pin  
A10  
Signal  
3.3 V  
Pin  
B10  
Signal  
Reserved  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
Reserved  
KEY  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
PRSNT2#  
KEY  
KEY  
KEY  
3.3 VAUX  
RST#  
3.3 V  
GNT#  
GND  
Reserved  
GND  
CLK  
GND  
REQ#  
3.3 V  
PME#  
AD30  
3.3 V  
AD28  
AD26  
GND  
AD31  
AD29  
GND  
AD27  
AD25  
3.3 V  
AD24  
IDSEL  
3.3 V  
AD22  
AD20  
GND  
C/BE3#  
AD23  
GND  
AD21  
AD19  
3.3 V  
AD18  
AD16  
3.3 V  
FRAME#  
GND  
AD17  
C/BE2#  
GND  
IRDY#  
3.3 V  
TRDY#  
GND  
DEVSEL#  
PCIXCAP  
LOCK#  
PERR#  
3.3 V  
STOP#  
3.3 V  
SDONE  
SBO#  
GND  
SERR#  
3.3 V  
PAR  
AD15  
3.3 V  
AD13  
AD11  
GND  
CBE1#  
AD14  
GND  
AD12  
AD10  
M66EN  
AD9  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
46  
April 2007  
Order Number: 311274-009  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 10.  
PCI-X Connector Pinout (Sheet 3 of 4)  
Pin  
A50  
Signal  
Pin  
B50  
Signal  
GND  
GND  
GND  
GND  
AD8  
AD7  
3.3 V  
AD5  
AD3  
GND  
AD1  
3.3 V  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
A70  
A71  
A72  
A73  
A74  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
A83  
A84  
A85  
A86  
A87  
A88  
A89  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
B70  
B71  
B72  
B73  
B74  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
B83  
B84  
B85  
B86  
B87  
B88  
B89  
CBEO#  
3.3 V  
AD6  
AD4  
GND  
AD2  
AD0  
3.3 V  
REQ64#  
5 V  
ACK64#  
5 V  
5 V  
5 V  
GND  
Reserved  
GND  
C/BE7#  
C/BE5#  
3.3 V  
PAR64  
AD62  
GND  
C/BE6#  
C/BE4#  
GND  
AD63  
AD61  
3.3 V  
AD59  
AD57  
GND  
AD60  
AD58  
GND  
AD56  
AD54  
3.3 V  
AD52  
AD50  
GND  
AD55  
AD53  
GND  
AD51  
AD49  
3.3 V  
AD47  
AD45  
GND  
AD48  
AD46  
GND  
AD44  
AD42  
3.3 V  
AD40  
AD38  
GND  
AD43  
AD41  
GND  
AD39  
AD37  
3.3V  
AD36  
AD34  
AD35  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
47  
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 10.  
PCI-X Connector Pinout (Sheet 4 of 4)  
Pin  
A90  
Signal  
Pin  
B90  
Signal  
GND  
AD33  
GND  
A91  
A92  
A93  
A94  
AD32  
B91  
B92  
B93  
B94  
Reserved  
GND  
Reserved  
Reserved  
GND  
Reserved  
6.2.4  
6.2.5  
Processor Sockets  
The processor is keyed so that it fits into the socket in one particular orientation.  
Firmware Hub (FWH) BIOS Socket  
®
The system boot ROM is installed on the Intel 82802AC Firmware Hub. The FWH is  
®
addressable on the LPC bus off the Intel 6300ESB ICH.  
The FWH or BIOS flash memory fits into the 32-pin socket U1H1, giving you the option  
to remove and reprogram it without the use of soldering equipment. There is also a  
flash utility that is supplied with the BIOS that can be used to program the FWH. This is  
the recommended way to program the FWH.  
There is only one correct orientation for the FWH to be placed into its socket. Line up  
the circular marking on the FWH, denoting pin one, with the arrow marking on the  
evaluation board socket.  
6.2.6  
Battery  
A type 2032, 3 V lithium coin cell battery is used in socket XB4G1 on the evaluation  
board. The battery is held in place by a metal arm. To remove the battery, gently push  
the metal arm and remove the battery.  
6.3  
On-Board Connectors  
Table 11.  
On-Board Connector  
Connector Reference Designator  
J1G1, J1F4  
Connector Description  
SATA Connector  
IDE Connector  
J1K2  
JJ1K1  
J9F4  
J2G1  
Floppy Connector  
ITP Connector  
Front Panel Connector  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
48  
April 2007  
Order Number: 311274-009  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.3.1  
SATA Connector  
Table 12.  
SATA Connector Pinout  
Pin  
Connector Description  
1
2
3
4
5
6
7
GND  
A+  
A-  
GND  
B-  
B+  
GND  
6.3.2  
IDE Connector  
®
The evaluation board has a 40-pin connector for the IDE controller present in the Intel  
6300ESB ICH. Table 13 lists the signals assigned to the IDE connector.  
Table 13.  
IDE Connector Pinout  
Pin  
Connector Description  
Reset IDE  
Pin  
21  
Connector Description  
PDDREQ  
1
2
GND  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
GND  
3
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
Host Data  
GND  
I/O Write#  
GND  
4
5
I/O Read#  
GND  
6
7
I/O CHRDY  
GND  
8
9
DACK#  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
GND  
IRQ14  
Reserved  
Addr1  
Primary IDE Cable Detect  
Addr0  
Addr2  
Chip Select 1#  
Chip Select 3#  
Activity  
Key  
GND  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
49  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.3.3  
Floppy Drive Connector  
The evaluation board provides one 34-pin floppy connector, which is located at J1K1.  
Table 14.  
Floppy Drive Connector Pinout  
Pin  
Signal  
Pin  
18  
Signal  
1
2
3
4
5
6
7
8
9
GND  
DIR#  
GND  
Drive Enable 0  
GND  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
STEP#  
GND  
Reserved  
Key  
Write Data#  
GND  
Drive Enable 1  
GND  
Write Gate#  
GND  
Index  
GND  
Track 00#  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
Motor Enable A#  
GND  
Write Protect#  
GND  
Reserved  
GND  
Read Data#  
GND  
Drive Select 0#  
GND  
Side 1 Select#  
GND  
Reserved  
GND  
Diskette Change#  
6.3.4  
Front Panel Connector  
The development kit is not shipped with a chassis, so the front panel connector is  
unused by default. However, if you want to place your evaluation board in a chassis,  
refer to Table 15 for the pinout of the front panel connector J2G1.  
Table 15.  
Front Panel Connector Pinout  
Pin  
Connector Description  
Pin  
Connector Description  
1
VCC  
VCC  
2
HD_ACT_LED_N  
FPNTPNL_PWR_LED  
FP_PWR_BTN_N  
GND  
3
5
7
9
4
GND  
6
FP_RST_BTN_N  
GND  
8
10  
No Pin  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
50  
April 2007  
Order Number: 311274-009  
       
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.4  
Jumpers  
The evaluation board has a number of jumpers that control various functions of the  
system.  
Table 16 presents the descriptions of the jumpers and their settings.  
Figure 22 illustrates the locations of the jumpers on the board.  
Table 16.  
Jumpers and Jumper Functions  
Jumper  
Function / Default Setting  
Comments  
2-4 = UP  
1-2 and 3-4 = DP  
J9E2  
ITP Mode / 1-2 and 3-4  
J7K2  
J6K1  
CPU 0 Fan Override / 1-2  
CPU 1 Fan Override / 1-2  
1-2 = Normal use  
2-3 = Clear CMOS  
J4G1  
Clear CMOS / 1-2  
J3K1  
J4A1  
J4B1  
J8E1  
J4F6  
CPU1 VIDs / 1.325 V (one jumper on position 5)  
5 VAUX enable / 1-2  
3.3 VAUX Enable / 1-2  
S3 Enable / 1-2  
Memory PLL0 / 1-2  
Valid for both FSB speeds  
Open = 667 MT/s  
2-3 = 533 MT/s  
J3J1  
CPU BSEL 0 / Open  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
51  
     
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Figure 22.  
Jumper Locations  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
52  
April 2007  
Order Number: 311274-009  
 
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.5  
SMBUS Headers  
The SMBUS headers are used to connect the SMBUS. Refer to the following tables for  
pinout information.  
Table 17 describes the SMBUS 3.3 V STBY pinout.  
Table 17.  
SMBUS 3.3 V STBY Pinout  
Pin  
Connector Description  
1
2
3
SMBDAT  
GND  
SMB CLK  
6.6  
Back Panel Connectors  
The evaluation board contains a number of connectors for external system devices and  
peripherals. Figure 23 shows the peripheral connectors.  
The following sections provide pinouts for each connector.  
Note:  
The video connector may not be present.  
Figure 23.  
Back Panel Connectors  
6.6.1  
PS/2-Style Mouse and Keyboard Connectors  
Table 18 lists the signals assigned to the PS/2-style keyboard and mouse connectors.  
The keyboard port is on the top and the mouse port is on the bottom.  
Table 18.  
PS/2-Style Mouse and Keyboard Pinout  
Pin  
Connector Description  
1,7  
2,8  
Data  
Reserved  
Ground  
3,9, 13-17  
4,10  
+5 V (fused)  
Clock  
5,11  
6, 12  
Reserved  
6.6.2  
Parallel Port  
Table 19 lists the signals assigned to the parallel port connector.  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
53  
             
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
Table 19.  
Parallel Port Connector Pinout  
Pin  
Connector Description  
Strobe#  
Pin  
14  
Connector Description  
Auto Feed#  
1
2
Data Bit 0  
Data Bit 1  
Data Bit 2  
Data Bit 3  
Data Bit 4  
Data Bit 5  
Data Bit 6  
Data Bit 7  
ACK#  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
Fault#  
3
INIT#  
4
SLC IN#  
Ground  
Ground  
Ground  
Ground  
Ground  
Ground  
Ground  
Ground  
5
6
7
8
9
10  
11  
12  
13  
Busy  
Paper end  
SLCT  
6.6.3  
Serial Ports  
Table 20 lists the signals assigned to the serial port connector.  
Table 20.  
Serial Port Connector Pinout  
Pin  
Connector Description  
1
2
3
4
5
6
7
8
9
DCD  
Serial In - RXD  
Serial Out - TXD  
DTR  
Ground  
DSR  
RTS  
CTS  
RI  
6.6.4  
Dual Stacked USB Connectors  
Table 21 lists the signals assigned to the dual stacked USB connector.  
Table 21.  
USB Connector Pinout  
Pin  
1,5  
Connector Description  
Power (fused)  
2,6  
3,7  
4,8  
USBP1 # [USBP2#]  
USBP1 [USBP2]  
Ground  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
54  
April 2007  
Order Number: 311274-009  
         
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
6.6.5  
Video Port  
Note:  
This section may not apply if video connector is not present on the board.  
Table 22 lists the signals assigned to the video port connector.  
Table 22.  
Video Port Connector Pinout  
Pin  
Connector Description  
1
VGA Red  
VGA Green  
VGA Blue  
Monitor ID  
GND  
2
3
4
5
6
GND  
7
GND  
8
GND  
9
GND  
10  
11  
12  
13  
14  
15  
GND  
Monitor ID  
DDCDA  
HSYNC  
YSYNC  
DDCLK  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
55  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
7.0  
Board Setup Checklist  
The following is a checklist of items to ensure proper functionality of the CRB.  
• All cables are properly plugged in:  
— Hard drives  
— SATA and/or IDE  
— Monitor, keyboard, mouse  
— Additional peripherals such as CD, DVD, floppy, etc.  
— Power  
• Fans are securely in place and plugged into the appropriate jumpers.  
• Memory, PCI, and PCI Express cards are secured in slots.  
• RTC battery is installed.  
• Jumpers are configured correctly (refer to Section 6.4, “Jumpers” on page 51).  
• Proper standoffs or mounting for board (if applicable).  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
56  
April 2007  
Order Number: 311274-009  
   
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
8.0  
Debug Procedure  
The debug procedure in this section is used to determine baseline functionality for the  
®
®
®
®
Dual-Core Intel Xeon processor LV with Intel E7520 Chipset and Intel 6300ESB  
ICH Development Kit. This is a cursory set of tests designed to provide a level of  
confidence in the platform operation.  
8.1  
Level 1 Debug (Port80/BIOS)  
Refer to the steps in Table 23 when debugging a board that does not boot.  
Table 23.  
Level 1 Debug (Port80/BIOS)  
Step  
Test  
Pass/Fail Criteria  
Green  
Cause of Failure  
Power sequence failure – go  
immediately to Level 2 debug  
1
Verify “SYSTEM PWRGD” LED  
Decimal on Port 80 display  
RED  
2
3
Is “PCI Reset” LED illuminated?  
Verify CPURST LED is off  
PCI reset stuck – go to Level 3 debug  
CPU reset stuck – go to Level 3  
debug  
Off  
System Hang – Check BIOS go to  
level 3 debug. Refer to AMI* BIOS  
documentation for details.  
Port 80 LEDs are posting  
boot codes and stopping  
4
Verify Port 80 posting  
Contact Intel representative for the  
latest BIOS image  
5
6
Verify BIOS settings  
Latest BIOS installed  
See default settings  
Verify default jumper settings  
Improper jumper settings  
8.2  
Level 2 Debug (Power Sequence)  
Table 24.  
Level 2 Debug (Power Sequence)  
Step  
Test  
Pass/Fail Criteria  
Cause of Failure  
Measure voltages across:  
3.3V  
-12V  
5V  
1
Primary power supply voltages  
External power supply failure  
5V  
12V  
2
3
4
5
6
7
8
1.8V  
1.8V  
DDR2 power supply failure  
MCH/ICH core power supply failure  
DDR2 standby power supply failure  
CPU_VTT power supply failure  
CPU0 VRD failure  
1.5V  
1.5V  
1.8V VSBY  
1.8V  
CPU VTT Power Supply  
CPU0 VRD  
1.05V  
1.2V – 1.4V  
1.2V – 1.4V  
Green  
CPU1 VRD  
CPU1 VRD failure  
Verify “SYSTEM PWRGD” LED  
Power sequence failure  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
April 2007  
Order Number: 311274-009  
User’s Manual  
57  
           
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH  
8.3  
Level 3 Debug (Voltage References)  
Table 25 includes the first items to look at when debugging a board that is not booting.  
Table 25.  
Level 3 Debug (Voltage Reference)  
Step  
Test  
Pass/Fail Criteria  
Cause of Failure  
1
MCH DDR2 Channel A Vref  
MCH DDR2 Channel B Vref  
MCH Hublink Vref  
0.9 V  
Vref incorrect: check resistor values  
Vref incorrect: check resistor values  
Vref incorrect: check resistor values  
Vswing incorrect: check resistor values  
Vref incorrect: check resistor values  
Vswing incorrect: check resistor values  
2
3
4
5
6
0.9 V  
0.354V  
0.804V  
0.347V  
0.696V  
MCH Hublink Vswing  
ICH Hublink Vref  
ICH Hublink Vswing  
CPU0 VTT Vref  
(back side of board)  
7
0.775V  
Vref incorrect: check resistor values  
CPU1 VTT Vref  
8
9
0.754V  
0.775V  
Vref incorrect: check resistor values  
Vref incorrect: check resistor values  
(back side of board)  
MCH VTT Vref  
Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH  
User’s Manual  
58  
April 2007  
Order Number: 311274-009  
   

Intel 80L188EA User Manual
JVC AV 21F15 User Manual
Lindy 20960 User Manual
Makita BSS501 User Manual
Measurement Specialties PCI QUAD AC5 User Manual
Moffat Blue Seal G512D B User Manual
Nortel Networks C4030 User Manual
Panasonic CT G2973 User Manual
Philips 20PT9007D User Manual
Philips 109B7 User Manual