Intel Box Core I7 4930k 3 4g BX80633I74930K User Manual

®
Intel Core™ i7 Processor Family for  
LGA2011 Socket  
Datasheet – Volume 1 of 2  
®
Supporting Desktop Intel Core™ i7-4960X Extreme Edition Processor  
Series for the LGA2011 Socket  
®
Supporting Desktop Intel Core™ i7-49xx and i7-48xx Processor Series  
for the LGA2011 Socket  
September 2013  
329366-001  
Table of Contents  
®
®
®
®
®
®
®
®
®
®
®
®
®
®
®
®
Datasheet  
3
®
®
7.1.6 Joint Test Action Group (JTAG) and Test Access  
4
Datasheet  
Figures  
Overshoot Example Waveform ......................................................................66  
CC  
Tables  
Datasheet  
5
7-12 V Overshoot Specifications.............................................................................. 66  
CC  
6
Datasheet  
Revision History  
Revision  
Number  
Description  
Date  
001  
Initial release  
September 2013  
§
Datasheet  
7
Introduction  
1 Introduction  
®
The Intel Core™ i7 processor family for LGA2011 socket are the next generation of  
64-bit, multi-core desktop processors built on 22-nanometer process technology. Based  
®
on the low-power/high-performance Intel Core™ i7 processor micro-architecture, the  
processor is designed for a two-chip platform instead of to the traditional three-chip  
platforms (processor, Memory Controller Hub, and Platform Controller Hub). The two-  
chip platform consists of a processor and the Platform Controller Hub (PCH) enabling  
higher performance, easier validation, and improved x-y footprint. Refer to Figure 1-1  
for a platform block diagram.  
The processor features per socket, up to 40 lanes of PCI Express* 3.0 links capable of  
8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of  
5.0 GT/s. The processor supports up to 46 bits of physical address space and a 48-bit  
virtual address space.  
Included in this family of processors is an integrated memory controller (IMC) and  
integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single  
die solution is known as a monolithic processor.  
The Datasheet - Volume 1 covers DC electrical specifications, land and signal  
definitions, differential signaling specifications, interface functional descriptions, power  
management descriptions, and additional feature information pertinent to the  
implementation and operation of the processor on its platform. Volume 2 provides  
register information. Refer to the Related Documents section for access to Volume 2.  
®
Note:  
Note:  
Note:  
Note:  
Note:  
Throughout this document, the Intel Core™ i7 processor family for LGA2011 socket  
may be referred to as “processor.  
®
Throughout this document, the Intel Core™ i7-49xx processor series for the LGA2011  
®
socket refers t the Intel Core™ i7-4930K processor.  
®
Throughout this document, the Intel Core™ i7-48xx processor series for the LGA2011  
®
socket refers to the Intel Core™ i7-4820K processor.  
®
Throughout this document, the Intel X79 Chipset Platform Controller Hub may be  
referred to as “PCH.  
Some processor features are not available on all platforms. Refer to the processor  
specification update for details.  
8
Datasheet  
 
Introduction  
Figure 1-1. Processor Platform Block Diagram Example  
1.1  
Processor Feature Details  
• Up to 6 execution cores  
®
• Each core supports two threads (Intel Hyper-Threading Technology), up to  
12 threads per socket  
• 32KB instruction and 32-KB data first-level cache (L1) for each core  
• 256KB shared instruction/data mid-level (L2) cache for each core  
• Up to 15MB last level cache (LLC): up to 2.5MB per core instruction/data last level  
cache (LLC), shared among all cores  
Datasheet  
9
   
Introduction  
1.2  
Supported Technologies  
• Intel Virtualization Technology (Intel VT)  
®
®
®
®
®
• Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d)  
®
®
• Intel Virtualization Technology (Intel VT) Processor Extensions  
®
• Intel 64 Architecture  
®
®
• Intel Streaming SIMD Extensions 4.1 (Intel SSE4.1)  
®
®
• Intel Streaming SIMD Extensions 4.2 (Intel SSE4.2)  
®
®
• Intel Advanced Vector Extensions (Intel AVX)  
®
• Intel AVX Floating Point Bit Depth Conversion (Float 16)  
®
• Intel Hyper-Threading Technology  
• Execute Disable Bit  
®
• Intel Turbo Boost Technology  
®
®
• Enhanced Intel SpeedStep Technology  
1.3  
Interfaces  
1.3.1  
System Memory Support  
• Supports four DDR3 channels  
• Unbuffered DDR3 DIMMs supported  
• Independent channel mode or lockstep mode  
• Data burst length of eight cycles for all memory organization modes  
• Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s, 1600 MT/s, and  
1866 MT/s  
• 64-bit wide channels  
• DDR3 standard I/O Voltage of 1.5 V  
• 1-Gb, 2-Gb, 4-Gb, and 8-Gb DDR3 DRAM technologies supported for these devices:  
— UDIMMs x8, x16  
• Up to 4 ranks supported per memory channel, 1, 2, or 4 ranks per DIMM  
• Open with adaptive idle page close timer or closed page policy  
• Per channel memory test and initialization engine can initialize DRAM to all logical  
zeros or a predefined test pattern  
• Minimum memory configuration: independent channel support with 1 DIMM  
populated  
• Command launch modes of 1n/2n  
• Improved Thermal Throttling  
• Memory thermal monitoring support for DIMM temperature using two memory  
signals, MEM_HOT_C{01/23}_N  
10  
Datasheet  
     
Introduction  
1.3.2  
PCI Express*  
• The PCI Express* port(s) are fully-compliant with the PCI Express* Base  
Specification, Revision 3.0 (PCIe 3.0)  
• Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)  
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express*  
devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports  
• 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0),  
also can be downgraded to x2 or x1  
• Negotiating down to narrower widths is supported, see Figure 1-2:  
— x16 port (Port 2 and Port 3) may negotiate down to x8, x4, x2, or x1  
— x8 port (Port 1) may negotiate down to x4, x2, or x1  
— x4 port (Port 0) may negotiate down to x2, or x1  
— When negotiating down to narrower widths, there are caveats as to how lane  
reversal is supported  
• Address Translation Services (ATS) 1.0 support  
• Hierarchical PCI-compliant configuration mechanism for downstream devices  
Traditional PCI style traffic (asynchronous snooped, PCI ordering)  
• PCI Express* extended configuration space. The first 256 bytes of configuration  
space aliases directly to the PCI compatibility configuration space. The remaining  
portion of the fixed 4-KB block of memory-mapped space above that (starting at  
100h) is known as extended configuration space.  
• PCI Express* Enhanced Access Mechanism – accessing the device configuration  
space in a flat memory mapped fashion  
• Automatic discovery, negotiation, and training of link out of reset  
• Supports receiving and decoding 64 bits of address from PCI Express*:  
— Memory transactions received from PCI Express* that go above the top of  
physical address space (when Intel VT-d is enabled, the check would be against  
the translated Host Physical Address (HPA)) are reported as errors by the  
processor.  
— Outbound access to PCI Express* will always have address bits 63:46 cleared  
• Re-issues Configuration cycles that have been previously completed with the  
Configuration Retry status  
• Power Management Event (PME) functions  
• Message Signaled Interrupt (MSI and MSI-X) messages  
• Degraded Mode support and Lane Reversal support  
• Static lane numbering reversal and polarity inversion support  
• Support for PCIe* 3.0 atomic operation, PCIe 3.0 optional extension on atomic  
read-modify-write mechanism  
Datasheet  
11  
 
Introduction  
Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)  
1.3.3  
Direct Media Interface Gen 2 (DMI2)  
• Serves as the chip-to-chip interface to the PCH  
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2  
• Operates at PCI Express* 1.0 or 2.0 speeds  
Transparent to software  
• Processor and peer-to-peer writes and reads with 64-bit address support  
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of  
Interrupt” broadcast message when initiated by the processor.  
• System Management Interrupt (SMI), SCI, and SERR error indication  
• Static lane numbering reversal support  
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp  
12  
Datasheet  
   
Introduction  
1.3.4  
Platform Environment Control Interface (PECI)  
The PECI is a one-wire interface that provides a communication channel between a  
PECI client (the processor) and a PECI master (the PCH). Refer to the Processor  
Thermal Mechanical Specifications and Design Guide for additional details on PECI  
services available in the processor (Refer to the Related Documents section).  
• Supports operation at up to 2 Mbps data transfers  
• Link layer improvements to support additional services and higher efficiency over  
PECI 2.0 generation  
• Services include processor thermal and estimated power information, control  
functions for power limiting, P-state and T-state control, and access for Machine  
Check Architecture registers and PCI configuration space (both within the processor  
package and downstream devices)  
• Single domain (Domain 0) is supported  
1.4  
Power Management Support  
1.4.1  
Processor Package and Core States  
• Advance Configuration and Power Interface (ACPI) C-states as implemented by the  
following processor C-states:  
— Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)  
— Core: CC0, CC1, CC1E, CC3, CC6, CC7  
• Enhanced Intel SpeedStep Technology  
1.4.2  
1.4.3  
System States Support  
• S0, S1, S3, S4, S5  
Memory Controller  
• Multiple CKE power-down modes  
• Multiple self-refresh modes  
• Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N signals  
1.4.4  
PCI Express*  
• L1 ASPM power management capability; L0s is not supported  
1.5  
Thermal Management Support  
• Digital Thermal Sensor with multiple on-die temperature zones  
• Adaptive Thermal Monitor  
• THERMTRIP_N and PROCHOT_N signal support  
• On-Demand mode clock modulation  
• Fan speed control with DTS  
Two integrated SMBus masters for accessing thermal data from DIMMs  
• New Memory Thermal Throttling features using MEM_HOT_C{01/23}_N signals  
Datasheet  
13  
             
Introduction  
1.6  
Package Summary  
The processor socket type is noted as LGA2011. The processor package is a  
52.5 x 45 mm FC-LGA package (LGA2011). Refer to the Processor Thermal Mechanical  
Specification and Design Guide (see Related Documents section) for the package  
mechanical specifications.  
1.7  
Terminology  
Table 1-1.  
Terminology (Sheet 1 of 3)  
Term  
Description  
Advanced Configuration and Power Interface  
ACPI  
ASPM  
CCM  
DCM  
Active State Power Management  
Continuous Conduction Mode  
Discontinuous Conduction Mode  
Third generation Double Data Rate SDRAM memory technology that is the successor  
to DDR2 SDRAM  
DDR3  
DMA  
DMI  
Direct Memory Access  
Direct Media Interface  
Direct Media Interface Gen 2  
Digital Thermal Sensor  
DMI2  
DTS  
Enhanced Intel  
Allows the operating system to reduce power consumption when performance is not  
needed.  
®
SpeedStep  
Technology (EIST)  
EPT  
Extended Page Tables  
ESD  
Electro-Static Discharge  
The Execute Disable bit allows memory to be marked as executable or non-  
executable when combined with a supporting operating system. If code attempts to  
run in non-executable memory, the processor raises an error to the operating  
system. This feature can prevent some classes of viruses or worms that exploit buffer  
overrun vulnerabilities and can thus help improve the overall security of the system.  
Execute Disable Bit  
®
See the Intel 64 and IA-32 Architectures Software Developer's Manuals for more  
detailed information.  
Refers to the normal operating conditions in which all processor specifications,  
including DC, AC, system bus, signal quality, mechanical, and thermal are satisfied.  
Functional Operation  
IHS  
Integrated Heat Spreader. A component of the processor package used to enhance  
the thermal performance of the package. Component thermal solutions interface with  
the processor at the IHS surface.  
The Integrated I/O Controller. An I/O controller that is integrated in the processor  
die.  
IIO  
The Integrated Memory Controller. A Memory Controller that is integrated in the  
processor die.  
IMC  
64-bit memory extensions to the IA-32 architecture. Further details on Intel 64  
architecture and programming model can be found at  
http://developer.intel.com/technology/intel64/.  
®
Intel 64 Technology  
®
®
®
Intel ME  
Intel Management Engine (Intel ME)  
®
Intel Turbo Boost Technology is a way to automatically run the processor core faster  
®
Intel Turbo Boost  
than the marked frequency if the part is operating under power, temperature, and  
current specifications limits of the Thermal Design Power (TDP). This results in  
increased performance of both single and multi-threaded applications.  
Technology  
Processor virtualization, which when used in conjunction with Virtual Machine Monitor  
software, enables multiple robust independent software environments inside a single  
platform.  
®
Intel Virtualization  
®
Technology (Intel VT)  
14  
Datasheet  
     
Introduction  
Table 1-1.  
Terminology (Sheet 2 of 3)  
Term  
Description  
®
®
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware  
assist, under system software (Virtual Machine Manager or operating system)  
control, for enabling I/O device virtualization. Intel VT-d also brings robust security  
by providing protection from errant DMAs by using DMA remapping, a key feature of  
Intel VT-d.  
®
Intel VT-d  
IOV  
I/O Virtualization  
Jitter  
JTAG  
Any timing variation of a transition edge or edges from the defined Unit Interval (UI).  
Joint Test Action Group  
The LGA2011-0 land FCLGA package mates with the system board through this  
surface mount, LGA2011-0 contact socket.  
LGA2011-0 Socket  
LLC  
Last Level Cache  
MCH  
Memory Controller Hub  
Non-Critical to Function: NCTF locations are typically redundant ground or non-  
critical reserved; thus, the loss of the solder joint continuity at end of life conditions  
will not affect the overall product functionality.  
NCTF  
NEBS  
PCH  
Network Equipment Building System. NEBS is the most common set of environmental  
design guidelines applied to telecommunications equipment in the United States.  
Platform Controller Hub. The next generation chipset with centralized platform  
capabilities including the main I/O interfaces along with display connectivity, audio  
features, power management, manageability, security, and storage features.  
PCI Express*  
PCI Express* 2  
PCI Express* 3  
PCU  
PCI Express* Generation 2.0/3.0  
PCI Express* Generation 2.0  
PCI Express* Generation 3.0  
Power Control Unit  
PECI  
Platform Environment Control Interface  
Pause Loop Exiting  
PLE  
Processor  
The 64-bit, single-core or multi-core component (package)  
The term “processor core” refers to silicon die itself that can contain multiple  
execution cores. Each execution core has an instruction cache, data cache, and  
256-KB L2 cache. All execution cores share the L3 cache. All DC and AC timing and  
signal integrity specifications are measured at the processor die (pads), unless  
otherwise noted.  
Processor Core  
QoS  
Quality of Service  
A unit of DRAM corresponding four to eight devices in parallel. These devices are  
usually, but not always, mounted on a single side of a DDR3 DIMM.  
Rank  
System Control Interrupt. Used in Advanced Configuration and Power Interface  
(ACPI) protocol.  
SCI  
System Management Bus. A two-wire interface through which simple system and  
power management related devices can communicate with the rest of the system. It  
SMBus  
2
is based on the principals of the operation of the I C* two-wire serial bus from  
Philips* Semiconductor.  
®
®
SSE  
STD  
STR  
SVID  
TAC  
TAP  
TCC  
TDP  
TLP  
Intel Streaming SIMD Extensions (Intel SSE)  
Suspend-to-Disk  
Suspend-to-RAM  
Serial Voltage Identification  
Thermal Averaging Constant  
Test Access Port  
Thermal Control Circuit  
Thermal Design Power  
Transaction Layer Packet  
Datasheet  
15  
Introduction  
Table 1-1.  
Terminology (Sheet 3 of 3)  
Term  
Description  
TSOD  
Thermal Sensor on DIMM  
Unbuffered Dual In-line Module  
UDIMM  
Uncore  
The portion of the processor comprising the shared cache, IMC, HA, PCU, and UBox.  
Signaling convention that is binary and unidirectional. In this binary signaling, one bit  
is sent for every edge of the forwarded clock, whether it be a rising edge or a falling  
edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at  
instance “n” is defined as:  
Unit Interval  
UI n = t n – t n – 1  
V
V
Processor core power supply  
CC  
Variable power supply for the processor system memory interface. V  
is the  
CCD  
, V  
CCD_01  
CCD_23  
generic term for V  
, V  
.
CCD_01  
CCD_23  
VID  
VM  
Voltage Identification  
Virtual Machine  
VMM  
VPID  
VR  
Virtual Machine Monitor  
Virtual Processor ID  
Voltage Regulator  
VRD  
VRM  
Voltage Regulator Down  
Voltage Regulator Module  
Processor ground  
V
SS  
x1  
Refers to a Link or Port with one Physical Lane  
Refers to a Link or Port with sixteen Physical Lanes  
Refers to a Link or Port with four Physical Lanes  
Refers to a Link or Port with eight Physical Lanes  
x16  
x4  
x8  
1.8  
Related Documents  
Refer to the following documents for additional information.  
Table 1-2.  
Processor Documents  
Document Number /  
Location  
Document  
®
Intel Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 2 of  
329367  
2
®
Intel Core™ i7 Processor Families for the LGA2011-0 Socket Thermal  
329368  
326199  
Mechanical Specifications and Design Guide  
®
Intel Core™ i7 Processor Family for LGA2011 Socket Specification Update  
16  
Datasheet  
   
Introduction  
Table 1-3.  
Public Specifications  
Document  
Document Number / Location  
Advanced Configuration and Power Interface Specification 3.0  
PCI Local Bus Specification 3.0  
PCI Express Base Specification - Revision 2.1 and 1.1  
PCI Express Base Specification - Revision 3.0  
System Management Bus (SMBus) Specification, Revision 2.0  
DDR3 SDRAM Specification  
Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life  
Specifications  
®
Intel 64 and IA-32 Architectures Software Developer’s Manuals  
Volume 1: Basic Architecture  
Volume 2A: Instruction Set Reference, A-M  
Volume 2B: Instruction Set Reference, N-Z  
Volume 3A: System Programming Guide  
Volume 3B: System Programming Guide  
®
Intel 64 and IA-32 Architectures Optimization Reference Manual  
®
Intel Virtualization Technology Specification for Directed I/O  
http://download.intel.com/technolog  
Direct_IO.pdf  
Architecture Specification  
National Institute of Standards and Technology NIST SP800-90  
http://csrc.nist.gov/publications/Pubs  
§
Datasheet  
17  
 
Interfaces  
2 Interfaces  
This chapter describes the functional behaviors supported by the processor. Topics  
covered include:  
2.1  
System Memory Interface  
2.1.1  
System Memory Technology Support  
The Integrated Memory Controller (IMC) supports DDR3 protocols with four  
independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.  
2.1.2  
System Memory Timing Support  
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and  
command signal mode timings on the main memory interface:  
• tCL = CAS Latency  
• tRCD = Activate Command to READ or WRITE Command delay  
• tRP = PRECHARGE Command Period  
• CWL = CAS Write Latency  
• Command Signal modes = 1n indicates a new command may be issued every clock  
and 2n indicates a new command may be issued every 2 clocks. Command launch  
mode programming depends on the transfer rate and memory configuration.  
18  
Datasheet  
       
Interfaces  
2.2  
PCI Express* Interface  
This section describes the PCI Express* 3.0 interface capabilities of the processor. See  
the PCI Express* Base Specification for details of PCI Express* 3.0.  
2.2.1  
PCI Express* Architecture  
Compatibility with the PCI addressing model is maintained to ensure that all existing  
applications and drivers operate unchanged. The PCI Express* configuration uses  
standard mechanisms as defined in the PCI Plug-and-Play specification.  
The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link  
Layer, and Physical Layer. The partitioning in the component is not necessarily along  
these same boundaries. Refer to the following figure for the PCI Express* Layering  
Diagram.  
Figure 2-1. PCI Express* Layering Diagram  
PCI Express* uses packets to communicate information between components. Packets  
are formed in the Transaction and Data Link Layers to carry the information from the  
transmitting component to the receiving component. As the transmitted packets flow  
through the other layers, the packets are extended with additional information  
necessary to handle packets at those layers. At the receiving side, the reverse process  
occurs and packets get transformed from their Physical Layer representation to the  
Data Link Layer representation and finally (for Transaction Layer Packets) to the form  
that can be processed by the Transaction Layer of the receiving device.  
Figure 2-2. Packet Flow through the Layers  
Datasheet  
19  
       
Interfaces  
2.2.1.1  
2.2.1.2  
Transaction Layer  
The upper layer of the PCI Express* architecture is the Transaction Layer. The  
Transaction Layer's primary responsibility is the assembly and disassembly of  
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as  
read and write, as well as certain types of events. The Transaction Layer also manages  
flow control of TLPs.  
Data Link Layer  
The middle layer in the PCI Express* stack, the Data Link Layer, serves as an  
intermediate stage between the Transaction Layer and the Physical Layer.  
Responsibilities of Data Link Layer include link management, error detection, and error  
correction.  
The transmission side of the Data Link Layer accepts TLPs assembled by the  
Transaction Layer, calculates and applies data protection code and TLP sequence  
number, and submits them to Physical Layer for transmission across the Link. The  
receiving Data Link Layer is responsible for checking the integrity of received TLPs and  
for submitting them to the Transaction Layer for further processing. On detection of TLP  
error(s), this layer is responsible for requesting retransmission of TLPs until information  
is correctly received, or the Link is determined to have failed. The Data Link Layer also  
generates and consumes packets that are used for Link management functions.  
2.2.1.3  
Physical Layer  
The Physical Layer includes all circuitry for interface operation, including driver and  
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance  
matching circuitry. It also includes logical functions related to interface initialization and  
maintenance. The Physical Layer exchanges data with the Data Link Layer in an  
implementation-specific format, and is responsible for converting this to an appropriate  
serialized format and transmitting it across the PCI Express* Link at a frequency and  
width compatible with the remote device.  
2.2.2  
PCI Express* Configuration Mechanism  
The PCI Express* link is mapped through a PCI-to-PCI bridge structure.  
PCI Express* extends the configuration space to 4096 bytes per-device/function, as  
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express*  
configuration space is divided into a PCI-compatible region (which consists of the first  
256 bytes of a logical device's configuration space) and an extended PCI Express*  
region (which consists of the remaining configuration space). The PCI-compatible  
region can be accessed using either the mechanisms defined in the PCI specification or  
using the enhanced PCI Express* configuration access mechanism described in the PCI  
Express* Enhanced Configuration Mechanism section.  
The PCI Express* Host Bridge is required to translate the memory-mapped PCI  
Express* configuration space accesses from the host processor to PCI Express*  
configuration cycles. To maintain compatibility with PCI configuration addressing  
mechanisms, it is recommended that system software access the enhanced  
configuration space using 32-bit operations (32-bit aligned) only.  
See the PCI Express* Base Specification for details of both the PCI-compatible and PCI  
Express* Enhanced configuration mechanisms and transaction rules.  
20  
Datasheet  
 
Interfaces  
2.3  
Direct Media Interface 2 (DMI2) / PCI Express*  
Interface  
Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub  
(PCH). DMI2 is similar to a four-lane PCI Express* supporting a speed of 5 GT/s per  
lane. Refer to Section 6.3 for additional details.  
Note:  
Only DMI2 x4 configuration is supported.  
2.3.1  
DMI2 Error Flow  
DMI2 can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or  
GPE. Any DMI2 related SERR activity is associated with Device 0.  
2.3.2  
2.3.3  
Processor / PCH Compatibility Assumptions  
The processor is compatible with the PCH and is not compatible with any previous Intel  
Memory Controller Hub (MCH) and Integrated Controller Hub (ICH) products.  
DMI2 Link Down  
The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to  
data link down, after the link was up, then the DMI2 link hangs the system by not  
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.  
Downstream transactions that had been successfully transmitted across the link prior  
to the link going down may be processed as normal. No completions from downstream,  
non-posted transactions are returned upstream over the DMI2 link after a link down  
event.  
2.4  
Platform Environment Control Interface (PECI)  
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking  
and data transfer. The bus requires no additional control lines. The physical layer is a  
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle  
level near zero volts. The duration of the signal driven high depends on whether the bit  
value is a logic ‘0’ or logic ‘1. PECI also includes variable data transfer rate established  
with every message. In this way, it is highly flexible even though underlying logic is  
simple.  
The interface design was optimized for interfacing to Intel processor and chipset  
components in both single processor and multiple processor environments. The single  
wire interface provides low board routing overhead for the multiple load connections in  
the congested routing area near the processor and chipset components. Bus speed,  
error checking, and low protocol overhead provides adequate link bandwidth and  
reliability to transfer critical device operating conditions and configuration information.  
Datasheet  
21  
         
Technologies  
3 Technologies  
This chapter covers the following technologies:  
®
®
• Intel Virtualization Technology (Intel VT)  
• Security Technologies  
®
®
• Intel Hyper-Threading Technology (Intel HT Technology)  
®
• Intel Turbo Boost Technology  
®
®
• Enhanced Intel SpeedStep Technology  
®
®
• Intel Advanced Vector Extensions (Intel AVX)  
®
®
3.1  
Intel Virtualization Technology (Intel VT)  
®
®
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple  
independent systems to software. This allows multiple, independent operating systems  
to run simultaneously on a single system. Intel VT comprises technology components  
to support virtualization of platforms based on Intel architecture microprocessors and  
chipsets.  
®
®
®
®
Intel Virtualization Technology (Intel VT) for Intel 64 and IA-32 Intel  
®
Architecture (Intel VT-x) adds hardware support in the processor to improve  
the virtualization performance and robustness. Intel VT-x specifications and  
®
functional descriptions are included in the Intel 64 and IA-32 Architectures  
Software Developer’s Manual, Volume 3B and is available at  
®
®
Intel Virtualization Technology (Intel VT) for Directed I/O  
®
(Intel VT-d) adds processor and uncore implementations to support and  
improve I/O virtualization performance and robustness. The Intel VT-d specification  
and other Intel VT documents can be referenced at  
®
3.1.1  
Intel VT-x Objectives  
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual  
Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable  
virtualized platforms. By using Intel VT-x, a VMM is:  
Robust: VMMs no longer need to use para-virtualization or binary translation. This  
means that off-the-shelf operating systems and applications can be run without any  
special steps.  
Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86  
processors.  
More reliable: Due to the hardware support, VMMs can now be smaller, less  
complex, and more efficient. This improves reliability and availability and reduces  
the potential for software conflicts.  
More secure: The use of hardware transitions in the VMM strengthens the isolation  
of VMs and further prevents corruption of one VM from affecting others on the  
same system.  
22  
Datasheet  
     
Technologies  
®
3.1.2  
Intel VT-x Features  
The processor core supports the following Intel VT-x features:  
• Extended Page Tables (EPT)  
— hardware assisted page table virtualization.  
— eliminates VM exits from guest operating system to the VMM for shadow page-  
table maintenance.  
• Virtual Processor IDs (VPID)  
— Ability to assign a VM ID to tag processor core hardware structures (such as,  
TLBs).  
— This avoids flushes on VM transitions to give a lower-cost VM transition time  
and an overall reduction in virtualization overhead.  
• Guest Preemption Timer  
— Mechanism for a VMM to preempt the execution of a guest operating system  
after an amount of time specified by the VMM. The VMM sets a timer value  
before entering a guest.  
— The feature aids VMM developers in flexibility and Quality of Service (QoS)  
guarantees.  
• Descriptor-Table Exiting  
— Descriptor-table exiting allows a VMM to protect a guest operating system from  
internal (malicious software based) attack by preventing relocation of key  
system data structures like IDT (interrupt descriptor table), GDT (global  
descriptor table), LDT (local descriptor table), and TSS (task segment selector).  
— A VMM using this feature can intercept (by a VM exit) attempts to relocate  
these data structures and prevent them from being tampered by malicious  
software.  
• Pause Loop Exiting (PLE)  
— PLE aims to improve virtualization performance and enhance the scaling of  
virtual machines with multiple virtual processors  
— PLE attempts to detect lock-holder preemption in a VM and helps the VMM to  
make better scheduling decisions  
®
3.1.3  
Intel VT-d Objectives  
The key Intel VT-d objectives are domain-based isolation and hardware-based  
virtualization. A domain can be abstractly defined as an isolated environment in a  
platform to which a subset of host physical memory is allocated. Virtualization allows  
for the creation of one or more partitions on a single system. This could be multiple  
partitions in the same operating system, or there can be multiple operating system  
instances running on the same system – offering benefits such as system  
consolidation, legacy migration, activity partitioning, or security.  
Datasheet  
23  
   
Technologies  
®
3.1.3.1  
Intel VT-d Features Supported  
The processor supports the following Intel VT-d features:  
• Root entry, context entry, and default context  
• Support for 4-K page sizes only  
• Support for register-based fault recording only (for single entry only) and support  
for MSI interrupts for faults  
— Support for fault collapsing based on Requester ID  
• Support for both leaf and non-leaf caching  
• Support for boot protection of default page table  
— Support for non-caching of invalid page table entries  
• Support for hardware based flushing of translated but pending writes and pending  
reads upon IOTLB invalidation  
• Support for page-selective IOTLB invalidation  
• Support for ARI (Alternative Requester ID – a PCI SIG ECR for increasing the  
function number count in a PCIe* device) to support I/O Virtualization (IOV)  
devices  
• Improved invalidation architecture  
• End point caching support (ATS)  
• Interrupt remapping  
®
3.1.4  
Intel Virtualization Technology Processor Extensions  
The processor supports the following Intel VT processor extension features:  
• Large Intel VT-d Pages  
— Adds 2MB and 1GB page sizes to Intel VT-d implementations  
— Matches current support for Extended Page Tables (EPT)  
— Ability to share processor EPT page-table (with super-pages) with Intel VT-d  
— Benefits:  
• Less memory foot-print for I/O page-tables when using super-pages  
• Potential for improved performance – due to shorter page-walks, allows  
hardware optimization for IOTLB  
Transition latency reductions expected to improve virtualization performance  
without the need for VMM enabling. This reduces the VMM overheads further and  
increase virtualization performance.  
24  
Datasheet  
 
Technologies  
3.2  
Security Technologies  
®
®
3.2.1  
Intel Advanced Encryption Standard New Instructions  
(Intel AES-NI) Instructions  
These instructions enable fast and secure data encryption and decryption, using the  
Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication  
number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in  
various protocols, the new instructions will be valuable for a wide range of applications.  
The architecture consists of six instructions that offer full hardware support for Intel  
AES-NI. Four instructions support the Intel AES-NI encryption and decryption, and the  
other two instructions support the Intel AES-NI key expansion. Together, they offer a  
significant increase in performance compared to pure software implementations.  
The Intel AES-NI instructions have the flexibility to support all three standard Intel  
AES-NI key lengths, all standard modes of operation, and even some nonstandard or  
future variants.  
Beyond improving performance, the Intel AES-NI instructions provide important  
security benefits. Since the instructions run in data-independent time and do not use  
lookup tables, the instructions help in eliminating the major timing and cache-based  
attacks that threaten table-based software implementations of Intel AES-NI. In  
addition, these instructions make AES simple to implement, with reduced code size.  
This helps reducing the risk of inadvertent introduction of security flaws, such as  
difficult-to-detect side channel leaks.  
3.2.2  
Execute Disable Bit  
The Intel Execute Disable Bit functionality can help prevent certain classes of malicious  
buffer overflow attacks when combined with a supporting operating system.  
• Allows the processor to classify areas in memory by where application code can  
execute and where it cannot.  
• When a malicious worm attempts to insert code in the buffer, the processor  
disables code execution, preventing damage and worm propagation.  
®
®
3.3  
Intel Hyper-Threading Technology (Intel HT  
Technology)  
®
®
The processor supports Intel Hyper-Threading Technology (Intel HT Technology)  
that allows an execution core to function as two logical processors. While some  
execution resources such as caches, execution units, and buses are shared, each  
logical processor has its own architectural state with its own set of general-purpose  
registers and control registers. This feature must be enabled using the BIOS and  
requires operating system support.  
Datasheet  
25  
       
Technologies  
®
3.4  
Intel Turbo Boost Technology  
Intel Turbo Boost Technology is a feature that allows the processor to opportunistically  
and automatically run faster than its rated operating frequency if it is operating below  
power, temperature, and current limits. The result is increased performance in multi-  
threaded and single threaded workloads. It should be enabled in the BIOS for the  
processor to operate with maximum performance.  
®
3.4.1  
Intel Turbo Boost Operating Frequency  
The processor’s rated frequency assumes that all execution cores are running an  
application at the thermal design power (TDP). However, under typical operation, not  
all cores are active. Therefore, most applications are consuming less than the TDP at  
the rated frequency. To take advantage of the available TDP headroom, the active cores  
can increase their operating frequency.  
To determine the highest performance frequency amongst active cores, the processor  
takes the following into consideration:  
• number of cores operating in the C0 state  
• estimated current consumption  
• estimated power consumption  
• die temperature  
Any of these factors can affect the maximum frequency for a given workload. If the  
power, current, or thermal limit is reached, the processor will automatically reduce the  
frequency to stay with its TDP limit.  
Note:  
Intel Turbo Boost Technology is only active if the operating system is requesting the P0  
state. For more information on P-states and C-states, refer to Chapter 4.  
®
®
3.5  
Enhanced Intel SpeedStep Technology  
®
The processor supports Enhanced Intel SpeedStep Technology as an advanced means  
of enabling very high performance while also meeting the power-conservation needs of  
the platform.  
Enhanced Intel SpeedStep Technology builds upon that architecture using design  
strategies that include the following:  
Separation between Voltage and Frequency Changes. By stepping voltage up  
and down in small increments separately from frequency changes, the processor is  
able to reduce periods of system unavailability that occur during frequency change.  
Thus, the system is able to transition between voltage and frequency states more  
often, providing improved power/performance balance.  
Clock Partitioning and Recovery. The bus clock continues running during state  
transition, even when the core clock and Phase-Locked Loop are stopped, which  
allows logic to remain active. The core clock can also restart more quickly under  
Enhanced Intel SpeedStep Technology.  
®
For additional information on Enhanced Intel SpeedStep Technology, refer to  
26  
Datasheet  
     
Technologies  
®
®
3.6  
Intel Advanced Vector Extensions (Intel AVX)  
Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of  
®
Intel Architecture. The introduction of Intel AVX started with the 2nd Generation Intel  
Core™ processor family. Intel AVX accelerates the trend of parallel computation in  
general purpose applications like image, video and audio processing, engineering  
applications (such as 3D modeling and analysis), scientific simulation, and financial  
analysts.  
Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main  
elements of Intel AVX are:  
• Support for wider vector data (up to 256-bit) for floating-point computation  
• Efficient instruction encoding scheme that supports 3 operand syntax and  
headroom for future extensions  
• Flexibility in programming environment, ranging from branch handling to relaxed  
memory alignment requirements  
• New data manipulation and arithmetic compute primitives, including broadcast,  
permute, fused-multiply-add, and so on  
• Floating point bit depth conversion (Float 16)  
• A group of 4 instructions that accelerate data conversion between 16-bit  
floating point format to 32-bit and vice versa.  
• This benefits image processing and graphical applications allowing  
compression of data so less memory and bandwidth is required.  
The key advantages of Intel AVX are:  
Performance – Intel AVX can accelerate application performance using data  
parallelism and scalable hardware infrastructure across existing and new  
application domains:  
— 256-bit vector data sets can be processed up to twice the throughput of 128-bit  
data sets  
— Application performance can scale up with the number of hardware threads and  
number of cores  
— Application domain can scale out with advanced platform interconnect fabrics  
Power Efficiency – Intel AVX is extremely power efficient. Incremental power is  
insignificant when the instructions are unused or scarcely used. Combined with the  
high performance that it can deliver, applications that lend themselves heavily to  
using Intel AVX can be much more energy efficient and realize a higher  
performance-per-watt.  
Extensibility – Intel AVX has built-in extensibility for the future vector extensions:  
— Operating System context management for vector-widths beyond 256 bits is  
streamlined  
— Efficient instruction encoding allows unlimited functional enhancements:  
• Vector width support beyond 256 bits  
• 256-bit Vector Integer processing  
• Additional computational and/or data manipulation primitives  
Datasheet  
27  
 
Technologies  
Compatibility – Intel AVX is backward compatible with previous ISA extensions  
including Intel SSE4:  
— Existing Intel SSE applications/library can:  
• Run unmodified and benefit from processor enhancements  
®
• Recompile existing Intel SSE intrinsic using compilers that generate  
Intel AVX code  
• Inter-operate with library ported to Intel AVX  
— Applications compiled with Intel AVX can inter-operate with existing Intel SSE  
libraries.  
§
28  
Datasheet  
Power Management  
4 Power Management  
This chapter provides information on the following power management topics:  
4.1  
Advanced Configuration and Power Interface  
(ACPI) States Supported  
The ACPI states supported by the processor are described in this section.  
4.1.1  
System States  
Table 4-1.  
System States  
State  
Description  
G0/S0  
G1/S3-Cold  
G1/S4  
Full On  
Suspend-to-RAM (STR). Context saved to memory.  
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).  
Soft off. All power lost (except wakeup on PCH). Total reboot.  
Mechanical off. All power removed from system.  
G2/S5  
G3  
4.1.2  
Processor Package and Core States  
The following table lists the package C-state support as: 1) the shallowest core C-state  
that allows entry into the package C-state, 2) the additional factors that will restrict the  
state from going any deeper, and 3) the actions taken with respect to the Ring Vcc, PLL  
state, and LLC.  
Table 4-3 lists the processor core C-states support.  
Datasheet  
29  
           
Power Management  
Table 4-2.  
Package C-State Support  
LLC  
Package C-  
State  
Core  
States  
Retentionand  
PLL-Off  
1
Limiting Factors  
Fully  
Notes  
Flushed  
PC0 – Active  
CC0  
N/A  
No  
No  
2
PCIe/PCH and Remote Socket  
Snoops  
PCIe/PCH and Remote Socket  
Accesses  
Interrupt response time  
requirement  
VccMin  
Freq = MinFreq  
PLL = ON  
PC2 –  
Snoopable  
Idle  
CC3–CC7  
No  
2
DMI Sidebands  
Configuration Constraints  
Core C-State  
at least  
one Core  
in C3  
Snoop Response Time  
Interrupt Response Time  
Non Snoop Response Time  
Vcc = retention  
PLL = OFF  
PC3 – Light  
Retention  
No  
No  
2, 3, 4  
2, 3, 4  
LLC ways open  
PC6 -  
Deeper  
Retention  
Snoop Response Time  
Non Snoop Response Time  
Interrupt Response Time  
Vcc = retention  
PLL = OFF  
CC6–CC7  
Notes:  
1.  
2.  
Package C7 is not supported.  
All package states are defined to be "E" states – such that the states always exit back into the LFM point  
upon execution resume  
3.  
4.  
The mapping of actions for PC3, and PC6 are suggestions – microcode will dynamically determine which  
actions should be taken based on the desired exit latency parameters.  
CC3/CC6 will all use a voltage below the VccMin operational point. The exact voltage selected will be a  
function of the snoop and interrupt response time requirements made by the devices (PCIe* and DMI) and  
the operating system.  
Table 4-3.  
Core C-State Support  
Core C-State  
Global Clock  
PLL  
L1/L2 Cache  
Core VCC  
Context  
CC0  
CC1  
CC1E  
CC3  
CC6  
CC7  
Running  
Stopped  
Stopped  
Stopped  
Stopped  
Stopped  
On  
On  
On  
On  
Off  
Off  
Coherent  
Coherent  
Active  
Active  
Maintained  
Maintained  
Coherent  
Request LFM  
Request Retention  
Power Gate  
Power Gate  
Maintained  
Flushed to LLC  
Flushed to LLC  
Flushed to LLC  
Maintained  
Flushed to LLC  
Flushed to LLC  
30  
Datasheet  
   
Power Management  
4.1.3  
Integrated Memory Controller (IMC) States  
Table 4-4.  
System Memory Power States  
State  
Description  
Power Up/Normal Operation CKE asserted. Active Mode, highest power consumption.  
Opportunistic, per rank control after idle time:  
Active Power Down (APD) (default mode)  
— CKE de-asserted. Power savings in this mode, relative to active idle  
state is about 55% of the memory power. Exiting this mode takes  
3 – 5 DCLK cycles.  
Pre-charge Power Down Fast Exit (PPDF)  
— CKE de-asserted. DLL-On. Also known as Fast CKE. Power savings in  
this mode, relative to active idle state is about 60% of the memory  
power. Exiting this mode takes 3 – 5 DCLK cycles.  
CKE Power Down  
Pre-charge Power Down Slow Exit (PPDS)  
— CKE de-asserted. DLL-Off. Also known as Slow CKE. Power savings in  
this mode, relative to active idle state is about 87% of the memory  
power. Exiting this mode takes 3 – 5 DCLK cycles until the first  
command is allowed and 16 cycles until first data is allowed.  
Register CKE Power Down:  
— IBT-ON mode: Both CKEs are de-asserted, the Input Buffer  
Terminators (IBTs) are left “on.  
— IBT-OFF mode: Both CKEs are de-asserted, the Input Buffer  
Terminators (IBTs) are turned “off.  
CKE de-asserted. In this mode, no transactions are executed and the system  
memory consumes the minimum possible power. Self-refresh modes apply to  
all memory channels for the processor.  
Self-Refresh  
IO-MDLL Off: Option that sets the IO master DLL off when self-refresh  
occurs.  
PLL Off: Option that sets the PLL off when self-refresh occurs.  
4.1.4  
Direct Media Interface Gen 2 (DMI2) / PCI Express* Link  
States  
Table 4-5.  
DMI2 / PCI Express* Link States  
State  
Description  
L0  
L1  
Full on – Active transfer state.  
Lowest Active State Power Management (ASPM) – Longer exit latency.  
Note: L1 is only supported when the DMI2/PCI Express* port is operating as a PCI Express* port.  
Datasheet  
31  
       
Power Management  
4.1.5  
G, S, and C State Combinations  
Table 4-6.  
G, S and C State Combinations  
Processor  
Global (G)  
State  
Sleep  
(S) State  
Processor  
State  
System  
Clocks  
Core  
Description  
(C) State  
G0  
G0  
G0  
S0  
S0  
S0  
C0  
C1/C1E  
C3  
Full On  
Auto-Halt  
Deep Sleep  
On  
On  
On  
Full On  
Auto-Halt  
Deep Sleep  
Deep Power  
Down  
Deep Power Down  
G0  
S0  
C6/C7  
On  
G1  
G1  
G2  
G3  
S3  
S4  
Power off  
Power off  
Power off  
Power off  
Off, except RTC Suspend to RAM  
Off, except RTC Suspend to Disk  
Off, except RTC Soft Off  
S5  
N/A  
Power off  
Hard off  
4.2  
Processor Core / Package Power Management  
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor  
®
frequency and core voltage based on workload. Each frequency and voltage operating  
point is defined by ACPI as a P-State. When the processor is not executing code, it is  
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-  
States have longer entry and exit latencies.  
®
®
4.2.1  
Enhanced Intel SpeedStep Technology  
®
The following are the key features of Enhanced Intel SpeedStep Technology:  
• Multiple frequency and voltage points for optimal performance and power  
efficiency. These operating points are known as P-States.  
• Frequency selection is software controlled by writing to processor MSRs. The  
voltage is optimized based on temperature, leakage, power delivery loadline, and  
dynamic capacitance.  
— If the target frequency is higher than the current frequency, V is ramped up  
CC  
to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage  
regulator. Once the voltage is established, the PLL locks on to the target  
frequency.  
— If the target frequency is lower than the current frequency, the PLL locks to the  
target frequency, then transitions to a lower voltage by signaling the target  
voltage on the SVID Bus.  
— All active processor cores share the same frequency and voltage. In a multi-  
core processor, the highest frequency P-state requested amongst all active  
cores is selected.  
— Software-requested transitions are accepted at any time. The processor has a  
new capability from the previous processor generation; it can preempt the  
previous transition and complete the new request without waiting for this  
request to complete.  
• The processor controls voltage ramp rates internally to ensure glitch-free  
transitions.  
• Because there is low transition latency between P-states, a significant number of  
transitions per second are possible.  
32  
Datasheet  
         
Power Management  
4.2.2  
Low-Power Idle States  
When the processor is idle, low-power idle states (C-states) are used to save power.  
More power savings actions are taken for numerically higher C-States. However, higher  
C-states have longer exit and entry latencies. Resolution of C-states occurs at the  
thread, processor core, and processor package level. Thread level C-states are  
available if Intel Hyper-Threading Technology is enabled. Entry and exit of the C-states  
at the thread and core level are shown in Figure 4-2.  
Figure 4-1. Idle Power Management Breakdown of the Processor Cores  
Figure 4-2. Thread and Core C-State Entry and Exit  
While individual threads can request low-power C-states, power saving actions only  
take place once the core C-state is resolved. Core C-states are automatically resolved  
by the processor. For thread and core C-states, a transition to and from C0 is required  
before entering any other C-state.  
Datasheet  
33  
     
Power Management  
Table 4-7.  
Coordination of Thread Power States at the Core Level  
Thread 1  
Processor Core  
C-State  
C0  
C1  
C3  
C6  
C7  
C0  
C0  
C0  
C0  
C0  
C0  
C1  
C3  
C6  
C7  
1
1
1
1
C0  
C0  
C0  
C0  
C1  
C1  
C1  
C1  
C1  
C3  
C3  
C3  
C1  
C3  
C6  
C6  
C1  
1
1
1
C3  
C6  
C7  
Thread 0  
Note:  
1. If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher.  
4.2.3  
Requesting Low-Power Idle States  
The core C-state will be C1E if all actives cores have also resolved a core C1 state or  
higher.  
The primary software interfaces for requesting low-power idle states are through the  
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).  
However, software may make C-state requests using the legacy method of I/O reads  
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This  
method of requesting C-states provides legacy support for operating systems that  
initiate C-state transitions using I/O reads.  
For legacy operating systems, P_LVLx I/O reads are converted within the processor to  
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in  
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be  
enabled in the BIOS.  
Note:  
The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read  
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in  
the following table.  
Table 4-8.  
P_LVLx to MWAIT Conversion  
P_LVLx  
MWAIT(Cx)  
Notes  
P_LVL2  
P_LVL3  
P_LVL4  
MWAIT(C3)  
MWAIT(C6)  
MWAIT(C7)  
C6. No sub-states allowed.  
C7. No sub-states allowed.  
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE Model Specific  
Register (MSR) to restrict the range of I/O addresses that are trapped and emulate  
MWAIT like functionality. Any P_LVLx reads outside of this range do not cause an I/O  
redirection to MWAIT(Cx) like request. The reads fall through like a normal I/O  
instruction.  
Note:  
When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The  
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O  
redirections enable the MWAIT 'break on EFLAGS.IF’ feature which triggers a wakeup  
on an interrupt even if interrupts are masked by EFLAGS.IF.  
34  
Datasheet  
     
Power Management  
4.2.4  
Core C-states  
The following are general rules for all core C-states, unless specified otherwise:  
• A core C-state is determined by the lowest numerical thread state (such as, Thread  
0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See  
• A core transitions to C0 state when:  
— an interrupt occurs.  
— there is an access to the monitored address if the state was entered using an  
MWAIT instruction.  
• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes  
only that thread. However, since both threads are no longer at the same core  
C-state, the core resolves to C0.  
• An interrupt only wakes the target thread for both C3 and C6 states. Any interrupt  
coming into the processor package may wake any core.  
4.2.4.1  
4.2.4.2  
Core C0 State  
The normal operating state of a core where code is being executed.  
Core C1/C1E State  
C1/C1E is a low-power state entered when all threads within a core execute a HLT or  
MWAIT(C1/C1E) instruction.  
A System Management Interrupt (SMI) handler returns execution to either Normal  
®
state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software  
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.  
While a core is in C1/C1E state, it processes bus snoops and snoops from other  
threads. For more information on C1E, see Section 4.2.5.2.  
4.2.4.3  
4.2.4.4  
Core C3 State  
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to  
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its  
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while  
maintaining its architectural state. All core clocks are stopped at this point. Because the  
core caches are flushed, the processor does not wake any core that is in the C3 state  
when either a snoop is detected or when another core accesses cacheable memory.  
Core C6 State  
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an  
MWAIT(C6) instruction. Before entering core C6, the core saves its architectural state  
to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.  
In addition to flushing core caches, the core architecture state is saved to the uncore.  
Once the core state save is completed, core voltage is reduced to zero. During exit, the  
core is powered on and its architectural state is restored.  
4.2.4.5  
Core C7 State  
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to  
the P_BLK or by an MWAIT(C7) instruction. Core C7 and core C7 substate are the same  
as Core C6. The processor does not support LLC flush under any condition.  
Datasheet  
35  
 
Power Management  
4.2.4.6  
Delayed Deep C-States  
The Delayed Deep C-states (DDCst) feature on this processor replaces the “C-state  
auto-demotion” scheme used in the previous processor generation. Deep C-states are  
defined as CC3 through CC7 (refer to Table 4-3 for supported deep C-states).  
The Delayed Deep C-states are intended to allow a staged entry into deeper C-states  
whereby the processor enters a lighter, short exit-latency C-state (core C1) for a period  
of time before committing to a long exit-latency deep C-state (core C3 and core C6).  
This is intended to allow the processor to get past the cluster of short-duration idles,  
providing each of those with a very fast wake-up time, but to still get the power benefit  
of the deep C-states on the longer idles.  
4.2.5  
Package C-States  
The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a  
summary of the general rules for package C-state entry. These apply to all package  
C-states unless specified otherwise:  
• A package C-state request is determined by the lowest numerical core C-state  
amongst all cores.  
• A package C-state is automatically resolved by the processor depending on the  
core idle power states and the status of the platform components.  
— Each core can be at a lower idle power state than the package if the platform  
does not grant the processor permission to enter a requested package C-state.  
— The platform may allow additional power savings to be realized in the  
processor.  
• For package C-states, the processor is not required to enter C0 before entering any  
other C-state.  
The processor exits a package C-state when a break event is detected. Depending on  
the type of break event, the processor does the following:  
• If a core break event is received, the target core is activated and the break event  
message is forwarded to the target core.  
— If the break event is not masked, the target core enters the core C0 state and  
the processor enters package C0.  
— If the break event is masked, the processor attempts to re-enter its previous  
package state.  
• If the break event was due to a memory access or snoop request.  
— But the platform did not request to keep the processor in a higher package  
C-state, the package returns to its previous C-state.  
— And the platform requests a higher power C-state, the memory access or snoop  
request is serviced and the package remains in the higher power C-state.  
The package C-states fall into two categories: independent and coordinated.  
C0/C1/C1E are independent, while C2/C3/C6 are coordinated.  
®
Starting with the 2nd Generation Intel Core™ processor family, package C-states are  
based on exit latency requirements that are accumulated from the PCIe* devices, PCH,  
and software sources. The level of power savings that can be achieved is a function of  
the exit latency requirement from the platform. As a result, there is no fixed  
relationship between the coordinated C-state of a package, and the power savings that  
will be obtained from the state. Coordinated package C-states offer a range of power  
savings that is a function of the guaranteed exit latency requirement from the platform.  
36  
Datasheet  
 
Power Management  
There is also a concept of Execution Allowed (EA). When EA status is 0, the cores in a  
socket are in C3 or a deeper state; a socket initiates a request to enter a coordinated  
package C-state. The coordination is across all sockets and the PCH.  
Table 4-9 shows an example of a dual-core processor package C-state resolution.  
Figure 4-3 summarizes package C-state transitions with package C2 as the interim  
between PC0 and PC1 prior to PC3 and PC6.  
Table 4-9.  
Coordination of Core Power States at the Package Level  
Core 1  
Package C-State  
C0  
C1  
C3  
C6  
C0  
C0  
C0  
C0  
C0  
C1  
C3  
C6  
1
1
1
C0  
C0  
C0  
C1  
C1  
C1  
C1  
C3  
C3  
C1  
C3  
C6  
Core 0  
1
1
Note:  
1. The package C-state will be C1E if all actives cores have resolved a core C1 state or higher.  
Figure 4-3. Package C-State Entry and Exit  
4.2.5.1  
Package C0 State  
The normal operating state for the processor. The processor remains in the normal  
state when at least one of its cores is in the C0 or C1 state or when the platform has  
not granted permission to the processor to go into a low-power state. Individual cores  
may be in lower power idle states while the package is in C0 state.  
Datasheet  
37  
   
Power Management  
4.2.5.2  
Package C1/C1E State  
No additional power reduction actions are taken in the package C1 state. However, if  
the C1E substate is enabled, the processor automatically transitions to the lowest  
supported core clock frequency, followed by a reduction in voltage. Autonomous power  
reduction actions that are based on idle timers, can trigger depending on the activity in  
the system.  
The package enters the C1 low-power state when:  
• At least one core is in the C1 state.  
• The other cores are in a C1 or lower power state.  
The package enters the C1E state when:  
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.  
• All cores are in a power state lower that C1/C1E but the package low-power state is  
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.  
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is  
enabled in POWER_CTL.  
No notification to the system occurs upon entry to C1/C1E.  
4.2.5.3  
Package C2 State  
Package C2 state is an intermediate state which represents the point at which the  
system level coordination is in progress. The package cannot reach this state unless all  
cores are in at least C3.  
The package will remain in C2 when:  
• it is awaiting for a coordinated response  
• the coordinated exit latency requirements are too stringent for the package to take  
any power saving actions  
If the exit latency requirements are high enough the package will transition to C3 or C6  
state depending on the state of the cores.  
4.2.5.4  
Package C3 State  
A processor enters the package C3 low-power state when:  
• At least one core is in the C3 state.  
• The other cores are in a C3 or lower power state, and the processor has been  
granted permission by the platform.  
• L3 shared cache retains context and becomes inaccessible in this state.  
• Additional power savings actions, as allowed by the exit latency requirements,  
include putting PCIe* links in L1, the uncore is not available, further voltage  
reduction can be taken.  
In package C3 state, the ring will be off and as a result no accesses to the LLC are  
possible. The content of the LLC is preserved.  
38  
Datasheet  
 
Power Management  
4.2.5.5  
Package C6 State  
A processor enters the package C6 low-power state when:  
• At least one core is in the C6 state.  
• The other cores are in a C6 or lower power state, and the processor has been  
granted permission by the platform.  
• L3 shared cache retains context and becomes inaccessible in this state.  
• Additional power savings actions, as allowed by the exit latency requirements,  
include putting PCIe* links in L1, the uncore is not available, further voltage  
reduction can be taken.  
In package C6 state, all cores have saved their architectural state and have had their  
core voltages reduced to zero volts. The LLC retains context, but no accesses can be  
made to the LLC in this state; the cores must break out to the internal state package  
C2 for snoops to occur.  
4.2.6  
Package C-State Power Specifications  
The following table lists the processor package C-state power specifications for various  
processor SKUs.  
The C-state power specification is based on post-silicon validation results. The  
processor case temperature is assumed at 50 °C for all C-states. Most of the idle power  
is attributed to the significant increase in higher speed I/O interfaces for the processor  
(PCIe*, DDR3).  
Table 4-10. Package C-State Power Specifications  
1
2
3
3
TDP SKUs  
C1E (W)  
C3 (W)  
C6 (W)  
6-Core  
130W (6-core)  
4-Core  
53  
53  
28  
28  
13  
13  
130W (4-core)  
Notes:  
1.  
2.  
3.  
SKUs are subject to change. Contact your Intel Field Representative to obtain the latest SKU information.  
o
Package C1E power specified at T  
Package C3/C6 power specified at T  
= 60 C  
CASE  
o
= 50 C  
CASE  
4.3  
System Memory Power Management  
The DDR3 power states can be summarized as the following:  
• Normal operation (highest power consumption).  
• CKE Power-Down: Opportunistic, per rank control after idle time. There may be  
different levels.  
— Active Power-Down.  
— Pre-charge Power-Down with Fast Exit.  
— Pre-charge power Down with Slow Exit.  
• Self-Refresh: In this mode no transaction is executed. The DDR consumes the  
minimum possible power.  
Datasheet  
39  
     
Power Management  
4.3.1  
CKE Power-Down  
The CKE input land is used to enter and exit different power-down modes. The memory  
controller has a configurable activity timeout for each rank. When no reads are present  
to a given rank for the configured interval, the memory controller will transition the  
rank to power-down mode.  
The memory controller transitions the DRAM to power-down by de-asserting CKE and  
driving a NOP command. The memory controller will tri-state all DDR interface lands  
except CKE (de-asserted) and ODT while in power-down. The memory controller will  
transition the DRAM out of power-down state by synchronously asserting CKE and  
driving a NOP command.  
When CKE is off, the internal DDR clock is disabled and the DDR power is significantly  
reduced.  
The DDR defines three levels of power-down:  
• Active power-down: This mode is entered if there are open pages when CKE is de-  
asserted. In this mode the open pages are retained. Existing this mode is 3 – 5  
DCLK cycles.  
• Pre-charge power-down fast exit: This mode is entered if all banks in DDR are pre-  
charged when de-asserting CKE. Existing this mode is 3 – 5 DCLK cycles. Difference  
from the active power-down mode is that when waking up all page-buffers are  
empty.  
• Pre-charge power-down slow exit: In this mode the data-in DLLs on DDR are off.  
Existing this mode is 3 – 5 DCLK cycles until the first command is allowed, but  
about 16 cycles until first data is allowed.  
4.3.2  
Self-Refresh  
The Power Control Unit (PCU) may request the memory controller to place the DRAMs  
in self-refresh state. Self-refresh per channel is supported. The BIOS can put the  
channel in self-refresh if software remaps memory to use a subset of all channels. Also,  
processor channels can enter self-refresh autonomously without a PCU instruction  
when the package is in a package C0 state.  
4.3.2.1  
Self-Refresh Entry  
Self-refresh entrance can be either disabled or triggered by an idle counter. Idle  
counter always clears with any access to the memory controller and remains clear as  
long as the memory controller is not drained. As soon as the memory controller is  
drained, the counter starts counting. When it reaches the idle-count, the memory  
controller will place the DRAMs in self-refresh state.  
Power may be removed from the memory controller core at this point. But V  
(1.5V or 1.35V) to the DDR I/O must be maintained.  
supply  
CCD  
40  
Datasheet  
   
Power Management  
4.3.2.2  
Self-Refresh Exit  
Self-refresh exit can be either a message from an external unit (PCU in most cases, but  
also possibly from any message-channel master) or as reaction for an incoming  
transaction.  
Here are the proper actions on self-refresh exit:  
• CK is enabled, and four CK cycles driven.  
• When proper skew between Address/Command and CK are established, assert  
CKE.  
• Issue NOPs for tXSRD cycles.  
• Issue ZQCL to each rank.  
• The global scheduler will be enabled to issue commands.  
4.3.2.3  
DLL and PLL Shutdown  
Self-refresh, according to configuration, may be a trigger for master DLL shut-down  
and PLL shut-down. The master DLL shut-down is issued by the memory controller  
after the DRAMs have entered self-refresh.  
The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a  
signal from the PLL indicating that the memory controller can start working again.  
4.3.3  
DRAM I/O Power Management  
Unused signals are tri-stated to save power. This includes all signals associated with an  
unused memory channel.  
The I/O buffer for an unused signal should be tri-stated (output driver disabled); the  
input receiver (differential sense-amp) should be disabled. The input path must be  
gated to prevent spurious results due to noise on the unused signals (typically handled  
automatically when input receiver is disabled).  
4.4  
Direct Media Interface 2 (DMI2) / PCI Express*  
Power Management  
Active State Power Management (ASPM) support using L1 state; L0s is not supported.  
§
Datasheet  
41  
   
Thermal Management Specifications  
5 Thermal Management  
Specifications  
The processor requires a thermal solution to maintain temperatures within operating  
limits. Any attempt to operate the processor outside these limits may result in  
permanent damage to the processor and potentially other components within the  
system. Maintaining the proper thermal environment is key to reliable, long-term  
system operation.  
A complete solution includes both component and system-level thermal management  
features. Component-level thermal solutions can include active or passive heatsinks  
attached to the processor Integrated Heat Spreader (IHS). Typical system-level  
thermal solutions may consist of system fans combined with ducting and venting.  
This section provides data necessary for developing a complete thermal solution. For  
more information on designing a component-level thermal solution, refer to the  
Processor Thermal Mechanical Specifications and Design Guidelines (see Related  
Documents section).  
§ §  
42  
Datasheet  
 
Signal Descriptions  
6 Signal Descriptions  
This chapter describes the processor signals. The signals are arranged in functional  
groups according to their associated interface or category.  
6.1  
System Memory Interface Signals  
Table 6-1.  
Memory Channel DDR0, DDR1, DDR2, DDR3  
Signal Name  
Description  
Bank Address: These signals define the bank which is the destination for  
the current Activate, Read, Write, or PRECHARGE command.  
DDR{0/1/2/3}_BA[2:0]  
DDR{0/1/2/3}_CAS_N  
Column Address Strobe  
Clock Enable  
DDR{0/1/2/3}_CKE[5:0]  
DDR{0/1/2/3}_CLK_DN[3:0]  
DDR{0/1/2/3}_CLK_DP[3:0]  
Differential Clocks to the DIMM: All command and control signals are  
valid on the rising edge of clock.  
Chip Select: Each signal selects one rank as the target of the command  
DDR{0/1/2/3}_CS_N[9:0]  
DDR{0/1/2/3}_DQ[63:00]  
and address.  
Data Bus: DDR3 Data bits.  
Data strobe: This is a differential pair Data Strobe. Differential strobes  
latch data for each DRAM. Different numbers of strobes are used  
depending on whether the connected DRAMs are x4,x8. Driven with edges  
in center of data, receive edges are aligned with data edges.  
DDR{0/1/2/3}_DQS_DP[17:00]  
DDR{0/1/2/3}_DQS_DN[17:00]  
Memory Address: Selects the Row address for Reads and writes, and the  
column address for activates. Also used to set values for DRAM  
configuration registers.  
DDR{0/1/2/3}_MA[15:00]  
DDR{0/1/2/3}_ODT[5:0]  
On-Die Termination: Enables DRAM on die termination during Data  
Write or Data Read transactions.  
DDR{0/1/2/3}_RAS_N  
DDR{0/1/2/3}_WE_N  
Row Address Strobe  
Write Enable  
Datasheet  
43  
       
Signal Descriptions  
Table 6-2.  
Memory Channel Miscellaneous  
Signal Name  
Description  
System Memory Reset: Reset signal from processor to DRAM devices on the  
DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while  
DDR_RESET_C23_N is used for memory channels 2 and 3.  
DDR_RESET_C01_N  
DDR_RESET_C23_N  
SMBus clock for the dedicated interface to the serial presence detect (SPD) and  
thermal sensors (TSoD) on the DIMMs. DDR_SCL_C01 is used for memory  
channels 0 and 1 while DDR_SCL_C23 is used for memory channels 2 and 3.  
DDR_SCL_C01  
DDR_SCL_C23  
SMBus data for the dedicated interface to the serial presence detect (SPD) and  
thermal sensors (TSoD) on the DIMMs. DDR_SDA_C1 is used for memory  
channels 0 and 1 while DDR_SDA_C23 is used for memory channels 2 and 3.  
DDR_SDA_C01  
DDR_SDA_C23  
Voltage reference for system memory reads: DDR_VREFDQRX_C01 is used for  
memory channels 0 and 1 while DDR_VREFDQRX_C23 is used for memory  
channels 2 and 3.  
DDR_VREFDQRX_C01  
DDR_VREFDQRX_C23  
Voltage reference for system memory writes: DDR_VREFDQTX_C01 is used for  
memory channels 0 and 1 while DDR_VREFDQTX_C23 is used for memory  
channels 2 and 3. These signals are not connected and there is no functionality  
provided on these two signals. The signals are unused by the processor.  
DDR_VREFDQTX_C01  
DDR_VREFDQTX_C23  
System memory impedance compensation: Impedance compensation must be  
terminated on the system board using a precision resistor.  
DDR{01/23}_RCOMP[2:0]  
DRAM_PWR_OK_C01  
DRAM_PWR_OK_C23  
Power good input signal used to indicate that the V  
power supply is stable for  
CCD  
memory channels 0 and 1, and channels 2 and 3.  
6.2  
PCI Express* Based Interface Signals  
Note:  
PCI Express* Ports 1, 2, and 3 signals are receive and transmit differential pairs.  
Table 6-3.  
PCI Express* Port 1 Signals  
Signal Name  
Description  
PE1A_RX_DN[3:0]  
PE1A_RX_DP[3:0]  
PCIe* Receive Data Input  
PCIe Receive Data Input  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PE1B_RX_DN[7:4]  
PE1B_RX_DP[7:4]  
PE1A_TX_DN[3:0]  
PE1A_TX_DP[3:0]  
PE1B_TX_DN[7:4]  
PE1B_TX_DP[7:4]  
Table 6-4.  
PCI Express* Port 2 Signals (Sheet 1 of 2)  
Signal Name  
Description  
PE2A_RX_DN[3:0]  
PE2A_RX_DP[3:0]  
PCIe Receive Data Input  
PCIe Receive Data Input  
PCIe Receive Data Input  
PCIe* Receive Data Input  
PCIe Transmit Data Output  
PE2B_RX_DN[7:4]  
PE2B_RX_DP[7:4]  
PE2C_RX_DN[11:8]  
PE2C_RX_DP[11:8]  
PE2D_RX_DN[15:12]  
PE2D_RX_DP[15:12]  
PE2A_TX_DN[3:0]  
PE2A_TX_DP[3:0]  
44  
Datasheet  
       
Signal Descriptions  
Table 6-4.  
PCI Express* Port 2 Signals (Sheet 2 of 2)  
Signal Name  
Description  
PE2B_TX_DN[7:4]  
PE2B_TX_DP[7:4]  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PE2C_TX_DN[11:8]  
PE2C_TX_DP[11:8]  
PE2D_TX_DN[15:12]  
PE2D_TX_DP[15:12]  
Table 6-5.  
PCI Express* Port 3 Signals  
Signal Name  
Description  
PE3A_RX_DN[3:0]  
PE3A_RX_DP[3:0]  
PCIe Receive Data Input  
PE3B_RX_DN[7:4]  
PE3B_RX_DP[7:4]  
PCIe Receive Data Input  
PCIe Receive Data Input  
PCIe Receive Data Input  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PCIe Transmit Data Output  
PE3C_RX_DN[11:8]  
PE3C_RX_DP[11:8]  
PE3D_RX_DN[15:12]  
PE3D_RX_DP[15:12]  
PE3A_TX_DN[3:0]  
PE3A_TX_DP[3:0]  
PE3B_TX_DN[7:4]  
PE3B_TX_DP[7:4]  
PE3C_TX_DN[11:8]  
PE3C_TX_DP[11:8]  
PE3D_TX_DN[15:12]  
PE3D_TX_DP[15:12]  
Table 6-6.  
PCI Express* Miscellaneous Signals  
Signal Name  
Description  
PCI RBIAS: This input is used to control PCI Express* bias currents. A 50 ohm  
1% tolerance resistor must be connected from this land to V by the platform.  
PE_RBIAS is required to be connected as if the link is being used even when PCIe*  
is not used.  
SS  
PE_RBIAS  
PCI RBIAS Sense: This signal provides dedicated bias resistor sensing to  
minimize the voltage drop caused by packaging and platform effects.  
PE_RBIAS_SENSE is required to be connected as if the link is being used even  
when PCIe* is not used.  
PE_RBIAS_SENSE  
PE_VREF_CAP  
PCI Express* Voltage Reference: PE_VREF_CAP is used to measure the actual  
output voltage and comparing it to the assumed voltage. A 0.01 uF capacitor must  
be connected from this land to V  
.
SS  
Datasheet  
45  
   
Signal Descriptions  
6.3  
Direct Media Interface Gen 2 (DMI2) / PCI  
Express* Port 0 Signals  
Table 6-7.  
DMI2 and PCI Express Port 0 Signals  
Signal Name  
Description  
DMI_RX_DN[3:0]  
DMI_RX_DP[3:0]  
DMI2 Receive Data Input  
DMI2 Transmit Data Output  
DMI_TX_DP[3:0]  
DMI_TX_DN[3:0]  
6.4  
Platform Environment Control Interface (PECI)  
Signal  
Table 6-8.  
Platform Environment Control Interface (PECI) Signals  
Signal Name  
Description  
Platform Environment Control Interface: This signal is the serial sideband  
interface to the processor and is used primarily for thermal, power and error  
management.  
PECI  
6.5  
System Reference Clock Signals  
Table 6-9.  
System Reference Clock (BCLK{0/1}) Signals  
Signal Name  
Description  
Reference Clock Differential input: These signals provide the PLL reference  
clock differential input into the processor. 100 MHz typical BCLK0 is the system  
clock and BCLK1 is the PCI Express* reference clock.  
BCLK{0/1}_D[N/P]  
6.6  
Joint Test Action Group (JTAG) and Test Access  
Point (TAP) Signals  
Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals (Sheet 1 of  
2)  
Signal Name  
Description  
Breakpoint and Performance Monitor Signals: I/O signals from the processor  
that indicate the status of breakpoints and programmable counters used for  
monitoring processor performance. These are 100 MHz signals.  
BPM_N[7:0]  
External Alignment of Reset: This signal is used to bring the processor up into  
a deterministic state. This signal is pulled up on the die; refer to Table 7-6 for  
details.  
EAR_N  
Probe Mode Ready: This signal is a processor output used by debug tools to  
PRDY_N  
PREQ_N  
TCK  
determine processor debug readiness.  
Probe Mode Request: This signal is used by debug tools to request debug  
operation of the processor.  
Test Clock: This signal provides the clock input for the processor Test Bus (also  
known as the Test Access Port).  
Test Data In: This signal transfers serial test data into the processor. TDI  
provides the serial input needed for JTAG specification support.  
TDI  
46  
Datasheet  
                 
Signal Descriptions  
Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals (Sheet 2 of  
2)  
Signal Name  
Description  
Test Data Out: This signal transfers serial test data out of the processor. TDO  
TDO  
TMS  
provides the serial output needed for JTAG specification support.  
Test Mode Select: This signal is a JTAG specification support signal used by  
debug tools.  
Test Reset: This signal resets the Test Access Port (TAP) logic. TRST_N must be  
driven low during power on Reset.  
TRST_N  
6.7  
Serial Voltage Identification (SVID) Signals  
Table 6-11. Serial Voltage Identification (SVID) Signals  
Signal Name  
Description  
SVIDALERT_N  
SVIDCLK  
Serial VID alert  
Serial VID clock  
Serial VID data out  
SVIDDATA  
6.8  
Processor Asynchronous Sideband and  
Miscellaneous Signals  
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 3)  
Signal Name  
Description  
BIST Enable Strap: This input allows the platform to enable or disable built-in  
self test (BIST) on the processor. This signal is pulled up on the die (refer to  
Table 7-6 for details).  
BIST_ENABLE  
Catastrophic Error: This signal indicates that the system has experienced a fatal  
or catastrophic error and cannot continue to operate. The processor will assert  
CAT_ERR_N for nonrecoverable machine check errors and other internal  
unrecoverable errors. It is expected that every processor in the system will wire-  
OR CAT_ERR_N for all processors. Since this is an I/O signal, external agents are  
allowed to assert this signal, which will cause the processor to take a machine  
check exception. This signal is sampled after PWRGOOD assertion.  
CAT_ERR_N  
On the processor, CAT_ERR_N is used for signaling the following types of errors:  
Legacy MCERRs, CAT_ERR_N is asserted for 16 BCLKs.  
Legacy IERRs, CAT_ERR_N remains asserted until warm or cold reset.  
CPU_ONLY_RESET  
ERROR_N[2:0]  
CPU Only Reset: Reserved, not used  
Error: These are error status signals for integrated I/O (IIO) unit:  
Error_N0 – Hardware correctable error (no operating system or firmware  
action necessary)  
Error_N1 – Non-fatal error (operating system or firmware action required to  
contain and recover)  
Error_N2 – Fatal error (system reset likely required to recover)  
Memory Throttle Control: MEM_HOT_C01_N and MEM_HOT_C23_N signals  
have two modes of operation – input and output mode.  
Input mode is externally asserted and is used to detect external events (such as  
VR_HOT# from the memory voltage regulator) and causes the processor to  
throttle the appropriate memory channels.  
Output mode is asserted by the processor known as level mode. In level mode,  
the output indicates that a particular branch of memory subsystem is hot.  
MEM_HOT_C01_N  
MEM_HOT_C23_N  
MEM_HOT_C01_N is used for memory channels 0 and 1 while MEM_HOT_C23_N  
is used for memory channels 2 and 3.  
Power Management Sync: A sideband signal to communicate power  
management status from the Platform Controller Hub (PCH) to the processor.  
PMSYNC  
Datasheet  
47  
       
Signal Descriptions  
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3)  
Signal Name  
Description  
Processor Hot: PROCHOT_N will go active when the processor temperature  
monitoring sensor detects that the processor has reached its maximum safe  
operating temperature. This indicates that the processor Thermal Control Circuit  
has been activated, if enabled. This signal can also be driven to the processor to  
activate the Thermal Control Circuit. This signal is sampled after PWRGOOD  
assertion.  
PROCHOT_N  
If PROCHOT_N is asserted at the de-assertion of RESET_N, the processor will tri-  
state its outputs.  
Power Good: This is a processor input. The processor requires this signal to be a  
clean indication that BCLK, V /V  
, V , V  
, and V  
, and V  
TTA TTD  
SA  
CCPLL  
CCD_01 CCD_23  
supplies are stable and within their specifications.  
“Clean” implies that the signal will remain low (capable of sinking leakage  
current), without glitches, from the time that the power supplies are turned on  
until the supplies come within specification. The signal must then transition  
monotonically to a high state.  
PWRGOOD can be driven inactive at any time, but clocks and power must again  
be stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions  
from inactive to active when all supplies except V are stable. V has a VBOOT  
CC  
CC  
PWRGOOD  
of zero volts and is not included in PWRGOOD indication in this phase. However,  
for the active to inactive transition, if any processor power supply (V , V /V  
,
TTA TTD  
CC  
V
, V  
, or V  
) is about to fail or is out of regulation, the PWRGOOD is to be  
SA  
CCD  
CCPLL  
negated.  
The signal must be supplied to the processor. It is used to protect internal circuits  
against voltage sequencing issues. It should be driven high throughout boundary  
scan operation.  
Note:  
V
has a VBOOT setting of 0.0V and is not included in the PWRGOOD  
CC  
indication and VSA has a Vboot setting of 0.9V.  
Reset: Asserting the RESET_N signal resets the processor to a known state and  
invalidates its internal caches without writing back any of their contents. Some  
PLL and error states are not effected by reset and only PWRGOOD forces them to  
a known state.  
RESET_N  
Safe Mode Boot: Strap signal. SAFE_MODE_BOOT allows the processor to wake  
up safely by disabling all clock gating. This allows BIOS to load registers or  
patches if required. This signal is sampled after PWRGOOD assertion. The signal is  
pulled down on the die (refer to Table 7-6 for details).  
SAFE_MODE_BOOT  
TEST[4:0]  
Test: Test[4:0] must be individually connected to an appropriate power source or  
ground through a resistor for proper processor operation.  
Thermal Trip: Assertion of THERMTRIP_N indicates one of two possible critical  
over-temperature conditions:  
The processor junction temperature has reached a level beyond which  
permanent silicon damage may occur and  
The system memory interface has exceeded a critical temperature limit set by  
BIOS.  
Measurement of the processor junction temperature is accomplished through  
multiple internal thermal sensors that are monitored by the Digital Thermal  
Sensor (DTS). Simultaneously, the Power Control Unit (PCU) monitors external  
memory temperatures using the dedicated SMBus interface to the DIMMs. If any  
of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to  
prevent damage to the DIMMs. Once activated, the processor will stop all  
execution and shut down all PLLs.  
THERMTRIP_N  
To further protect the processor, its core voltage (V ), V , V  
CCD  
, V , V  
,
CC  
TTA  
TTD  
SA  
CCPLL  
V
supplies must be removed following the assertion of THERMTRIP_N. Once  
activated, THERMTRIP_N remains latched until RESET_N is asserted. While the  
assertion of the RESET_N signal may de-assert THERMTRIP_N, if the processor's  
junction temperature remains at or above the trip level, THERMTRIP_N will again  
be asserted after RESET_N is de-asserted. This signal can also be asserted if the  
system memory interface has exceeded a critical temperature limit set by BIOS.  
This signal is sampled after PWRGOOD assertion.  
48  
Datasheet  
Signal Descriptions  
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 3 of 3)  
Signal Name  
Description  
®
®
Intel Trusted Execution Technology (Intel TXT) Agent: This is a strap  
signal:  
®
0 = Default. The socket is not the Intel TXT Agent.  
1 = The socket is the Intel TXT Agent.  
®
TXT_AGENT  
In non-Scalable dual-processor (DP) platforms, the legacy socket (identified by  
SOCKET_ID[1:0] = 00b) with Intel TXT Agent should always set the TXT_AGENT  
to 1b.  
On Scalable DP platforms the TXT AGENT is at the Node Controller.  
This signal is pulled down on the die (refer to Table 7-6 for details).  
®
®
Intel Trusted Execution Technology (Intel TXT) Platform Enable: This is  
a strap signal:  
®
0 = The platform is not Intel TXT enabled. All sockets should be set to zero.  
Scalable DP (sDP) platforms should choose this setting if the Node Controller  
does not support Intel TXT.  
1 = Default. The platform is Intel TXT enabled. All sockets should be set to one.  
In a non-Scalable DP platform this is the default. When this is set, Intel TXT  
functionality requires the user to explicitly enable Intel TXT using BIOS  
setup.  
TXT_PLTEN  
This signal is pulled up on the die (refer to Table 7-6 for details).  
Table 6-13. Miscellaneous Signals  
Signal Name  
Description  
BCLK Select: These configuration straps are used to inform the processor that a  
non-standard value for BCLK will be applied at reset. A "11" encoding on these  
inputs informs the processor to run at DEFAULT BCLK = 100 MHz. These signals  
have internal pull-up to V .  
TT  
The encoding is as follows:  
BCLK_SELECT1  
BCLK_SELECT0  
BCLK Selected  
100 MHz (default)  
100 MHz  
125 MHz  
Reserved  
BCLK_SELECT[1:0]  
X
1
1
0
0
X
1
0
1
0
Reserved  
CORE_VREF_CAP  
CORE_RBIAS  
A capacitor must be connected from this land.  
This input is used to control bias currents.  
This signal provides dedicated bias resistor sensing to minimize the voltage drop  
caused by packaging and platform effects.  
CORE_RBIAS_SENSE  
Processor Selected: This output can be used by the platform to determine if the  
®
installed processor is an Intel Core™ i7 processor family for LGA2011 socket or a  
PROC_SEL_N  
future processor. There is no connection to the processor silicon for this signal.  
This signal is also used by the V  
support future processors.  
and V rails to switch their output voltage to  
CCPLL  
TT  
RESERVED: All signals that are RSVD must be left unconnected on the board.  
Refer to Section 7.1.9 for details.  
RSVD  
Socket Occupied: SKTOCC_N is used to indicate that a processor is present. This  
is pulled to ground on the processor package; there is no connection to the  
processor silicon for this signal.  
SKTOCC_N  
TESTHI_BH48  
TESTHI_BF48  
TESTHI_AT50  
Test High: TESTHI_XX signal must be pulled up on the board.  
Datasheet  
49  
 
Signal Descriptions  
6.9  
Processor Power and Ground Supplies  
Table 6-14. Power and Ground Signals  
Signal Name  
Description  
Variable power supply for the processor cores, lowest level caches (LLC), ring  
interface, and home agent. It is provided by a VRM/EVRD 12.0 compliant regulator  
for each processor socket. The output voltage of this supply is selected by the  
processor, using the serial voltage ID (SVID) bus.  
VCC  
Note:  
V
has a Vboot setting of 0.0 V and is not included in the PWRGOOD  
CC  
indication.  
VCC_SENSE and VSS_VCC_SENSE provide an isolated, low impedance connection  
to the processor core power and ground. These signals must be connected to the  
voltage regulator feedback circuit that insures the output voltage (that is,  
processor voltage) remains within specification.  
VCC_SENSE  
VSS_VCC_SENSE  
VSA_SENSE and VSS_VSA_SENSE provide an isolated, low impedance connection  
to the processor system agent (VSA) power plane. These signals must be  
connected to the voltage regulator feedback circuit that insures the output voltage  
(that is, processor voltage) remains within specification.  
VSA_SENSE  
VSS_VSA_SENSE  
VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low impedance  
connection to the processor I/O power plane. These signals must be connected to  
the voltage regulator feedback circuit that insures the output voltage (that is,  
processor voltage) remains within specification.  
VTTD_SENSE  
VSS_VTTD_SENSE  
Variable power supply for the processor system memory interface. These signals  
are provided by two VRM/EVRD 12.0 compliant regulators per processor socket.  
VCCD_01 and VCCD_23 are used for memory channels 0, 1, 2, and 3 respectively.  
The valid voltage of this supply (1.50V or 1.35V) is configured by BIOS after  
determining the operating voltages of the installed memory. VCCD_01 and  
VCCD_23 will also be referred to as VCCD.  
VCCD_01 and VCCD_23  
Note: The processor must be provided VCCD_01 and VCCD_23 for proper  
operation, even in configurations where no memory is populated. A  
VRM/EVRD 12.0 controller is recommended, but not required.  
VCCPLL  
VSA  
Fixed power supply (1.7V) for the processor phased lock loop (PLL).  
Variable power supply for the processor system agent units. These include logic  
(non-I/O) for the integrated I/O controller, the integrated memory controller  
(IMC), and the Power Control Unit (PCU). The output voltage of this supply is  
selected by the processor, using the serial voltage ID (SVID) bus.  
Note: VSA has a Vboot setting of 0.9V.  
VSS  
Processor ground node.  
Combined fixed analog and digital power supply for I/O sections of the processor,  
Direct Media Interface Gen 2 (DMI2) interface, and PCI Express* interface. These  
signals will also be referred to as VTT.  
VTTA  
VTTD  
§
§
§ §  
50  
Datasheet  
   
Electrical Specifications  
7 Electrical Specifications  
This chapter covers the following topics:  
7.1  
Processor Signaling  
The processor includes 2011 lands that use various signaling technologies. Signals are  
grouped by electrical characteristics and buffer type into various signal groups. These  
include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2,  
Platform Environmental Control Interface (PECI), System Reference Clock, SMBus,  
JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband,  
Miscellaneous, and Power/Other signals. Refer to Table 7-5 for details.  
7.1.1  
System Memory Interface Signal Groups  
The system memory interface uses DDR3 technology that consists of numerous signal  
groups. These include Reference Clocks, Command Signals, Control Signals, and Data  
Signals. Each group consists of numerous signals that may use various signaling  
technologies. Refer to Table 7-5 for further details. Throughout this chapter the system  
memory interface may be referred to as DDR3.  
7.1.2  
7.1.3  
PCI Express* Signals  
The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI  
Express miscellaneous signals. Refer to Table 7-5 for further details.  
Direct Media Interface Gen 2 (DMI2) / PCI Express*  
Signals  
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands  
to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The  
DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals  
and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Refer to Table 7-5  
for further details.  
Datasheet  
51  
         
Electrical Specifications  
7.1.4  
Platform Environmental Control Interface (PECI)  
PECI is an Intel proprietary interface that provides a communication channel between  
Intel processors and chipset components to external system management logic and  
thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS)  
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)  
activation temperature. Temperature sensors located throughout the die are  
implemented as analog-to-digital converters calibrated at the factory. PECI provides an  
interface for external devices to read processor temperature, perform processor  
manageability functions, and manage processor interface tuning and diagnostics. Refer  
to the Processor Thermal Mechanical Specifications and Design Guidelines (see Related  
Documents section) for processor specific implementation details for PECI.  
The PECI interface operates at a nominal voltage set by V  
. The set of DC electrical  
TTD  
specifications shown in Table 7-14 is used with devices normally operating from a V  
interface supply.  
TTD  
7.1.4.1  
Input Device Hysteresis  
The PECI client and host input buffers must use a Schmitt-triggered input design for  
improved noise immunity. Refer to Figure 7-1 and Table 7-14.  
Figure 7-1. Input Device Hysteresis  
7.1.5  
System Reference Clocks (BCLK{0/1}_DP,  
BCLK{0/1}_DN)  
The processor core, processor uncore, PCI Express* and DDR3 memory interface  
frequencies) are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. The  
processor maximum core frequency and DDR memory frequency are set during  
manufacturing. It is possible to override the processor core frequency setting using  
software. This permits operation at lower core frequencies than the factory set  
maximum core frequency.  
The processor core frequency is configured during reset by using values stored within  
the device during manufacturing. The stored value sets the lowest core multiplier at  
which the particular processor can operate. If higher speeds are desired, the  
appropriate ratio can be configured using the IA32_PERF_CTL MSR (MSR 199h); Bits  
[15:0].  
52  
Datasheet  
     
Electrical Specifications  
Clock multiplying within the processor is provided by the internal phase locked loop  
(PLL) that requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with  
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,  
BCLK{0/1}_DN inputs are provided in Table 7-15.  
7.1.5.1  
PLL Power Supply  
An on-die PLL filter solution is implemented on the processor. Refer to Table 7-10 for  
DC specifications.  
7.1.6  
Joint Test Action Group (JTAG) and Test Access  
Port (TAP) Signals  
Due to the voltage levels supported by other components in the JTAG and Test Access  
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by  
any other components within the system. A translation buffer should be used to  
connect to the rest of the chain, unless one of the other components is capable of  
accepting an input of the appropriate voltage. Two copies of each signal may be  
required with each driving a different voltage level.  
7.1.7  
Processor Sideband Signals  
The processor includes asynchronous sideband signals that provide asynchronous  
input, output or I/O signals between the processor and the platform or PHC.Details are  
in Table 7-5.  
All processor asynchronous sideband input signals are required to be asserted/de-  
asserted for a defined number of BCLKs for the processor to recognize the proper signal  
state.  
7.1.8  
Power, Ground and Sense Signals  
Processors also include various other signals including power/ground and sense points.  
Details are in Table 7-5.  
7.1.8.1  
Power and Ground Lands  
All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their  
respective processor power planes, while all VSS lands must be connected to the  
system ground plane.  
For clean on-chip power distribution, processors include lands for all required voltage  
supplies. The lands are listed in Table 7-1.  
Datasheet  
53  
     
Electrical Specifications  
Table 7-1.  
Power and Ground Lands  
Power and  
Ground Lands  
Number of  
Lands  
Comments  
Each VCC land must be supplied with the voltage determined by the  
SVID Bus signals. Table 7-3 defines the voltage level associated with  
V
208  
3
CC  
each core SVID pattern. V has a VBOOT setting of 0.0V.  
CC  
Each VCCPLL land is connected to a 1.70 V supply to power the Phase  
Lock Loop (PLL) clock generation circuitry. An on-die PLL filter  
solution is implemented within the processor.  
V
CCPLL  
Each VCCD land is connected to a switchable 1.50V and 1.35V supply  
to provide power to the processor DDR3 interface. These supplies  
V
V
CCD_01  
CCD_23  
51  
also power the DDR3 memory subsystem. V  
is also controlled by  
CCD  
the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23.  
V
14  
19  
VTTA lands must be supplied by a fixed 1.0V supply.  
TTA  
V
V
lands must be supplied by a fixed 1.0V supply.  
TTD  
TTD  
Each VSA land must be supplied with the voltage determined by the  
V
25  
SVID Bus signals, typically set at 0.940V. V has a VBOOT setting of  
SA  
SS  
SA  
0.9V.  
V
548  
Ground  
7.1.8.2  
Decoupling Guidelines  
Due to its large number of transistors and high internal clock speeds, the processor is  
capable of generating large current swings between low and full power states. This may  
cause voltages on power planes to sag below their minimum values if bulk decoupling is  
not adequate. Large electrolytic bulk capacitors (C  
) help maintain the output  
BULK  
voltage during current transients; such as transients when coming out of an idle  
condition. Care must be used in the baseboard design to ensure that the voltages  
provided to the processor remain within the specifications listed in Table 7-10. Failure  
to do so can result in timing violations or reduced lifetime of the processor.  
7.1.8.3  
Voltage Identification (VID)  
The reference voltage or the VID setting is set using the SVID communication bus  
between the processor and the voltage regulator controller chip. The VID settings are  
the nominal voltages to be delivered to the processor VCC, VSA, VCCD lands. Table 7-3  
specifies the reference voltage level corresponding to the VID value transmitted over  
serial VID. The VID codes will change due to temperature and/or current load changes  
to minimize the power and to maximize the performance of the part. The specifications  
are set so that a voltage regulator can operate with all supported frequencies.  
Individual processor VID values may be calibrated during manufacturing such that two  
processor units with the same core frequency may have different default VID settings.  
The processor uses voltage identification signals to support automatic selection of V  
CC,  
V , and V  
power supply voltages. If the processor socket is empty (SKTOCC_N  
SA  
CCD  
high), or a “not supported” response is received from the SVID bus, the voltage  
regulation circuit cannot supply the voltage that is requested; the voltage regulator  
must disable itself or not power on. The Vout MAX register (30h) is programmed by the  
processor to set the maximum supported VID code and if the programmed VID code is  
higher than the VID supported by the VR, the VR will respond with a “not supported”  
acknowledgement.  
54  
Datasheet  
   
Electrical Specifications  
7.1.8.3.1  
Serial Voltage Identification (SVID) Commands  
The processor provides the ability to operate while transitioning to a new VID setting  
and its associated processor voltage rails (V V , and V ). This is represented by a  
CC, SA  
CCD  
DC shift. It should be noted that a low-to-high or high-to-low voltage state change may  
result in as many VID transitions as necessary to reach the target voltage. Transitions  
above the maximum specified VID are not supported. The processor supports the  
following VR commands:  
• SetVID_fast (20mV/μs for V , 10mV/μs for V /V  
),  
CC  
SA CCD  
• SetVID_slow (5mV/μs for V , 2.5mV/μs for V /V  
), and  
CC  
SA CCD  
• Slew Rate Decay (downward voltage only and it is a function of the output  
capacitance time constant) commands. Table 7-3 includes SVID step sizes and DC  
shift ranges. Minimum and maximum voltages must be maintained as shown in  
The VRM or EVRD used must be capable of regulating its output to the value defined by  
the new VID.  
Power source characteristics must be ensured to be stable when the supply to the  
voltage regulator is stable.  
7.1.8.3.2  
SetVID Fast Command  
The SetVID-fast command contains the target VID in the payload byte. The range of  
voltage is defined in the VID table. The VR should ramp to the new VID setting with a  
fast slew rate as defined in the slew rate data register; typically, 10 to 20 mV/μs  
depending on platform, voltage rail, and the amount of decoupling capacitance.  
The SetVID-fast command is preemptive; the VR interrupts its current processes and  
moves to the new VID. The SetVID-fast command operates on one VR address at a  
time. This command is used in the processor for package C6 fast exit and entry.  
7.1.8.3.3  
SetVID Slow Command  
The SetVID-slow command contains the target VID in the payload byte. The range of  
voltage is defined in the VID table. The VR should ramp to the new VID setting with a  
“slow” slew rate as defined in the slow slew rate data register. The SetVID_Slow is 1/4  
slower than the SetVID_fast slew rate.  
The SetVID-slow command is preemptive; that is, the VR interrupts its current  
processes and moves to the new VID. This is the instruction used for normal P-state  
voltage change. This command is used in the processor for the Intel Enhanced  
SpeedStep Technology transitions.  
7.1.8.3.4  
SetVID Decay Command  
The SetVID-Decay command is the slowest of the DVID transitions. It is only used for  
VID down transitions. The VR does not control the slew rate; the output voltage  
declines with the output load current only.  
The SetVID-Decay command is preemptive; that is, the VR interrupts its current  
processes and moves to the new VID.  
Datasheet  
55  
Electrical Specifications  
7.1.8.3.5  
SVID Power State Functions – SetPS  
The processor has three power state functions and these states will be set seamlessly  
with the SVID bus using the SetPS command. Based on the power state command, the  
SetPS commands send information to the VR controller to configure the VR to improve  
efficiency, especially at light loads. For example, typical power states are:  
• PS(00h): Represents full power or active mode  
• PS(01h): Represents a light load 5A to 20A  
• PS(02h): Represents a very light load <5A  
The VR may change its configuration to meet the processor power needs with greater  
efficiency. For example, it may reduce the number of active phases, transition from  
CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode,  
reduce the switching frequency or pulse skip, or change to asynchronous regulation.  
For example, typical power states are 00h = run in normal mode; a command of  
01h= shed phases mode, and an 02h=pulse skip.  
The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(00h)  
to PS(02h) for example. There are multiple VR design schemes that can be used to  
maintain a greater efficiency in these different power states; work with your VR  
controller suppliers for optimizations.  
The SetPS command sends a byte that is encoded as to what power state the VR  
should transition to.  
If a power state is not supported by the controller, the slave should acknowledge with  
command rejected (11b).  
If the VR is in a low-power state and receives a SetVID command moving the VID up,  
the VR exits the low-power state to normal mode (PS0) to move the voltage up as fast  
as possible. The processor must re-issue the low-power state (PS1 or PS2) command if  
it is in a low-current condition at the new higher voltage. See Figure 7-2 for VR power  
state transitions.  
Figure 7-2. Voltage Regulator (VR) Power-State Transitions  
56  
Datasheet  
 
Electrical Specifications  
7.1.8.3.6  
SVID Voltage Rail Addressing  
The processor addresses four different voltage rail control segments within VR12 (V ,  
CC  
V
, V  
, and V ). The SVID data packet contains a 4-bit addressing code.  
CCD_01  
CCD_23 SA  
Table 7-2.  
Serial Voltage Identification (SVID) Address Usage  
PWM Address (Hex)  
Processor  
00  
01  
02  
03  
04  
05  
V
V
cc  
sa  
V
CCD_01  
+1 not used  
V
CCD_23  
+1 not used  
Notes:  
1.  
2.  
3.  
Check with VR vendors for determining the physical address assignment method for their controllers.  
VR addressing is assigned on a per voltage rail basis.  
Dual VR controllers will have two addresses with the lowest order address, always being the higher phase  
count.  
4.  
For future platform flexibility, the VR controller should include an address offset, as shown with +1 not  
used.  
Table 7-3.  
VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 1 of 2)  
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
CC, SA  
CC, SA  
CC, SA  
CC, SA  
CC, SA  
CC, SA  
Hex  
Hex  
Hex  
Hex  
Hex  
Hex  
V
V
V
V
V
V
00  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
0.00000  
0.50000  
0.50500  
0.51000  
0.51500  
0.52000  
0.52500  
0.53000  
0.53500  
0.54000  
0.54500  
0.55000  
0.55500  
0.56000  
0.56500  
0.57000  
0.57500  
0.58000  
0.58500  
0.59000  
0.59500  
0.60000  
0.60500  
0.61000  
0.61500  
0.62000  
0.62500  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
0.67000  
0.67500  
0.68000  
0.68500  
0.69000  
0.69500  
0.70000  
0.70500  
0.71000  
0.71500  
0.72000  
0.72500  
0.73000  
0.73500  
0.74000  
0.74500  
0.75000  
0.75500  
0.76000  
0.76500  
0.77000  
0.77500  
0.78000  
0.78500  
0.79000  
0.79500  
0.80000  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
0.84500  
0.85000  
0.85500  
0.86000  
0.86500  
0.87000  
0.87500  
0.88000  
0.88500  
0.89000  
0.89500  
0.90000  
0.90500  
0.91000  
0.91500  
0.92000  
0.92500  
0.93000  
0.93500  
0.94000  
0.94500  
0.95000  
0.95500  
0.96000  
0.96500  
0.97000  
0.97500  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
1.02000  
1.02500  
1.03000  
1.03500  
1.04000  
1.04500  
1.05000  
1.05500  
1.06000  
1.06500  
1.07000  
1.07500  
1.08000  
1.08500  
1.09000  
1.09500  
1.10000  
1.10500  
1.11000  
1.11500  
1.12000  
1.12500  
1.13000  
1.13500  
1.14000  
1.14500  
1.15000  
BE  
BF  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
1.19500  
1.20000  
1.20500  
1.21000  
1.21500  
1.22000  
1.22500  
1.23000  
1.23500  
1.24000  
1.24500  
1.25000  
1.25500  
1.26000  
1.26500  
1.27000  
1.27500  
1.28000  
1.28500  
1.29000  
1.29500  
1.30000  
1.30500  
1.31000  
1.31500  
1.32000  
1.32500  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
1.37000  
1.37500  
1.38000  
1.38500  
1.39000  
1.39500  
1.40000  
1.40500  
1.41000  
1.41500  
1.42000  
1.42500  
1.43000  
1.43500  
1.44000  
1.44500  
1.45000  
1.45500  
1.46000  
1.46500  
1.47000  
1.47500  
1.48000  
1.48500  
1.49000  
1.49500  
1.50000  
Datasheet  
57  
   
Electrical Specifications  
Table 7-3.  
VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2)  
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
V
V
CCD  
,
CC, SA  
CC, SA  
CC, SA  
CC, SA  
CC, SA  
CC, SA  
Hex  
Hex  
Hex  
Hex  
Hex  
Hex  
V
V
V
V
V
V
4D  
4E  
4F  
50  
51  
52  
53  
54  
0.63000  
0.63500  
0.64000  
0.64500  
0.65000  
0.65500  
0.66000  
0.66500  
70  
71  
72  
73  
74  
75  
76  
77  
0.80500  
0.81000  
0.81500  
0.82000  
0.82500  
0.83000  
0.83500  
0.84000  
93  
94  
95  
96  
97  
98  
99  
9A  
0.98000  
0.98500  
0.99000  
0.99500  
1.00000  
1.00500  
1.01000  
1.01500  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
1.15500  
1.16000  
1.16500  
1.17000  
1.17500  
1.18000  
1.18500  
1.19000  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
1.33000  
1.33500  
1.34000  
1.34500  
1.35000  
1.35500  
1.36000  
1.36500  
FC  
FD  
FE  
FF  
1.50500  
1.51000  
1.51500  
1.52000  
Notes:  
1.  
2.  
3.  
4.  
00h = Off State  
VID Range HEX 01-32 are not used by the processor.  
For VID Ranges supported, see Table 7-10.  
V
is a fixed voltage of 1.35V or 1.5V.  
CCD  
7.1.9  
Reserved or Unused Signals  
All Reserved (RSVD) signals must not be connected. Connection of these signals to V ,  
CC  
V
, V  
, V  
V
, V , or to any other signal (including each other) can result in  
TTA  
TTD  
CCD, CCPLL SS  
component malfunction or incompatibility with future processors. See Chapter 8 for a  
land listing of the processor and the location of all Reserved (RSVD) signals.  
For reliable operation, always connect unused inputs or bi-directional signals to an  
appropriate signal level. Unused active high inputs should be connected through a  
resistor to ground (V ). Unused outputs may be left unconnected; however, this may  
SS  
interfere with some Test Access Port (TAP) functions, complicate debug probing, and  
prevent boundary scan testing. A resistor must be used when tying bi-directional  
signals to power or ground. When tying any signal to power or ground, a resistor will  
also allow for system testability.  
7.2  
Signal Group Summary  
Signals are grouped by buffer type and similar characteristics as listed in Table 7-5. The  
buffer type indicates which signaling technology and specifications apply to the signals.  
Table 7-4.  
Signal Description Buffer Types  
Signal  
Description  
Analog  
Analog reference or output. May be used as a threshold voltage or for buffer  
compensation  
Asynchronous  
CMOS  
Signal has no timing relationship with any system reference clock.  
CMOS buffers: 1.0V or 1.5V tolerant  
DDR3  
DDR3 buffers: 1.5V and 1.35V tolerant  
DMI2  
Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*  
2.0 and 1.0 Signaling Environment AC Specifications.  
Open Drain CMOS  
PCI Express*  
Open Drain CMOS (ODCMOS) buffers: 1.0V tolerant  
PCI Express* interface signals. These signals are compatible with PCI Express 3.0  
Signalling Environment AC Specifications and are AC coupled. The buffers are not  
3.3-V tolerant. Refer to the PCI Express specification.  
Reference  
SSTL  
Voltage reference signal.  
Source Series Terminated Logic (JEDEC SSTL_15)  
Note:  
1.  
Qualifier for a buffer type.  
58  
Datasheet  
       
Electrical Specifications  
Table 7-5.  
Signal Groups (Sheet 1 of 3)  
Differential /  
Single Ended  
1
Buffer Type  
Signals  
2
DDR3 Reference Clocks  
Differential  
SSTL Output  
DDR{0/1/2/3}_CLK_D[N/P][3:0]  
2
DDR3 Command Signals  
DDR{0/1/2/3}_BA[2:0]  
DDR{0/1/2/3}_CAS_N  
DDR{0/1/2/3}_MA[15:00]  
DDR{0/1/2/3}_MA_PAR  
DDR{0/1/2/3}_RAS_N  
DDR{0/1/2/3}_WE_N  
SSTL Output  
Single ended  
CMOS1.5v Output  
DDR_RESET_C{01/23}_N  
2
DDR3 Control Signals  
DDR{0/1/2/3}_CS_N[9:0]  
DDR{0/1/2/3}_ODT[5:0]  
DDR{0/1/2/3}_CKE[5:0]  
CMOS1.5v Output  
Single ended  
Reference Output  
Reference Input  
DDR_VREFDQTX_C{01/23}  
DDR_VREFDQRX_C{01/23}  
DDR{01/23}_RCOMP[2:0]  
2
DDR3 Data Signals  
Differential  
SSTL Input/Output  
SSTL Input/Output  
SSTL Input  
DDR{0/1/2/3}_DQS_D[N/P][17:00]  
DDR{0/1/2/3}_DQ[63:00]  
Single ended  
DDR{0/1/2/3}_PAR_ERR_N  
2
DDR3 Miscellaneous Signals  
Single ended  
CMOS1.5v Input  
DRAM_PWR_OK_C{01/23}  
PCI Express* Port 1, 2, and 3 Signals  
PE1A_RX_D[N/P][3:0]  
PE1B_RX_D[N/P][7:4]  
PE2A_RX_D[N/P][3:0]  
PE2B_RX_D[N/P][7:4]  
PE2C_RX_D[N/P][11:8]  
PE2D_RX_D[N/P][15:12]  
PE3A_RX_D[N/P][3:0]  
PE3B_RX_D[N/P][7:4]  
PE3C_RX_D[N/P][11:8]  
PE3D_RX_D[N/P][15:12]  
Differential  
PCI Express* Input  
PE1A_TX_D[N/P][3:0]  
PE1B_TX_D[N/P][7:4]  
PE2A_TX_D[N/P][3:0]  
PE2B_TX_D[N/P][7:4]  
PE2C_TX_D[N/P][11:8]  
PE2D_TX_D[N/P][15:12]  
PE3A_TX_D[N/P][3:0]  
PE3B_TX_D[N/P][7:4]  
PE3C_TX_D[N/P][11:8]  
PE3D_TX_D[N/P][15:12]  
Differential  
PCI Express* Output  
Datasheet  
59  
 
Electrical Specifications  
Table 7-5.  
Signal Groups (Sheet 2 of 3)  
Differential /  
Single Ended  
1
Buffer Type  
Signals  
PCI Express* Miscellaneous Signals  
Analog Input  
Single ended  
PE_RBIAS_SENSE  
PE_RBIAS  
PE_VREF_CAP  
Reference Input/Output  
DMI2/PCI Express* Signals  
DMI2 Input  
DMI2 Output  
Platform Environmental Control Interface (PECI)  
DMI_RX_D[N/P][3:0]  
DMI_TX_D[N/P][3:0]  
Differential  
Single ended  
PECI  
PECI  
System Reference Clock (BCLK{0/1})  
Differential  
CMOS1.0v Input  
BCLK{0/1}_D[N/P]  
SMBus  
DDR_SCL_C{01/23}  
DDR_SDA_C{01/23}  
PEHPSCL  
Open Drain CMOS  
Input/Output  
Single ended  
PEHPSDA  
JTAG and TAP Signals  
CMOS1.0v Input  
TCK, TDI, TMS, TRST_N  
PREQ_N  
CMOS1.0v Input/Output  
CMOS1.0v Output  
PRDY_N  
Single ended  
BPM_N[7:0]  
EAR_N  
Open Drain CMOS  
Input/Output  
Open Drain CMOS Output  
TDO  
Serial VID Interface (SVID) Signals  
CMOS1.0v Input  
SVIDALERT_N  
SVIDDATA  
Open Drain CMOS  
Single ended  
Input/Output  
Open Drain CMOS Output  
SVIDCLK  
Processor Asynchronous Sideband Signals  
BIST_ENABLE  
PWRGOOD  
PMSYNC  
CMOS1.0v Input  
RESET_N  
SAFE_MODE_BOOT  
TXT_AGENT  
TXT_PLTEN  
Single ended  
CAT_ERR_N  
MEM_HOT_C{01/23}_N  
PROCHOT_N  
Open Drain CMOS  
Input/Output  
ERROR_N[2:0]  
THERMTRIP_N  
Open Drain CMOS Output  
Miscellaneous Signals  
IVT_ID_N  
SKTOCC_N  
N/A  
Output  
60  
Datasheet  
Electrical Specifications  
Table 7-5.  
Signal Groups (Sheet 3 of 3)  
Differential /  
Single Ended  
1
Buffer Type  
Signals  
Power/Other Signals  
Power / Ground  
V
, V  
V
V
V
V
V
V
CC  
TTA, TTD, CCD_01, CCD_23, CCPLL, SA and SS  
VCC_SENSE  
VSS_VCC_SENSE  
VSS_VTTD_SENSE  
VTTD_SENSE  
Sense Points  
VSA_SENSE  
VSS_VSA_SENSE  
Notes:  
1.  
2.  
Refer to Chapter 6 for signal description details.  
DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2 and DDR3 Channel 3.  
Table 7-6.  
Signals with On-Die Termination  
Pull-Up /  
Signal Name  
Rail  
Value  
Units  
Notes  
Pull-Down  
DDR{0/1}_PAR_ERR_N  
DDR{2/3}_PAR_ERR_N  
TXT_AGENT  
Pull-Up  
Pul-Up  
VCCD_01  
VCCD_23  
VSS  
65  
65  
2K  
2K  
2K  
2K  
2K  
Pull-Down  
Pull-Down  
Pul-Up  
SAFE_MODE_BOOT  
BIST_ENABLE  
VSS  
VTT  
TXT_PLTEN  
Pul-Up  
VTT  
EAR_N  
Pull-Up  
VTT  
1
Notes:  
1.  
Refer to Table 7-17 for details on the R  
(Buffer on Resistance) value for this signal.  
ON  
7.3  
Power-On Configuration (POC) Options  
Several configuration options can be configured by hardware. The processor samples  
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or  
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these  
options, refer to Table 7-7.  
The sampled information configures the processor for subsequent operation. These  
configuration options cannot be changed, except by another reset transition of the  
latching signal (RESET_N or PWRGOOD).  
Table 7-7.  
Power-On Configuration Option Lands  
Configuration Option  
Land Name  
Notes  
Output tri state  
PROCHOT_N  
BIST_ENABLE  
TXT_PLTEN  
1
2
3
3
3
3
Execute BIST (Built-In Self Test)  
®
®
Enable Intel Trusted Execution Technology (Intel TXT) Platform  
Power-up Sequence Halt for ITP configuration  
Enable Intel Trusted Execution Technology (Intel TXT) Agent  
Enable Safe Mode Boot  
EAR_N  
TXT_AGENT  
SAFE_MODE_BOOT  
Notes:  
1.  
Output tri-state option enables Fault Resilient Booting (FRB). The RESET_N signal is used to latch  
PROCHOT_N for enabling FRB mode.  
2.  
3.  
BIST_ENABLE is sampled at RESET_N de-assertion (on the falling edge).  
This signal is sampled after PWRGOOD assertion.  
Datasheet  
61  
       
Electrical Specifications  
7.4  
Absolute Maximum and Minimum Ratings  
Table 7-8 specifies absolute maximum and minimum ratings. At conditions outside  
functional operation condition limits, but within absolute maximum and minimum  
ratings, neither functionality nor long-term reliability can be expected. If a device is  
returned to conditions within functional operation limits after having been subjected to  
conditions outside these limits, but within the absolute maximum and minimum  
ratings, the device may be functional; however, with its lifetime degraded depending on  
exposure to conditions exceeding the functional operation condition limits.  
Although the processor contains protective circuitry to resist damage from Electro-  
Static Discharge (ESD), precautions should always be taken to avoid high static  
voltages or electric fields.  
Table 7-8.  
Processor Absolute Minimum and Maximum Ratings  
1,2  
Symbol  
Parameter  
Min  
Max  
Unit  
Notes  
Processor core voltage with respect to  
SS  
V
V
V
-0.3  
1.4  
V
CC  
V
Processor PLL voltage with respect to  
-0.3  
-0.3  
2.0  
V
V
CCPLL  
CCD  
V
SS  
Processor I/O supply voltage for DDR3  
(standard voltage) with respect to V  
1.85  
SS  
Processor I/O supply voltage for DDR3L  
(low Voltage) with respect to V  
V
V
-0.3  
-0.3  
-0.3  
1.7  
1.4  
1.4  
V
V
V
CCD  
SA  
SS  
Processor SA voltage with respect to V  
SS  
V
V
Processor analog I/O voltage with  
TTA  
TTD  
respect to V  
SS  
Notes:  
1.  
For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must  
be satisfied.  
2.  
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.  
7.4.1  
Storage Conditions Specifications  
Environmental storage condition limits define the temperature and relative humidity  
limits to which the device is exposed to while being stored in a Moisture Barrier Bag.  
The specified storage conditions are for component level prior to board attach (see  
notes in Table 7-9 for post board attach limits).  
Table 7-9 specifies absolute maximum and minimum storage temperature limits that  
represent the maximum or minimum device condition beyond which damage, latent or  
otherwise, may occur. The table also specifies sustained storage temperature, relative  
humidity, and time-duration limits. These limits specify the maximum or minimum  
device storage conditions for a sustained period of time. At conditions outside sustained  
limits, but within absolute maximum and minimum ratings, quality and reliability may  
be affected.  
Table 7-9.  
Storage Condition Ratings (Sheet 1 of 2)  
Symbol  
Parameter  
Min  
Max  
Unit  
The minimum/maximum device storage temperature  
beyond which damage (latent or otherwise) may  
occur when subjected to for any length of time.  
T
-25  
125  
°C  
absolute storage  
The minimum/maximum device storage temperature  
for a sustained period of time.  
T
-5  
40  
°C  
sustained storage  
62  
Datasheet  
       
Electrical Specifications  
Table 7-9.  
Storage Condition Ratings (Sheet 2 of 2)  
Symbol  
Parameter  
Min  
Max  
Unit  
The ambient storage temperature (in shipping media)  
for a short period of time.  
T
-20  
85  
°C  
short term storage  
The maximum device storage relative humidity for a  
sustained period of time.  
RH  
60% @ 24  
°C  
sustained storage  
A prolonged or extended period of time; typically  
associated with sustained storage conditions  
Unopened bag, includes 6 months storage time by  
customer.  
Time  
0
0
30  
72  
months  
hours  
sustained storage  
A short period of time (in shipping media).  
Time  
short term storage  
Notes:  
1.  
Storage conditions are applicable to storage environments only. In this scenario, the processor must not  
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect  
the long-term reliability of the device. For functional operation, refer to the processor case temperature  
specifications in the appropriate processor Thermal Mechanical Specifications and Design Guide (see  
Related Documents section).  
2.  
3.  
4.  
These ratings apply to the Intel component and do not include the tray or packaging.  
Failure to adhere to this specification can affect the long-term reliability of the processor.  
Non-operating storage limits post board attach: Storage condition limits for the component once attached  
to the application board are not specified. Intel does not conduct component level certification assessments  
post board attach given the multitude of attach methods, socket types and board types used by customers.  
Provided as general guidance only, Intel board products are specified and certified to meet the following  
temperature and humidity limits (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to  
90%, non condensing with a maximum wet bulb of 28 °C).  
5.  
Device storage temperature qualification methods follow JEDEC* High and Low Temperature Storage Life  
Standards: JESD22-A119 (low temperature) and JESD22-A103 (high temperature).  
7.5  
DC Specifications  
DC specifications are defined at the processor pads, unless otherwise noted.  
DC specifications are only valid while meeting specifications for case temperature, clock  
frequency, and input voltages. Care should be taken to read all notes associated with  
each specification. For case temperature specifications, refer to the appropriate  
processor Thermal Mechanical Specifications and Design Guide (see Related Documents  
section).  
7.5.1  
Voltage and Current Specifications  
Table 7-10. Voltage Specifications (Sheet 1 of 2)  
Voltage  
Plane  
1
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Notes  
V
VID Range  
V
V
VID  
CC  
0.6  
1.35  
V
2, 3  
CC  
Retention Voltage  
VID in package C3  
and C6 states  
Retention  
VID  
0.65  
V
2, 3  
V
V
V
Loadline Slope  
Tolerance Band  
Ripple  
3, 4, 7, 8,  
11, 13, 18  
CC  
CC  
CC  
V
V
LL  
V
V
0.8  
15  
5
m  
mV  
mV  
CC  
CC  
CC  
CC  
CC  
3, 4, 7, 8,  
11, 13, 18  
TOB  
Ripple  
3, 4, 7, 8,  
11, 13, 18  
V
V
Vcc  
VID step size during  
a transition  
VID_STEP  
5.0  
1.7  
mV  
V
10  
(Vcc, Vsa,  
Vccd)  
PLL Voltage  
11, 12, 13,  
17  
V
V
0.955*V  
1.045*V  
CCPLL_TYP  
CCPLL  
CCPLL  
CCPLL_TYP  
Datasheet  
63  
     
Electrical Specifications  
Table 7-10. Voltage Specifications (Sheet 2 of 2)  
Voltage  
Plane  
1
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Notes  
V
(
V
I/O Voltage for  
DDR3 (Standard  
Voltage)  
CCD  
CCD_01,  
CCD_23)  
11, 13, 14,  
16, 17  
V
V
0.95*V  
1.5  
1.05*V  
CCD_TYP  
V
CCD  
CCD_TYP  
V
VTTD)  
V
Uncore Voltage  
3, 5, 9, 12,  
13  
TT ( TTA,  
V
0.957*V  
1.00  
1.043*V  
TT_TYP  
V
V
TT  
TT_TYP  
Vsa VID Range  
V
V
V
0.6  
0.940  
1.25  
2, 3, 14, 15  
SA_VID  
SA  
SA  
System Agent  
Voltage  
3, 6, 12,  
14, 19  
V
V
- 0.057  
V
V + 0.057  
SA_VID  
V
SA  
SA_VID  
SA_VID  
Notes:  
1.  
2.  
3.  
4.  
Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on pre-silicon  
characterization.  
Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have  
different settings.  
These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is  
required.  
The V voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE and  
CC  
VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth  
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M  
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external  
noise from the system is not coupled in the scope probe.  
5.  
6.  
The V  
and V  
voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and  
TTA,  
TTD  
VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth  
oscilloscope limit (or DC to 20MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M  
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external  
noise from the system is not coupled in the scope probe.  
The V voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE and  
SA  
VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth  
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 M  
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external  
noise from the system is not coupled in the scope probe.  
7.  
8.  
9.  
The processor should not be subjected to any static V level that exceeds the V  
associated with any particular current.  
CC  
CC_MAX  
Failure to adhere to this specification can shorten processor lifetime.  
Minimum V and maximum I are specified at the maximum processor case temperature (T  
). I  
is specified at the  
CC  
CC_MAX  
CC  
CC  
CASE  
CC_MAX  
relative V  
point on the V load line. The processor is capable of drawing I  
for up to 5 seconds.  
CC_MAX  
The processor should not be subjected to any static V  
current. Failure to adhere to this specification can shorten processor lifetime.  
V
level that exceeds the V  
associated with any particular  
TTA, TTD  
TT_MAX  
10. This specification represents the V reduction or V increase due to each VID transition, see Section 7.1.8.3.  
CC  
CC  
11. Baseboard bandwidth is limited to 20 MHz.  
12. N/A  
13. DC + AC + Ripple = Total Tolerance  
14. For Power State Functions see Section 7.1.8.3.5.  
15.  
16.  
V
V
does not have a loadline, the output voltage is expected to be the VID value.  
SA_VID  
CCD  
17. The V  
tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*V  
.
CCD  
, V  
CCD23  
, V  
voltage specification requirements are measured across vias on the platform. Choose V  
,
CCPLL  
CCD01  
CCD23  
CCPLL  
V
, or V  
vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit (or DC to 20 MHz  
CCD01  
for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1M minimum impedance. The maximum  
length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in  
the scope probe.  
18.  
19.  
V
V
has a Vboot setting of 0.0V and is not included in the PWRGOOD indication.  
has a Vboot setting of 0.9V.  
CC  
SA  
64  
Datasheet  
Electrical Specifications  
Table 7-11. Current Specifications  
Processor TDP / Core  
Count  
1
Parameter Symbol and Definition  
TDC (A)  
Max (A)  
Notes  
I
CC  
130W 6-core, 4-core  
130W 6-core, 4-core  
130W 6-core, 4-core  
130W 6-core, 4-core  
130W 6-core, 4-core  
130W 6-core, 4-core  
130W 6-core, 4-core  
135  
165  
4, 5  
Core Supply, Processor Current on V  
CC  
I
TT  
20  
20  
3
24  
24  
4
4, 5  
4, 5  
4, 5  
4, 5  
4, 5  
4
I/O Termination Supply, Processor Current on  
V
/V  
TTA TTD  
I
SA  
System Agent Supply, Processor Current on  
V
SA  
I
CCD_01  
DDR3 Supply, Processor Current V  
CCD_01  
I
CCD_23  
3
4
DDR3 Supply, Processor Current V  
CCD_23  
I
CCPLL  
2
2
PLL Supply, Processor Current on V  
CCPLL  
I
I
V
DDR3 Supply, Current  
in System S3 Standby  
CCD_01_23, CCD_23_23  
on V  
0.5  
CCD_01/ CCD_23  
State  
Notes:  
1.  
Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon  
characterization.  
2.  
I
(Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing  
CC_TDC  
indefinitely and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for  
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion.  
3.  
4.  
Specification is at T  
= 50 C. Characterized by design (not tested).  
CASE  
CCD_23_MAX  
I
and I  
refers only to the processor current draw and does not account for the current consumption by  
CCD_01_MAX  
the memory devices. Memory Standby Current is characterized by design and not tested.  
5.  
Minimum V and maximum I are specified at the maximum processor case temperature (T  
). I  
is specified at the  
CC  
CC  
CASE  
CC_MAX  
relative V  
point on the V load line. The processor is capable of drawing I  
for up to 5 seconds. Refer to  
CC_MAX  
CC  
CC_MAX  
Figure 7-3 for further details on the average processor current draw over various time durations.  
Datasheet  
65  
 
Electrical Specifications  
7.5.2  
Die Voltage Validation  
Core voltage (V ) overshoot events at the processor must meet the specifications in  
CC  
Table 7-12 when measured across the VCC_SENSE and VSS_VCC_SENSE lands.  
Overshoot events that are < 10 ns in duration may be ignored. These measurements of  
processor die level overshoot should be taken with a 100 MHz bandwidth limited  
oscilloscope.  
7.5.2.1  
V
Overshoot Specifications  
CC  
The processor can tolerate short transient overshoot events where V exceeds the VID  
CC  
voltage when transitioning from a high-to-low current load condition. This overshoot  
cannot exceed VID + V  
(V  
is the maximum allowable overshoot above  
OS_MAX  
OS_MAX  
VID). These specifications apply to the processor die voltage as measured across the  
VCC_SENSE and VSS_VCC_SENSE lands.  
Table 7-12. V  
Overshoot Specifications  
CC  
Symbol  
Parameter  
Min  
Max  
Units  
Figure  
Notes  
V
Magnitude of V overshoot above VID  
65  
mV  
OS_MAX  
CC  
Time duration of V overshoot above VccMAX  
CC  
value at the new lighter load  
T
25  
ms  
OS_MAX  
Figure 7-3. V  
Overshoot Example Waveform  
CC  
Notes:  
1.  
2.  
3.  
4.  
V
is the measured overshoot voltage.  
OS_MAX  
OS_MAX  
T
is the measured time duration above VccMAX(I1).  
Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1.  
VccMAX(I1) = VID - I1*RLL + 15mV  
66  
Datasheet  
     
Electrical Specifications  
7.5.3  
Signal DC Specifications  
DC specifications are defined at the processor pads, unless otherwise noted.  
DC specifications are only valid while meeting specifications for case temperature, clock  
frequency, and input voltages. Care should be taken to read all notes associated with  
each specification.  
Table 7-13. DDR3 and DDR3L Signal DC Specifications (Sheet 1 of 2)  
1
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Notes  
I
Input Leakage Current  
-1.4  
+1.4  
mA  
10  
IL  
Data Signals  
V
V
Input Low Voltage  
Input High Voltage  
0.43*V  
V
V
2, 3  
IL  
CCD  
0.57*V  
21  
2, 4, 5  
6
IH  
CCD  
DDR3 Data Buffer On  
Resistance  
R
31  
ON  
On-Die Termination for Data  
Signals  
45  
90  
55  
110  
Data ODT  
8
On-Die Termination for  
Parity Error Signals  
PAR_ERR_N ODT  
59  
72  
Reference Clock Signals, Command, and Data Signals  
Output Low Voltage  
(V  
ON  
/ 2)* (R  
VTT_TERM  
CCD  
ON  
V
V
V
V
2, 7  
OL  
/(R +R  
))  
Output High Voltage  
V
((V  
/ 2)*  
CCD  
CCD –  
2, 5, 7  
OH  
(R /(R +R ))  
VTT_TERM  
ON  
ON  
Reference Clock Signal  
DDR3 Clock Buffer On  
Resistance  
R
21  
31  
6
ON  
Command Signals  
DDR3 Command Buffer On  
Resistance  
R
R
V
16  
25  
24  
75  
V
6
6
ON  
DDR3 Reset Buffer On  
Resistance  
ON  
Output Low Voltage, Signals  
DDR_RESET_ C{01/23}_N  
0.2*V  
1, 2  
OL_CMOS1.5v  
CCD  
Output High Voltage,  
Signals  
DDR_RESET_ C{01/23}_N  
V
0.9*V  
V
1, 2  
1, 2  
OH_CMOS1.5v  
CCD  
I
Input Leakage Current  
-100  
+100  
A  
IL_CMOS1.5v  
Control Signals  
DDR3 Control Buffer On  
Resistance  
R
21  
31  
6
ON  
DDR01_RCOMP[0]  
DDR01_RCOMP[1]  
DDR01_RCOMP[2]  
DDR23_RCOMP[0]  
DDR23_RCOMP[1]  
DDR23_RCOMP[2]  
COMP Resistance  
COMP Resistance  
COMP Resistance  
COMP Resistance  
COMP Resistance  
COMP Resistance  
128.7  
25.839  
198  
130  
26.1  
200  
130  
26.1  
200  
131.3  
26.361  
202  
9, 12  
9, 12  
9, 12  
9, 12  
9, 12  
9, 12  
128.7  
25.839  
198  
131.3  
26.361  
202  
Datasheet  
67  
   
Electrical Specifications  
Table 7-13. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)  
1
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Notes  
DDR3 Miscellaneous Signals  
Input Low Voltage  
DRAM_PWR_OK_C{01/23}  
0.55*V  
+
2, 3,  
CCD  
V
V
V
V
IL  
0.2  
11, 13  
Input High Voltage  
DRAM_PWR_OK_C{01/23}  
0.55*V  
+ 0.3  
2, 4, 5,  
11, 13  
CCD  
IH  
Notes:  
1.  
2.  
Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
The voltage rail V  
processor.  
which will be set to 1.50V or 1.35V nominal depending on the voltage of all DIMMs connected to the  
CCD  
3.  
4.  
5.  
V
V
V
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.  
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.  
IL  
IH  
IH  
and V  
may experience excursions above V  
. However, input signal drivers must comply with the signal quality  
OH  
CCD  
specifications.  
This is the pull down driver resistance. Reset drive does not have a termination.  
6.  
7.  
8.  
9.  
R
is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM datasheet.  
VTT_TERM  
The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.  
COMP resistance must be provided on the system board with 1% resistors. DDR01_RCOMP[2:0] and DDR23_RCOMP[2:0]  
resistors are terminated to V  
.
SS  
10. Input leakage current is specified for all DDR3 signals.  
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300mV and -200mV and the  
edge must be monotonic.  
12. The DDR01/23_RCOMP error tolerance is ±15% from the compensated value.  
13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling can be  
used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of  
specification. For details, refer to the processor Datasheet, Volume 2 of 2; see Related Documents section.  
Table 7-14. PECI DC Specifications  
1
Symbol  
Definition and Conditions  
Input Voltage Range  
Min  
Max  
Units Figure Notes  
V
V
V
V
-0.150  
0.100 * V  
0.275 * V  
0.550 * V  
V
V
V
V
V
2
In  
TT  
Hysteresis  
Hysteresis  
TT  
TT  
TT  
Negative-edge threshold voltage  
Positive-edge threshold voltage  
High level output source  
0.500 * V  
0.725 * V  
N
P
TT  
2
TT  
I
I
-6.0  
50  
mA  
3
SOURCE  
Leak+  
V
= 0.75 * V  
TT  
OH  
High impedance state leakage to V  
OL  
(V  
=
TTD  
leak  
200  
μA  
V
)
R
C
V
Buffer On Resistance  
20  
N/A  
36  
10  
ON  
Bus capacitance per node  
pF  
4, 5  
Bus  
Signal noise immunity above 300 MHz  
0.100 * V  
N/A  
V
p-p  
Noise  
TT  
Output Edge Rate (50 ohm to VSS, between V  
IL  
1.5  
4
V/ns  
and V  
)
IH  
Notes:  
1.  
2.  
V
supplies the PECI interface. PECI behavior does not affect V  
minimum/maximum specification  
TTD  
TTD  
It is expected that the PECI driver will take into account the variance in the receiver input thresholds and be able to drive its  
output within safe limits (-0.150V to 0.275*V for the low level and 0.725*V to V +0.150V for the high level).  
TTD  
TTD  
TTD  
3.  
4.  
The leakage specification applies to powered devices on the PECI bus.  
One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional  
nodes.  
5.  
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit  
rate at which the interface can operate.  
68  
Datasheet  
 
Electrical Specifications  
Table 7-15. System Reference Clock (BCLK{0/1}) DC Specifications  
1
Symbol  
Parameter  
Signal  
Min  
Max  
Unit Figure Notes  
V
V
V
Differential Input High Voltage  
Differential Input Low Voltage  
Absolute Crossing Point  
Differential  
Differential  
Single Ended  
0.150  
N/A  
V
V
V
BCLK_diff_ih  
BCLK_diff_il  
-0.150  
0.550  
(abs)  
0.250  
2, 4, 7  
cross  
cross  
Relative Crossing Point  
0.250 +  
0.550 +  
V
(rel)  
Single Ended  
0.5*(VH  
0.5*(VH  
V
3, 4, 5  
avg  
avg  
0.700)  
0.700)  
V  
Range of Crossing Points  
Threshold Voltage  
Single Ended  
Single Ended  
N/A  
N/A  
0.140  
V
V
6
8
cross  
V
Vcross - 0.1  
Vcross + 0.1  
1.50  
TH  
I
Input Leakage Current  
Pad Capacitance  
A  
pF  
IL  
C
N/A  
0.9  
1.2  
pad  
Notes:  
1.  
Unless otherwise noted, all specifications in this table apply to all processor frequencies. These specifications are specified at  
the processor pad.  
2.  
Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling  
edge of BCLK{0/1}_DP.  
3.  
4.  
5.  
6.  
7.  
8.  
V
is the statistical average of the VH measured by the oscilloscope.  
Havg  
The crossing point must meet the absolute and relative crossing point specifications simultaneously.  
V
V
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.  
is defined as the total variation of all crossing voltages as defined in Note 3.  
Havg  
CROSS  
The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.  
For Vin between 0 and V  
.
IH  
Table 7-16. SMBus DC Specifications  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
V
V
V
V
R
Input Low Voltage  
Input High Voltage  
Hysteresis  
0.7*VTT  
0.1*VTT  
0.3*V  
V
V
IL  
TT  
IH  
V
Hysteresis  
Output Low Voltage  
Buffer On Resistance  
Leakage Current  
0.2*V  
14  
V
OL  
TT  
4
ON  
I
50  
200  
0.6  
A  
V/ns  
L
Output Edge Rate (50 ohm to V , between V and V )  
IH  
0.05  
TT  
IL  
Datasheet  
69  
   
Electrical Specifications  
Table 7-17. Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals DC  
Specifications  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
V
V
V
V
V
V
Input Low Voltage  
0.7*V  
0.3*V  
V
V
V
V
V
V
IL  
TT  
TT  
TT  
Input High Voltage  
Input Low Voltage: PREQ_N  
Input High Voltage: PREQ_N  
Output Low Voltage  
Hysteresis  
IH  
TT  
TT  
TT  
0.4*V  
IL  
0.8*V  
IH  
0.2*V  
OL  
0.1*V  
Hysteresis  
Buffer On Resistance  
BPM_N[7:0], PRDY_N, TDO  
R
4
14  
ON  
I
Input Leakage Current  
50  
200  
A  
IL  
Input Edge Rate  
0.05  
0.2  
V/ns  
V/ns  
1, 2  
1
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI,  
TMS, TRST_N  
Output Edge Rate (50 ohm to V  
)
TT  
1.5  
Signal: BPM_N[7:0], PRDY_N, TDO  
Note:  
1.  
2.  
These signals are measured between V and V  
.
IL  
IH  
The signal edge rate must be met or the signal must transition monotonically to the asserted state.  
Table 7-18. Serial VID Interface (SVID) DC Specifications  
Symbol  
Parameter  
Processor I/O Voltage  
Min  
Typ  
Max  
Units  
Notes  
V
V
VTT – 3%  
1.0  
VTT + 3%  
V
TT  
Input Low Voltage  
Signals SVIDDATA, SVIDALERT_N  
0.4*V  
V
V
1
1
IL  
TT  
Input High Voltage  
Signals SVIDDATA, SVIDALERT_N  
V
0.7*V  
IH  
TT  
Output Low Voltage  
Signals SVIDCLK, SVIDDATA  
V
V
R
0.3*V  
V
V
1
1
OL  
TT  
Hysteresis  
0.05*V  
4
Hysteresis  
ON  
TT  
Buffer On Resistance  
Signals SVIDCLK, SVIDDATA  
14  
W
2
I
Input Leakage Current  
±50  
0.05  
0.20  
±200  
A  
3
IL  
Input Edge Rate  
Signal: SVIDALERT_N  
V/ns  
V/ns  
4, 5  
4
Output Edge Rate (50 ohm to V  
)
1.5  
TT  
Notes:  
1.  
2.  
3.  
4.  
5.  
V
refers to instantaneous V .  
TT TT  
Measured at 0.31*V  
TT  
Vin between 0V and V  
These are measured between V and V  
The signal edge rate must be met or the signal must transition monotonically to the asserted state.  
TT  
.
IH  
IL  
70  
Datasheet  
   
Electrical Specifications  
Table 7-19. Processor Asynchronous Sideband DC Specifications  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
CMOS1.0v Signals  
V
V
V
Input Low Voltage  
Input High Voltage  
Hysteresis  
0.7*V  
0.1*V  
50  
0.3*V  
V
V
1, 2  
1, 2  
1, 2  
1, 2  
IL_CMOS1.0v  
IH_CMOS1.0v  
Hysteresis  
TT  
TT  
TT  
V
I
Input Leakage Current  
200  
A  
IL_CMOS1.0v  
Open Drain CMOS (ODCMOS) Signals  
Input Low Voltage  
Signals: MEM_HOT_C01/23_N, PROCHOT_N  
V
V
0.3*V  
0.4*V  
V
V
1, 2  
1,2  
IL_ODCMOS  
IL_ODCMOS  
TT  
TT  
Input Low Voltage  
Signals: CAT_ERR_N  
V
V
Input High Voltage  
Output Low Voltage  
0.7*V  
V
V
1, 2  
1, 2  
IH_ODCMOS  
OL_ODCMOS  
TT  
0.2*V  
TT  
Hysteresis  
V
V
0.1*V  
V
V
1, 2  
1, 2  
Hysteresis  
TT  
Signals: MEM_HOT_C01/23_N, PROCHOT_N  
Hysteresis  
Signal: CAT_ERR_N  
0.05*V  
Hysteresis  
TT  
I
Input Leakage Current  
Buffer On Resistance  
Output Edge Rate  
50  
4
200  
14  
A  
Leak  
R
W
1, 2  
3
ON  
0.05  
0.2  
0.60  
1.5  
V/ns  
V/ns  
Signal:MEM_HOT_C{01/23}_N, ERROR_N[2:0],  
THERMTRIP, PROCHOT_N  
Output Edge Rate  
Signal: CAT_ERR_N  
3
Notes:  
1.  
2.  
3.  
This table applies to the processor sideband and miscellaneous signals specified in Table 7-5.  
Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
These signals are measured between V and V  
.
IL  
IH  
Table 7-20. Miscellaneous Signals DC Specifications  
Symbol  
Parameter  
Min  
Typical  
Max  
Units  
Notes  
IVT_ID_N Signal  
V
Output Absolute Maximum Voltage  
Output Current  
1.10  
1.80  
0
V
O_ABS_MAX  
I
A  
1
O
SKTOCC_N Signal  
V
Output Absolute Maximum Voltage  
Output Maximum Current  
3.30  
3.50  
1
V
O_ABS_MAX  
I
mA  
OMAX  
Notes:  
1.  
IVT_ID_N land is a no connect on the die.  
Datasheet  
71  
   
Electrical Specifications  
7.5.3.1  
7.5.3.2  
7.5.3.3  
PCI Express* DC Specifications  
The processor DC specifications for the PCI Express* are available in the PCI Express  
Base Specification, Revision 3.0. This document will provide only the processor  
exceptions to the PCI Express Base Specification, Revision 3.0.  
DMI2/PCI Express* DC Specifications  
The processor DC specifications for the DMI2/PCI Express* are available in the PCI  
Express Base Specification, Revisions 2.0 and 1.0. This document will provide only the  
processor exceptions to the PCI Express Base Specification, Revisions 2.0 and 1.0.  
Reset and Miscellaneous Signal DC Specifications  
For a power-on Reset, RESET_N must stay active for at least 3.5 millisecond after V  
CC  
and BCLK{0/1} have reached their proper specifications. RESET_N must not be kept  
asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held  
asserted for at least 3.5 millisecond before it is de-asserted again. RESET_N must be  
held asserted before PWRGOOD is asserted. This signal does not have on-die  
termination and must be terminated on the system board.  
§ §  
72  
Datasheet  
Processor Land Listing  
8 Processor Land Listing  
This chapter provides the processor land lists. Table 8-1 is a listing of all processor  
lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands  
ordered by land number.  
Datasheet  
73  
   
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 1 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 2 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
BCLK0_DN  
BCLK0_DP  
CM44  
CN43  
BA45  
AW45  
AT48  
AR43  
AT44  
AU43  
AV44  
BB44  
AW43  
BA43  
AY44  
CC51  
AN43  
CB18  
CMOS  
CMOS  
I
DDR0_CLK_DP[1]  
DDR0_CLK_DP[2]  
DDR0_CLK_DP[3]  
DDR0_CS_N[0]  
DDR0_CS_N[1]  
DDR0_CS_N[2]  
DDR0_CS_N[3]  
DDR0_CS_N[4]  
DDR0_CS_N[5]  
DDR0_CS_N[6]  
DDR0_CS_N[7]  
DDR0_CS_N[8]  
DDR0_CS_N[9]  
DDR0_DQ[00]  
DDR0_DQ[01]  
DDR0_DQ[02]  
DDR0_DQ[03]  
DDR0_DQ[04]  
DDR0_DQ[05]  
DDR0_DQ[06]  
DDR0_DQ[07]  
DDR0_DQ[08]  
DDR0_DQ[09]  
DDR0_DQ[10]  
DDR0_DQ[11]  
DDR0_DQ[12]  
DDR0_DQ[13]  
DDR0_DQ[14]  
DDR0_DQ[15]  
DDR0_DQ[16]  
DDR0_DQ[17]  
DDR0_DQ[18]  
DDR0_DQ[19]  
DDR0_DQ[20]  
DDR0_DQ[21]  
DDR0_DQ[22]  
DDR0_DQ[23]  
DDR0_DQ[24]  
DDR0_DQ[25]  
DDR0_DQ[26]  
DDR0_DQ[27]  
DDR0_DQ[28]  
DDR0_DQ[29]  
DDR0_DQ[30]  
CG23  
CG21  
CH22  
CN25  
CH26  
CC23  
CB28  
CG27  
CF26  
CB26  
CC25  
CL27  
CK28  
CC7  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
O
I
O
BCLK1_DN  
BCLK1_DP  
CMOS  
I
O
CMOS  
I
O
BIST_ENABLE  
BPM_N[0]  
CMOS  
I
O
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
O
BPM_N[1]  
O
BPM_N[2]  
O
BPM_N[3]  
O
BPM_N[4]  
O
BPM_N[5]  
O
BPM_N[6]  
O
BPM_N[7]  
O
CAT_ERR_N  
CPU_ONLY_RESET  
DDR_RESET_C01_N  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CD8  
CMOS1.5  
v
CK8  
CL9  
DDR_RESET_C23_N  
AE27  
CMOS1.5  
v
O
BY6  
CA7  
DDR_SCL_C01  
DDR_SCL_C23  
DDR_SDA_C01  
DDR_SDA_C23  
CY42  
U43  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
DC  
I/O  
I/O  
I/O  
I/O  
I
CJ7  
CL7  
CW41  
R43  
CB2  
CB4  
DDR_VREFDQRX_C  
01  
BY16  
CH4  
DDR_VREFDQRX_C  
23  
J1  
DC  
DC  
DC  
I
CJ5  
CA1  
DDR_VREFDQTX_C  
01  
CN41  
P42  
O
O
CA3  
CG3  
DDR_VREFDQTX_C  
23  
CG5  
DDR0_BA[0]  
CM28  
CN27  
CM20  
CL29  
CL19  
CM18  
CH20  
CP18  
CF20  
CE19  
CF24  
CE23  
CE21  
CF22  
CH24  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CK12  
CM12  
CK16  
CM16  
CG13  
CL11  
CJ15  
CL15  
BY10  
BY12  
CB12  
CD12  
BW9  
CA9  
DDR0_BA[1]  
DDR0_BA[2]  
DDR0_CAS_N  
DDR0_CKE[0]  
DDR0_CKE[1]  
DDR0_CKE[2]  
DDR0_CKE[3]  
DDR0_CKE[4]  
DDR0_CKE[5]  
DDR0_CLK_DN[0]  
DDR0_CLK_DN[1]  
DDR0_CLK_DN[2]  
DDR0_CLK_DN[3]  
DDR0_CLK_DP[0]  
CH10  
74  
Datasheet  
 
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 3 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 4 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR0_DQ[31]  
DDR0_DQ[32]  
DDR0_DQ[33]  
DDR0_DQ[34]  
DDR0_DQ[35]  
DDR0_DQ[36]  
DDR0_DQ[37]  
DDR0_DQ[38]  
DDR0_DQ[39]  
DDR0_DQ[40]  
DDR0_DQ[41]  
DDR0_DQ[42]  
DDR0_DQ[43]  
DDR0_DQ[44]  
DDR0_DQ[45]  
DDR0_DQ[46]  
DDR0_DQ[47]  
DDR0_DQ[48]  
DDR0_DQ[49]  
DDR0_DQ[50]  
DDR0_DQ[51]  
DDR0_DQ[52]  
DDR0_DQ[53]  
DDR0_DQ[54]  
DDR0_DQ[55]  
DDR0_DQ[56]  
DDR0_DQ[57]  
DDR0_DQ[58]  
DDR0_DQ[59]  
DDR0_DQ[60]  
DDR0_DQ[61]  
DDR0_DQ[62]  
DDR0_DQ[63]  
DDR0_DQS_DN[00]  
DDR0_DQS_DN[01]  
DDR0_DQS_DN[02]  
DDR0_DQS_DN[03]  
DDR0_DQS_DN[04]  
DDR0_DQS_DN[05]  
DDR0_DQS_DN[06]  
DDR0_DQS_DN[07]  
DDR0_DQS_DN[08]  
DDR0_DQS_DN[09]  
DDR0_DQS_DN[10]  
CF10  
CE31  
CC31  
CE35  
CC35  
CD30  
CB30  
CD34  
CB34  
CL31  
CJ31  
CL35  
CJ35  
CK30  
CH30  
CK34  
CH34  
CB38  
CD38  
CE41  
CD42  
CC37  
CE37  
CC41  
CB42  
CH38  
CK38  
CH42  
CK42  
CJ37  
CL37  
CJ41  
CL41  
CG7  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
DDR0_DQS_DN[11]  
DDR0_DQS_DN[12]  
DDR0_DQS_DN[13]  
DDR0_DQS_DN[14]  
DDR0_DQS_DN[15]  
DDR0_DQS_DN[16]  
DDR0_DQS_DN[17]  
DDR0_DQS_DP[00]  
DDR0_DQS_DP[01]  
DDR0_DQS_DP[02]  
DDR0_DQS_DP[03]  
DDR0_DQS_DP[04]  
DDR0_DQS_DP[05]  
DDR0_DQS_DP[06]  
DDR0_DQS_DP[07]  
DDR0_DQS_DP[08]  
DDR0_DQS_DP[09]  
DDR0_DQS_DP[10]  
DDR0_DQS_DP[11]  
DDR0_DQS_DP[12]  
DDR0_DQS_DP[13]  
DDR0_DQS_DP[14]  
DDR0_DQS_DP[15]  
DDR0_DQS_DP[16]  
DDR0_DQS_DP[17]  
DDR0_MA_PAR  
CL13  
CC11  
CB32  
CH32  
CE39  
CL39  
CF16  
CH8  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
CF4  
CK14  
CE11  
CC33  
CJ33  
CD40  
CK40  
CC17  
CE7  
CC5  
CJ13  
CB10  
CD32  
CK32  
CC39  
CJ39  
CD16  
CM26  
CL25  
CR25  
CG25  
CK24  
CM24  
CL23  
CN23  
CM22  
CK22  
CN21  
CK26  
CL21  
CK20  
CG29  
CG19  
CN19  
CE25  
CE27  
DDR0_MA[00]  
O
DDR0_MA[01]  
O
DDR0_MA[02]  
O
DDR0_MA[03]  
O
DDR0_MA[04]  
O
DDR0_MA[05]  
O
DDR0_MA[06]  
O
DDR0_MA[07]  
O
CE3  
DDR0_MA[08]  
O
CH14  
CD10  
CE33  
CL33  
CB40  
CH40  
CE17  
CF8  
DDR0_MA[09]  
O
DDR0_MA[10]  
O
DDR0_MA[11]  
O
DDR0_MA[12]  
O
DDR0_MA[13]  
O
DDR0_MA[14]  
O
DDR0_MA[15]  
O
DDR0_ODT[0]  
O
CD4  
DDR0_ODT[1]  
O
Datasheet  
75  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 5 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 6 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR0_ODT[2]  
DDR0_ODT[3]  
DDR0_ODT[4]  
DDR0_ODT[5]  
DDR0_PAR_ERR_N  
DDR0_RAS_N  
CH28  
CF28  
CB24  
CC27  
CC21  
CE29  
CN29  
CA17  
CC19  
CB20  
DB26  
DC25  
DF18  
CY30  
CT20  
CU19  
CY18  
DA17  
CR19  
CT18  
CV20  
CV22  
CY24  
DA21  
CY20  
CY22  
CV24  
DC21  
DB24  
CU23  
CR23  
CR27  
CU25  
CT24  
DA29  
CT26  
CR21  
DA27  
CP4  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Analog  
Analog  
Analog  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
O
O
DDR1_DQ[06]  
DDR1_DQ[07]  
DDR1_DQ[08]  
DDR1_DQ[09]  
DDR1_DQ[10]  
DDR1_DQ[11]  
DDR1_DQ[12]  
DDR1_DQ[13]  
DDR1_DQ[14]  
DDR1_DQ[15]  
DDR1_DQ[16]  
DDR1_DQ[17]  
DDR1_DQ[18]  
DDR1_DQ[19]  
DDR1_DQ[20]  
DDR1_DQ[21]  
DDR1_DQ[22]  
DDR1_DQ[23]  
DDR1_DQ[24]  
DDR1_DQ[25]  
DDR1_DQ[26]  
DDR1_DQ[27]  
DDR1_DQ[28]  
DDR1_DQ[29]  
DDR1_DQ[30]  
DDR1_DQ[31]  
DDR1_DQ[32]  
DDR1_DQ[33]  
DDR1_DQ[34]  
DDR1_DQ[35]  
DDR1_DQ[36]  
DDR1_DQ[37]  
DDR1_DQ[38]  
DDR1_DQ[39]  
DDR1_DQ[40]  
DDR1_DQ[41]  
DDR1_DQ[42]  
DDR1_DQ[43]  
DDR1_DQ[44]  
DDR1_DQ[45]  
DDR1_DQ[46]  
DDR1_DQ[47]  
DDR1_DQ[48]  
DDR1_DQ[49]  
CV2  
CW3  
DA7  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
O
DC7  
I
DC11  
DE11  
CY6  
O
DDR0_WE_N  
O
DDR01_RCOMP[0]  
DDR01_RCOMP[1]  
DDR01_RCOMP[2]  
DDR1_BA[0]  
I
DB6  
I
DB10  
DF10  
CR7  
I
O
DDR1_BA[1]  
O
CU7  
DDR1_BA[2]  
O
CT10  
CP10  
CP6  
DDR1_CAS_N  
O
DDR1_CKE[0]  
O
DDR1_CKE[1]  
O
CT6  
DDR1_CKE[2]  
O
CW9  
CV10  
CR13  
CU13  
CR17  
CU17  
CT12  
CV12  
CT16  
CV16  
CT30  
CP30  
CT34  
CP34  
CU29  
CR29  
CU33  
CR33  
DA33  
DD32  
DC35  
DA35  
DA31  
CY32  
DF34  
DE35  
CR37  
CU37  
DDR1_CKE[3]  
O
DDR1_CKE[4]  
O
DDR1_CKE[5]  
O
DDR1_CLK_DN[0]  
DDR1_CLK_DN[1]  
DDR1_CLK_DN[2]  
DDR1_CLK_DN[3]  
DDR1_CLK_DP[0]  
DDR1_CLK_DP[1]  
DDR1_CLK_DP[2]  
DDR1_CLK_DP[3]  
DDR1_CS_N[0]  
DDR1_CS_N[1]  
DDR1_CS_N[2]  
DDR1_CS_N[3]  
DDR1_CS_N[4]  
DDR1_CS_N[5]  
DDR1_CS_N[6]  
DDR1_CS_N[7]  
DDR1_CS_N[8]  
DDR1_CS_N[9]  
DDR1_DQ[00]  
DDR1_DQ[01]  
DDR1_DQ[02]  
DDR1_DQ[03]  
DDR1_DQ[04]  
DDR1_DQ[05]  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP2  
CV4  
CY4  
CM4  
CL3  
76  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 7 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 8 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR1_DQ[50]  
CR41  
CU41  
CT36  
CV36  
CT40  
CV40  
DE37  
DF38  
DD40  
DB40  
DA37  
DC37  
DA39  
DF40  
CT4  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
DDR1_DQS_DP[12]  
DDR1_DQS_DP[13]  
DDR1_DQS_DP[14]  
DDR1_DQS_DP[15]  
DDR1_DQS_DP[16]  
DDR1_DQS_DP[17]  
DDR1_MA_PAR  
DDR1_MA[00]  
DDR1_MA[01]  
DDR1_MA[02]  
DDR1_MA[03]  
DDR1_MA[04]  
DDR1_MA[05]  
DDR1_MA[06]  
DDR1_MA[07]  
DDR1_MA[08]  
DDR1_MA[09]  
DDR1_MA[10]  
DDR1_MA[11]  
DDR1_MA[12]  
DDR1_MA[13]  
DDR1_MA[14]  
DDR1_MA[15]  
DDR1_ODT[0]  
DDR1_ODT[1]  
DDR1_ODT[2]  
DDR1_ODT[3]  
DDR1_ODT[4]  
DDR1_ODT[5]  
DDR1_PAR_ERR_N  
DDR1_RAS_N  
DDR1_WE_N  
CT14  
CU31  
DC33  
CP38  
DB38  
CY14  
DE25  
DC23  
DE23  
DF24  
DA23  
DB22  
DF22  
DE21  
DF20  
DB20  
DA19  
DF26  
DE19  
DC19  
DB30  
DB18  
DC17  
CT22  
DA25  
CY26  
CV26  
CU27  
CY28  
CU21  
DB28  
CV28  
R17  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
DDR1_DQ[51]  
DDR1_DQ[52]  
DDR1_DQ[53]  
DDR1_DQ[54]  
DDR1_DQ[55]  
DDR1_DQ[56]  
DDR1_DQ[57]  
O
DDR1_DQ[58]  
O
DDR1_DQ[59]  
O
DDR1_DQ[60]  
O
DDR1_DQ[61]  
O
DDR1_DQ[62]  
O
DDR1_DQ[63]  
O
DDR1_DQS_DN[00]  
DDR1_DQS_DN[01]  
DDR1_DQS_DN[02]  
DDR1_DQS_DN[03]  
DDR1_DQS_DN[04]  
DDR1_DQS_DN[05]  
DDR1_DQS_DN[06]  
DDR1_DQS_DN[07]  
DDR1_DQS_DN[08]  
DDR1_DQS_DN[09]  
DDR1_DQS_DN[10]  
DDR1_DQS_DN[11]  
DDR1_DQS_DN[12]  
DDR1_DQS_DN[13]  
DDR1_DQS_DN[14]  
DDR1_DQS_DN[15]  
DDR1_DQS_DN[16]  
DDR1_DQS_DN[17]  
DDR1_DQS_DP[00]  
DDR1_DQS_DP[01]  
DDR1_DQS_DP[02]  
DDR1_DQS_DP[03]  
DDR1_DQS_DP[04]  
DDR1_DQS_DP[05]  
DDR1_DQS_DP[06]  
DDR1_DQS_DP[07]  
DDR1_DQS_DP[08]  
DDR1_DQS_DP[09]  
DDR1_DQS_DP[10]  
DDR1_DQS_DP[11]  
O
DC9  
O
CV8  
O
CR15  
CT32  
CY34  
CR39  
DE39  
DE15  
CR1  
O
O
O
O
O
O
O
DB8  
O
CT8  
O
CP14  
CR31  
DE33  
CT38  
CY38  
DB14  
CR3  
O
O
O
I
O
O
DDR2_BA[0]  
O
DE9  
DDR2_BA[1]  
L17  
O
CU9  
DDR2_BA[2]  
P24  
O
CU15  
CP32  
DB34  
CU39  
DC39  
DC15  
CT2  
DDR2_CAS_N  
DDR2_CKE[0]  
DDR2_CKE[1]  
DDR2_CKE[2]  
DDR2_CKE[3]  
DDR2_CKE[4]  
DDR2_CKE[5]  
DDR2_CLK_DN[0]  
DDR2_CLK_DN[1]  
T16  
O
AA25  
T26  
O
O
U27  
O
AD24  
AE25  
AE23  
Y24  
O
O
O
DD8  
O
CP8  
Y22  
O
Datasheet  
77  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 9 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 10 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR2_CLK_DN[2]  
DDR2_CLK_DN[3]  
DDR2_CLK_DP[0]  
DDR2_CLK_DP[1]  
DDR2_CLK_DP[2]  
DDR2_CLK_DP[3]  
DDR2_CS_N[0]  
DDR2_CS_N[1]  
DDR2_CS_N[2]  
DDR2_CS_N[3]  
DDR2_CS_N[4]  
DDR2_CS_N[5]  
DDR2_CS_N[6]  
DDR2_CS_N[7]  
DDR2_CS_N[8]  
DDR2_CS_N[9]  
DDR2_DQ[00]  
DDR2_DQ[01]  
DDR2_DQ[02]  
DDR2_DQ[03]  
DDR2_DQ[04]  
DDR2_DQ[05]  
DDR2_DQ[06]  
DDR2_DQ[07]  
DDR2_DQ[08]  
DDR2_DQ[09]  
DDR2_DQ[10]  
DDR2_DQ[11]  
DDR2_DQ[12]  
DDR2_DQ[13]  
DDR2_DQ[14]  
DDR2_DQ[15]  
DDR2_DQ[16]  
DDR2_DQ[17]  
DDR2_DQ[18]  
DDR2_DQ[19]  
DDR2_DQ[20]  
DDR2_DQ[21]  
DDR2_DQ[22]  
DDR2_DQ[23]  
DDR2_DQ[24]  
DDR2_DQ[25]  
DDR2_DQ[26]  
DDR2_DQ[27]  
W21  
W23  
AB24  
AB22  
AA21  
AA23  
AB20  
AE19  
AD16  
AA15  
AA19  
P18  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
O
DDR2_DQ[28]  
DDR2_DQ[29]  
DDR2_DQ[30]  
DDR2_DQ[31]  
DDR2_DQ[32]  
DDR2_DQ[33]  
DDR2_DQ[34]  
DDR2_DQ[35]  
DDR2_DQ[36]  
DDR2_DQ[37]  
DDR2_DQ[38]  
DDR2_DQ[39]  
DDR2_DQ[40]  
DDR2_DQ[41]  
DDR2_DQ[42]  
DDR2_DQ[43]  
DDR2_DQ[44]  
DDR2_DQ[45]  
DDR2_DQ[46]  
DDR2_DQ[47]  
DDR2_DQ[48]  
DDR2_DQ[49]  
DDR2_DQ[50]  
DDR2_DQ[51]  
DDR2_DQ[52]  
DDR2_DQ[53]  
DDR2_DQ[54]  
DDR2_DQ[55]  
DDR2_DQ[56]  
DDR2_DQ[57]  
DDR2_DQ[58]  
DDR2_DQ[59]  
DDR2_DQ[60]  
DDR2_DQ[61]  
DDR2_DQ[62]  
DDR2_DQ[63]  
DDR2_DQS_DN[00]  
DDR2_DQS_DN[01]  
DDR2_DQS_DN[02]  
DDR2_DQS_DN[03]  
DDR2_DQS_DN[04]  
DDR2_DQS_DN[05]  
DDR2_DQS_DN[06]  
DDR2_DQS_DN[07]  
AA35  
W35  
AB32  
AD32  
AC13  
AE13  
AG11  
AF10  
AD14  
AA13  
AB10  
AD10  
V6  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
O
O
O
O
O
O
O
O
O
O
AB16  
Y16  
O
O
Y6  
W17  
AA17  
T40  
O
AF8  
AG7  
U7  
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V40  
W7  
P36  
AD8  
AE7  
R13  
U13  
T10  
V10  
T14  
V14  
R9  
T36  
R41  
U41  
R37  
U37  
AE41  
AD40  
AA37  
AC37  
AC41  
AA41  
AF38  
AE37  
U33  
U9  
W3  
Y4  
AF4  
AE5  
U3  
R33  
V4  
W29  
U29  
AF2  
AE3  
T38  
AD38  
W31  
AA33  
AC11  
AB8  
U11  
AC3  
T34  
P34  
V30  
T30  
AC35  
AE35  
AE33  
AF32  
78  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 11 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 12 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR2_DQS_DN[08]  
DDR2_DQS_DN[09]  
DDR2_DQS_DN[10]  
DDR2_DQS_DN[11]  
DDR2_DQS_DN[12]  
DDR2_DQS_DN[13]  
DDR2_DQS_DN[14]  
DDR2_DQS_DN[15]  
DDR2_DQS_DN[16]  
DDR2_DQS_DN[17]  
DDR2_DQS_DP[00]  
DDR2_DQS_DP[01]  
DDR2_DQS_DP[02]  
DDR2_DQS_DP[03]  
DDR2_DQS_DP[04]  
DDR2_DQS_DP[05]  
DDR2_DQS_DP[06]  
DDR2_DQS_DP[07]  
DDR2_DQS_DP[08]  
DDR2_DQS_DP[09]  
DDR2_DQS_DP[10]  
DDR2_DQS_DP[11]  
DDR2_DQS_DP[12]  
DDR2_DQS_DP[13]  
DDR2_DQS_DP[14]  
DDR2_DQS_DP[15]  
DDR2_DQS_DP[16]  
DDR2_DQS_DP[17]  
DDR2_MA_PAR  
AB28  
W39  
AC39  
T32  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
DDR2_MA[15]  
DDR2_ODT[0]  
DDR2_ODT[1]  
DDR2_ODT[2]  
DDR2_ODT[3]  
DDR2_ODT[4]  
DDR2_ODT[5]  
DDR2_PAR_ERR_N  
DDR2_RAS_N  
U25  
Y20  
W19  
AD18  
Y18  
AD22  
AE21  
AD20  
U17  
P16  
U15  
AC15  
Y14  
A17  
E19  
B24  
B14  
K24  
M24  
J25  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Analog  
Analog  
Analog  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
O
O
O
O
O
O
O
I
AB34  
AD12  
AA7  
V12  
AD4  
AD28  
V38  
O
O
I
DDR2_WE_N  
DDR23_RCOMP[0]  
DDR23_RCOMP[1]  
DDR23_RCOMP[2]  
DDR3_BA[0]  
AB38  
U31  
AC33  
AE11  
AC7  
W11  
AB4  
AC27  
U39  
AB40  
V32  
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O  
I/O  
I/O  
DDR3_BA[1]  
DDR3_BA[2]  
DDR3_CAS_N  
DDR3_CKE[0]  
DDR3_CKE[1]  
DDR3_CKE[2]  
DDR3_CKE[3]  
N25  
R25  
R27  
J23  
DDR3_CKE[4]  
Y34  
DDR3_CKE[5]  
AB12  
Y8  
DDR3_CLK_DN[0]  
DDR3_CLK_DN[1]  
DDR3_CLK_DN[2]  
DDR3_CLK_DN[3]  
DDR3_CLK_DP[0]  
DDR3_CLK_DP[1]  
DDR3_CLK_DP[2]  
DDR3_CLK_DP[3]  
DDR3_CS_N[0]  
DDR3_CS_N[1]  
DDR3_CS_N[2]  
DDR3_CS_N[3]  
DDR3_CS_N[4]  
DDR3_CS_N[5]  
DDR3_CS_N[6]  
DDR3_CS_N[7]  
DDR3_CS_N[8]  
DDR3_CS_N[9]  
DDR3_DQ[00]  
DDR3_DQ[01]  
DDR3_DQ[02]  
J21  
T12  
M20  
K22  
L23  
AC5  
AC29  
M18  
AB18  
R19  
L21  
DDR2_MA[00]  
O
K20  
M22  
G19  
J19  
DDR2_MA[01]  
O
DDR2_MA[02]  
U19  
T20  
O
DDR2_MA[03]  
O
DDR2_MA[04]  
P20  
O
F14  
DDR2_MA[05]  
U21  
R21  
O
G15  
K18  
G17  
F16  
DDR2_MA[06]  
O
DDR2_MA[07]  
P22  
O
DDR2_MA[08]  
T22  
O
DDR2_MA[09]  
R23  
O
E15  
D16  
K16  
B40  
A39  
C37  
DDR2_MA[10]  
T18  
O
DDR2_MA[11]  
U23  
T24  
O
DDR2_MA[12]  
O
DDR2_MA[13]  
R15  
O
DDR2_MA[14]  
W25  
O
Datasheet  
79  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 13 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 14 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR3_DQ[03]  
DDR3_DQ[04]  
DDR3_DQ[05]  
DDR3_DQ[06]  
DDR3_DQ[07]  
DDR3_DQ[08]  
DDR3_DQ[09]  
DDR3_DQ[10]  
DDR3_DQ[11]  
DDR3_DQ[12]  
DDR3_DQ[13]  
DDR3_DQ[14]  
DDR3_DQ[15]  
DDR3_DQ[16]  
DDR3_DQ[17]  
DDR3_DQ[18]  
DDR3_DQ[19]  
DDR3_DQ[20]  
DDR3_DQ[21]  
DDR3_DQ[22]  
DDR3_DQ[23]  
DDR3_DQ[24]  
DDR3_DQ[25]  
DDR3_DQ[26]  
DDR3_DQ[27]  
DDR3_DQ[28]  
DDR3_DQ[29]  
DDR3_DQ[30]  
DDR3_DQ[31]  
DDR3_DQ[32]  
DDR3_DQ[33]  
DDR3_DQ[34]  
DDR3_DQ[35]  
DDR3_DQ[36]  
DDR3_DQ[37]  
DDR3_DQ[38]  
DDR3_DQ[39]  
DDR3_DQ[40]  
DDR3_DQ[41]  
DDR3_DQ[42]  
DDR3_DQ[43]  
DDR3_DQ[44]  
DDR3_DQ[45]  
DDR3_DQ[46]  
E37  
F40  
D40  
F38  
A37  
N39  
L39  
L35  
J35  
M40  
K40  
K36  
H36  
A35  
F34  
D32  
F32  
E35  
C35  
A33  
B32  
M32  
L31  
M28  
L27  
L33  
K32  
N27  
M26  
D12  
A11  
C9  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
DDR3_DQ[47]  
M10  
E7  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
DDR3_DQ[48]  
DDR3_DQ[49]  
F6  
DDR3_DQ[50]  
N7  
DDR3_DQ[51]  
P6  
DDR3_DQ[52]  
C7  
DDR3_DQ[53]  
D6  
DDR3_DQ[54]  
L7  
DDR3_DQ[55]  
M6  
DDR3_DQ[56]  
G3  
DDR3_DQ[57]  
H2  
DDR3_DQ[58]  
N3  
DDR3_DQ[59]  
P4  
DDR3_DQ[60]  
F4  
DDR3_DQ[61]  
H4  
DDR3_DQ[62]  
L1  
DDR3_DQ[63]  
M2  
DDR3_DQS_DN[00]  
DDR3_DQS_DN[01]  
DDR3_DQS_DN[02]  
DDR3_DQS_DN[03]  
DDR3_DQS_DN[04]  
DDR3_DQS_DN[05]  
DDR3_DQS_DN[06]  
DDR3_DQS_DN[07]  
DDR3_DQS_DN[08]  
DDR3_DQS_DN[09]  
DDR3_DQS_DN[10]  
DDR3_DQS_DN[11]  
DDR3_DQS_DN[12]  
DDR3_DQS_DN[13]  
DDR3_DQS_DN[14]  
DDR3_DQS_DN[15]  
DDR3_DQS_DN[16]  
DDR3_DQS_DN[17]  
DDR3_DQS_DP[00]  
DDR3_DQS_DP[01]  
DDR3_DQS_DP[02]  
DDR3_DQS_DP[03]  
DDR3_DQS_DP[04]  
DDR3_DQS_DP[05]  
DDR3_DQS_DP[06]  
DDR3_DQS_DP[07]  
DDR3_DQS_DP[08]  
B38  
L37  
G33  
P28  
B10  
L11  
J7  
L3  
G27  
G39  
K38  
B34  
M30  
G11  
M12  
H6  
E9  
F12  
B12  
F10  
A9  
K4  
H28  
D38  
J37  
E33  
N29  
D10  
N11  
K6  
J13  
L13  
J9  
L9  
K14  
M14  
K10  
M4  
E27  
80  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 15 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 16 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DDR3_DQS_DP[09]  
DDR3_DQS_DP[10]  
DDR3_DQS_DP[11]  
DDR3_DQS_DP[12]  
DDR3_DQS_DP[13]  
DDR3_DQS_DP[14]  
DDR3_DQS_DP[15]  
DDR3_DQS_DP[16]  
DDR3_DQS_DP[17]  
DDR3_MA_PAR  
DDR3_MA[00]  
DDR3_MA[01]  
DDR3_MA[02]  
DDR3_MA[03]  
DDR3_MA[04]  
DDR3_MA[05]  
DDR3_MA[06]  
DDR3_MA[07]  
DDR3_MA[08]  
DDR3_MA[09]  
DDR3_MA[10]  
DDR3_MA[11]  
DDR3_MA[12]  
DDR3_MA[13]  
DDR3_MA[14]  
DDR3_MA[15]  
DDR3_ODT[0]  
DDR3_ODT[1]  
DDR3_ODT[2]  
DDR3_ODT[3]  
DDR3_ODT[4]  
DDR3_ODT[5]  
DDR3_PAR_ERR_N  
DDR3_RAS_N  
E39  
M38  
D34  
N31  
E11  
K12  
G7  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
DMI_TX_DN[1]  
DMI_TX_DN[2]  
DMI_TX_DN[3]  
DMI_TX_DP[0]  
DMI_TX_DP[1]  
DMI_TX_DP[2]  
DMI_TX_DP[3]  
TXT_PLTEN  
E43  
D44  
E45  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
CMOS  
O
O
O
O
O
O
O
I
B42  
C43  
B44  
C45  
V52  
CW17  
J3  
F28  
B18  
A19  
E21  
F20  
B20  
D20  
A21  
F22  
B22  
D22  
G23  
D18  
A23  
E23  
A13  
D24  
F24  
L19  
F18  
E17  
J17  
DRAM_PWR_OK_C0  
1
CMOS1.5  
v
I
DRAM_PWR_OK_C2  
3
L15  
CMOS1.5  
v
I
O
O
EAR_N  
CH56  
BD50  
CB54  
BC51  
AH42  
AK52  
CB22  
E13  
ODCMOS  
ODCMOS  
ODCMOS  
ODCMOS  
I/O  
O
O
O
O
I
O
ERROR_N[0]  
O
ERROR_N[1]  
O
ERROR_N[2]  
O
IVT_ID_N  
O
TXT_AGENT  
CMOS  
ODCMOS  
ODCMOS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
O
MEM_HOT_C01_N  
MEM_HOT_C23_N  
PE_RBIAS  
I/O  
I/O  
I/O  
I
O
O
AH52  
AF52  
AJ43  
E51  
O
PE_RBIAS_SENSE  
PE_VREF_CAP  
PE1A_RX_DN[0]  
PE1A_RX_DN[1]  
PE1A_RX_DN[2]  
PE1A_RX_DN[3]  
PE1A_RX_DP[0]  
PE1A_RX_DP[1]  
PE1A_RX_DP[2]  
PE1A_RX_DP[3]  
PE1A_TX_DN[0]  
PE1A_TX_DN[1]  
PE1A_TX_DN[2]  
PE1A_TX_DN[3]  
PE1A_TX_DP[0]  
PE1A_TX_DP[1]  
PE1A_TX_DP[2]  
PE1A_TX_DP[3]  
PE1B_RX_DN[4]  
PE1B_RX_DN[5]  
PE1B_RX_DN[6]  
PE1B_RX_DN[7]  
PE1B_RX_DP[4]  
O
I/O  
I
O
O
F52  
I
O
F54  
I
O
G55  
C51  
D52  
D54  
E55  
I
O
I
O
I
O
I
O
I
D14  
M16  
G21  
B16  
A15  
E47  
D48  
E49  
D50  
C47  
B48  
C49  
B50  
D42  
O
K42  
L43  
O
O
O
O
O
O
O
O
I
O
I
K44  
L45  
O
DDR3_WE_N  
O
H42  
J43  
DMI_RX_DN[0]  
DMI_RX_DN[1]  
DMI_RX_DN[2]  
DMI_RX_DN[3]  
DMI_RX_DP[0]  
DMI_RX_DP[1]  
DMI_RX_DP[2]  
DMI_RX_DP[3]  
DMI_TX_DN[0]  
I
I
H44  
J45  
I
I
L53  
I
M54  
L57  
I
I
I
I
M56  
J53  
I
I
I
O
Datasheet  
81  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 17 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 18 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
PE1B_RX_DP[5]  
PE1B_RX_DP[6]  
PE1B_RX_DP[7]  
PE1B_TX_DN[4]  
PE1B_TX_DN[5]  
PE1B_TX_DN[6]  
PE1B_TX_DN[7]  
PE1B_TX_DP[4]  
PE1B_TX_DP[5]  
PE1B_TX_DP[6]  
PE1B_TX_DP[7]  
PE2A_RX_DN[0]  
PE2A_RX_DN[1]  
PE2A_RX_DN[2]  
PE2A_RX_DN[3]  
PE2A_RX_DP[0]  
PE2A_RX_DP[1]  
PE2A_RX_DP[2]  
PE2A_RX_DP[3]  
PE2A_TX_DN[0]  
PE2A_TX_DN[1]  
PE2A_TX_DN[2]  
PE2A_TX_DN[3]  
PE2A_TX_DP[0]  
PE2A_TX_DP[1]  
PE2A_TX_DP[2]  
PE2A_TX_DP[3]  
PE2B_RX_DN[4]  
PE2B_RX_DN[5]  
PE2B_RX_DN[6]  
PE2B_RX_DN[7]  
PE2B_RX_DP[4]  
PE2B_RX_DP[5]  
PE2B_RX_DP[6]  
PE2B_RX_DP[7]  
PE2B_TX_DN[4]  
PE2B_TX_DN[5]  
PE2B_TX_DN[6]  
PE2B_TX_DN[7]  
PE2B_TX_DP[4]  
PE2B_TX_DP[5]  
PE2B_TX_DP[6]  
PE2B_TX_DP[7]  
PE2C_RX_DN[10]  
K54  
J57  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
I
I
PE2C_RX_DN[11]  
PE2C_RX_DN[8]  
PE2C_RX_DN[9]  
PE2C_RX_DP[10]  
PE2C_RX_DP[11]  
PE2C_RX_DP[8]  
PE2C_RX_DP[9]  
PE2C_TX_DN[10]  
PE2C_TX_DN[11]  
PE2C_TX_DN[8]  
PE2C_TX_DN[9]  
PE2C_TX_DP[10]  
PE2C_TX_DP[11]  
PE2C_TX_DP[8]  
PE2C_TX_DP[9]  
PE2D_RX_DN[12]  
PE2D_RX_DN[13]  
PE2D_RX_DN[14]  
PE2D_RX_DN[15]  
PE2D_RX_DP[12]  
PE2D_RX_DP[13]  
PE2D_RX_DP[14]  
PE2D_RX_DP[15]  
PE2D_TX_DN[12]  
PE2D_TX_DN[13]  
PE2D_TX_DN[14]  
PE2D_TX_DN[15]  
PE2D_TX_DP[12]  
PE2D_TX_DP[13]  
PE2D_TX_DP[14]  
PE2D_TX_DP[15]  
PE3A_RX_DN[0]  
PE3A_RX_DN[1]  
PE3A_RX_DN[2]  
PE3A_RX_DN[3]  
PE3A_RX_DP[0]  
PE3A_RX_DP[1]  
PE3A_RX_DP[2]  
PE3A_RX_DP[3]  
PE3A_TX_DN[0]  
PE3A_TX_DN[1]  
PE3A_TX_DN[2]  
PE3A_TX_DN[3]  
PE3A_TX_DP[0]  
AU57  
AK56  
AM58  
AJ57  
AR57  
AH56  
AK58  
BB54  
BA51  
AY52  
BA53  
AY54  
AW51  
AV52  
AW53  
AV58  
AT56  
BA57  
BB56  
AT58  
AP56  
AY58  
AY56  
AY50  
BA49  
AY48  
BA47  
AV50  
AW49  
AV48  
AW47  
AH44  
AJ45  
AH46  
AC49  
AF44  
AG45  
AF46  
AA49  
K50  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
I
I
K56  
I
I
K46  
O
O
O
O
O
O
O
O
I
I
L47  
I
K48  
I
L49  
I
H46  
O
O
O
O
O
O
O
O
I
J47  
H48  
J49  
N55  
V54  
I
V56  
I
W55  
L55  
I
I
T54  
I
I
T56  
I
I
U55  
I
I
AR49  
AP50  
AR51  
AP52  
AN49  
AM50  
AN51  
AM52  
AD54  
AD56  
AE55  
AF58  
AB54  
AB56  
AC55  
AE57  
AJ53  
AK54  
AR53  
AT54  
AG53  
AH54  
AN53  
AP54  
AL57  
O
O
O
O
O
O
O
O
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
O
O
O
O
O
L51  
U47  
T48  
H50  
82  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 19 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 20 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
PE3A_TX_DP[1]  
PE3A_TX_DP[2]  
PE3A_TX_DP[3]  
PE3B_RX_DN[4]  
PE3B_RX_DN[5]  
PE3B_RX_DN[6]  
PE3B_RX_DN[7]  
PE3B_RX_DP[4]  
PE3B_RX_DP[5]  
PE3B_RX_DP[6]  
PE3B_RX_DP[7]  
PE3B_TX_DN[4]  
PE3B_TX_DN[5]  
PE3B_TX_DN[6]  
PE3B_TX_DN[7]  
PE3B_TX_DP[4]  
PE3B_TX_DP[5]  
PE3B_TX_DP[6]  
PE3B_TX_DP[7]  
PE3C_RX_DN[10]  
PE3C_RX_DN[11]  
PE3C_RX_DN[8]  
PE3C_RX_DN[9]  
PE3C_RX_DP[10]  
PE3C_RX_DP[11]  
PE3C_RX_DP[8]  
PE3C_RX_DP[9]  
PE3C_TX_DN[10]  
PE3C_TX_DN[11]  
PE3C_TX_DN[8]  
PE3C_TX_DN[9]  
PE3C_TX_DP[10]  
PE3C_TX_DP[11]  
PE3C_TX_DP[8]  
PE3C_TX_DP[9]  
PE3D_RX_DN[12]  
PE3D_RX_DN[13]  
PE3D_RX_DN[14]  
PE3D_RX_DN[15]  
PE3D_RX_DP[12]  
PE3D_RX_DP[13]  
PE3D_RX_DP[14]  
PE3D_RX_DP[15]  
PE3D_TX_DN[12]  
J51  
R47  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
O
O
O
I
PE3D_TX_DN[13]  
PE3D_TX_DN[14]  
PE3D_TX_DN[15]  
PE3D_TX_DP[12]  
PE3D_TX_DP[13]  
PE3D_TX_DP[14]  
PE3D_TX_DP[15]  
PECI  
AB44  
AA43  
P44  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PECI  
O
O
P48  
O
AB50  
AB52  
AC53  
AC51  
Y50  
AA45  
Y44  
O
I
O
I
AC43  
T44  
O
I
O
I
BJ47  
BH48  
BF48  
K52  
I/O  
I/O  
I/O  
I
Y52  
I
PEHPSCL  
PEHPSDA  
PMSYNC  
PRDY_N  
PREQ_N  
PROCHOT_N  
PWRGOOD  
RESET_N  
RSVD  
ODCMOS  
ODCMOS  
CMOS  
AA53  
AA51  
T52  
I
I
O
O
O
O
O
O
O
O
I
R53  
CMOS  
O
U51  
U53  
CMOS  
I/O  
I/O  
I
T50  
BD52  
BJ53  
CK44  
A53  
ODCMOS  
CMOS  
U49  
P52  
CMOS  
I
R51  
P50  
RSVD  
AB48  
AJ55  
AL55  
AM44  
AP48  
AR55  
AU55  
AV46  
AY46  
B46  
R49  
RSVD  
AH50  
AJ49  
AH48  
AJ51  
AF50  
AG49  
AF48  
AG51  
U45  
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
O
O
O
O
O
O
O
O
I
RSVD  
BC47  
BD44  
BD46  
BD48  
BE43  
BE45  
BE47  
BF46  
BG43  
BG45  
BH44  
BH46  
BJ43  
BJ45  
BK44  
BL43  
BL45  
AB46  
T46  
RSVD  
RSVD  
AC47  
R45  
RSVD  
RSVD  
Y46  
RSVD  
P46  
RSVD  
AA47  
AJ47  
AR47  
AP46  
AR45  
AG47  
AN47  
AM46  
AN45  
AC45  
RSVD  
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
I
RSVD  
O
RSVD  
Datasheet  
83  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 21 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 22 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
RSVD  
BM44  
BM46  
BN47  
BP44  
BP46  
BR43  
BR47  
BT44  
BU43  
BY46  
C53  
SVIDDATA  
TCK  
BR45  
BY44  
BW43  
CA43  
DB4  
ODCMOS  
CMOS  
I/O  
I
RSVD  
RSVD  
TDI  
CMOS  
I
RSVD  
TDO  
ODCMOS  
O
O
O
O
O
I
RSVD  
TEST0  
TEST1  
TEST2  
TEST3  
TEST4  
THERMTRIP_N  
TMS  
RSVD  
CW1  
F2  
RSVD  
RSVD  
D4  
RSVD  
BA55  
BL47  
BV44  
CT54  
AG19  
AG25  
AG27  
AG29  
AG31  
AG33  
AG35  
AG37  
AG39  
AG41  
AL1  
RSVD  
ODCMOS  
CMOS  
CMOS  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
O
I
RSVD  
RSVD  
CA45  
CD44  
CE43  
CF44  
CG11  
CP54  
CY46  
CY48  
CY56  
CY58  
D46  
TRST_N  
VCC  
I
RSVD  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
D56  
VCC  
RSVD  
DA57  
DB56  
DC55  
DD54  
DE55  
E53  
VCC  
AL11  
AL13  
AL15  
AL17  
AL3  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
RSVD  
VCC  
AL5  
RSVD  
E57  
VCC  
AL7  
RSVD  
F46  
VCC  
AL9  
RSVD  
F56  
VCC  
AM10  
AM12  
AM14  
AM16  
AM2  
RSVD  
F58  
VCC  
RSVD  
H56  
VCC  
RSVD  
H58  
VCC  
RSVD  
J15  
VCC  
RSVD  
K58  
VCC  
AM4  
RSVD  
M48  
VCC  
AM6  
RSVD  
W15  
Y48  
VCC  
AM8  
RSVD  
VCC  
AN1  
SAFE_MODE_BOOT  
SKTOCC_N  
SVIDALERT_N  
SVIDCLK  
DA55  
BU49  
CR43  
CB44  
CMOS  
I
O
I
VCC  
AN11  
AN13  
AN15  
AN17  
VCC  
CMOS  
VCC  
ODCMOS  
O
VCC  
84  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 23 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 24 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
VCC  
Direction  
Land Name  
Direction  
AN3  
AN5  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
AY6  
AY8  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
AN7  
BA1  
AN9  
BA11  
BA13  
BA15  
BA17  
BA3  
AP10  
AP12  
AP14  
AP16  
AP2  
BA5  
AP4  
BA7  
AP6  
BA9  
AP8  
BB10  
BB12  
BB14  
BB16  
BB2  
AU1  
AU11  
AU13  
AU15  
AU17  
AU3  
BB4  
BB6  
AU5  
BB8  
AU7  
BE1  
AU9  
BE11  
BE13  
BE15  
BE17  
BE3  
AV10  
AV12  
AV14  
AV16  
AV2  
BE5  
AV4  
BE7  
AV6  
BE9  
AV8  
BF10  
BF12  
BF14  
BF16  
BF2  
AW1  
AW11  
AW13  
AW15  
AW17  
AW3  
AW5  
AW7  
AW9  
AY10  
AY12  
AY14  
AY16  
AY2  
BF4  
BF6  
BF8  
BG1  
BG11  
BG13  
BG15  
BG17  
BG3  
BG5  
BG7  
AY4  
Datasheet  
85  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 25 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 26 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
BG9  
BH10  
BH12  
BH14  
BH16  
BH2  
BH4  
BH6  
BH8  
BJ1  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
BR11  
BR13  
BR15  
BR17  
BR3  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
BR5  
BR7  
BR9  
BT10  
BT12  
BT14  
BT16  
BT2  
BJ11  
BJ13  
BJ15  
BJ17  
BJ3  
BT4  
BT6  
BJ5  
BT8  
BJ7  
BU1  
BJ9  
BU11  
BU13  
BU15  
BU17  
BU3  
BK10  
BK12  
BK14  
BK16  
BK2  
BU5  
BK4  
BU7  
BK6  
BU9  
BK8  
BV10  
BV12  
BV14  
BV16  
BV2  
BN1  
BN11  
BN13  
BN15  
BN17  
BN3  
BN5  
BN7  
BN9  
BP10  
BP12  
BP14  
BP16  
BP2  
BV4  
BV6  
BV8  
BY18  
BY26  
BY28  
BY30  
BY32  
BY34  
BY36  
BY38  
BY40  
CA25  
CA29  
BP4  
BP6  
BP8  
BR1  
86  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 27 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 28 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
VCC_SENSE  
Direction  
Land Name  
Direction  
BW3  
CD20  
CD22  
CD24  
CD26  
CD28  
CJ19  
CJ21  
CJ23  
CJ25  
CJ27  
CP20  
CP22  
CP24  
CP26  
CP28  
CW19  
CW21  
CW23  
CW25  
CW27  
DD18  
DD20  
DD22  
DD24  
DD26  
AC17  
AC19  
AC21  
AC23  
AC25  
C15  
O
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCPLL  
VCCPLL  
VCCPLL  
VSA  
N19  
N21  
N23  
V16  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_01  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
V18  
V20  
V22  
V24  
BY14  
CA13  
CA15  
AE15  
AE17  
AF18  
AG15  
AG17  
AH10  
AH12  
AH14  
AH16  
AH2  
AH4  
AH6  
AH8  
AJ1  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
VSA  
AJ11  
AJ13  
AJ3  
VSA  
VSA  
VSA  
AJ5  
VSA  
AJ7  
VSA  
AJ9  
VSA  
B54  
C17  
VSA  
G43  
G49  
N45  
N51  
AG13  
A41  
C19  
VSA  
C21  
VSA  
C23  
VSA  
G13  
VSA_SENSE  
VSS  
O
H16  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
H18  
VSS  
A43  
H20  
VSS  
A45  
H22  
VSS  
A47  
H24  
VSS  
A49  
N15  
VSS  
A5  
N17  
VSS  
A51  
Datasheet  
87  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 29 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 30 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
A7  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AG1  
AG3  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
AA11  
AA29  
AA3  
AG43  
AG5  
AA31  
AA39  
AA5  
AG55  
AG57  
AG9  
AA55  
AA9  
AH58  
AJ15  
AJ17  
AK10  
AK12  
AK14  
AK16  
AK2  
AB14  
AB36  
AB42  
AB6  
AC31  
AC9  
AD26  
AD34  
AD36  
AD42  
AD44  
AD46  
AD48  
AD50  
AD52  
AD6  
AK4  
AK42  
AK44  
AK46  
AK48  
AK50  
AK6  
AK8  
AL43  
AL45  
AL49  
AL51  
AL53  
AM56  
AN55  
AN57  
AP42  
AP44  
AP58  
AR1  
AE29  
AE31  
AE39  
AE43  
AE47  
AE49  
AE51  
AE9  
AF12  
AF16  
AF20  
AF26  
AF34  
AF36  
AF40  
AF42  
AF54  
AF56  
AF6  
AR11  
AR13  
AR15  
AR17  
AR3  
AR5  
AR7  
AR9  
AT10  
88  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 31 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 32 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
VSS  
Direction  
Land Name  
Direction  
AT12  
AT14  
AT16  
AT2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
BD14  
BD16  
BD2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
BD4  
AT4  
BD54  
BD56  
BD6  
AT46  
AT52  
AT6  
BD8  
AT8  
BE49  
BE51  
BF42  
BF44  
BG47  
BH58  
BJ55  
BJ57  
BK42  
BK46  
BK48  
BK50  
BK52  
BK54  
BL1  
AU45  
AU47  
AU49  
AU51  
AV42  
AV54  
AV56  
AW55  
AW57  
B36  
B52  
B6  
B8  
BB42  
BB46  
BB48  
BB50  
BB52  
BB58  
BC1  
BL11  
BL13  
BL15  
BL17  
BL3  
BL49  
BL5  
BC11  
BC13  
BC15  
BC17  
BC3  
BL7  
BL9  
BM10  
BM12  
BM14  
BM16  
BM2  
BC43  
BC45  
BC5  
BC53  
BC55  
BC57  
BC7  
BM4  
BM6  
BM8  
BN43  
BN45  
BP58  
BR53  
BC9  
BD10  
BD12  
Datasheet  
89  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 33 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 34 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
BR57  
BT46  
BT48  
BT50  
BT52  
BT54  
BT56  
BU45  
BU51  
BW1  
BW11  
BW13  
BW15  
BW17  
BW5  
BW7  
BY24  
BY4  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CB48  
CB50  
CB52  
CB56  
CB6  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
CB8  
CC13  
CC29  
CC3  
CC43  
CC47  
CC49  
CC9  
CD18  
CD36  
CD6  
CE13  
CE5  
BY42  
BY58  
BY8  
CE9  
CF12  
CF14  
CF30  
CF32  
CF34  
CF36  
CF38  
CF40  
CF42  
CF6  
C11  
C13  
C3  
C33  
C39  
C41  
C5  
C55  
CA11  
CA19  
CA27  
CA31  
CA33  
CA35  
CA37  
CA39  
CA41  
CA5  
CG15  
CG31  
CG33  
CG35  
CG37  
CG39  
CG41  
CG43  
CG53  
CG9  
CA55  
CA57  
CB16  
CB36  
CB46  
CH12  
CH16  
CH36  
CH44  
CH46  
90  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 35 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 36 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
VSS  
Direction  
Land Name  
Direction  
CH48  
CH50  
CH52  
CH54  
CH6  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CN55  
CN57  
CN7  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CN9  
CP12  
CP16  
CP36  
CP40  
CP42  
CP44  
CP46  
CP48  
CP50  
CP52  
CP56  
CR11  
CR35  
CR47  
CR49  
CR5  
CJ11  
CJ17  
CJ29  
CJ3  
CJ43  
CJ45  
CJ47  
CJ51  
CJ9  
CK10  
CK36  
CK4  
CK6  
CL17  
CL43  
CL5  
CR9  
CM10  
CM14  
CM30  
CM32  
CM34  
CM36  
CM38  
CM40  
CM42  
CM6  
CT28  
CT42  
CU1  
CU11  
CU3  
CU35  
CU5  
CV14  
CV18  
CV30  
CV32  
CV34  
CV38  
CV42  
CV54  
CV58  
CV6  
CM8  
CN11  
CN13  
CN15  
CN17  
CN3  
CN31  
CN33  
CN35  
CN37  
CN39  
CN5  
CW11  
CW13  
CW15  
CW29  
CW31  
CW33  
CN53  
Datasheet  
91  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 37 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 38 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CW35  
CW37  
CW39  
CW5  
CW51  
CW53  
CW55  
CW57  
CW7  
CY10  
CY12  
CY16  
CY2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DD38  
DD6  
DE17  
DE41  
DE53  
DE7  
DF12  
DF36  
DF42  
DF44  
DF46  
DF48  
DF50  
DF52  
DF8  
E1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
CY36  
CY40  
CY44  
CY50  
CY8  
E29  
E3  
D2  
E31  
E41  
E5  
D26  
D36  
D8  
F36  
DA11  
DA3  
F42  
F44  
DA41  
DA43  
DA45  
DA47  
DA5  
F48  
F50  
F8  
G1  
G25  
G31  
G35  
G37  
G41  
G45  
G47  
G5  
DA51  
DA9  
DB12  
DB2  
DB32  
DB36  
DB58  
DC3  
G51  
G53  
G57  
G9  
DC41  
DC5  
DD10  
DD12  
DD14  
DD34  
DD36  
H10  
H12  
H14  
H32  
92  
Datasheet  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 39 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 40 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
VSS  
Direction  
Land Name  
Direction  
H34  
H38  
H40  
H52  
H54  
H8  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
P12  
P14  
P26  
P30  
P32  
P38  
P40  
P54  
P56  
P8  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
J11  
J27  
J31  
J33  
J39  
J41  
J5  
R11  
R29  
R3  
J55  
K2  
R31  
R35  
R39  
R5  
K26  
K28  
K30  
K34  
K8  
R55  
R7  
T28  
T4  
L25  
L29  
L41  
L5  
T42  
T6  
T8  
M34  
M36  
M42  
M44  
M46  
M50  
M52  
M8  
U35  
U5  
V26  
V28  
V34  
V36  
V42  
V44  
V46  
V48  
V50  
V8  
N13  
N33  
N35  
N37  
N41  
N43  
N47  
N49  
N5  
W13  
W33  
W37  
W41  
W43  
W45  
W47  
W5  
N53  
N9  
P10  
Datasheet  
93  
Processor Land Listing  
Table 8-1.  
Land List by Land Name  
(Sheet 41 of 42)  
Table 8-1.  
Land List by Land Name  
(Sheet 42 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
VSS  
W51  
W53  
W9  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VTTD  
BV42  
BY20  
BY22  
CA21  
CA23  
BP42  
PWR  
PWR  
PWR  
PWR  
PWR  
VSS  
VTTD  
VSS  
VTTD  
VSS  
Y10  
VTTD  
VSS  
Y12  
VTTD  
VSS  
Y28  
VTTD_SENSE  
O
VSS  
Y30  
VSS  
Y32  
VSS  
Y36  
VSS  
Y38  
VSS  
Y40  
VSS  
Y42  
VSS  
Y56  
VSS_VCC_SENSE  
VSS_VSA_SENSE  
VSS_VTTD_SENSE  
VTTA  
BY2  
O
O
O
AF14  
BT42  
AE45  
AE53  
AM48  
AM54  
AU53  
CA53  
CC45  
CG55  
CJ49  
CR45  
CR51  
DA49  
W49  
Y54  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTA  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
VTTD  
AF22  
AF24  
AG21  
AG23  
AM42  
AT42  
AY42  
BD42  
BH42  
BK56  
BL51  
BM42  
BR55  
BU47  
94  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 1 of 42)  
Table 8-2.  
Land List by Land  
Number (Sheet 2 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
A11  
A13  
DDR3_DQ[33]  
DDR3_MA[13]  
DDR3_WE_N  
DDR3_BA[0]  
DDR3_MA[00]  
DDR3_MA[05]  
DDR3_MA[11]  
DDR3_DQ[22]  
DDR3_DQ[16]  
DDR3_DQ[07]  
DDR3_DQ[01]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I/O  
O
AA55  
AA7  
VSS  
GND  
SSTL  
GND  
DDR2_DQS_DN[14]  
VSS  
I/O  
A15  
O
AA9  
A17  
O
AB10  
AB12  
AB14  
AB16  
AB18  
AB20  
AB22  
AB24  
AB28  
AB32  
AB34  
AB36  
AB38  
AB4  
DDR2_DQ[38]  
DDR2_DQS_DP[13]  
VSS  
SSTL  
SSTL  
GND  
I/O  
I/O  
A19  
O
A21  
O
A23  
O
DDR2_CS_N[6]  
DDR2_MA[00]  
DDR2_CS_N[0]  
DDR2_CLK_DP[1]  
DDR2_CLK_DP[0]  
DDR2_DQS_DN[08]  
DDR2_DQ[30]  
DDR2_DQS_DN[12]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
O
O
A33  
I/O  
I/O  
I/O  
I/O  
A35  
O
A37  
O
A39  
O
A41  
I/O  
I/O  
I/O  
A43  
VSS  
A45  
VSS  
A47  
VSS  
A49  
VSS  
DDR2_DQS_DP[01]  
DDR2_DQS_DP[07]  
DDR2_DQS_DP[10]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
A5  
VSS  
A51  
VSS  
AB40  
AB42  
AB44  
AB46  
AB48  
AB50  
AB52  
AB54  
AB56  
AB6  
A53  
RSVD  
A7  
VSS  
GND  
SSTL  
GND  
PE3D_TX_DN[13]  
PE3C_TX_DN[11]  
RSVD  
PCIEX3  
PCIEX3  
O
O
A9  
DDR3_DQ[39]  
VSS  
I/O  
AA11  
AA13  
AA15  
AA17  
AA19  
AA21  
AA23  
AA25  
AA29  
AA3  
DDR2_DQ[37]  
DDR2_CS_N[3]  
DDR2_CS_N[9]  
DDR2_CS_N[4]  
DDR2_CLK_DP[2]  
DDR2_CLK_DP[3]  
DDR2_CKE[0]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
O
PE3B_RX_DN[4]  
PE3B_RX_DN[5]  
PE2B_RX_DP[4]  
PE2B_RX_DP[5]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I
I
I
I
O
O
O
O
AB8  
DDR2_DQS_DN[05]  
DDR2_DQS_DN[04]  
DDR2_DQ[32]  
DDR23_RCOMP[1]  
VCCD_23  
SSTL  
SSTL  
SSTL  
Analog  
PWR  
I/O  
I/O  
I/O  
I
O
AC11  
AC13  
AC15  
AC17  
AC19  
AC21  
AC23  
AC25  
AC27  
AC29  
AC3  
VSS  
GND  
AA31  
AA33  
AA35  
AA37  
AA39  
AA41  
AA43  
AA45  
AA47  
AA49  
AA5  
VSS  
GND  
DDR2_DQS_DN[03]  
DDR2_DQ[28]  
DDR2_DQ[10]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
VCCD_23  
PWR  
VCCD_23  
PWR  
VCCD_23  
PWR  
VCCD_23  
PWR  
DDR2_DQ[13]  
PE3D_TX_DN[14]  
PE3D_TX_DP[12]  
PE3C_TX_DP[9]  
PE3A_RX_DP[3]  
VSS  
SSTL  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I/O  
O
DDR2_DQS_DP[08]  
DDR2_DQS_DP[17]  
DDR2_DQS_DN[07]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
O
O
AC31  
AC33  
AC35  
AC37  
AC39  
I
DDR2_DQS_DP[03]  
DDR2_DQ[24]  
DDR2_DQ[11]  
DDR2_DQS_DN[10]  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
AA51  
AA53  
PE3B_RX_DP[7]  
PE3B_RX_DP[6]  
PCIEX3  
PCIEX3  
I
I
Datasheet  
95  
 
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 3 of 42)  
Table 8-2.  
Land List by Land  
Number (Sheet 4 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
AC41  
AC43  
AC45  
AC47  
AC49  
AC5  
DDR2_DQ[12]  
SSTL  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
SSTL  
PCIEX3  
PCIEX3  
PCIEX3  
SSTL  
GND  
I/O  
O
AE25  
AE27  
DDR2_CKE[4]  
SSTL  
O
O
PE3D_TX_DP[14]  
PE3D_TX_DN[12]  
PE3C_TX_DN[9]  
PE3A_RX_DN[3]  
DDR2_DQS_DP[16]  
PE3B_RX_DN[7]  
PE3B_RX_DN[6]  
PE2B_RX_DP[6]  
DDR2_DQS_DP[05]  
VSS  
DDR_RESET_C23_N CMOS1.5  
v
O
AE29  
AE3  
VSS  
GND  
SSTL  
GND  
O
DDR2_DQ[63]  
VSS  
I/O  
I
AE31  
AE33  
AE35  
AE37  
AE39  
AE41  
AE43  
AE45  
AE47  
AE49  
AE5  
I/O  
I
DDR2_DQ[26]  
DDR2_DQ[25]  
DDR2_DQ[15]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
AC51  
AC53  
AC55  
AC7  
I
I
I/O  
DDR2_DQ[08]  
VSS  
SSTL  
GND  
I/O  
AC9  
AD10  
AD12  
AD14  
AD16  
AD18  
AD20  
AD22  
AD24  
AD26  
AD28  
AD32  
AD34  
AD36  
AD38  
AD4  
DDR2_DQ[39]  
DDR2_DQS_DN[13]  
DDR2_DQ[36]  
DDR2_CS_N[2]  
DDR2_ODT[2]  
DDR2_PAR_ERR_N  
DDR2_ODT[4]  
DDR2_CKE[3]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
O
VTTA  
PWR  
VSS  
GND  
VSS  
GND  
DDR2_DQ[59]  
VSS  
SSTL  
GND  
I/O  
O
AE51  
AE53  
AE55  
AE57  
AE7  
I
VTTA  
PWR  
O
PE2B_RX_DN[6]  
PE2B_RX_DP[7]  
DDR2_DQ[47]  
VSS  
PCIEX3  
PCIEX3  
SSTL  
GND  
I
I
O
I/O  
DDR2_DQS_DN[17]  
DDR2_DQ[31]  
VSS  
SSTL  
SSTL  
GND  
I/O  
I/O  
AE9  
AF10  
AF12  
AF14  
AF16  
AF18  
AF2  
DDR2_DQ[35]  
VSS  
SSTL  
GND  
I/O  
O
VSS  
GND  
VSS_VSA_SENSE  
VSS  
DDR2_DQS_DN[01]  
DDR2_DQS_DN[16]  
DDR2_DQ[09]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
GND  
PWR  
VSA  
AD40  
AD42  
AD44  
AD46  
AD48  
AD50  
AD52  
AD54  
AD56  
AD6  
DDR2_DQ[62]  
VSS  
SSTL  
GND  
I/O  
I/O  
AF20  
AF22  
AF24  
AF26  
AF32  
AF34  
AF36  
AF38  
AF4  
VSS  
GND  
VTTD  
PWR  
VSS  
GND  
VTTD  
PWR  
VSS  
GND  
VSS  
GND  
VSS  
GND  
DDR2_DQ[27]  
VSS  
SSTL  
GND  
VSS  
GND  
PE2B_RX_DN[4]  
PE2B_RX_DN[5]  
VSS  
PCIEX3  
PCIEX3  
GND  
I
I
VSS  
GND  
DDR2_DQ[14]  
DDR2_DQ[58]  
VSS  
SSTL  
SSTL  
GND  
I/O  
I/O  
AD8  
DDR2_DQ[46]  
DDR2_DQS_DP[04]  
DDR2_DQ[33]  
VSA  
SSTL  
SSTL  
SSTL  
PWR  
I/O  
I/O  
I/O  
AF40  
AF42  
AF44  
AF46  
AF48  
AF50  
AF52  
AE11  
AE13  
AE15  
AE17  
AE19  
AE21  
AE23  
VSS  
GND  
PE3A_RX_DP[0]  
PE3A_RX_DP[2]  
PE3C_RX_DP[8]  
PE3C_RX_DP[10]  
PE_RBIAS_SENSE  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
I
I
I
I
I
VSA  
PWR  
DDR2_CS_N[1]  
DDR2_ODT[5]  
DDR2_CKE[5]  
SSTL  
SSTL  
SSTL  
O
O
O
96  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 5 of 42)  
Table 8-2.  
Land List by Land  
Number (Sheet 6 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
AF54  
AF56  
AF58  
AF6  
VSS  
GND  
GND  
AH50  
AH52  
AH54  
AH56  
AH58  
AH6  
PE3C_RX_DN[10]  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I
I/O  
O
VSS  
PE_RBIAS  
PE2B_RX_DN[7]  
PCIEX3  
GND  
I
PE2B_TX_DP[5]  
VSS  
PE2C_RX_DP[8]  
I
AF8  
DDR2_DQ[42]  
SSTL  
GND  
I/O  
VSS  
AG1  
VSS  
VSA  
PWR  
AG11  
AG13  
AG15  
AG17  
AG19  
AG21  
AG23  
AG25  
AG27  
AG29  
AG3  
DDR2_DQ[34]  
SSTL  
I/O  
O
AH8  
VSA  
PWR  
VSA_SENSE  
AJ1  
VSA  
PWR  
VSA  
PWR  
PWR  
AJ11  
AJ13  
AJ15  
AJ17  
AJ3  
VSA  
PWR  
VSA  
VSA  
PWR  
VCC  
PWR  
VSS  
GND  
VTTD  
PWR  
VSS  
GND  
VTTD  
PWR  
VSA  
PWR  
VCC  
PWR  
AJ43  
AJ45  
AJ47  
AJ49  
AJ5  
PE_VREF_CAP  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PWR  
I/O  
VCC  
PWR  
PE3A_RX_DN[1]  
I
I
I
VCC  
PWR  
PE3D_RX_DN[12]  
VSS  
GND  
PE3C_RX_DN[11]  
AG31  
AG33  
AG35  
AG37  
AG39  
AG41  
AG43  
AG45  
AG47  
AG49  
AG5  
VCC  
PWR  
VSA  
VCC  
PWR  
AJ51  
AJ53  
AJ55  
AJ57  
AJ7  
PE3C_RX_DN[9]  
PCIEX3  
PCIEX3  
I
VCC  
PWR  
PE2B_TX_DN[4]  
O
VCC  
PWR  
RSVD  
VCC  
PWR  
PE2C_RX_DP[10]  
PCIEX3  
PWR  
I
VCC  
PWR  
VSA  
VSS  
GND  
AJ9  
VSA  
PWR  
PE3A_RX_DP[1]  
PE3D_RX_DP[12]  
PE3C_RX_DP[11]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I
I
I
AK10  
AK12  
AK14  
AK16  
AK2  
VSS  
GND  
VSS  
GND  
VSS  
GND  
VSS  
GND  
AG51  
AG53  
AG55  
AG57  
AG7  
PE3C_RX_DP[9]  
PE2B_TX_DP[4]  
VSS  
PCIEX3  
PCIEX3  
GND  
I
VSS  
GND  
O
AK4  
VSS  
GND  
AK42  
AK44  
AK46  
AK48  
AK50  
AK52  
AK54  
AK56  
AK58  
AK6  
VSS  
GND  
VSS  
GND  
VSS  
GND  
DDR2_DQ[43]  
VSS  
SSTL  
GND  
I/O  
VSS  
GND  
AG9  
VSS  
GND  
AH10  
AH12  
AH14  
AH16  
AH2  
VSA  
PWR  
VSS  
GND  
VSA  
PWR  
TXT_AGENT  
PE2B_TX_DN[5]  
PE2C_RX_DN[8]  
PE2C_RX_DP[9]  
VSS  
CMOS  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I
O
I
VSA  
PWR  
VSA  
PWR  
VSA  
PWR  
I
AH4  
VSA  
PWR  
AH42  
AH44  
AH46  
AH48  
IVT_ID_N  
PE3A_RX_DN[0]  
PE3A_RX_DN[2]  
PE3C_RX_DN[8]  
O
I
AK8  
VSS  
GND  
PCIEX3  
PCIEX3  
PCIEX3  
AL1  
VCC  
PWR  
I
AL11  
AL13  
VCC  
PWR  
I
VCC  
PWR  
Datasheet  
97  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 7 of 42)  
Table 8-2.  
Land List by Land  
Number (Sheet 8 of 42)  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
AL15  
AL17  
AL3  
VCC  
PWR  
PWR  
PWR  
GND  
GND  
GND  
PWR  
GND  
GND  
AN57  
AN7  
VSS  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
PCIEX3  
VCC  
VCC  
VCC  
AN9  
VCC  
AL43  
AL45  
AL49  
AL5  
VSS  
AP10  
AP12  
AP14  
AP16  
AP2  
VCC  
VSS  
VCC  
VSS  
VCC  
VCC  
VCC  
AL51  
AL53  
AL55  
AL57  
AL7  
VSS  
VCC  
VSS  
AP4  
VCC  
RSVD  
AP42  
AP44  
AP46  
AP48  
AP50  
AP52  
AP54  
AP56  
AP58  
AP6  
VSS  
PE2C_RX_DN[10]  
PCIEX3  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
I
VSS  
VCC  
PE3D_RX_DN[14]  
I
AL9  
VCC  
RSVD  
AM10  
AM12  
AM14  
AM16  
AM2  
VCC  
PE2A_TX_DN[1]  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
I
VCC  
PE2A_TX_DN[3]  
VCC  
PE2B_TX_DP[7]  
VCC  
PE2D_RX_DP[13]  
VCC  
VSS  
AM4  
VCC  
VCC  
PWR  
AM42  
AM44  
AM46  
AM48  
AM50  
AM52  
AM54  
AM56  
AM58  
AM6  
VTTD  
AP8  
VCC  
PWR  
RSVD  
AR1  
VSS  
GND  
PE3D_RX_DP[14]  
VTTA  
PCIEX3  
PWR  
I
AR11  
AR13  
AR15  
AR17  
AR3  
VSS  
GND  
VSS  
GND  
PE2A_TX_DP[1]  
PE2A_TX_DP[3]  
VTTA  
PCIEX3  
PCIEX3  
PWR  
O
O
VSS  
GND  
VSS  
GND  
VSS  
GND  
VSS  
GND  
AR43  
AR45  
AR47  
AR49  
AR5  
BPM_N[0]  
ODCMOS  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I/O  
I
PE2C_RX_DN[9]  
VCC  
PCIEX3  
PWR  
I
PE3D_RX_DN[15]  
PE3D_RX_DN[13]  
I
AM8  
VCC  
PWR  
PE2A_TX_DN[0]  
O
AN1  
VCC  
PWR  
VSS  
AN11  
AN13  
AN15  
AN17  
AN3  
VCC  
PWR  
AR51  
AR53  
AR55  
AR57  
AR7  
PE2A_TX_DN[2]  
PCIEX3  
PCIEX3  
O
O
VCC  
PWR  
PE2B_TX_DN[6]  
VCC  
PWR  
RSVD  
VCC  
PWR  
PE2C_RX_DP[11]  
PCIEX3  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PWR  
I
VCC  
PWR  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VTTD  
AN43  
AN45  
AN47  
AN49  
AN5  
CPU_ONLY_RESET  
PE3D_RX_DP[15]  
PE3D_RX_DP[13]  
PE2A_TX_DP[0]  
VCC  
ODCMOS  
PCIEX3  
PCIEX3  
PCIEX3  
PWR  
I/O  
I
AR9  
AT10  
AT12  
AT14  
AT16  
AT2  
I
O
AN51  
AN53  
AN55  
PE2A_TX_DP[2]  
PE2B_TX_DP[6]  
VSS  
PCIEX3  
PCIEX3  
GND  
O
O
AT4  
AT42  
98  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 9 of 42)  
Table 8-2.  
Land List by Land  
Number (Sheet 10 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
AT44  
AT46  
AT48  
AT52  
AT54  
AT56  
AT58  
AT6  
BPM_N[1]  
ODCMOS  
GND  
I/O  
AW11 VCC  
AW13 VCC  
AW15 VCC  
AW17 VCC  
PWR  
PWR  
VSS  
BIST_ENABLE  
CMOS  
GND  
I
PWR  
VSS  
PWR  
PE2B_TX_DN[7]  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
I
AW3  
VCC  
PWR  
PE2D_RX_DN[13]  
AW43 BPM_N[5]  
ODCMOS  
CMOS  
PCIEX3  
PCIEX3  
PWR  
I/O  
I
PE2D_RX_DP[12]  
I
AW45 BCLK1_DP  
VSS  
AW47 PE2D_TX_DP[15]  
AW49 PE2D_TX_DP[13]  
O
AT8  
VSS  
GND  
O
AU1  
VCC  
PWR  
AW5  
VCC  
AU11  
AU13  
AU15  
AU17  
AU3  
VCC  
PWR  
AW51 PE2C_TX_DP[11]  
AW53 PE2C_TX_DP[9]  
AW55 VSS  
PCIEX3  
PCIEX3  
GND  
O
O
VCC  
PWR  
VCC  
PWR  
VCC  
PWR  
AW57 VSS  
GND  
VCC  
PWR  
AW7  
AW9  
AY10  
AY12  
AY14  
AY16  
AY2  
VCC  
PWR  
AU43  
AU45  
AU47  
AU49  
AU5  
BPM_N[2]  
ODCMOS  
GND  
I/O  
VCC  
PWR  
VSS  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VCC  
PWR  
VCC  
PWR  
AU51  
AU53  
AU55  
AU57  
AU7  
VSS  
GND  
VCC  
PWR  
VTTA  
PWR  
AY4  
VCC  
PWR  
RSVD  
AY42  
AY44  
AY46  
AY48  
AY50  
AY52  
AY54  
AY56  
AY58  
AY6  
VTTD  
PWR  
PE2C_RX_DN[11]  
PCIEX3  
PWR  
I
BPM_N[7]  
RSVD  
ODCMOS  
I/O  
VCC  
AU9  
VCC  
PWR  
PE2D_TX_DN[14]  
PE2D_TX_DN[12]  
PE2C_TX_DN[8]  
PE2C_TX_DP[10]  
PE2D_RX_DP[15]  
PE2D_RX_DP[14]  
VCC  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PWR  
O
O
O
O
I
AV10  
AV12  
AV14  
AV16  
AV2  
VCC  
PWR  
VCC  
PWR  
VCC  
PWR  
VCC  
PWR  
VCC  
PWR  
I
AV4  
VCC  
PWR  
AV42  
AV44  
AV46  
AV48  
AV50  
AV52  
AV54  
AV56  
AV58  
AV6  
VSS  
GND  
AY8  
VCC  
PWR  
BPM_N[3]  
RSVD  
ODCMOS  
I/O  
B10  
DDR3_DQS_DN[04]  
DDR3_DQ[37]  
DDR3_CAS_N  
DDR3_RAS_N  
DDR3_MA_PAR  
DDR3_MA[03]  
DDR3_MA[07]  
DDR3_BA[2]  
DDR3_DQ[23]  
DDR3_DQS_DN[11]  
VSS  
SSTL  
I/O  
I/O  
O
B12  
SSTL  
PE2D_TX_DP[14]  
PE2D_TX_DP[12]  
PE2C_TX_DP[8]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
B14  
SSTL  
B16  
SSTL  
O
B18  
SSTL  
O
B20  
SSTL  
O
VSS  
GND  
B22  
SSTL  
O
PE2D_RX_DN[12]  
VCC  
PCIEX3  
PWR  
I
B24  
SSTL  
O
B32  
SSTL  
I/O  
I/O  
AV8  
VCC  
PWR  
B34  
SSTL  
AW1  
VCC  
PWR  
B36  
GND  
Datasheet  
99  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 11 of  
Table 8-2.  
Land List by Land  
Number (Sheet 12 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
B38  
B40  
DDR3_DQS_DN[00]  
SSTL  
SSTL  
I/O  
I/O  
O
BB8  
BC1  
VCC  
PWR  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
DDR3_DQ[00]  
VSS  
B42  
DMI_TX_DP[0]  
PCIEX  
PCIEX  
BC11  
BC13  
BC15  
BC17  
BC3  
VSS  
B44  
DMI_TX_DP[2]  
O
VSS  
B46  
RSVD  
VSS  
B48  
DMI_RX_DP[1]  
PCIEX  
PCIEX  
GND  
I
I
VSS  
B50  
DMI_RX_DP[3]  
VSS  
B52  
VSS  
BC43  
BC45  
BC47  
BC5  
VSS  
B54  
VSA  
PWR  
VSS  
B6  
VSS  
GND  
RSVD  
VSS  
B8  
VSS  
GND  
GND  
ODCMOS  
GND  
BA1  
VCC  
PWR  
BC51  
BC53  
BC55  
BC57  
BC7  
ERROR_N[2]  
VSS  
O
BA11  
BA13  
BA15  
BA17  
BA3  
VCC  
PWR  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
BC9  
VSS  
GND  
BA43  
BA45  
BA47  
BA49  
BA5  
BPM_N[6]  
ODCMOS  
CMOS  
PCIEX3  
PCIEX3  
PWR  
I/O  
I
BD10  
BD12  
BD14  
BD16  
BD2  
VSS  
GND  
BCLK1_DN  
VSS  
GND  
PE2D_TX_DN[15]  
O
VSS  
GND  
PE2D_TX_DN[13]  
O
VSS  
GND  
VCC  
VSS  
GND  
BA51  
BA53  
BA55  
BA57  
BA7  
PE2C_TX_DN[11]  
PCIEX3  
PCIEX3  
O
O
I
BD4  
VSS  
GND  
PE2C_TX_DN[9]  
BD42  
BD44  
BD46  
BD48  
BD50  
BD52  
BD54  
BD56  
BD6  
VTTD  
RSVD  
RSVD  
RSVD  
ERROR_N[0]  
PROCHOT_N  
VSS  
PWR  
TEST4  
PE2D_RX_DN[14]  
PCIEX3  
PWR  
I
VCC  
BA9  
VCC  
PWR  
ODCMOS  
ODCMOS  
GND  
O
BB10  
BB12  
BB14  
BB16  
BB2  
VCC  
PWR  
I/O  
VCC  
PWR  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
BD8  
VSS  
GND  
BB4  
VCC  
PWR  
BE1  
VCC  
PWR  
BB42  
BB44  
BB46  
BB48  
BB50  
BB52  
BB54  
BB56  
BB58  
BB6  
VSS  
GND  
BE11  
BE13  
BE15  
BE17  
BE3  
VCC  
PWR  
BPM_N[4]  
ODCMOS  
GND  
I/O  
VCC  
PWR  
VSS  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
BE43  
BE45  
BE47  
BE49  
BE5  
RSVD  
RSVD  
RSVD  
VSS  
PE2C_TX_DN[10]  
PE2D_RX_DN[15]  
VSS  
PCIEX3  
PCIEX3  
GND  
O
I
GND  
PWR  
VCC  
PWR  
VCC  
100  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 13 of  
Table 8-2.  
Land List by Land  
Number (Sheet 14 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
BE51  
BE7  
VSS  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
BJ17  
BJ3  
VCC  
PWR  
PWR  
VCC  
VCC  
BE9  
VCC  
BJ43  
BJ45  
BJ47  
BJ5  
RSVD  
RSVD  
PECI  
VCC  
BF10  
BF12  
BF14  
BF16  
BF2  
VCC  
VCC  
PECI  
PWR  
CMOS  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
I/O  
I
VCC  
VCC  
BJ53  
BJ55  
BJ57  
BJ7  
PWRGOOD  
VSS  
VCC  
BF4  
VCC  
VSS  
BF42  
BF44  
BF46  
BF48  
BF6  
VSS  
VCC  
VSS  
BJ9  
VCC  
RSVD  
PEHPSDA  
VCC  
BK10  
BK12  
BK14  
BK16  
BK2  
VCC  
ODCMOS  
PWR  
I/O  
VCC  
VCC  
BF8  
VCC  
PWR  
VCC  
BG1  
VCC  
PWR  
VCC  
BG11  
BG13  
BG15  
BG17  
BG3  
VCC  
PWR  
BK4  
VCC  
VCC  
PWR  
BK42  
BK44  
BK46  
BK48  
BK50  
BK52  
BK54  
BK56  
BK6  
VSS  
VCC  
PWR  
RSVD  
VSS  
VCC  
PWR  
GND  
GND  
GND  
GND  
GND  
PWR  
PWR  
PWR  
GND  
GND  
GND  
GND  
GND  
GND  
VCC  
PWR  
VSS  
BG43  
BG45  
BG47  
BG5  
RSVD  
RSVD  
VSS  
VSS  
VSS  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VSS  
VCC  
VTTD  
VCC  
BG7  
VCC  
BG9  
VCC  
BK8  
VCC  
BH10  
BH12  
BH14  
BH16  
BH2  
VCC  
BL1  
VSS  
VCC  
BL11  
BL13  
BL15  
BL17  
BL3  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
BH4  
VCC  
VSS  
BH42  
BH44  
BH46  
BH48  
BH58  
BH6  
VTTD  
RSVD  
RSVD  
PEHPSCL  
VSS  
BL43  
BL45  
BL47  
BL49  
BL5  
RSVD  
RSVD  
THERMTRIP_N  
VSS  
ODCMOS  
GND  
O
ODCMOS  
GND  
I/O  
VSS  
GND  
VCC  
PWR  
BL51  
BL7  
VTTD  
VSS  
PWR  
BH8  
VCC  
PWR  
GND  
BJ1  
VCC  
PWR  
BL9  
VSS  
GND  
BJ11  
BJ13  
BJ15  
VCC  
PWR  
BM10  
BM12  
BM14  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
VCC  
PWR  
VSS  
GND  
Datasheet  
101  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 15 of  
Table 8-2.  
Land List by Land  
Number (Sheet 16 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
BM16  
BM2  
VSS  
GND  
GND  
GND  
PWR  
BR57  
BR7  
VSS  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VSS  
VCC  
BM4  
VSS  
BR9  
VCC  
BM42  
BM44  
BM46  
BM6  
VTTD  
RSVD  
RSVD  
VSS  
BT10  
BT12  
BT14  
BT16  
BT2  
VCC  
VCC  
VCC  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
VCC  
BM8  
VSS  
VCC  
BN1  
VCC  
BT4  
VCC  
BN11  
BN13  
BN15  
BN17  
BN3  
VCC  
BT42  
BT44  
BT46  
BT48  
BT50  
BT52  
BT54  
BT56  
BT6  
VSS_VTTD_SENSE  
RSVD  
VSS  
O
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCC  
VSS  
VCC  
VSS  
BN43  
BN45  
BN47  
BN5  
VSS  
VSS  
VSS  
VSS  
RSVD  
VCC  
VSS  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VCC  
BN7  
VCC  
BT8  
VCC  
BN9  
VCC  
BU1  
VCC  
BP10  
BP12  
BP14  
BP16  
BP2  
VCC  
BU11  
BU13  
BU15  
BU17  
BU3  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
BP4  
VCC  
BU43  
BU45  
BU47  
BU49  
BU5  
RSVD  
VSS  
BP42  
BP44  
BP46  
BP58  
BP6  
VTTD_SENSE  
RSVD  
RSVD  
VSS  
O
GND  
PWR  
VTTD  
SKTOCC_N  
VCC  
O
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
CMOS  
PWR  
PWR  
GND  
VCC  
BU51  
BU7  
VSS  
BP8  
VCC  
VCC  
BR1  
VCC  
BU9  
VCC  
BR11  
BR13  
BR15  
BR17  
BR3  
VCC  
BV10  
BV12  
BV14  
BV16  
BV2  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
BR43  
BR45  
BR47  
BR5  
RSVD  
SVIDDATA  
RSVD  
VCC  
BV4  
VCC  
ODCMOS  
I/O  
BV42  
BV44  
BV6  
VTTD  
TMS  
I
PWR  
GND  
PWR  
VCC  
BR53  
BR55  
VSS  
BV8  
VCC  
VTTD  
BW1  
VSS  
102  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 17 of  
Table 8-2.  
Land List by Land  
Number (Sheet 18 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
BW11 VSS  
BW13 VSS  
BW15 VSS  
BW17 VSS  
GND  
GND  
GND  
GND  
C37  
C39  
DDR3_DQ[02]  
SSTL  
GND  
I/O  
VSS  
C41  
VSS  
GND  
C43  
DMI_TX_DP[1]  
DMI_TX_DP[3]  
DMI_RX_DP[0]  
DMI_RX_DP[2]  
VSS  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
GND  
O
O
I
BW3  
VCC_SENSE  
O
I
C45  
BW43 TDI  
CMOS  
GND  
GND  
SSTL  
SSTL  
SSTL  
PWR  
DC  
C47  
BW5  
BW7  
BW9  
BY10  
BY12  
BY14  
BY16  
VSS  
C49  
I
VSS  
C5  
DDR0_DQ[28]  
DDR0_DQ[24]  
DDR0_DQ[25]  
VCCPLL  
I/O  
I/O  
I/O  
C51  
PE1A_RX_DP[0]  
RSVD  
PCIEX3  
I
C53  
C55  
VSS  
GND  
SSTL  
SSTL  
SSTL  
GND  
C7  
DDR3_DQ[52]  
DDR3_DQ[34]  
DDR0_DQ[12]  
VSS  
I/O  
I/O  
I/O  
DDR_VREFDQRX_C0  
1
I
C9  
CA1  
BY18  
BY2  
VCC  
PWR  
CA11  
CA13  
CA15  
CA17  
CA19  
CA21  
CA23  
CA25  
CA27  
CA29  
CA3  
VSS_VCC_SENSE  
VTTD  
O
VCCPLL  
VCCPLL  
DDR01_RCOMP[0]  
VSS  
PWR  
BY20  
BY22  
BY24  
BY26  
BY28  
BY30  
BY32  
BY34  
BY36  
BY38  
BY4  
PWR  
PWR  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
PWR  
GND  
CMOS  
PWR  
VTTD  
Analog  
GND  
I
VSS  
VCC  
VTTD  
PWR  
VCC  
VTTD  
PWR  
VCC  
VCC  
PWR  
VCC  
VSS  
GND  
VCC  
VCC  
PWR  
VCC  
DDR0_DQ[13]  
VSS  
SSTL  
GND  
I/O  
VCC  
CA31  
CA33  
CA35  
CA37  
CA39  
CA41  
CA43  
CA45  
CA5  
VSS  
VSS  
GND  
BY40  
BY42  
BY44  
BY46  
BY58  
BY6  
VCC  
VSS  
GND  
VSS  
VSS  
GND  
TCK  
I
VSS  
GND  
RSVD  
VSS  
GND  
VSS  
GND  
SSTL  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
SSTL  
TDO  
ODCMOS  
O
DDR0_DQ[04]  
VSS  
I/O  
RSVD  
BY8  
VSS  
GND  
PWR  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
C11  
VSS  
CA53  
CA55  
CA57  
CA7  
VTTA  
C13  
VSS  
VSS  
C15  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VSS  
VSS  
C17  
DDR0_DQ[05]  
DDR0_DQ[29]  
DDR0_DQS_DP[12]  
DDR0_DQ[26]  
VSS  
I/O  
I/O  
I/O  
I/O  
C19  
CA9  
C21  
CB10  
CB12  
CB16  
CB18  
C23  
C3  
C33  
VSS  
DDR_RESET_C01_N CMOS1.5  
v
O
C35  
DDR3_DQ[21]  
I/O  
Datasheet  
103  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 19 of  
Table 8-2.  
Land List by Land  
Number (Sheet 20 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
CB2  
DDR0_DQ[08]  
SSTL  
Analog  
ODCMOS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I
CC51  
CC7  
CAT_ERR_N  
ODCMOS  
SSTL  
GND  
I/O  
I/O  
CB20  
CB22  
CB24  
CB26  
CB28  
CB30  
CB32  
CB34  
CB36  
CB38  
CB4  
DDR01_RCOMP[2]  
MEM_HOT_C01_N  
DDR0_ODT[4]  
DDR0_CS_N[6]  
DDR0_CS_N[3]  
DDR0_DQ[37]  
DDR0_DQS_DN[13]  
DDR0_DQ[39]  
VSS  
DDR0_DQ[00]  
VSS  
I/O  
O
CC9  
CD10  
CD12  
CD16  
CD18  
CD20  
CD22  
CD24  
CD26  
CD28  
CD30  
CD32  
CD34  
CD36  
CD38  
CD4  
DDR0_DQS_DN[03]  
DDR0_DQ[27]  
DDR0_DQS_DP[17]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
O
O
I/O  
I/O  
I/O  
VCCD_01  
PWR  
VCCD_01  
PWR  
VCCD_01  
PWR  
DDR0_DQ[48]  
DDR0_DQ[09]  
DDR0_DQS_DN[06]  
DDR0_DQ[55]  
SVIDCLK  
SSTL  
SSTL  
SSTL  
SSTL  
ODCMOS  
GND  
I/O  
I/O  
I/O  
I/O  
O
VCCD_01  
PWR  
VCCD_01  
PWR  
CB40  
CB42  
CB44  
CB46  
CB48  
CB50  
CB52  
CB54  
CB56  
CB6  
DDR0_DQ[36]  
DDR0_DQS_DP[13]  
DDR0_DQ[38]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
VSS  
VSS  
GND  
DDR0_DQ[49]  
DDR0_DQS_DN[10]  
DDR0_DQS_DP[06]  
DDR0_DQ[51]  
RSVD  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
VSS  
GND  
VSS  
GND  
CD40  
CD42  
CD44  
CD6  
ERROR_N[1]  
VSS  
ODCMOS  
GND  
O
VSS  
GND  
VSS  
GND  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
CB8  
VSS  
GND  
CD8  
DDR0_DQ[01]  
DDR0_DQS_DP[03]  
VSS  
I/O  
I/O  
CC11  
CC13  
CC17  
CC19  
CC21  
CC23  
CC25  
CC27  
CC29  
CC3  
DDR0_DQS_DN[12]  
VSS  
SSTL  
GND  
I/O  
CE11  
CE13  
CE17  
CE19  
CE21  
CE23  
CE25  
CE27  
CE29  
CE3  
DDR0_DQS_DP[08]  
DDR01_RCOMP[1]  
DDR0_PAR_ERR_N  
DDR0_CS_N[2]  
DDR0_CS_N[7]  
DDR0_ODT[5]  
VSS  
SSTL  
Analog  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I
DDR0_DQS_DN[08]  
DDR0_CKE[5]  
DDR0_CLK_DN[2]  
DDR0_CLK_DN[1]  
DDR0_ODT[0]  
DDR0_ODT[1]  
DDR0_RAS_N  
DDR0_DQS_DN[01]  
DDR0_DQ[32]  
DDR0_DQS_DN[04]  
DDR0_DQ[34]  
DDR0_DQ[53]  
DDR0_DQS_DN[15]  
DDR0_DQ[50]  
RSVD  
I/O  
O
I
O
O
O
O
O
O
O
O
VSS  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CC31  
CC33  
CC35  
CC37  
CC39  
CC41  
CC43  
CC45  
CC47  
CC49  
CC5  
DDR0_DQ[33]  
DDR0_DQS_DP[04]  
DDR0_DQ[35]  
DDR0_DQ[52]  
DDR0_DQS_DP[15]  
DDR0_DQ[54]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CE31  
CE33  
CE35  
CE37  
CE39  
CE41  
CE43  
CE5  
VTTA  
PWR  
VSS  
GND  
SSTL  
GND  
SSTL  
VSS  
GND  
CE7  
DDR0_DQS_DP[09]  
VSS  
I/O  
I/O  
VSS  
GND  
CE9  
DDR0_DQS_DP[10]  
SSTL  
I/O  
CF10  
DDR0_DQ[31]  
104  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 21 of  
Table 8-2.  
Land List by Land  
Number (Sheet 22 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
CF12  
CF14  
CF16  
CF20  
CF22  
CF24  
CF26  
CF28  
CF30  
CF32  
CF34  
CF36  
CF38  
CF4  
VSS  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
SSTL  
GND  
GND  
CH16  
CH20  
CH22  
CH24  
CH26  
CH28  
CH30  
CH32  
CH34  
CH36  
CH38  
CH4  
VSS  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
GND  
ODCMOS  
GND  
SSTL  
GND  
SSTL  
SSTL  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
PWR  
VSS  
DDR0_CKE[2]  
DDR0_CLK_DP[3]  
DDR0_CLK_DP[0]  
DDR0_CS_N[1]  
DDR0_ODT[2]  
DDR0_DQ[45]  
DDR0_DQS_DN[14]  
DDR0_DQ[47]  
VSS  
O
O
DDR0_DQS_DN[17]  
DDR0_CKE[4]  
DDR0_CLK_DN[3]  
DDR0_CLK_DN[0]  
DDR0_CS_N[5]  
DDR0_ODT[3]  
VSS  
I/O  
O
O
O
O
O
O
O
I/O  
I/O  
I/O  
O
VSS  
VSS  
DDR0_DQ[56]  
DDR0_DQ[10]  
DDR0_DQS_DN[07]  
DDR0_DQ[58]  
VSS  
I/O  
I/O  
I/O  
I/O  
VSS  
VSS  
CH40  
CH42  
CH44  
CH46  
CH48  
CH50  
CH52  
CH54  
CH56  
CH6  
DDR0_DQS_DP[01]  
VSS  
I/O  
CF40  
CF42  
CF44  
CF6  
VSS  
VSS  
RSVD  
VSS  
VSS  
GND  
VSS  
CF8  
DDR0_DQS_DN[09]  
RSVD  
SSTL  
I/O  
I/O  
VSS  
CG11  
CG13  
CG15  
CG19  
CG21  
CG23  
CG25  
CG27  
CG29  
CG3  
VSS  
DDR0_DQ[20]  
VSS  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
SSTL  
GND  
PWR  
SSTL  
GND  
SSTL  
GND  
SSTL  
EAR_N  
I/O  
I/O  
VSS  
DDR0_MA[14]  
DDR0_CLK_DP[2]  
DDR0_CLK_DP[1]  
DDR0_MA[02]  
DDR0_CS_N[4]  
DDR0_MA[13]  
DDR0_DQ[14]  
VSS  
O
O
CH8  
DDR0_DQS_DP[00]  
VSS  
CJ11  
CJ13  
CJ15  
CJ17  
CJ19  
CJ21  
CJ23  
CJ25  
CJ27  
CJ29  
CJ3  
O
DDR0_DQS_DP[11]  
DDR0_DQ[22]  
VSS  
I/O  
I/O  
O
O
O
VCCD_01  
I/O  
VCCD_01  
CG31  
CG33  
CG35  
CG37  
CG39  
CG41  
CG43  
CG5  
VCCD_01  
VSS  
VCCD_01  
VSS  
VCCD_01  
VSS  
VSS  
VSS  
VSS  
VSS  
CJ31  
CJ33  
CJ35  
CJ37  
CJ39  
CJ41  
CJ43  
CJ45  
CJ47  
CJ49  
DDR0_DQ[41]  
DDR0_DQS_DP[05]  
DDR0_DQ[43]  
DDR0_DQ[60]  
DDR0_DQS_DP[16]  
DDR0_DQ[62]  
VSS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VSS  
DDR0_DQ[15]  
VSS  
I/O  
CG53  
CG55  
CG7  
VTTA  
DDR0_DQS_DN[00]  
VSS  
I/O  
I/O  
I/O  
CG9  
CH10  
CH12  
CH14  
DDR0_DQ[30]  
VSS  
VSS  
VSS  
DDR0_DQS_DN[02]  
VTTA  
Datasheet  
105  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 23 of  
Table 8-2.  
Land List by Land  
Number (Sheet 24 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
CJ5  
DDR0_DQ[11]  
SSTL  
GND  
SSTL  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
SSTL  
SSTL  
CMOS  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
SSTL  
I/O  
I/O  
CL9  
DDR0_DQ[03]  
SSTL  
GND  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
SSTL  
GND  
GND  
CMOS  
GND  
GND  
GND  
GND  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
GND  
DC  
I/O  
I/O  
CJ51  
CJ7  
VSS  
CM10  
CM12  
CM14  
CM16  
CM18  
CM20  
CM22  
CM24  
CM26  
CM28  
CM30  
CM32  
CM34  
CM36  
CM38  
CM4  
VSS  
DDR0_DQ[06]  
VSS  
DDR0_DQ[17]  
VSS  
CJ9  
CK10  
CK12  
CK14  
CK16  
CK20  
CK22  
CK24  
CK26  
CK28  
CK30  
CK32  
CK34  
CK36  
CK38  
CK4  
VSS  
DDR0_DQ[19]  
DDR0_CKE[1]  
DDR0_BA[2]  
DDR0_MA[07]  
DDR0_MA[04]  
DDR0_MA_PAR  
DDR0_BA[0]  
VSS  
I/O  
O
DDR0_DQ[16]  
DDR0_DQS_DP[02]  
DDR0_DQ[18]  
DDR0_MA[12]  
DDR0_MA[08]  
DDR0_MA[03]  
DDR0_MA[10]  
DDR0_CS_N[9]  
DDR0_DQ[44]  
DDR0_DQS_DP[14]  
DDR0_DQ[46]  
VSS  
I/O  
I/O  
I/O  
O
O
O
O
O
O
O
O
O
O
VSS  
I/O  
I/O  
I/O  
VSS  
VSS  
VSS  
DDR1_DQ[04]  
VSS  
I/O  
I
DDR0_DQ[57]  
VSS  
I/O  
CM40  
CM42  
CM44  
CM6  
VSS  
CK40  
CK42  
CK44  
CK6  
DDR0_DQS_DP[07]  
DDR0_DQ[59]  
RESET_N  
I/O  
I/O  
I
BCLK0_DN  
VSS  
CM8  
VSS  
VSS  
CN11  
CN13  
CN15  
CN17  
CN19  
CN21  
CN23  
CN25  
CN27  
CN29  
CN3  
VSS  
CK8  
DDR0_DQ[02]  
DDR0_DQ[21]  
DDR0_DQS_DN[11]  
DDR0_DQ[23]  
VSS  
I/O  
I/O  
I/O  
I/O  
VSS  
CL11  
CL13  
CL15  
CL17  
CL19  
CL21  
CL23  
CL25  
CL27  
CL29  
CL3  
VSS  
VSS  
DDR0_MA[15]  
DDR0_MA[09]  
DDR0_MA[06]  
DDR0_CS_N[0]  
DDR0_BA[1]  
DDR0_WE_N  
VSS  
O
O
O
O
O
O
DDR0_CKE[0]  
DDR0_MA[11]  
DDR0_MA[05]  
DDR0_MA[00]  
DDR0_CS_N[8]  
DDR0_CAS_N  
DDR1_DQ[05]  
DDR0_DQ[40]  
DDR0_DQS_DN[05]  
DDR0_DQ[42]  
DDR0_DQ[61]  
DDR0_DQS_DN[16]  
DDR0_DQ[63]  
VSS  
O
O
O
O
O
O
CN31  
CN33  
CN35  
CN37  
CN39  
CN41  
VSS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VSS  
CL31  
CL33  
CL35  
CL37  
CL39  
CL41  
CL43  
CL5  
VSS  
VSS  
VSS  
DDR_VREFDQTX_C0  
1
O
I
CN43  
CN5  
BCLK0_DP  
VSS  
CMOS  
GND  
GND  
GND  
CN53  
CN55  
VSS  
VSS  
VSS  
CL7  
DDR0_DQ[07]  
I/O  
106  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 25 of  
Table 8-2.  
Land List by Land  
Number (Sheet 26 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
CN57  
CN7  
VSS  
GND  
GND  
GND  
SSTL  
GND  
SSTL  
GND  
SSTL  
SSTL  
PWR  
PWR  
PWR  
PWR  
PWR  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
CR33  
CR35  
CR37  
CR39  
CR41  
CR43  
CR45  
CR47  
CR49  
CR5  
DDR1_DQ[39]  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
CMOS  
PWR  
GND  
GND  
GND  
PWR  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
CMOS  
SSTL  
SSTL  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
VSS  
VSS  
CN9  
VSS  
DDR1_DQ[48]  
DDR1_DQS_DN[06]  
DDR1_DQ[50]  
SVIDALERT_N  
VTTA  
I/O  
I/O  
I/O  
I
CP10  
CP12  
CP14  
CP16  
CP18  
CP2  
DDR1_DQ[19]  
VSS  
I/O  
I/O  
DDR1_DQS_DN[12]  
VSS  
DDR0_CKE[3]  
DDR1_DQ[01]  
VCCD_01  
O
VSS  
I/O  
VSS  
CP20  
CP22  
CP24  
CP26  
CP28  
CP30  
CP32  
CP34  
CP36  
CP38  
CP4  
VSS  
VCCD_01  
CR51  
CR7  
VTTA  
VCCD_01  
DDR1_DQ[16]  
VSS  
I/O  
VCCD_01  
CR9  
VCCD_01  
CT10  
CT12  
CT14  
CT16  
CT18  
CT2  
DDR1_DQ[18]  
DDR1_DQ[28]  
DDR1_DQS_DP[12]  
DDR1_DQ[30]  
DDR1_CKE[5]  
DDR1_DQS_DP[09]  
DDR1_CKE[0]  
DDR1_ODT[0]  
DDR1_CS_N[5]  
DDR1_CS_N[7]  
VSS  
I/O  
I/O  
I/O  
I/O  
O
DDR1_DQ[33]  
DDR1_DQS_DP[04]  
DDR1_DQ[35]  
VSS  
I/O  
I/O  
I/O  
DDR1_DQS_DP[15]  
DDR1_DQ[00]  
VSS  
I/O  
I/O  
I/O  
O
CT20  
CT22  
CT24  
CT26  
CT28  
CT30  
CT32  
CT34  
CT36  
CT38  
CT4  
CP40  
CP42  
CP44  
CP46  
CP48  
CP50  
CP52  
CP54  
CP56  
CP6  
O
VSS  
O
VSS  
O
VSS  
VSS  
DDR1_DQ[32]  
DDR1_DQS_DN[04]  
DDR1_DQ[34]  
DDR1_DQ[52]  
DDR1_DQS_DN[15]  
DDR1_DQS_DN[00]  
DDR1_DQ[54]  
VSS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VSS  
VSS  
RSVD  
VSS  
GND  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
DDR1_DQ[20]  
DDR1_DQS_DP[11]  
DDR1_DQS_DN[09]  
VSS  
I/O  
I/O  
I/O  
CP8  
CT40  
CT42  
CT54  
CT6  
CR1  
CR11  
CR13  
CR15  
CR17  
CR19  
CR21  
CR23  
CR25  
CR27  
CR29  
CR3  
TRST_N  
I
DDR1_DQ[24]  
DDR1_DQS_DN[03]  
DDR1_DQ[26]  
DDR1_CKE[4]  
DDR1_CS_N[8]  
DDR1_CS_N[2]  
DDR0_MA[01]  
DDR1_CS_N[3]  
DDR1_DQ[37]  
DDR1_DQS_DP[00]  
DDR1_DQS_DN[13]  
I/O  
I/O  
I/O  
O
DDR1_DQ[21]  
DDR1_DQS_DN[11]  
VSS  
I/O  
I/O  
CT8  
CU1  
CU11  
CU13  
CU15  
CU17  
CU19  
CU21  
CU23  
CU25  
VSS  
O
DDR1_DQ[25]  
DDR1_DQS_DP[03]  
DDR1_DQ[27]  
DDR1_CKE[1]  
DDR1_PAR_ERR_N  
DDR1_CS_N[1]  
DDR1_CS_N[4]  
I/O  
I/O  
I/O  
O
O
O
O
I/O  
I/O  
I/O  
I
O
CR31  
O
Datasheet  
107  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 27 of  
Table 8-2.  
Land List by Land  
Number (Sheet 28 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
CU27  
CU29  
CU3  
DDR1_ODT[4]  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
SSTL  
GND  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
SSTL  
O
CW25 VCCD_01  
CW27 VCCD_01  
CW29 VSS  
PWR  
PWR  
DDR1_DQ[36]  
VSS  
I/O  
GND  
CU31  
CU33  
CU35  
CU37  
CU39  
CU41  
CU5  
DDR1_DQS_DP[13]  
DDR1_DQ[38]  
VSS  
I/O  
I/O  
CW3  
DDR1_DQ[07]  
SSTL  
GND  
I/O  
CW31 VSS  
CW33 VSS  
CW35 VSS  
CW37 VSS  
CW39 VSS  
CW41 DDR_SDA_C01  
GND  
DDR1_DQ[49]  
DDR1_DQS_DP[06]  
DDR1_DQ[51]  
VSS  
I/O  
I/O  
I/O  
GND  
GND  
GND  
ODCMOS  
GND  
I/O  
CU7  
DDR1_DQ[17]  
DDR1_DQS_DP[02]  
DDR1_DQ[23]  
DDR1_DQ[29]  
VSS  
I/O  
I/O  
I/O  
I/O  
CW5  
VSS  
CU9  
CW51 VSS  
CW53 VSS  
CW55 VSS  
CW57 VSS  
GND  
CV10  
CV12  
CV14  
CV16  
CV18  
CV2  
GND  
GND  
GND  
DDR1_DQ[31]  
VSS  
I/O  
CW7  
CW9  
CY10  
CY12  
CY14  
CY16  
CY18  
CY2  
VSS  
GND  
DDR1_DQ[22]  
VSS  
SSTL  
GND  
I/O  
DDR1_DQ[06]  
DDR1_CLK_DN[0]  
DDR1_CLK_DN[1]  
DDR1_CLK_DP[2]  
DDR1_ODT[3]  
DDR1_WE_N  
VSS  
I/O  
O
CV20  
CV22  
CV24  
CV26  
CV28  
CV30  
CV32  
CV34  
CV36  
CV38  
CV4  
VSS  
GND  
O
DDR1_DQS_DP[17]  
VSS  
SSTL  
GND  
I/O  
O
O
O
DDR1_CKE[2]  
VSS  
SSTL  
GND  
O
CY20  
CY22  
CY24  
CY26  
CY28  
CY30  
CY32  
CY34  
CY36  
CY38  
CY4  
DDR1_CLK_DP[0]  
DDR1_CLK_DP[1]  
DDR1_CLK_DN[2]  
DDR1_ODT[2]  
DDR1_ODT[5]  
DDR1_CAS_N  
DDR1_DQ[45]  
DDR1_DQS_DN[05]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
O
O
VSS  
VSS  
O
DDR1_DQ[53]  
VSS  
I/O  
O
O
DDR1_DQ[02]  
DDR1_DQ[55]  
VSS  
I/O  
I/O  
O
CV40  
CV42  
CV54  
CV58  
CV6  
I/O  
I/O  
VSS  
VSS  
DDR1_DQS_DN[16]  
DDR1_DQ[03]  
VSS  
SSTL  
SSTL  
GND  
I/O  
I/O  
VSS  
CV8  
DDR1_DQS_DN[02]  
TEST1  
I/O  
O
CY40  
CY42  
CY44  
CY46  
CY48  
CY50  
CY56  
CY58  
CY6  
CW1  
DDR_SCL_C01  
VSS  
ODCMOS  
GND  
I/O  
CW11 VSS  
CW13 VSS  
CW15 VSS  
GND  
GND  
GND  
RSVD  
RSVD  
CW17 DRAM_PWR_OK_C0 CMOS1.5  
I
VSS  
GND  
1
v
RSVD  
CW19 VCCD_01  
CW21 VCCD_01  
CW23 VCCD_01  
PWR  
PWR  
PWR  
RSVD  
DDR1_DQ[12]  
VSS  
SSTL  
GND  
I/O  
CY8  
108  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 29 of  
Table 8-2.  
Land List by Land  
Number (Sheet 30 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
D10  
D12  
DDR3_DQS_DP[04]  
DDR3_DQ[32]  
DDR3_ODT[4]  
DDR3_CS_N[8]  
DDR3_MA[10]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
GND  
SSTL  
I/O  
I/O  
O
DA49  
DA5  
VTTA  
PWR  
GND  
VSS  
D14  
DA51  
DA55  
DA57  
DA7  
VSS  
GND  
D16  
O
SAFE_MODE_BOOT  
RSVD  
CMOS  
I
D18  
O
D2  
DDR1_DQ[08]  
VSS  
SSTL  
GND  
SSTL  
GND  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
SSTL  
I/O  
I/O  
D20  
DDR3_MA[04]  
DDR3_MA[08]  
DDR3_MA[14]  
VSS  
O
O
O
DA9  
D22  
DB10  
DB12  
DB14  
DB18  
DB2  
DDR1_DQ[14]  
VSS  
D24  
D26  
DDR1_DQS_DN[17]  
DDR1_MA[14]  
VSS  
I/O  
O
D32  
DDR3_DQ[18]  
DDR3_DQS_DP[11]  
VSS  
I/O  
I/O  
D34  
D36  
DB20  
DB22  
DB24  
DB26  
DB28  
DB30  
DB32  
DB34  
DB36  
DB38  
DB4  
DDR1_MA[08]  
DDR1_MA[04]  
DDR1_CS_N[0]  
DDR1_BA[0]  
DDR1_RAS_N  
DDR1_MA[13]  
VSS  
O
O
O
O
O
O
D38  
DDR3_DQS_DP[00]  
TEST3  
I/O  
O
D4  
D40  
DDR3_DQ[05]  
DMI_TX_DN[0]  
DMI_TX_DN[2]  
RSVD  
SSTL  
PCIEX  
PCIEX  
I/O  
O
D42  
D44  
O
D46  
D48  
DMI_RX_DN[1]  
DMI_RX_DN[3]  
PE1A_RX_DP[1]  
PE1A_RX_DP[2]  
RSVD  
PCIEX  
PCIEX  
I
I
I
I
DDR1_DQS_DP[05]  
VSS  
I/O  
D50  
D52  
PCIEX3  
PCIEX3  
DDR1_DQS_DP[16]  
TEST0  
I/O  
O
D54  
D56  
DB40  
DB56  
DB58  
DB6  
DDR1_DQ[59]  
RSVD  
SSTL  
I/O  
D6  
DDR3_DQ[53]  
VSS  
SSTL  
GND  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
GND  
I/O  
D8  
VSS  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
DA11  
DA17  
DA19  
DA21  
DA23  
DA25  
DA27  
DA29  
DA3  
DA31  
DA33  
DA35  
DA37  
DA39  
DA41  
DA43  
DA45  
DA47  
VSS  
DDR1_DQ[13]  
DDR1_DQS_DN[10]  
DDR1_DQ[10]  
DDR1_DQS_DP[08]  
DDR1_MA[15]  
DDR1_MA[12]  
DDR1_CLK_DP[3]  
DDR1_MA[00]  
DDR1_BA[1]  
VSS  
I/O  
I/O  
I/O  
I/O  
O
DDR1_CKE[3]  
DDR1_MA[09]  
DDR1_CLK_DN[3]  
DDR1_MA[03]  
DDR1_ODT[1]  
DDR1_CS_N[9]  
DDR1_CS_N[6]  
VSS  
O
O
O
O
O
O
O
DB8  
DC11  
DC15  
DC17  
DC19  
DC21  
DC23  
DC25  
DC3  
O
O
O
O
DDR1_DQ[44]  
DDR1_DQ[40]  
DDR1_DQ[43]  
DDR1_DQ[60]  
DDR1_DQ[62]  
VSS  
I/O  
I/O  
I/O  
I/O  
I/O  
DC33  
DC35  
DC37  
DC39  
DC41  
DC5  
DDR1_DQS_DP[14]  
DDR1_DQ[42]  
DDR1_DQ[61]  
DDR1_DQS_DP[07]  
VSS  
I/O  
I/O  
I/O  
I/O  
VSS  
VSS  
VSS  
DC55  
DC7  
RSVD  
VSS  
DDR1_DQ[09]  
SSTL  
I/O  
Datasheet  
109  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 31 of  
Table 8-2.  
Land List by Land  
Number (Sheet 32 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
DC9  
DD10  
DD12  
DD14  
DD18  
DD20  
DD22  
DD24  
DD26  
DD32  
DD34  
DD36  
DD38  
DD40  
DD54  
DD6  
DDR1_DQS_DN[01]  
SSTL  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
SSTL  
GND  
GND  
GND  
SSTL  
I/O  
DF42  
DF44  
DF46  
DF48  
DF50  
DF52  
DF8  
E1  
VSS  
GND  
GND  
VSS  
VSS  
VSS  
VSS  
GND  
VSS  
VSS  
GND  
VCCD_01  
VSS  
GND  
VCCD_01  
VSS  
GND  
VCCD_01  
VSS  
GND  
VCCD_01  
VSS  
GND  
VCCD_01  
E11  
E13  
E15  
E17  
E19  
E21  
E23  
E27  
E29  
E3  
DDR3_DQS_DP[13]  
MEM_HOT_C23_N  
DDR3_CS_N[7]  
DDR3_ODT[2]  
DDR3_BA[1]  
DDR3_MA[01]  
DDR3_MA[12]  
DDR3_DQS_DP[08]  
VSS  
SSTL  
ODCMOS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
O
DDR1_DQ[41]  
VSS  
I/O  
I/O  
VSS  
O
VSS  
O
DDR1_DQ[58]  
RSVD  
O
O
VSS  
GND  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
I/O  
DD8  
DDR1_DQS_DP[10]  
DDR1_DQ[11]  
DDR1_DQS_DN[08]  
VSS  
I/O  
I/O  
I/O  
DE11  
DE15  
DE17  
DE19  
DE21  
DE23  
DE25  
DE33  
DE35  
DE37  
DE39  
DE41  
DE53  
DE55  
DE7  
VSS  
GND  
E31  
E33  
E35  
E37  
E39  
E41  
E43  
E45  
E47  
E49  
E5  
VSS  
GND  
DDR3_DQS_DP[02]  
DDR3_DQ[20]  
DDR3_DQ[03]  
DDR3_DQS_DP[09]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
I/O  
DDR1_MA[11]  
DDR1_MA[06]  
DDR1_MA[01]  
DDR1_MA_PAR  
DDR1_DQS_DN[14]  
DDR1_DQ[47]  
DDR1_DQ[56]  
DDR1_DQS_DN[07]  
VSS  
O
O
O
O
I/O  
I/O  
I/O  
I/O  
DMI_TX_DN[1]  
DMI_TX_DN[3]  
DMI_RX_DN[0]  
DMI_RX_DN[2]  
VSS  
PCIEX  
PCIEX  
PCIEX  
PCIEX  
GND  
O
O
I
I
VSS  
E51  
E53  
E55  
E57  
E7  
PE1A_RX_DN[0]  
RSVD  
PCIEX3  
I
I
RSVD  
VSS  
GND  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
PE1A_RX_DP[3]  
RSVD  
PCIEX3  
DE9  
DDR1_DQS_DP[01]  
DDR1_DQ[15]  
VSS  
I/O  
I/O  
DF10  
DF12  
DF18  
DF20  
DF22  
DF24  
DF26  
DF34  
DF36  
DF38  
DF40  
DDR3_DQ[48]  
DDR3_DQ[35]  
DDR3_DQ[38]  
DDR3_DQ[36]  
DDR3_CS_N[2]  
DDR3_CS_N[6]  
DDR3_ODT[1]  
TEST2  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I/O  
I/O  
O
E9  
DDR1_BA[2]  
DDR1_MA[07]  
DDR1_MA[05]  
DDR1_MA[02]  
DDR1_MA[10]  
DDR1_DQ[46]  
VSS  
O
O
F10  
F12  
F14  
F16  
F18  
F2  
O
O
O
O
O
I/O  
O
F20  
F22  
F24  
DDR3_MA[02]  
DDR3_MA[06]  
DDR3_MA[15]  
SSTL  
SSTL  
SSTL  
O
DDR1_DQ[57]  
DDR1_DQ[63]  
I/O  
I/O  
O
O
110  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 33 of  
Table 8-2.  
Land List by Land  
Number (Sheet 34 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
F28  
F32  
F34  
F36  
F38  
F4  
DDR3_DQS_DP[17]  
DDR3_DQ[19]  
DDR3_DQ[17]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
SSTL  
GND  
GND  
I/O  
I/O  
I/O  
G7  
G9  
DDR3_DQS_DP[15]  
SSTL  
GND  
I/O  
VSS  
H10  
H12  
H14  
H16  
H18  
H2  
VSS  
GND  
VSS  
GND  
DDR3_DQ[06]  
DDR3_DQ[60]  
DDR3_DQ[04]  
VSS  
I/O  
I/O  
I/O  
VSS  
GND  
VCCD_23  
VCCD_23  
DDR3_DQ[57]  
VCCD_23  
VCCD_23  
VCCD_23  
DDR3_DQS_DN[17]  
VSS  
PWR  
F40  
F42  
F44  
F46  
F48  
F50  
F52  
F54  
F56  
F58  
F6  
PWR  
SSTL  
PWR  
I/O  
I/O  
VSS  
H20  
H22  
H24  
H28  
H32  
H34  
H36  
H38  
H4  
RSVD  
PWR  
VSS  
GND  
GND  
PWR  
VSS  
SSTL  
GND  
PE1A_RX_DN[1]  
PE1A_RX_DN[2]  
RSVD  
PCIEX3  
PCIEX3  
I
I
VSS  
GND  
DDR3_DQ[15]  
VSS  
SSTL  
GND  
I/O  
I/O  
RSVD  
DDR3_DQ[49]  
VSS  
SSTL  
GND  
GND  
SSTL  
PWR  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
SSTL  
GND  
SSTL  
GND  
GND  
SSTL  
GND  
PWR  
GND  
GND  
PWR  
GND  
GND  
GND  
PCIEX3  
GND  
I/O  
I/O  
DDR3_DQ[61]  
VSS  
SSTL  
GND  
F8  
H40  
H42  
H44  
H46  
H48  
H50  
H52  
H54  
H56  
H58  
H6  
G1  
VSS  
PE1A_TX_DP[0]  
PE1A_TX_DP[2]  
PE1B_TX_DP[4]  
PE1B_TX_DP[6]  
PE3A_TX_DP[0]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
O
O
G11  
G13  
G15  
G17  
G19  
G21  
G23  
G25  
G27  
G3  
DDR3_DQS_DN[13]  
VCCD_23  
DDR3_CS_N[3]  
DDR3_CS_N[5]  
DDR3_CS_N[0]  
DDR3_PAR_ERR_N  
DDR3_MA[09]  
VSS  
O
O
O
I
VSS  
GND  
O
RSVD  
RSVD  
DDR3_DQS_DN[08]  
DDR3_DQ[56]  
VSS  
I/O  
I/O  
DDR3_DQS_DN[15]  
VSS  
SSTL  
GND  
DC  
I/O  
I
H8  
G31  
G33  
G35  
G37  
G39  
G41  
G43  
G45  
G47  
G49  
G5  
J1  
DDR_VREFDQRX_C2  
3
DDR3_DQS_DN[02]  
VSS  
I/O  
I/O  
J11  
J13  
J15  
J17  
J19  
J21  
J23  
J25  
J27  
J3  
VSS  
GND  
DDR3_DQ[40]  
RSVD  
SSTL  
I/O  
VSS  
DDR3_DQS_DN[09]  
VSS  
DDR3_ODT[3]  
DDR3_CS_N[1]  
DDR3_CLK_DN[1]  
DDR3_CLK_DN[0]  
DDR3_CKE[2]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
GND  
SSTL  
O
O
O
O
O
VSA  
VSS  
VSS  
VSA  
VSS  
DDR3_DQS_DP[16]  
VSS  
I/O  
I/O  
G51  
G53  
G55  
G57  
VSS  
J31  
J33  
J35  
VSS  
VSS  
PE1A_RX_DN[3]  
VSS  
I
DDR3_DQ[11]  
Datasheet  
111  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 35 of  
Table 8-2.  
Land List by Land  
Number (Sheet 36 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
J37  
J39  
J41  
J43  
J45  
J47  
J49  
J5  
DDR3_DQS_DP[01]  
SSTL  
GND  
I/O  
L11  
L13  
L15  
DDR3_DQS_DN[05]  
DDR3_DQ[41]  
SSTL  
SSTL  
I/O  
I/O  
I
VSS  
VSS  
GND  
DRAM_PWR_OK_C2 CMOS1.5  
3
v
PE1A_TX_DP[1]  
PE1A_TX_DP[3]  
PE1B_TX_DP[5]  
PE1B_TX_DP[7]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
O
L17  
L19  
L21  
L23  
L25  
L27  
L29  
L3  
DDR2_BA[1]  
DDR3_ODT[0]  
DDR3_CLK_DP[1]  
DDR3_CLK_DP[0]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
O
O
O
O
J51  
J53  
J55  
J57  
J7  
PE3A_TX_DP[1]  
PE1B_RX_DP[4]  
VSS  
PCIEX3  
PCIEX3  
GND  
O
I
DDR3_DQ[27]  
VSS  
SSTL  
GND  
I/O  
DDR3_DQS_DN[07]  
DDR3_DQ[25]  
DDR3_DQ[28]  
DDR3_DQ[10]  
DDR3_DQS_DN[01]  
DDR3_DQ[09]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PE1B_RX_DP[6]  
DDR3_DQS_DN[06]  
DDR3_DQ[42]  
DDR3_DQ[46]  
DDR3_DQS_DP[14]  
DDR3_DQ[44]  
DDR3_CS_N[9]  
DDR3_CS_N[4]  
VSS  
PCIEX3  
SSTL  
I
L31  
L33  
L35  
L37  
L39  
L41  
L43  
L45  
L47  
L49  
L5  
I/O  
I/O  
I/O  
I/O  
I/O  
O
J9  
SSTL  
K10  
K12  
K14  
K16  
K18  
K2  
SSTL  
SSTL  
SSTL  
SSTL  
PE1A_TX_DN[1]  
PE1A_TX_DN[3]  
PE1B_TX_DN[5]  
PE1B_TX_DN[7]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
O
SSTL  
O
GND  
K20  
K22  
K24  
K26  
K28  
K30  
K32  
K34  
K36  
K38  
K4  
DDR3_CLK_DP[2]  
DDR3_CLK_DN[3]  
DDR3_CKE[0]  
VSS  
SSTL  
O
O
O
SSTL  
SSTL  
L51  
L53  
L55  
L57  
L7  
PE3A_TX_DN[1]  
PE1B_RX_DN[4]  
PE2A_RX_DP[0]  
PE1B_RX_DN[6]  
DDR3_DQ[54]  
DDR3_DQ[43]  
DDR3_DQ[47]  
DDR3_DQS_DN[14]  
DDR3_DQ[45]  
DDR3_ODT[5]  
DDR2_MA_PAR  
DDR3_DQ[63]  
DDR3_CLK_DN[2]  
DDR3_CLK_DP[3]  
DDR3_CKE[1]  
DDR3_DQ[31]  
DDR3_DQ[26]  
DDR3_DQS_DN[12]  
DDR3_DQ[24]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
O
I
GND  
VSS  
GND  
I
VSS  
GND  
I
DDR3_DQ[29]  
VSS  
SSTL  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
GND  
L9  
DDR3_DQ[14]  
DDR3_DQS_DN[10]  
DDR3_DQS_DN[16]  
DDR3_DQ[13]  
PE1A_TX_DN[0]  
PE1A_TX_DN[2]  
PE1B_TX_DN[4]  
PE1B_TX_DN[6]  
PE3A_TX_DN[0]  
PMSYNC  
SSTL  
I/O  
I/O  
I/O  
I/O  
O
M10  
M12  
M14  
M16  
M18  
M2  
SSTL  
SSTL  
K40  
K42  
K44  
K46  
K48  
K50  
K52  
K54  
K56  
K58  
K6  
SSTL  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
CMOS  
PCIEX3  
PCIEX3  
O
O
I/O  
O
O
M20  
M22  
M24  
M26  
M28  
M30  
M32  
M34  
M36  
O
O
O
O
I
I/O  
I/O  
I/O  
I/O  
PE1B_RX_DP[5]  
PE1B_RX_DP[7]  
RSVD  
I
I
DDR3_DQS_DP[06]  
VSS  
SSTL  
GND  
SSTL  
I/O  
I/O  
K8  
VSS  
GND  
L1  
DDR3_DQ[62]  
112  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 37 of  
Table 8-2.  
Land List by Land  
Number (Sheet 38 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
M38  
M4  
DDR3_DQS_DP[10]  
DDR3_DQS_DP[07]  
DDR3_DQ[12]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
I/O  
I/O  
I/O  
P18  
P20  
P22  
P24  
P26  
P28  
P30  
P32  
P34  
P36  
P38  
P4  
DDR2_CS_N[5]  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
GND  
SSTL  
SSTL  
GND  
SSTL  
GND  
DC  
O
O
O
O
DDR2_MA[04]  
DDR2_MA[07]  
DDR2_BA[2]  
VSS  
M40  
M42  
M44  
M46  
M48  
M50  
M52  
M54  
M56  
M6  
VSS  
VSS  
DDR3_DQS_DN[03]  
VSS  
I/O  
RSVD  
VSS  
GND  
GND  
PCIEX3  
PCIEX3  
SSTL  
GND  
SSTL  
GND  
PWR  
PWR  
PWR  
PWR  
PWR  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
SSTL  
GND  
GND  
PWR  
GND  
GND  
GND  
PWR  
GND  
PCIEX3  
SSTL  
GND  
GND  
GND  
GND  
SSTL  
VSS  
VSS  
DDR2_DQ[21]  
DDR2_DQ[02]  
VSS  
I/O  
I/O  
PE1B_RX_DN[5]  
PE1B_RX_DN[7]  
DDR3_DQ[55]  
VSS  
I
I
I/O  
DDR3_DQ[59]  
VSS  
I/O  
O
M8  
P40  
P42  
N11  
N13  
N15  
N17  
N19  
N21  
N23  
N25  
N27  
N29  
N3  
DDR3_DQS_DP[05]  
VSS  
I/O  
DDR_VREFDQTX_C2  
3
P44  
P46  
P48  
P50  
P52  
P54  
P56  
P6  
PE3D_TX_DN[15]  
PE3C_TX_DP[8]  
PE3A_TX_DP[3]  
PE3B_TX_DP[6]  
PE3B_TX_DP[4]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
O
O
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
VCCD_23  
DDR3_CKE[3]  
DDR3_DQ[30]  
DDR3_DQS_DP[03]  
DDR3_DQ[58]  
DDR3_DQS_DP[12]  
VSS  
O
VSS  
GND  
I/O  
I/O  
I/O  
I/O  
DDR3_DQ[51]  
VSS  
SSTL  
I/O  
P8  
GND  
R11  
R13  
R15  
R17  
R19  
R21  
R23  
R25  
R27  
R29  
R3  
VSS  
GND  
N31  
N33  
N35  
N37  
N39  
N41  
N43  
N45  
N47  
N49  
N5  
DDR2_DQ[48]  
DDR2_MA[13]  
DDR2_BA[0]  
DDR2_MA[01]  
DDR2_MA[06]  
DDR2_MA[09]  
DDR3_CKE[4]  
DDR3_CKE[5]  
VSS  
SSTL  
I/O  
O
SSTL  
VSS  
SSTL  
O
VSS  
SSTL  
O
DDR3_DQ[08]  
VSS  
I/O  
SSTL  
O
SSTL  
O
VSS  
SSTL  
O
VSA  
SSTL  
O
VSS  
GND  
VSS  
VSS  
GND  
VSS  
R31  
R33  
R35  
R37  
R39  
R41  
R43  
R45  
R47  
VSS  
GND  
N51  
N53  
N55  
N7  
VSA  
DDR2_DQ[17]  
VSS  
SSTL  
I/O  
I/O  
VSS  
GND  
PE2A_RX_DN[0]  
DDR3_DQ[50]  
VSS  
I
DDR2_DQ[06]  
VSS  
SSTL  
I/O  
GND  
N9  
DDR2_DQ[04]  
DDR_SDA_C23  
PE3C_TX_DP[10]  
PE3A_TX_DP[2]  
SSTL  
I/O  
I/O  
O
P10  
P12  
P14  
P16  
VSS  
ODCMOS  
PCIEX3  
PCIEX3  
VSS  
VSS  
O
DDR2_WE_N  
O
Datasheet  
113  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 39 of  
Table 8-2.  
Land List by Land  
Number (Sheet 40 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
R49  
R5  
PE3B_TX_DP[7]  
PCIEX3  
GND  
O
U3  
DDR2_DQ[60]  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
VSS  
U31  
U33  
U35  
U37  
U39  
U41  
U43  
U45  
U47  
U49  
U5  
DDR2_DQS_DP[02]  
DDR2_DQ[16]  
VSS  
R51  
R53  
R55  
R7  
PE3B_TX_DP[5]  
PRDY_N  
PCIEX3  
CMOS  
GND  
O
O
VSS  
DDR2_DQ[07]  
DDR2_DQS_DP[09]  
DDR2_DQ[05]  
DDR_SCL_C23  
PE3C_TX_DN[10]  
PE3A_TX_DN[2]  
PE3B_TX_DN[7]  
VSS  
SSTL  
SSTL  
SSTL  
ODCMOS  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
I/O  
I/O  
I/O  
I/O  
O
VSS  
GND  
R9  
DDR2_DQ[54]  
DDR2_DQ[50]  
DDR2_DQS_DP[15]  
DDR2_DQ[52]  
DDR2_CAS_N  
DDR2_MA[10]  
DDR2_MA[03]  
DDR2_MA[08]  
DDR2_MA[12]  
DDR2_CKE[1]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
I/O  
O
T10  
T12  
T14  
T16  
T18  
T20  
T22  
T24  
T26  
T28  
T30  
T32  
T34  
T36  
T38  
T4  
O
O
O
O
U51  
U53  
U55  
U7  
PE3B_TX_DN[5]  
PREQ_N  
PCIEX3  
CMOS  
PCIEX3  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
PWR  
O
O
I/O  
I
O
PE2A_RX_DP[3]  
DDR2_DQ[44]  
DDR2_DQ[55]  
DDR2_DQ[51]  
DDR2_DQS_DN[15]  
DDR2_DQ[53]  
VCCD_23  
O
I/O  
I/O  
I/O  
I/O  
I/O  
U9  
DDR2_DQ[23]  
DDR2_DQS_DN[11]  
DDR2_DQ[20]  
DDR2_DQ[03]  
DDR2_DQS_DN[00]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
V10  
V12  
V14  
V16  
V18  
V20  
V22  
V24  
V26  
V28  
V30  
V32  
V34  
V36  
V38  
V4  
VCCD_23  
PWR  
VCCD_23  
PWR  
T40  
T42  
T44  
T46  
T48  
T50  
T52  
T54  
T56  
T6  
DDR2_DQ[00]  
VSS  
SSTL  
GND  
I/O  
VCCD_23  
PWR  
VCCD_23  
PWR  
PE3D_TX_DP[15]  
PE3C_TX_DN[8]  
PE3A_TX_DN[3]  
PE3B_TX_DN[6]  
PE3B_TX_DN[4]  
PE2A_RX_DP[1]  
PE2A_RX_DP[2]  
VSS  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
PCIEX3  
GND  
O
O
O
O
O
I
VSS  
GND  
VSS  
GND  
DDR2_DQ[22]  
DDR2_DQS_DP[11]  
VSS  
SSTL  
SSTL  
GND  
I/O  
I/O  
VSS  
GND  
I
DDR2_DQS_DP[00]  
DDR2_DQ[61]  
DDR2_DQ[01]  
VSS  
SSTL  
SSTL  
SSTL  
GND  
I/O  
I/O  
I/O  
T8  
VSS  
GND  
V40  
V42  
V44  
V46  
V48  
V50  
V52  
V54  
V56  
V6  
U11  
U13  
U15  
U17  
U19  
U21  
U23  
U25  
U27  
U29  
DDR2_DQS_DN[06]  
DDR2_DQ[49]  
DDR23_RCOMP[0]  
DDR2_RAS_N  
DDR2_MA[02]  
DDR2_MA[05]  
DDR2_MA[11]  
DDR2_MA[15]  
DDR2_CKE[2]  
DDR2_DQ[19]  
SSTL  
SSTL  
Analog  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
I/O  
I/O  
I
VSS  
GND  
VSS  
GND  
O
VSS  
GND  
O
VSS  
GND  
O
TXT_PLTEN  
PE2A_RX_DN[1]  
PE2A_RX_DN[2]  
DDR2_DQ[40]  
VSS  
CMOS  
PCIEX3  
PCIEX3  
SSTL  
GND  
I
I
O
O
I
O
I/O  
I/O  
V8  
114  
Datasheet  
Processor Land Listing  
Table 8-2.  
Land List by Land  
Number (Sheet 41 of  
Table 8-2.  
Land List by Land  
Number (Sheet 42 of  
Land  
No.  
Buffer  
Type  
Land  
No.  
Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
W11  
W13  
W15  
W17  
W19  
W21  
W23  
W25  
W29  
W3  
DDR2_DQS_DP[06]  
VSS  
SSTL  
GND  
I/O  
Y46  
Y48  
Y50  
Y52  
Y54  
Y56  
Y6  
PE3C_TX_DP[11]  
PCIEX3  
O
RSVD  
RSVD  
PE3B_RX_DP[4]  
PE3B_RX_DP[5]  
VTTA  
PCIEX3  
PCIEX3  
PWR  
I
I
DDR2_CS_N[8]  
DDR2_ODT[1]  
DDR2_CLK_DN[2]  
DDR2_CLK_DN[3]  
DDR2_MA[14]  
DDR2_DQ[18]  
DDR2_DQ[56]  
DDR2_DQS_DN[02]  
VSS  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
SSTL  
GND  
SSTL  
GND  
GND  
GND  
GND  
PWR  
GND  
GND  
GND  
PCIEX3  
SSTL  
GND  
GND  
GND  
Analog  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
GND  
GND  
GND  
SSTL  
GND  
GND  
SSTL  
GND  
GND  
PCIEX3  
O
O
O
VSS  
GND  
O
DDR2_DQ[41]  
DDR2_DQS_DP[14]  
SSTL  
I/O  
I/O  
O
Y8  
SSTL  
I/O  
I/O  
I/O  
W31  
W33  
W35  
W37  
W39  
W41  
W43  
W45  
W47  
W49  
W5  
§
DDR2_DQ[29]  
VSS  
I/O  
I/O  
DDR2_DQS_DN[09]  
VSS  
VSS  
VSS  
VSS  
VTTA  
VSS  
W51  
W53  
W55  
W7  
VSS  
VSS  
PE2A_RX_DN[3]  
DDR2_DQ[45]  
VSS  
I
I/O  
W9  
Y10  
Y12  
Y14  
Y16  
Y18  
Y20  
Y22  
Y24  
Y28  
Y30  
Y32  
Y34  
Y36  
Y38  
Y4  
VSS  
VSS  
DDR23_RCOMP[2]  
DDR2_CS_N[7]  
DDR2_ODT[3]  
DDR2_ODT[0]  
DDR2_CLK_DN[1]  
DDR2_CLK_DN[0]  
VSS  
I
O
O
O
O
O
VSS  
VSS  
DDR2_DQS_DP[12]  
VSS  
I/O  
I/O  
O
VSS  
DDR2_DQ[57]  
VSS  
Y40  
Y42  
Y44  
VSS  
PE3D_TX_DP[13]  
Datasheet  
115  
Package Mechanical Specifications  
9 Package Mechanical  
Specifications  
The processor is in a Flip-Chip Land Grid Array (FCLGA12) package that interfaces with  
the baseboard using an LGA2011-0 socket. The package consists of a processor  
mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to  
the package substrate and core and serves as the mating surface for processor  
component thermal solutions, such as a heatsink. Refer to the Processor Thermal  
Mechanical Specifications and Design Guidelines (see Related Documents section) for  
complete details on the LGA2011-0 socket.  
§
116  
Datasheet  
 
Boxed Processor Specifications  
10 Boxed Processor Specifications  
10.1  
Introduction  
Intel boxed processors are intended for system integrators who build systems from  
components available through distribution channels. The processors (LGA2011-0) are  
offered as Intel boxed processors; however, the thermal solutions is sold separately.  
Boxed processors do not include a thermal solution in the box. Intel offers boxed  
thermal solutions separately through the same distribution channels. Refer to the  
Processor Thermal Mechanical Specifications and Design Guidelines (see Related  
Documents section) for a description of Boxed Processor thermal solutions.  
10.2  
Boxed Processor Contents  
The Boxed processor and Boxed Thermal Solution contents are outlined below.  
Boxed Processor  
• Processor  
• Installation and warranty manual  
• Intel Inside Logo  
Boxed Thermal Solution  
• Thermal solution assembly  
• Thermal interface material (pre-applied)  
• Installation and warranty manual  
§
Datasheet  
117  
     

Intel 80960HD User Manual
Intel S845WD1 E User Manual
JVC AV 28E50SK AV 32E50SK User Manual
LG Electronics 44MK User Manual
LG Electronics LG Life Good Computer Monitor M197WA User Manual
LG Electronics LG Life Good CRT Television 30FZ4D User Manual
Philips 24CE3276 User Manual 1
Philips 29PT5515 User Manual
Philips 107561 User Manual
Philips ScanCard SC3132N User Manual