Intel 80C51FA User Manual

80C51FA/83C51FA  
EVENT-CONTROL CHMOS SINGLE-CHIP  
8-BIT MICROCONTROLLER  
Automotive  
Y
Y
Extended Automotive  
Temperature Range  
Programmable Serial Channel with:  
- Framing Error Detection  
- Automatic Address Recognition  
b
a
(
40 C to 125 C Ambient)  
§
§
Y
Y
Y
High Performance CHMOS Process  
TTL and CMOS Compatible Logic  
Levels  
Three 16-Bit Timer/Counters  
- Timer 2 is an Up/Down  
Timer/Counter  
Y
Y
Y
64K External Program Memory Space  
64K External Data Memory Space  
Y
Programmable Counter Array with:  
- High Speed Output  
- Compare/Capture  
- Pulse Width Modulator  
- Watchdog Timer Capabilities  
MCS 51 Microcontroller Fully  
É
Compatible Instruction Set  
Y
Power Saving Idle and Power Down  
Modes  
Y
Y
ONCE (On-Circuit Emulation) Mode  
Available in PLCC and PDIP Packages  
Y
Y
Y
Y
Y
8K On-Chip ROM  
256 Bytes of On-Chip Data RAM  
Boolean Processor  
Ý
(See Packaging Specification, Order 231369)  
Y
Available in 12 MHz and 16 MHz  
Versions  
32 Programmable I/O Lines  
7 Interrupt Sources  
MEMORY ORGANIZATION  
PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. In addition the  
device can address up to 64K of program memory external to the chip.  
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of  
external data memory.  
The Intel 80C51FA/83C51FA is a single-chip control oriented microcontroller which is fabricated on Intel's  
CHMOS III (83C51FA) ROM technology. For the remainder of this datasheet references to the ROMless  
(80C51FA) and ROM (83C51FA) versions will be denoted as 83C51FA. Being a member of the MCS 51  
É
microcontroller family, the 83C51FA uses the same powerful instruction set, has the same architecture, and is  
pin-for-pin compatible with the existing MCS 51 microcontroller products. The 83C51FA is an enhanced  
version of the 87C51. It's added features make it an even more powerful microcontroller for applications that  
require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as brake and  
traction control. It also has a more versatile serial channel that facilitates multi-processor communications.  
NOTICE:  
This datasheet contains information on products in full production. Specifications within this datasheet  
are subject to change without notice. Verify with your local Intel sales office that you have the latest  
datasheet before finalizing a design.  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
COPYRIGHT ©INTEL CORPORATION, 2004  
June 2004  
Order Number: 270501-008  
AUTOMOTIVE 80C51FA/83C51FA  
temperature range of 0 C to 70 C ambient. With the  
extended temperature range option, operational  
characteristics are guaranteed over the temperature  
°
°
80C51FA/83C51FA PRODUCT  
OPTIONS  
range of  
ambient. For the automo-  
-40 °C to + 85°C  
Intel’s extended and automotive temperature range  
products are designed to meet the needs of those  
applications whose operating requirements exceed  
commercial standards.  
tive temperature range option, operational charac-  
teristics are guaranteed over the temperature range  
of -40°C to +125°C ambient.  
As shown in Figure 2 temperature, burn-in, and  
package options are identified by a one- or two-letter  
prefix to the part number.  
With the commercial standard temperature range,  
operational characteristics are guaranteed over the  
x
x
x
270501–2  
Figure 2. MCS® 51 Microcontroller Product Family Nomenclature  
Table 1. Temperature Options  
Operating  
Temperature  
Classification  
Temperature  
Designation  
Burn-In  
Options  
Temperature  
C Ambient  
°
-
-
+
Extended  
T
L
40 to 85  
Standard  
Extended  
+
40 to 85  
-
-
+
Automotive  
A
B
40 to 125  
Standard  
Extended  
+
40 to 125  
3
AUTOMOTIVE 80C51FA/83C51FA  
PIN DESCRIPTIONS  
Port Pin  
Alternate Function  
V
: Supply voltage.  
CC  
P1.0  
T2 (External Count Input to Timer/  
Counter 2)  
V
: Circuit ground.  
SS  
P1.1  
T2EX (Timer/Counter 2 Capture/  
Reload Trigger and Direction Control)  
Port 0: Port 0 is an 8-bit, open drain, bidirectional  
I/O port. As an output port each pin can sink several  
LS TTL inputs. Port 0 pins that have 1's written to  
them float, and in that state can be used as high-im-  
pedance inputs.  
P1.2  
P1.3  
ECI (External Count Input to the PCA)  
CEX0 (External I/O for Compare/  
Capture Module 0)  
P1.4  
P1.5  
P1.6  
P1.7  
CEX1 (External I/O for Compare/  
Capture Module 1)  
Port 0 is also the multiplexed low-order address and  
data bus during accesses to external Program and  
Data Memory. In this application it uses strong inter-  
nal pullups when emitting1's, and can source and  
sink several LS TTL inputs.  
CEX2 (External I/O for Compare/  
Capture Module 2)  
CEX3 (External I/O for Compare/  
Capture Module 3)  
CEX4 (External I/O for Compare/  
Capture Module 4)  
Port 0 outputs the code bytes during program verifi-  
cation. External pullup resistors are required during  
program verification.  
Port 2: Port 2 is an 8-bit bidirectional I/O port with  
internal pullups. The Port 2 output buffers can drive  
LS TTL inputs. Port 2 pins that have 1's written to  
them are pulled high by the internal pullups, and in  
that state can be used as inputs. As inputs, Port 2  
pins that are externally pulled low will source current  
Port 1: Port 1 is an 8-bit bidirectional I/O port with  
internal pullups. The Port 1 output buffers can drive  
LS TTL inputs. Port 1 pins that have 1's written to  
them are pulled high by the internal pullups, and in  
that state can be used as inputs. As inputs, Port 1  
pins that are externally pulled low will source current  
(I , on the datasheet) because of the internal pull-  
IL  
ups.  
(I , on the datasheet) because of the internal pull-  
IL  
ups.  
Port 2 emits the high-order address byte during  
fetches from external Program Memory and during  
accesses to external Data Memory that use 16-bit  
addresses (MOVX @DPTR). In this application it  
uses strong internal pullups when emitting 1's. Dur-  
ing accesses to external Data Memory that use 8-bit  
In addition, Port 1 serves the functions of the follow-  
ing special features of the 83C51FA:  
Pin (PDIP)  
Pad (PLCC)  
270501±3  
270501±4  
**Do not connect reserved pins.  
Diagrams are for pin reference only. Package sizes are not to scale.  
Figure 3. Pin Connections  
4
AUTOMOTIVE 80C51FA/83C51FA  
addresses (MOVX @Ri), Port 2 emits the contents of  
the P2 Special Function Register.  
EA/V : External Access enable. EA must be  
PP  
strapped to V  
in order to enable the device to  
SS  
fetch code from external Program Memory locations  
0000H to 0FFFFH. Note, however, that if either of  
the Program Lock bits are programmed, EA will be  
internally latched on reset.  
Port 3: Port 3 is an 8-bit bidirectional I/O port with  
internal pullups. The Port 3 output buffers can drive  
LS TTL inputs. Port 3 pins that have 1's written to  
them are pulled high by the internal pullups, and in  
that state can be used as inputs. As inputs, Port 3  
pins that are externally pulled low will source current  
EA should be strapped to V  
executions.  
for internal program  
CC  
(I , on the datasheet) because of the pullups.  
IL  
XTAL1: Input to the inverting oscillator amplifier.  
Port 3 also serves the functions of various special  
features of the MCS 51 microcontroller family, as  
listed below:  
XTAL2: Output from the inverting oscillator amplifi-  
er.  
Port Pin  
Alternate Function  
RXD (serial input port)  
TXD (serial output port)  
INT0 (external interrupt 0)  
INT1 (external interrupt 1)  
T0 (Timer 0 external input)  
T1 (Timer 1 external input)  
WR (external data memory write strobe)  
RD (external data memory read strobe)  
OSCILLATOR CHARACTERISTICS  
P3.0  
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
XTAL1 and XTAL2 are the input and output, respec-  
tively, of a inverting amplifier which can be config-  
ured for use as an on-chip oscillator, as shown in  
Figure 4. Either a quartz crystal or ceramic resonator  
may be used. More detailed information concerning  
the use of the on-chip oscillator is available in Appli-  
cation Note AP-155, ``Oscillators for Microcontrol-  
lers.''  
To drive the device from an external clock source,  
XTAL1 should be driven, while XTAL2 floats, as  
shown in Figure 5. There are no requirements on the  
duty cycle of the external clock signal, since the in-  
put to the internal clocking circuitry is through a di-  
vide-by-two flip-flop, but minimum and maximum  
high and low times specified on the datasheet must  
be observed.  
RESET: Reset input. A high on this pin for two ma-  
chine cycles while the oscillator is running resets the  
device. An internal pulldown resistor permits a pow-  
er-on reset with only a capacitor connected to V  
.
CC  
ALE/PROG : Address Latch Enable output pulse for  
latching the low byte of the address during accesses  
to external memory.  
An external oscillator may encounter as much as a  
100 pF load at XTAL1 when it starts up. This is due  
to interaction between the amplifier and its feedback  
In normal operation ALE is emitted at a constant  
rate of (/6 the oscillator frequency, and may be used  
for external timing or clocking purposes. Note, how-  
ever, that one ALE pulse is skipped during each ac-  
cess to external Data Memory.  
capacitance. Once the external signal meets the V  
IL  
and V specifications the capacitance will not ex-  
IH  
ceed 20 pF.  
Throughout the remainder of this datasheet, ALE will  
refer to the signal coming out of the ALE/PROG pin,  
and the pin will be referred to as the ALE/PROG pin.  
PSEN: Program Store Enable is the read strobe to  
external Program Memory.  
When the 83C51FA is executing code from external  
Program Memory, PSEN is activated twice each ma-  
chine cycle, except that two PSEN activations are  
skipped during each access to external Data Memo-  
ry.  
270501±5  
e
g
C1, C2  
30 pF 10 pF for Crystals  
For Ceramic Resonators, contact resonator manufacturer.  
Figure 4. Oscillator Connections  
5
AUTOMOTIVE 80C51FA/83C51FA  
restored to its normal operating level and must be  
held active long enough for the oscillator to restart  
and stabilize (normally less than 10 ms).  
With an external interrupt, INT0 or INT1 must be en-  
abled and configured as level-sensitive. Holding the  
pin low restarts the oscillator but bringing the pin  
back high completes the exit. Once the interrupt is  
serviced, the next instruction to be executed after  
RETI will be the one following the instruction that put  
the device into Power Down.  
270501±6  
Figure 5. External Clock Drive Configuration  
DESIGN CONSIDERATION  
IDLE MODE  
When the Idle mode is terminated by a hardware  
reset, the device normally resumes program execu-  
tion, from where it left off, up to two machine cycles  
before the internal reset algorithm takes control. On-  
chip hardware inhibits access to internal RAM in this  
event, but access to the port pins is not inhibited. To  
eliminate the possibility of an unexpected write when  
Idle is terminated by reset, the instruction following  
the one that invokes Idle should not be one that  
writes to a port pin or to external memory.  
The user's software can invoke the Idle Mode. When  
the microcontroller is in this mode, power consump-  
tion is reduced. The Special Function Registers and  
the onboard RAM retain their values during Idle, but  
the processor stops executing instructions. Idle  
Mode will be exited if the chip is reset or if an en-  
abled interrupt occurs. The PCA timer/counter can  
optionally be left running or paused during Idle  
Mode.  
ONCE MODE  
POWER DOWN MODE  
The ONCE (``On-CircuitEmulation'') Mode facilitates  
testing and debugging of systems using the  
83C51FA without the 83C51FA having to be re-  
moved from the circuit. The ONCE Mode is invoked  
by:  
To save even more power, a Power Down mode can  
be invoked by software. In this mode, the oscillator  
is stopped and the instruction that invoked Power  
Down is the last instruction executed. The on-chip  
RAM and Special Function Registers retain their val-  
ues if the Power Down mode is terminated with an  
interrupt.  
1) Pull ALE low while the device is in reset and  
PSEN is high;  
2) Hold ALE low as RST is deactivated.  
On the 83C51FA either a hardware reset or external  
interrupt can cause an exit from Power Down. Reset  
redefines all the SFRs but does not change the on-  
chip RAM. An external interrupt allows both the  
SFRs and the on-chip RAM to retain their values.  
While the device is in ONCE Mode, the Port 0 pins  
float, the other port pins and ALE and PSEN are  
weakly pulled high. The oscillator circuit remains ac-  
tive. While the 83C51FA is in this mode, an emulator  
or test CPU can be used to drive the circuit. Normal  
operation is restored when a normal reset is applied.  
To properly terminate Power Down the reset or ex-  
ternal interrupt should not be executed before V is  
CC  
Table 2. Status of the External Pins during Idle and Power Down  
Program  
Memory  
Mode  
Idle  
ALE  
PSEN  
PORT0  
PORT1  
PORT2  
PORT3  
Internal  
External  
Internal  
External  
1
1
0
0
1
1
0
0
Data  
Float  
Data  
Float  
Data  
Data  
Data  
Data  
Data  
Address  
Data  
Data  
Data  
Data  
Data  
Idle  
Power Down  
Power Down  
Data  
NOTE:  
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook, and Applica-  
tion Note AP-252, ``Designingwith the 80C51BH.''  
6
AUTOMOTIVE 80C51FA/83C51FA  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This is a production data sheet. The specifi-  
cations are subject to change without notice.  
Ambient Temperature  
Under Bias...................................-40°C to +125°C  
*WARNING: Stressing the device beyond the ``Absolute  
Maximum Ratings'' may cause permanent damage.  
These are stress ratings only. Operation beyond the  
``Operating Conditions'' is not recommended and ex-  
tended exposure beyond the ``Operating Conditions''  
may affect device reliability.  
Storage Temperature.......................-65°C to +150°C  
Voltage on Any Other Pin to V  
SS........-0.5V to +6.5V  
I
I/O Pin........................................................15mA  
OL  
Power Dissipation  
(Based on PACKAGE heat transfer limitations, not  
device power consumption)  
Typical Junction Temperature (T )................+135°C  
J
a
(Based upon Ambient Temperature at 125 C)  
§
Typical Thermal Resistance  
Junction-to-Ambient (i  
)
JA  
PDIP.......................................................45°C/W  
PLCC......................................................46°C/W  
e b  
a
e
e
g
DC CHARACTERISTICS: (T  
40 C to 125 C; V  
5V 10%; V  
0V)  
§
§
A
CC  
SS  
Symbol  
Parameter  
Input Low Voltage  
Input Low Voltage EA  
Input High Voltage  
Min  
Typ  
Max  
Unit  
Test Conditions  
b
0.5  
0
b
b
V
V
V
0.2 V  
0.2 V  
0.1  
0.3  
V
V
V
IL  
CC  
CC  
IL1  
IH  
a
a
0.2 V  
0.9  
V
0.5  
CC  
CC  
(Except XTAL2, RST, EA)  
a
V
V
V
Input High Voltage  
(XTAL, RST)  
0.7 V  
V
0.5  
V
V
V
IH1  
OL  
CC  
CC  
(1)  
e
Output Low Voltage  
(Ports 1, 2 and 3)  
0.45  
0.45  
I
1.6 mA  
OL  
e
e
e
Output Low Voltage  
I
20  
3.2 mA  
7.0 mA  
OL1  
OL  
(1)  
(Port 0, ALE/PROG, PSEN)  
I
OL  
I
OL  
e b  
60 mA  
V
Output High Voltage  
(Ports 1, 2 and 3  
ALE/PROG and PSEN)  
2.4  
0.9 V  
V
I
OH  
OH  
(2)  
e b  
e b  
e b  
V
V
I
10 mA  
CC  
OH  
V
OH1  
Output High Voltage  
2.4  
0.9 V  
I
OH  
800 mA  
(2)  
(Port 0 in External Bus Mode)  
V
I
80 mA  
CC  
OH  
b
b
g
e
I
I
Logical 0 Input Current  
(Ports 1, 2 and 3)  
10  
50  
10  
mA  
V
0.45V  
IL  
IN  
e
Input leakage Current  
(Port 0)  
0.02  
mA  
V
IN  
V
IL  
or V  
LI  
IH  
7
AUTOMOTIVE 80C51FA/83C51FA  
e b  
a
e
e
g
DC CHARACTERISTICS: (T  
40 C to 125 C; V  
5V 10%; V  
0V) (Continued)  
§
§
A
CC  
SS  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit Test Conditions  
b
b
e
I
TL  
Logical 1 to 0 Transition Current  
(Ports 1, 2, and 3)  
265  
650  
mA  
V
IN  
2V  
RRST  
CIO  
RST Pulldown Resistor  
Pin Capacitance  
40  
100  
10  
225  
KX  
pF  
@1MHz, 25 C  
§
I
Power Supply Current:  
(Note 3)  
CC  
Running at 12 MHz (Figure 5)  
Idle Mode at 12 MHz (Figure 5)  
40  
15  
150  
mA  
mA  
mA  
Power Down Mode (I  
)
PD  
NOTES:  
1. Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V s of ALE and Ports 1 and 3.  
OL  
The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0  
transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE  
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch  
with a Schmitt Trigger Strobe input.  
2. Capacitive loading on Ports 0 and 2 cause the V  
address lines are stabilizing.  
on ALE and PSEN to drop below the 0.9 V specification when the  
OH  
CC  
3. See Figures 6±9 for test conditions. Minimum V  
for Power Down is 2.0V.  
CC  
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and  
5.0V.  
5. Under steady state (non-transient) conditions, I must be externally limited as follows:  
OL  
10 mA  
Maximum I per Port Pin:  
OL  
Maximum I per 8-Bit Port -  
OL  
Port 0:  
Ports 1, 2, and 3:  
Maximum Total I for all Output Pins:  
26 mA  
15 mA  
71 mA  
OL  
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater  
OL  
OL  
than the listed test conditions.  
6. Contact Intel for design-in information.  
8
AUTOMOTIVE 80C51FA/83C51FA  
270501±7  
I
Max at other frequencies is given by:  
CC  
Active Mode  
I
270501±8  
e
c
a
e
e
Max  
(3  
Osc Freq)  
4
TCLCH  
TCHCL  
5 ns  
CC  
Idle Mode  
Max  
e
c
a
I
(0.49  
Osc Freq)  
1.6  
CC  
Figure 7. I Test Condition, Active Mode  
CC  
Where Osc Freq is in MHz, I  
is in mA.  
CC  
All other pins disconnected.  
Figure 6. I vs Frequency  
CC  
270501±10  
Figure 9. I Test Condition,  
CC  
270501±9  
Power Down Mode.  
e
e
TCLCH  
TCHCL  
5 ns  
All other pins disconnected.  
Figure 8. I Test Condition Idle Mode.  
CC  
e
V
2.0V to 5.5V.  
CC  
All other pins disconnected.  
270501±11  
e
e
Figure 10. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH  
TCHCL  
5 ns.  
CC  
9
AUTOMOTIVE 80C51FA/83C51FA  
L: Logic level LOW, or ALE  
P: PSEN  
EXPLANATION OF THE AC SYMBOLS  
Q: Output Data  
R: RD signal  
T: Time  
Each timing symbol has 5 characters. The first char-  
acter is always a `T' (stands for time). The other  
characters, depending on their positions, stand for  
the name of a signal or the logical status of that  
signal. The following is a list of all the characters and  
what they stand for.  
V: Valid  
W: WR signal  
X: No longer a valid logic level  
Z: Float  
A: Address  
C: Clock  
For example,  
D: Input Data  
H: Logic level HIGH  
I: Instruction (program memory contents)  
e
e
T
AVLL  
T
LLPL  
Time from Address Valid to ALE Low  
Time from ALE Low to PSEN Low  
e b  
a
e
e
g
AC CHARACTERISTICS (T  
40 C to 125 C, V  
5V 10%, V  
0V, Load Capacitance  
e
80 pF)  
§
§
A
e
CC  
SS  
for Port 0, ALE/PROG and PSEN 100 pF, Load Capacitance for All Other Outputs  
EXTERNAL MEMORY CHARACTERISTICS  
12 MHz Oscillator  
Variable Oscillator  
Symbol  
Parameter  
Units  
Min  
Max  
Min  
Max  
1/T  
Oscillator Frequency  
3.5  
16  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLCL  
b
40  
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ALE Pulse Width  
127  
43  
2T  
LHLL  
CLCL  
b
40  
Address Valid to ALE Low  
Address Hold After ALE Low  
ALE Low to Valid Instruction In  
ALE Low to PSEN Low  
T
T
AVLL  
LLAX  
LLIV  
CLCL  
CLCL  
b
53  
30  
b
224  
135  
4T  
3T  
110  
115  
CLCL  
b
53  
T
30  
LLPL  
CLCL  
b
45  
PSEN Pulse Width  
205  
3T  
PLPH  
PLIV  
CLCL  
b
PSEN Low to Valid Instruction In  
Input Instr Hold After PSEN Trans  
Input Instr Float After PSEN Trans  
Address to Valid Instruction In  
PSEN Low to Address Float  
RD Pulse Width  
CLCL  
0
0
PXIX  
b
b
59  
302  
10  
T
25  
PXIZ  
CLCL  
5T  
115  
AVIV  
CLCL  
10  
PLAZ  
RLRH  
WLWH  
RLDV  
RHDX  
RHDZ  
LLDV  
AVDV  
LLWL  
AVWL  
QVWX  
WHQX  
QVWH  
RLAZ  
WHLH  
b
b
400  
400  
6T  
6T  
100  
100  
CLCL  
WR Pulse Width  
CLCL  
b
RD Low to Valid Data In  
Data Hold After RD High  
Data Float After RD High  
ALE Low to Valid Data In  
Address Valid to Valid Data In  
ALE Low to RD or WR Low  
Data Valid to WR Low  
242  
5T  
175  
CLCL  
b
b
10  
10  
b
107  
507  
575  
300  
2T  
60  
CLCL  
b
8T  
9T  
160  
175  
CLCL  
CLCL  
b
b
a
50  
200  
203  
23  
3T  
50  
130  
50  
3T  
CLCL  
CLCL  
b
4T  
T
CLCL  
CLCL  
CLCL  
CLCL  
b
b
b
Address Valid before WR Low  
Data Hold after WR High  
Data Valid to WE High  
33  
T
50  
433  
7T  
150  
RD Low to Address Float  
RD or WR High to ALE High  
0
0
b
a
40  
43  
123  
T
40  
T
CLCL  
CLCL  
10  
AUTOMOTIVE 80C51FA/83C51FA  
EXTERNAL PROGRAM MEMORY READ CYCLE  
270501±12  
EXTERNAL DATA MEMORY READ CYCLE  
270501±13  
EXTERNAL DATA MEMORY WRITE CYCLE  
270501±14  
11  
AUTOMOTIVE 80C51FA/83C51FA  
SERIAL PORT TIMING-SHIFT REGISTER MODE  
e b  
a
e
e
e
g
Test Conditions:  
T
A
40 C to 125 C; V  
5V 10%; V  
0V; Load Capacitance  
Variable Oscillator  
Min Max  
80 pF  
§
§
CC  
SS  
12 MHz Oscillator  
Symbol  
Parameter  
Units  
Min  
1
Max  
T
T
Serial Port Clock Cycle Time  
12T  
ms  
XLXL  
CLCL  
b
CLCL  
Output Data Setup to Clock  
Rising Edge  
700  
10T  
133  
ns  
QVXH  
b
T
XHQX  
T
XHDX  
T
XHDV  
Output Data Hold after  
Clock Rising Edge  
50  
0
2T  
117  
ns  
ns  
ns  
CLCL  
Input Data Hold After Clock  
Rising Edge  
0
b
133  
Clock Rising Edge to Input  
Data Valid  
700  
10T  
CLCL  
SHIFT REGISTER MODE TIMING WAVEFORMS  
270501±15  
EXTERNAL CLOCK DRIVE  
Symbol  
Parameter  
Oscillator Frequency  
High Time  
Min  
3.5  
20  
Max  
Units  
MHz  
ns  
1/T  
16  
CLCL  
CHCX  
T
T
T
T
Low Time  
20  
ns  
CLCX  
CLCH  
CHCL  
Rise Time  
20  
20  
ns  
Fall Time  
ns  
EXTERNAL CLOCK DRIVE WAVEFORM  
270501±16  
12  
AUTOMOTIVE 80C51FA/83C51FA  
AC TESTING INPUT, OUTPUT WAVEFORMS  
FLOAT WAVEFORMS  
270501±18  
For timing purposes a port pin is no longer floating when a  
100 mV change from load voltage occurs, and begins to float  
270501±17  
b
AC Inputs during testing are driven at V  
0.5V for a Logic ``1''  
and 0.45V for a Logic ``0''. Timing measurements are made at V  
CC  
IH  
when a 100 mV change from the loaded V /V  
level occurs.  
OH OL  
min for a Logic ``1'' and V max for a Logic ``0''.  
t
OL  
g
I
/I  
20 mA. This is for Ports 1, 2 and 3.  
OL OH  
DATASHEET REVISION HISTORY  
The following are key differences between this datasheet and the -007 version:  
1. Product prefix variables are now indicated with an x.  
The following are key differences between this datasheet and the -006 version:  
1. The ``preliminary'' status was dropped and replaced with production status (no label).  
2. Trademarks were updated.  
The following are key differences between the -006 and the -005 version of the datasheet:  
1. Preliminary notice has been added to the Title page.  
2. Figure 3 Pin Connections has been modified, RST pin is now RESET pin.  
3. RST pin description is now RESET pin description.  
4. Figure 6 I vs. Frequency has been corrected to show test conditions.  
CC  
5. I Max spec has been corrected.  
CC  
6. A.C. Characteristic table 1/T  
spec has been changed to have a Max frequency of 16 MHz.  
CLCL  
The following are key differences between the -005 and the -004 version of the datasheet:  
1. ``NC'' pin labels changed to ``Reserved'' in Figure 3.  
2. Capacitor value for ceramic resonators deleted in Figure 4.  
The following are the key differences between the -003 version of the 8XC51FA datasheet and the -004  
version of the 80C51FA/83C51FA datasheet:  
1. Removed references to EPROM from the 8XC51FA datasheet.  
2. Revised Figure 4, ``Oscillator Connections''.  
The following are the key differences between the -002 and the -003 version of this datasheet:  
1. Dropped word ``maximum'' from I in the Absolute Maximum Rating table.  
OL  
2. Dropped EA from I specification of the DC table.  
LI  
3. Corrected TQVWH specification (from TTCLCL -70 to TCLCL -150).  
4. Added note on external clock capacitance loading.  
5. Changed the title to 80C51FA/83C51FA Event-Control CHMOS Single-Chip 8-Bit Microcontroller.  
6. Added pin count to Figure 1.  
g
7. Changed I to 10 μA.  
LI  
8. Added I Power Down Mode 150 nA.  
CC  
13  

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