Intel 80C188XL User Manual

80C186XL/80C188XL  
Microprocessor  
User’s Manual  
80C186XL/80C188XL  
Microprocessor  
User’s Manual  
1995  
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© INTEL CORPORATION, 1995  
CONTENTS  
CHAPTER 1  
INTRODUCTION  
1.1  
1.2  
1.3  
1.3.1  
1.3.2  
HOW TO USE THIS MANUAL....................................................................................... 1-2  
RELATED DOCUMENTS.............................................................................................. 1-3  
ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-4  
FaxBack Service .......................................................................................................1-4  
Bulletin Board System (BBS) ....................................................................................1-5  
1.3.2.1  
1.3.3  
1.3.4  
How to Find ApBUILDER Software and Hypertext Documents on the BBS ...1-6  
CompuServe Forums ................................................................................................1-6  
World Wide Web .......................................................................................................1-6  
TECHNICAL SUPPORT ................................................................................................ 1-6  
PRODUCT LITERATURE.............................................................................................. 1-7  
TRAINING CLASSES.................................................................................................... 1-7  
1.4  
1.5  
1.6  
CHAPTER 2  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.1  
2.1.1  
ARCHITECTURAL OVERVIEW .................................................................................... 2-1  
Execution Unit ...........................................................................................................2-2  
Bus Interface Unit .....................................................................................................2-3  
General Registers .....................................................................................................2-4  
Segment Registers ...................................................................................................2-5  
Instruction Pointer .....................................................................................................2-6  
Flags .........................................................................................................................2-7  
Memory Segmentation ..............................................................................................2-8  
Logical Addresses ...................................................................................................2-10  
Dynamically Relocatable Code ...............................................................................2-13  
2.1.2  
2.1.3  
2.1.4  
2.1.5  
2.1.6  
2.1.7  
2.1.8  
2.1.9  
2.1.10 Stack Implementation .............................................................................................2-15  
2.1.11 Reserved Memory and I/O Space ...........................................................................2-15  
2.2  
2.2.1  
2.2.1.1  
2.2.1.2  
SOFTWARE OVERVIEW............................................................................................ 2-17  
Instruction Set .........................................................................................................2-17  
Data Transfer Instructions .............................................................................2-18  
Arithmetic Instructions ...................................................................................2-19  
Bit Manipulation Instructions .........................................................................2-21  
String Instructions ..........................................................................................2-22  
Program Transfer Instructions .......................................................................2-23  
Processor Control Instructions ......................................................................2-27  
Addressing Modes ..................................................................................................2-27  
Register and Immediate Operand Addressing Modes ...................................2-27  
Memory Addressing Modes ...........................................................................2-28  
I/O Port Addressing .......................................................................................2-36  
Data Types Used in the 80C186 Modular Core Family .................................2-37  
2.2.1.3  
2.2.1.4  
2.2.1.5  
2.2.1.6  
2.2.2  
2.2.2.1  
2.2.2.2  
2.2.2.3  
2.2.2.4  
iii  
CONTENTS  
2.3  
2.3.1  
2.3.1.1  
2.3.1.2  
2.3.1.3  
2.3.2  
2.3.3  
2.3.4  
2.3.5  
INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39  
Interrupt/Exception Processing ...............................................................................2-39  
Non-Maskable Interrupts ...............................................................................2-42  
Maskable Interrupts .......................................................................................2-43  
Exceptions .....................................................................................................2-43  
Software Interrupts ..................................................................................................2-45  
Interrupt Latency .....................................................................................................2-45  
Interrupt Response Time ........................................................................................2-46  
Interrupt and Exception Priority ...............................................................................2-46  
CHAPTER 3  
BUS INTERFACE UNIT  
3.1  
3.2  
3.2.1  
3.2.2  
3.3  
MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-1  
ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-1  
16-Bit Data Bus .........................................................................................................3-1  
8-Bit Data Bus ...........................................................................................................3-5  
MEMORY AND I/O INTERFACES................................................................................. 3-6  
16-Bit Bus Memory and I/O Requirements ...............................................................3-7  
8-Bit Bus Memory and I/O Requirements .................................................................3-7  
BUS CYCLE OPERATION ............................................................................................ 3-7  
Address/Status Phase ............................................................................................3-10  
Data Phase .............................................................................................................3-13  
Wait States ..............................................................................................................3-13  
Idle States ...............................................................................................................3-18  
BUS CYCLES .............................................................................................................. 3-20  
Read Bus Cycles ....................................................................................................3-20  
3.3.1  
3.3.2  
3.4  
3.4.1  
3.4.2  
3.4.3  
3.4.4  
3.5  
3.5.1  
3.5.1.1  
3.5.2  
3.5.3  
3.5.3.1  
3.5.4  
3.5.5  
3.5.6  
Refresh Bus Cycles .......................................................................................3-22  
Write Bus Cycles .....................................................................................................3-22  
Interrupt Acknowledge Bus Cycle ...........................................................................3-25  
System Design Considerations .....................................................................3-27  
HALT Bus Cycle ......................................................................................................3-28  
Temporarily Exiting the HALT Bus State .................................................................3-30  
Exiting HALT ...........................................................................................................3-32  
3.6  
SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-33  
Buffering the Data Bus ............................................................................................3-34  
Synchronizing Software and Hardware Events .......................................................3-36  
Using a Locked Bus ................................................................................................3-37  
Using the Queue Status Signals .............................................................................3-38  
MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-39  
Entering Bus HOLD ................................................................................................3-39  
3.6.1  
3.6.2  
3.6.3  
3.6.4  
3.7  
3.7.1  
3.7.1.1  
3.7.1.2  
3.7.2  
3.8  
HOLD Bus Latency ........................................................................................3-40  
Refresh Operation During a Bus HOLD ........................................................3-41  
Exiting HOLD ..........................................................................................................3-43  
BUS CYCLE PRIORITIES........................................................................................... 3-44  
iv  
CONTENTS  
CHAPTER 4  
PERIPHERAL CONTROL BLOCK  
4.1  
4.2  
4.3  
4.4  
4.4.1  
4.4.2  
4.4.3  
PERIPHERAL CONTROL REGISTERS........................................................................ 4-1  
PCB RELOCATION REGISTER.................................................................................... 4-1  
RESERVED LOCATIONS ............................................................................................. 4-4  
ACCESSING THE PERIPHERAL CONTROL BLOCK.................................................. 4-4  
Bus Cycles ...............................................................................................................4-4  
READY Signals and Wait States .............................................................................4-4  
F-Bus Operation .......................................................................................................4-5  
4.4.3.1  
4.4.3.2  
4.4.3.3  
4.5  
4.5.1  
Writing the PCB Relocation Register ...............................................................4-6  
Accessing the Peripheral Control Registers ....................................................4-6  
Accessing Reserved Locations .......................................................................4-6  
SETTING THE PCB BASE LOCATION......................................................................... 4-6  
Considerations for the 80C187 Math Coprocessor Interface ....................................4-7  
CHAPTER 5  
CLOCK GENERATION AND POWER MANAGEMENT  
5.1  
5.1.1  
5.1.1.1  
5.1.1.2  
5.1.2  
5.1.3  
5.1.4  
CLOCK GENERATION.................................................................................................. 5-1  
Crystal Oscillator .......................................................................................................5-1  
Oscillator Operation .........................................................................................5-2  
Selecting Crystals ............................................................................................5-5  
Using an External Oscillator ......................................................................................5-6  
Output from the Clock Generator ..............................................................................5-6  
Reset and Clock Synchronization .............................................................................5-6  
5.2  
5.2.1  
5.2.1.1  
5.2.1.2  
POWER MANAGEMENT............................................................................................. 5-10  
Power-Save Mode ..................................................................................................5-11  
Entering Power-Save Mode ..........................................................................5-11  
Leaving Power-Save Mode ...........................................................................5-13  
Example Power-Save Initialization Code .......................................................5-13  
5.2.1.3  
CHAPTER 6  
CHIP-SELECT UNIT  
6.1  
6.2  
6.3  
6.4  
COMMON METHODS FOR GENERATING CHIP-SELECTS....................................... 6-1  
CHIP-SELECT UNIT FEATURES AND BENEFITS ...................................................... 6-1  
CHIP-SELECT UNIT FUNCTIONAL OVERVIEW ......................................................... 6-2  
PROGRAMMING........................................................................................................... 6-6  
6.4.1  
6.4.2  
6.4.2.1  
6.4.2.2  
6.4.2.3  
6.4.2.4  
Initialization Sequence ..............................................................................................6-6  
Programming the Active Ranges ............................................................................6-12  
UCS Active Range ........................................................................................6-12  
LCS Active Range .........................................................................................6-13  
MCS Active Range ........................................................................................6-13  
PCS Active Range .........................................................................................6-15  
Bus Wait State and Ready Control .........................................................................6-15  
Overlapping Chip-Selects .......................................................................................6-16  
6.4.3  
6.4.4  
v
CONTENTS  
6.4.5  
6.4.6  
Memory or I/O Bus Cycle Decoding ........................................................................6-17  
Programming Considerations ..................................................................................6-17  
CHIP-SELECTS AND BUS HOLD............................................................................... 6-18  
EXAMPLES ................................................................................................................. 6-18  
Example 1: Typical System Configuration ..............................................................6-18  
6.5  
6.6  
6.6.1  
CHAPTER 7  
REFRESH CONTROL UNIT  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.7.1  
7.7.2  
7.7.2.1  
7.7.2.2  
7.7.2.3  
7.7.3  
7.8  
THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2  
REFRESH CONTROL UNIT CAPABILITIES................................................................. 7-2  
REFRESH CONTROL UNIT OPERATION.................................................................... 7-2  
REFRESH ADDRESSES............................................................................................... 7-4  
REFRESH BUS CYCLES.............................................................................................. 7-5  
GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5  
PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7  
Calculating the Refresh Interval ................................................................................7-7  
Refresh Control Unit Registers .................................................................................7-7  
Refresh Base Address Register ......................................................................7-8  
Refresh Clock Interval Register .......................................................................7-8  
Refresh Control Register .................................................................................7-9  
Programming Example ...........................................................................................7-10  
REFRESH OPERATION AND BUS HOLD.................................................................. 7-12  
CHAPTER 8  
INTERRUPT CONTROL UNIT  
8.1  
8.2  
8.2.1  
8.2.1.1  
8.2.1.2  
8.2.1.3  
FUNCTIONAL OVERVIEW............................................................................................ 8-1  
MASTER MODE ............................................................................................................ 8-2  
Generic Functions in Master Mode ...........................................................................8-2  
Interrupt Masking .............................................................................................8-3  
Interrupt Priority ...............................................................................................8-3  
Interrupt Nesting ..............................................................................................8-4  
8.3  
FUNCTIONAL OPERATION IN MASTER MODE ......................................................... 8-5  
Typical Interrupt Sequence .......................................................................................8-5  
Priority Resolution .....................................................................................................8-5  
8.3.1  
8.3.2  
8.3.2.1  
8.3.2.2  
8.3.3  
8.3.3.1  
8.3.4  
8.3.5  
8.3.6  
8.3.7  
Priority Resolution Example ............................................................................8-6  
Interrupts That Share a Single Source ............................................................8-7  
Cascading with External 8259As ..............................................................................8-7  
Special Fully Nested Mode ..............................................................................8-8  
Interrupt Acknowledge Sequence .............................................................................8-9  
Polling .......................................................................................................................8-9  
Edge and Level Triggering ......................................................................................8-10  
Additional Latency and Response Time .................................................................8-10  
vi  
CONTENTS  
8.4  
8.4.1  
PROGRAMMING THE INTERRUPT CONTROL UNIT ............................................... 8-11  
Interrupt Control Registers ......................................................................................8-12  
Interrupt Request Register ......................................................................................8-16  
Interrupt Mask Register ...........................................................................................8-16  
Priority Mask Register .............................................................................................8-17  
In-Service Register .................................................................................................8-18  
Poll and Poll Status Registers .................................................................................8-19  
End-of-Interrupt (EOI) Register ...............................................................................8-21  
Interrupt Status Register .........................................................................................8-22  
SLAVE MODE ............................................................................................................. 8-23  
Slave Mode Programming ......................................................................................8-25  
8.4.2  
8.4.3  
8.4.4  
8.4.5  
8.4.6  
8.4.7  
8.4.8  
8.5  
8.5.1  
8.5.1.1  
8.5.1.2  
8.5.1.3  
8.5.2  
8.5.3  
Interrupt Vector Register ...............................................................................8-26  
End-Of-Interrupt Register ..............................................................................8-27  
Other Registers .............................................................................................8-28  
Interrupt Vectoring in Slave Mode ...........................................................................8-29  
Initializing the Interrupt Control Unit for Master Mode .............................................8-30  
CHAPTER 9  
TIMER/COUNTER UNIT  
9.1  
9.2  
9.2.1  
9.2.2  
9.2.3  
FUNCTIONAL OVERVIEW............................................................................................ 9-1  
PROGRAMMING THE TIMER/COUNTER UNIT .......................................................... 9-6  
Initialization Sequence ............................................................................................9-11  
Clock Sources .........................................................................................................9-12  
Counting Modes ......................................................................................................9-12  
9.2.3.1  
Retriggering ...................................................................................................9-13  
Pulsed and Variable Duty Cycle Output ..................................................................9-14  
Enabling/Disabling Counters ...................................................................................9-15  
Timer Interrupts .......................................................................................................9-16  
Programming Considerations ..................................................................................9-16  
TIMING ........................................................................................................................ 9-16  
Input Setup and Hold Timings .................................................................................9-16  
Synchronization and Maximum Frequency .............................................................9-17  
9.2.4  
9.2.5  
9.2.6  
9.2.7  
9.3  
9.3.1  
9.3.2  
9.3.2.1  
Timer/Counter Unit Application Examples .....................................................9-17  
Real-Time Clock .....................................................................................................9-17  
Square-Wave Generator .........................................................................................9-17  
Digital One-Shot ......................................................................................................9-17  
9.3.3  
9.3.4  
9.3.5  
CHAPTER 10  
DIRECT MEMORY ACCESS UNIT  
10.1 FUNCTIONAL OVERVIEW.......................................................................................... 10-1  
10.1.1 The DMA Transfer ..................................................................................................10-1  
10.1.1.1  
10.1.1.2  
DMA Transfer Directions ...............................................................................10-3  
Byte and Word Transfers ..............................................................................10-3  
10.1.2 Source and Destination Pointers ............................................................................10-3  
vii  
CONTENTS  
10.1.3 DMA Requests ........................................................................................................10-3  
10.1.4 External Requests ...................................................................................................10-4  
10.1.4.1  
10.1.4.2  
Source Synchronization ................................................................................10-5  
Destination Synchronization ..........................................................................10-5  
10.1.5 Internal Requests ....................................................................................................10-6  
10.1.5.1  
10.1.5.2  
Timer 2-Initiated Transfers ............................................................................10-6  
Unsynchronized Transfers ............................................................................10-6  
10.1.6 DMA Transfer Counts .............................................................................................10-7  
10.1.7 Termination and Suspension of DMA Transfers .....................................................10-7  
10.1.7.1  
10.1.7.2  
10.1.7.3  
10.1.7.4  
Termination at Terminal Count ......................................................................10-7  
Software Termination ....................................................................................10-7  
Suspension of DMA During NMI ...................................................................10-7  
Software Suspension ....................................................................................10-7  
10.1.8 DMA Unit Interrupts ................................................................................................10-8  
10.1.9 DMA Cycles and the BIU ........................................................................................10-8  
10.1.10 The Two-Channel DMA Unit ...................................................................................10-8  
10.1.10.1  
DMA Channel Arbitration ...............................................................................10-8  
10.2 PROGRAMMING THE DMA UNIT ............................................................................ 10-10  
10.2.1 DMA Channel Parameters ....................................................................................10-10  
10.2.1.1  
10.2.1.2  
10.2.1.3  
10.2.1.4  
10.2.1.5  
10.2.1.6  
10.2.1.7  
10.2.1.8  
Programming the Source and Destination Pointers ....................................10-10  
Selecting Byte or Word Size Transfers ........................................................10-14  
Selecting the Source of DMA Requests ......................................................10-17  
Arming the DMA Channel ............................................................................10-18  
Selecting Channel Synchronization .............................................................10-18  
Programming the Transfer Count Options ...................................................10-18  
Generating Interrupts on Terminal Count ....................................................10-19  
Setting the Relative Priority of a Channel ....................................................10-19  
10.2.2 Suspension of DMA Transfers ..............................................................................10-20  
10.2.3 Initializing the DMA Unit ........................................................................................10-20  
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......................................... 10-20  
10.3.1 DRQ Pin Timing Requirements .............................................................................10-20  
10.3.2 DMA Latency ........................................................................................................10-21  
10.3.3 DMA Transfer Rates .............................................................................................10-21  
10.3.4 Generating a DMA Acknowledge ..........................................................................10-22  
10.4 DMA UNIT EXAMPLES ............................................................................................. 10-22  
CHAPTER 11  
MATH COPROCESSING  
11.1 OVERVIEW OF MATH COPROCESSING.................................................................. 11-1  
11.2 AVAILABILITY OF MATH COPROCESSING.............................................................. 11-1  
11.3 THE 80C187 MATH COPROCESSOR........................................................................ 11-2  
11.3.1 80C187 Instruction Set ...........................................................................................11-2  
11.3.1.1  
11.3.1.2  
11.3.1.3  
Data Transfer Instructions .............................................................................11-3  
Arithmetic Instructions ...................................................................................11-3  
Comparison Instructions ................................................................................11-5  
viii  
CONTENTS  
11.3.1.4  
11.3.1.5  
11.3.1.6  
Transcendental Instructions ..........................................................................11-5  
Constant Instructions .....................................................................................11-6  
Processor Control Instructions ......................................................................11-6  
11.3.2 80C187 Data Types ................................................................................................11-7  
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION...................................... 11-7  
11.4.1 Clocking the 80C187 .............................................................................................11-10  
11.4.2 Processor Bus Cycles Accessing the 80C187 ......................................................11-10  
11.4.3 System Design Tips ..............................................................................................11-11  
11.4.4 Exception Trapping ...............................................................................................11-13  
11.5 EXAMPLE MATH COPROCESSOR ROUTINES...................................................... 11-13  
CHAPTER 12  
ONCE MODE  
12.1 ENTERING/LEAVING ONCE MODE........................................................................... 12-1  
APPENDIX A  
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
A.1  
A.1.1  
A.1.2  
A.1.3  
80C186 INSTRUCTION SET ADDITIONS ................................................................... A-1  
Data Transfer Instructions ...................................................................................... A-1  
String Instructions ................................................................................................... A-2  
High-Level Instructions ........................................................................................... A-2  
80C186 INSTRUCTION SET ENHANCEMENTS......................................................... A-8  
Data Transfer Instructions ...................................................................................... A-8  
Arithmetic Instructions ............................................................................................ A-9  
Bit Manipulation Instructions ................................................................................... A-9  
A.2  
A.2.1  
A.2.2  
A.2.3  
A.2.3.1  
A.2.3.2  
Shift Instructions ............................................................................................. A-9  
Rotate Instructions ....................................................................................... A-10  
APPENDIX B  
INPUT SYNCHRONIZATION  
B.1  
B.2  
WHY SYNCHRONIZERS ARE REQUIRED................................................................. B-1  
ASYNCHRONOUS PINS.............................................................................................. B-2  
APPENDIX C  
INSTRUCTION SET DESCRIPTIONS  
APPENDIX D  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
INDEX  
ix  
CONTENTS  
Figure  
FIGURES  
Page  
2-1  
2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
2-8  
Simplified Functional Block Diagram of the 80C186 Family CPU ................................2-2  
Physical Address Generation.......................................................................................2-3  
General Registers ........................................................................................................2-4  
Segment Registers.......................................................................................................2-6  
Processor Status Word ................................................................................................2-9  
Segment Locations in Physical Memory.....................................................................2-10  
Currently Addressable Segments...............................................................................2-11  
Logical and Physical Address ....................................................................................2-12  
Dynamic Code Relocation..........................................................................................2-14  
Stack Operation..........................................................................................................2-16  
Flag Storage Format ..................................................................................................2-19  
Memory Address Computation...................................................................................2-29  
Direct Addressing.......................................................................................................2-30  
Register Indirect Addressing ......................................................................................2-31  
Based Addressing ......................................................................................................2-31  
Accessing a Structure with Based Addressing...........................................................2-32  
Indexed Addressing....................................................................................................2-33  
Accessing an Array with Indexed Addressing ............................................................2-33  
Based Index Addressing ............................................................................................2-34  
Accessing a Stacked Array with Based Index Addressing.........................................2-35  
String Operand...........................................................................................................2-36  
I/O Port Addressing....................................................................................................2-36  
80C186 Modular Core Family Supported Data Types................................................2-38  
Interrupt Control Unit..................................................................................................2-39  
Interrupt Vector Table.................................................................................................2-40  
Interrupt Sequence.....................................................................................................2-42  
Interrupt Response Factors........................................................................................2-46  
Simultaneous NMI and Exception ..............................................................................2-47  
Simultaneous NMI and Single Step Interrupts............................................................2-48  
Simultaneous NMI, Single Step and Maskable Interrupt............................................2-49  
Physical Data Bus Models............................................................................................3-2  
16-Bit Data Bus Byte Transfers....................................................................................3-3  
16-Bit Data Bus Even Word Transfers .........................................................................3-4  
16-Bit Data Bus Odd Word Transfers...........................................................................3-5  
8-Bit Data Bus Word Transfers.....................................................................................3-6  
Typical Bus Cycle.........................................................................................................3-8  
T-State Relation to CLKOUT........................................................................................3-8  
BIU State Diagram .......................................................................................................3-9  
T-State and Bus Phases ............................................................................................3-10  
Address/Status Phase Signal Relationships ..............................................................3-11  
Demultiplexing Address Information...........................................................................3-12  
Data Phase Signal Relationships...............................................................................3-14  
Typical Bus Cycle with Wait States ............................................................................3-15  
ARDY and SRDY Pin Block Diagram.........................................................................3-15  
2-9  
2-10  
2-11  
2-12  
2-13  
2-14  
2-15  
2-16  
2-17  
2-18  
2-19  
2-20  
2-21  
2-22  
2-23  
2-24  
2-25  
2-26  
2-27  
2-28  
2-29  
2-30  
3-1  
3-2  
3-3  
3-4  
3-5  
3-6  
3-7  
3-8  
3-9  
3-10  
3-11  
3-12  
3-13  
3-14  
x
CONTENTS  
Page  
FIGURES  
Figure  
3-15  
3-16  
3-17  
3-18  
3-19  
3-20  
3-21  
3-22  
3-23  
3-24  
3-25  
3-26  
3-27  
3-28  
3-29  
3-30  
3-31  
3-32  
3-33  
3-34  
3-35  
3-36  
3-37  
4-1  
5-1  
5-2  
5-3  
5-4  
5-5  
5-6  
5-7  
5-8  
5-9  
5-10  
6-1  
6-2  
6-3  
6-4  
6-5  
6-6  
6-7  
Generating a Normally Not-Ready Bus Signal...........................................................3-16  
Generating a Normally Ready Bus Signal..................................................................3-17  
Normally Not-Ready System Timing ..........................................................................3-18  
Normally Ready System Timings ...............................................................................3-19  
Typical Read Bus Cycle .............................................................................................3-21  
Read-Only Device Interface .......................................................................................3-22  
Typical Write Bus Cycle..............................................................................................3-23  
16-Bit Bus Read/Write Device Interface.....................................................................3-24  
Interrupt Acknowledge Bus Cycle...............................................................................3-26  
Typical 82C59A Interface...........................................................................................3-27  
HALT Bus Cycle.........................................................................................................3-29  
Returning to HALT After a HOLD/HLDA Bus Exchange ............................................3-30  
Returning to HALT After a Refresh Bus Cycle ...........................................................3-31  
Returning to HALT After a DMA Bus Cycle................................................................3-32  
Exiting HALT ..............................................................................................................3-33  
DEN and DT/R Timing Relationships.........................................................................3-34  
Buffered AD Bus System............................................................................................3-35  
Qualifying DEN with Chip-Selects..............................................................................3-36  
Queue Status Timing..................................................................................................3-39  
Timing Sequence Entering HOLD ..............................................................................3-40  
Refresh Request During HOLD..................................................................................3-42  
Latching HLDA ...........................................................................................................3-43  
Exiting HOLD..............................................................................................................3-44  
PCB Relocation Register..............................................................................................4-2  
Clock Generator ...........................................................................................................5-1  
Ideal Operation of Pierce Oscillator..............................................................................5-2  
Crystal Connections to Microprocessor........................................................................5-3  
Equations for Crystal Calculations................................................................................5-4  
Simple RC Circuit for Powerup Reset ..........................................................................5-7  
Cold Reset Waveform ..................................................................................................5-8  
Warm Reset Waveform ................................................................................................5-9  
Clock Synchronization at Reset..................................................................................5-10  
Power-Save Register .................................................................................................5-12  
Power-Save Clock Transition.....................................................................................5-13  
Common Chip-Select Generation Methods..................................................................6-2  
Chip-Select Block Diagram...........................................................................................6-3  
Chip-Select Relative Timings .......................................................................................6-4  
UCS Reset Configuration.............................................................................................6-5  
UMCS Register Definition.............................................................................................6-7  
LMCS Register Definition.............................................................................................6-8  
MMCS Register Definition............................................................................................6-9  
PACS Register Definition ...........................................................................................6-10  
MPCS Register Definition...........................................................................................6-11  
MCS3:0 Active Ranges ..............................................................................................6-14  
6-8  
6-9  
6-10  
xi  
CONTENTS  
Figure  
FIGURES  
Page  
6-11  
6-12  
6-13  
7-1  
7-2  
7-3  
7-4  
7-5  
7-6  
7-7  
7-8  
7-9  
8-1  
8-2  
8-3  
8-4  
8-5  
8-6  
Wait State and Ready Control Functions ...................................................................6-16  
Using Chip-Selects During HOLD ..............................................................................6-18  
Typical System ...........................................................................................................6-19  
Refresh Control Unit Block Diagram.............................................................................7-1  
Refresh Control Unit Operation Flow Chart..................................................................7-3  
Refresh Address Formation..........................................................................................7-4  
Suggested DRAM Control Signal Timing Relationships...............................................7-6  
Formula for Calculating Refresh Interval for RFTIME Register....................................7-7  
Refresh Base Address Register...................................................................................7-8  
Refresh Clock Interval Register....................................................................................7-9  
Refresh Control Register............................................................................................7-10  
Regaining Bus Control to Run a DRAM Refresh Bus Cycle.......................................7-13  
Interrupt Control Unit in Master Mode ..........................................................................8-2  
Using External 8259A Modules in Cascade Mode.......................................................8-8  
Interrupt Control Unit Latency and Response Time ...................................................8-11  
Interrupt Control Register for Internal Sources...........................................................8-13  
Interrupt Control Register for Noncascadable External Pins......................................8-14  
Interrupt Control Register for Cascadable Interrupt Pins............................................8-15  
Interrupt Request Register .........................................................................................8-16  
Interrupt Mask Register ..............................................................................................8-17  
Priority Mask Register ................................................................................................8-18  
In-Service Register.....................................................................................................8-19  
Poll Register ...............................................................................................................8-20  
Poll Status Register....................................................................................................8-21  
End-of-Interrupt Register............................................................................................8-22  
Interrupt Status Register ............................................................................................8-23  
Interrupt Control Unit in Slave Mode ..........................................................................8-24  
Interrupt Sources in Slave Mode................................................................................8-25  
Interrupt Vector Register (Slave Mode Only)..............................................................8-27  
End-of-Interrupt Register in Slave Mode....................................................................8-28  
Request, Mask, and In-Service Registers ..................................................................8-28  
Interrupt Vectoring in Slave Mode..............................................................................8-29  
Interrupt Response Time in Slave Mode....................................................................8-30  
Timer/Counter Unit Block Diagram...............................................................................9-2  
Counter Element Multiplexing and Timer Input Synchronization..................................9-3  
Timers 0 and 1 Flow Chart ...........................................................................................9-4  
Timer/Counter Unit Output Modes................................................................................9-6  
Timer 0 and Timer 1 Control Registers ........................................................................9-7  
Timer 2 Control Register ..............................................................................................9-9  
Timer Count Registers................................................................................................9-10  
Timer Maxcount Compare Registers..........................................................................9-11  
TxOUT Signal Timing.................................................................................................9-15  
Typical DMA Transfer.................................................................................................10-2  
DMA Request Minimum Response Time ...................................................................10-4  
8-7  
8-8  
8-9  
8-10  
8-11  
8-12  
8-13  
8-14  
8-15  
8-16  
8-17  
8-18  
8-19  
8-20  
8-21  
9-1  
9-2  
9-3  
9-4  
9-5  
9-6  
9-7  
9-8  
9-9  
10-1  
10-2  
xii  
CONTENTS  
Page  
FIGURES  
Figure  
10-3  
10-4  
10-5  
10-6  
10-7  
10-8  
10-9  
Source-Synchronized Transfers.................................................................................10-5  
Destination-Synchronized Transfers ..........................................................................10-6  
Two-Channel DMA Module ........................................................................................10-9  
Examples of DMA Priority.........................................................................................10-10  
DMA Source Pointer (High-Order Bits).....................................................................10-11  
DMA Source Pointer (Low-Order Bits) .....................................................................10-12  
DMA Destination Pointer (High-Order Bits)..............................................................10-13  
10-10 DMA Destination Pointer (Low-Order Bits)...............................................................10-14  
10-11 DMA Control Register...............................................................................................10-15  
10-12 Transfer Count Register...........................................................................................10-19  
11-1  
11-2  
11-3  
11-4  
12-1  
A-1  
A-2  
A-3  
A-4  
A-5  
80C187-Supported Data Types..................................................................................11-8  
80C186 Modular Core Family/80C187 System Configuration....................................11-9  
80C187 Configuration with a Partially Buffered Bus.................................................11-12  
80C187 Exception Trapping via Processor Interrupt Pin..........................................11-14  
Entering/Leaving ONCE Mode ...................................................................................12-2  
Formal Definition of ENTER........................................................................................ A-3  
Variable Access in Nested Procedures ....................................................................... A-4  
Stack Frame for Main at Level 1.................................................................................. A-4  
Stack Frame for Procedure A at Level 2 ..................................................................... A-5  
Stack Frame for Procedure B at Level 3 Called from A............................................... A-6  
Stack Frame for Procedure C at Level 3 Called from B .............................................. A-7  
Input Synchronization Circuit....................................................................................... B-1  
A-6  
B-1  
xiii  
CONTENTS  
Table  
TABLES  
Page  
1-1  
1-2  
2-1  
2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
2-8  
2-9  
2-10  
2-11  
2-12  
3-1  
3-2  
3-3  
3-4  
3-5  
3-6  
3-7  
3-8  
4-1  
5-1  
6-1  
6-2  
6-3  
6-4  
6-5  
6-6  
7-1  
8-1  
8-2  
8-3  
8-4  
8-5  
9-1  
9-2  
11-1  
11-2  
11-3  
11-4  
11-5  
11-6  
11-7  
Comparison of 80C186 Modular Core Family Products...............................................1-2  
Related Documents and Software................................................................................1-3  
Implicit Use of General Registers.................................................................................2-5  
Logical Address Sources............................................................................................2-13  
Data Transfer Instructions..........................................................................................2-18  
Arithmetic Instructions................................................................................................2-20  
Arithmetic Interpretation of 8-Bit Numbers .................................................................2-21  
Bit Manipulation Instructions ......................................................................................2-21  
String Instructions.......................................................................................................2-22  
String Instruction Register and Flag Use....................................................................2-23  
Program Transfer Instructions....................................................................................2-25  
Interpretation of Conditional Transfers.......................................................................2-26  
Processor Control Instructions ...................................................................................2-27  
Supported Data Types ...............................................................................................2-37  
Bus Cycle Types ........................................................................................................3-12  
Read Bus Cycle Types...............................................................................................3-20  
Read Cycle Critical Timing Parameters......................................................................3-20  
Write Bus Cycle Types...............................................................................................3-23  
Write Cycle Critical Timing Parameters......................................................................3-25  
HALT Bus Cycle Pin States........................................................................................3-29  
Queue Status Signal Decoding ..................................................................................3-38  
Signal Condition Entering HOLD................................................................................3-40  
Peripheral Control Block...............................................................................................4-3  
Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit ........................5-4  
Chip-Select Unit Registers ...........................................................................................6-6  
UCS Block Size and Starting Address........................................................................6-12  
LCS Active Range......................................................................................................6-13  
MCS Active Range.....................................................................................................6-13  
MCS Block Size and Start Address Restrictions ........................................................6-14  
PCS Active Range......................................................................................................6-15  
Identification of Refresh Bus Cycles.............................................................................7-5  
Default Interrupt Priorities.............................................................................................8-3  
Fixed Interrupt Types ...................................................................................................8-9  
Interrupt Control Unit Registers in Master Mode ........................................................8-11  
Interrupt Control Unit Register Comparison ...............................................................8-26  
Slave Mode Fixed Interrupt Type Bits ........................................................................8-26  
Timer 0 and 1 Clock Sources.....................................................................................9-12  
Timer Retriggering......................................................................................................9-13  
80C187 Data Transfer Instructions.............................................................................11-3  
80C187 Arithmetic Instructions...................................................................................11-4  
80C187 Comparison Instructions...............................................................................11-5  
80C187 Transcendental Instructions..........................................................................11-5  
80C187 Constant Instructions....................................................................................11-6  
80C187 Processor Control Instructions......................................................................11-6  
80C187 I/O Port Assignments..................................................................................11-10  
xiv  
CONTENTS  
Page  
TABLES  
Table  
C-1  
C-2  
C-3  
C-4  
D-1  
D-2  
D-3  
D-4  
D-5  
Instruction Format Variables........................................................................................C-1  
Instruction Operands ...................................................................................................C-2  
Flag Bit Functions........................................................................................................C-3  
Instruction Set .............................................................................................................C-4  
Operand Variables ......................................................................................................D-1  
Instruction Set Summary.............................................................................................D-2  
Machine Instruction Decoding Guide...........................................................................D-9  
Mnemonic Encoding Matrix (Left Half) ......................................................................D-20  
Abbreviations for Mnemonic Encoding Matrix ...........................................................D-22  
xv  
CONTENTS  
Example  
EXAMPLES  
Page  
5-1  
6-1  
7-1  
8-1  
9-1  
9-2  
9-3  
10-1  
10-2  
11-1  
11-2  
Initializing the Power Management Unit for Power-Save Mode .................................5-14  
Initializing the Chip-Select Unit...................................................................................6-20  
Initializing the Refresh Control Unit............................................................................7-11  
Initializing the Interrupt Control Unit for Master Mode................................................8-31  
Configuring a Real-Time Clock...................................................................................9-18  
Configuring a Square-Wave Generator......................................................................9-21  
Configuring a Digital One-Shot...................................................................................9-22  
Initializing the DMA Unit ...........................................................................................10-23  
Timed DMA Transfers ..............................................................................................10-26  
Initialization Sequence for 80C187 Math Coprocessor ............................................11-15  
Floating Point Math Routine Using FSINCOS..........................................................11-16  
xvi  
1
Introduction  
CHAPTER 1  
INTRODUCTION  
The 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcom-  
puter engine of choice. There are literally millions of 8086/8088-based systems in the world to-  
day. The amount of software written for the 8086/8088 is rivaled by no other architecture.  
By the early 1980’s, however, it was clear that a replacement for the 8086/8088 was necessary.  
An 8086/8088 system required dozens of support chips to implement even a moderately complex  
design. Intel recognized the need to integrate commonly used system peripherals onto the same  
silicon die as the CPU. In 1982 Intel addressed this need by introducing the 80186/80188 family  
of embedded microprocessors. The original 80186/80188 integrated an enhanced 8086/8088  
CPU with six commonly used system peripherals. A parallel effort within Intel also gave rise to  
the 80286 microprocessor in 1982. The 80286 began the trend toward the very high performance  
Intel architecture that today includes the Intel386 , Intel486 and Pentium microprocessors.  
As technology advanced and turned toward small geometry CMOS processes, it became clear  
that a new 80186 was needed. In 1987 Intel announced the second generation of the 80186 family:  
the 80C186/C188. The 80C186 family is pin compatible with the 80186 family, while adding an  
enhanced feature set. The high-performance CHMOS III process allowed the 80C186 to run at  
twice the clock rate of the NMOS 80186, while consuming less than one-fourth the power.  
The 80186 family took another major step in 1990 with the introduction of the 80C186EB family.  
The 80C186EB heralded many changes for the 80186 family. First, the enhanced 8086/8088 CPU  
was redesigned as a static, stand-alone module known as the 80C186 Modular Core. Second, the  
80186 family peripherals were also redesigned as static modules with standard interfaces. The  
goal behind this redesign effort was to give Intel the capability to proliferate the 80186 family  
rapidly, in order to provide solutions for an even wider range of customer applications.  
The 80C186EB/C188EB was the first product to use the new modular capability. The  
80C186EB/C188EB includes a different peripheral set than the original 80186 family. Power  
consumption was dramatically reduced as a direct result of the static design, power management  
features and advanced CHMOS IV process. The 80C186EB/C188EB has found acceptance in a  
wide array of portable equipment ranging from cellular phones to personal organizers.  
In 1991 the 80C186 Modular Core family was again extended with the introduction of three new  
products: the 80C186XL, the 80C186EA and the 80C186EC. The 80C186XL/C188XL is a high-  
er performance, lower power replacement for the 80C186/C188. The 80C186EA/C188EA com-  
bines the feature set of the 80C186 with new power management features for power-critical  
applications. The 80C186EC/C188EC offers the highest level of integration of any of the 80C186  
Modular Core family products, with 14 on-chip peripherals (see Table 1-1).  
1-1  
INTRODUCTION  
The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers  
the designer the peace of mind of a well-established architecture with the benefits of state-of-the-  
art technology.  
Table 1-1. Comparison of 80C186 Modular Core Family Products  
Feature  
80C186XL  
80C186EA  
80C186EB  
80C186EC  
Enhanced 8086 Instruction Set  
Low-Power Static Modular CPU  
Power-Save (Clock Divide) Mode  
Powerdown and Idle Modes  
80C187 Interface  
ONCE Mode  
Interrupt Control Unit  
8259  
Compatible  
Timer/Counter Unit  
Chip-Select Unit  
DMA Unit  
Enhanced  
Enhanced  
4 Channel  
2 Channel  
2 Channel  
Serial Communications Unit  
Refresh Control Unit  
Watchdog Timer Unit  
I/O Ports  
Enhanced  
16 Total  
Enhanced  
22 Total  
1.1 HOW TO USE THIS MANUAL  
This manual uses phrases such as 80C186 Modular Core Family or 80C188 Modular Core, as  
well as references to specific products such as 80C188EA. Each phrase refers to a specific set of  
80C186 family products. The phrases and the products they refer to are as follows:  
80C186 Modular Core Family: This phrase refers to any device that uses the modular  
80C186/C188 CPU core architecture. At this time these include the 80C186EA/C188EA,  
80C186EB/C188EB, 80C186EC/C188EC and 80C186XL/C188XL.  
80C186 Modular Core: Without the word family, this phrase refers only to the 16-bit bus mem-  
bers of the 80C186 Modular Core Family.  
80C188 Modular Core: This phrase refers to the 8-bit bus products.  
80C188EC: A specific product reference refers only to the named device. For example, On the  
80C188EC… refers strictly to the 80C188EC and not to any other device.  
1-2  
 
INTRODUCTION  
Each chapter covers a specific section of the device, beginning with the CPU core. Each periph-  
eral chapter includes programming examples intended to aid in your understanding of device op-  
eration. Please read the comments carefully, as not all of the examples include all the code  
necessary for a specific application.  
This user’s guide is a supplement to the device data sheet. Specific timing values are not dis-  
cussed in this guide. When designing a system, always consult the most recent version of the de-  
vice data sheet for up-to-date specifications.  
1.2 RELATED DOCUMENTS  
The following table lists documents and software that are useful in designing systems that incor-  
porate the 80C186 Modular Core Family. These documents are available through Intel Literature.  
To order a document, call the number listed for your area in “Product Literature” on page 1-7.  
NOTE  
If you will be transferring a design from the 80186/80188 or 80C186/80C188  
to the 80C186XL/80C188XL, refer to FaxBack Document No. 2132.  
Table 1-2. Related Documents and Software  
Document  
Document/Software Title  
Order No.  
Embedded Microprocessors (includes 186 family data sheets)  
186 Embedded Microprocessor Line Card  
272396  
272079  
272430  
272431  
80186/80188 High-Integration 16-Bit Microprocessor Data Sheet  
80C186XL/C188XL-20, -12 16-Bit High-Integration Embedded Microprocessor  
Data Sheet  
80C186EA/80C188EA-20, -12 and 80L186EA/80L188EA-13, -8 (low power  
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet  
272432  
272433  
272434  
80C186EB/80C188EB-20, -13 and 80L186EB/80L188EB-13, -8 (low power  
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet  
80C186EC/80C188EC-20, -13 and 80L186EC/80L188EC-13, -8 (low power  
versions) 16-Bit High-Integration Embedded Microprocessor Data Sheet  
80C187 80-Bit Math Coprocessor Data Sheet  
270640  
272324  
272164  
270950  
270830  
272047  
231017  
240487  
Low Voltage Embedded Design  
80C186/C188, 80C186XL/C188XL Microprocessor User’s Manual  
80C186EA/80C188EA Microprocessor User’s Manual  
80C186EB/80C188EB Microprocessor User’s Manual  
80C186EC/80C188EC Microprocessor User’s Manual  
8086/8088/8087/80186/80188 Programmer’s Pocket Reference Guide  
8086/8088 User’s Manual Programmer’s and Hardware Reference Manual  
1-3  
INTRODUCTION  
Table 1-2. Related Documents and Software (Continued)  
Document/Software Title  
Document  
Order No.  
ApBUILDER Software  
272216  
272275  
80C186EA Hypertext Manual  
80C186EB Hypertext Manual  
80C186EC Hypertext Manual  
80C186XL Hypertext Manual  
ZCON - Z80 Code Converter  
272296  
272298  
272630  
Available on BBS  
1.3 ELECTRONIC SUPPORT SYSTEMS  
Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel  
also maintains several forums on CompuServe and offers a variety of information on the World  
Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical infor-  
mation whenever you need it.  
1.3.1 FaxBack Service  
FaxBack is an on-demand publishing system that sends documents to your fax machine. You can  
get product announcements, change notifications, product literature, device characteristics, de-  
sign recommendations, and quality and reliability information from FaxBack 24 hours a day, 7  
days a week.  
1-800-628-2283  
916-356-3105  
U.S. and Canada  
U.S., Canada, Japan, APac  
Europe  
44(0)1793-496646  
Think of the FaxBack service as a library of technical documents that you can access with your  
phone. Just dial the telephone number and respond to the system prompts. After you select a doc-  
ument, the system sends a copy to your fax machine.  
Each document has an order number and is listed in a subject catalog. The first time you use Fax-  
Back, you should order the appropriate subject catalogs to get a complete list of document order  
numbers. Catalogs are updated twice monthly. In addition, daily update catalogs list the title, sta-  
tus, and order number of each document that has been added, revised, or deleted during the past  
eight weeks. To recieve the update for a subject catalog, enter the subject catalog number fol-  
lowed by a zero. For example, for the complete microcontroller and flash catalog, request docu-  
ment number 2; for the daily update to the microcontroller and flash catalog, request document  
number 20.  
1-4  
 
INTRODUCTION  
The following catalogs and information are available at the time of publication:  
1. Solutions OEM subscription form  
2. Microcontroller and flash catalog  
3. Development tools catalog  
4. Systems catalog  
5. Multimedia catalog  
6. Multibus and iRMX® software catalog and BBS file listings  
7. Microprocessor, PCI, and peripheral catalog  
8. Quality and reliability and change notification catalog  
9. iAL (Intel Architecture Labs) technology catalog  
1.3.2 Bulletin Board System (BBS)  
The bulletin board system (BBS) lets you download files to your computer. The application BBS  
has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firm-  
ware upgrades, application notes and utilities, and quality and reliability data.  
916-356-3600  
U.S., Canada, Japan, APac (up to 19.2 Kbaud)  
U.S., Canada, Japan, APac (2400 baud only)  
Europe  
916-356-7209  
44(0)1793-496340  
The toll-free BBS (available in the U.S. and Canada) offers lists of documents available from  
FaxBack, a master list of files available from the application BBS, and a BBS user’s guide. The  
BBS file listing is also available from FaxBack (catalog number 6; see page 1-4 for phone num-  
bers and a description of the FaxBack service).  
1-800-897-2536  
U.S. and Canada only  
Any customer with a modem and computer can access the BBS. The system provides automatic  
configuration support for 1200- through 19200-baud modems. Typical modem settings are 14400  
baud, no parity, 8 data bits, and 1 stop bit (14400, N, 8, 1).  
To access the BBS, just dial the telephone number and respond to the system prompts. During  
your first session, the system asks you to register with the system operator by entering your name  
and location. The system operator will set up your access account within 24 hours. At that time,  
you can access the files on the BBS.  
NOTE  
If you encounter any difficulty accessing the high-speed modem, try the  
dedicated 2400-baud modem. Use these modem settings: 2400, N, 8, 1.  
1-5  
 
INTRODUCTION  
1.3.2.1  
How to Find ApBUILDER Software and Hypertext Documents on the BBS  
The latest ApBUILDER files and hypertext manuals and data sheets are available first from the  
BBS. To access the files, complete these steps:  
1. Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu.  
2. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area  
number.  
3. Type 25 and press <Enter> to select ApBUILDER/Hypertext. The BBS displays several  
options: one for ApBUILDER software and the others for hypertext documents for  
specific product families.  
4. Type 1 and press <Enter> to list the latest ApBUILDER files, or type the number of the  
appropriate product family sublevel and press <Enter> for a list of available hypertext  
manuals and datasheets.  
5. Type the file numbers to select the files you wish to download (for example, 1,6 for files 1  
and 6 or 3-7 for files 3, 4, 5, 6, and 7) and press <Enter>. The BBS displays the approx-  
imate time required to download the selected files and gives you the option to download  
them.  
1.3.3 CompuServe Forums  
The CompuServe forums provide a means for you to gather information, share discoveries, and  
debate issues. Type “go intel” for access. For information about CompuServe access and service  
fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).  
1.3.4 World Wide Web  
Intel offers a variety of information through the World Wide Web (http://www.intel.com/). Select  
“Embedded Design Products” from the Intel home page.  
1.4 TECHNICAL SUPPORT  
In the U.S. and Canada, technical support representatives are available to answer your questions  
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice  
telephone number and indicate whether you prefer a response by phone or by fax). Outside the  
U.S. and Canada, please contact your local distributor.  
1-800-628-8686  
916-356-7599  
U.S. and Canada  
U.S. and Canada  
U.S. and Canada  
916-356-6100 (fax)  
1-6  
INTRODUCTION  
1.5 PRODUCT LITERATURE  
You can order product literature from the following Intel literature centers.  
1-800-468-8118, ext. 283  
708-296-9333  
U.S. and Canada  
U.S. (from overseas)  
Europe (U.K.)  
Germany  
44(0)1793-431155  
44(0)1793-421333  
44(0)1793-421777  
81(0)120-47-88-32  
France  
Japan (fax only)  
1.6 TRAINING CLASSES  
In the U.S. and Canada, you can register for training classes through the Intel customer training  
center. Classes are held in the U.S.  
1-800-234-8806  
U.S. and Canada  
1-7  
 
2
Overview of the  
80C186 Family  
Architecture  
CHAPTER 2  
OVERVIEW OF THE 80C186 FAMILY  
ARCHITECTURE  
The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086,  
8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core  
maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors,  
while adding hardware and software performance enhancements. Most instructions require fewer  
clocks to execute on the 80C186 Modular Core because of hardware enhancements in the Bus  
Interface Unit and the Execution Unit. Several additional instructions simplify programming and  
reduce code size (see Appendix A, “80C186 Instruction Set Additions and Extensions”).  
2.1 ARCHITECTURAL OVERVIEW  
The 80C186 Modular Microprocessor Core incorporates two separate processing units: an Exe-  
cution Unit (EU) and a Bus Interface Unit (BIU). The Execution Unit is functionally identical  
among all family members. The Bus Interface Unit is configured for a 16-bit external data bus  
for the 80C186 core and an 8-bit external data bus for the 80C188 core. The two units interface  
via an instruction prefetch queue.  
The Execution Unit executes instructions; the Bus Interface Unit fetches instructions, reads op-  
erands and writes results. Whenever the Execution Unit requires another opcode byte, it takes the  
byte out of the prefetch queue. The two units can operate independently of one another and are  
able, under most circumstances, to overlap instruction fetches and execution.  
The 80C186 Modular Core family has a 16-bit Arithmetic Logic Unit (ALU). The Arithmetic  
Logic Unit performs 8-bit or 16-bit arithmetic and logical operations. It provides for data move-  
ment between registers, memory and I/O space.  
The 80C186 Modular Core family CPU allows for high-speed data transfer from one area of  
memory to another using string move instructions and between an I/O port and memory using  
block I/O instructions. The CPU also provides many conditional branch and control instructions.  
The 80C186 Modular Core architecture features 14 basic registers grouped as general registers,  
segment registers, pointer registers and status and control registers. The four 16-bit general-pur-  
pose registers (AX, BX, CX and DX) can be used as operands for most arithmetic operations as  
either 8- or 16-bit units. The four 16-bit pointer registers (SI, DI, BP and SP) can be used in arith-  
metic operations and in accessing memory-based variables. Four 16-bit segment registers (CS,  
DS, SS and ES) allow simple memory partitioning to aid modular programming. The status and  
control registers consist of an Instruction Pointer (IP) and the Processor Status Word (PSW) reg-  
ister, which contains flag bits. Figure 2-1 is a simplified CPU block diagram.  
2-1  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Address Bus (20 Bits)  
General  
Registers  
Σ
AH  
AL  
BL  
CL  
DL  
Data  
Bus  
BH  
CH  
DH  
(16 Bits)  
CS  
DS  
SS  
ES  
IP  
SP  
BP  
SI  
DI  
ALU Data Bus  
(16 Bits)  
Internal  
Communications  
Registers  
Temporary  
Registers  
Bus  
Control  
Logic  
External  
Bus  
Instruction Queue  
ALU  
EU  
Control  
1 2 3 4 5 6  
System  
Q Bus  
(8 Bits)  
Flags  
Execution Unit  
(EU)  
Bus Interface Unit  
(BIU)  
A1012-0A  
Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU  
2.1.1 Execution Unit  
The Execution Unit executes all instructions, provides data and addresses to the Bus Interface  
Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within  
the Execution Unit maintains the CPU status and control flags and manipulates the general reg-  
isters and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide  
for fast internal transfers.  
2-2  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
The Execution Unit does not connect directly to the system bus. It obtains instructions from a  
queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a  
peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Ad-  
dresses manipulated by the Execution Unit are 16 bits wide. The Bus Interface Unit, however,  
performs an address calculation that allows the Execution Unit to access the full megabyte of  
memory space.  
To execute an instruction, the Execution Unit must first fetch the object code byte from the in-  
struction queue and then execute the instruction. If the queue is empty when the Execution Unit  
is ready to fetch an instruction byte, the Execution Unit waits for the Bus Interface Unit to fetch  
the instruction byte.  
2.1.2 Bus Interface Unit  
The 80C186 Modular Core and 80C188 Modular Core Bus Interface Units are functionally iden-  
tical. They are implemented differently to match the structure and performance characteristics of  
their respective system buses. The Bus Interface Unit executes all external bus cycles. This unit  
consists of the segment registers, the Instruction Pointer, the instruction code queue and several  
miscellaneous registers. The Bus Interface Unit transfers data to and from the Execution Unit on  
the ALU data bus.  
The Bus Interface Unit generates a 20-bit physical address in a dedicated adder. The adder shifts  
a 16-bit segment value left 4 bits and then adds a 16-bit offset. This offset is derived from com-  
binations of the pointer registers, the Instruction Pointer and immediate values (see Figure 2-2).  
Any carry from this addition is ignored.  
Shift left 4 bits  
1
2
0
3
2
4
0
Segment Base  
Offset  
15  
Logical  
Address  
0
2
0
1
2
3
0
3
4
2
6
0
0
15  
19  
+
0
2
0
15  
= 1  
19  
2
2
0
Physical Address  
To Memory  
A1500-0A  
Figure 2-2. Physical Address Generation  
2-3  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit  
sequentially prefetches instructions from memory. As long as the prefetch queue is partially full,  
the Execution Unit fetches instructions.  
2.1.3 General Registers  
The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The  
general registers are subdivided into two sets of four registers. These sets are the data registers  
(also called the H & L group for high and low) and the pointer and index registers (also called the  
P & I group).  
H
L
15  
8
7
0
AX  
Accumulator  
Base  
AH  
BH  
CH  
DH  
AL  
BL  
CL  
DL  
BX  
CX  
DX  
Data  
Group  
Count  
Data  
SP  
BP  
SI  
Stack Pointer  
Base Pointer  
Pointer  
and  
Index  
Group  
Source Index  
Destination Index  
DI  
A1033-0A  
Figure 2-3. General Registers  
2-4  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
The data registers can be addressed by their upper or lower halves. Each data register can be used  
interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always access-  
ed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and log-  
ic operations. Arithmetic and logic operations can also use the pointer and index registers. Some  
instructions use certain registers implicitly (see Table 2-1), allowing compact encoding.  
Table 2-1. Implicit Use of General Registers  
Register  
Operations  
AX  
AL  
AH  
BX  
CX  
CL  
DX  
SP  
SI  
Word Multiply, Word Divide, Word I/O  
Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal Arithmetic  
Byte Multiply, Byte Divide  
Translate  
String Operations, Loops  
Variable Shift and Rotate  
Word Multiply, Word Divide, Indirect I/O  
Stack Operations  
String Operations  
DI  
String Operations  
The contents of the general-purpose registers are undefined following a processor reset.  
2.1.4 Segment Registers  
The 80C186 Modular Core family memory space is 1 Mbyte in size and divided into logical seg-  
ments of up to 64 Kbytes each. The CPU has direct access to four segments at a time. The segment  
registers contain the base addresses (starting locations) of these memory segments (see Figure  
2-4). The CS register points to the current code segment, which contains instructions to be  
fetched. The SS register points to the current stack segment, which is used for all stack operations.  
The DS register points to the current data segment, which generally contains program variables.  
The ES register points to the current extra segment, which is typically used for data storage. The  
CS register initializes to 0FFFFH, and the SS, DS and ES registers initialize to 0000H. Programs  
can access and manipulate the segment registers with several instructions.  
2-5  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
15  
0
CS  
DS  
SS  
ES  
Code Segment  
Data Segment  
Stack Segment  
Extra Segment  
Figure 2-4. Segment Registers  
2.1.5 Instruction Pointer  
The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset  
of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer,  
but it can change, be saved or be restored as a result of program execution. For example, if the  
Instruction Pointer is saved on the stack, it is first automatically adjusted to point to the next in-  
struction to be executed.  
Reset initializes the Instruction Pointer to 0000H. The CS and IP values comprise a starting exe-  
cution address of 0FFFF0H (see “Logical Addresses” on page 2-10 for a description of address  
formation).  
2-6  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.1.6 Flags  
The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit  
posts as the result of arithmetic or logical operations. Program branch instructions allow a pro-  
gram to alter its execution depending on conditions flagged by a prior operation. Different in-  
structions affect the status flags differently, generally reflecting the following states:  
If the Auxiliary Flag (AF) is set, there has been a carry out from the low nibble into the high  
nibble or a borrow from the high nibble into the low nibble of an 8-bit quantity (low-order  
byte of a 16-bit quantity). This flag is used by decimal arithmetic instructions.  
If the Carry Flag (CF) is set, there has been a carry out of or a borrow into the high-order bit  
of the instruction result (8- or 16-bit). This flag is used by instructions that add or subtract  
multibyte numbers. Rotate instructions can also isolate a bit in memory or a register by  
placing it in the Carry Flag.  
If the Overflow Flag (OF) is set, an arithmetic overflow has occurred. A significant digit  
has been lost because the size of the result exceeded the capacity of its destination location.  
An Interrupt On Overflow instruction is available that will generate an interrupt in this  
situation.  
If the Sign Flag (SF) is set, the high-order bit of the result is a 1. Since negative binary  
numbers are represented in standard two’s complement notation, SF indicates the sign of  
the result (0 = positive, 1 = negative).  
If the Parity Flag (PF) is set, the result has even parity, an even number of 1 bits. This flag  
can be used to check for data transmission errors.  
If the Zero Flag (ZF) is set, the result of the operation is zero.  
Additional control flags (see Figure 2-5) can be set or cleared by programs to alter processor op-  
erations:  
Setting the Direction Flag (DF) causes string operations to auto-decrement. Strings are  
processed from high address to low address (or “right to left”). Clearing DF causes string  
operations to auto-increment. Strings are processed from low address to high address (or  
“left to right”).  
Setting the Interrupt Enable Flag (IF) allows the CPU to recognize maskable external or  
internal interrupt requests. Clearing IF disables these interrupts. The Interrupt Enable Flag  
has no effect on software interrupts or non-maskable interrupts.  
Setting the Trap Flag (TF) bit puts the processor into single-step mode for debugging. In  
this mode, the CPU automatically generates an interrupt after each instruction. This allows  
a program to be inspected instruction by instruction during execution.  
The status and control flags are contained in a 16-bit Processor Status Word (see Figure 2-5). Re-  
set initializes the Processor Status Word to 0F000H.  
2-7  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.1.7 Memory Segmentation  
Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of  
user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long.  
Each segment is composed of contiguous memory locations. Segments are independent and sep-  
arately addressable. Software assigns every segment a base address (starting location) in memory  
space. All segments begin on 16-byte memory boundaries. There are no other restrictions on seg-  
ment locations. Segments can be adjacent, disjoint, partially overlapped or fully overlapped (see  
Figure 2-6). A physical memory location can be mapped into (covered by) one or more logical  
segments.  
2-8  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Register Name:  
Processor Status Word  
PSW (FLAGS)  
Register Mnemonic:  
Register Function:  
Posts CPU status information.  
15  
0
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
A1035-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
OF  
Overflow Flag  
0
If OF is set, an arithmetic overflow has occurred.  
If DF is set, string instructions are processed high  
address to low address. If DF is clear, strings are  
processed low address to high address.  
DF  
IF  
Direction Flag  
0
If IF is set, the CPU recognizes maskable interrupt  
requests. If IF is clear, maskable interrupts are  
ignored.  
Interrupt  
Enable Flag  
0
TF  
SF  
ZF  
Trap Flag  
Sign Flag  
Zero Flag  
0
0
0
If TF is set, the processor enters single-step mode.  
If SF is set, the high-order bit of the result of an  
operation is 1, indicating it is negative.  
If ZF is set, the result of an operation is zero.  
If AF is set, there has been a carry from the low  
nibble to the high or a borrow from the high nibble  
to the low nibble of an 8-bit quantity. Used in BCD  
operations.  
AF  
Auxiliary Flag  
0
If PF is set, the result of an operation has even  
parity.  
PF  
CF  
Parity Flag  
Carry Flag  
0
0
If CF is set, there has been a carry out of, or a  
borrow into, the high-order bit of the result of an  
instruction.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 2-5. Processor Status Word  
2-9  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Fully  
Overlapped  
Partly  
Overlapped  
Segment D  
Disjoint  
Logical  
Segments  
Contiguous  
Segment C  
Segment E  
Segment A  
Segment B  
Physical  
Memory  
0H  
10000H  
20000H  
30000H  
A1036-0A  
Figure 2-6. Segment Locations in Physical Memory  
The four segment registers point to four “currently addressable” segments (see Figure 2-7). The  
currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64  
Kbytes for stack and 128 Kbytes for data storage. Programs access code and data in another seg-  
ment by updating the segment register to point to the new segment.  
2.1.8 Logical Addresses  
It is useful to think of every memory location as having two kinds of addresses, physical and log-  
ical. A physical address is a 20-bit value that identifies a unique byte location in the memory  
space. Physical addresses range from 0H to 0FFFFFH. All exchanges between the CPU and  
memory use physical addresses.  
Programs deal with logical rather than physical addresses. Program code can be developed with-  
out prior knowledge of where the code will be located in memory. A logical address consists of  
a segment base value and an offset value. For any given memory location, the segment base value  
locates the first byte of the segment. The offset value represents the distance, in bytes, of the tar-  
get location from the beginning of the segment. Segment base and offset values are unsigned 16-  
bit quantities. Many different logical addresses can map to the same physical location. In Figure  
2-8, physical memory location 2C3H is contained in two different overlapping segments, one be-  
ginning at 2B0H and the other at 2C0H.  
2-10  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
FFFFFH  
A
B
Data:  
Code:  
Stack:  
Extra:  
DS:  
CS:  
SS:  
ES:  
B
C
E
D
H
E
J
F
G
H
I
J
K
0H  
A1037-0A  
Figure 2-7. Currently Addressable Segments  
The segment register is automatically selected according to the rules in Table 2-2. All information  
in one segment type generally shares the same logical attributes (e.g., code or data). This leads to  
programs that are shorter, faster and better structured.  
The Bus Interface Unit must obtain the logical address before generating the physical address.  
The logical address of a memory location can come from different sources, depending on the type  
of reference that is being made (see Table 2-2).  
Segment registers always hold the segment base addresses. The Bus Interface Unit determines  
which segment register contains the base address according to the type of memory reference  
made. However, the programmer can explicitly direct the Bus Interface Unit to use any currently  
addressable segment (except for the destination operand of a string instruction). In assembly lan-  
guage, this is done by preceding an instruction with a segment override prefix.  
2-11  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2C4H  
2C3H  
2C2H  
2C1H  
2C0H  
2BFH  
2BEH  
2BDH  
2BCH  
2BBH  
2BAH  
2B9H  
2B8H  
2B7H  
2B6H  
2B5H  
2B4H  
2B3H  
2B2H  
2B1H  
2B0H  
Physical  
Address  
Offset  
(3H)  
Segment  
Base  
Offset  
(13H)  
Logical  
Addresses  
Segment  
Base  
A1038-0A  
Figure 2-8. Logical and Physical Address  
2-12  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Table 2-2. Logical Address Sources  
Default  
Segment Base  
Alternate  
Segment Base  
Type of Memory Reference  
Offset  
Instruction Fetch  
CS  
SS  
DS  
DS  
ES  
SS  
NONE  
NONE  
IP  
Stack Operation  
SP  
Variable (except following)  
String Source  
CS, ES, SS  
CS, ES, SS  
NONE  
Effective Address  
SI  
DI  
String Destination  
BP Used as Base Register  
CS, DS, ES  
Effective Address  
Instructions are always fetched from the current code segment. The IP register contains the in-  
struction’s offset from the beginning of the segment. Stack instructions always operate on the cur-  
rent stack segment. The Stack Pointer (SP) register contains the offset of the top of the stack from  
the base of the stack. Most variables (memory operands) are assumed to reside in the current data  
segment, but a program can instruct the Bus Interface Unit to override this assumption. Often, the  
offset of a memory variable is not directly available and must be calculated at execution time. The  
addressing mode specified in the instruction determines how this offset is calculated (see “Ad-  
dressing Modes” on page 2-27). The result is called the operand’s Effective Address (EA).  
Strings are addressed differently than other variables. The source operand of a string instruction  
is assumed to lie in the current data segment. However, the program can use another currently  
addressable segment. The operand’s offset is taken from the Source Index (SI) register. The des-  
tination operand of a string instruction always resides in the current extra segment. The destina-  
tion’s offset is taken from the Destination Index (DI) register. The string instructions  
automatically adjust the SI and DI registers as they process the strings one byte or word at a time.  
When an instruction designates the Base Pointer (BP) register as a base register, the variable is  
assumed to reside in the current stack segment. The BP register provides a convenient way to ac-  
cess data on the stack. The BP register can also be used to access data in any other currently ad-  
dressable segment.  
2.1.9 Dynamically Relocatable Code  
The segmented memory structure of the 80C186 Modular Core family allows creation of dynam-  
ically relocatable (position-independent) programs. Dynamic relocation allows a multiprogram-  
ming or multitasking system to make effective use of available memory. The processor can write  
inactive programs to a disk and reallocate the space they occupied to other programs. A disk-res-  
ident program can then be read back into available memory locations and restarted whenever it  
is needed. If a program needs a large contiguous block of storage and the total amount is available  
only in non-adjacent fragments, other program segments can be compacted to free enough con-  
tinuous space. This process is illustrated in Figure 2-9.  
2-13  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Before  
After  
Relocation  
Relocation  
Code  
Segment  
CS  
SS  
CS  
SS  
Stack  
Segment  
DS  
ES  
DS  
ES  
Code  
Segment  
Data  
Segment  
Stack  
Segment  
Data  
Segment  
Extra  
Segment  
Extra  
Segment  
Free Space  
A1039-0A  
Figure 2-9. Dynamic Code Relocation  
To be dynamically relocatable, a program must not load or alter its segment registers and must  
not transfer directly to a location outside the current code segment. All program offsets must be  
relative to the segment registers. This allows the program to be moved anywhere in memory, pro-  
vided that the segment registers are updated to point to the new base addresses.  
2-14  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.1.10 Stack Implementation  
Stacks in the 80C186 Modular Core family reside in memory space. They are located by the Stack  
Segment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only  
one stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximum  
length of a segment. Growing a stack segment beyond 64 Kbytes overwrites the beginning of the  
segment. The SS register contains the base address of the current stack. The top of the stack, not  
the base address, is the origination point of the stack. The SP register contains an offset that points  
to the Top of Stack (TOS).  
Stacks are 16 bits wide. Instructions operating on a stack add and remove stack elements one  
word at a time. An element is pushed onto the stack (see Figure 2-10) by first decrementing the  
SP register by 2 and then writing the data word. An element is popped off the stack by copying  
it from the top of the stack and then incrementing the SP register by 2. The stack grows down in  
memory toward its base address. Stack operations never move or erase elements on the stack. The  
top of the stack changes only as a result of updating the stack pointer.  
2.1.11 Reserved Memory and I/O Space  
Two specific areas in memory and one area in I/O space are reserved in the 80C186 Core family.  
Locations 0H through 3FFH in low memory are used for the Interrupt Vector Table.  
Programs should not be loaded here.  
Locations 0FFFF0H through 0FFFFFH in high memory are used for system reset code  
because the processor begins execution at 0FFFF0H.  
Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intel  
hardware products and must not be used. On the 80C186 core, these addresses are used as  
I/O ports for the 80C187 numerics processor extension.  
2-15  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
POP AX  
POP BX  
10  
50  
PUSH AX  
Existing  
Stack  
12  
34  
BB AA  
1062 00  
11  
33  
55  
77  
99  
1062 00  
1060 22  
105E 44  
105B 66  
105A 88  
11  
33  
55  
77  
99  
1062 00  
11  
33  
55  
77  
99  
1060 22  
105E 44  
105B 66  
105A 88  
1060 22  
105E 44  
105B 66  
105A 88  
TOS  
TOS  
1058 AA BB  
1058 AA BB  
1058 AA BB  
TOS  
1056 01  
1054 45  
23  
67  
1056 34  
1054 45  
12  
67  
1056 34  
1054 45  
12  
67  
1052 89 AB  
1050 CD EF  
1052 89 AB  
1050 CD EF  
1052 89 AB  
1050 CD EF  
SS  
SP  
SS  
SP  
SS  
SP  
10  
00  
50  
08  
10  
00  
50  
06  
10  
50  
00 0A  
Stack operation for code sequence  
PUSH AX  
POP AX  
POP BX  
A1013-0A  
Figure 2-10. Stack Operation  
2-16  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.2 SOFTWARE OVERVIEW  
All 80C186 Modular Core family members execute the same instructions. This includes all the  
8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 In-  
struction Set Additions and Extensions”). The following sections describe the instructions by cat-  
egory and provide a detailed discussion of the operand addressing modes.  
Software for 80C186 core family systems need not be written in assembly language. The proces-  
sor provides direct hardware support for programs written in the many high-level languages  
available. The hardware addressing modes provide straightforward implementations of based  
variables, arrays, arrays of structures and other high-level language data constructs. A powerful  
set of memory-to-memory string operations allow efficient character data manipulation. Finally,  
routines with critical performance requirements can be written in assembly language and linked  
with high-level code.  
2.2.1 Instruction Set  
The 80C186 Modular Core family instructions treat different types of operands uniformly. Nearly  
every instruction can operate on either byte or word data. Register, memory and immediate op-  
erands can be specified interchangeably in most instructions. Immediate values are exceptions:  
they must serve as source operands and not destination operands. Memory variables can be ma-  
nipulated (added to, subtracted from, shifted, compared) without being moved into and out of reg-  
isters. This saves instructions, registers and execution time in assembly language programs. In  
high-level languages, where most variables are memory-based, compilers can produce faster and  
shorter object programs.  
The 80C186 Modular Core family instruction set can be viewed as existing on two levels. One is  
the assembly level and the other is the machine level. To the assembly language programmer, the  
80C186 Modular Core family appears to have about 100 instructions. One MOV (data move) in-  
struction, for example, transfers a byte or a word from a register, a memory location or an imme-  
diate value to either a register or a memory location. The 80C186 Modular Core family CPUs,  
however, recognize 28 different machine versions of the MOV instruction.  
The two levels of instruction sets address two requirements: efficiency and simplicity. Approxi-  
mately 300 forms of machine-level instructions make very efficient use of storage. For example,  
the machine instruction that increments a memory operand is three or four bytes long because the  
address of the operand must be encoded in the instruction. Incrementing a register, however, re-  
quires less information, so the instruction can be shorter. The 80C186 Core family has eight sin-  
gle-byte machine-level instructions that increment different 16-bit registers.  
The assembly level instructions simplify the programmer’s view of the instruction set. The pro-  
grammer writes one form of an INC (increment) instruction and the assembler examines the op-  
erand to determine which machine level instruction to generate. The following paragraphs  
provide a functional description of the assembly-level instructions.  
2-17  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.2.1.1  
Data Transfer Instructions  
The instruction set contains 14 data transfer instructions. These instructions move single bytes  
and words between memory and registers. They also move single bytes and words between the  
AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and  
their functions.  
Table 2-3. Data Transfer Instructions  
General-Purpose  
MOV  
Move byte or word  
PUSH  
POP  
Push word onto stack  
Pop word off stack  
PUSHA  
POPA  
XCHG  
XLAT  
Push registers onto stack  
Pop registers off stack  
Exchange byte or word  
Translate byte  
Input/Output  
IN  
Input byte or word  
Output byte or word  
OUT  
Address Object and Stack Frame  
LEA  
Load effective address  
Load pointer using DS  
Load pointer using ES  
Build stack frame  
LDS  
LES  
ENTER  
LEAVE  
Tear down stack frame  
Flag Transfer  
LAHF  
Load AH register from flags  
Store AH register in flags  
Push flags from stack  
Pop flags off stack  
SAHF  
PUSHF  
POPF  
Data transfer instructions are categorized as general purpose, input/output, address object and  
flag transfer. The stack manipulation instructions, used for transferring flag contents and instruc-  
tions used for loading segment registers are also included in this group. Figure 2-11 shows the  
flag storage formats. The address object instructions manipulate the addresses of variables in-  
stead of the values of the variables.  
2-18  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
LAHF  
SAHF  
S Z U A U P U C  
7 6 5 4 3 2 1 0  
PUSHF  
POPF  
U U U U O D I T S Z U A U P U C  
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  
U = Undefined; Value is indeterminate  
O = Overflow Flag  
D = Direction Flag  
I = Interrupt Enable Flag  
T = Trap Flag  
S = Sign Flag  
Z = Zero Flag  
A = Auxiliary Carry Flag  
P = Parity Flag  
C = Carry Flag  
A1014-0A  
Figure 2-11. Flag Storage Format  
2.2.1.2  
Arithmetic Instructions  
The arithmetic instructions (see Table 2-4) operate on four types of numbers:  
Unsigned binary  
Signed binary (integers)  
Unsigned packed decimal  
Unsigned unpacked decimal  
2-19  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Table 2-5 shows the interpretations of various bit patterns according to number type. Binary num-  
bers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed  
decimal and one digit per byte for unpacked decimal. The processor assumes that the operands in  
arithmetic instructions contain data that represents valid numbers for that instruction. Invalid data  
may produce unpredictable results. The Execution Unit analyzes the results of arithmetic instruc-  
tions and adjusts status flags accordingly.  
Table 2-4. Arithmetic Instructions  
Addition  
ADD  
ADC  
INC  
Add byte or word  
Add byte or word with carry  
Increment byte or word by 1  
ASCII adjust for addition  
Decimal adjust for addition  
AAA  
DAA  
Subtraction  
SUB  
SBB  
DEC  
NEG  
CMP  
AAS  
DAS  
Subtract byte or word  
Subtract byte or word with borrow  
Decrement byte or word by 1  
Negate byte or word  
Compare byte or word  
ASCII adjust for subtraction  
Decimal adjust for subtraction  
Multiplication  
MUL  
IMUL  
AAM  
Multiply byte or word unsigned  
Integer multiply byte or word  
ASCII adjust for multiplication  
Division  
DIV  
Divide byte or word unsigned  
Integer divide byte or word  
ASCII adjust for division  
Convert byte to word  
IDIV  
AAD  
CBW  
CWD  
Convert word to double-word  
2-20  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Table 2-5. Arithmetic Interpretation of 8-Bit Numbers  
Unsigned  
Binary  
Signed  
Binary  
Unpacked  
Decimal  
Packed  
Decimal  
Hex  
Bit Pattern  
07  
89  
C5  
0 0 0 0 0 1 1 1  
1 0 0 0 1 0 0 1  
1 1 0 0 0 1 0 1  
7
+7  
7
7
137  
197  
–119  
–59  
invalid  
89  
invalid  
2.2.1.3  
Bit Manipulation Instructions  
There are three groups of instructions for manipulating bits within bytes and words. These three  
groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their  
functions.  
Table 2-6. Bit Manipulation Instructions  
Logicals  
NOT  
AND  
OR  
“Not” byte or word  
“And” byte or word  
“Inclusive or” byte or word  
“Exclusive or” byte or word  
“Test” byte or word  
XOR  
TEST  
Shifts  
SHL/SAL  
SHR  
Shift logical/arithmetic left byte or word  
Shift logical right byte or word  
SAR  
Shift arithmetic right byte or word  
Rotates  
ROL  
ROR  
RCL  
RCR  
Rotate left byte or word  
Rotate right byte or word  
Rotate through carry left byte or word  
Rotate through carry right byte or word  
Logical instructions include the Boolean operators NOT, AND, OR and exclusive OR (XOR), as  
well as a TEST instruction. The TEST instruction sets the flags as a result of a Boolean AND op-  
eration but does not alter either of its operands.  
Individual bits in bytes and words can be shifted either arithmetically or logically. Up to 32 shifts  
can be performed, according to the value of the count operand coded in the instruction. The count  
can be specified as an immediate value or as a variable in the CL register. This allows the shift  
count to be a supplied at execution time. Arithmetic shifts can be used to multiply and divide bi-  
nary numbers by powers of two. Logical shifts can be used to isolate bits in bytes or words.  
2-21  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Individual bits in bytes and words can also be rotated. The processor does not discard the bits ro-  
tated out of an operand. The bits circle back to the other end of the operand. The number of bits  
to be rotated is taken from the count operand, which can specify either an immediate value or the  
CL register. The carry flag can act as an extension of the operand in two of the rotate instructions.  
This allows a bit to be isolated in the Carry Flag (CF) and then tested by a JC (jump if carry) or  
JNC (jump if not carry) instruction.  
2.2.1.4  
String Instructions  
Five basic string operations process strings of bytes or words, one element (byte or word) at a  
time. Strings of up to 64 Kbytes can be manipulated with these instructions. Instructions are avail-  
able to move, compare or scan for a value, as well as to move string elements to and from the  
accumulator. Table 2-7 lists the string instructions. These basic operations can be preceded by a  
one-byte prefix that causes the instruction to be repeated by the hardware, allowing long strings  
to be processed much faster than is possible with a software loop. The repetitions can be termi-  
nated by a variety of conditions. Repeated operations can be interrupted and resumed.  
Table 2-7. String Instructions  
REP  
Repeat  
REPE/REPZ  
REPNE/REPNZ  
MOVSB/MOVSW  
MOVS  
Repeat while equal/zero  
Repeat while not equal/not zero  
Move byte string/word string  
Move byte or word string  
Input byte or word string  
Output byte or word string  
Compare byte or word string  
Scan byte or word string  
Load byte or word string  
Store byte or word string  
INS  
OUTS  
CMPS  
SCAS  
LODS  
STOS  
String instructions operate similarly in many respects (see Table 2-8). A string instruction can  
have a source operand, a destination operand, or both. The hardware assumes that a source string  
resides in the current data segment. A segment prefix can override this assumption. A destination  
string must be in the current extra segment. The assembler does not use the operand names to ad-  
dress strings. Instead, the contents of the Source Index (SI) register are used as an offset to address  
the current element of the source string. The contents of the Destination Index (DI) register are  
taken as the offset of the current destination string element. These registers must be initialized to  
point to the source and destination strings before executing the string instructions. The LDS, LES  
and LEA instructions are useful in performing this function.  
2-22  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
String instructions automatically update the SI register, the DI register, or both, before processing  
the next string element. The Direction Flag (DF) determines whether the index registers are auto-  
incremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both  
registers by one for byte strings or by two for word strings.  
If a repeat prefix is used, the count register (CX) is decremented by one after each repetition of  
the string instruction. The CX register must be initialized to the number of repetitions before the  
string instruction is executed. If the CX register is 0, the string instruction is not executed and  
control goes to the following instruction.  
Table 2-8. String Instruction Register and Flag Use  
SI  
Index (offset) for source string  
Index (offset) for destination string  
Repetition counter  
DI  
CX  
AL/AX  
Scan value  
Destination for LODS  
Source for STOS  
DF  
ZF  
Direction Flag  
0 = auto-increment SI, DI  
1 = auto-decrement SI, DI  
Scan/compare terminator  
2.2.1.5  
Program Transfer Instructions  
The contents of the Code Segment (CS) and Instruction Pointer (IP) registers determine the in-  
struction execution sequence in the 80C186 Modular Core family. The CS register contains the  
base address of the current code segment. The Instruction Pointer register points to the memory  
location of the next instruction to be fetched. In most operating conditions, the next instruction  
will already have been fetched and will be waiting in the CPU instruction queue. Program transfer  
instructions operate on the IP and CS registers. Changing the contents of these registers causes  
normal sequential operation to be altered. When a program transfer occurs, the queue no longer  
contains the correct instruction. The Bus Interface Unit obtains the next instruction from memory  
using the new IP and CS values. It then passes the instruction directly to the Execution Unit and  
begins refilling the queue from the new location.  
The 80C186 Modular Core family offers four groups of program transfer instructions (see Table  
2-9). These are unconditional transfers, conditional transfers, iteration control instructions and in-  
terrupt-related instructions.  
2-23  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Unconditional transfer instructions can transfer control either to a target instruction within the  
current code segment (intrasegment transfer) or to a different code segment (intersegment trans-  
fer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans-  
fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and  
JMP are all unconditional transfers.  
CALL is used to transfer the program to a procedure. A CALL can be NEAR or FAR. A NEAR  
CALL stacks only the Instruction Pointer, while a FAR CALL stacks both the Instruction Pointer  
and the Code Segment register. The RET instruction uses the information pushed onto the stack  
to determine where to return when the procedure finishes. Note that the RET and CALL instruc-  
tions must be the same type. This can be a problem when the CALL and RET instructions are in  
separately assembled programs. The JMP instruction does not push any information onto the  
stack. A JMP instruction can be NEAR or FAR.  
Conditional transfer instructions are jumps that may or may not transfer control, depending on  
the state of the CPU flags when the instruction is executed. Each conditional transfer instruction  
tests a different combination of flags for a condition (see Table 2-10). If the condition is logically  
TRUE, control is transferred to the target specified in the instruction. If the condition is FALSE,  
control passes to the instruction following the conditional jump. All conditional jumps are  
SHORT. The target must be in the current code segment within –128 to +127 bytes of the next  
instruction’s first byte. For example, JMP 00H causes a jump to the first byte of the next instruc-  
tion. Jumps are made by adding the relative displacement of the target to the Instruction Pointer.  
All conditional jumps are self-relative and are appropriate for position-independent routines.  
2-24  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Table 2-9. Program Transfer Instructions  
Conditional Transfers  
Jump if above/not below nor equal  
JA/JNBE  
JAE/JNB  
JB/JNAE  
JBE/JNA  
JC  
Jump if above or equal/not below  
Jump if below/not above nor equal  
Jump if below or equal/not above  
Jump if carry  
JE/JZ  
Jump if equal/zero  
JG/JNLE  
JGE/JNL  
JL/JNGE  
JLE/JNG  
JNC  
Jump if greater/not less nor equal  
Jump if greater or equal/not less  
Jump if less/not greater nor equal  
Jump if less or equal/not greater  
Jump if not carry  
JNE/JNZ  
JNO  
Jump if not equal/not zero  
Jump if not overflow  
JNP/JPO  
JNS  
Jump if not parity/parity odd  
Jump if not sign  
JO  
Jump if overflow  
JP/JPE  
JS  
Jump if parity/parity even  
Jump if sign  
Unconditional Transfers  
CALL  
RET  
JMP  
Call procedure  
Return from procedure  
Jump  
Iteration Control  
LOOP  
Loop  
LOOPE/LOOPZ  
LOOPNE/LOOPNZ  
JCXZ  
Loop if equal/zero  
Loop if not equal/not zero  
Jump if register CX=0  
Interrupts  
INT  
Interrupt  
INTO  
BOUND  
IRET  
Interrupt if overflow  
Interrupt if out of array bounds  
Interrupt return  
2-25  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Iteration control instructions can be used to regulate the repetition of software loops. These in-  
structions use the CX register as a counter. Like the conditional transfers, the iteration control in-  
structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of  
themselves. They are SHORT transfers.  
The interrupt instructions allow programs and external hardware devices to activate interrupt ser-  
vice routines. The effect of a software interrupt is similar to that of a hardware-initiated interrupt.  
The processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in  
software or with an NMI (Non-Maskable Interrupt).  
Table 2-10. Interpretation of Conditional Transfers  
Mnemonic  
JA/JNBE  
Condition Tested  
(CF or ZF)=0  
“Jump if…”  
above/not below nor equal  
above or equal/not below  
below/not above nor equal  
below or equal/not above  
carry  
JAE/JNB  
JB/JNAE  
JBE/JNA  
JC  
CF=0  
CF=1  
(CF or ZF)=1  
CF=1  
JE/JZ  
ZF=1  
equal/zero  
JG/JNLE  
JGE/JNL  
JL/JNGE  
JLE/JNG  
JNC  
((SF xor OF) or ZF)=0  
(SF xor OF)=0  
(SF xor OF)=1  
((SF xor OF) or ZF)=1  
CF=0  
greater/not less nor equal  
greater or equal/not less  
less/not greater nor equal  
less or equal/not greater  
not carry  
JNE/JNZ  
JNO  
ZF=0  
not equal/not zero  
not overflow  
OF=0  
JNP/JPO  
JNS  
PF=0  
not parity/parity odd  
not sign  
SF=0  
JO  
OF=1  
overflow  
JP/JPE  
JS  
PF=1  
parity/parity equal  
sign  
SF=1  
NOTE: The terms above and below refer to the relationship of two unsigned values;  
greater and less refer to the relationship of two signed values.  
2-26  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.2.1.6  
Processor Control Instructions  
Processor control instructions (see Table 2-11) allow programs to control various CPU functions.  
Seven of these instructions update flags, four of them are used to synchronize the microprocessor  
with external events, and the remaining instruction causes the CPU to do nothing. Except for flag  
operations, processor control instructions do not affect the flags.  
Table 2-11. Processor Control Instructions  
Flag Operations  
STC  
CLC  
CMC  
STD  
CLD  
STI  
Set Carry flag  
Clear Carry flag  
Complement Carry flag  
Set Direction flag  
Clear Direction flag  
Set Interrupt Enable flag  
Clear Interrupt Enable flag  
CLI  
External Synchronization  
HLT  
Halt until interrupt or reset  
Wait for TEST pin active  
WAIT  
ESC  
Escape to external processor  
Lock bus during next instruction  
LOCK  
No Operation  
NOP  
No operation  
2.2.2 Addressing Modes  
The 80C186 Modular Core family members access instruction operands in several ways. Oper-  
ands can be contained either in registers, in the instruction itself, in memory or at I/O ports. Ad-  
dresses of memory and I/O port operands can be calculated in many ways. These addressing  
modes greatly extend the flexibility and convenience of the instruction set. The following para-  
graphs briefly describe register and immediate modes of operand addressing. A detailed descrip-  
tion of the memory and I/O addressing modes is also provided.  
2.2.2.1  
Register and Immediate Operand Addressing Modes  
Usually, the fastest, most compact operand addressing forms specify only register operands. This  
is because the register operand addresses are encoded in instructions in just a few bits and no bus  
cycles are run (the operation occurs within the CPU). Registers can serve as source operands, des-  
tination operands, or both.  
2-27  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Immediate operands are constant data contained in an instruction. Immediate data can be either  
8 or 16 bits in length. Immediate operands are available directly from the instruction queue and  
can be accessed quickly. As with a register operand, no bus cycles need to be run to get an imme-  
diate operand. Immediate operands can be only source operands and must have a constant value.  
2.2.2.2  
Memory Addressing Modes  
Although the Execution Unit has direct access to register and immediate operands, memory op-  
erands must be transferred to and from the CPU over the bus. When the Execution Unit needs to  
read or write a memory operand, it must pass an offset value to the Bus Interface Unit. The Bus  
Interface Unit adds the offset to the shifted contents of a segment register, producing a 20-bit  
physical address. One or more bus cycles are then run to access the operand.  
The offset that the Execution Unit calculates for memory operand is called the operand’s Effec-  
tive Address (EA). This address is an unsigned 16-bit number that expresses the operand’s dis-  
tance, in bytes, from the beginning of the segment in which it resides. The Execution Unit can  
calculate the effective address in several ways. Information encoded in the second byte of the in-  
struction tells the Execution Unit how to calculate the effective address of each memory operand.  
A compiler or assembler derives this information from the instruction written by the programmer.  
Assembly language programmers have access to all addressing modes.  
The Execution Unit calculates the Effective Address by summing a displacement, the contents of  
a base register and the contents of an index register (see Figure 2-12). Any combination of these  
can be present in a given instruction. This allows a variety of memory addressing modes.  
2-28  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Single Index  
Double Index  
BX  
or  
BX  
or  
SI  
or  
BP  
or  
BP  
DI  
Encoded  
in the  
Instruction  
+
SI  
EU  
or  
DI  
Explicit  
in the  
Instruction  
Effective  
Address  
+
+
Displacement  
0000  
CS  
or  
SS 0000  
or  
Assumed Unless  
Overridden  
by Prefix  
BIU  
DS 0000  
or  
+
+
ES 0000  
Physical Addr  
A1015-0A  
Figure 2-12. Memory Address Computation  
The displacement is an 8- or 16-bit number contained in the instruction. The displacement gen-  
erally is derived from the position of the operand’s name (a variable or label) in the program. The  
programmer can modify this value or explicitly specify the displacement.  
2-29  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
The BX or BP register can be specified as the base register for an effective address calculation.  
Similarly, either the SI or the DI register can be specified as the index register. The displacement  
value is a constant. The contents of the base and index registers can change during execution. This  
allows one instruction to access different memory locations depending upon the current values in  
the base or base and index registers. The default base register for effective address calculations  
with the BP register is SS, although DS or ES can be specified.  
Direct addressing is the simplest memory addressing mode (see Figure 2-13). No registers are in-  
volved, and the effective address is taken directly from the displacement of the instruction. Pro-  
grammers typically use direct addressing to access scalar variables.  
With register indirect addressing, the effective address of a memory operand can be taken directly  
from one of the base or index registers (see Figure 2-14). One instruction can operate on various  
memory locations if the base or index register is updated accordingly. Any 16-bit general register  
can be used for register indirect addressing with the JMP or CALL instructions.  
In based addressing, the effective address is the sum of a displacement value and the contents of  
the BX or BP register (see Figure 2-15). Specifying the BP register as a base register directs the  
Bus Interface Unit to obtain the operand from the current stack segment (unless a segment over-  
ride prefix is present). This makes based addressing with the BP register a convenient way to ac-  
cess stack data.  
Displacement  
EA  
Opcode  
Mod R/M  
A1016-0A  
Figure 2-13. Direct Addressing  
2-30  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Opcode  
Mod R/M  
BX  
or  
BP  
or  
SI  
or  
EA  
DI  
A1017-0A  
Figure 2-14. Register Indirect Addressing  
Mod R/M  
Opcode  
Displacement  
BX  
or  
+
BP  
EA  
A1018-0A  
Figure 2-15. Based Addressing  
Based addressing provides a simple way to address data structures that may be located in different  
places in memory (see Figure 2-16). A base register can be pointed at the structure. Elements of  
the structure can then be addressed by their displacements. Different copies of the same structure  
can be accessed by simply changing the base register.  
2-31  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Displacement  
High Address  
Displacement  
(Rate)  
Age  
Status  
Rate  
(Rate)  
+
+
Vac  
Sick  
Div  
Base  
Register  
Base Register  
EA  
Dept  
Employee  
EA  
Age  
Status  
Rate  
Vac  
Sick  
Div  
Dept  
Employee  
Low Address  
A1019-0A  
Figure 2-16. Accessing a Structure with Based Addressing  
With indexed addressing, the effective address is calculated by summing a displacement and the  
contents of an index register (SI or DI, see Figure 2-17). Indexed addressing is often used to ac-  
cess elements in an array (see Figure 2-18). The displacement locates the beginning of the array,  
and the value of the index register selects one element. If the index register contains 0000H, the  
processor selects the first element. Since all array elements are the same length, simple arithmetic  
on the register can select any element.  
2-32  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Mod R/M  
Opcode  
Displacement  
SI  
or  
DI  
+
EA  
A1020-0A  
Figure 2-17. Indexed Addressing  
High Address  
Array (8)  
Array (7)  
Array (6)  
Array (5)  
Array (4)  
Array (3)  
Array (2)  
Array (1)  
Array (0)  
Displacement  
Displacement  
+
+
Index Register  
14  
Index Register  
2
EA  
EA  
1 Word  
Low Address  
A1021-0A  
Figure 2-18. Accessing an Array with Indexed Addressing  
2-33  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Based index addressing generates an effective address that is the sum of a base register, an index  
register and a displacement (see Figure 2-19). The two address components can be determined at  
execution time, making this a very flexible addressing mode.  
Opcode  
Mod R/M  
Displacement  
BX  
or  
+
BP  
SI  
or  
DI  
+
EA  
A1022-0A  
Figure 2-19. Based Index Addressing  
Based index addressing provides a convenient way for a procedure to address an array located on  
a stack (see Figure 2-20). The BP register can contain the offset of a reference point on the stack.  
This is typically the top of the stack after the procedure has saved registers and allocated local  
storage. The offset of the beginning of the array from the reference point can be expressed by a  
displacement value. The index register can be used to access individual array elements. Arrays  
contained in structures and matrices (two-dimensional arrays) can also be accessed with based  
indexed addressing.  
String instructions do not use normal memory addressing modes to access operands. Instead, the  
index registers are used implicitly (see Figure 2-21). When a string instruction executes, the SI  
register must point to the first byte or word of the source string, and the DI register must point to  
the first byte or word of the destination string. In a repeated string operation, the CPU will auto-  
matically adjust the SI and DI registers to obtain subsequent bytes or words. For string instruc-  
tions, the DS register is the default segment register for the SI register and the ES register is the  
default segment register for the DI register. This allows string instructions to operate on data lo-  
cated anywhere within the 1 Mbyte address space.  
2-34  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
High Address  
Displacement  
6
Parm 2  
Parm 1  
IP  
Displacement  
6
+
+
Old BP  
Old BX  
Old AX  
Array (6)  
Array (5)  
Array (4)  
Array (3)  
Array (2)  
Array (1)  
Array (0)  
Count  
Base Register (BP)  
Base Register  
(BP)  
+
+
Index Register  
12  
Index Register  
12  
EA  
EA  
Temp  
Status  
1 Word  
Low Address  
A1024-0A  
Figure 2-20. Accessing a Stacked Array with Based Index Addressing  
2-35  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Opcode  
SI  
DI  
Source EA  
Destination EA  
A1025-0A  
Figure 2-21. String Operand  
2.2.2.3  
I/O Port Addressing  
Any memory operand addressing modes can be used to access an I/O port if the port is memory-  
mapped. String instructions can also be used to transfer data to memory-mapped ports with an  
appropriate hardware interface.  
Two addressing modes can be used to access ports located in the I/O space (see Figure 2-22). For  
direct I/O port addressing, the port number is an 8-bit immediate operand. This allows fixed ac-  
cess to ports numbered 0 to 255. Indirect I/O port addressing is similar to register indirect address-  
ing of memory operands. The DX register contains the port number, which can range from 0 to  
65,535. Adjusting the contents of the DX register allows one instruction to access any port in the  
I/O space. A group of adjacent ports can be accessed using a simple software loop that adjusts the  
value of the DX register.  
Data  
Opcode  
Opcode  
Port Address  
DX  
Port Address  
Direct Port  
Addressing  
Indirect Port  
Addressing  
A1026-0A  
Figure 2-22. I/O Port Addressing  
2-36  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.2.2.4  
Data Types Used in the 80C186 Modular Core Family  
The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated  
in Figure 2-23. In general, individual data elements must fit within defined segment limits.  
Table 2-12. Supported Data Types  
Type  
Integer  
Description  
A signed 8- or 16-bit binary numeric value (signed byte or word). All operations assume  
a 2’s complement representation.  
The 80C187 numerics processor extension, when added to an 80C186 Modular Core  
system, directly supports signed 32- and 64-bit integers (signed double-words and  
quad-words). The 80C188 Modular Core does not support the 80C187.  
Ordinal  
BCD  
An unsigned 8- or 16-bit binary numeric value (unsigned byte or word).  
A byte (unpacked) representation of a single decimal digit (0-9).  
ASCII  
A byte representation of alphanumeric and control characters using the ASCII  
standard.  
Packed BCD  
String  
A byte (packed) representation of two decimal digits (0-9).One digit is stored in each  
nibble (4 bits) of the byte.  
A contiguous sequence of bytes or words. A string can contain from 1 byte to 64  
Kbytes.  
Pointer  
A 16- or 32-bit quantity. A 16-bit pointer consists of a 16-bit offset component; a 32-bit  
pointer consists of the combination of a 16-bit base component (selector) plus a 16-bit  
offset component.  
Floating Point  
A signed 32-, 64-, or 80-bit real number representation.  
The 80C187 numerics processor extension, when added to an 80C186 Modular Core  
system, directly supports floating point operands. The 80C188 Modular Core does not  
support the 80C187.  
2-37  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
7
0
7
0
Signed Byte  
Sign Bit  
Unsigned Byte  
MSB  
Magnitude  
Magnitude  
+1  
0
0
+1  
1514  
0
15  
8 7  
0
8 7  
Unsigned  
Word  
Signed Word  
Sign Bit  
MSB  
MSB  
Magnitude  
0
Magnitude  
24 23  
+3  
+2  
+1  
0
31  
63  
16 15  
8 7  
Signed Double  
Word*  
MSB  
Sign Bit  
Magnitude  
+7  
+6  
+5  
+4  
+1  
0
0
+3  
+2  
4847  
32 31  
16 15  
Signed Quad  
Word*  
MSB  
+n  
Sign Bit  
Magnitude  
7
0
+1  
7
7
0
0
0 7  
0 7  
0
Binary Coded  
Decimal (BCD)  
BCD Digit n  
+n  
BCD Digit 1  
+1  
BCD Digit 0  
0
7
0
ASCII  
ASCII Character n  
+n  
ASCII Character 1 ASCII Character 0  
0
+1  
0 7  
7
0
7
0
Packed BCD  
Least  
Significant Digit  
Most  
Significant Digit  
0
+n  
7
+1  
0 7  
8 7  
7
0
0
String  
Byte Word n  
+3  
Byte Word 1  
+1  
16 15  
Byte Word 0  
0
+2  
31  
24 23  
0
Pointer  
Selector  
+8 +7  
Offset  
+4  
+9  
+6  
+5  
+3  
+2  
+1  
+0  
0
79  
Floating  
Point*  
Sign Bit  
Magnitude  
Exponent  
NOTE: *Directly supported if the system contains an 80C187.  
A1027-0B  
Figure 2-23. 80C186 Modular Core Family Supported Data Types  
2-38  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.3 INTERRUPTS AND EXCEPTION HANDLING  
Interrupts and exceptions alter program execution in response to an external event or an error  
condition. An interrupt handles asynchronous external events, for example an NMI. Exceptions  
result directly from the execution of an instruction, usually an instruction fault. The user can  
cause a software interrupt by executing an “INTn” instruction. The CPU processes software in-  
terrupts in the same way that it handles exceptions.  
The 80C186 Modular Core responds to interrupts and exceptions in the same way for all devices  
within the 80C186 Modular Core family. However, devices within the family may have different  
Interrupt Control Units. The Interrupt Control Unit handles all external interrupt sources and pre-  
sents them to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).  
This discussion covers only those areas of interrupts and exceptions that are common to the  
80C186 Modular Core family. The Interrupt Control Unit is proliferation-dependent; see Chapter  
8, “Interrupt Control Unit,” for additional information.  
NMI  
Maskable  
Interrupt  
Request  
Interrupt  
Control  
Unit  
External  
Interrupt  
Sources  
CPU  
Interrupt  
Acknowledge  
A1028-0A  
Figure 2-24. Interrupt Control Unit  
2.3.1 Interrupt/Exception Processing  
The 80C186 Modular Core can service up to 256 different interrupts and exceptions. A 256-entry  
Interrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each en-  
try consists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) of  
the first instruction in the interrupt service routine. Each interrupt or exception is given a type  
number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that in-  
terrupt types 0–31 are reserved for Intel and should not be used by an application program.  
2-39  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Memory  
Address  
Table  
Entry  
Vector  
Definition  
Memory  
Address  
Table  
Entry  
Vector  
Definition  
3FE  
3FC  
CS  
IP  
2E  
2C  
2A  
CS  
IP  
Type 255  
Type 11 - DMA1  
Type 10 - DMA0  
Type 9 - Reserved  
Type 8 - Timer 0  
Type 7 - ESC Opcode  
User  
Available  
CS  
IP  
28  
26  
24  
22  
20  
1E  
1C  
1A  
18  
16  
14  
12  
10  
0E  
0C  
0A  
08  
06  
04  
02  
00  
82  
80  
7E  
7C  
CS  
IP  
CS  
IP  
Type 32  
Type 31  
CS  
IP  
CS  
IP  
CS  
IP  
Reserved  
52  
50  
4E  
4C  
4A  
48  
46  
44  
42  
40  
3E  
3C  
3A  
38  
36  
34  
32  
30  
CS  
IP  
CS  
IP  
Type 20  
Type 6 - Unused  
Opcode  
CS  
IP  
CS  
IP  
Type 19 - Timer 2  
Type 18 - Timer 1  
Type 17 - Reserved  
Type 16 - Numerics  
Type 15 - INT3  
Type 5 - Array  
Bounds  
CS  
IP  
CS  
IP  
Type 4 - Overflow  
Type 3 - Breakpoint  
Type 2 - NMI  
CS  
IP  
CS  
IP  
CS  
IP  
CS  
IP  
CS  
IP  
CS  
IP  
Type 1 - Single-Step  
Type 0 - Divide Error  
CS  
IP  
CS  
IP  
Type 14 - INT2  
CS  
IP  
Type 13 - INT1  
2 Bytes  
CS  
IP  
Type 12 - INT0  
CS =Code Segment Value  
IP = Instruction Pointer Value  
2 Bytes  
A1009-02  
Figure 2-25. Interrupt Vector Table  
When an interrupt is acknowledged, a common event sequence (Figure 2-26) allows the proces-  
sor to execute the interrupt service routine.  
1. The processor saves a partial machine status by pushing the Processor Status Word onto  
the stack.  
2-40  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This  
prevents maskable interrupts or single step exceptions from interrupting the processor  
during the interrupt service routine.  
3. The current CS and IP are pushed onto the stack.  
4. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt  
Vector Table and begins executing from that point.  
The CPU is now executing the interrupt service routine. The programmer must save (usually by  
pushing onto the stack) all registers used in the interrupt service routine; otherwise, their contents  
will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt En-  
able bit in the Processor Status Word.  
When exiting an interrupt service routine, the programmer must restore (usually by popping off  
the stack) the saved registers and execute an IRET instruction, which performs the following  
steps.  
1. Loads the return CS and IP by popping them off the stack.  
2. Pops and restores the old Processor Status Word from the stack.  
The CPU now executes from the point at which the interrupt or exception occurred.  
2-41  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Interrupt Enable Bit  
Trap Flag  
Stack  
1
2
PSW  
CS  
0 0  
Processor Status Word  
IP  
SP  
3
Code Segment Register  
Instruction Pointer  
4
CS  
IP  
Interrupt  
Vector  
Table  
A1029-0A  
Figure 2-26. Interrupt Sequence  
Non-Maskable Interrupts  
2.3.1.1  
The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a  
catastrophic event such as impending power failure. An NMI cannot be prevented (or masked)  
by software. When the NMI input is asserted, the interrupt processing sequence begins after ex-  
ecution of the current instruction completes (see “Interrupt Latency” on page 2-45). The CPU au-  
tomatically generates a type 2 interrupt vector.  
The NMI input is asynchronous. Setup and hold times are given only to guarantee recognition on  
a specific clock edge. To be recognized, NMI must be asserted for at least one CLKOUT period  
and meet the correct setup and hold times. NMI is edge-triggered and level-latched. Multiple  
NMI requests cause multiple NMI service routines to be executed. NMI can be nested in this man-  
ner an infinite number of times.  
2-42  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.3.1.2  
Maskable Interrupts  
Maskable interrupts are the most common way to service external hardware interrupts. Software  
can globally enable or disable maskable interrupts. This is done by setting or clearing the Inter-  
rupt Enable bit in the Processor Status Word.  
The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents  
them to the core via a single maskable interrupt input. The Interrupt Control Unit provides the  
interrupt vector type to the 80C186 Modular Core. The Interrupt Control Unit differs among  
members of the 80C186 Modular Core family; see Chapter 8, “Interrupt Control Unit,” for infor-  
mation.  
2.3.1.3  
Exceptions  
Exceptions occur when an unusual condition prevents further instruction processing until the ex-  
ception is corrected. The CPU handles software interrupts and exceptions in the same way. The  
interrupt type for an exception is either predefined or supplied by the instruction.  
Exceptions are classified as either faults or traps, depending on when the exception is detected  
and whether the instruction that caused the exception can be restarted. Faults are detected and ser-  
viced before the faulting instruction can be executed. The return address pushed onto the stack  
in the interrupt processing instruction points to the beginning of the faulting instruction. This al-  
lows the instruction to be restarted. Traps are detected and serviced immediately after the instruc-  
tion that caused the trap. The return address pushed onto the stack during the interrupt processing  
points to the instruction following the trapping instruction.  
Divide Error — Type 0  
A Divide Error trap is invoked when the quotient of an attempted division exceeds the maximum  
value of the destination. A divide-by-zero is a common example.  
Single Step — Type 1  
The Single Step trap occurs after the CPU executes one instruction with the Trap Flag (TF) bit set  
in the Processor Status Word. This allows programs to execute one instruction at a time. Inter-  
rupts are not generated after prefix instructions (e.g., REP), after instructions that modify segment  
registers (e.g., POP DS) or after the WAIT instruction. Vectoring to the single-step interrupt ser-  
vice routine clears the Trap Flag bit. An IRET instruction in the interrupt service routine restores  
the Trap Flag bit to logic “1” and transfers control to the next instruction to be single-stepped.  
2-43  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Breakpoint Interrupt — Type 3  
The Breakpoint Interrupt is a single-byte version of the INT instruction. It is commonly used by  
software debuggers to set breakpoints in RAM. Because the instruction is only one byte long, it  
can substitute for any instruction.  
Interrupt on Overflow — Type 4  
The Interrupt on Overflow trap occurs if the Overflow Flag (OF) bit is set in the Processor Status  
Word and the INT0 instruction is executed. Interrupt on Overflow is a common method for han-  
dling arithmetic overflows conditionally.  
Array Bounds Check — Type 5  
An Array Bounds trap occurs when the array index is outside the array bounds during execution  
of the BOUND instruction (see Appendix A, “80C186 Instruction Set Additions and Exten-  
sions”).  
Invalid Opcode — Type 6  
Execution of an undefined opcode causes an Invalid Opcode trap.  
Escape Opcode — Type 7  
The Escape Opcode fault is used for floating point emulation. With 80C186 Modular Core family  
members, this fault is enabled by setting the Escape Trap (ET) bit in the Relocation Register (see  
Chapter 4, “Peripheral Control Block”). When a floating point instruction is executed with the  
Escape Trap bit set, the Escape Opcode fault occurs, and the Escape Opcode service routine em-  
ulates the floating point instruction. If the Escape Trap bit is cleared, the CPU sends the floating  
point instruction to an external 80C187.  
80C188 Modular Core Family members do not support the 80C187 interface and always generate  
the Escape Opcode Fault. The 80C186XL will generate the Escape Opcode Fault regardless of  
the state of the Escape Trap bit unless it is in Numerics Mode.  
Numerics Coprocessor Fault — Type 16  
The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The  
80C187 reports the exception by asserting the ERROR pin. The 80C186 Modular Core checks  
the ERROR pin only when executing a numerics instruction. A Numerics Coprocessor Fault in-  
dicates that the previous numerics instruction caused the exception. The 80C187 saves the ad-  
dress of the floating point instruction that caused the exception. The return address pushed onto  
the stack during the interrupt processing points to the numerics instruction that detected the ex-  
ception. This way, the last numerics instruction can be restarted.  
2-44  
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.3.2 Software Interrupts  
A Software Interrupt is caused by executing an “INTn” instruction. The n parameter corresponds  
to the specific interrupt type to be executed. The interrupt type can be any number between 0 and  
255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt  
(NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in  
the Interrupt Status register are not altered.  
The CPU processes software interrupts and exceptions in the same way. Software interrupts, ex-  
ceptions and traps cannot be masked.  
2.3.3 Interrupt Latency  
Interrupt latency is the amount of time it takes for the CPU to recognize the existence of an inter-  
rupt. The CPU generally recognizes interrupts only between instructions or on instruction bound-  
aries. Therefore, the current instruction must finish executing before an interrupt can be  
recognized.  
The worst-case 80C186 instruction execution time is an integer divide instruction with segment  
override prefix. The instruction takes 69 clocks, assuming an 80C186 Modular Core family mem-  
ber and a zero wait-state external bus. The execution time for an 80C188 Modular Core family  
member may be longer, depending on the queue.  
This is one factor in determining interrupt latency. In addition, the following are also factors in  
determining maximum latency:  
1. The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.  
2. The CPU does not recognize interrupts during HOLD.  
3. Once communication is completely established with an 80C187, the CPU does not  
recognize interrupts until the numerics instruction is finished.  
The CPU can recognize interrupts only on valid instruction boundaries. A valid instruction  
boundary usually occurs when the current instruction finishes. The following is a list of excep-  
tions:  
1. MOVs and POPs referencing a segment register delay the servicing of interrupts until  
after the following instruction. The delay allows a 32-bit load to the SS and SP without an  
interrupt occurring between the two loads.  
2. The CPU allows interrupts between repeated string instructions. If multiple prefixes  
precede a string instruction and the instruction is interrupted, only the one prefix  
preceding the string primitive is restored.  
3. The CPU can be interrupted during a WAIT instruction. The CPU will return to the WAIT  
instruction.  
2-45  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
2.3.4 Interrupt Response Time  
Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction  
in the service routine is executed. Interrupt response time is less for interrupts or exceptions  
which supply their own vector type. The maskable interrupt has a longer response time because  
the vector type must be supplied by the Interrupt Control Unit (see Chapter 8, “Interrupt Control  
Unit”).  
Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supply  
their type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use of  
idle bus cycles. This can increase interrupt response time.  
Clocks  
Idle  
5
4
5
Read IP  
Idle  
Read CS  
Idle  
4
4
4
3
4
4
5
Push Flags  
Idle  
Push CS  
Push IP  
Idle  
First Instruction Fetch  
From Interrupt Routine  
Total 42  
A1030-0A  
Figure 2-27. Interrupt Response Factors  
2.3.5 Interrupt and Exception Priority  
Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable in-  
terrupt are both recognized on the same instruction boundary, NMI has precedence. The  
maskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest  
priority.  
2-46  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Only the single step exception can occur concurrently with another exception. At most, two ex-  
ceptions can occur at the same instruction boundary and one of those exceptions must be the sin-  
gle step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now),  
only one exception can occur at any given instruction boundary.  
An exception has priority over both NMI and the maskable interrupt. However, a pending NMI  
can interrupt the CPU at any valid instruction boundary. Therefore, NMI can interrupt an excep-  
tion service routine. If an exception and NMI occur simultaneously, the exception vector is taken,  
then is followed immediately by the NMI vector (see Figure 2-28). While the exception has high-  
er priority at the instruction boundary, the NMI interrupt service routine is executed first.  
F = 1  
NMI  
Divide Error  
Divide  
Push PSW, CS, IP  
Fetch Divide Error Vector  
Push PSW, CS, IP  
Fetch NMI Vector  
Execute NMI  
Service Routine  
IRET  
Execute Divide  
Service Routine  
IRET  
A1031-0A  
Figure 2-28. Simultaneous NMI and Exception  
2-47  
 
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc-  
tion boundary as a single step, the interrupt vector is taken first, then is followed immediately by  
the single step vector. However, the single step service routine is executed before the interrupt  
service routine (see Figure 2-29). If the single step service routine re-enables single step by exe-  
cuting the IRET, the interrupt service routine will also be single stepped. This can severely limit  
the real-time response of the CPU to an interrupt.  
To prevent the single-step routine from executing before a maskable interrupt, disable interrupts  
while single stepping an instruction, then enable interrupts in the single step service routine. The  
maskable interrupt is serviced from within the single step service routine and that interrupt ser-  
vice routine is not single-stepped. To prevent single stepping before an NMI, the single-step ser-  
vice routine must compare the return address on the stack to the NMI vector. If they are the same,  
return to the NMI service routine immediately without executing the single step service routine.  
NMI  
Trap Flag = 1  
Instruction  
Push PSW, CS, IP  
Fetch Divide Error Vector  
Trap Flag = 0  
Push PSW, CS, IP  
Fetch Single Step Vector  
Execute Single Step  
Service Routine  
IRET  
Trap Flag = ???  
A1032-0A  
Figure 2-29. Simultaneous NMI and Single Step Interrupts  
The most complicated case is when an NMI, a maskable interrupt, a single step and another ex-  
ception are pending on the same instruction boundary. Figure 2-30 shows how this case is prior-  
itized by the CPU. Note that if the single-step routine sets the Trap Flag (TF) bit before executing  
the IRET instruction, the NMI routine will also be single stepped.  
2-48  
   
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE  
Interrupt Enable Bit (IE) = 1  
Trap Flag (TF) = 1  
NMI  
Divide  
Timer Interrupt  
Push PSW, CS, IP  
Fetch Divide Error Vector  
Interrupt Enable Bit (IE) = 0  
Trap Flag (TF) = 0  
Interrupt Enable Bit (IE) = 0  
Trap Flag (TF) = 0  
Push PSW, CS, IP  
Fetch NMI Vector  
Push PSW, CS, IP  
Fetch Single Step Vector  
Interrupt Enable Bit (IE) = 0  
Trap Flag (TF) = 0  
Execute Single Step  
Service Routine  
IRET  
Interrupt Enable Bit (IE) = 0  
Trap Flag (TF) = ???  
Interrupt Enable Bit (IE) = 1  
Trap Flag (TF) = X  
Push PSW, CS, IP  
Fetch Single Step Vector  
Interrupt Enable Bit (IE) = 1  
Trap Flag (TF) = X  
Execute Single Step Service Routine  
IRET  
A1034-0A  
Figure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt  
2-49  
 
3
Bus Interface Unit  
CHAPTER 3  
BUS INTERFACE UNIT  
The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass  
data to and from the execution unit, and pass data to and from the integrated peripheral units.  
The BIU drives address, data, status and control information to define a bus cycle. The start of a  
bus cycle presents the address of a memory or I/O location and status information defining the  
type of bus cycle. Read or write control signals follow the address and define the direction of data  
flow. A read cycle requires data to flow from the selected memory or I/O device to the BIU. In a  
write cycle, the data flows from the BIU to the selected memory or I/O device. Upon termination  
of the bus cycle, the BIU latches read data or removes write data.  
3.1 MULTIPLEXED ADDRESS AND DATA BUS  
The BIU has a combined address and data bus, commonly referred to as a time-multiplexed bus.  
Time multiplexing address and data information makes the most efficient use of device package  
pins. A system with address latching provided within the memory and I/O devices can directly  
connect to the address/data bus (or local bus). The local bus can be demultiplexed with a single  
set of address latches to provide non-multiplexed address and data information to the system.  
3.2 ADDRESS AND DATA BUS CONCEPTS  
The programmer views the memory or I/O address space as a sequence of bytes. Memory space  
consists of 1 Mbyte, while I/O space consists of 64 Kbytes. Any byte can contain an 8-bit data  
element, and any two consecutive bytes can contain a 16-bit data element (identified as a word).  
The discussions in this section apply to both memory and I/O bus cycles. For brevity, memory  
bus cycles are used for examples and illustration.  
3.2.1 16-Bit Data Bus  
The memory address space on a 16-bit data bus is physically implemented by dividing the address  
space into two banks of up to 512 Kbytes each (see Figure 3-1). One bank connects to the lower  
half of the data bus and contains even-addressed bytes (A0=0). The other bank connects to the  
upper half of the data bus and contains odd-addressed bytes (A0=1). Address lines A19:1 select  
a specific byte within each bank. A0 and Byte High Enable (BHE) determine whether one bank  
or both banks participate in the data transfer.  
3-1  
BUS INTERFACE UNIT  
Physical Implementation  
of the Address Space for  
16-Bit Systems  
Physical Implementation  
of the Address Space for  
8-Bit Systems  
1 MByte  
512 KBytes  
512 KBytes  
FFFFF  
FFFFE  
FFFFF  
FFFFD  
FFFFE  
FFFFC  
2
1
0
5
3
1
4
2
0
A19:0  
A19:1  
D15:8  
BHE  
D7:0  
A0  
A1100-0A  
Figure 3-1. Physical Data Bus Models  
Byte transfers to even addresses transfer information over the lower half of the data bus (see Fig-  
ure 3-2). A0 low enables the lower bank, while BHE high disables the upper bank. The data value  
from the upper bank is ignored during a bus read cycle. BHE high prevents a write operation from  
destroying data in the upper bank.  
Byte transfers to odd addresses transfer information over the upper half of the data bus (see Figure  
3-2). BHE low enables the upper bank, while A0 high disables the lower bank. The data value  
from the lower bank is ignored during a bus read cycle. A0 high prevents a write operation from  
destroying data in the lower bank.  
To access even-addressed 16-bit words (two consecutive bytes with the least-significant byte at  
an even address), information is transferred over both halves of the data bus (see Figure 3-3).  
A19:1 select the appropriate byte within each bank. A0 and BHE drive low to enable both banks  
simultaneously.  
Odd-addressed word accesses require the BIU to split the transfer into two byte operations (see  
Figure 3-4). The first operation transfers data over the upper half of the bus, while the second op-  
eration transfers data over the lower half of the bus. The BIU automatically executes the two-byte  
sequence whenever an odd-addressed word access is performed.  
3-2  
 
BUS INTERFACE UNIT  
Even Byte Transfer  
Y + 1  
X + 1  
Y
(X)  
A0  
(Low)  
A19:1  
D15:8  
D7:0  
BHE  
(High)  
Odd Byte Transfer  
Y + 1  
(X + 1)  
Y
X
A19:1  
D7:0  
D15:8  
A0  
(High)  
BHE  
(Low)  
A1104-0A  
Figure 3-2. 16-Bit Data Bus Byte Transfers  
3-3  
 
BUS INTERFACE UNIT  
(X)  
(X + 1)  
A19:1  
D15:8  
D7:0  
BHE  
A0  
(Low)  
(Low)  
A1107-0A  
Figure 3-3. 16-Bit Data Bus Even Word Transfers  
During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer  
occurs on only one half of the bus. This action simplifies the decoding requirements for read-only  
devices (e.g., ROM, EPROM, Flash). During the byte read, an external device can drive both  
halves of the bus, and the BIU automatically accesses the correct half. During the byte write op-  
eration, the BIU drives both halves of the bus. Information on the half of the bus not involved in  
the transfer is indeterminate. This action requires that the appropriate bank (defined by BHE or  
A0 high) be disabled to prevent destroying data.  
3-4  
 
BUS INTERFACE UNIT  
First Bus Cycle  
Y
X
(X + 1)  
A0  
(High)  
A19:1  
D15:8  
D7:0  
BHE  
(Low)  
Second Bus Cycle  
Y + 1  
X + 1  
(Y)  
X
A0  
(Low)  
A19:1  
D15:8  
D7:0  
BHE  
(High)  
A1108-0A  
Figure 3-4. 16-Bit Data Bus Odd Word Transfers  
3.2.2 8-Bit Data Bus  
The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte  
(see Figure 3-1 on page 3-2). Address lines A19:0 select a specific byte within the bank. Unlike  
transfers with a 16-bit bus, byte and word transfers (to even or odd addresses) all transfer data  
over the same 8-bit bus.  
Byte transfers to even or odd addresses transfer information in one bus cycle. Word transfers to  
even or odd addresses transfer information in two bus cycles. The BIU automatically converts the  
word access into two consecutive byte accesses, making the operation transparent to the program-  
mer.  
3-5  
 
BUS INTERFACE UNIT  
For word transfers, the word address defines the first byte transferred. The second byte transfer  
occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus in-  
terface.  
Second Bus Cycle  
(X + 1)  
First Bus Cycle  
(X)  
A19:0  
D7:0  
A19:0  
D7:0  
A1109-0A  
Figure 3-5. 8-Bit Data Bus Word Transfers  
3.3 MEMORY AND I/O INTERFACES  
The CPU can interface with 8- and 16-bit memory and I/O devices. Memory devices exchange  
information with the CPU during memory read, memory write and instruction fetch bus cycles.  
I/O (peripheral) devices exchange information with the CPU during memory read, memory write,  
I/O read, I/O write and interrupt acknowledge bus cycles. Memory-mapped I/O refers to periph-  
eral devices that exchange information during memory cycles. Memory-mapped I/O allows the  
full power of the instruction set to be used when communicating with peripheral devices.  
I/O read and I/O write bus cycles use a separate I/O address space. Only IN and OUT instructions  
can access I/O address space, and information must be transferred between the peripheral device  
and the AX register. The first 256 bytes (0–255) of I/O space can be accessed directly by the I/O  
instructions. The entire 64 Kbyte I/O address space can be accessed only indirectly, through the  
DX register. I/O instructions always force address bits A19:16 to zero.  
Interrupt acknowledge, or INTA, bus cycles access an I/O device intended to increase interrupt  
input capability. Valid address information is not generated as part of the INTA bus cycle, and  
data is transferred only over the lower bank (16-bit device).  
3-6  
 
BUS INTERFACE UNIT  
3.3.1 16-Bit Bus Memory and I/O Requirements  
A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store  
instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction  
prefetch bus cycles require that both banks be used. The lower bank contains the even bytes of  
code and the upper bank contains the odd bytes of code.  
Memory used to store interrupt vectors and stack data must be 16 bits wide. Memory address  
space between 0H and 3FFH (1 Kbyte) holds the starting location of an interrupt routine. In re-  
sponse to an interrupt, the BIU fetches two consecutive, even-addressed words from this 1 Kbyte  
address space. Stack pushes and pops always write or read even-addressed word data.  
3.3.2 8-Bit Bus Memory and I/O Requirements  
An 8-bit bus interface has no restrictions on implementing the memory or I/O interfaces. All  
transfers, bytes and words, occur over the single 8-bit bus. Operations requiring word transfers  
automatically execute two consecutive byte transfers.  
3.4 BUS CYCLE OPERATION  
The BIU executes a bus cycle to transfer data between any of the integrated units and any external  
memory or I/O devices (see Figure 3-6). A bus cycle consists of a minimum of four CPU clocks  
known as “T-states.” A T-state is bounded by one falling edge of CLKOUT to the next falling  
edge of CLKOUT (see Figure 3-7). Phase 1 represents the low time of the T-state and starts at the  
high-to-low transition of CLKOUT. Phase 2 represents the high time of the T-state and starts at  
the low-to-high transition of CLKOUT. Address, data and control signals generated by the BIU  
go active and inactive at different phases within a T-state.  
3-7  
BUS INTERFACE UNIT  
T4  
T1  
T2  
T3  
T4  
CLKOUT  
ALE  
Valid Status  
Address  
S2:0  
Data  
AD15:0  
RD / WR  
A1507-0A  
Figure 3-6. Typical Bus Cycle  
TN  
Rising  
Edge  
Falling  
Edge  
CLKOUT  
Phase 1  
(Low Phase)  
Phase 2  
(High Phase)  
A1111-0A  
Figure 3-7. T-State Relation to CLKOUT  
Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T-  
states labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple  
T3 states occur to generate wait states. The TW symbol represents a wait state.  
The operation of a bus cycle can be separated into two phases:  
Address/Status Phase  
Data Phase  
3-8  
   
BUS INTERFACE UNIT  
The address/status phase starts just before T1 and continues through T1. The data phase starts at  
T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases.  
T4  
Bus Ready  
Request Pending  
HOLD Deasserted  
Halt Bus Cycle  
T1  
T2  
T3  
Bus Not  
Ready  
Request Pending  
HOLD Deasserted  
Bus Ready  
No Request Pending  
HOLD Deasserted  
TI  
RES#  
Asserted  
HOLD Asserted  
A1533-02  
Figure 3-8. BIU State Diagram  
3-9  
 
BUS INTERFACE UNIT  
T4  
T3  
T4  
T1  
T2  
or TI  
or TW  
or TI  
CLKOUT  
Address/  
Status Phase  
Data Phase  
A1113-0A  
Figure 3-9. T-State and Bus Phases  
3.4.1 Address/Status Phase  
Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus  
cycle begins with the transition of ALE and S2:0. These signals transition during phase 2 of the  
T-state just prior to T1. Either T4 or TI precedes T1, depending on the operation of the previous  
bus cycle (see Figure 3-8 on page 3-9).  
ALE provides a strobe to latch physical address information. Address is presented on the multi-  
plexed address/data bus during T1 (see Figure 3-10). The falling edge of ALE occurs during the  
middle of T1 and provides a strobe to latch the address. Figure 3-11 presents a typical circuit for  
latching addresses.  
The status signals (S2:0) define the type of bus cycle (Table 3-1). S2:0 remain valid until phase  
1 of T3 (or the last TW, when wait states occur). The circuit shown in Figure 3-11 can also be  
used to extend S2:0 beyond the T3 (or TW) state.  
3-10  
 
BUS INTERFACE UNIT  
T4  
T1  
T2  
5
or TI  
CLKOUT  
ALE  
4
1
2
3
6
AD15:0  
A19:16  
Valid  
Address  
Valid  
S2:0  
Valid  
BHE  
NOTES:  
1. T  
2. T  
3. T  
4. T  
5. T  
6. T  
T
: Clock high to ALE high, S2:0 valid.  
CHLH CHSV  
: Clock low to address valid, BHE valid.  
: Address valid to ALE low (address setup to ALE).  
: Clock high to ALE low.  
: Clock low to address invalid (address hold from clock low).  
: ALE low to address invalid (address hold from ALE).  
CLAV  
AVLL  
CHLL  
CLAZ  
LLAX  
A1509-0A  
Figure 3-10. Address/Status Phase Signal Relationships  
3-11  
 
BUS INTERFACE UNIT  
Latched  
Address Signals  
Signals From CPU  
4
3
I
A19:16  
S2:0  
4
LA19:16  
O
O
I
3
LS2:0  
STB  
OE  
8
8
AD15:8  
I
8
LA15:8  
O
O
STB  
OE  
I
AD7:0  
ALE  
8
LA7:0  
STB  
OE  
A1102-0A  
Figure 3-11. Demultiplexing Address Information  
Table 3-1. Bus Cycle Types  
Status Bit  
Operation  
S2  
S1  
S0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge  
I/O Read  
I/O Write  
Halt  
Instruction Prefetch  
Memory Read  
Memory Write  
Idle (passive)  
3-12  
   
BUS INTERFACE UNIT  
3.4.2 Data Phase  
Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle  
type that does not have a data phase is a bus halt. During the data phase, the bus transfers infor-  
mation between the internal units and the memory or peripheral device selected during the ad-  
dress/status phase. Appropriate control signals become active to coordinate the transfer of data.  
The data phase begins at phase 1 of T2 and continues until phase 2 of T4 or TI. The length of the  
data phase varies depending on the number of wait states. Wait states occur after T3 and before  
T4 or TI.  
3.4.3 Wait States  
Wait states extend the data phase of the bus cycle. Memory and I/O devices that cannot provide  
or accept data in the minimum four CPU clocks require wait states. Figure 3-13 shows a typical  
The bus ready inputs (ARDY and SRDY) and the Chip-Select Unit control bus cycle wait states.  
Only the bus ready inputs are described in this chapter. (See Chapter 6, “Chip-Select Unit,” for  
additional information.)  
Figure 3-14 shows a simplified block diagram of the ARDY and SRDY inputs. Either ARDY or  
SRDY active signals a bus ready condition; therefore, both pins must be inactive to signal a not-  
ready condition. Depending on the size and characteristics of the system, ready implementation  
can take one of two approaches: normally not-ready or normally ready.  
3-13  
BUS INTERFACE UNIT  
T3  
T4  
T2  
or TW  
or TI  
CLKOUT  
RD/ WR  
4
2
1
6
7
AD15:0  
Write  
Valid Write Data  
5
3
Valid  
Read Data  
AD15:0  
Read  
S2:0  
NOTES:  
1. T  
2. T  
3. T  
4. T  
5. T  
6. T  
7. T  
T
: Clock low to valid RD/WR active, write data valid.  
CLRL/CLWL, CLOV  
CLSH  
DVCL  
CLRH/CLWH  
CLDX  
WHDX  
RHAV  
: Clock low to status inactive.  
: Data input valid to clock low.  
: Clock valid to RD/WR inactive.  
: Data input HOLD from clock low.  
: Output data HOLD from WR high.  
: Bus no longer floating from RD high.  
Figure 3-12. Data Phase Signal Relationships  
3-14  
 
BUS INTERFACE UNIT  
T1  
T2  
T3  
TW  
TW  
T4  
CLKOUT  
ALE  
Valid  
S2:0  
Address  
Address  
A19:16  
Valid Write Data  
AD15:0  
WR  
READY  
A1040-0A  
Figure 3-13. Typical Bus Cycle with Wait States  
ARDY  
BUS READY  
D
Q
D
Q
Rising  
Edge  
Falling  
Edge  
CLKOUT  
SRDY  
A1041-0A  
Figure 3-14. ARDY and SRDY Pin Block Diagram  
3-15  
   
BUS INTERFACE UNIT  
A normally not-ready system is one in which ARDY and SRDY remain low at all times except  
to signal a ready condition. For any bus cycle, only the selected device drives either ready input  
high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to  
generate a normally not-ready signal. Note that if no device is selected the bus remains not-  
ready indefinitely. Systems with many slow devices that cannot operate at the maximum bus  
bandwidth usually implement a normally not-ready signal.  
The start of a bus cycle clears the wait state module and forces ARDY low. After every rising  
edge of CLKOUT, INPUT1 and INPUT2 are shifted through the module and eventually drive  
ARDY high. Assuming INPUT1 and INPUT2 are valid prior to phase 2 of T2, no delay through  
the module causes one wait state. Each additional clock delay through the module generates one  
additional wait state. Two inputs are used to establish different wait state conditions. The same  
circuit works for SRDY, but no delay through the module results in no wait states.  
CS1  
CS2  
Wait State Module  
Input 1  
Input 2  
CS3  
CS4  
Out  
READY  
ALE  
Clear  
Clock  
CLKOUT  
A1080-0A  
Figure 3-15. Generating a Normally Not-Ready Bus Signal  
A normally ready signal remains high at all times except when the selected device needs to signal  
a not-ready condition. For any bus cycle, only the selected device drives the ready input (or in-  
puts) low to delay the completion of the bus cycle. The circuit shown in Figure 3-16 illustrates a  
simple circuit to generate a normally ready signal. Note that if no device is selected the bus re-  
mains ready. Systems that have few or no devices requiring wait states usually implement a nor-  
mally ready signal.  
The start of a bus cycle preloads a zero shifter and forces SRDY active (high). SRDY remains  
active if neither CS1 or CS2 goes low. Should either CS1 or CS2 go low, zeros are shifted out on  
every rising edge of CLKOUT, causing SRDY to go inactive. At the end of the shift pattern,  
SRDY is forced active again. Assuming CS1 and CS2 are active just prior to phase 2 of T2, shift-  
ing one zero through the module causes one wait state. Each additional zero shifted through the  
module generates one wait state. The same circuit works for ARDY, but shifting one zero through  
the module generates two wait states.  
3-16  
 
BUS INTERFACE UNIT  
Wait State Module  
Enable  
CS1  
CS2  
Out  
READY  
ALE  
Load  
CLKOUT  
Clock  
A1081-0A  
Figure 3-16. Generating a Normally Ready Bus Signal  
The ARDY input has two major timing concerns that can affect whether a normally ready or nor-  
mally not-ready signal may be required. Two latches capture the state of the ARDY input (see  
Figure 3-14 on page 3-15). The first latch captures ARDY on the phase 2 clock edge. The second  
latch captures ARDY and the result of first latch on the phase 1 clock edge. The following items  
define the requirements of the ARDY input to meet ready or not-ready bus conditions.  
The bus is ready if both of these two conditions are true:  
— ARDY is active prior to the phase 2 clock edge, and  
— ARDY remains active after the phase 1 clock edge.  
The bus is not-ready if either of these two conditions is true:  
— ARDY is inactive prior to the phase 2 clock edge, or  
— ARDY is inactive prior to the phase 1 clock edge.  
A single latch captures the state of the SRDY input (see Figure 3-14 on page 3-15). SRDY must  
be valid by the phase 1 clock edge. The following items define the requirements of the SRDY  
input to meet ready or not-ready bus conditions.  
The bus is ready if SRDY is active prior to the phase 1 clock edge.  
The bus is not-ready if SRDY is inactive prior to the phase 1 clock edge.  
A normally not-ready system must generate a valid ARDY input at phase 2 of T2 or a valid SRDY  
input at phase 1 of T3 to prevent wait states. If it cannot, then running without wait states requires  
a normally ready system. Figure 3-17 illustrates the timing necessary to prevent wait states in a  
normally not-ready system. Figure 3-17 also shows how to terminate a bus cycle with wait states  
in a normally not-ready system.  
3-17  
 
BUS INTERFACE UNIT  
T2  
or T3  
or TW  
T3  
or TW  
T4  
CLKOUT  
2
1
3
ARDY  
SRDY  
In a Normally-Not-Ready system, wait states are inserted until (1 or 2) and 3 are met.  
1. T  
2. T  
3. T  
: ARDY active to clock high (assumes ARDY remains active until 3).  
: SRDY active to clock low.  
ARYCH  
SRYCL  
T
: ARDY and SRDY hold from clock low.  
CLARX, CLSRY  
Failure to meet SRDY setup and hold can cause a device failure  
(i.e., the bus hangs or operates inappropriately).  
!
A1511-0A  
Figure 3-17. Normally Not-Ready System Timing  
A valid not-ready input can be generated as late as phase 1 of T3 to insert wait states in a normally  
ready system. A normally not-ready system must run wait states if the not-ready condition cannot  
be met in time. Figure 3-18 illustrates the minimum and maximum timing necessary to insert wait  
states in a normally ready system. Figure 3-18 also shows how to terminate a bus cycle with wait  
states in a normally ready system.  
The BIU can execute an indefinite number of wait states. However, bus cycles with large numbers  
of wait states limit the performance of the CPU and the integrated peripherals. CPU performance  
suffers because the instruction prefetch queue cannot be kept full. Integrated peripheral perfor-  
mance suffers because the maximum bus bandwidth decreases.  
3.4.4 Idle States  
Under most operating conditions, the BIU executes consecutive (back-to-back) bus cycles. How-  
ever, several conditions cause the BIU to become idle. An idle condition occurs between bus cy-  
cles (see Figure 3-8 on page 3-9) and may last an indefinite period of time, depending on the  
instruction sequence.  
3-18  
 
BUS INTERFACE UNIT  
T2  
T3  
TW  
T4  
CLKOUT  
ARDY  
2
1
In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met.  
(Assumes SRDY is low.)  
1. T  
2. T  
: ARDY low to clock high  
ARYCH  
: Clock high to ARDY high (ARDY inactive hold time)  
ARYCHL  
T2  
T3  
TW  
T4  
CLKOUT  
2
1
ARDY  
SRDY  
Alternatively, in a Normally-Ready system, a wait state will be inserted  
when1 & 2 are met for SRDY and ARDY.  
1. T  
2. T  
, T  
: ARDY and SRDY low to clock low  
: ARDY and SRDY low from clock low  
ARYCL SRYCL  
, T  
CHARX CLSRY  
Failure to meet ARDY and SRDY setup and hold can cause a device failure  
(i.e., the bus hangs or operates inappropriately).  
!
A1512-0A  
Figure 3-18. Normally Ready System Timings  
Conditions causing the BIU to become idle include the following.  
The instruction prefetch queue is full.  
An effective address calculation is in progress.  
The bus cycle inherently requires idle states (e.g., interrupt acknowledge, locked opera-  
tions).  
Instruction execution forces idle states (e.g., HLT, WAIT).  
3-19  
 
BUS INTERFACE UNIT  
An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle con-  
tinues to float the bus. An idle bus state following a bus write cycle continues to drive the bus.  
The BIU drives no control strobes active in an idle state except to indicate the start of another bus  
cycle.  
3.5 BUS CYCLES  
There are four basic types of bus cycles: read, write, interrupt acknowledge and halt. Interrupt  
acknowledge and halt bus cycles define special bus operations and require separate discussions.  
Read bus cycles include memory, I/O and instruction prefetch bus operations. Write bus cycles  
include memory and I/O bus operations. All read and write bus cycles have the same basic format.  
The following sections present timing equations containing symbols found in the data sheet. The  
timing equations provide information necessary to start a worst-case design analysis.  
3.5.1 Read Bus Cycles  
Figure 3-19 illustrates a typical read cycle. Table 3-2 lists the three types of read bus cycles.  
Table 3-2. Read Bus Cycle Types  
Status Bit  
Bus Cycle Type  
S2  
S1  
S0  
0
0
1
Read I/O — Initiated by the Execution Unit for IN, OUT, INS, OUTS instructions  
or by the DMA Unit. A19:16 are driven to zero (see Chapter 10, “Direct Memory  
Access Unit”).  
1
1
0
0
0
1
Instruction Prefetch — Initiated by the BIU. Data read from the bus fills the  
prefetch queue.  
Read Memory — A19:0 select the desired byte or word memory location.  
Figure 3-20 illustrates a typical 16-bit interface connection to a read-only device interface. The  
same example applies to an 8-bit bus system, except that no devices connect to an upper bus. Four  
parameters (Table 3-3) must be evaluated when determining the compatibility of a memory (or  
I/O) device. TADLTCH defines the delay through the address latch.  
Table 3-3. Read Cycle Critical Timing Parameters  
Memory Device  
Parameter  
Description  
Equation  
TOE  
TACC  
TCE  
Output enable (RD low) to data valid  
Address valid to data valid  
2T  
3T  
3T  
– T  
– T  
– T  
– T  
DVCL  
CLCL  
CLCL  
CLCL  
RHAV  
CLRL  
CLAV  
–T  
T
ADLTCH – DVCL  
Chip enable (UCS) to data valid  
Output disable (RD high) to output float  
– T  
CLIS  
CLOV2  
TDF  
T
3-20  
   
BUS INTERFACE UNIT  
TOE, TACC and TCE define the maximum data access requirements for the memory device. These  
device parameters must be less than the value calculated in the equation column. An equal to or  
greater than result indicates that wait states must be inserted into the bus cycle.  
TDF determines the maximum time the memory device can float its outputs before the next bus  
cycle begins. A TDF value greater than the equation result indicates a buffer fight. A buffer fight  
means two (or more) devices are driving the bus at the same time. This can lead to short circuit  
conditions, resulting in large current spikes and possible device damage.  
TRHAX cannot be lengthened (other than by slowing the clock rate). To resolve a buffer fight con-  
dition, choose a faster device or buffer the AD bus (see “Buffering the Data Bus” on page 3-34).  
T1  
T2  
T3  
T4  
CLKOUT  
S2:0  
Status Valid  
ALE  
Address Valid  
A18:16 = 0, A19=Valid Status  
Valid  
A19:16  
A15:8  
BHE  
RFSH  
A15:0  
[AD7:0]  
Data  
Valid  
Address  
Valid  
RD  
DT/R  
DEN  
A1046-0A  
Figure 3-19. Typical Read Bus Cycle  
3-21  
 
BUS INTERFACE UNIT  
3.5.1.1  
Refresh Bus Cycles  
A refresh bus cycle operates similarly to a normal read bus cycle except for the following:  
For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the  
bus is ignored.  
For an 8-bit data bus, address bit A0 drives to a 1 (high) and RFSH is driven active (low).  
The data value on the bus is ignored. RFSH has the same bus timing as BHE.  
UCS  
CE  
AD7:0  
O
A
0-7  
27C256  
LA15:1  
RD  
0-14  
OE  
OE  
A
0-14  
0-7  
27C256  
AD15:8  
O
CE  
Note: A and BHE are not used.  
0
A1105-0A  
Figure 3-20. Read-Only Device Interface  
3.5.2 Write Bus Cycles  
Figure 3-21 illustrates a typical write bus cycle. The bus cycle starts with the transition of ALE  
high and the generation of valid status bits S2:0. The bus cycle ends when WR transitions high  
(inactive), although data remains valid for one additional clock. Table 3-4 lists the two types of  
write bus cycles.  
3-22  
 
BUS INTERFACE UNIT  
T1  
T2  
T3  
T4  
CLKOUT  
S2:0  
Status Valid  
ALE  
Address Valid  
A18:16 = 0, A19=Valid Status  
A19:16  
BHE  
[A15:8]  
Valid  
A15:0  
[AD7:0]  
Address  
Valid  
Data Valid  
WR  
DT/R  
DEN  
A1047-0A  
Figure 3-21. Typical Write Bus Cycle  
Table 3-4. Write Bus Cycle Types  
Status Bits  
S1  
Bus Cycle Type  
S2  
S0  
0
1
0
Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions or by the  
DMA Unit. A15:0 select the desired I/O port. A19:16 are driven to zero (see  
Chapter 10, “Direct Memory Access Unit”).  
1
1
0
Write Memory —Initiated by any of the Byte/ Word memory instructions or the  
DMA Unit. A19:0 selects the desired byte or word memory location.  
Figure 3-22 illustrates a typical 16-bit interface connection to a read/write device. Write bus cy-  
cles have many parameters that must be evaluated in determining the compatibility of a memory  
(or I/O) device. Table 3-5 lists some critical write bus cycle parameters.  
3-23  
   
BUS INTERFACE UNIT  
Most memory and peripheral devices latch data on the rising edge of the write strobe. Address,  
chip-select and data must be valid (set up) prior to the rising edge of WR. TAW, TCW and TDW de-  
fine the minimum data setup requirements. The value calculated by their respective equations  
must be greater than the device requirements. To increase the calculated value, insert wait states.  
A0:14  
OE  
LA15:1  
RD  
AD7:0  
I/O1:8  
WE  
CS1  
LA0  
WR  
A0:14  
OE  
BHE  
AD15:8  
I/O1:8  
WE  
LCS  
CS1  
A1106-0A  
Figure 3-22. 16-Bit Bus Read/Write Device Interface  
3-24  
 
BUS INTERFACE UNIT  
The minimum device data hold time (from WR high) is defined by TDH. The calculated value  
must be greater than the minimum device requirements; however, the value can be changed only  
by decreasing the clock rate.  
Table 3-5. Write Cycle Critical Timing Parameters  
Memory Device  
Parameter  
Description  
Equation  
TWC  
TAW  
TCW  
TWR  
TDW  
TDH  
TWP  
Write cycle time  
4T  
3T  
3T  
CLCL  
Address valid to end of write strobe (WR high)  
Chip enable (LCS) to end of write strobe (WR high)  
Write recover time  
– T  
ADLTCH  
CLCL  
CLCL  
TWHLH  
2T  
Data valid to write strobe (WR high)  
Data hold from write strobe (WR high)  
Write pulse width  
CLCL  
TWHDX  
TWLWH  
TWC and TWP define the minimum time (maximum frequency) a device can process write bus cy-  
cles. TWR determines the minimum time from the end of the current write cycle to the start of the  
next write cycle. All three parameters require that calculated values be greater than device re-  
quirements. The calculated TWC and TWP values increase with the insertion of wait states. The cal-  
culated TWR value, however, can be changed only by decreasing the clock rate.  
3.5.3 Interrupt Acknowledge Bus Cycle  
Interrupt expansion is accomplished by interfacing the Interrupt Control Unit with a peripheral  
device such as the 82C59A Programmable Interrupt Controller. (See Chapter 8, “Interrupt Con-  
trol Unit,” for more information.) The BIU controls the bus cycles required to fetch vector infor-  
mation from the peripheral device, then passes the information to the CPU. These bus cycles,  
collectively known as Interrupt Acknowledge bus cycles, operate similarly to read bus cycles.  
However, instead of generating RD to enable the peripheral, the INTA signal is used. Figure 3-23  
illustrates a typical Interrupt Acknowledge (or INTA) bus cycle.  
An Interrupt Acknowledge bus cycle consists of two consecutive bus cycles. LOCK is generated  
to indicate the sequential bus operation. The second bus cycle strobes vector information only  
from the lower half of the bus (D7:0). In a 16-bit bus system, the upper half of the bus (D15:8)  
floats.  
3-25  
 
BUS INTERFACE UNIT  
T1  
T2  
T3  
T4  
TI  
TI  
T1  
T2  
T3  
T4  
CLKOUT  
ALE  
S2:0  
INTA0  
INTA1  
Note  
Note  
AD15:0  
[AD7:0]  
Note  
LOCK  
DT/R  
DEN  
A19:16  
[A15:8]  
A15:8 are unknown  
A19:16 are driven low  
BHE  
RD, WR  
NOTE: Vector Type is read from AD7:0 only.  
INTA occurs during T2 in slave mode.  
A1048-0A  
Figure 3-23. Interrupt Acknowledge Bus Cycle  
3-26  
 
BUS INTERFACE UNIT  
Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate  
both bus cycles in the interrupt acknowledge sequence.  
NOTE  
Due to an internal condition, external ready is ignored if the device is  
configured in Cascade mode and the Peripheral Control Block (PCB) is  
located at 0000H in I/O space. In this case, wait states cannot be added to  
interrupt acknowledge bus cycles. However, you can add wait states to  
interrupt acknowledge cycles if the PCB is located at any other address.  
3.5.3.1  
System Design Considerations  
Although ALE is generated for both bus cycles, the BIU does not drive valid address information.  
Actually, all address bits except A19:16 float during the time ALE becomes active (on both 8-  
and 16-bit bus devices). Address-decoding circuitry must be disabled for Interrupt Acknowledge  
bus cycles to prevent erroneous operation.  
Processor  
82C59A  
INTA0  
INTA  
INT  
IR0  
IR7  
INT0  
RD  
RD  
WR  
CS  
A0  
WR  
PCS0  
LA1  
D7:0  
AD7:0  
A1065-0A  
Figure 3-24. Typical 82C59A Interface  
3-27  
 
BUS INTERFACE UNIT  
3.5.4 HALT Bus Cycle  
Suspending the CPU reduces device power consumption and potentially reduces interrupt latency  
time. The HLT instruction initiates two events:  
1. Suspends the Execution Unit.  
2. Instructs the BIU to execute a HALT bus cycle.  
After executing a HALT bus cycle, the BIU suspends operation until one of the following events  
occurs:  
An interrupt is generated.  
A bus HOLD is generated.  
A DMA request is generated.  
A refresh request is generated.  
Figure 3-25 shows the operation of a HALT bus cycle. The address/data bus either floats or drives  
during T1, depending on the next bus cycle to be executed by the BIU. Under most instruction  
sequences, the BIU floats the address/data bus because the next operation would most likely be  
an instruction prefetch. However, if the HALT occurs just after a bus write operation, the ad-  
dress/data bus drives either data or address information during T1. A19:16 continue to drive the  
previous bus cycle information under most instruction sequences (otherwise, they drive the next  
prefetch address). The BIU always operates in the same way for any given instruction sequence.  
The Chip-Select Unit prevents a programmed chip-select from going active during a HALT bus  
cycle. However, chip-selects generated by external decoder circuits must be disabled for HALT  
bus cycles.  
Table 3-5 lists the state of each pin after entering the HALT bus state.  
3-28  
BUS INTERFACE UNIT  
T1  
TI  
TI  
CLKOUT  
ALE  
S2:0  
011  
AD15:0  
[AD7:0]  
Note 1  
Note 1  
[A15:8]  
A19:16  
Note 2  
BHE  
[RFSH = 1]  
NOTES:  
1. The AD15:0 [AD7:0] bus can be floating, driving a previous write data value,  
or driving the next instruction prefetch address value. For an 8-bit device,  
A15:8 drives either the previous bus address value or the next instruction  
prefetch address value.  
2. The A19:16 bus drives either zero (all low) or 8H (all low except A19/S6,  
which can be high if the previous bus cycle was a DMA or refresh operation).  
A1513-0A  
Figure 3-25. HALT Bus Cycle  
Table 3-6. HALT Bus Cycle Pin States  
Pin(s)  
Pin State  
Float  
AD15:0 (AD7:0 for 8-bit)  
A15:8 (8-bit)  
Drive Address  
Drive 8H or Zero  
Drive Last Value  
Drive One  
A19:16  
BHE (16-bit)  
RD, WR, DEN, DT/R, RFSH (8-bit), S2:0  
3-29  
 
BUS INTERFACE UNIT  
3.5.5 Temporarily Exiting the HALT Bus State  
A DMA request, refresh request or bus hold request causes the BIU to exit the HALT bus state  
temporarily. This can occur only when in the Active or Idle power management mode. The BIU  
returns to the HALT bus state after it completes the desired bus operation. However, the BIU  
does not execute another bus HALT cycle (i.e., ALE and bus cycle status are not regenerated).  
Figures 3-26, 3-27 and 3-28 illustrate how the BIU temporarily exits and then returns to the  
HALT bus state.  
CLKOUT  
HOLD  
HLDA  
AD15:0  
AD7:0  
A15:8  
A19:16  
CONTROL  
A1516-0A  
Figure 3-26. Returning to HALT After a HOLD/HLDA Bus Exchange  
3-30  
 
BUS INTERFACE UNIT  
CLKOUT  
ALE  
S2:0  
AD15:0  
[AD7:0]  
Addr  
Addr  
Note 1  
Note 1  
Note 2  
[A15:8]  
A19:16  
Address  
A19 = 1, A18:16 = 0  
Note 3  
BHE  
RFSH  
NOTES:  
1. Previous bus cycle value.  
2. Only occurs for BHE on the first refresh bus cycle after entering HALT.  
3. BHE = 1 for 16-bit device, RFSH = 0 for 8-bit device.  
A1514-0A  
Figure 3-27. Returning to HALT After a Refresh Bus Cycle  
3-31  
 
BUS INTERFACE UNIT  
T4 T1 T2 T3 T4 T1 T2 T3 TI TI TI TI  
CLKOUT  
ALE  
S2:0  
Valid Status  
Addr  
Valid Status  
AD15:0  
[AD7:0]  
Valid Data  
Addr  
Note  
Address  
[A15:8]  
A19:16  
Address  
8H  
Addr  
8H  
Note  
Note  
Addr  
BHE  
[RFSH=1]  
Valid  
Valid  
NOTE: Drives previous bus cycle value.  
A1515-0A  
Figure 3-28. Returning to HALT After a DMA Bus Cycle  
3.5.6 Exiting HALT  
An NMI or any unmasked INTn interrupt causes the BIU to exit HALT. The first bus operations  
to occur after exiting HALT are read cycles to reload the CS:IP registers. Figure 3-29 shows how  
the HALT bus state is exited when an NMI or INTn occurs.  
3-32  
 
BUS INTERFACE UNIT  
CLKOUT  
NMI/INTx  
ALE  
Note 1  
Valid  
S2:0  
AD15:0  
[AD7:0]  
Note 2  
Addr  
Address  
Addr  
[A15:8]  
A19:16  
Note 2  
Note 2  
Note 2  
BHE  
RFSH  
NOTES: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min).  
2. Previous bus cycle value.  
A1517-0A  
Figure 3-29. Exiting HALT  
3.6 SYSTEM DESIGN ALTERNATIVES  
Most system designs require no signals other than those already provided by the BIU. However,  
heavily loaded bus conditions, slow memory or peripheral device performance and off-board de-  
vice interfaces may not be supported directly without modifying the BIU interface. The following  
sections deal with topics to enhance or modify the operation of the BIU.  
3-33  
 
BUS INTERFACE UNIT  
3.6.1 Buffering the Data Bus  
The BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or trans-  
ceivers. The timing relationship of DEN and DT/R is shown in Figure 3-30. The following con-  
ditions require transceivers:  
The capacitive load on the address/data bus gets too large.  
The current load on the address/data bus exceeds device specifications.  
Additional VOL and VOH drive is required.  
A memory or I/O device cannot float its outputs in time to prevent bus contention, even at  
reset.  
T1  
T2  
T3  
T4  
T1  
CLKOUT  
RD,WR  
DT/R  
DEN  
Read Cycle Operation  
A1094-A0  
Figure 3-30. DEN and DT/R Timing Relationships  
The circuit shown in Figure 3-31 illustrates how to use transceivers to buffer the address/data bus.  
The connection between the processor and the transceiver is known as thelocal bus. A connection  
between the transceiver and other memory or I/O devices is known as the buffered bus. A fully  
buffered system has no devices attached to the local bus. A partially buffered system has devices  
on both the local and buffered buses.  
3-34  
   
BUS INTERFACE UNIT  
ALE  
A19:16  
Latch  
Address Bus  
Processor  
AD15:0  
Address  
Memory  
Transceiver  
Data  
Data Bus  
CS  
or  
I/O  
DEN  
Device  
DT/ R  
CPU Local Bus  
Buffered Bus  
A1095-0A  
Figure 3-31. Buffered AD Bus System  
In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered  
system requires that DEN be qualified with another signal to prevent the transceiver from going  
active for local bus accesses. Figure 3-32 illustrates how to use chip-selects to qualify DEN.  
DT/R always connects directly to the transceiver. However, an inverter may be required if the po-  
larity of DT/R does not match the transceiver. DT/R goes low (0) only for memory and I/O read,  
instruction prefetch and interrupt acknowledge bus cycles.  
3-35  
 
BUS INTERFACE UNIT  
8
A
AD15:8  
DEN  
8
D15:8  
B
OE  
T
MCS0  
Buffer  
Buffered  
Data  
Bus  
8
A
AD7:0  
8
OE  
T
B
D7:0  
DT/R  
Buffer  
8
Local  
Data  
Bus  
8
A1058-0B  
Figure 3-32. Qualifying DEN with Chip-Selects  
3.6.2 Synchronizing Software and Hardware Events  
The execution sequence of a program and hardware events occurring within a system are often  
asynchronous to each other. In some systems there may be a requirement to suspend program ex-  
ecution until an event (or events) occurs, then continue program execution.  
One way to synchronize software execution with hardware events requires the use of interrupts.  
Executing a HALT instruction suspends program execution until an unmasked interrupt occurs.  
However, there is a delay associated with servicing the interrupt before program execution can  
proceed. Using the WAIT instruction removes the delay associated with servicing interrupts.  
3-36  
 
BUS INTERFACE UNIT  
The WAIT instruction suspends program execution until one of two events occurs: an interrupt  
is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does  
not require that program execution be transferred to a new location (i.e., an interrupt routine is  
not executed). In processing the WAIT instruction, program execution remains suspended as long  
as TEST remains high (at least until an interrupt occurs). When TEST is sampled low, program  
execution resumes.  
The TEST input and WAIT instruction provide a mechanism to delay program execution until a  
hardware event occurs, without having to absorb the delay associated with servicing an interrupt.  
3.6.3 Using a Locked Bus  
To address the problems of controlling accesses to shared resources, the BIU provides a hardware  
LOCK output. The execution of a LOCK prefix instruction activates the LOCK output.  
LOCK goes active in phase 1 of T1 of the first bus cycle following execution of the LOCK prefix  
instruction. It remains active until phase 1 of T1 of the first bus cycle following the execution of  
the instruction following the LOCK prefix. To provide bus access control in multiprocessor sys-  
tems, the LOCK signal should be incorporated into the system bus arbitration logic residing in  
the CPU.  
During normal multiprocessor system operation, priority of the shared system bus is determined  
by the arbitration circuits on a cycle by cycle basis. As each CPU requires a transfer over the sys-  
tem bus, it requests access to the bus via its resident bus arbitration logic. When the CPU gains  
priority (determined by the system bus arbitration scheme and any associated logic), it takes con-  
trol of the bus, performs its bus cycle and either maintains bus control, voluntarily releases the  
bus or is forced off the bus by the loss of priority.  
The lock mechanism prevents the CPU from losing bus control (either voluntarily or by force)  
and guarantees that the CPU can execute multiple bus cycles without intervention and possible  
corruption of the data by another CPU. A classic use of the mechanism is the “TEST and SET  
semaphore,” during which a CPU must read from a shared memory location and return data to  
the location without allowing another CPU to reference the same location during the test and set  
operations.  
Another application of LOCK for multiprocessor systems consists of a locked block move, which  
allows high speed message transfer from one CPU’s message buffer to another. During the locked  
instruction (i.e., while LOCK is active), a bus hold, DMA or refresh request is recorded, but is  
not acknowledged until completion of the locked instruction. However, LOCK has no effect on  
interrupts. As an example, a locked HALT instruction causes bus hold, DMA or refresh bus re-  
quests to be ignored, but still allows the CPU to exit the HALT state on an interrupt.  
3-37  
BUS INTERFACE UNIT  
In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre-  
cede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are  
not acknowledged until the instruction following the prefix completes (except for instructions  
that are servicing interrupts during their execution, such as HALT, WAIT and repeated string  
primitives).Note that multiple prefix bytes can precede an instruction.  
Another example is a string primitive preceded by the repetition prefix (REP), which can be in-  
terrupted after each execution of the string primitive, even if the REP prefix is combined with the  
LOCK prefix. This prevents interrupts from being locked out during a block move or other re-  
peated string operations. However, bus hold, DMA and refresh requests remain locked out until  
LOCK is removed (either when the block operation completes or after an interrupt occurs.  
3.6.4 Using the Queue Status Signals  
Older-generation devices require the queue status signals to interface with an 8087 math copro-  
cessor. Newer devices do not require these signals because they use the 80187 math coprocessor,  
which has an I/O port interface similar to that of a peripheral device.  
The queue status signals, QS0 and QS1, indicate the state of the internal queue (Table 3-7). Since  
the Execution Unit can remove information from the queue on any clock boundary, the queue sta-  
tus pins may change state on every phase 1 clock edge (Figure 3-33). Although these signals can-  
not be related to any specific T-state, the relationship between the queue status signals and BIU  
operation always remains the same for a given instruction sequence.  
QS0 and QS1 are alternate functions of ALE and WR, respectively. To enable QS0 and QS1, you  
must connect the RD pin directly to ground. In this case, RD, WR and ALE are no longer avail-  
able and must be generated by external hardware such as an 82C88 or a programmable logic de-  
vice.  
Table 3-7. Queue Status Signal Decoding  
QS1  
QS0  
Queue Status  
0
0
No queue operation occurred.  
0
1
1
0
The first byte of a new instruction was removed from the queue.  
The queue was reinitialized. All prefetch information was flushed; the BIU must begin  
prefetching new queue information.  
1
1
A subsequent byte of an instruction was removed from the queue. The current instruction  
contains multiple opcode bytes or immediate data.  
3-38  
 
BUS INTERFACE UNIT  
CLKOUT  
QS0, QS1  
A1059-0A  
Figure 3-33. Queue Status Timing  
3.7 MULTI-MASTER BUS SYSTEM DESIGNS  
The BIU supports protocols for transferring control of the local bus between itself and other de-  
vices capable of acting as bus masters. To support such a protocol, the BIU uses a hold request  
input (HOLD) and a hold acknowledge output (HLDA) as bus transfer handshake signals. To  
gain control of the bus, a device asserts the HOLD input, then waits until the HLDA output goes  
active before driving the bus. After HLDA goes active, the requesting device can take control of  
the local bus and remains in control of the bus until HOLD is removed.  
3.7.1 Entering Bus HOLD  
In responding to the hold request input, the BIU floats the entire address and data bus, and many  
of the control signals. Figure 3-34 illustrates the timing sequence when acknowledging the hold  
request. Table 3-8 lists the states of the BIU pins when HLDA is asserted. All device pins not  
mentioned in Table 3-8 or shown in Figure 3-34 remain either active (e.g., CLKOUT and  
T1OUT) or inactive (e.g., UCS and INTA). Refer to the data sheet for specific details of pin func-  
tions during a bus hold.  
3-39  
 
BUS INTERFACE UNIT  
CLKOUT  
1
HOLD  
4
2
HLDA  
3
AD15:0  
DEN  
Float  
A19:16  
RD, WR,  
DT/R,  
Float  
BHE, S2:0  
LOCK  
NOTES:  
1. T  
2. T  
3. T  
4. T  
: HOLD input to clock low  
: Clock high to output float  
: Clock low to output float  
HVCL  
CHCZ  
CLAZ  
: Clock low to HLDA high  
CLHAV  
A1518-0A  
Figure 3-34. Timing Sequence Entering HOLD  
Table 3-8. Signal Condition Entering HOLD  
Signal  
HOLD Condition  
A19:16, S2:0, RD, WR, DT/R, BHE (RFSH), LOCK  
AD15:0 (16-bit), AD7:0 (8-bit), A15:8 (8-bit), DEN  
These signals float one-half clock before HLDA  
is generated (i.e., phase 2).  
which HLDA is generated (i.e., phase 1).  
3.7.1.1  
HOLD Bus Latency  
The duration between the time that the external device asserts HOLD and the time that the BIU  
asserts HLDA is known as bus latency. In Figure 3-34, the two-clock delay between HOLD and  
HLDA represents the shortest bus latency. Normally this occurs only if the bus is idle or halted  
or if the bus hold request occurs just before the BIU begins another bus cycle.  
3-40  
   
BUS INTERFACE UNIT  
The major factors that influence bus latency are listed below (in order from longest delay to short-  
est delay).  
1. Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be  
serviced.  
2. Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot be  
serviced. Performing a locked move string operation can take several thousands of clocks.  
3. Completion of Current Bus Cycle — A bus hold request cannot be serviced until the  
current bus cycle completes. A bus hold request will not separate bus cycles required to  
move odd-aligned word data. Also, bus cycles with long wait states will delay the  
servicing of a bus hold request.  
4. Interrupt Acknowledge Bus Cycle — A bus hold request is not serviced until after an  
INTA bus cycle has completed. An INTA bus cycle drives LOCK active.  
5. DMA and Refresh Bus Cycles — A bus hold request is not serviced until after the DMA  
request or refresh bus cycle has completed. Refresh bus cycles have a higher priority than  
hold bus requests. A bus hold request cannot separate the bus cycles associated with a  
DMA transfer (worst case is an odd-aligned transfer, which takes four bus cycles to  
complete).  
3.7.1.2  
Refresh Operation During a Bus HOLD  
Under normal operating conditions, once HLDA has been asserted it remains asserted until  
HOLD is removed. However, when a refresh bus request is generated, the HLDA output is re-  
moved (driven low) to signal the need for the BIU to regain control of the local bus. The BIU does  
not gain control of the bus until HOLD is removed. This procedure prevents the BIU from just  
arbitrarily regaining control of the bus.  
Figure 3-35 shows the timing associated with the occurrence of a refresh request while HLDA is  
active. Note that HLDA can be as short as one clock in duration. This happens when a refresh  
request occurs just after HLDA is granted. A refresh request has higher priority than a bus hold  
request; therefore, when the two occur simultaneously, the refresh request occurs before HLDA  
becomes active.  
3-41  
BUS INTERFACE UNIT  
CLKOUT  
1
3
4
HOLD  
HLDA  
2
5
AD15:0  
DEN  
A19:16  
RD, WR,  
BHE, S2:0  
DT/R,  
5
LOCK  
NOTES:  
1. HLDA is deasserted, signaling need to run refresh bus cycle.  
2. External bus master terminates use of the bus.  
3. HOLD deasserted.  
4. Hold may be reasserted after one clock.  
5. BIU runs refresh cycle.  
A1061-0A  
Figure 3-35. Refresh Request During HOLD  
The device requesting a bus hold must be able to detect a HLDA pulse that is one clock in dura-  
tion. A bus lockup (hang) condition can result if the requesting device fails to detect the short  
HLDA pulse and continues to wait for HLDA to be asserted while the BIU waits for HOLD to be  
deasserted. The circuit shown in Figure 3-36 can be used to latch HLDA.  
3-42  
 
BUS INTERFACE UNIT  
+5  
PRE  
CLR  
D
Latched HLDA  
Q
HLDA  
RESET  
HOLD  
A1535-0A  
Figure 3-36. Latching HLDA  
The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain  
the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is  
complete, the BIU will release the bus and generate HLDA.  
3.7.2 Exiting HOLD  
Figure 3-37 shows the timing associated with exiting the bus hold state. Normally a bus operation  
(e.g., an instruction prefetch) occurs just after HOLD is released. In a 16-bit bus system, the upper  
half of the bus (D15:8) floats.  
3-43  
 
BUS INTERFACE UNIT  
CLKOUT  
1
2
4
3
5
HOLD  
HLDA  
AD15:0  
DEN  
RD, WR, BHE,  
DT/R, S2:0,  
A19:16, LOCK  
NOTES:  
1. T  
2.  
: HOLD recognition setup to clock low  
: HOLD internally synchronized  
HVCL  
3. T  
4. T  
5. T  
: Clock low to HLDA low  
: Clock high to signal active (high or low)  
: Clock low to signal active (high or low)  
CLHAV  
CHCV  
CLAV  
A1063-0A  
Figure 3-37. Exiting HOLD  
3.8 BUS CYCLE PRIORITIES  
The BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals  
(e.g., Interrupt Control Unit) and external bus masters (i.e., bus hold requests). The list below  
summarizes the priorities for all bus cycle requests (from highest to lowest).  
1. Instruction execution read/write following a non-pipelined effective address calculation.  
2. Refresh bus cycles.  
3. Bus hold request.  
4. Single step interrupt vectoring sequence.  
5. Non-Maskable interrupt vectoring sequence.  
3-44  
 
BUS INTERFACE UNIT  
6. Internal error (e.g., divide error, overflow) interrupt vectoring sequence.  
7. Hardware (e.g., INT0, DMA) interrupt vectoring sequence.  
8. 80C187 Math Coprocessor error interrupt vectoring sequence.  
9. DMA bus cycles.  
10. General instruction execution. This category includes read/write operations following a  
pipelined effective address calculation, vectoring sequences for software interrupts and  
numerics code execution. The following points apply to sequences of related execution  
cycles.  
— The second read/write cycle of an odd-addressed word operation is inseparable from  
the first bus cycle.  
— The second read/write cycle of an instruction with both load and store accesses (e.g.,  
XCHG) can be separated from the first cycle by other bus cycles.  
— Successive bus cycles of string instructions (e.g., MOVS) can be separated by other bus  
cycles.  
— When a locked instruction begins, its associated bus cycles become the highest priority  
and cannot be separated (or preempted) until completed.  
11. Bus cycles necessary to fill the prefetch queue.  
3-45  
4
Peripheral Control  
Block  
CHAPTER 4  
PERIPHERAL CONTROL BLOCK  
All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers  
within an integrated Peripheral Control Block (PCB). The peripheral control registers are physi-  
cally located in the peripheral devices they control, but they are addressed as a single block of  
registers. The Peripheral Control Block encompasses 256 contiguous bytes and can be located on  
any 256-byte boundary of memory or I/O space. The PCB Relocation Register, which is also lo-  
cated within the Peripheral Control Block, controls the location of the PCB.  
4.1 PERIPHERAL CONTROL REGISTERS  
Each of the integrated peripherals’ control and status registers is located at a fixed offset above  
the programmed base location of the Peripheral Control Block (see Table 4-1). These registers  
are described in the chapters that cover the associated peripheral. “Accessing the Peripheral Con-  
trol Block” on page 4-4 discusses how the registers are accessed and outlines considerations for  
reading and writing them.  
4.2 PCB RELOCATION REGISTER  
In addition to control registers for the integrated peripherals, the Peripheral Control Block con-  
tains the PCB Relocation Register (Figure 4-1). The Relocation Register is located at a fixed off-  
set within the Peripheral Control Block (Table 4-1). If the Peripheral Control Block is moved, the  
Relocation Register also moves.  
The PCB Relocation Register allows the Peripheral Control Block to be relocated to any 256-byte  
boundary within memory or I/O space. The Memory I/O bit (MEM) selects either memory space  
or I/O space, and the R19:8 bits specify the starting (base) address of the PCB. The remaining bit,  
Escape Trap (ET), controls access to the math coprocessor interface.  
“Setting the PCB Base Location” on page 4-6 describes how to set the base location and outlines  
some restrictions on the Peripheral Control Block location.  
4-1  
PERIPHERAL CONTROL BLOCK  
Register Name:  
PCB Relocation Register  
RELREG  
Register Mnemonic:  
Register Function:  
Relocates the PCB within memory or I/O space.  
15  
0
E
T
S
L
M
E
M
R
1
9
R
1
8
R
1
7
R
1
6
R
1
5
R
1
4
R
1
3
R
1
2
R
1
1
R
1
0
R
9
R
8
A1262-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
ET  
Escape Trap  
0
If ET is set, the CPU will trap when an ESC  
instruction is executed.  
SL  
Slave/Master  
Memory I/O  
0
0
If SL is set, the Interrupt Control Unit operates in  
slave mode. If SL is clear, it operates in master  
mode.  
MEM  
R19:8  
If MEM is set, the PCB is located in memory  
space. If MEM is clear, the PCB is located in I/O  
space.  
PCB Base  
Address  
Upper Bits  
0FFH  
R19:8 define the upper address bits of the PCB  
base address. All lower bits are zero. R19:16 are  
ignored when the PCB is mapped to I/O space.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 4-1. PCB Relocation Register  
4-2  
 
PERIPHERAL CONTROL BLOCK  
Table 4-1. Peripheral Control Block  
PCB  
Offset  
PCB  
Offset  
PCB  
Offset  
PCB  
Offset  
Function  
Function  
Function  
Function  
00H  
02H  
04H  
06H  
08H  
0AH  
0CH  
0EH  
10H  
12H  
14H  
16H  
18H  
1AH  
1CH  
1EH  
20H  
22H  
24H  
26H  
28H  
2AH  
2CH  
2EH  
30H  
32H  
34H  
36H  
38H  
3AH  
3CH  
3EH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
EOI  
40H  
42H  
44H  
46H  
48H  
4AH  
4CH  
4EH  
50H  
52H  
54H  
56H  
58H  
5AH  
5CH  
5EH  
60H  
62H  
64H  
66H  
68H  
6AH  
6CH  
6EH  
70H  
72H  
74H  
76H  
78H  
7AH  
7CH  
7EH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
T0CNT  
80H  
82H  
84H  
86H  
88H  
8AH  
8CH  
8EH  
90H  
92H  
94H  
96H  
98H  
9AH  
9CH  
9EH  
A0H  
A2H  
A4H  
A6H  
A8H  
AAH  
ACH  
AEH  
B0H  
B2H  
B4H  
B6H  
B8H  
BAH  
BCH  
BEH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
UMCS  
C0H  
C2H  
C4H  
C6H  
C8H  
CAH  
CCH  
CEH  
D0H  
D2H  
D4H  
D6H  
D8H  
DAH  
DCH  
DEH  
E0H  
E2H  
E4H  
E6H  
E8H  
EAH  
ECH  
EEH  
F0H  
F2H  
F4H  
F6H  
F8H  
FAH  
FCH  
FEH  
D0SRCL  
D0SRCH  
D0DSTL  
D0DSTH  
D0TC  
D0CON  
Reserved  
Reserved  
D1SRCL  
D1SRCH  
D1DSTL  
D1DSTH  
D1TC  
T0CMPA  
T0CMPB  
T0CON  
T1CNT  
T1CMPA  
T1CMPB  
T1CON  
D1CON  
Reserved  
Reserved  
RFBASE  
RFTIME  
RFCON  
T2CNT  
T2CMPA  
Reserved  
T2CON  
LMCS  
POLL  
PACS  
POLLSTS  
IMASK  
MMCS  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PWRSAV  
PWRCON  
Reserved  
STEPID  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
MPCS  
PRIMSK  
INSERV  
REQST  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
INSTS  
TCUCON  
DMA0CON  
DMA1CON  
I0CON  
Reserved  
Reserved  
Reserved  
RELREG  
I1CON  
I2CON  
I3CON  
4-3  
 
PERIPHERAL CONTROL BLOCK  
4.3 RESERVED LOCATIONS  
Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused  
locations are reserved. Reading from these locations yields an undefined result. If reserved reg-  
isters are written (for example, during a block MOV instruction) they must be set to 0H.  
NOTE  
Failure to follow this guideline could result in incompatibilities with future  
80C186 Modular Core family products.  
4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK  
All communication between integrated peripherals and the Modular CPU Core occurs over a spe-  
cial bus, called the F-Bus, which always carries 16-bit data. The Peripheral Control Block, like  
all integrated peripherals, is always accessed 16 bits at a time.  
4.4.1  
Bus Cycles  
The processor runs an external bus cycle for any memory or I/O cycle accessing a location within  
the Peripheral Control Block. Address, data and control information is driven on the external pins  
as with an ordinary bus cycle. Information returned by an external device is ignored, even if the  
access does not correspond to the location of an integrated peripheral control register. This is also  
true for the 80C188 Modular Core family, except that word accesses made to integrated registers  
are performed in two bus cycles.  
4.4.2  
READY Signals and Wait States  
The processor generates an internal READY signal whenever an integrated peripheral is access-  
ed. External READY is ignored. READY is also generated if an access is made to a location with-  
in the Peripheral Control Block that does not correspond to an integrated peripheral control  
register. For accesses to timer control and counting registers, the processor inserts one wait state.  
This is required to properly multiplex processor and counter element accesses to the timer control  
registers. For accesses to the remaining locations in the Peripheral Control Block, the processor  
does not insert wait states.  
4-4  
 
PERIPHERAL CONTROL BLOCK  
4.4.3  
F-Bus Operation  
The F-Bus functions differently than the external data bus for byte and word accesses. All write  
transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the in-  
struction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control  
Block register at location [DX]. If DX were an odd location, AL would be placed in [DX] and  
AH would be placed at [DX–1]. A word operation to an odd address would write [DX] and [DX–  
1] with AL and AH, respectively. This differs from normal external bus operation where un-  
aligned word writes modify [DX] and [DX+1]. In summary, do not use odd-aligned byte or word  
writes to the PCB.  
Aligned word reads work normally. Unaligned word reads work differently. For example, IN AX,  
DX (DX is odd) will transfer [DX] into AL and [DX–1] into AH. Byte reads from even or odd  
addresses work normally, but only a byte will be read. For example, IN AL, DX will not transfer  
[DX] into AX (only AL is modified).  
No problems will arise if the following recommendations are adhered to.  
Word reads  
Byte reads  
Aligned word reads of the PCB work normally. Access only even-  
aligned words with IN AX, DX or MOV word register, even PCB  
address.  
Byte reads of the PCB work normally. Beware of reading word-wide  
PCB registers that may change value between successive reads (e.g.,  
timer count value).  
Word writes  
Always write even-aligned words to the PCB. Writing an odd-  
aligned word will give unexpected results.  
For the 80C186 Modular Core, use either  
– OUT DX, AX or  
– OUT DX, AL or  
– MOV even PCB address, word register.  
For the 80C188 Modular Core, using OUT DX, AX will perform an  
unnecessary bus cycle and is not recommended. Use either  
– OUT DX, AL or  
– MOV even-aligned byte PCB address, byte register low byte.  
Byte writes  
Always use even-aligned byte writes to the PCB. Even-aligned byte  
writes will modify the entire word PCB location. Do not perform  
unaligned byte writes to the PCB.  
4-5  
PERIPHERAL CONTROL BLOCK  
4.4.3.1  
Writing the PCB Relocation Register  
Whenever mapping the Peripheral Control Block to another location, the user should program the  
Relocation Register with a byte write (i.e., OUT DX, AL). Internally, the Relocation Register is  
written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit  
bus cycle. If a word instruction (i.e., OUT DX, AX) is used with an 80C188 Modular Core family  
member, the Relocation Register is written on the first bus cycle. The Bus Interface Unit then runs  
an unnecessary second bus cycle. The address of the second bus cycle is no longer within the con-  
trol block, since the Peripheral Control Block was moved on the first cycle. External READY  
must now be generated to complete the cycle. For this reason, we recommend byte operations for  
the Relocation Register.  
4.4.3.2  
Accessing the Peripheral Control Registers  
Byte instructions should be used for the registers in the Peripheral Control Block of an 80C188  
Modular Core family member. This requires half the bus cycles of word operations. Byte opera-  
tions are valid only for even-addressed writes to the Peripheral Control Block. A word read (e.g.,  
IN AX, DX) must be performed to read a 16-bit Peripheral Control Block register when possible.  
4.4.3.3  
Accessing Reserved Locations  
Unused locations are reserved. If a write is made to these locations, a bus cycle occurs, but data  
is not stored. If a subsequent read is made to the same location, the value written is not read back.  
If reserved registers are written (for example, during a block MOV instruction) they must be  
cleared to 0H.  
NOTE  
Failure to follow this guideline could result in incompatibilities with future  
80C186 Modular Core family products.  
4.5 SETTING THE PCB BASE LOCATION  
Upon reset, the PCB Relocation Register (see Figure 4-1 on page 4-2) contains the value 00FFH,  
which causes the Peripheral Control Block to be located at the top of I/O space (0FF00H to  
0FFFFH). Writing the PCB Relocation Register allows the user to change that location.  
4-6  
 
PERIPHERAL CONTROL BLOCK  
As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the  
user would program the PCB Relocation Register with the value 1100H. Since the Relocation  
Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset.  
NOTE  
Due to an internal condition, external ready is ignored if the device is  
configured in Cascade mode and the Peripheral Control Block (PCB) is  
located at 0000H in I/O space. In this case, wait states cannot be added to  
interrupt acknowledge bus cycles. However, you can add wait states to  
interrupt acknowledge cycles if the PCB is located at any other address.  
4.5.1 Considerations for the 80C187 Math Coprocessor Interface  
Systems using the 80C187 math coprocessor interface must not relocate the Peripheral Control  
Block to location 0000H in I/O space. The 80C187 interface uses I/O locations 0F8H through  
0FFH. If the Peripheral Control Block resides in these locations, the processor communicates  
with the Peripheral Control Block, not the 80C187 interface circuitry.  
NOTE  
If the PCB is located at 0000H in I/O space and access to the math coprocessor  
interface is enabled (the Escape Trap bit is clear), a numerics (ESC) instruction  
causes indeterminate system operation.  
Since the 8-bit bus version of the device does not support the 80C187, it automatically traps an  
ESC instruction to the Type 7 interrupt, regardless of the state of the Escape Trap (ET) bit.  
For details on the math coprocessor interface, see Chapter 11, “Math Coprocessing.”  
4-7  
5
ClockGenerationand  
Power Management  
CHAPTER 5  
CLOCK GENERATION AND POWER  
MANAGEMENT  
The clock generation and distribution circuits provide uniform clock signals for the Execution  
Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family  
processors have additional logic that controls the clock signals to provide power management  
functions.  
5.1 CLOCK GENERATION  
The clock generation circuit (Figure 5-1) includes a crystal oscillator, a divide-by-two counter  
and power-save and reset circuitry. See “Power-Save Mode” on page 5-11 for a discussion of  
Power-Save mode as a power management option.  
Schmitt Trigger  
"Squares-up" CLKIN  
Power Save  
X1  
1
2
Internal  
Phase  
Clocks  
÷ 2  
Clock  
Clock  
Divider  
Phase  
Drivers  
To CLKOUT  
X2  
Reset Circuitry  
Internal Reset  
RES  
A1519-0A  
Figure 5-1. Clock Generator  
5.1.1 Crystal Oscillator  
The internal oscillator is a parallel resonant Pierce oscillator, a specific form of the common  
phase shift oscillator.  
5-1  
 
CLOCK GENERATION AND POWER MANAGEMENT  
5.1.1.1  
Oscillator Operation  
A phase shift oscillator operates through positive feedback, where a non-inverted, amplified ver-  
sion of the input connects back to the input. A 360° phase shift around the loop will sustain the  
feedback in the oscillator. The on-chip inverter provides a 180° phase shift. The combination of  
the inverter’s output impedance and the first load capacitor (see Figure 5-2) provides another 90°  
phase shift. At resonance, the crystal becomes primarily resistive. The combination of the crystal  
and the second load capacitor provides the final 90° phase shift. Above and below resonance, the  
crystal is reactive and forces the oscillator back toward the crystal’s nominal frequency.  
Z = Inverter Output Z  
0
90˚  
90˚  
180˚  
NOTE:  
At resonance, the crystal is essentially resistive.  
Below resonance, the crystal is capacitive.  
A1125-0A  
Figure 5-2. Ideal Operation of Pierce Oscillator  
Figure 5-3 shows the actual microprocessor crystal connections. For low frequencies, crystal ven-  
dors offer fundamental mode crystals. At higher frequencies, a third overtone crystal is the only  
choice. The external capacitors, CX1 at X1 and CX2 at X2, together with stray capacitance, form  
the load. A third overtone crystal requires an additional inductor L1 and capacitor C1 to select the  
third overtone frequency and reject the fundamental frequency. See “Selecting Crystals” on page  
5-5 for a more detailed discussion of crystal vibration modes.  
5-2  
 
CLOCK GENERATION AND POWER MANAGEMENT  
Choose C1 and L1 component values in the third overtone crystal circuit to satisfy the following  
conditions:  
The LC components form an equivalent series resonant circuit at a frequency below the  
fundamental frequency. This criterion makes the circuit inductive at the fundamental  
frequency. The inductive circuit cannot make the 90° phase shift and oscillations do not  
take place.  
The LC components form an equivalent parallel resonant circuit at a frequency about  
halfway between the fundamental frequency and the third overtone frequency. This  
criterion makes the circuit capacitive at the third overtone frequency, necessary for oscil-  
lation.  
The two capacitors and inductor at X2, plus some stray capacitance, approximately equal  
the 20 pF load capacitor, CX2, used alone in the fundamental mode circuit.  
(a)  
(b)  
(c)  
Fundamental  
Mode Circuit  
Third Overtone  
Mode Circuit  
Third Overtone Mode  
(Equivalent Circuit)  
C
X1  
X1  
X1  
X2  
C
L
X2  
1
L
1
X2  
C
C
C
C
1
X2  
X1  
X2  
L
= (See text)  
C
= C  
X2  
= 20pF  
C
= 200pF  
1
1
X1  
A1520-0A  
Figure 5-3. Crystal Connections to Microprocessor  
Choosing C1 as 200 pF (at least 10 times the value of the load capacitor) simplifies the circuit  
analysis. At the series resonance, the capacitance connected to L1 is 200 pF in series with 20 pF.  
The equivalent capacitance is still about 20 pF and the equation in Figure 5-4(a) yields the series  
resonant frequency.  
5-3  
 
CLOCK GENERATION AND POWER MANAGEMENT  
To examine the parallel resonant frequency, refer to Figure 5-3(c), an equivalent circuit to Figure  
5-3(b). The capacitance connected to L1 is 200 pF in parallel with 20 pF. The equivalent capaci-  
tance is still about 200 pF (within 10%) and the equation in Figure 5-4(a) now yields the parallel  
resonant frequency.  
(a) Series or Parallel Resonant Frequency  
(b) Equivalent Capacitance  
ω2C1Cx2  
L1 C1 Cx2  
1
f = ------------------------  
C eq = -----------------------------------------------------------  
ω2C1L1 1  
2π L1C1  
Figure 5-4. Equations for Crystal Calculations  
The equation in Figure 5-4(b) yields the equivalent capacitance Ceq at the operation frequency.  
The desired operation frequency is the third overtone frequency marked on the crystal. Optimiz-  
ing equations for the above three criteria yields Table 5-1. This table shows suggested standard  
inductor values for various processor frequencies. The equivalent capacitance is about 15 pF.  
Table 5-1. Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit  
CLKOUT  
Frequency (MHz)  
Third-Overtone Crystal  
Frequency (MHz)  
Inductor L  
1
Values (µH)  
10  
12  
16  
20  
20  
25  
32  
40  
10.0, 12.0, 15.0  
6.8, 8.2, 10.0  
3.9, 4.7, 5.6  
2.2, 2.7, 3.3  
5-4  
   
CLOCK GENERATION AND POWER MANAGEMENT  
5.1.1.2  
Selecting Crystals  
When specifying crystals, consider these parameters:  
Resonance and Load Capacitance — Crystals carry a parallel or series resonance specifi-  
cation. The two types do not differ in construction, just in test conditions and expected  
circuit application. Parallel resonant crystals carry a test load specification, with typical  
load capacitance values of 15, 18 or 22 pF. Series resonant crystals do not carry a load  
capacitance specification. You may use a series resonant crystal with the microprocessor,  
even though the circuit is parallel resonant. However, it will vibrate at a frequency slightly  
(on the order of 0.1%) higher than its calibration frequency.  
Vibration Mode — The vibration mode is either fundamental or third overtone. Crystal  
thickness varies inversely with frequency. Vendors furnish third or higher overtone crystals  
to avoid manufacturing very thin, fragile quartz crystal elements. At a given frequency, an  
overtone crystal is thicker and more rugged than its fundamental mode counterpart. Below  
20 MHz, most crystals are fundamental mode. In the 20 to 32 MHz range, you can purchase  
both modes. You must know the vibration mode to know whether to add the LC circuit at  
X2.  
Equivalent Series Resistance (ESR) — ESR is proportional to crystal thickness, inversely  
proportional to frequency. A lower value gives a faster startup time, but the specification is  
usually not important in microprocessor applications.  
Shunt Capacitance — A lower value reduces ESR, but typical values such as 7 pF will work  
fine.  
Drive Level — Specifies the maximum power dissipation for which the manufacturer  
calibrated the crystal. It is proportional to ESR, frequency, load and VCC. Disregard this  
specification unless you use a third overtone crystal whose ESR and frequency will be  
relatively high. Several crystal manufacturers stock a standard microprocessor crystal line.  
Specifying a “microprocessor grade” crystal should ensure that the rated drive level is a  
couple of milliwatts with 5-volt operation.  
Temperature Range — Specifies an operating range over which the frequency will not vary  
beyond a stated limit. Specify the temperature range to match the microprocessor  
temperature range.  
Tolerance — The allowable frequency deviation at a particular calibration temperature,  
usually 25° C. Quartz crystals are more accurate than microprocessor applications call for;  
do not pay for a tighter specification than you need. Vendors quote frequency tolerance in  
percentage or parts per million (ppm). Standard microprocessor crystals typically have a  
frequency tolerance of 0.01% (100 ppm). If you use these crystals, you can usually  
disregard all the other specifications; these crystals are ideal for the 80C186 Modular Core  
family.  
5-5  
 
CLOCK GENERATION AND POWER MANAGEMENT  
An important consideration when using crystals is that the oscillator start correctly over the volt-  
age and temperature ranges expected in operation. Observe oscillator startup in the laboratory.  
Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus sta-  
bility. In your experiments, consider stray capacitance and scope loading effects.  
For help in selecting external oscillator components for unusual circumstances, count on the crys-  
tal manufacturer as your best resource. Using low-cost ceramic resonators in place of crystals is  
possible if your application will tolerate less precise frequencies.  
5.1.2 Using an External Oscillator  
The microprocessor’s on-board clock oscillator allows the use of a relatively low cost crystal.  
However, the designer may also use a “canned oscillator” or other external frequency source.  
Connect the external frequency input (EFI) signal directly to the oscillator X1 input. Leave X2  
unconnected. This oscillator input drives the internal divide-by-two counter directly, generating  
the CPU clock signals. The external frequency input can have practically any duty cycle, provid-  
ed it meets the minimum high and low times stated in the data sheet. Selecting an external clock  
oscillator is more straightforward than selecting a crystal.  
5.1.3 Output from the Clock Generator  
The crystal oscillator output drives a divide-by-two circuit, generating a 50% duty cycle clock for  
the processor’s integrated components. All processor timings refer to this clock, available exter-  
nally at the CLKOUT pin. CLKOUT changes state on the high-to-low transition of the X1 signal,  
even during reset and bus hold.  
In a CMOS circuit, significant current flows only during logic level transitions. Since the micro-  
processor consists mostly of clocked circuitry, the clock distribution is the basis of power man-  
agement.  
5.1.4 Reset and Clock Synchronization  
The clock generator provides a system reset signal (RESET). The RES input generates RESET  
and the clock generator synchronizes it to the CLKOUT signal.  
A Schmitt trigger in the RES input ensures that the switch point for a low-to-high transition is  
greater than the switch point for a high-to-low transition. The processor must remain in reset a  
minimum of 4 CLKOUT cycles after VCC and CLKOUT stabilize. The hysteresis allows a simple  
RC circuit to drive the RES input (see Figure 5-5). Typical applications can use about 100 milli-  
seconds as an RC time constant.  
5-6  
CLOCK GENERATION AND POWER MANAGEMENT  
Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES  
input during power supply and oscillator startup. The processor’s pins assume their reset pin  
states a maximum of 28 X1 periods after X1 and VCC stabilize. Assert RES 4 additional X1 peri-  
ods after the device pins assume their reset states.  
Applying RES when the device is running constitutes a warm reset (see Figure 5-7). In this case,  
assert RES for at least 4 CLKOUT periods. The device pins will assume their reset states on the  
second falling edge of X1 following the assertion of RES.  
V
cc  
-t  
RC  
50 k typical  
V
= V 1 - e  
c(t)  
RESET IN  
RES  
1µf typical  
A1521-0A  
Figure 5-5. Simple RC Circuit for Powerup Reset  
The processor exits reset identically in both cases. The falling RES edge generates an internal RE-  
SYNC pulse (see Figure 5-8), resynchronizing the divide-by-two internal phase clock. The clock  
generator samples RES on the falling X1 edge. If RES is sampled high while CLKOUT is high,  
the processor forces CLKOUT low for the next two X1 cycles. The clock essentially “skips a  
beat” to synchronize the internal phases. If RES is sampled high while CLKOUT is low, CLK-  
OUT is already in phase.  
5-7  
 
CLOCK GENERATION AND POWER MANAGEMENT  
X1  
V
cc  
Vcc and X1 stable to output valid 28 X1 periods (max)  
CLKOUT  
UCS, LCS  
MCS3:0, NCS  
TMR OUT0  
TMR OUT1  
PCS6:0  
HLDA, ALE  
A19:16  
AD15:0, S2:0  
RD, WR, DEN  
DT/R, LOCK  
RES  
RESET  
V
and X1 stable to RES high,  
RES high to  
first bus activity,  
7 CLKOUT periods.  
cc  
approximately 32 X1 periods.  
NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low.  
A1508-0B  
Figure 5-6. Cold Reset Waveform  
5-8  
 
CLOCK GENERATION AND POWER MANAGEMENT  
X1  
CLKOUT  
UCS, LCS  
MCS3:0  
PCS6:0,NCS  
TMR OUT0  
TMR OUT1  
HLDA, ALE  
A19/S6:  
A16  
AD15:0  
S2:0, RD  
WR, DEN  
DT/R  
LOCK  
RES  
RESET  
RES high  
to first bus  
activity 7  
CLKOUT  
periods.  
Minimum RES low  
time 4 CLKOUT  
periods.  
A1522-0B  
Figure 5-7. Warm Reset Waveform  
At the second falling CLKOUT edge after sampling RES inactive, the processor deasserts RE-  
SET. Bus activity starts 6½ CLKOUT periods after recognition of RES in the logic high state. If  
an alternate bus master asserts HOLD during reset, the processor immediately asserts HLDA and  
will not prefetch instructions.  
5-9  
 
CLOCK GENERATION AND POWER MANAGEMENT  
X1  
5
2
RES  
1
RESYNC  
(Internal)  
1
CLKOUT  
RESET  
2
3
6
4
NOTES:  
1. Setup of RES to falling X1.  
2. RESYNC pulse generated.  
3. RESYNC drives CLKOUT high, resynchronizing the clock generator.  
4. RESET goes active.  
5. RES allowed to go inactive after minimum 4 CLKOUT cycles.  
6. RESET goes inactive 1 1/2 CLKOUT cycles after RES sampled inactive.  
A1523-0A  
Figure 5-8. Clock Synchronization at Reset  
5.2 POWER MANAGEMENT  
Many VLSI devices available today use dynamic circuitry. A dynamic circuit uses a capacitor  
(usually parasitic gate or diffusion capacitance) to store information. The stored charge decays  
over time due to leakage currents in the silicon. If the device does not use the stored information  
before it decays, the state of the entire device may be lost. Circuits must periodically refresh dy-  
namic RAMs, for example, to ensure data retention. Any microprocessor that has a minimum  
clock frequency has dynamic logic. On a dynamic microprocessor, if you stop or slow the clock,  
the dynamic nodes within it begin discharging. With a long enough delay, the processor is likely  
to lose its present state, needing a reset to resume normal operation.  
An 80C186 Modular Core microprocessor is fully static. The CPU stores its current state in  
flip-flops, not capacitive nodes. The clock signal to both the CPU core and the peripherals can  
stop without losing any internal information, provided the design maintains power. When the  
clock restarts, the device will execute from its previous state. When the processor is inactive for  
significant periods, special power management hardware takes advantage of static operation to  
achieve major power savings.  
5-10  
 
CLOCK GENERATION AND POWER MANAGEMENT  
5.2.1 Power-Save Mode  
Power-Save mode is a means for reducing operating current. Power-Save mode enables a pro-  
grammable clock divider in the clock generation circuit.  
NOTE  
Power-Save mode can be used to stretch bus cycles as an alternative to wait  
states.  
Possible clock divisor settings are 1 (undivided), 4, 8 and 16. The divided frequency feeds the  
core, the integrated peripherals and CLKOUT. The processor operates at the divided clock rate  
exactly as if the crystal or external oscillator frequency were lower by the same amount. Since  
the processor is static, a lower limit clock frequency does not apply. It may be necessary to repro-  
gram integrated peripherals such as the Timer Counter Unit and the Refresh Control Unit to com-  
pensate for the overall reduced clock rate.  
5.2.1.1  
Entering Power-Save Mode  
The Power-Save Register (Figure 5-9) controls Power-Save mode operation. The lower two bits  
select the divisor. When program execution sets the PSEN bit, the processor enters Power-Save  
mode. The internal clock frequency changes at the falling edge of T3 of the write to the Power-  
Save Register. CLKOUT changes simultaneously and does not glitch. Figure 5-10 illustrates the  
change at CLKOUT.  
5-11  
 
CLOCK GENERATION AND POWER MANAGEMENT  
Register Name:  
Power Save Register  
PWRSAV  
Register Mnemonic:  
Register Function:  
Enables and sets clock division factor.  
15  
0
P
S
E
N
F
1
F
0
A1130-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
PSEN  
Power Save  
Enable  
0H  
Setting this bit enables Power Save mode and  
divides the internal operating clock by the value  
defined by F1:0. Clearing this bit disables  
Power-Save mode and forces the CPU to  
operate at full speed. PSEN is automatically  
cleared whenever an interrupt occurs.  
F1:0  
Clock  
Division  
Factor  
0H  
These bits control the clock division factor used  
when Power Save mode is enabled. The  
allowable values are listed below:  
F1 F0 Divisor  
0
0
1
1
0
1
0
1
By 1 (undivided)  
By 4  
By 8  
By 16  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 5-9. Power-Save Register  
5-12  
 
CLOCK GENERATION AND POWER MANAGEMENT  
T2  
T3  
T4  
CLKOUT  
WR  
2
1
NOTES:  
1. : Write to Power-Save Register (as viewed on the bus).  
2. : Low-going edge of T3 starts new clock rate.  
A1124-0A  
Figure 5-10. Power-Save Clock Transition  
5.2.1.2  
Leaving Power-Save Mode  
Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in  
the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.  
When the PSEN bit clears, the clock returns to its undivided frequency (standard divide-by-two)  
at the falling T3 edge of the write to the Power-Save Register. The same result happens from re-  
programming the clock divisor to a new value. The Power-Save Register can be read or written  
at any time.  
Unmasked interrupts include those from the Interrupt Control Unit, but not software interrupts.  
If an NMI occurs, or an unmasked interrupt request has sufficient priority to pass to the core,  
Power-Save mode will end. The PSEN bit clears and the clock resumes full-speed operation at  
the falling edge of a bus cycle T3 state. However, the exact bus cycle of the transition is unde-  
fined. The Return from Interrupt instruction (IRET) does not automatically set the PSEN bit  
again. If you still want Power-Save mode operation, you can set the PSEN bit as part of the inter-  
rupt service routine.  
5.2.1.3  
Example Power-Save Initialization Code  
Example 5-1 illustrates programming the Power-Save Unit for a typical system. The program also  
includes code to change the DRAM refresh rate to compensate for the reduced clock rate.  
5-13  
 
CLOCK GENERATION AND POWER MANAGEMENT  
$mod186  
name  
example_PSU_code  
;FUNCTION:  
This function reduces CPU power consumption  
by dividing the CPU operating frequency by a  
divisor.  
;
;
; SYNTAX:  
; INPUTS:  
;
extern void far power_save(int divisor);  
divisor - This variable represents F0, F1 and F2  
of PWRSAV.  
; OUTPUTS:  
None  
;
;
NOTE:  
Parameters are passed on the stack as required  
by high-level languages  
;substitute register offset  
PWRSAV  
RFTIME  
equ  
equ  
xxxxH  
xxxxH  
;Power-Save Register  
;Refresh Interval Count  
;Register  
;Refresh Control Register  
;Power-Save enable bit  
RFCON  
PSEN  
equ  
equ  
xxxxH  
8000H  
data  
FreqTable  
data  
segment public 'data'  
dw 1, 4, 8, 16, 32, 64, 0, 0  
ends  
lib_80C186  
segment public 'code'  
assume cs:lib_80C186, ds:data  
public _power_save  
proc far  
_power_save  
push bp  
;save caller's bp  
mov  
bp, sp  
;get current top of stack  
;save registers that will  
;be modified  
push ax  
push dx  
_divisor  
equ word ptr[bp+6]  
;get parameter off the  
;stack  
mov dx, RFTIME  
;get current DRAM refresh  
;rate  
;mask off unwanted bits  
in  
ax, dx  
and ax, 01ffh  
div FreqTable[_divisor]  
;divide refresh rate  
;by _divisor  
out dx, ax  
;set new refresh rate  
;select Power-Save Register  
;get divisor  
mov dx, PWRSAV  
mov ax, _divisor  
and ax, 7  
;mask off unwanted bits  
;set enable bit  
or  
ax, PSEN  
out dx, ax  
pop dx  
pop bx  
pop ax  
pop bp  
ret  
;divide frequency  
;restore saved registers  
;restore caller's bp  
_power_save  
lib_80C186  
endp  
ends  
end  
Example 5-1. Initializing the Power Management Unit for Power-Save Mode  
5-14  
 
6
Chip-Select Unit  
CHAPTER 6  
CHIP-SELECT UNIT  
Every system requires some form of component-selection mechanism to enable the CPU to ac-  
cess a specific memory or peripheral device. The signal that selects the memory or peripheral de-  
vice is referred to as a chip-select. Besides selecting a specific device, each chip-select can be  
used to control the number of wait states inserted into the bus cycle. Devices that are too slow to  
keep up with the maximum bus bandwidth can use wait states to slow the bus down.  
6.1 COMMON METHODS FOR GENERATING CHIP-SELECTS  
One method of generating chip-selects uses latched address signals directly. An example inter-  
face is shown in Figure 6-1(A). In the example, an inverted A16 is connected to an SRAM device  
with an active-low chip-select. Any bus cycle with an address between 10000H and 1FFFFH  
(A16 = 1) enables the SRAM device. Also note that any bus cycle with an address starting at  
30000H, 50000H, 70000H and so on also selects the SRAM device.  
Decoding more address bits solves the problem of a chip-select being active over multiple address  
ranges. In Figure 6-1(B), a one-of-eight decoder is connected to the uppermost address bits. Each  
decoded output is active for one-eighth of the 1 Mbyte address space. However, each chip-select  
has a fixed starting address and range. Future system memory changes could require circuit  
changes to accommodate the additional memory.  
6.2 CHIP-SELECT UNIT FEATURES AND BENEFITS  
The Chip-Select Unit overcomes limitations of the designs shown in Figure 6-1 and has the fol-  
lowing features:  
Ten chip-select outputs  
Programmable start and stop addresses  
Memory or I/O bus cycle decoder  
Programmable wait-state generator  
Provision to disable a chip-select  
Provision to override bus ready  
Figure 6-2 illustrates the logic blocks that generate a chip-select. Each chip-select has a duplicate  
set of logic.  
6-1  
CHIP-SELECT UNIT  
27C256  
74AC138  
Selects 896K to 1M  
A19  
A18  
A17  
A3  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
D7:0  
Selects 768K to 896K  
A2  
A1  
A0:12  
A1:13  
D15:8  
E1  
E2  
ALE  
RD  
OE  
CS  
HLDA  
Selects 128K to 256K  
Selects 0 to 128K  
A16  
E3  
(A)  
(B)  
Chip-Selects Using  
Addresses Directly  
Chip-Selects Using  
Simple Decoder  
A1168-0A  
Figure 6-1. Common Chip-Select Generation Methods  
6.3 CHIP-SELECT UNIT FUNCTIONAL OVERVIEW  
The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the  
appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note  
that the chip-select goes active in the same bus state as address goes active, eliminating any delay  
through address latches and decoder circuits. The Chip-Select Unit activates a chip-select for bus  
cycles initiated by the CPU, DMA Control Unit or Refresh Control Unit.  
Six of the chip-selects map only into memory address space, while the remaining seven can map  
into either memory or I/O address space. The chip-selects typically associate with memory and  
peripheral devices as follows:  
6-2  
 
CHIP-SELECT UNIT  
Internal  
Address Bus  
= Block Size  
= Block Size  
UCS  
LCS  
= Block Size/4  
= Block Size/4  
= Block Size/4  
= Block Size/4  
MCS3  
MCS2  
MCS1  
MCS0  
= Base  
= Base  
Base + 0  
PCS0  
PCS1  
PCS2  
PCS3  
PCS4  
Base + 128  
Base + 256  
Base + 384  
Base + 512  
Base + 640  
Base + 768  
Memory/  
I/O Selector  
MS  
A
B
PCS5  
PCS6  
MUX  
A/B  
A1  
A2  
Internal Address Bit  
EX Control Bit  
A1139-0A  
Figure 6-2. Chip-Select Block Diagram  
6-3  
 
CHIP-SELECT UNIT  
UCS  
LCS  
Mapped only to the upper memory address space; selects the BOOT memory  
device (EPROM or Flash memory types).  
Mapped only to the lower memory address space; selects a static memory  
(SRAM) device that stores the interrupt vector table, local stack, local data, and  
scratch pad data.  
MCS3:0  
PCS6:0  
Mapped only to memory address space; selects additional SRAM memory,  
DRAM memory, or the system bus.  
Mapped to memory or I/O address space; selects peripheral devices or generates  
a DMA acknowledge strobe. Note that each PCSx is not individually config-  
urable for I/O space or memory space.  
T4  
T1  
T2  
T3  
T4  
CLKOUT  
ALE  
AD15:0  
A19:16  
Address Valid  
Status  
UCS, PCS6:0  
MCS3:0, LCS  
S2:0  
RD, WR  
A1140-0A  
Figure 6-3. Chip-Select Relative Timings  
The UCS chip-select always ends at address location 0FFFFH; its block size (and thus its starting  
address) is programmed in the UMCS register (Figure 6-5 on page 6-7). The LCS chip-select al-  
ways starts at address location 0H; its block size (and thus its ending address) is programmed in  
the LMCS Control register (Figure 6-6 on page 6-8). The block size can range from 1 Kbyte to  
256 Kbytes for both.  
The MCS3:0 chip-selects access a contiguous block of memory address space. The block size can  
range from 8 Kbytes to 512 Kbytes; it is programmed in the MMCS register (Figure 6-7 on page  
6-9). Each chip-select goes active for one-fourth of the block. The start address is programmed  
in the MPCS register (Figure 6-9 on page 6-11); it must be an integer multiple of the block size.  
Because of the start address limitation, the MCS3:0 chip-selects cannot cover the entire memory  
address space between the LCS and UCS chip-selects.  
6-4  
 
CHIP-SELECT UNIT  
By combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space.  
Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256  
Kbytes.  
The PCS6:0 chip-selects access a contiguous, 896-byte block of memory or I/O address space.  
Each chip-select goes active for one-seventh of the block (128 bytes). The start address is pro-  
grammed in the PACS register (Figure 6-8 on page 6-10); it can begin on any 1 Kbyte boundary.  
A chip-select goes active when it meets all of the following criteria:  
1. The chip-select is enabled.  
2. The bus cycle status matches the default or programmed type (memory or I/O).  
3. The bus cycle address is within the default or programmed block size.  
4. The bus cycle is not accessing the Peripheral Control Block.  
A memory address applies to memory read, memory write and instruction prefetch bus cycles.  
An I/O address applies to I/O read and I/O write bus cycles. Interrupt acknowledge and HALT  
bus cycles never activate a chip-select, regardless of the address generated.  
After power-on or system reset, only the UCS chip-select is initialized and active (see Figure 6-4).  
Address  
1
1MB  
SRDY  
ARDY  
UCS  
Data  
1023K  
UCS  
Active For  
Top 1 KByte  
Memory  
Map  
Processor  
0
NOTE:  
1. 3 wait states automatically inserted. Bus READY must be provided.  
A1006-0A  
Figure 6-4. UCS Reset Configuration  
6-5  
 
CHIP-SELECT UNIT  
6.4 PROGRAMMING  
Four registers determine the operating characteristics of the chip-selects. The Peripheral Control  
Block defines the location of the Chip-Select Unit registers. Table 6-1 lists the registers and their  
associated programming names.  
Table 6-1. Chip-Select Unit Registers  
Control Register  
Mnemonic  
Alternate Register  
Mnemonic  
Chip-Select Affected  
UMCS  
LMCS  
MMCS  
PACS  
None  
None  
UCS  
LCS  
MPCS  
MPCS  
MCS3:0  
PCS6:0  
The control registers (Figures 6-5 through 6-7) define the base address and bus ready and wait  
state requirements for the corresponding chip-selects. The alternate control register (Figure 6-9)  
defines the block size for MCS3:0. It also selects memory or I/O space for PCS6:0, selects the  
function of the PCS6:5 pins, and defines the bus ready and wait state requirements for PCS6:4.  
6.4.1 Initialization Sequence  
Chip-selects do not have to be initialized in any specific order. However, the following guidelines  
help prevent a system failure.  
1. Initialize local memory chip-selects  
2. Initialize local peripheral chip-selects  
3. Perform local diagnostics  
4. Initialize off-board memory and peripheral chip-selects  
5. Complete system diagnostics  
An unmasked interrupt or NMI must not occur until the interrupt vector addresses have been writ-  
ten to memory. Failure to prevent an interrupt from occurring during initialization will cause a  
system failure. Use external logic to generate the chip-select if interrupts cannot be masked prior  
to initialization.  
6-6  
 
CHIP-SELECT UNIT  
Register Name:  
UCS Control Register  
UMCS  
Register Mnemonic:  
Register Function:  
Controls the operation of the UCS chip-select.  
15  
0
U
1
7
U
1
6
U
1
5
U
1
4
U
1
3
U
1
2
U
1
1
U
1
0
R
2
R
1
R
0
A1141-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Start  
U17:10  
0FFH  
Defines the starting address for the chip-select.  
During memory bus cycles, U17:10 are  
compared with the A17:10 address bits. An  
equal to or greater than result enables the UCS  
chip-select if A19:18 are both one. Table 6-2 on  
page 6-12 lists the only valid programming  
combinations.  
Address  
R2  
Bus Ready  
Disable  
0H  
3H  
When R2 is clear, bus ready must be active to  
complete a bus cycle. When R2 is set, R1:0  
control the number of bus wait states and bus  
ready is ignored.  
R1:0  
Wait State  
Value  
R1:0 define the minimum number of wait states  
inserted into the bus cycle.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products. Programming  
U17:10 with values other than those shown in Table 6-2 on page 6-12 results in  
unreliable chip-select operation. Reading this register (before writing it) enables  
the chip-select; however, none of the programmable fields will be properly initial-  
ized.  
Figure 6-5. UMCS Register Definition  
6-7  
 
CHIP-SELECT UNIT  
Register Name:  
LCS Control Register  
Register Mnemonic:  
Register Function:  
LMCS  
Controls the operation of the LCS chip-select.  
15  
0
U
1
7
U
1
6
U
1
5
U
1
4
U
1
3
U
1
2
U
1
1
U
1
0
R
2
R
1
R
0
A1142-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
U17:10  
Ending  
Address  
00H  
Defines the ending address for the chip-select.  
During memory bus cycles, U17:10 are  
compared with the A17:10 address bits. A less  
than result enables the LCS chip-select if  
A19:18 are both zero. Table 6.3 on page 6-13  
lists the only valid programming combinations.  
R2  
Bus Ready  
Disable  
X
When R2 is clear, bus ready must be active to  
complete a bus cycle. When R2 is set, R1:0  
control the number of bus wait states and bus  
ready is ignored.  
R1:0  
Wait State  
Value  
3H  
R1:0 define the minimum number of wait states  
inserted into the bus cycle.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products. Programming  
U17:10 with values other than those shown in Table 6.3 on page 6-13 results in  
unreliable chip-select operation. Reading this register (before writing it) enables  
the chip-select; however, none of the programmable fields will be properly initial-  
ized.  
Figure 6-6. LMCS Register Definition  
6-8  
 
CHIP-SELECT UNIT  
Register Name:  
MCS Control Register  
MMCS  
Register Mnemonic:  
Register Function:  
Controls the operation of the MCS chip-selects.  
15  
0
U
1
9
U
1
8
U
1
7
U
1
6
U
1
5
U
1
4
U
1
3
R
2
R
1
R
0
A1143-0B  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Start  
Function  
Defines the starting address for the block of  
U19:13  
XXH  
Address  
MCS chip-selects. During memory bus cycles,  
U19:13 are compared with the A19:13 address  
bits. An equal to or greater than result enables  
the MCS chip-select. The starting address must  
be an integer multiple of the block size defined  
in the MPCS register. See Table 6-5 on page  
6-14 for additional information.  
R2  
Bus Ready  
Disable  
X
When R2 is clear, bus ready must be active to  
complete a bus cycle. When R2 is set, R1:0  
control the number of bus wait states and bus  
ready is ignored.  
R1:0  
Wait State  
Value  
3H  
R1:0 define the minimum number of wait states  
inserted into the bus cycle.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products. A starting address  
other than an integer multiple of the block size defined in the MPCS register  
causes unreliable chip-select operation. (See Table 6-5 on page 6-14 for details.)  
Reading this register and the MPCS register (before writing them) enables the  
MCS chip-selects; however, none of the programmable fields will be properly ini-  
tialized.  
Figure 6-7. MMCS Register Definition  
6-9  
 
CHIP-SELECT UNIT  
Register Name:  
PCS Control Register  
Register Mnemonic:  
Register Function:  
PACS  
Controls the operation of the PCS chip-selects.  
15  
0
U
1
9
U
1
8
U
1
7
U
1
6
U
1
5
U
1
4
U
1
3
R
2
R
1
R
0
A1143-0B  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Start  
Function  
U19:13  
XXH  
Defines the starting address for the block of  
PCS chip-selects. During memory or I/O bus  
Address  
cycles, U19:13 are compared with the A19:13  
address bits. An equal to or greater than result  
enables the PCS chip-select. U19:16 must be  
programmed to zero for proper I/O bus cycle  
operation.  
R2  
Bus Ready  
Disable  
X
When R2 is clear, bus ready must be active to  
complete a bus cycle. When R2 is set, R1:0  
control the number of bus wait states and bus  
ready is ignored.  
R1:0  
Wait State  
Value  
3H  
R1:0 define the minimum number of wait states  
inserted into the bus cycle.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products. U19:16 must be  
programmed to zero for proper I/O bus cycle operation. Reading this register and  
the MPCS register (before writing them) enables the PCS chip-selects; however,  
none of the programmable fields will be properly initialized.  
Figure 6-8. PACS Register Definition  
6-10  
 
CHIP-SELECT UNIT  
Register Name:  
MCS and PCS Alternate Control Register  
Register Mnemonic:  
Register Function:  
MPCS  
Controls operation of the MCS and PCS chip-  
selects.  
15  
0
M
6
M
5
M
4
M
3
M
2
M
1
M
0
E
X
M
S
R
2
R
1
R
0
A1144-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
M6:0  
Block Size  
XXH  
XH  
Defines the block size for the MCS chip-selects.  
Table 6-5 on page 6-14 lists allowable values.  
EX  
MS  
R2  
Pin Selector  
Setting EX configures PCS6:5 as chip-selects.  
Clearing EX configures the pins as latched  
address bits A2:A1.  
Bus Cycle  
Selector  
XH  
X
Clearing MS activates PCS6:0 for I/O bus  
cycles. Setting MS activates PCS6:0 for  
memory bus cycles.  
Bus Ready  
Disable for  
PCS6:4  
Applies only to PCS6:4. When R2 is clear, bus  
ready must be active to complete a bus cycle.  
When R2 is set, R1:0 control the number of bus  
wait states and bus ready is ignored.  
R1:0  
Wait State  
Value for  
PCS6:4  
3H  
Apply only to PCS6:4. R1:0 define the minimum  
number of wait states inserted into the bus  
cycle.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products. A starting address  
other than an integer multiple of the block size defined in this register causes  
unreliable chip-select operation. Reading this register and the MMCS or PACS  
register (before writing them) enables the associated chip-selects; however, none  
of the programmable fields will be properly initialized.  
Figure 6-9. MPCS Register Definition  
6-11  
 
CHIP-SELECT UNIT  
The UMCS and LMCS registers can be programmed in any sequence. To program the MCS and  
PCS chip-selects, follow this sequence:  
1. Program the MPCS register  
2. Program the MMCS register to enable the MCS chip-selects.  
3. Program the PACS register to enable the PCS chip-selects.  
6.4.2 Programming the Active Ranges  
The active ranges of the chip-selects are determined by a combination of their starting or ending  
addresses and block sizes. This section describes how to control the active range of each chip-  
select.  
6.4.2.1  
UCS Active Range  
The UCS starting address is 100000H (1 Mbyte) minus the block size; its ending address is fixed  
at 0FFFFFH.Table 6-2 defines the acceptable values for the field (U17:10) in the UMCS register  
that determines the UCS block size and starting address.  
Table 6-2. UCS Block Size and Starting Address  
UMCS Field  
U17:10  
Block Size  
(Kbytes)  
Starting Address  
00H  
80H  
C0H  
E0H  
F0H  
F8H  
FCH  
FEH  
FFH  
256  
128  
64  
32  
16  
8
0C0000H  
0E0000H  
0F0000H  
0F8000H  
0FC000H  
0FE000H  
0FF000H  
0FF800H  
0FFC00H  
4
2
1
6-12  
 
CHIP-SELECT UNIT  
6.4.2.2  
LCS Active Range  
The LCS starting address is fixed at zero in memory address space; its ending address is the pro-  
grammed block size minus one. Table 6.3 defines the acceptable values for the field (U17:10) in  
the LMCS register that determines the LCS block size and ending address.  
Table 6.3 LCS Active Range  
LMCS Field  
U17:10  
Block Size  
(Kbytes)  
Ending Address  
00H  
01H  
03H  
07H  
0FH  
1FH  
3FH  
7FH  
1
2
003FFH  
007FFH  
00FFFH  
01FFFH  
03FFFH  
07FFFH  
0FFFFH  
1FFFFH  
3FFFFH  
4
8
16  
32  
64  
128  
256  
6.4.2.3  
MCS Active Range  
The starting and ending addresses of the individual MCS chip-selects are determined by the base  
address programmed in the MMCS register and the block size programmed in the MPCS register  
(see Table 6-4 and Figure 6-10). The base address must be an integer multiple of the block size.  
Table 6-5 lists the allowable block sizes and base address limitations.  
Table 6-4. MCS Active Range  
Active Range  
Chip-  
Select  
Start Address  
Base  
Ending Address  
MCS0  
MCS1  
MCS2  
MCS3  
Base + (1/4 block size –1)  
Base + 1/4 block size Base + (1/2 block size –1)  
Base + 1/2 block size Base + (3/4 block size –1)  
Base + 3/4 block size Base + (block size – 1)  
6-13  
   
CHIP-SELECT UNIT  
Table 6-5. MCS Block Size and Start Address Restrictions  
MPCS Block Size Bits  
Block Size  
(Kbytes)  
MMCS Start Address  
Restrictions  
M6  
M5  
M4  
M3  
M2  
M1  
M0  
0
0
0
0
0
0
1
0
0
0
0
0
1
X
0
0
0
0
1
X
X
0
0
0
0
0
1
1
X
X
X
X
X
X
8
None  
16  
U13 must be zero.  
0
1
X
X
X
X
X
32  
U14:13 must be zero.  
U15:13 must be zero.  
U16:13 must be zero.  
U17:13 must be zero.  
1
X
X
X
X
64  
X
X
X
128  
256  
512  
U18:13 must be zero.  
NOTE: If U19 is one, will overlap UCS.  
X= don’t care, but should be 0 for future compatibility.  
Starting Address  
Ending Address  
Block Size is  
defined by M6:0  
Base + (Block Size-1)  
MCS3 Active Range  
Base + 3/4 Block Size  
Base + 1/2 Block Size  
Base + 1/4 Block Size  
Base + (3/4 Block Size-1)  
Base + (1/2 Block Size-1)  
Base + (1/4 Block Size-1)  
MCS2 Active Range  
MCS1 Active Range  
MCS0 Active Range  
MCS Base  
(Defined by U19:13)  
Memory Map  
A1136-0C  
Figure 6-10. MCS3:0 Active Ranges  
6-14  
   
CHIP-SELECT UNIT  
6.4.2.4  
PCS Active Range  
Each PCS chip-select starts at an offset above the base address programmed in the PACS register  
and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address  
location. Table 6-6 lists the active range for each PCS chip-select.  
Table 6-6. PCS Active Range  
Active Range  
Chip-  
Select  
Start Address  
Base  
Ending Address  
PCS0  
PCS1  
PCS2  
PCS3  
PCS4  
PCS5  
PCS6  
Base + 127 (7FH)  
Base + 255 (0FFH)  
Base + 383 (17FH)  
Base + 511 (1FFH)  
Base + 639 (27FH)  
Base + 767 (2FFH)  
Base + 895 (37FH)  
Base + 128 (080H)  
Base + 256 (100H)  
Base + 384 (180H)  
Base + 512 (200H)  
Base + 640 (280H)  
Base + 768 (300H)  
6.4.3 Bus Wait State and Ready Control  
Normally, the bus ready input must be inactive at the appropriate time to insert wait states into  
the bus cycle. The Chip-Select Unit can ignore the state of the bus ready input to extend and com-  
plete the bus cycle automatically. Most memory and peripheral devices operate properly using  
three or fewer wait states. However, accessing such devices as a dual-port memory, an expansion  
bus interface, a system bus interface or remote peripheral devices can require more than three  
wait states to complete a bus cycle.  
A three-bit field (R2:0) in the control registers defines the number of wait states and the ready  
requirements for the chip-selects. Figure 6-11 shows a simplified logic diagram of the wait state  
and ready control functions.  
6-15  
 
CHIP-SELECT UNIT  
BUS READY  
R2 Control Bit  
READY  
Wait  
State  
Counter  
Wait  
State  
Ready  
Wait State Value (R1:0)  
A1137-0A  
Figure 6-11. Wait State and Ready Control Functions  
The R2 control bit determines whether the bus cycle completes normally (requires bus ready) or  
unconditionally (ignores bus ready). The R1:0 bits define the number of wait states to insert into  
the bus cycle. For devices requiring three or fewer wait states, you can set R2 (ignore bus ready)  
and program R1:0 with the number of required wait states. For devices that may require more than  
three wait states, you must clear R2 (require bus ready).  
A bus cycle with wait states automatically inserted cannot be shortened. A bus cycle that ignores  
bus ready cannot be lengthened.  
6.4.4 Overlapping Chip-Selects  
The Chip-Select Unit activates all enabled chip-selects programmed to cover the same physical  
address space. This is true if any portion of the chip-selects’ address ranges overlap (i.e., chip-  
selects’ ranges do not need to overlap completely to all go active). There are various reasons for  
overlapping chip-selects. For example, a system might have a need for overlapping a portion of  
read-only memory with read/write memory or copying data to two devices simultaneously.  
If overlapping chip-selects do not have identical wait state and bus ready programming, the Chip-  
Select Unit uses the following priority scheme:  
1. If any MCS chip-select is active, it uses the R2:0 bits in the MPCS register.  
2. If the PCS chip-selects overlap LCS, it uses the R2:0 bits in the LMCS register.  
3. If the PCS chip-selects overlap UCS, it uses the R2:0 bits in the UMCS register.  
6-16  
 
CHIP-SELECT UNIT  
For example, assume MCS3 overlaps UCS. MCS3 is programmed for two wait states and re-  
quires bus ready, while UCS is programmed for no wait states and ignores bus ready. An access  
to the overlapped region has two wait states and requires bus ready (the values programmed in  
the R2:0 bits in the MPCS register).  
Be cautious when overlapping chip-selects with different wait state or bus ready programming.  
The following two conditions require special attention to ensure proper system operation:  
1. When all overlapping chip-selects ignore bus ready but have different wait states, verify  
that each chip-select still works properly using the highest wait state value. A system  
failure may result when too few or too many wait states occur in the bus cycle.  
2. If one or more of the overlapping chip-selects requires bus ready, verify that all chip-  
selects that ignore bus ready still work properly using both the smallest wait state value  
and the longest possible bus cycle. A system failure may result when too few or too many  
wait states occur in the bus cycle.  
6.4.5 Memory or I/O Bus Cycle Decoding  
The UCS, LCS and MCS chip-selects activate only for memory bus cycles. The PCS chip-selects  
activate for either memory or I/O bus cycles, depending on the state of the MS bit in the MPCS  
register (Figure 6-9 on page 6-11). Memory bus cycles consist of memory read, memory write  
and instruction prefetch cycles. I/O bus cycles consist of I/O read and I/O write cycles.  
Chip-selects go active for bus cycles initiated by the CPU, DMA Control Unit and Refresh Con-  
trol Unit.  
6.4.6 Programming Considerations  
When programming the PCS chip-selects active for I/O bus cycles, remember that eight bytes of  
I/O are reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the inter-  
face to an 80C187 math coprocessor. A chip-select can overlap this reserved space provided there  
is no intention of using the 80C187. However, to avoid possible future compatibility issues, Intel  
recommends that the PCS chip-selects not start at I/O address location 0H.  
Reading or writing the chip-select registers enables the corresponding chip-select. Reading a reg-  
ister before writing to it enables the chip-select without initializing the programmable fields,  
which causes indeterminate operation. For example, reading the LMCS register enables the LCS  
chip-select, but it does not ensure that LCS is programmed correctly. Once you enable a chip-  
select, you cannot disable it, but you can change its operation by writing to the appropriate reg-  
ister.  
6-17  
CHIP-SELECT UNIT  
6.5 CHIP-SELECTS AND BUS HOLD  
The Chip-Select Unit decodes only internally generated address and bus state information. An ex-  
ternal bus master cannot make use of the Chip-Select Unit. During HLDA, all chip-selects remain  
inactive.  
The circuit shown in Figure 6-12 allows an external bus master to access a device during bus  
HOLD.  
CSU Chip Select  
Device select  
External Master Chip Select  
A1167-0A  
Figure 6-12. Using Chip-Selects During HOLD  
6.6 EXAMPLES  
The following sections provide examples of programming the Chip-Select Unit to meet the needs  
of a particular application. The examples do not go into hardware analysis or design issues.  
6.6.1 Example 1: Typical System Configuration  
Figure 6-13 illustrates a block diagram of a typical system design with a 128 Kbyte EPROM and  
a 32 Kbyte SRAM. The peripherals are mapped to I/O address space. Example 6.1 shows a pro-  
gram template for initializing the Chip-Select Unit.  
6-18  
 
CHIP-SELECT UNIT  
Processor  
ARDY  
SRDY  
EPROM  
128K  
D
R
A
M
256K  
SRAM  
32K  
Floppy  
Disk  
Control  
ALE  
L
a
t
c
h
20  
Addr  
Bus  
A19:16  
AD15:0  
DACK  
AD Bus  
DRQ  
A0  
CE  
CE  
CE  
CE  
DRQ  
PCS1  
UCS  
4
MCS3:0  
LCS  
PCS0  
A1138-0A  
Figure 6-13. Typical System  
6-19  
 
CHIP-SELECT UNIT  
$
$
TITLE  
MOD186XREF  
NAME  
(Chip-Select Unit Initialization)  
CSU_EXAMPLE_1  
; External reference from this module  
include(PCBMAP.INC  
$
;File declares register  
;locations and names.  
; Module equates  
; Configuration equates  
INTRDY EQU  
EXTRDY EQU  
0004H  
0000H  
0080H  
0040H  
;Internal bus ready modifier  
;External bus ready modifier  
;PCS Memory/IO select modifier  
;PCS/Latched address modifier  
IO  
EQU  
ALLPCS EQU  
;Below is a list of the default system memory and I/O environment. These  
;defaults configure the Chip-Select Unit for proper system operation.  
;EPROM memory is located from 0E0000 to 0FFFFF (128 Kbytes).  
;Wait states are calculated assuming 16MHz operation.  
;UCS# controls the accesses to EPROM memory space.  
EPROM_SIZE EQU 128  
EPROM_BASE EQU 1024 - EPROM_SIZE;Start address in Kbytes  
EPROM_WAIT EQU 1 ;Wait states  
;Size in Kbytes  
;The UMCS register values are calculated using the above system contraints  
;and the equations below.  
UMCS_VAL EQU  
(EPROM_BASE SHL 6)OR (0C038H) OR  
(EPROM_RDY) OR (EPROM_WAIT)  
&
;SRAM memory starts at 0H and continues to 7FFFH (32 Kbytes).  
;Wait states are calculated assuming 16MHz operation.  
;LCS# controls the accesses to SRAM memory space.  
SRAM_SIZE EQU 32  
SRAM_BASE EQU 0  
SRAM_WAIT EQU 0  
SRAM_RDY EQU INTRDY  
;Size in Kbytes  
;Start address in Kbytes  
;Wait states  
;Ignore bus ready  
;The LMCS register value is calculated using the above system constraints  
;and the equations below  
LMCS_VAL EQU ((SRAM_SIZE - 1)SHL6) OR (0038H) OR  
&
(SRAM_RDY)  
OR (SRAM_WAIT)  
;A DRAM interface is selected by the MCS3:0 chip-selects. The BASE value  
;defines the starting address of the DRAM window. The SIZE value (along with  
;the BASE ;value) defines the ending address. Zero wait state performance  
;is assumed. The Refresh Control Unit uses DRAM_BASE to properly configure  
;refresh operation.  
Example 6-1. Initializing the Chip-Select Unit  
6-20  
CHIP-SELECT UNIT  
DRAM_BASE EQU  
DRAM_SIZE EQU  
DRAM_WAIT EQU  
256  
256  
0
;window start address in Kbytes  
;window size in Kbytes  
;wait states  
DRAM_RDY  
EQU  
INTRDY  
;ignore bus ready  
;The MPCS register is used to program both the MCS and PCS chip-selects.  
;Below are the equates for the I/O peripherals (also used to program the PACS  
;register.  
IO_WAIT  
IO_RDY  
EQU  
EQU  
4
;IO wait states  
INTRDY  
IO  
;ignore bus ready  
PCS_SPACE EQU  
;put PCS# chip-selects in I/O space  
;generate PCS5# and PCS6#  
PCS_FUNC  
EQU  
ALLPCS  
;The MMCS and MPCS register values are calculated using the above system  
;constraints and the equations below:  
MMCS_VAL  
MPCS_VAL  
&
EQU  
EQU  
(DRAM_BASE SHL 6) OR (001F8H) OR (DRAM_RDY) OR (DRAM_WAIT)  
(DRAM_SIZE SHL 5) OR (08038H) OR (PCS_SPACE) OR (PCS_FUNC) OR  
(IO_RDY) OR (IO_WAIT)  
;I/O is selected using the PCS0# chip-select. Wait states assume operation at  
;16 MHz. For this example, the Floppy Disk Controller is connected to PCS2# and  
;PCS1# provides the DACK signal.  
IO_BASE  
EQU  
1
;I/O start address in Kbytes  
;The PACS register value is calculated using the above system constraints and  
;the equation below.  
PACS_VAL  
EQU  
(IO_BASE SHL 6) OR (0038H) OR (IO_RDY) OR (IO_WAIT)  
;The following statements define the default assumptions for segment locations.  
ASSUME CS:CODE  
ASSUME DS:DATA  
ASSUME SS:DATA  
ASSUME ES:DATA  
CODE  
;
SEGMENT PUBLIC 'CODE'  
;Entry point on power-up  
;
FW_START  
LABEL FAR  
CLI  
;forces far jump  
;disable interrupts  
;Place register initialization code here  
;
;Set up chip-selects.  
;UCS - EPROM Select  
;LCS - SRAM Select  
;PCS - I/O Select  
;MCS - DRAM Select  
(initialized during POWER_ON code)  
(set to SRAM size)  
(PCS1:0 to support floppy)  
(set to DRAM size)  
mov  
mov  
out  
dx, LMCS_REG  
ax, LMCS_VAL  
dx, al  
;set up LMCS register  
;remember that byte writes are OK  
Example 6-1. Initializing the Chip-Select Unit (Continued)  
6-21  
CHIP-SELECT UNIT  
mov  
mov  
out  
dx, MPCS_REG  
ax, MPCS_VAL  
dx, al  
;ready for PCS lines 4-6  
;as well as MCS programming  
mov  
mov  
out  
dx, MMCS_REG  
ax, MMCS_VAL  
dx, al  
;set up DRAM chip-selects  
;set up I/O chip-select  
mov  
mov  
out  
dx, PACS_REG  
ax, PACS_VAL  
dx, al  
CODE  
;
ENDS  
;Power-on reset code to get started  
;
ASSUME CS:POWER_ON  
POWER_ON SEGMENT AT 0FFFFH  
mov  
mov  
out  
jmp  
ENDS  
dx, UMCS_REG  
ax, UMCS_VAL  
dx, al  
;point to UMCS register  
;reprogram UMCS to match system  
;requirements  
FW_START  
;jump to initialization code  
POWER_ON  
;
;Data segment  
;
DATA  
SEGMENTPUBLIC 'DATA'  
DD 256 DUP (?)  
;Place memory variables here  
DW 500 DUP (?)  
STACK_TOP LABEL WORD  
DATA ENDS  
;Program ends  
;reserved for interrupt vectors  
;stack allocation  
END  
Example 6-1. Initializing the Chip-Select Unit (Continued)  
6-22  
7
Refresh Control Unit  
CHAPTER 7  
REFRESH CONTROL UNIT  
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrat-  
ed address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit  
and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an  
external DRAM controller to use chip-selects, wait state logic and status lines.  
Refresh Clock  
Interval Register  
CPU  
Clock  
9-Bit Down  
Refresh Request  
Counter  
BIU  
Interface  
Refresh Acknowledge  
CLR  
REQ  
F-Bus  
Refresh Control  
Register  
9-Bit Address Counter  
Refresh Address  
Register  
Refresh Base  
Address Register  
7
13  
20-Bit  
Refresh Address  
A1539-01  
Figure 7-1. Refresh Control Unit Block Diagram  
7-1  
 
REFRESH CONTROL UNIT  
7.1 THE ROLE OF THE REFRESH CONTROL UNIT  
Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution.  
Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor  
does it transfer data. The DRAM refresh process freshens individual DRAM rows in “dummy  
read” cycles, while cycling through all necessary addresses.  
The microprocessor interface to DRAMs is more complicated than other memory interfaces. A  
complete DRAM controller requires circuitry beyond that provided by the processor even in the  
simplest configurations. This circuitry must respond correctly to reads, writes and DRAM refresh  
cycles. The external DRAM controller generates the Row Address Strobe (RAS), Column Ad-  
dress Strobe (CAS) and other DRAM control signals.  
Pseudo-static RAMs use dynamic memory cells but generate address strobes and refresh address-  
es internally. The address counters still need external timing pulses. These pulses are easy to de-  
rive from the processor’s bus control signals. Pseudo-static RAMs do not need a full DRAM  
controller.  
7.2 REFRESH CONTROL UNIT CAPABILITIES  
A 9-bit address counter forms the refresh addresses, supporting any dynamic memory devices  
with up to 9 rows of memory cells (9 refresh address bits). This includes all practical DRAM sizes  
for the processor’s 1 Mbyte address space.  
7.3 REFRESH CONTROL UNIT OPERATION  
Figure 7-2 illustrates Refresh Control Unit counting, address generation and BIU bus cycle gen-  
eration in flowchart form.  
The nine-bit down-counter loads from the Refresh Interval Register on the falling edge of CLK-  
OUT. Once loaded, it decrements every falling CLKOUT edge until it reaches one. Then the  
down-counter reloads and starts counting again, simultaneously triggering a refresh request.  
Once enabled, the DRAM refresh process continues indefinitely until the user reprograms the Re-  
fresh Control Unit, a reset occurs, or the processor enters Powerdown mode. Power-Save mode  
divides the Refresh Control Unit clocks, so reprogramming the Refresh Interval Register be-  
comes necessary.  
The refresh request remains active until the bus becomes available. When the bus is free, the BIU  
will run its “dummy read” cycle. Refresh bus requests have higher priority than most CPU bus  
cycles, all DMA bus cycles and all interrupt vectoring sequences. Refresh bus cycles also have a  
higher priority than the HOLD/HLDA bus arbitration protocol (see “Refresh Operation and Bus  
HOLD” on page 7-12).  
7-2  
 
REFRESH CONTROL UNIT  
Refresh Control  
Unit Operation  
BIU Refresh  
Bus Operation  
Refresh Request  
Acknowledged  
Set "E" Bit  
Execute  
Memory Read  
Load Counter  
From Refresh Clock  
Interval Register  
Increment  
Address  
Counter = ?  
Remove  
Request  
Executed  
Every  
Clock  
Continue  
Decrement  
Counter  
Generated BIU  
Request  
A1265-0A  
Figure 7-2. Refresh Control Unit Operation Flow Chart  
The nine-bit refresh clock counter does not wait until the BIU services the refresh request to con-  
tinue counting. This operation ensures that refresh requests occur at the correct interval. Other-  
wise, the time between refresh requests would be a function of varying bus activity. When the  
BIU services the refresh request, it clears the request and increments the refresh address.  
7-3  
 
REFRESH CONTROL UNIT  
The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another  
request before the BIU handles the present request, the BIU loses the present request. However,  
the address associated with the request is not lost. The refresh address changes only after the BIU  
runs a refresh bus cycle. If a DRAM refresh cycle is excessively delayed, there is still a chance  
that the processor will successfully refresh the corresponding row of cells in the DRAM, retaining  
the data.  
7.4 REFRESH ADDRESSES  
Figure 7-3 shows the physical address generated during a refresh bus cycle. This figure applies  
to both the 8-bit and 16-bit data bus microprocessor versions. Refresh address bits RA19:13 come  
from the Refresh Base Address Register. (See “Refresh Base Address Register” on page 7-8.)  
From Refresh Base  
Address Register  
Fixed  
0
From Refresh Address Counter Fixed  
0 RA RA RA RA RA RA RA RA RA 1  
RA RA RA RA RA RA RA 0  
19 18 17 16 15 14 13  
9
8
7
6
5
4
3
2
1
19  
0
20-Bit Refresh Address  
A1502-0A  
Figure 7-3. Refresh Address Formation  
Refresh address bits RA12:10 are always zero. A linear-feedback shift counter generates address  
bits RA9:1 and RA0 is always one. The counter does not count linearly from 0 through 1FFH.  
However, the counting algorithm cycles uniquely through all possible 9-bit values. It matters only  
that each row of DRAM memory cells is refreshed at a specific interval. The order of the rows is  
unimportant.  
Address bit A0 is fixed at one during all refresh operations. In applications based on a 16-bit data  
bus processor, A0 typically selects memory devices placed on the low (even) half of the bus. Ap-  
plications based on an 8-bit data bus processor typically use A0 as a true address bit. The DRAM  
controller must not route A0 to row address pins on the DRAMs.  
7-4  
 
REFRESH CONTROL UNIT  
7.5 REFRESH BUS CYCLES  
Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig-  
nals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh  
bus cycle. The 16-bit bus processor drives both the BHE and A0 pins high during refresh cycles.  
The 8-bit bus version replaces the BHE pin with RFSH, which has the same timings. The 8-bit  
bus processor drives RFSH low and A0 high during refresh cycles.  
Table 7-1. Identification of Refresh Bus Cycles  
Data Bus Width  
BHE/RFSH  
A0  
16-Bit Device  
8-Bit Device  
1
0
1
1
7.6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS  
The basic DRAM access method consists of four phases:  
1. The DRAM controller supplies a row address to the DRAMs.  
2. The DRAM controller asserts a Row Address Strobe (RAS), which latches the row  
address inside the DRAMs.  
3. The DRAM controller supplies a column address to the DRAMs.  
4. The DRAM controller asserts a Column Address Strobe (CAS), which latches the column  
address inside the DRAMs.  
Most 80C186 Modular Core family DRAM interfaces use only this method. Others are not dis-  
cussed here.  
The DRAM controller’s purpose is to use the processor’s address, status and control lines to gen-  
erate the multiplexed addresses and strobes. These signals must be appropriate for three bus cycle  
types: read, write and refresh. They must also meet specific pulse width, setup and hold timing  
requirements. DRAM interface designs need special attention to transmission line effects, since  
DRAMs represent significant loads on the bus.  
DRAM controllers may be either clocked or unclocked. An unclocked DRAM controller requires  
a tapped digital delay line to derive the proper timings.  
Clocked DRAM controllers may use either discrete or programmable logic devices. A state ma-  
chine design is appropriate, especially if the circuit must provide wait state control (beyond that  
possible with the processor’s Chip-Select Unit). Because of the microprocessor’s four-clock bus,  
clocking some logic elements on each CLKOUT phase is advantageous (see Figure 7-4).  
7-5  
 
REFRESH CONTROL UNIT  
T4  
T1  
T2  
T3/TW  
T4  
CLKOUT  
Muxed  
Address  
Column  
Row  
S2:0  
CS  
RAS  
CAS  
WE  
1
2
NOTES:  
1. CAS is unnecessary for refresh cycles only.  
2. WE is necessary for write cycles only.  
A1267-0A  
Figure 7-4. Suggested DRAM Control Signal Timing Relationships  
The cycle begins with presentation of the row address. RAS should go active on the falling edge  
of T2. At the rising edge of T2, the address lines should switch to a column address. CAS goes  
active on the falling edge of T3. Refresh cycles do not require CAS. When CAS is present, the  
“dummy read” cycle becomes a true read cycle (the DRAM drives the bus), and the DRAM row  
still gets refreshed.  
Both RAS and CAS stay active during any wait states. They go inactive on the falling edge of T4.  
At the rising edge of T4, the address multiplexer shifts to its original selection (row addressing),  
preparing for the next DRAM access.  
7-6  
 
REFRESH CONTROL UNIT  
7.7 PROGRAMMING THE REFRESH CONTROL UNIT  
Given a specific processor operating frequency and information about the DRAMs in the system,  
the user can program the Refresh Control Unit registers.  
7.7.1 Calculating the Refresh Interval  
DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary  
and the maximum period to run the cycles. (The number of refresh cycles is the same as the num-  
ber of rows.) You must compensate for bus latency — the time it takes for the Refresh Control  
Unit to gain control of the bus. This is typically 1–5%, but if an external bus master will be ex-  
tremely slow to release the bus, increase the overhead percentage. At standard operating frequen-  
cies, DRAM refresh bus overhead totals 2–3% of the total bus bandwidth.  
Given this information and the CPU operating frequency, use the formula in Figure 7-5 to deter-  
mine the correct value for the RFTIME Register value.  
RPERIOD × FCPU  
------------------------------------------------------------------------------- = RFTIME RegisterValue  
Rows + (Rows × Overhead%)  
RPERIOD  
FCPU  
=
=
=
Maximum refresh period specified by DRAM manufacturer (in µs).  
Operating frequency (in MHz).  
Rows  
Total number of rows to be refreshed.  
Overhead % = Derating factor to compensate for missed refresh requests (typically 1 – 5 %).  
Figure 7-5. Formula for Calculating Refresh Interval for RFTIME Register  
If the processor enters Power-Save mode, the refresh rate must increase to offset the reduced CPU  
clock rate to preserve memory. At lower frequencies, the refresh bus overhead increases. At fre-  
quencies less than about 1.5 MHz, the Bus Interface Unit will spend almost all its time running  
refresh cycles. There may not be enough bandwidth left for the processor to perform other activ-  
ities, especially if the processor must share the bus with an external master.  
7.7.2 Refresh Control Unit Registers  
Three contiguous Peripheral Control Block registers operate the Refresh Control Unit: the Re-  
fresh Base Address Register, Refresh Clock Interval Register and the Refresh Control Register.  
7-7  
 
REFRESH CONTROL UNIT  
7.7.2.1  
Refresh Base Address Register  
The Refresh Base Address Register (Figure 7-6) programs the base (upper seven bits) of the re-  
fresh address. Seven-bit mapping places the refresh address at any 4 Kbyte boundary within the  
1 Mbyte address space. When the partial refresh address from the 9-bit address counter (see Fig-  
ure 7-1 and “Refresh Control Unit Capabilities” on page 7-2) passes 1FFH, the Refresh Control  
Unit does not increment the refresh base address. Setting the base address ensures that the address  
driven during a refresh bus cycle activates the DRAM chip select.  
Register Name:  
Refresh Base Address Register  
RFBASE  
Register Mnemonic:  
Register Function:  
Determines upper 7 bits of refresh address.  
15  
0
R
A
1
R
A
1
R
A
1
R
A
1
R
A
1
R
A
1
R
A
1
9
8
7
6
5
4
3
A1503-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
RA19:13  
Refresh  
Base  
00H  
Uppermost address bits for DRAM refresh  
cycles.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 7-6. Refresh Base Address Register  
Refresh Clock Interval Register  
7.7.2.2  
The Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests. The  
higher the value, the longer the time between requests. The down-counter decrements every fall-  
ing CLKOUT edge, regardless of core activity. When the counter reaches one, the Refresh Con-  
trol Unit generates a refresh request, and the counter reloads the value from the register. Since  
Power-Save mode divides the clock to the Refresh Control Unit, this register will require repro-  
gramming if Power-Save mode is used.  
7-8  
   
REFRESH CONTROL UNIT  
Register Name:  
Refresh Clock Interval Register  
Register Mnemonic:  
Register Function:  
RFTIME  
Sets refresh rate.  
15  
0
R
C
8
R
C
7
R
C
6
R
C
5
R
C
4
R
C
3
R
C
2
R
C
1
R
C
0
A1288-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
RC8:0  
Refresh Counter  
Reload Value  
000H  
Sets the desired clock count between refresh  
cycles.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 7-7. Refresh Clock Interval Register  
7.7.2.3  
Refresh Control Register  
Figure 7-8 shows the Refresh Control Register. The user may read or write the REN bit at any  
time to turn the Refresh Control Unit on or off. The lower nine bits contain the current nine-bit  
down-counter value. The user cannot program these bits. Disabling the Refresh Control Unit  
clears both the counter and the corresponding counter bits in the control register.  
7-9  
 
REFRESH CONTROL UNIT  
Register Name:  
Refresh Control Register  
RFCON  
Register Mnemonic:  
Register Function:  
Controls Refresh Unit operation.  
15  
0
R
E
N
R
C
8
R
C
7
R
C
6
R
C
5
R
C
4
R
C
3
R
C
2
R
C
1
R
C
0
A1311-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
REN  
Refresh  
Control Unit  
Enable  
0
Setting REN enables the Refresh Unit. Clearing  
REN disables the Refresh Unit.  
RC8:0  
Refresh  
Counter  
000H  
These bits contain the present value of the  
down-counter that triggers refresh requests.  
The user cannot program these bits.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 7-8. Refresh Control Register  
7.7.3 Programming Example  
Example 7-1 contains sample code to initialize the Refresh Control Unit. Example 5-2 on page  
5-14 shows the additional code to reprogram the Refresh Control Unit upon entering Power-Save  
mode.  
7-10  
 
REFRESH CONTROL UNIT  
$mod186  
name  
example_80C186_RCU_code  
; FUNCTION: This function initializes the DRAM Refresh  
; Control Unit to refresh the DRAM starting at dram_addr  
; at clock_time intervals.  
; SYNTAX:  
; extern void far config_rcu(int dram_addr, int clock_time);  
; INPUTS:  
;
dram_addr - Base address of DRAM to refresh  
clock_time - DRAM refresh rate  
; OUTPUTS:  
None  
;
;
NOTE: Parameters are passed on the stack as  
required by high-level languages.  
RFBASE  
RFTIME  
RFCON  
equ xxxxh  
equ xxxxh  
equ xxxxh  
equ 8000h  
;substitute register offset  
Enable  
;enable bit  
lib_80186  
segment public 'code'  
assume cs:lib_80186  
public _config_rcu  
proc far  
_config_rcu  
push bp  
;save caller's bp  
mov bp, sp  
;get current top of stack  
_clock_time  
_dram_addr  
equ word ptr[bp+6]  
equ word ptr[bp+8]  
;get parameters off  
;the stack  
push ax  
push cx  
push dx  
push di  
;save registers that  
;will be modified  
Example 7-1. Initializing the Refresh Control Unit  
7-11  
 
REFRESH CONTROL UNIT  
mov dx, RFBASE  
mov ax, _dram_addr  
out dx, al  
;set upper 7 address bits  
;set clock pre_scaler  
;Enable RCU  
mov dx, RFTIME  
mov ax, _clock_time  
out dx, al  
mov dx, RFCON  
mov ax, Enable  
out dx, al  
mov cx, 8  
;8 dummy cycles are  
;required by DRAMs  
;before actual use  
xor di, di  
_exercise_ram:  
mov word ptr [di], 0  
loop _exercise_ram  
pop di  
pop dx  
pop cx  
pop ax  
pop bp  
;restore saved registers  
;restore caller’s bp  
ret  
_config_rcu  
lib_80186  
endp  
ends  
end  
Example 7-1. Initializing the Refresh Control Unit (Continued)  
7.8 REFRESH OPERATION AND BUS HOLD  
When another bus master controls the bus, the processor keeps HLDA active as long as the  
HOLD input remains active. If the Refresh Control Unit generates a refresh request during bus  
hold, the processor drives the HLDA signal inactive, indicating to the current bus master that it  
wishes to regain bus control (see Figure 7-9). The BIU begins a refresh bus cycle only after the  
alternate master removes HOLD. The user must design the system so that the processor can re-  
gain bus control. If the alternate master asserts HOLD after the processor starts the refresh cycle,  
the CPU will relinquish control by asserting HLDA when the refresh cycle is complete.  
7-12  
 
REFRESH CONTROL UNIT  
T1  
T1  
T1  
T1  
T1  
T4  
T1  
CLKOUT  
4
3
1
HOLD  
HLDA  
2
6
AD15:0  
DEN  
RD, WR,  
BHE, S2:0  
DT / R,  
5
A19:16  
NOTES:  
1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T  
2. External bus master terminates use of the bus.  
.
CLHAV  
3. HOLD deasserted; greater than T  
.
HVCL  
4. Hold may be reasserted after one clock.  
5. Lines come out of float in order to run DRAM refresh cycle.  
A1534-0A  
Figure 7-9. Regaining Bus Control to Run a DRAM Refresh Bus Cycle  
7-13  
 
8
Interrupt Control  
Unit  
CHAPTER 8  
INTERRUPT CONTROL UNIT  
The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception  
Handling” on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities be-  
yond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two  
modes: Master or Slave.  
In Master mode, the ICU controls the maskable interrupt input to the CPU. Interrupts can origi-  
nate from the on-chip peripherals and from four external interrupt pins. The ICU synchronizes  
and prioritizes all interrupt sources and presents the correct interrupt type vector to the CPU. (See  
Figure 8-1.) Most systems use master mode.  
In Slave mode, an external 8259A module controls the maskable interrupt input to the CPU and  
acts as the master interrupt controller. The ICU processes only those interrupts from the on-chip  
peripherals and acts as an interrupt input to the 8259A. (See Figure 8-15 on page 8-24.) This mode  
can be useful in larger system designs.  
The Interrupt Control Unit has the following features:  
Programmable priority of each interrupt source  
Individual masking of each interrupt source  
Nesting of interrupt sources  
Support for polled operation  
Support for cascading external 8259A modules to expand external interrupt sources  
8.1 FUNCTIONAL OVERVIEW  
All microcomputer systems must communicate in some way with the external world. A typical  
system might have a keyboard, a disk drive and a communications port, all requiring CPU atten-  
tion at different times. There are two distinct ways to process peripheral I/O requests: polling and  
interrupts.  
Polling requires that the CPU check each peripheral device in the system periodically to see-  
whether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port,  
for instance) thousands of times before it required servicing. In most cases, the use of polling has  
a detrimental effect on system throughput. Any time used to check the peripherals is time spent  
away from the main processing tasks.  
8-1  
INTERRUPT CONTROL UNIT  
Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires  
servicing. The CPU then stops executing the main task, saves its state and transfers execution to  
the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the  
CPU’s original state is restored and execution continues at the point of interruption in the main  
task.  
8.2 MASTER MODE  
Figure 8-1 shows a block diagram of the Interrupt Control Unit in Master mode. In this mode, the  
ICU processes all interrupt requests, both external and internal. The three timer interrupt requests  
share a single input, while the others are supported directly.  
DMA  
0
DMA  
1
Timer 0 Timer 1 Timer 2  
INT0 INT1 INT2 INT3  
Interrupt  
Priority  
Resolver  
Vector  
Generation  
Logic  
To CPU Interrupt Request  
F - Bus  
A1506-A0  
Figure 8-1. Interrupt Control Unit in Master Mode  
8.2.1 Generic Functions in Master Mode  
Several functions of the Interrupt Control Unit are common among most interrupt controllers.  
This section describes how those generic functions are implemented in the Interrupt Control Unit.  
8-2  
 
INTERRUPT CONTROL UNIT  
8.2.1.1  
Interrupt Masking  
There are circumstances in which a programmer may need to disable an interrupt source tempo-  
rarily (for example, while executing a time-critical section of code or servicing a high-priority  
task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Con-  
trol Unit can be masked either globally or individually.  
The Interrupt Enable bit in the Processor Status Word globally enables or disables the maskable  
interrupt request from the Interrupt Control Unit. The programmer controls the Interrupt Enable  
bit with the STI (set interrupt) and CLI (clear interrupt) instructions.  
Besides being globally enabled or disabled by the Interrupt Enable bit, each interrupt source can  
be individually enabled or disabled. The Interrupt Mask register has a single bit for each interrupt  
source. The programming can selectively mask (disable) or unmask (enable) each interrupt  
source by setting or clearing the corresponding bit in the Interrupt Mask register.  
8.2.1.2  
Interrupt Priority  
One critical function of the Interrupt Control Unit is to prioritize interrupt requests. When multi-  
ple interrupts are pending, priority determines which interrupt request is serviced first. In many  
systems, an interrupt handler may itself be interrupted by another interrupt source. This is known  
as interrupt nesting. With interrupt nesting, priority determines whether an interrupt source can  
preempt an interrupt handler that is currently executing.  
Each interrupt source is assigned a priority between zero (highest) and seven (lowest). After reset,  
the interrupts default to the priorities shown in Table 8-1. Because the timers share an interrupt  
source, they also share a priority. Within the assigned priority, each has a relative priority (Timer  
0 has the highest relative priority and Timer 2 has the lowest).  
Table 8-1. Default Interrupt Priorities  
Interrupt Name  
Relative Priority  
Timer 0  
Timer 1  
Timer 2  
DMA0  
DMA1  
INT0  
0 (a)  
0 (b)  
0 (c)  
1
2
3
4
5
6
INT1  
INT2  
INT3  
8-3  
 
INTERRUPT CONTROL UNIT  
The priority of each source is programmable. The Interrupt Control register enables the  
programmer to assign each source a priority that differs from the default. The priority must still  
be between zero (highest) and seven (lowest). Interrupt sources can be programmed to share a  
priority. The Interrupt Control Unit uses the default priorities (see Table 8-1) within the shared  
priority level to determine which interrupt to service first. For example, assume that INT0 and  
INT1 are both programmed to priority seven. Because INT0 has the higher default priority, it is  
serviced first.  
Interrupt sources can be masked on the basis of their priority. The Priority Mask register masks  
all interrupts with priorities lower than its programmed value. After reset, the Priority Mask reg-  
ister contains priority seven, which effectively enables all interrupts. The programmer can then  
program the register with any valid priority level.  
8.2.1.3  
Interrupt Nesting  
When entering an interrupt handler, the CPU pushes the Processor Status Word onto the stack  
and clears the Interrupt Enable bit. The processor enters all interrupt handlers with maskable in-  
terrupts disabled. Maskable interrupts remain disabled until either the IRET instruction restores  
the Interrupt Enable bit or the programmer explicitly enables interrupts. Enabling maskable in-  
terrupts within an interrupt handler allows interrupts to be nested. Otherwise, interrupts are pro-  
cessed sequentially; one interrupt handler must finish before another executes.  
The simplest way to use the Interrupt Control Unit is without nesting. The operation and servicing  
of all sources of maskable interrupts is straightforward. However, the application tradeoff is that  
an interrupt handler will finish executing even if a higher priority interrupt occurs. This can add  
considerable latency to the higher priority interrupt.  
In the simplest terms, the Interrupt Control Unit asserts the maskable interrupt request to the CPU,  
waits for the interrupt acknowledge, then presents the interrupt type of the highest priority un-  
masked interrupt to the CPU. The CPU then executes the interrupt handler for that interrupt. Be-  
cause the interrupt handler never sets the Interrupt Enable bit, it can never be interrupted.  
The function of the Interrupt Control Unit is more complicated with interrupt nesting. In this case,  
an interrupt can occur during execution of an interrupt handler. That is, one interrupt can preempt  
another. Two rules apply for interrupt nesting:  
An interrupt source cannot preempt interrupts of higher priority.  
An interrupt source cannot preempt itself. The interrupt handler must finish executing  
before the interrupt is serviced again. (Special Fully Nested Mode is an exception. See  
“Special Fully Nested Mode” on page 8-8.)  
8-4  
INTERRUPT CONTROL UNIT  
8.3 FUNCTIONAL OPERATION IN MASTER MODE  
This section covers the process in which the Interrupt Control Unit receives interrupts and asserts  
the maskable interrupt request to the CPU.  
8.3.1 Typical Interrupt Sequence  
When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the In-  
terrupt Request register to indicate that the interrupt is pending. The Interrupt Control Unit checks  
all pending interrupt sources. If the interrupt is unmasked and meets the priority criteria (see “Pri-  
ority Resolution” on page 8-5), the Interrupt Control Unit asserts the maskable interrupt request  
to the CPU, then waits for the interrupt acknowledge.  
When the Interrupt Control Unit receives the interrupt acknowledge, it passes the interrupt type  
to the CPU. At that point, the CPU begin the interrupt processing sequence.(See “Interrupt/Ex-  
ception Processing” on page 2-39 for details.) The Interrupt Control Unit always passes the vector  
that has the highest priority at the time the acknowledge is received. If a higher priority interrupt  
occurs before the interrupt acknowledge, the higher priority interrupt has precedence.  
When it receives the interrupt acknowledge, the Interrupt Control Unit clears the corresponding  
bit in the Interrupt Request register and sets the corresponding bit in the In-Service register. The  
In-Service register keeps track of which interrupt handlers are being processed. At the end of an  
interrupt handler, the programmer must issue an End-of-Interrupt (EOI) command to explicitly  
clear the In-Service register bit. If the bit remains set, the Interrupt Control Unit cannot process  
any additional interrupts from that source.  
8.3.2 Priority Resolution  
The decision to assert the maskable interrupt request to the CPU is somewhat complicated. The  
complexity is needed to support interrupt nesting. First, an interrupt occurs and the corre-  
sponding Interrupt Request register bit is set. The Interrupt Control Unit then asserts the  
maskable interrupt request to the CPU, if the pending interrupt satisfies these requirements:  
1. its Interrupt Mask bit is cleared (it is unmasked)  
2. its priority is higher than the value in the Priority Mask register  
3. its In-Service bit is cleared  
4. its priority is equal to or greater than that of any interrupt whose In-Service bit is set  
The In-Service register keeps track of interrupt handler execution. The Interrupt Control Unit  
uses this information to decide whether another interrupt source has sufficient priority to preempt  
an interrupt handler that is executing.  
8-5  
 
INTERRUPT CONTROL UNIT  
8.3.2.1  
Priority Resolution Example  
This example illustrates priority resolution. Assume these initial conditions:  
the Interrupt Control Unit has been initialized  
no interrupts are pending  
no In-Service bits are set  
the Interrupt Enable bit is set  
all interrupts are unmasked  
the default priority scheme is being used  
the Priority Mask register is set to the lowest priority (seven)  
The example uses two external interrupt sources, INT0 and INT3, to describe the process.  
1. A low-to-high transition on INT0 sets its Interrupt Request bit. The interrupt is now  
pending.  
2. Because INT0 is the only pending interrupt, it meets all the priority criteria. The Interrupt  
Control Unit asserts the interrupt request to the CPU and waits for an acknowledge.  
3. The CPU acknowledges the interrupt.  
4. The Interrupt Control Unit passes the interrupt type (in this case, type 12) to the CPU.  
5. The Interrupt Control Unit clears the INT0 bit in the Interrupt Request register and sets the  
INT0 bit in the In-Service register.  
6. The CPU executes the interrupt processing sequence and begins executing the interrupt  
handler for INT0.  
7. During execution of the INT0 interrupt handler, a low-to-high transition on INT3 sets its  
Interrupt Request bit.  
8. The Interrupt Control Unit determines that INT3 has a lower priority than INT0, which is  
currently executing (INT0’s In-Service bit is set). INT3 does not meet the priority criteria,  
so no interrupt request is sent to the CPU. (If INT3were programmed with a higher  
priority than INT0, the request would be sent.) INT3 remains pending in the Interrupt  
Request register.  
9. The INT0 interrupt handler completes and sends an EOI command to clear the INT0 bit in  
the In-Service register.  
10. INT3 is still pending and now meets all the priority criteria. The Interrupt Control Unit  
asserts the interrupt request to the CPU and the process begins again.  
8-6  
INTERRUPT CONTROL UNIT  
8.3.2.2  
Interrupts That Share a Single Source  
Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For  
example, the three timers share a single input.) Although these interrupts share an input, each has  
its own interrupt vector. (For example, when a Timer 0 interrupt occurs, the Timer 0 interrupt  
handler is executed.) This section uses the three timers as an example to describe how these in-  
terrupts are prioritized and serviced.  
The Interrupt Status register acts as a second-level request register to process the timer interrupts.  
It contains a bit for each timer interrupt. When a timer interrupt occurs, both the individual Inter-  
rupt Status register bit and the shared Interrupt Request register bit are set. From this point, the  
interrupt is processed like any other interrupt source.  
When the shared interrupt is acknowledged, the timer interrupt with the highest priority (see Ta-  
ble 8-1 on page 8-3) at that time is serviced first and that timer’s Interrupt Status bit is cleared.  
If no other timer Interrupt Status bits are set, the shared Interrupt Request bit is also cleared. If  
other timer interrupts are pending, the Interrupt Request bit remains set.  
When the timer interrupt is acknowledged, the shared In-Service bit is set. No other timer inter-  
rupts can occur when the In-Service bit is set. If a second timer interrupt occurs while another  
timer interrupt is being serviced, the second interrupt remains pending until the interrupt handler  
for the first interrupt finishes and clears the In-Service bit. (This is true even if the second interrupt  
has a higher priority than the first.)  
8.3.3 Cascading with External 8259As  
For applications that require more external interrupt pins than the number provided on the Inter-  
rupt Control Unit, external 8259A modules can be used to increase the number of external inter-  
rupt pins. The cascade mode of the Interrupt Control Unit supports the external 8259As. The  
INT2/INTA0 and INT3/INTA1 pins can serve either of two functions. Outside cascade mode,  
they serve as external interrupt inputs. In cascade mode, they serve as interrupt acknowledge out-  
puts. INTA0 is the acknowledge for INT0, and INTA1 is the acknowledge for INT1. (See Figure  
8-2.)  
The INT2/INTA0 and INT3/INTA1 pins are inputs after reset until the pins are confiugred as out-  
puts. The pullup resistors ensure that the INTA pins never float (which would cause a spurious  
interrupt acknowledge to the 8259A). The value of the resistors must be high enough to prevent  
excessive loading on the pins.  
8-7  
INTERRUPT CONTROL UNIT  
INT  
INT0  
V
8259A  
or  
CC  
82C59A  
INTA  
INT  
INTA0  
INT1  
Interrupt  
Control  
Unit  
V
8259A  
or  
CC  
82C59A  
INTA  
INTA1  
A1211-A0  
Figure 8-2. Using External 8259A Modules in Cascade Mode  
Special Fully Nested Mode  
8.3.3.1  
Special fully nested mode is an optional feature normally used with cascade mode. It is applicable  
only to INT0 and INT1. In special fully nested mode, an interrupt request is serviced even if its  
In-Service bit is set.  
In cascade mode, an 8259A controls up to eight external interrupts that share a single interrupt  
input pin. Special fully nested mode allows the 8259A’s priority structure to be maintained. For  
example, assume that the CPU is servicing a low-priority interrupt from the 8259A. While the  
interrupt handler is executing, the 8259A receives a higher priority interrupt from one of its sourc-  
es. The 8259A applies its own priority criteria to that interrupt and asserts its interrupt to the In-  
terrupt Control Unit. Special fully nested mode allows the higher priority interrupt to be serviced  
even though the In-Service bit for that source is already set. A higher priority interrupt has pre-  
empted a lower priority interrupt, and interrupt nesting is fully maintained.  
Special fully nested mode can also be used without cascade mode. In this case, it allows a single  
external interrupt pin (either INT0 or INT1) to preempt itself.  
8-8  
   
INTERRUPT CONTROL UNIT  
8.3.4 Interrupt Acknowledge Sequence  
During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type  
to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector ad-  
dress in the interrupt vector table. (“Interrupt/Exception Processing” on page 2-39 describes the  
interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector ta-  
ble.)  
The interrupt types for all sources are fixed and unalterable (see Table 8-2). The Interrupt Control  
Unit passes these types to the CPU internally. The first external indication of the interrupt ac-  
knowledge sequence is the CPU fetch from the interrupt vector table.  
In cascade mode, the external 8259A supplies the interrupt type. In this case, the CPU runs an  
external interrupt acknowledge cycle to fetch the interrupt type from the 8259A (see “Interrupt  
Acknowledge Bus Cycle” on page 3-25).  
Table 8-2. Fixed Interrupt Types  
Interrupt Name  
Interrupt Type  
Timer 0  
Timer 1  
Timer 2  
DMA0  
DMA1  
INT0  
8
18  
19  
10  
11  
12  
13  
14  
15  
INT1  
INT2  
INT3  
8.3.5 Polling  
In some applications, it is desirable to poll the Interrupt Control Unit. The CPU polls the Interrupt  
Control Unit for any pending interrupts, and software can service interrupts whenever it is con-  
venient. The Poll and Poll Status registers support polling.  
Software reads the Poll register to get the type of the highest priority pending interrupt, then calls  
the corresponding interrupt handler. Reading the Poll register also acknowledges the interrupt.  
This clears the Interrupt Request bit and sets the In-Service bit for the interrupt. The Poll Status  
register has the same format as the Poll register, but reading the Poll Status register does not ac-  
knowledge the interrupt.  
8-9  
 
INTERRUPT CONTROL UNIT  
8.3.6 Edge and Level Triggering  
The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “In-  
terrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-trig-  
gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must  
remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge-  
detection circuitry. (See the current data sheet for timing requirements.) The edge-detection cir-  
cuitry must be reset to enable further interrupts to occur.  
A level-triggered interrupt is generated by a valid logic one on the external interrupt pin. The pin  
must remain high until after the CPU acknowledges the interrupt. Unlike edge-triggered inter-  
rupts, level-triggered interrupts will continue to occur if the pin remains high. A level-triggered  
external interrupt pin must go low before the EOI command to prevent another interrupt.  
NOTE  
When external 8259As are cascaded into the Interrupt Control Unit, INT0 and  
INT1 must be programmed for level-triggered interrupts.  
8.3.7 Additional Latency and Response Time  
The Interrupt Control Unit adds 5 clocks to the interrupt latency of the CPU. Cascade mode adds  
13 clocks to the interrupt response time because the CPU must run the interrupt acknowledge bus  
cycles. (See Figure 8-3 on page 8-11 and Figure 2-27 on page 2-46.)  
8-10  
 
INTERRUPT CONTROL UNIT  
Clocks  
Interrupt presented to control unit  
Interrupt presented to CPU  
5
INTA  
IDLE  
INTA  
IDLE  
READ IP  
IDLE  
4
2
4
5
4
Cascade Mode Only  
3 (5 if not cascade mode)  
READ CS  
IDLE  
PUSH FLAGS  
IDLE  
PUSH CS  
PUSH IP  
IDLE  
4
4
4
3
4
4
5
First instruction fetch  
from interrupt routine  
Total 55  
A1212-A0  
Figure 8-3. Interrupt Control Unit Latency and Response Time  
8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT  
Table 8-3 lists the Interrupt Control Unit registers in master mode with their Peripheral Control  
Block offset addresses. The remainder of this section describes the functions of the registers.  
Table 8-3. Interrupt Control Unit Registers in Master Mode  
Register Name  
INT3 Control  
Offset Address  
3EH  
3CH  
3AH  
38H  
34H  
36H  
32H  
30H  
2EH  
INT2 Control  
INT1 Control  
INT0 Control  
DMA0 Control  
DMA1 Control  
Timer Control  
Interrupt Status  
Interrupt Request  
8-11  
   
INTERRUPT CONTROL UNIT  
Table 8-3. Interrupt Control Unit Registers in Master Mode (Continued)  
Register Name  
In-Service  
Offset Address  
2CH  
2AH  
28H  
26H  
24H  
22H  
Priority Mask  
Interrupt Mask  
Poll Status  
Poll  
EOI  
8.4.1 Interrupt Control Registers  
Each interrupt source has its own Interrupt Control register. The Interrupt Control register allows  
you to define the behavior of each interrupt source. Figure 8-4 shows the registers for the timers  
and DMA channels, Figure 8-5 shows the registers for INT3:2, and Figure 8-6 shows the registers  
for INT0 and INT1.  
All Interrupt Control registers have a three-bit field (PM2:0) that defines the priority level for the  
interrupt source and a mask bit (MSK) that enables or disables the interrupt source. The mask bit  
is the same as the one in the Interrupt Mask register. Modifying a bit in either register also mod-  
ifies that same bit in the other register.  
The Interrupt Control registers for the external interrupt pins also have a bit (LVL) that selects  
level-triggered or edge-triggered mode for that interrupt. (See “Edge and Level Triggering” on  
page 8-10.)  
The Interrupt Control registers for the cascadable external interrupt pins (INT0 and INT1) have  
two additional bits to support the external 8259As. The CAS bit enables cascade mode, and the  
SFNM bit enables special fully nested mode.  
8-12  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Interrupt Control Register (internal sources)  
Register Mnemonic:  
Register Function:  
TCUCON, DMA0CON, DMA1CON  
Control register for the internal interrupt sources  
15  
0
M
S
K
P
M
2
P
M
1
P
M
0
A1213-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
MSK  
Interrupt  
Mask  
1
Clear to enable interrupts from this source.  
Defines the priority level for this source.  
PM2:0  
Priority  
Level  
111  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-4. Interrupt Control Register for Internal Sources  
8-13  
 
INTERRUPT CONTROL UNIT  
.
Register Name:  
Interrupt Control Register (non-cascadable pins)  
I2CON, I3CON  
Register Mnemonic:  
Register Function:  
Control register for the non-cascadable external  
internal interrupt pins  
15  
0
L
V
L
M
S
K
P
M
2
P
M
1
P
M
0
A1214-A0  
Bit  
Reset  
State  
Bit Name  
Mnemonic  
Function  
LVL  
Level-trigger  
0
Selects the interrupt triggering mode:  
0 = edge triggering  
1 = level triggering.  
MSK  
Interrupt  
Mask  
1
Clear to enable interrupts from this source.  
Defines the priority level for this source.  
PM2:0  
Priority  
Level  
111  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-5. Interrupt Control Register for Noncascadable External Pins  
8-14  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Interrupt Control Register (cascadable pins)  
Register Mnemonic:  
Register Function:  
I0CON, I1CON  
Control register for the cascadable external  
interrupt pins  
15  
0
S
F
N
M
C
A
S
L
V
L
M
S
K
P
M
2
P
M
1
P
M
0
A1215-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
SFNM  
Special  
Fully  
0
Set to enable special fully nested mode.  
Nested  
Mode  
CAS  
LVL  
Cascade  
Mode  
0
0
Set to enable cascade mode.  
Level-trigger  
Selects the interrupt triggering mode:  
0 = edge triggering  
1 = level triggering.  
The LVL bit must be set when external 8259As  
are cascaded into the Interrupt Control Unit.  
MSK  
Interrupt  
Mask  
1
Clear to enable interrupts from this source.  
Defines the priority level for this source.  
PM2:0  
Priority  
Level  
111  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins  
8-15  
 
INTERRUPT CONTROL UNIT  
8.4.2 Interrupt Request Register  
The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source  
requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is  
masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external  
interrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the Interrupt  
Request bit will be cleared, but the interrupt will not be serviced.  
Register Name:  
Interrupt Request Register  
REQST  
Register Mnemonic:  
Register Function:  
Stores pending interrupt requests  
15  
0
I
I
I
I
D
M
A
1
D
M
A
0
T
M
R
N
T
3
N
T
2
N
T
1
N
T
0
A1201-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
INT3:0  
External  
Interrupts  
0000 0  
A bit is set to indicate a pending interrupt from  
the corresponding external interrupt pin.  
DMA1:0  
TMR  
DMA  
Interrupt  
0
0
A bit is set to indicate a pending interrupt from  
the corresponding DMA channel.  
Timer  
Interrupt  
This bit is set to indicate a pending interrupt  
from one of the timers.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-7. Interrupt Request Register  
8.4.3 Interrupt Mask Register  
The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This reg-  
ister allows you to mask (disable) individual interrupts. Set a mask bit to disable interrupts from  
the corresponding source. The mask bit is the same as the one in the Interrupt Control register.  
Modifying a bit in either register also modifies that same bit in the other register.  
8-16  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Interrupt Mask Register  
IMASK  
Register Mnemonic:  
Register Function:  
Masks individual interrupt sources  
15  
0
I
I
I
I
D
M
A
1
D
M
A
0
T
M
R
N
T
3
N
T
2
N
T
1
N
T
0
A1202-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
Set a bit to mask (disable) interrupt requests  
INT3:0  
External  
Interrupt  
Mask  
0000 0  
from the corresponding external interrupt pin.  
DMA1:0  
TMR  
DMA  
Interrupt  
Mask  
0
0
Set to mask (disable) interrupt requests from  
the corresponding DMA channel .  
Timer  
Interrupt  
Mask  
Set to mask (disable) interrupt requests from  
the timers.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-8. Interrupt Mask Register  
8.4.4 Priority Mask Register  
The Priority Mask register (Figure 8-9) contains a three-level field that holds a priority value.  
This register allows you to mask interrupts based on their priority levels. Write a priority value  
to the PM2:0 field to specify the lowest priority interrupt to be serviced. This disables (masks)  
any interrupt source whose priority is lower than the PM2:0 value. After reset, the Priority Mask  
register is set to the lowest priority (seven), which enables all interrupts of any priority.  
8-17  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Priority Mask Register  
PRIMSK  
Register Mnemonic:  
Register Function:  
Masks lower-priority interrupt sources  
15  
0
P
M
2
P
M
1
P
M
0
A1216-A0  
Bit  
Reset  
State  
Bit Name  
Mnemonic  
Function  
Defines a priority-based interrupt mask.  
Interrupts whose priority is lower than this value  
are masked.  
PM2:0  
Priority  
Mask  
111  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-9. Priority Mask Register  
8.4.5 In-Service Register  
The In-Service register has a bit for each interrupt source. The bits indicate which source’s inter-  
rupt handlers are currently executing. The In-Service bit is set when an interrupt is acknowl-  
edged; the interrupt handler must clear it with an End-of-Interrupt (EOI) command. The Interrupt  
Control Unit uses the In-Service register to support interrupt nesting.  
8-18  
 
INTERRUPT CONTROL UNIT  
Register Name:  
In-Service Register  
INSERV  
Register Mnemonic:  
Register Function:  
Indicates which interrupt handlers are in process  
15  
0
I
I
I
I
D
M
A
1
D
M
A
0
T
M
R
N
T
3
N
T
2
N
T
1
N
T
0
A1192-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
INT3:0  
External  
Interrupt In-  
Service  
0000 0  
A bit is set to indicate that the corresponding  
external interrupt is being serviced.  
DMA1:0  
TMR  
DMA  
Interrupt In-  
Service  
0
0
This bit is set to indicate that the corresponding  
DMA channel interrupt is being serviced.  
Timer  
Interrupt In-  
Service  
This bit is set to indicate that a timer interrupt is  
being serviced.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-10. In-Service Register  
8.4.6 Poll and Poll Status Registers  
The Poll and Poll Status registers allow you to poll the Interrupt Control Unit and service inter-  
rupts through software. You can read these registers to determine whether an interrupt is pending  
and, if so, the interrupt type. The registers contain identical information, but reading them pro-  
duces different results.  
8-19  
INTERRUPT CONTROL UNIT  
Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPU  
had started the interrupt vectoring sequence. The Interrupt Control Unit updates the Interrupt Re-  
quest, In-Service, Poll, and Poll Status registers, as it does in the normal interrupt acknowledge  
sequence. However, the processor does not run an interrupt acknowledge sequence or fetch the  
vector from the vector table. Instead, software must read the interrupt type and execute the proper  
routine to service the pending interrupt.  
Reading the Poll Status register (Figure 8-12) will merely transmit the status of the polling bits  
without modifying any of the other Interrupt Controller registers.  
Register Name:  
Poll Register  
POLL  
Register Mnemonic:  
Register Function:  
Read to check for and acknowledge pending  
interrupts when polling  
15  
0
I
V
T
4
V
T
3
V
T
2
V
T
1
V
T
0
R
E
Q
A1208-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
IREQ  
Interrupt  
Request  
0
This bit is set to indicate a pending interrupt.  
VT4:0  
Vector Type  
0
Contains the interrupt type of the highest  
priority pending interrupt.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-11. Poll Register  
8-20  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Poll Status Register  
POLLSTS  
Register Mnemonic:  
Register Function:  
Read to check for pending interrupts when polling  
15  
0
I
V
T
4
V
T
3
V
T
2
V
T
1
V
T
0
R
E
Q
A1209-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
IREQ  
Interrupt  
Request  
0
This bit is set to indicate a pending interrupt.  
VT4:0  
Vector Type  
0
Contains the interrupt type of the highest  
priority pending interrupt.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-12. Poll Status Register  
8.4.7 End-of-Interrupt (EOI) Register  
The End-of-Interrupt register (Figure 8-13) issues an End-of-Interrupt (EOI) command to the In-  
terrupt Control Unit, which clears the In-Service bit for the associated interrupt. An interrupt han-  
dler typically ends with an EOI command. There are two types of EOI commands: nonspecific  
and specific. A nonspecific EOI simply clears the In-Service bit of the highest priority interrupt.  
To issue a nonspecific EOI command, set the NSPEC bit. (Write 8000H to the EOI register.)  
A specific EOI clears a particular In-Service bit. To issue a specific EOI command, clear the  
NSPEC bit and write the VT4:0 bits with the interrupt type of the interrupt whose In-Service bit  
you wish to clear. For example, to clear the In-Service bit for INT2, write 000EH to the EOI reg-  
ister. The timer interrupts share an In-Service bit. To clear the In-Service bit for any timer inter-  
rupt with a specific EOI, write 0008H (interrupt type 8) to the EOI register.  
8-21  
 
INTERRUPT CONTROL UNIT  
Register Name:  
End-of-Interrupt Register  
EOI  
Register Mnemonic:  
Register Function:  
Used to issue an EOI command  
15  
0
N
S
P
E
C
V
T
4
V
T
3
V
T
2
V
T
1
V
T
0
A1210-A0  
Bit  
Reset  
State  
Bit Name  
Mnemonic  
Function  
NSPEC  
VT4:0  
Nonspecific  
EOI  
0
Set to issue a nonspecific EOI.  
Interrupt  
Type  
0 0000  
Write with the interrupt type of the interrupt  
whose In-Service bit is to be cleared.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-13. End-of-Interrupt Register  
8.4.8 Interrupt Status Register  
The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer  
interrupt. The CPU sets the DMA Halt bit to suspend DMA transfers while an NMI is processed.  
Software can also read and write this bit. See “Suspension of DMA Transfers” on page 10-20 for  
details. A timer bit is set to indicate a pending interrupt and is cleared when the interrupt request  
is acknowledged. Any number of bits can be set at any one time.  
8-22  
 
INTERRUPT CONTROL UNIT  
Register Name:  
Interrupt Status Register  
INTSTS  
Register Mnemonic:  
Register Function:  
Indicates pending shared-source interrupts and  
DMA suspension  
15  
0
D
H
L
T
M
R
2
T
M
R
1
T
M
R
0
T
A1193-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
This bit is set to suspend DMA activity.  
DHLT  
DMA Halt  
0
TMR2:0  
Timer  
Interrupt  
Pending  
000  
A bit is set to indicate a pending interrupt from  
the corresponding timer.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-14. Interrupt Status Register  
NOTE  
Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.  
A conflict with the internal use of the register may cause incorrect processing  
of timer interrupts.  
The DHLT bit does not function when the interrupt controller is in slave mode.  
8.5 SLAVE MODE  
Although Master mode is the most common, Slave mode is useful in larger system designs. In  
Slave mode, an external 8259A module controls the interrupt input to the CPU and acts as the  
master interrupt controller. The Interrupt Control Unit processes only the internal interrupt re-  
quests and acts as an interrupt input to the external 8259A. In simplest terms, the Interrupt Control  
Unit behaves like a cascaded 8259A to the master 8259A. (See Figures 8-15 and 8-16.)  
8-23  
 
INTERRUPT CONTROL UNIT  
INT0  
INT  
V
CC  
8259A/  
82C59A  
INTA  
INTA  
80186  
Modular  
Core  
Cascade  
Address  
Decode  
Select  
IRQ  
A1194-A0  
Figure 8-15. Interrupt Control Unit in Slave Mode  
8-24  
 
INTERRUPT CONTROL UNIT  
DMA  
0
DMA  
1
Timer 0 Timer 1 Timer 2  
Interrupt  
Priority  
Resolver  
Vector  
Generation  
Logic  
To External 8259A  
Interrupt Request  
F - Bus  
A1195-A0  
Figure 8-16. Interrupt Sources in Slave Mode  
8.5.1 Slave Mode Programming  
Some registers differ between Slave mode and Master mode. Slave mode adds the Interrupt Vec-  
tor Register; it does not support the Poll, Poll Status Registers, INT3 and INT2 Control registers;  
and it replaces the Timer, INT1 and INT0 Control registers with individual Timer 0, Timer 1, and  
Timer 2 Control registers. The remaining registers retain the same functions as in Master mode;  
however, some bit positions change to accommodate the addition of the individual timer inter-  
rupts and the deletion of the external interrupts. Table 8-4 compares the Master and Slave mode  
registers and lists their PCB offset addresses.  
8-25  
 
INTERRUPT CONTROL UNIT  
8.5.1.1  
Interrupt Vector Register  
The Interrupt Vector Register is used only in Slave mode. In Master mode, the interrupt vector  
types are fixed; in Slave mode they are programmable. The Interrupt Vector Register is used to  
specify the five most-significant bits of the interrupt vector type. The three least-significant bits  
are fixed (Table 8-5).  
Table 8-4. Interrupt Control Unit Register Comparison  
Master Mode  
Register Name  
Slave Mode  
Register Name  
PCB Offset  
Address  
INT3 Control  
INT2 Control  
INT1 Control  
INT0 Control  
DMA1 Control  
DMA0 Control  
Timer Control  
Interrupt Status  
Interrupt Request  
In-Service  
(not used)  
3EH  
3CH  
3AH  
38H  
36H  
34H  
32H  
30H  
2EH  
2CH  
2AH  
28H  
26H  
24H  
22H  
20H  
(not used)  
Timer 2 Control  
Timer 1 Control  
DMA1 Control  
DMA0 Control  
Timer 0 Control  
Interrupt Status  
Interrupt Request  
In-Service  
Priority Mask  
Interrupt Mask  
Poll Status  
Priority Mask  
Interrupt Mask  
(not used)  
Poll  
(not used)  
EOI  
EOI  
(not used)  
Interrupt Vector  
Table 8-5. Slave Mode Fixed Interrupt Type Bits  
Type Bits  
Interrupt Source  
2
1
0
Timer 0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(reserved)  
DMA 0  
DMA 1  
Timer 1  
Timer 2  
(reserved)  
(reserved)  
8-26  
   
INTERRUPT CONTROL UNIT  
Register Name:  
Interrupt Vector Register (Slave Mode only)  
Register Mnemonic:  
Register Function:  
INTVEC  
Specifies the five most-significant bit of the interrupt  
vector types for the internal interrupt sources  
15  
0
T
4
T
3
T
2
T
1
T
0
A1196-A0  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
Specifies the five most-significant bits of the  
interrupt vector types for the internal interrupt  
sources. The three least-significant bits are  
fixed (see Table 8-5).  
T4:0  
Interrupt  
Vector Type  
Field  
00000  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-17. Interrupt Vector Register (Slave Mode Only)  
End-Of-Interrupt Register  
8.5.1.2  
The End-of-Interrupt (EOI) register has the same function in Slave mode as in Master mode.  
However, non-specific EOI commands are not supported, so the NSPEC bit is omitted from the  
register. Only specific EOI commands can be issued. To clear an In-Service bit in Slave mode,  
write the three least-significant bits of the interrupt type (from Table 8-5) to the VT2:0 bits.  
8-27  
INTERRUPT CONTROL UNIT  
Register Name:  
End-of-Interrupt Register (in Slave Mode)  
EOI  
Register Mnemonic:  
Register Function:  
Used to issue the EOI command  
15  
0
V
T
2
V
T
1
V
T
0
A1197-A0  
Bit  
Reset  
State  
Bit Name  
Mnemonic  
Function  
VT2:0  
Interrupt  
Type  
0
Write the three LSBs of the interrupt type (see  
Table 8-5) to these bits to issue an EOI  
command in slave mode.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 8-18. End-of-Interrupt Register in Slave Mode  
Other Registers  
8.5.1.3  
The Priority Mask register is identical in Slave mode and Master mode. The Interrupt Request,  
Interrupt Mask, and In-Service registers retain the same function, but individual bits differ to ac-  
commodate the addition of the individual timer interrupts and the deletion of the external inter-  
rupts. Figure 8-19 shows the bit positions for Slave mode.  
15  
0
T
M
R
2
T
M
R
1
D
M
A
0
D
M
A
1
T
M
R
0
Figure 8-19. Request, Mask, and In-Service Registers  
8-28  
 
INTERRUPT CONTROL UNIT  
8.5.2 Interrupt Vectoring in Slave Mode  
In Slave mode, the external 8259A module acts as the master interrupt controller. Therefore, in-  
terrupt acknowledge cycles are required for every interrupt, including those from integrated pe-  
ripherals. During the first interrupt acknowledge cycle, the external 8259A determines which  
slave interrupt controller has the highest priority interrupt request. It then drives that slave’s ad-  
dress onto its CAS2:0 pins (Figure 8-20). External logic must decode the correct slave address  
from the CAS2:0 pins to drive the SELECT pin.  
T1  
T2  
T3  
T4  
TI  
TI  
T1  
T2  
T3  
T4  
CLKOUT  
S2:0  
INTA  
INTA  
INTA0  
SELECT  
LOCK  
Slave Cascade Address From 8259A  
CAS2:0  
NOTES:  
1. INT1/SELECT has the SELECT function in slave mode.  
2. INT2/INTA0 has the INTA0 function in slave mode.  
3. Cascade address is driven by the external 8259A.  
4. SELECT must be driven before phase 2 of T2 of the second INTA.  
5. SELECT read by processor.  
6. ALE is generated for each INTA.  
7. RD is inactive.  
A1199-A0  
Figure 8-20. Interrupt Vectoring in Slave Mode  
The SELECT pin is the slave-select input to the Interrupt Control Unit. During the second inter-  
rupt acknowledge cycle, the highest-priority slave interrupt controller transfers the interrupt type  
of its highest priority interrupt to the CPU. If the Interrupt Control Unit is the highest-priority  
slave, it passes the interrupt type to the CPU internally; however, the interrupt acknowledge cycle  
still must occur for the benefit of the external 8259A module.  
8-29  
 
INTERRUPT CONTROL UNIT  
External interrupt acknowledge cycles must be run for every maskable interrupt. Therefore, the  
interrupt response time for every interrupt will be 55 clocks, as shown in Figure 8-21.  
Clocks  
Interrupt presented to Interrupt Control Unit  
5
Interrupt presented to external 82C59A  
INTA  
IDLE  
INTA  
IDLE  
READ IP  
IDLE  
READ CS  
IDLE  
PUSH FLAGS  
IDLE  
PUSH CS  
PUSH IP  
IDLE  
4
2
4
5
4
3
4
4
4
3
4
4
5
First instruction fetch  
from interrupt routine  
Total 55  
A1200-A0  
Figure 8-21. Interrupt Response Time in Slave Mode  
8.5.3 Initializing the Interrupt Control Unit for Master Mode  
Follow these steps to initialize the Interrupt Control Unit for Master mode.  
1. Determine which interrupt sources you want to use.  
2. Determine whether to use the default priority scheme or devise your own.  
3. Program the Interrupt Control register for each interrupt source.  
— For external interrupt pins, select edge or level triggering.  
— For INT0 or INT1, enable cascade mode, special fully nested mode, or both, if you  
wish to use them.  
— If you are using a custom priority scheme, program the priority level for each interrupt  
source.  
4. Program the Priority Mask with a priority mask level, if you wish to mask interrupts based  
on priority. (The default is level seven, which enables all interrupt levels.)  
8-30  
 
INTERRUPT CONTROL UNIT  
5. Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable.  
Example 8-1 shows sample code to initialize the Interrupt Control Unit.  
$mod186  
name  
;
example_80C186_ICU_initialization  
;This routine configures the interrupt controller to provide two cascaded  
;interrupt inputs (through an external 8259A connected to INT0 and INTA0#)  
;and two direct interrupt inputs connected to INT1 and INT3. The default  
;priorities are used.  
;
;The example assumes that the register addresses have been properly defined.  
;
code  
segment  
assume cs:code  
proc near  
push dx  
set_int_  
push ax  
mov ax,0110111B  
mov dx,I0CON  
out dx,ax  
mov ax,01001101B  
mov dx,IMASK  
out dx,ax  
pop ax  
;cascade mode, priority seven  
;INT0 control register  
;unmask INT1 and INT3  
pop dx  
ret  
set_int_  
code  
endp  
ends  
end  
Example 8-1. Initializing the Interrupt Control Unit for Master Mode  
8-31  
 
9
Timer/Counter Unit  
CHAPTER 9  
TIMER/COUNTER UNIT  
The Timer/Counter Unit can be used in many applications. Some of these applications include a  
real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented  
in a system design. A real-time clock can be used to update time-dependent memory variables. A  
square-wave generator can be used to provide a system clock tick for peripheral devices. (See  
“Timer/Counter Unit Application Examples” on page 9-17 for code examples that configure the  
Timer/Counter Unit for these applications.)  
9.1 FUNCTIONAL OVERVIEW  
The Timer/Counter Unit is composed of three independent 16-bit timers (see Figure 9-1). The op-  
eration of these timers is independent of the CPU. The internal Timer/Counter Unit can be mod-  
eled as a single counter element, time-multiplexed to three register banks. The register banks are  
dual-ported between the counter element and the CPU. During a given bus cycle, the counter el-  
ement and CPU can both access the register banks; these accesses are synchronized.  
The Timer/Counter Unit is serviced over four clock periods, one timer during each clock, with an  
idle clock at the end (see Figure 9-2). No connection exists between the counter element’s se-  
quencing through timer register banks and the Bus Interface Unit’s sequencing through T-states.  
Timer operation and bus interface operation are asynchronous. This time-multiplexed scheme re-  
sults in a delay of 2½ to 6½ CLKOUT periods from timer input to timer output.  
Each timer keeps its own running count and has a user-defined maximum count value. Timers 0  
and 1 can use one maximum count value (single maximum count mode) or two alternating max-  
imum count values (dual maximum count mode). Timer 2 can use only one maximum count val-  
ue. The control register for each timer determines the counting mode to be used. When a timer is  
serviced, its present count value is incremented and compared to the maximum count for that tim-  
er. If these two values match, the count value resets to zero. The timers can be configured either  
to stop after a single cycle or to run continuously.  
Timers 0 and 1 are functionally identical. Figure 9-3 illustrates their operation. Each has a  
latched, synchronized input pin and a single output pin. Each timer can be clocked internally or  
externally. Internally, the timer can either increment at ¼ CLKOUT frequency or be prescaled by  
Timer 2. A timer that is prescaled by Timer 2 increments when Timer 2 reaches its maximum  
count value.  
9-1  
TIMER/COUNTER UNIT  
T0 In  
T1 In  
Transition Latch/  
Synchronizer  
Transition Latch/  
Synchronizer  
Timer 0  
Registers  
T0  
Out  
Output Latch  
Output Latch  
Counter  
Element  
CPU  
Timer 1  
Registers  
T1  
Out  
Timer 2  
Registers  
Interrupt  
Latch  
CPU  
Clock  
A1292-0A  
Figure 9-1. Timer/Counter Unit Block Diagram  
9-2  
 
TIMER/COUNTER UNIT  
Timer 0 Timer 1 Timer 2  
Timer 0 Timer 1 Timer 2  
Timer 0  
ServicedServicedServiced Dead ServicedServicedServiced Dead Serviced  
3
4
1
T0IN  
2
5
T1IN  
T0OUT  
T1OUT  
NOTES:  
1. T0IN resolution time (setup time met).  
2. T1IN resolution time (setup time not met).  
3. Modified count value written into Timer 0 count register.  
4. T1IN resolution time, count value written into Timer 1 count register.  
5. T1IN resolution time.  
A1293-0A  
Figure 9-2. Counter Element Multiplexing and Timer Input Synchronization  
9-3  
 
TIMER/COUNTER UNIT  
Timer  
Enabled  
(EN = 1)  
?
No  
Done  
Start  
Yes  
External  
Clocking  
(EXT = 1)  
?
No  
Yes  
No  
Yes  
Retrigger  
(RTG = 1)  
?
Lo to Hi  
transition on input  
pin since last  
service  
Lo to Hi  
Yes  
Yes  
No  
Timer Input  
at High Level  
?
transition on input  
pin since last  
service  
?
?
Yes  
No  
No  
Clear Count  
Register  
No  
Prescaler On  
(P = 1)  
?
Yes  
Done  
Did Timer 2  
Reach Maxcount  
Last Service  
State  
Yes  
Increment  
Counter  
?
No  
Continued  
"A"  
Done  
A1294-0A  
Figure 9-3. Timers 0 and 1 Flow Chart  
9-4  
 
TIMER/COUNTER UNIT  
Continued From  
"A"  
Alternating  
Maxcount Regs  
(ALT = 1)  
?
Yes  
No  
No  
(Use"B")  
Yes  
(Use"A")  
Using  
Counter =  
Compare "A"  
?
Yes  
Maxcount A  
(RIU = 0)  
?
No  
No  
No  
Counter =  
Compare "A"  
?
Counter =  
Compare "B"  
?
Done  
Yes  
Yes  
Pulse TOUT Pin  
Low For 1 Clock  
Set RIU Bit  
TOUT Pin Driven Low  
Clear RIU Bit  
TOUT Pin Driven High  
Yes  
Yes  
Continuous Mode  
Continuous Mode  
(CONT=1)  
?
(CONT=1)  
?
No  
No  
No  
Interrupt Bit Set  
?
Clear Enable Bit  
(Stop Counting)  
Clear Enable Bit  
(Stop Counting)  
Yes  
Request Interrupt  
Clear Counter  
Done  
A1295-0A  
Figure 9-3. Timers 0 and 1 Flow Chart (Continued)  
9-5  
TIMER/COUNTER UNIT  
When configured for internal clocking, the Timer/Counter Unit uses the input pins either to en-  
able timer counting or to retrigger the associated timer. Externally, a timer increments on low-to-  
high transitions on its input pin (up to ¼ CLKOUT frequency).  
Timers 0 and 1 each have a single output pin. Timer output can be either a single pulse, indicating  
the end of a timing cycle, or a variable duty cycle wave. These two output options correspond to  
single maximum count mode and dual maximum count mode, respectively (Figure 9-4). Inter-  
rupts can be generated at the end of every timing cycle.  
Timer 2 has no input or output pins and can be operated only in single maximum count mode  
(Figure 9-4). It can be used as a free-running clock and as a prescaler to Timers 0 and 1. Timer 2  
can be clocked only internally, at ¼ CLKOUT frequency. Timer 2 can also generate interrupts at  
the end of every timing cycle.  
Maxcount A  
Maxcount B  
Dual Maximum  
Count Mode  
One CPU  
Clock  
Maxcount A  
Single Maximum  
Count Mode  
Figure 9-4. Timer/Counter Unit Output Modes  
9.2 PROGRAMMING THE TIMER/COUNTER UNIT  
Each timer has three registers: a Timer Control register (Figure 9-5 and Figure 9-6), a Timer  
Count register (Figure 9-7) and a Timer Maxcount Compare register (Figure 9-8). Timers 0 and  
1 also have access to an additional Maxcount Compare register. The Timer Control register con-  
trols timer operation. The Timer Count register holds the current timer count value, and the Max-  
count Compare register holds the maximum timer count value.  
9-6  
 
TIMER/COUNTER UNIT  
Register Name:  
Timer 0 and 1 Control Registers  
T0CON, T1CON  
Register Mnemonic:  
Register Function:  
Defines Timer 0 and 1 operation.  
15  
0
E
N
I
N
H
I
N
T
R
I
U
M
C
R
T
G
P
E
X
T
A
L
T
C
O
N
T
A1297-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
EN  
Enable  
0
Set to enable the timer. This bit can be written only  
when the INH bit is set.  
INH  
INT  
RIU  
MC  
Inhibit  
X
X
X
X
Set to enable writes to the EN bit. Clear to ignore  
writes to the EN bit. The INH bit is not stored; it  
always reads as zero.  
Interrupt  
Set to generate an interrupt request when the Count  
register equals a Maximum Count register. Clear to  
disable interrupt requests.  
Register In  
Use  
Indicates which compare register is in use. When set,  
the current compare register is Maxcount Compare B;  
when clear, it is Maxcount Compare A.  
Maximum  
Count  
This bit is set when the counter reaches a maximum  
count. The MC bit must be cleared by writing to the  
Timer Control register. This is not done automati-  
cally. If MC is clear, the counter has not reached a  
maximum count.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 9-5. Timer 0 and Timer 1 Control Registers  
9-7  
 
TIMER/COUNTER UNIT  
Register Name:  
Timer 0 and 1 Control Registers  
T0CON, T1CON  
Register Mnemonic:  
Register Function:  
Defines Timer 0 and 1 operation.  
15  
0
E
N
I
N
H
I
N
T
R
I
U
M
C
R
T
G
P
E
X
T
A
L
T
C
O
N
T
A1297-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
RTG  
Retrigger  
X
This bit specifies the action caused by a low-to-high  
transition on the TMR INx input. Set RTG to reset the  
count; clear RTG to enable counting. This bit is  
ignored with external clocking (EXT=1).  
P
Prescaler  
X
Set to increment the timer when Timer 2 reaches its  
maximum count. Clear to increment the timer at ¼  
CLKOUT. This bit is ignored with external clocking  
(EXT=1).  
EXT  
ALT  
External  
Clock  
X
X
Set to use external clock; clear to use internal clock.  
The RTG and P bits are ignored with external clocking  
(EXT set).  
Alternate  
Compare  
Register  
This bit controls whether the timer runs in single or  
dual maximum count mode (see Figure 9-4 on page  
9-6). Set to specify dual maximum count mode; clear  
to specify single maximum count mode.  
CONT  
Continuous  
Mode  
X
Set to cause the timer to run continuously. Clear to  
disable the counter (clear the EN bit) after each  
counting sequence.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)  
9-8  
TIMER/COUNTER UNIT  
Register Name:  
Timer 2 Control Register  
T2CON  
Register Mnemonic:  
Register Function:  
Defines Timer 2 operation.  
15  
0
E
N
I
N
H
I
N
T
M
C
C
O
N
T
A1298-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
Set to enable the timer. This bit can be written  
EN  
Enable  
0
only when the INH bit is set.  
INH  
INT  
MC  
Inhibit  
X
X
X
Set to enable writes to the EN bit. Clear to  
ignore writes to the EN bit. The INH bit is not  
stored; it always reads as zero.  
Interrupt  
Set to generate an interrupt request when the  
Count register equals a Maximum Count  
register. Clear to disable interrupt requests.  
Maximum  
Count  
This bit is set when the counter reaches a  
maximum count. The MC bit must be cleared  
by writing to the Timer Control register. This  
is not done automatically. If MC is clear, the  
counter has not reached a maximum count.  
CONT  
Continuous  
Mode  
X
Set to cause the timer to run continuously.  
Clear to disable the counter (clear the EN bit)  
after each counting sequence.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 9-6. Timer 2 Control Register  
9-9  
 
TIMER/COUNTER UNIT  
Register Name:  
Timer Count Register  
Register Mnemonic:  
Register Function:  
T0CNT, T1CNT, T2CNT  
Contains the current timer count.  
15  
0
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
9
T
C
8
T
C
7
T
C
6
T
C
5
T
C
4
T
C
3
T
C
2
T
C
1
T
C
0
5
4
3
2
1
0
A1299-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
TC15:0  
Timer Count  
Value  
XXXXH  
Contains the current count of the associated  
timer.  
Figure 9-7. Timer Count Registers  
9-10  
 
TIMER/COUNTER UNIT  
Register Name:  
Timer Maxcount Compare Register  
Register Mnemonic:  
Register Function:  
T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA  
Contains timer maximum count value.  
15  
0
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
9
T
C
8
T
C
7
T
C
6
T
C
5
T
C
4
T
C
3
T
C
2
T
C
1
T
C
0
5
4
3
2
1
0
A1300-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Timer  
Compare  
Value  
Function  
TC15:0  
XXXXH  
Contains the maximum value a timer will count  
to before resetting its Count register to zero.  
Figure 9-8. Timer Maxcount Compare Registers  
9.2.1 Initialization Sequence  
When initializing the Timer/Counter Unit, the following sequence is suggested:  
1. If timer interrupts will be used, program interrupt vectors into the Interrupt Vector Table.  
2. Clear the Timer Count register. This must be done before the timer is enabled because  
the count register is undefined at reset. Clearing the count register ensures that counting  
begins at zero.  
3. Write the desired maximum count value to the Timer Maxcount Compare register. For  
dual maximum count mode, write a value to both Maxcount Compare A and B.  
4. Program the Timer Control register to enable the timer. When using Timer 2 to prescale  
another timer, enable Timer 2 last. If Timer 2 is enabled first, it will be at an unknown  
point in its timing cycle when the timer to be prescaled is enabled. This results in an  
unpredictable duration of the first timing cycle for the prescaled timer.  
9-11  
 
TIMER/COUNTER UNIT  
9.2.2 Clock Sources  
The 16-bit Timer Count register increments once for each timer event. A timer event can be a  
low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU  
16  
clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 ) events can be count-  
ed.  
Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer  
events by setting the External (EXT) bit in their control registers. Transitions on the external pin  
are synchronized to the CPU clock before being presented to the timer circuitry. The timer counts  
transitions on this pin. The input signal must go low, then high, to cause the timer to increment.  
The maximum count-rate for the timers is ¼ the CPU clock rate (measured at CLKOUT) because  
the timers are serviced only once every four clocks.  
All timers can use transitions of the CPU clock as timer events. For internal clocking, the timer  
increments every fourth CPU clock due to the counter element’s time-multiplexed servicing  
scheme. Timer 2 can use only the internal clock as a timer event.  
Timers 0 and 1 can also use Timer 2 reaching its maximum count as a timer event. In this config-  
uration, Timer 0 or Timer 1 increments each time Timer 2 reaches its maximum count. See Table  
9-1 for a summary of clock sources for Timers 0 and 1. Timer 2 must be initialized and running  
in order to increment values in other timer/counters.  
Table 9-1. Timer 0 and 1 Clock Sources  
EXT  
P
Clock Source  
0
0
1
0
1
Timer clocked internally at ¼ CLKOUT frequency.  
Timer clocked internally, prescaled by Timer 2.  
Timer clocked externally at up to ¼ CLKOUT frequency.  
X
9.2.3 Counting Modes  
All timers have a Timer Count register and a Maxcount Compare A register. Timers 0 and 1 also  
have access to a second Maxcount Compare B register. Whenever the contents of the Timer  
Count register equal the contents of the Maxcount Compare register, the count register resets to  
zero. The maximum count value will never be stored in the count register. This is because the  
counter element increments, compares and resets a timer in one clock cycle. Therefore, the max-  
imum value is never written back to the count register. The Maxcount Compare register can be  
written at any time during timer operation.  
9-12  
 
TIMER/COUNTER UNIT  
The timer counting from its initial count (usually zero) to its maximum count (either Maxcount  
Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of  
0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count  
of 1, etc.  
Only equivalence between the Timer Count and Maxcount Compare registers is checked. The  
count does not reset to zero if its value is greater than the maximum count. If the count value ex-  
ceeds the Maxcount Compare value, the timer counts to 0FFFFH, increments to zero, then counts  
to the value in the Maxcount Compare register. Upon reaching a maximum count value, the Max-  
imum Count (MC) bit in the Timer Control register sets. The MC bit must be cleared by writing  
to the Timer Control register. This is not done automatically.  
The Timer/Counter Unit can be configured to execute different counting sequences. The timers  
can operate in single maximum count mode (all timers) or dual maximum count mode (Timers 0  
and 1 only). They can also be programmed to run continuously in either of these modes. The Al-  
ternate (ALT) bit in the Timer Control register determines the counting modes used by Timers 0  
and 1.  
All timers can use single maximum count mode, where only Maxcount Compare A is used. The  
timer will count to the value contained in Maxcount Compare A and reset to zero. Timer 2 can  
operate only in this mode.  
Timers 0 and 1 can also use dual maximum count mode. In this mode, Maxcount Compare A and  
Maxcount Compare B are both used. The timer counts to the value contained in Maxcount Com-  
pare A, resets to zero, counts to the value contained in Maxcount Compare B, and resets to zero  
again. The Register In Use (RIU) bit in the Timer Control register indicates which Maxcount  
Compare register is currently in use.  
The timers can be programmed to run continuously in single maximum count and dual maximum  
count modes. The Continuous (CONT) bit in the Timer Control register determines whether a  
timer is disabled after a single counting sequence.  
9.2.3.1  
Retriggering  
The timer input pins affect timer counting in three ways (see Table 9-2). The programming of the  
External (EXT) and Retrigger (RTG) bits in the Timer Control register determines how the input  
signals are used. When the timers are clocked internally, the RTG bit determines whether the in-  
put pin enables timer counting or retriggers the current timing cycle.  
When the EXT and RTG bits are clear, the timer counts internal timer events. In this mode, the  
input is level-sensitive, not edge-sensitive. A low-to-high transition on the timer input is not re-  
quired for operation. The input pin acts as an external enable. If the input is high, the timer will  
count through its sequence, provided the timer remains enabled.  
9-13  
TIMER/COUNTER UNIT  
Table 9-2. Timer Retriggering  
EXT  
RTG  
Timer Operation  
0
0
0
1
Timer counts internal events, if input pin remains high.  
Timer counts internal events; count resets to zero on every low-to-high transition on  
the input pin.  
1
X
Timer input acts as clock source.  
When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer input  
pin causes the Count register to reset to zero. After the timer is enabled, counting begins only after  
the first low-to-high transition on the input pin. If another low-to-high transition occurs before  
the end of the timer cycle, the timer count resets to zero and the timer cycle begins again. In dual  
maximum count mode, the Register In Use (RIU) bit does not clear when a low-to-high transition  
occurs. For example, if the timer retriggers while Maxcount Compare B is in use, the timer resets  
to zero and counts to maximum count B before the RIU bit clears. In dual maximum count  
mode, the timer retriggering extends the use of the current Maxcount Compare register.  
9.2.4 Pulsed and Variable Duty Cycle Output  
Timers 0 and 1 each have an output pin that can perform two functions. First, the output can be a  
single pulse, indicating the end of a timing cycle (single maximum count mode). Second, the out-  
put can be a level, indicating the Maxcount Compare register currently in use (dual maximum  
count mode). The output occurs one clock after the counter element services the timer when the  
maximum count is reached (see Figure 9-9).  
With external clocking, the time between a transition on a timer input and the corresponding tran-  
sition of the timer output varies from 2½ to 6½ clocks. This delay occurs due to the time-multi-  
plexed servicing scheme of the Timer/Counter Unit. The exact timing depends on when the input  
occurs relative to the counter element’s servicing of the timer. Figure 9-2 on page 9-3 shows the  
two extremes in timer output delay. Timer 0 demonstrates the best possible case, where the input  
occurs immediately before the timer is serviced. Timer 1 demonstrates the worst possible case,  
where the input is latched, but the setup time is not met and the input is not recognized until the  
counter element services the timer again.  
In single maximum count mode, the timer output pin goes low for one CPU clock period (see Fig-  
ure 9-4 on page 9-6). This occurs when the count value equals the Maxcount Compare A value.  
If programmed to run continuously, the timer generates periodic pulses.  
9-14  
 
TIMER/COUNTER UNIT  
Timer 0  
Serviced  
1
Internal Count Value  
TxOUT Pin  
Maxcount - 1  
0
NOTE: 1. T  
CLOV1  
A1301-0A  
Figure 9-9. TxOUT Signal Timing  
In dual maximum count mode, the timer output pin indicates which Maxcount Compare register  
is currently in use. A low output indicates Maxcount Compare B, and a high output indicates  
Maxcount Compare A (see Figure 9-4 on page 9-6). If programmed to run continuously, a repet-  
itive waveform can be generated. For example, if Maxcount Compare A contains 10, Maxcount  
Compare B contains 20, and CLKOUT is 12.5 MHz, the timer generates a 33 percent duty cycle  
waveform at 104 KHz. The output pin always goes high at the end of the counting sequence (even  
if the timer is not programmed to run continuously).  
9.2.5 Enabling/Disabling Counters  
Each timer has an Enable (EN) bit in its Control register to allow or prevent timer counting. The  
Inhibit (INH) bit controls write accesses to the EN bit. Timers 0 and 1 can be programmed to use  
their input pins as enable functions also. If a timer is disabled, the count register does not incre-  
ment when the counter element services the timer.  
The Enable bit can be altered by programming or the timers can be programmed to disable them-  
selves at the end of a counting sequence with the Continuous (CONT) bit. If the timer is not pro-  
grammed for continuous operation, the Enable bit automatically clears at the end of a counting  
sequence. In single maximum count mode, this occurs after Maxcount Compare A is reached. In  
dual maximum count mode, this occurs after Maxcount Compare B is reached (Timers 0 and 1  
only).  
9-15  
 
TIMER/COUNTER UNIT  
The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer  
counting. When using internal clocking, the input pin can be programmed either to enable the tim-  
er or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control reg-  
ister. When used as an enable function, the input pin either allows (input high) or prevents (input  
low) timer counting. To ensure recognition of an input level, it must be valid for four CPU clocks.  
This is due to the counter element’s time-multiplexed servicing scheme for the timers.  
9.2.6 Timer Interrupts  
All timers can generate internal interrupt requests. Although all three timers share a single inter-  
rupt request to the CPU, each has its own vector location and internal priority. Timer 0 has the  
highest interrupt priority and Timer 2 has the lowest.  
Timer Interrupts are enabled or disabled by the Interrupt (INT) bit in the Timer Control register.  
If enabled, an interrupt is generated every time a maximum count value is reached. In dual max-  
imum count mode, an interrupt is generated each time the value in Maxcount Compare A or Max-  
count Compare B is reached. If the interrupt is disabled after a request has been generated, but  
before a pending interrupt is serviced, the interrupt request remains active (the Interrupt Control-  
ler latches the request). If a timer generates a second interrupt request before the CPU services  
the first interrupt request, the first request is lost.  
9.2.7 Programming Considerations  
Timer registers can be read or written whether the timer is operating or not. Since processor ac-  
cesses to timer registers are synchronized with counter element accesses, a half-modified count  
register will never be read.  
When Timer 0 and Timer 1 use an internal clock source, the input pin must be high to enable  
counting.  
9.3 TIMING  
Certain timing considerations need to be made with the Timer/Counter Unit. These include input  
setup and hold times, synchronization and operating frequency.  
9.3.1 Input Setup and Hold Timings  
To ensure recognition, setup and hold times must be met with respect to CPU clock edges. The  
timer input signal must be valid TCHIS before the rising edge of CLKOUT and must remain valid  
TCHIH after the same rising edge. If these timing requirements are not met, the input will not be  
recognized until the next clock edge.  
9-16  
TIMER/COUNTER UNIT  
9.3.2 Synchronization and Maximum Frequency  
All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic  
required to synchronize the external signals, and the multiplexing of the counter element, the  
Timer/Counter Unit can operate only up to ¼ of the CLKOUT frequency. Clocking at greater fre-  
quencies will result in missed clocks.  
9.3.2.1  
Timer/Counter Unit Application Examples  
The following examples are possible applications of the Timer/Counter Unit. They include a real-  
time clock, a square wave generator and a digital one-shot.  
9.3.3 Real-Time Clock  
Example 9-1 contains sample code to configure Timer 2 to generate an interrupt request every 10  
milliseconds. The CPU then increments memory-based clock variables.  
9.3.4 Square-Wave Generator  
A square-wave generator can be useful to act as a system clock tick. Example 9-2 illustrates how  
to configure Timer 1 to operate this way.  
9.3.5 Digital One-Shot  
Example 9-3 configures Timer 1 to act as a digital one-shot.  
9-17  
 
TIMER/COUNTER UNIT  
$mod186  
name example_80186_family_timer_code  
;FUNCTION: This function sets up the timer and interrupt controller  
;
to cause the timer to generate an interrupt every  
10 milliseconds and to service interrupts to  
implement a real time clock.  
;
;
;
;
Timer 2 is used in this example because no input or  
output signals are required.  
;
;
;SYNTAX:  
extern void far set_time(hour, minute, second, T2Compare)  
;
;INPUTS:  
hour - hour to set time to.  
;
minute - minute to set time to.  
second - second to set time to.  
T2Compare - T2CMPA value (see note below)  
;
;
;
;OUTPUTS:  
None  
;NOTE:  
Parameters are passed on the stack as required by  
high-level languages  
;
;
;
;
;
;
;
;
;
;
;
For a CLKOUT of 16Mhz,  
f(timer2)  
= 16Mhz/4  
= 4Mhz  
= 0.25us for T2CMPA = 1  
T2CMPA(10ms)  
= 10ms/0.25us  
= 10e-3/0.25e-6  
= 40000  
;substitute register offsets  
T2CON equ xxxxh  
T2CMPA equ xxxxh  
T2CNT equ xxxxh  
TCUCON equ xxxxh  
;Timer 2 Control register  
;Timer 2 Compare register  
;Timer 2 Counter register  
;Int. Control register  
;End Of Interrupt register  
;Interrupt Status register  
;timer 2:vector type 19  
EOI  
equ xxxxh  
INTSTS equ xxxxh  
timer_2_int equ 19  
data segment public ’data’  
public _hour, _minute, _second, _msec  
_hour  
db ?  
db ?  
db ?  
db ?  
_minute  
_second  
_msec  
data ends  
Example 9-1. Configuring a Real-Time Clock  
9-18  
 
TIMER/COUNTER UNIT  
lib_80186 segment public ’code’  
assume cs:lib_80186, ds:data  
public _set_time  
_set_time proc far  
push  
mov  
bp  
bp, sp  
;save caller’s bp  
;get current top of stack  
hour  
equ word ptr[bp+6]  
;get parameters off stack  
minute equ word ptr[bp+8]  
second equ word ptr[bp+10]  
T2Compare equ word ptr[bp+12]  
push  
push  
push  
ax  
dx  
si  
;save registers used  
;set interrupt vector  
push  
xor  
mov  
mov  
mov  
ds  
ax, ax  
ds, ax  
si, 4*timer_2_int  
word ptr ds:[si], offset  
timer_2_interrupt_routine  
inc  
inc  
mov  
pop  
si  
si  
ds:[si], cs  
ds  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
ax, hour  
;set time  
_hour, al  
ax, minute  
_minute, al  
ax, second  
_second, al  
_msec, 0  
mov  
xor  
out  
dx, T2CNT  
ax, ax  
dx, al  
;clear Count register  
mov  
mov  
out  
mov  
mov  
out  
dx, T2CMPA  
ax, T2Compare  
dx, al  
dx, T2CON  
ax, 0E001H  
dx, al  
;set maximum count value  
;see note in header above  
;set up the control word:  
;enable counting,  
;generate interrupt on MC,  
;continuous counting  
mov  
xor  
out  
dx, TCUCON  
ax, ax  
dx, al  
;set up interrupt controller  
;unmask highest priority interrupt  
Example 9-1. Configuring a Real-Time Clock (Continued)  
9-19  
TIMER/COUNTER UNIT  
sti  
;enable interrupts  
pop  
pop  
pop  
pop  
ret  
si  
dx  
ax  
bp  
;restore saved registers  
;restore caller’s bp  
_set_time endp  
timer_2_interrupt_routine proc far  
push  
push  
cmp  
ax  
;save registers used  
dx  
_msec, 99  
bump_second  
_msec  
;has 1 sec passed?  
;if above or equal...  
jae  
inc  
jmp  
short reset_int_ctl  
bump_second:  
mov  
cmp  
jae  
inc  
jmp  
_msec, 0  
;reset millisecond  
;has 1 minute passed?  
_minute, 59  
bump_minute  
_second  
short reset_int_ctl  
bump_minute:  
mov  
cmp  
jae  
inc  
jmp  
_second, 0  
;reset second  
;has 1 hour passed?  
_minute, 59  
bump_hour  
_minute  
short reset_int_ctl  
bump_hour:  
mov  
_minute, 0  
_hour, 12  
reset_hour  
_hour  
;reset minute  
;have 12 hours passed?  
cmp  
jae  
inc  
jmp  
reset_int_ctl  
reset_hour:  
mov  
_hour, 1  
;reset hour  
reset_int_ctl:  
mov  
mov  
out  
pop  
pop  
iret  
dx, EOI  
ax, 8000h  
dx, al  
dx  
;non-specific end of interrupt  
ax  
timer_2_interrupt_routine endp  
lib_80186  
ends  
end  
Example 9-1. Configuring a Real-Time Clock (Continued)  
9-20  
TIMER/COUNTER UNIT  
$mod186  
name  
example_timer1_square_wave_code  
;FUNCTION: This function generates a square wave of given  
;
;
frequency and duty cycle on Timer 1 output pin.  
; SYNTAX: extern void far clock(int mark, int space)  
;
; INPUTS: mark - This is the mark (1) time.  
;
;
;
;
;
;
;
space - This is the space (0) time.  
The register compare value for a given time can be  
easily calculated from the formula below.  
CompareValue = (req_pulse_width*f)/4  
; OUTPUTS: None  
;
;
;
NOTE: Parameters are passed on the stack as required by  
high-level Languages  
T1CMPA equ xxxxH  
;substitute register offsets  
T1CMPB equ xxxxH  
T1CNT equ xxxxH  
T1CON equ xxxxH  
lib_80186  
segment public ’code’  
assume cs:lib_80186  
public  
_clock  
_clock  
proc far  
push  
mov  
bp  
;save caller’s bp  
;get current top of stack  
;get parameters off the stack  
bp, sp  
_space equ word ptr[bp+6]  
_mark equ word ptr[bp+8]  
push  
push  
push  
ax  
bx  
dx  
;save registers that will be  
;modified  
mov  
mov  
out  
dx, T1CMPA  
ax, _mark  
dx, al  
;set mark time  
mov  
mov  
out  
dx, T1CMPB  
ax, _space  
dx, al  
;set space time  
;Clear Timer 1 Counter  
;start Timer 1  
mov  
xor  
out  
dx, T1CNT  
ax, ax  
dx, al  
mov  
mov  
out  
dx, T1CON  
ax, C003H  
dx, al  
Example 9-2. Configuring a Square-Wave Generator  
9-21  
 
TIMER/COUNTER UNIT  
pop  
pop  
pop  
dx  
bx  
ax  
;restore saved registers  
;restore caller’s bp  
pop  
ret  
bp  
_clock  
endp  
ends  
lib_80186  
end  
Example 9-2. Configuring a Square-Wave Generator (Continued)  
$mod186  
name example_timer1_1_shot_code  
; FUNCTION: This function generates an active-low one-shot pulse  
;
on Timer 1 output pin.  
;
; SYNTAX:  
extern void far one_shot(int CMPB);  
;
; INPUTS:  
CMPB - This is the T1CMPB value required to generate a  
pulse of a given pulse width. This value is calculated  
from the formula below.  
;
;
;
;
;
CMPB = (req_pulse_width*f)/4  
; OUTPUTS: None  
;
; NOTE:  
;
Parameters are passed on the stack as required by  
high-level languages  
T1CNT equ xxxxH  
;substitute register offsets  
T1CMPA equ xxxxH  
T1CMPB equ xxxxH  
T1CON equ xxxxH  
MaxCount equ 0020H  
lib_80186  
segment public ’code’  
assume cs:lib_80186  
public  
_one_shot  
_one_shot  
proc far  
push  
mov  
bp  
bp, sp  
;save caller’s bp  
;get current top of stack  
Example 9-3. Configuring a Digital One-Shot  
9-22  
 
TIMER/COUNTER UNIT  
_CMPB equ word ptr[bp+6]  
;get parameter off the stack  
push  
push  
mov  
xor  
out  
mov  
mov  
out  
mov  
mov  
out  
mov  
mov  
out  
ax  
;save registers that will be  
;modified  
dx  
dx, T1CNT  
ax, ax  
dx, al  
dx, T1CMPA  
ax, 1  
dx, al  
dx, T1CMPB  
ax, _CMPB  
dx, al  
dx, T1CON  
ax, C002H  
dx, al  
;Clear Timer 1 Counter  
;set time before t_shot to 0  
;set pulse time  
;start Timer 1  
CountDown: in ax, dx  
;read in T1CON  
test  
jz  
ax, MaxCount  
CountDown  
;max count occurred?  
;no: then wait  
and  
out  
ax, not MaxCount  
dx, al  
;clear max count bit  
;update T1CON  
pop  
pop  
dx  
ax  
bp  
;restore saved registers  
;restore caller’s bp  
pop  
ret  
_one_shot  
lib_80186  
end  
endp  
ends  
Example 9-3. Configuring a Digital One-Shot (Continued)  
9-23  
10  
Direct Memory  
Access Unit  
CHAPTER 10  
DIRECT MEMORY ACCESS UNIT  
In many applications, large blocks of data must be transferred between memory and I/O space. A  
disk drive, for example, usually reads and writes data in blocks that may be thousands of bytes  
long. If the CPU were required to handle each byte of the transfer, the main tasks would suffer a  
severe performance penalty. Even if the data transfers were interrupt driven, the overhead for  
transferring control to the interrupt handler would still decrease system throughput.  
Direct Memory Access, or DMA, allows data to be transferred between memory and peripherals  
without the intervention of the CPU. Systems that use DMA have a special device, known as  
the DMA controller, that takes control of the system bus and performs the transfer between mem-  
ory and the peripheral device. When the DMA controller receives a request for a transfer from a  
peripheral, it signals the CPU that it needs control of the system bus. The CPU then releases con-  
trol of the bus and the DMA controller performs the transfer. In many cases, the CPU releases the  
bus and continues to execute instructions from the prefetch queue. If the DMA transfers are rel-  
atively infrequent, there is no degradation of software performance; the DMA transfer is trans-  
parent to the CPU.  
The DMA Unit has two channels. Each channel can accept DMA requests from one of three  
sources: an external request pin, the Timer/Counter Unit or direct programming. Data can be  
transferred between any combination of memory and I/O space. The DMA Unit can access the  
entire memory and I/O space in either byte or word increments.  
10.1 FUNCTIONAL OVERVIEW  
The DMA Unit consists of two channels that are functionally identical. The following discussion  
is hierarchical, beginning with an overview of a single channel and ending with a description of  
the two-channel unit.  
10.1.1 The DMA Transfer  
A DMA transfer begins with a request. The requesting device may either have data to transmit (a  
source request) or it may require data (a destination request). Alternatively, transfers may be ini-  
tiated by the system software without an external request.  
10-1  
DIRECT MEMORY ACCESS UNIT  
When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMA  
transfer, while the DMA channel provides the address information for the source and destination  
devices. The DMA Unit does not provide a discrete DMA acknowledge signal, unlike other DMA  
controller chips (an acknowledge can be synthesized, however). The DMA channel continues  
transferring data as long as the request is active and it has not exceeded its programmed transfer  
limit.  
Every DMA transfer consists of two distinct bus cycles: a fetch and a deposit (see Figure 10-1 on  
page 10-2). During the fetch cycle, the byte or word is read from the data source and placed in an  
internal temporary storage register. The data in the temporary storage register is written to the  
destination during the deposit cycle. The two bus cycles are indivisible; they cannot be separated  
by a bus hold request, a refresh request or another DMA request.  
Deposit  
Fetch  
TI  
T1  
T2  
T3  
T4  
T1  
T2  
T3  
T4  
CLKOUT  
ALE  
AD15:0  
Source  
Address  
Source  
Data  
Destination Destination  
Address Data  
RD  
WR  
A1186-0A  
Figure 10-1. Typical DMA Transfer  
10-2  
 
DIRECT MEMORY ACCESS UNIT  
10.1.1.1  
DMA Transfer Directions  
The source and destination addresses for a DMA transfer are programmable and can be in either  
memory or I/O space. DMA transfers can be programmed for any of the following four direc-  
tions:  
from memory space to I/O space  
from I/O space to memory space  
from memory space to memory space  
from I/O space to I/O space  
DMA transfers can access the Peripheral Control Block.  
10.1.1.2  
Byte and Word Transfers  
DMA transfers can be programmed to handle either byte or word transfers. The handling of byte  
and word data is the same as that for normal bus cycles and is dependent upon the processor bus  
width. For example, odd-aligned word DMA transfers on a processor with a 16-bit bus requires  
two fetches and two deposits (all back-to-back). BIU bus cycles are covered in Chapter 3, “Bus  
Interface Unit.” Word transfers are illegal on the 8-bit bus device.  
10.1.2 Source and Destination Pointers  
Each DMA channel maintains a twenty-bit pointer for the source of data and a twenty-bit pointer  
for the destination of data. The twenty-bit pointers allow access to the full 1 Mbyte of memory  
space. The DMA Unit views memory as a linear (unsegmented) array.  
With a twenty-bit pointer, it is possible to create an I/O address that is above the CPU limit of 64  
Kbytes. The DMA Unit will run I/O DMA cycles above 64K, even though these addresses are  
not accessible through CPU instructions (e.g., IN and OUT). Some applications may wish to  
make use of this by swapping pages of data from I/O space above 64K to standard CPU memory.  
The source and destination pointers can be individually programmed to increment, decrement or  
remain constant after each transfer. The programmed data width (byte or word) determines the  
amount that a pointer is incremented or decremented. Word transfers change the pointer by two;  
byte transfers change the pointer by one.  
10.1.3 DMA Requests  
There are three distinct sources of DMA requests: the external DRQ pin, the internal DMA re-  
quest line and the system software. In all three cases, the system software must arm a DMA chan-  
nel before it recognizes DMA requests. (See “Arming the DMA Channel” on page 10-18.)  
10-3  
DIRECT MEMORY ACCESS UNIT  
10.1.4 External Requests  
External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling  
edge of CLKOUT. It takes a minimum of four clocks before the DMA cycle is initiated by the  
BIU (see Figure 10-2). The DMA request is cleared four clocks before the end of the DMA cycle  
(effectively re-arming the DRQ input).  
T1  
T1 or  
TW or  
TI  
T2 or  
TW or  
TI  
T3 or  
TW or  
TI  
of  
DMA  
Cycle  
T4 or  
TI  
4
DRQ  
1
2
3
NOTES:  
1. T  
: DMA request to clock low.  
INVCL  
2. Synchronizer resolution time.  
3. DMA unit priority arbitration and overhead.  
4. Bus interface unit latches DMA request and decides to run DMA cycle.  
A1528-0A  
Figure 10-2. DMA Request Minimum Response Time  
External requests (and the resulting DMA transfer) are classified as either source-synchronized  
or destination-synchronized. A source-synchronized request originates from the peripheral that is  
sending data. For example, a disk controller in the process of reading data from a disk would use  
a source-synchronized request (data would be moving from the disk to memory). A destination-  
synchronized request originates from the peripheral that is receiving data. If a disk controller  
were writing data to a disk, it would use a destination-synchronized request (data would be mov-  
ing from memory to the disk). The type of synchronization a channel uses is programmable. (See  
“Selecting Channel Synchronization” on page 10-18.)  
10-4  
 
DIRECT MEMORY ACCESS UNIT  
10.1.4.1  
Source Synchronization  
A typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals  
deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas-  
serted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase)  
to prevent another DMA cycle from occurring. A source-synchronized transfer provides the  
source device at least three clock cycles from the time it is accessed (acknowledged) to deassert  
its request line if further transfers are not required.  
Deposit Cycle  
T2 T3 T4  
Fetch Cycle  
T2 T3  
T1  
T4  
T1  
1
CLKOUT  
DRQ (Case 1)  
2
DRQ (Case 2)  
NOTES:  
1. Current source synchronized transfer will not be immediately  
followed by another DMA transfer.  
2. Current source synchronized transfer will be immediately  
followed by another DMA transfer.  
A1188-0A  
Figure 10-3. Source-Synchronized Transfers  
10.1.4.2  
Destination Synchronization  
A destination-synchronized transfer differs from a source-synchronized transfer by the addition  
of two idle states at the end of the deposit cycle (Figure 10-4). The two idle states extend the DMA  
cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the  
cycle. If the two idle states were not inserted, the destination device would not be able to deassert  
its request in time to prevent another DMA cycle from occurring.  
The insertion of two idle states at the end of a destination synchronization transfer has an impor-  
tant side effect. A destination-synchronized DMA channel gives up the bus during the idle  
states, allowing any other bus master to gain ownership. This includes the CPU, the Refresh  
Control Unit, an external bus master or another DMA channel.  
10-5  
 
DIRECT MEMORY ACCESS UNIT  
Deposit Cycle  
Fetch Cycle  
T2 T3  
T1  
T4  
T1  
T2  
T3  
T4  
TI  
TI  
CLKOUT  
DRQ  
(Case 1)  
1
DRQ  
(Case 2)  
2
NOTES:  
1. Current destination synchronized transfer will not be immediately  
followed by another DMA transfer.  
2. Current destination synchronized transfer will be immediately  
followed by another DMA transfer.  
A1189-0A  
Figure 10-4. Destination-Synchronized Transfers  
10.1.5 Internal Requests  
Internal DMA requests can come from either Timer 2 or the system software.  
10.1.5.1 Timer 2-Initiated Transfers  
When programmed for Timer 2-initiated transfers, the DMA channel performs one DMA transfer  
every time that Timer 2 reaches its maximum count. Timer-initiated transfers are useful for ser-  
vicing time-based peripherals. For example, an A/D converter would require data every 22 mi-  
croseconds in order to produce an audio range waveform. In this case, the DMA source would  
point to the waveform data, the destination would point to the A/D converter and Timer 2 would  
request a transfer every 22 microseconds. (See “Timed DMA Transfers” on page 10-26.)  
10.1.5.2  
Unsynchronized Transfers  
DMA transfers can be initiated directly by the system software by selecting unsynchronized  
transfers. Unsynchronized transfers continue, back-to-back, at the full bus bandwidth, until the  
channel’s transfer count reaches zero or DMA transfers are suspended by an NMI.  
10-6  
 
DIRECT MEMORY ACCESS UNIT  
10.1.6 DMA Transfer Counts  
Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total  
number of transfers the channel runs. The transfer count is decremented by one after each transfer  
(regardless of data size). The DMA channel can be programmed to terminate transfers when the  
transfer count reaches zero (also referred to as terminal count).  
10.1.7 Termination and Suspension of DMA Transfers  
When DMA transfers for a channel are terminated, no further DMA requests for that channel will  
be granted until the channel is re-started by direct programming. A suspended DMA transfer tem-  
porarily disables transfers in order to perform a specific task. A suspended DMA channel does  
not need to be re-started by direct programming.  
10.1.7.1  
Termination at Terminal Count  
When programmed to terminate on terminal count, the DMA channel disarms itself when the  
transfer count value reaches zero. No further DMA transfers take place on the channel until it is  
re-armed by direct programming. Unsynchronized transfers always terminate when the transfer  
count reaches zero, regardless of programming.  
10.1.7.2  
Software Termination  
A DMA channel can be disarmed by direct programming. Any DMA transfer that is in progress  
will complete, but no further transfers are run until the channel is re-armed.  
10.1.7.3  
Suspension of DMA During NMI  
DMA transfers are inhibited during the service of Non-Maskable Interrupts (NMI). DMA activity  
is halted in order to give the CPU full command of the system bus during the NMI service. Exit  
from the NMI via an IRET instruction re-enables the DMA Unit. DMA transfers can be enabled  
during an NMI service routine by the system software.  
10.1.7.4  
Software Suspension  
DMA transfers can be temporarily suspended by direct programming. In time-critical sections of  
code, such as interrupt handlers, it may be necessary to shut off DMA activity temporarily in or-  
der to give the CPU total control of the bus.  
10-7  
DIRECT MEMORY ACCESS UNIT  
10.1.8 DMA Unit Interrupts  
Each DMA channel can be programmed to generate an interrupt request when its transfer count  
reaches zero.  
10.1.9 DMA Cycles and the BIU  
The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a  
pending request, it signals the BIU. If the BIU has no other higher-priority request pending, it runs  
the DMA cycle. (BIU priority is described in Chapter 3, “Bus Interface Unit.”) The BIU signals  
that it is running a bus cycle initiated by a master other than the CPU by driving the S6 status bit  
high.  
The Chip-Select Unit monitors the BIU addresses to determine which chip-select, if any, to acti-  
vate. Because the DMA Unit uses the BIU, chip-selects are active for DMA cycles. If a DMA  
channel accesses a region of memory or I/O space within a chip-select’s programmed range, then  
that chip-select is asserted during the cycle. The Chip-Select Unit will not recognize DMA cycles  
that access I/O space above 64K.  
10.1.10 The Two-Channel DMA Unit  
Two DMA channels are combined with arbitration logic to form the DMA Unit (see Figure 10-5).  
10.1.10.1 DMA Channel Arbitration  
Within the two-channel DMA Unit, the arbitration logic decides which channel takes precedence  
when both channels simultaneously request transfers. Each channel can be set to either low pri-  
ority or high priority. If the two channels are set to the same priority (either both high or both  
low), then the channels rotate priority.  
10.1.10.1.1 Fixed Priority  
Fixed priority results when one channel in a module is programmed to high priority and the other  
is set to low priority. If both DMA requests occur simultaneously, the high priority channel per-  
forms its transfer (or transfers) first. The high priority channel continues to perform transfers as  
long as the following conditions are met:  
the channel’s DMA request is still active  
the channel has not terminated or suspended transfers (through programming or interrupts)  
the channel has not released the bus (through the insertion of idle states for destination-  
synchronized transfers)  
10-8  
DIRECT MEMORY ACCESS UNIT  
The last point is extremely important when the two channels use different synchronization. For  
example, consider the case in which channel 1 is programmed for high priority and destination  
synchronization and channel 0 is programmed for low priority and source synchronization. If a  
DMA request occurs for both channels simultaneously, channel 1 performs the first transfer. At  
the end of channel 1’s deposit cycle, two idle states are inserted (thus releasing the bus). With the  
bus released, channel 0 is free to perform its transfer even though the higher-priority channel  
has not completed all of its transfers. Channel 1 regains the bus at the end of channel 0’s trans-  
fer. The transfers will alternate as long as both requests remain active.  
Module  
Timer 2  
DMA Request  
Internal - DMA  
Request  
Multiplexer  
Inter-module  
Arbitration  
Logic  
Timer 2  
Request  
Timer 2 Request  
Source Pointer  
Source Pointer  
Destination Pointer  
Destination Pointer  
Channel 0  
Channel 1  
Control Logic  
Control Logic  
DRQ Pin  
DRQ Pin  
A1540-01  
Figure 10-5. Two-Channel DMA Module  
A higher-priority DMA channel will interrupt the transfers of a lower-priority channel. Figure  
10-6 shows several transfers with different combinations of channel priority and synchronization.  
10-9  
 
DIRECT MEMORY ACCESS UNIT  
Both Requests Asserted  
Channel  
Priority  
Synch  
0
1
Etc.  
Low Low  
SRC SRC  
Channel 1 Channel 0 Channel 1 Channel 0  
Channel  
Priority High Low  
Synch  
0
1
Etc.  
Etc.  
Channel 0 Channel 0  
Channel 1 Channel 1  
SRC SRC  
Channel 0 Completes  
All Transfers  
Channel  
Priority High Low  
Synch Dest SRC  
0
1
Channel 0  
Channel 1 Channel 0  
Channel 1  
Destination Synch Releases Bus  
A1190-0A  
Figure 10-6. Examples of DMA Priority  
10.1.10.1.2 Rotating Priority  
Channel priority rotates when the channels are programmed as both high or both low priority. The  
highest priority is initially assigned to channel 1 of the module. After a channel performs a trans-  
fer, it is assigned the lower priority. When requests are active for both channels, the transfers al-  
ternate between the two. Channel 1 is reassigned high priority whenever the bus is released (that  
is, at the end of a destination-synchronized transfer or when DMA requests are no longer active).  
10.2 PROGRAMMING THE DMA UNIT  
A total of six Peripheral Control Block registers configure each DMA channel.  
10.2.1 DMA Channel Parameters  
The first step in programming the DMA Unit is to set up the parameters for each channel.  
10.2.1.1  
Programming the Source and Destination Pointers  
The following parameters are programmable for the source and destination pointers:  
pointer address  
address space (memory or I/O)  
automatic pointer indexing (increment, decrement or no change) after transfer  
10-10  
 
DIRECT MEMORY ACCESS UNIT  
Two 16-bit Peripheral Control Block registers define each of the 20-bit pointers. Figures 10.7 and  
10.8 show the layout of the DMA Source Pointer address registers, and Figures 10.9 and 10.10  
show the layout of the DMA Destination Pointer address registers. The DSA19:16 and  
DDA19:16 (high-order address bits) are driven on the bus even if I/O transfers have been pro-  
grammed. When performing I/O transfers within the normal 64K I/O space only, the high-order  
bits in the pointer registers must be cleared.  
Register Name:  
DMA Source Address Pointer (High)  
DxSRCH  
Register Mnemonic:  
Register Function:  
Contains the upper 4 bits of the DMA Source pointer.  
15  
0
D
S
A
1
D
S
A
1
D
S
A
1
D
S
A
1
9
8
7
6
A1185-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
DSA19:16  
DMA  
Source  
Address  
XXXXH  
DSA19:16 are driven on A19:16 during the  
fetch phase of a DMA transfer.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 10-7. DMA Source Pointer (High-Order Bits)  
10-11  
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Source Address Pointer (Low)  
DxSRCL  
Register Mnemonic:  
Register Function:  
Contains the lower 16 bits of the DMA Source pointer.  
15  
0
D
S
A
1
D
S
A
1
D
S
A
1
D
S
A
1
D
S
A
1
D
S
A
1
D
S
A
9
D
S
A
8
D
S
A
7
D
S
A
6
D
S
A
5
D
S
A
4
D
S
A
3
D
S
A
2
D
S
A
1
D
S
A
0
5
4
3
2
1
0
A1177-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
DMA  
Source  
Address  
Function  
DSA15:0  
XXXXH  
DSA15:0 are driven on the lower 16 bits of the  
address bus during the fetch phase of a DMA  
transfer.  
Figure 10-8. DMA Source Pointer (Low-Order Bits)  
The address space referenced by the source and destination pointers is programmed in the DMA  
Control Register for the channel (see Figure 10-11 on page 10-15). The SMEM and DMEM bits  
control the address space (memory or I/O) for source pointer and destination pointer, respective-  
ly.  
Automatic pointer indexing is also controlled by the DMA Control Register. Each pointer has two  
bits, increment and decrement, that control the indexing. If the increment and decrement bits for  
a pointer are programmed to the same value, then the pointer remains constant. The programmed  
data width (byte or word) for the channel automatically controls the amount that a pointer is in-  
cremented or decremented.  
10-12  
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Destination Address Pointer (High)  
Register Mnemonic:  
Register Function:  
DxDSTH  
Contains the upper 4 bits of the DMA  
Destination pointer.  
15  
0
D
D
A
1
D
D
A
1
D
D
A
1
D
D
A
1
9
8
7
6
A1178-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
DDA19:16  
DMA  
Destination  
Address  
XXXXH  
DDA19:16 are driven on A19:16 during the  
deposit phase of a DMA transfer.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written  
to a logic zero to ensure compatibility with future Intel products.  
Figure 10-9. DMA Destination Pointer (High-Order Bits)  
10-13  
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Destination Address Pointer (Low)  
DxDSTL  
Register Mnemonic:  
Register Function:  
Contains the lower 16 bits of the DMA Destination  
pointer.  
15  
0
D
D
A
1
D
D
A
1
D
D
A
1
D
D
A
1
D
D
A
1
D
D
A
1
D
D
A
9
D
D
A
8
D
D
A
7
D
D
A
6
D
D
A
5
D
D
A
4
D
D
A
3
D
D
A
2
D
D
A
1
D
D
A
0
5
4
3
2
1
0
A1179-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
DMA  
Destination  
Address  
Function  
DDA15:0  
XXXXH  
DDA15:0 are driven on the lower 16 bits of the  
address bus during the deposit phase of a DMA  
transfer.  
Figure 10-10. DMA Destination Pointer (Low-Order Bits)  
Selecting Byte or Word Size Transfers  
10.2.1.2  
The WORD bit in the DMA Control Register (Figure 10-11) controls the data size for a channel.  
When WORD is set, the channel transfers data in 16-bit words. Byte transfers are selected by  
clearing the WORD bit. The data size for a channel also affects pointer indexing. Word transfers  
modify (increment or decrement) the pointer registers by two for each transfer, while byte trans-  
fers modify the pointer registers by one.  
10-14  
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Control Register  
DxCON  
Register Mnemonic:  
Register Function:  
Controls DMA channel parameters.  
15  
0
D
M
E
D
D
E
C
D
I
N
C
S
M
E
S
D
E
C
S
I
N
C
T
C
I
N
T
S
Y
N
1
S
Y
N
0
P
I
C
H
G
S
T
R
T
W
D
R
Q
O
R
D
M
M
A1180-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
DMEM  
Destination  
Address  
Space  
X
Selects memory or I/O space for the destination  
pointer. Set DMEM to select memory space; clear  
DMEM to select I/O space.  
Select  
DDEC  
DINC  
Destination  
Decrement  
X
X
X
Set DDEC to automatically decrement the destination  
pointer after each transfer. (See Note.)  
Destination  
Increment  
Set DINC to automatically increment the destination  
pointer after each transfer. (See Note.)  
SMEM  
Source  
Address  
Space  
Select  
Selects memory or I/O space for the source pointer.  
Set SMEM to select memory space; clear SMEM to  
select I/O space.  
SDEC  
SINC  
Source  
Decrement  
X
X
Set SDEC to automatically decrement the source  
pointer after each transfer. (See Note.)  
Source  
Increment  
Set SINC to automatically increment the source  
pointer after each transfer. (See Note.)  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products. A pointer remains constant if  
its increment and decrement bits are equal.  
Figure 10-11. DMA Control Register  
10-15  
 
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Control Register  
DxCON  
Register Mnemonic:  
Register Function:  
Controls DMA channel parameters.  
15  
0
D
M
E
D
D
E
C
D
I
N
C
S
M
E
S
D
E
C
S
I
N
C
T
C
I
N
T
S
Y
N
1
S
Y
N
0
P
I
C
H
G
S
T
R
T
W
D
R
Q
O
R
D
M
M
A1180-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
TC  
Terminal  
Count  
X
Set TC to terminate transfers on Terminal Count. This bit  
is ignored for unsynchronized transfers (that is, the DMA  
channel behaves as if TC is set, regardless of its  
condition).  
INT  
Interrupt  
X
Set INT to generate an interrupt request on Terminal  
Count. The TC bit must be set to generate an interrupt.  
SYN1:0  
Synchron-  
XX  
Selects channel synchronization:  
ization Type  
SYN1 SYN0  
Synchronization Type  
Unsynchronized  
0
0
1
1
0
1
0
1
Source-synchronized  
Destination-synchronized  
Reserved (do not use)  
P
Relative  
Priority  
X
X
Set P to select high priority for the channel; clear P to  
select low priority for the channel.  
IDRQ  
Internal  
DMA  
Request  
Select  
Set IDRQ to select internal DMA requests and ignore  
the external DRQ pin. Clear IDRQ to select the DRQ pin  
as the source of DMA requests. When IDRQ is set, the  
channel must be configured for source-synchronized  
transfers (SYN1:0 = 01).  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 10-11. DMA Control Register (Continued)  
10-16  
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Control Register  
Register Mnemonic:  
Register Function:  
DxCON  
Controls DMA channel parameters.  
15  
0
D
M
E
D
D
E
C
D
I
N
C
S
M
E
S
D
E
C
S
I
N
C
T
C
I
N
T
S
Y
N
1
S
Y
N
0
P
I
C
H
G
S
T
R
T
W
D
R
Q
O
R
D
M
M
A1180-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
CHG  
Change  
Start Bit  
X
Set CHG to enable modifying the STRT bit.  
STRT  
Start DMA  
Channel  
0
Set STRT to arm the DMA channel. The STRT bit can  
be modified only when the CHG bit is set.  
WORD  
Word  
Transfer  
Select  
X
Set WORD to select word transfers; clear WORD to  
select byte transfers. The 8-bit bus versions of the  
device ignore the WORD bit.  
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a  
logic zero to ensure compatibility with future Intel products.  
Figure 10-11. DMA Control Register (Continued)  
10.2.1.3  
Selecting the Source of DMA Requests  
DMA requests can come from either an internal source (Timer 2) or an external source.  
Internal DMA requests are selected by setting the IDRQ bit in the DMA Control Register (see  
Figure 10-11 on page 10-15) for the channel. The DMA channel ignores its DRQ pin when inter-  
nal requests are programmed. Similarly, the DMA channel responds only to the DRQ pin (and  
ignores internal requests) when external requests are selected.  
10-17  
DIRECT MEMORY ACCESS UNIT  
10.2.1.4  
Arming the DMA Channel  
Each DMA channel must be armed before it can recognize DMA requests. A channel is armed  
by setting its STRT (Start) bit in the DMA Control Register (Figure 10-11 on page 10-15). The  
STRT bit can be modified only if the CHG (Change Start) bit is set at the same time. The CHG  
bit is a safeguard to prevent accidentally arming a DMA channel while modifying other channel  
parameters.  
A DMA channel is disarmed by clearing its STRT bit. The STRT bit is cleared either directly by  
software or by the channel itself when it is programmed to terminate on terminal count.  
10.2.1.5  
Selecting Channel Synchronization  
The synchronization method for a channel is controlled by the SYN1:0 bits in the DMA Control  
Register (Figure 10-11 on page 10-15).  
NOTE  
The combination SYN1:0=11 is reserved and will result in unpredictable  
operation. When IDRQ is set (internal requests selected) the channel must  
always be programmed for source-synchronized transfers (SYN1:0=01).  
When programmed for unsynchronized transfers (SYN1:0=00), the DMA channel will begin to  
transfer data as soon as the STRT bit is set.  
10.2.1.6  
Programming the Transfer Count Options  
The Transfer Count Register (Figure 10-12) and the TC bit in the DMA Control Register (Figure  
10-11 on page 10-15) are used to stop DMA transfers for a channel after a specified number of  
transfers have occurred.  
The transfer count (the number of transfers desired) is written to the DMA Transfer Count Reg-  
ister. The Transfer Count Register is 16 bits wide, limiting the total number of transfers for a  
channel to 65,536 (without reprogramming). The Transfer Count Register is decremented by one  
after each transfer (for both byte and word transfers).  
10-18  
   
DIRECT MEMORY ACCESS UNIT  
Register Name:  
DMA Transfer Count  
DxTC  
Register Mnemonic:  
Register Function:  
Contains the DMA channel’s transfer count.  
15  
0
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
1
T
C
9
T
C
8
T
C
7
T
C
6
T
C
5
T
C
4
T
C
3
T
C
2
T
C
1
T
C
0
5
4
3
2
1
0
A1172-0A  
Bit  
Mnemonic  
Reset  
State  
Bit Name  
Function  
TC15:0  
Transfer  
Count  
XXXXH  
Contains the transfer count for a DMA channel.  
This value is decremented by one after each  
transfer.  
Figure 10-12. Transfer Count Register  
The TC bit, when set, instructs the DMA channel to disarm itself (by clearing the STRT bit) when  
the transfer count reaches zero. If the TC bit is cleared, the channel continues to perform transfers  
regardless of the state of the Transfer Count Register. Unsynchronized (software-initiated) trans-  
fers always terminate when the transfer count reaches zero; the TC bit is ignored.  
10.2.1.7  
Generating Interrupts on Terminal Count  
A channel can be programmed to generate an interrupt request whenever the transfer count reach-  
es zero. Both the TC bit and the INT bit in the DMA Control Register (Figure 10-11 on page  
10-15) must be set to generate an interrupt request.  
10.2.1.8  
Setting the Relative Priority of a Channel  
The priority of a channel is controlled by the Priority bit in the DMA Control Register (Figure  
10-11 on page 10-15). A channel may be assigned either high or low priority. If both channels are  
programmed to the same priority (i.e., both high or both low), the channels rotate priority.  
10-19  
 
DIRECT MEMORY ACCESS UNIT  
10.2.2 Suspension of DMA Transfers  
Whenever the CPU receives an NMI, all DMA activity is suspended at the end of the current  
transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Regis-  
ter (Figure 8-14 on page 8-23). When an IRET instruction is executed, the CPU clears the DHLT  
bit and DMA transfers are allowed to resume. Software can read and write the DHLT bit.  
NOTE  
Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.  
A conflict with the internal use of the register may cause incorrect processing  
of timer interrupts.  
The DHLT bit does not function when the interrupt controller is in slave mode.  
10.2.3 Initializing the DMA Unit  
Use the following sequence when programming the DMA Unit:  
1. Program the source and destination pointers for all used channels.  
2. Program the DMA Control Registers in order of highest-priority channel to lowest-  
priority channel.  
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT  
This section covers hardware interfacing and performance factors for the DMA Unit.  
10.3.1 DRQ Pin Timing Requirements  
The DRQ pins are sampled on the falling edge of CLKOUT. The DRQ pins must be set up a min-  
imum of TINVCL before CLKOUT falling, to guarantee recognition at a specific clock edge. Refer  
to the data sheet for specific values.  
The DRQ pins have an internal synchronizer. Violating the setup time can cause only a missed  
DMA request, not a processor malfunction.  
10-20  
DIRECT MEMORY ACCESS UNIT  
10.3.2 DMA Latency  
DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run.  
The DMA latency for a channel is controlled by many factors:  
Bus HOLD — Bus HOLD takes precedence over internal DMA requests. Using bus HOLD  
will degrade DMA latency.  
LOCKed Instructions — Long LOCKed instructions (e.g., LOCK REP MOVS) will  
monopolize the bus, preventing access by the DMA Unit.  
Inter-channel Priority Scheme — Setting a channel at low priority will affect its latency.  
The minimum latency in all cases is four CLKOUT cycles. This is the amount of time it takes to  
synchronize and prioritize a request.  
10.3.3 DMA Transfer Rates  
The maximum DMA transfer rate is a function of processor operating frequency and synchroni-  
zation mode. For unsynchronized and source-synchronized transfers, the 80C186 Modular Core  
can transfer two bytes every eight CLKOUT cycles. For destination-synchronized transfers, the  
addition of two idle T-states reduces the bandwidth by two clocks per word.  
Maximum DMA transfer rates (in Mbytes per second) for the 80C186 Modular Core are calcu-  
lated by the following equations, where FCPU is the CPU operating frequency (in megahertz).  
For unsynchronized and source-synchronized transfers:  
0.25 × FCPU  
For destination-synchronized transfers:  
0.20 × FCPU  
Because of its 8-bit data bus, the 80C188 Modular Core can transfer only one byte per DMA cy-  
cle. Therefore, the maximum transfer rates for the 80C188 Modular Core are half those calculated  
by the equations for the 80C186 Modular Core.  
10-21  
DIRECT MEMORY ACCESS UNIT  
10.3.4 Generating a DMA Acknowledge  
The DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line can be  
programmed to activate for the memory or I/O range that requires the acknowledge. The chip-  
select must be programmed to activate only when a DMA is in progress. Latched status line S6  
can be used as a qualifier to the chip-select for situations in which the chip-select line will be ac-  
tive for both DMA and normal data accesses.  
10.4 DMA UNIT EXAMPLES  
Example 10-1 sets up channel 0 to perform an unsynchronized burst transfer from memory to  
memory while channel 1 is used to service an external DMA request from a hard disk controller.  
Example 10-2 shows timed DMA transfers. A sawtooth waveform is created using DMA trans-  
fers to an A/D converter.  
10-22  
DIRECT MEMORY ACCESS UNIT  
$MOD186  
name  
DMA_EXAMPLE_1  
; This example shows code necessary to set up two DMA channels.  
; One channel performs an unsynchronized transfer from memory to memory.  
; The second channel is used by a hard disk controller located in  
; I/O space.  
; It is assumed that the constants for PCB register addresses are  
; defined elsewhere with EQUates.  
CODE_SEG SEGMENT  
ASSUME CS:CODE_SEG  
START:  
MOV  
MOV  
AX, DATA_SEG  
DS, AX  
; DATA SEGMENT POINTER  
ASSUME DS:DATA_SEG  
; First we must initialize DMA channel 0. DMA0 will perform an  
; unsynchronized transfer from SOURCE_DATA_1 to DEST_DATA_1.  
; The first step is to calculate the proper values for the  
; source and destination pointers.  
MOV  
AX, SEG SOURCE_DATA_1  
ROL  
MOV  
AND  
AX, 4  
; GET HIGH 4 BITS  
; SAVE ROTATED VALUE  
; GET SHIFTED LOW 4 NIBBLES  
BX, AX  
AX, 0FFF0H  
ADD  
AX, OFFSET SOURCE_DATA_1  
; NOW LOW BYTES OF POINTER ARE IN AX  
ADC  
BX, 0  
; ADD IN THE CARRY  
; TO THE HIGH NIBBLE  
; GET JUST THE HIGH NIBBLE  
AND  
MOV  
OUT  
BX, 000FH  
DX, D0SRCL  
DX, AL  
; AX=LOW 4 BYTES  
MOV  
MOV  
OUT  
DX, D0SRCH  
AX, BX  
DX, AX  
; GET HIGH NIBBLE  
; SOURCE POINTER DONE. REPEAT FOR DESTINATION.  
MOV  
AX, SEG DEST_DATA_1  
ROL  
MOV  
AND  
AX, 4  
; GET HIGH 4 BITS  
; SAVE ROTATED VALUE  
; GET SHIFTED LOW 4 NIBBLES  
BX, AX  
AX, 0FFF0H  
ADD  
AX, OFFSET DEST_DATA_1  
; NOW LOW BYTES OF POINTER ARE IN AX  
ADC  
BX, 0  
; ADD IN THE CARRY  
; TO THE HIGH NIBBLE  
; GET JUST THE HIGH NIBBLE  
AND  
MOV  
OUT  
BX, 000FH  
DX, D0DSTL  
DX, AX  
; AX=LOW 4 BYTES  
Example 10-1. Initializing the DMA Unit  
10-23  
 
DIRECT MEMORY ACCESS UNIT  
MOV  
MOV  
OUT  
DX, D0DSTH  
AX, BX  
DX, AX  
; GET HIGH NIBBLE  
; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT.  
MOV  
MOV  
OUT  
AX, 29  
DX, D0TC  
DX, AX  
; THE MESSAGE IS 29 BYTES LONG.  
; XFER COUNT REG  
; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS:  
;
;
;
;
;
;
DESTINATION  
-----------  
SOURCE  
------  
MEMORY SPACE MEMORY SPACE  
INCREMENT PTR INCREMENT PTR  
; TERMINATE ON TC, NO INTERRUPT, UNSYNCHRONIZED, LOW PRIORITY RELATIVE  
; TO CHANNEL 1, BYTE XFERS. WE START THE CHANNEL.  
MOV  
MOV  
OUT  
AX, 1011011000000110B  
DX, D0CON  
DX, AX  
; THE UNSYNCHRONIZED BURST IS NOW RUNNING ON THE BUS...  
; NOW SET UP CHANNEL 1 TO SERVICE THE DISK CONTROLLER.  
; FOR THIS EXAMPLE WE WILL ONLY BE READING FROM THE DISK.  
; THE SOURCE IS THE I/O PORT FOR THE DISK CONTROLLER.  
MOV  
MOV  
OUT  
AX, DISK_IO_ADDR  
DX, D1SRCL  
DX, AX  
; PROGRAM LOW ADDR  
; HI ADDR FOR IO=0  
XOR  
MOV  
OUT  
AX, AX  
DX, D1SRCH  
DX, AX  
; THE DESTINATION IS THE DISK BUFFER IN MEMORY  
MOV  
AX, SEG DISK_BUFF  
ROL  
MOV  
AND  
AX, 4  
; GET HIGH 4 BITS  
; SAVE ROTATED VALUE  
; GET SHIFTED LOW 4 NIBBLES  
BX, AX  
AX, 0FFF0H  
ADD  
AX, OFFSET DISK_BUFF  
; NOW LOW BYTES OF POINTER ARE IN AX  
ADC  
BX, 0  
; ADD IN THE CARRY  
; TO THE HIGH NIBBLE  
; GET JUST THE HIGH NIBBLE  
AND  
MOV  
OUT  
MOV  
MOV  
OUT  
BX, 000FH  
DX, D1DSTL  
DX, AL  
DX, D1DSTH  
AX, BX  
DX, AX  
; AX=LOW 4 BYTES  
; GET HIGH NIBBLE  
; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT.  
Example 10-1. Initializing the DMA Unit (Continued)  
10-24  
DIRECT MEMORY ACCESS UNIT  
MOV  
AX, 512  
; THE DISK READS IN 512 BYTE  
; XFER COUNT REG  
SECTORS  
MOV  
OUT  
DX, D1TC  
DX, AX  
; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS:  
;
;
;
;
;
;
DESTINATION  
-----------  
MEMORY SPACE  
INCREMENT PTR  
SOURCE  
------  
I/O SPACE  
CONSTANT PTR  
; TERMINATE ON TC, INTERRUPT, SOURCE SYNC, HIGH PRIORITY RELATIVE TO  
; CHANNEL 0, BYTE XFERS, USE DRQ PIN FOR REQUEST SOURCE. ARM CHANNEL.  
MOV  
MOV  
OUT  
AX, 1010001101100110B  
DX, D0CON  
DX, AX  
; REQUESTS ON DRQ1 WILL NOW RESULT IN TRANSFERS  
CODE_SEG ENDS  
DATA_SEG SEGMENT  
SOURCE_DATA_1DB '80C186EC INTEGRATED PROCESSOR'  
DEST_DATA_1DB  
DISK_BUFF DB  
DATA_SEG ENDS  
30 DUP('MITCH')  
; JUNK DATA FOR TEST  
512 DUP(?)  
END START  
Example 10-1. Initializing the DMA Unit (Continued)  
10-25  
DIRECT MEMORY ACCESS UNIT  
$mod186  
name  
DMA_EXAMPLE_1  
; This example sets up the DMA Unit to perform a transfer from memory to  
; I/O space every 22 uS. The data is sent to an A/D converter.  
; It is assumed that the constants for PCB register addresses are  
; defined elsewhere with EQUates.  
CODE_SEG SEGMENT  
ASSUME CS:CODE_SEG  
START:  
MOV  
MOV  
AX, DATA_SEG  
DS, AX  
; DATA SEGMENT POINTER  
ASSUME DS:DATA_SEG  
; First, set up the pointers. The source is in memory.  
MOV  
AX, SEG WAVEFORM_DATA  
ROL  
MOV  
AND  
AX, 4  
; GET HIGH 4 BITS  
; SAVE ROTATED VALUE  
; GET SHIFTED LOW 4 NIBBLES  
BX, AX  
AX, 0FFF0H  
ADD  
AX, OFFSET WAVEFORM_DATA  
; NOW LOW BYTES OF POINTER ARE IN AX.  
ADC  
BX, 0  
; ADD IN THE CARRY  
; TO THE HIGH NIBBLE  
; GET JUST THE HIGH NIBBLE  
AND  
MOV  
OUT  
BX, 000FH  
DX, D0SRCL  
DX, AX  
; AX=LOW 4 BYTES  
MOV  
MOV  
OUT  
DX, D0SRCH  
AX, BX  
; GET HIGH NIBBLE  
; I/O ADDRESS OF D/A  
DX, AX  
MOV  
MOV  
OUT  
AX, DA_CNVTR  
DX, D0DSTL  
DX, AX  
MOV  
XOR  
OUT  
DX, D0DSTH  
AX, AX  
; CLEAR HIGH NIBBLE  
DX, AX  
; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT.  
MOV  
MOV  
OUT  
AX, 255  
DX, D0TC  
DX, AX  
; 8-BIT D/A, SO WE SEND 256 BYTES  
; TO GET A FULL SCALE  
; PROGRAM IDRQ MUX  
MOV  
MOV  
DX, DMAPRI  
AX, 00H  
; TIMER2 IS IDRQ SOURCE  
; MODULES HAVE EQUAL PRIORITY  
OUT  
DX, AX  
Example 10-2. Timed DMA Transfers  
10-26  
 
DIRECT MEMORY ACCESS UNIT  
; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS:  
;
;
;
;
;
;
DESTINATION  
-----------  
I/O SPACE  
SOURCE  
------  
MEMORY SPACE  
CONSTANT PTR INCREMENT PTR  
; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS,  
; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS.  
MOV  
MOV  
OUT  
AX, 0001011101010110B  
DX, D0CON  
DX, AX  
; NOW WE ASSUME THAT TIMER 2 HAS BEEN PROPERLY PROGRAMMED FOR A 22uS DELAY.  
; WHEN THE TIMER IS STARTED, A DMA TRANSFER WILL OCCUR EVERY 22uS.  
CODE_SEG ENDS  
DATA_SEG SEGMENT  
WAVEFORM_DATADB 0,1,2,3,4,5,6,7,8,9,10,11,12,13  
DB  
14,15,16,17,18,19,20,21,22,23,24  
; ETC., UP TO 255  
DATA_SEG ENDS  
END START  
Example 10-2. Timed DMA Transfers (Continued)  
10-27  
11  
Math Coprocessing  
CHAPTER 11  
MATH COPROCESSING  
The 80C186 Modular Core Family meets the need for a general-purpose embedded microproces-  
sor. In most data control applications, efficient data movement and control instructions are fore-  
most and arithmetic performed on the data is simple. However, some applications do require  
more powerful arithmetic instructions and more complex data types than those provided by the  
80C186 Modular Core.  
11.1 OVERVIEW OF MATH COPROCESSING  
Applications needing advanced mathematics capabilities have the following characteristics.  
Numeric data values are non-integral or vary over a wide range  
Algorithms produce very large or very small intermediate results  
Computations must be precise (i.e., calculations must retain several significant digits)  
Computations must be reliable without dependence on programmed algorithms  
Overall math performance exceeds that afforded by a general-purpose processor and  
software alone  
For the 80C186 Modular Core family, the 80C187 math coprocessor satisfies the need for pow-  
erful mathematics. The 80C187 can increase the math performance of the microprocessor system  
by 50 to 100 times.  
11.2 AVAILABILITY OF MATH COPROCESSING  
The 80C186 Modular Core supports the 80C187 with a hardware interface under microcode con-  
trol. However, not all proliferations support the 80C187. Some package types have insufficient  
leads to support the required external handshaking requirements. The 3-volt versions of the pro-  
cessor do not specify math coprocessing because the 80C187 has only a 5-volt rating. Please refer  
to the current data sheets for details.  
To execute numerics instructions, the 80C186XL must exit reset in Enhanced Mode. The pro-  
cessor checks its TEST pin at reset and automatically enters Enhanced Mode if the math copro-  
cessor is present.  
11-1  
MATH COPROCESSING  
The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) to  
control the availability of math coprocessing. If the ET bit is set, an attempted numerics execution  
results in a Type 7 interrupt. The 80C187 will not work with the 8-bit bus version of the processor  
because all 80C187 accesses must be 16-bit. The 80C188 Modular Core automatically traps ESC  
(numerics) opcodes to the Type 7 interrupt, regardless of Relocation Register programming.  
11.3 THE 80C187 MATH COPROCESSOR  
The 80C187’s high performance is due to its 80-bit internal architecture. It contains three units:  
a Floating Point Unit, a Data Interface and Control Unit and a Bus Control Logic Unit. The foun-  
dation of the Floating Point Unit is an 8-element register file, which can be used either as indi-  
vidually addressable registers or as a register stack. The register file allows storage of  
intermediate results in the 80-bit format. The Floating Point Unit operates under supervision of  
the Data Interface and Control Unit. The Bus Control Logic Unit maintains handshaking and  
communications with the host microprocessor. The 80C187 has built-in exception handling.  
The 80C187 executes code written for the Intel387™ DX and Intel387 SX math coprocessors.  
The 80C187 conforms to ANSI/IEEE Standard 754-1985.  
11.3.1 80C187 Instruction Set  
80C187 instructions fall into six functional groups: data transfer, arithmetic, comparison, tran-  
scendental, constant and processor control. Typical 80C187 instructions accept one or two oper-  
ands and produce a single result. Operands are usually located in memory or the 80C187 stack.  
Some operands are predefined; for example, FSQRT always takes the square root of the number  
in the top stack element. Other instructions allow or require the programmer to specify the oper-  
and(s) explicitly along with the instruction mnemonic. Still other instructions accept one explicit  
operand and one implicit operand (usually the top stack element).  
As with the basic (non-numerics) instruction set, there are two types of operands for coprocessor  
instructions, source and destination. Instruction execution does not alter a source operand. Even  
when an instruction converts the source operand from one format to another (for example, real to  
integer), the coprocessor performs the conversion in a work area to preserve the source operand.  
A destination operand differs from a source operand because the 80C187 can alter the register  
when it receives the result of the operation. For most destination operands, the coprocessor usu-  
ally replaces the destinations with results.  
11-2  
MATH COPROCESSING  
11.3.1.1  
Data Transfer Instructions  
Data transfer instructions move operands between elements of the 80C187 register stack or be-  
tween stack top and memory. Instructions can convert any data type to temporary real and load it  
onto the stack in a single operation. Conversely, instructions can convert a temporary real oper-  
and on the stack to any data type and store it to memory in a single operation. Table 11-1 sum-  
marizes the data transfer instructions.  
Table 11-1. 80C187 Data Transfer Instructions  
Real Transfers  
FLD  
Load real  
FST  
Store real  
FSTP  
FXCH  
Store real and pop  
Exchange registers  
Integer Transfers  
FILD  
Integer load  
FIST  
Integer store  
FISTP  
Integer store and pop  
Packed Decimal Transfers  
FBLD  
Packed decimal (BCD) load  
FBSTP  
Packed decimal (BCD) store and pop  
11.3.1.2  
Arithmetic Instructions  
The 80C187’s arithmetic instruction set includes many variations of add, subtract, multiply, and  
divide operations and several other useful functions. Examples include a simple absolute value  
and a square root instruction that executes faster than ordinary division. Other arithmetic instruc-  
tions perform exact modulo division, round real numbers to integers and scale values by powers  
of two.  
Table 11-2 summarizes the available operation and operand forms for basic arithmetic. In addi-  
tion to the four normal operations, “reversed” instructions make subtraction and division “sym-  
metrical” like addition and multiplication. In summary, the arithmetic instructions are highly  
flexible for these reasons:  
the 80C187 uses register or memory operands  
the 80C187 can save results in a choice of registers  
11-3  
 
MATH COPROCESSING  
Available data types include temporary real, long real, short real, short integer and word integer.  
The 80C187 performs automatic type conversion to temporary real.  
Table 11-2. 80C187 Arithmetic Instructions  
Addition  
Add real  
Division  
Divide real  
FADD  
FDIV  
FADDP  
FIADD  
Add real and pop  
Integer add  
FDIVP  
FIDIV  
FDIVR  
Divide real and pop  
Integer divide  
Divide real reversed  
Subtraction  
FSUB  
Subtract real  
FDIVRP  
FIDIVR  
Divide real reversed and pop  
Integer divide reversed  
FSUBP  
FISUB  
Subtract real and pop  
Integer subtract  
Other Operations  
FSUBR  
FSUBRP  
FISUBR  
Subtract real reversed  
FSQRT  
Square root  
Scale  
Subtract real reversed and pop  
Integer subtract reversed  
FSCALE  
FPREM  
FRNDINT  
Partial remainder  
Round to integer  
Multiplication  
FMUL  
Multiply real  
FXTRACT  
FABS  
Extract exponent and significand  
Absolute value  
FMULP  
FIMUL  
Multiply real and pop  
Integer multiply  
FCHS  
Change sign  
FPREMI  
Partial remainder (IEEE)  
11-4  
 
MATH COPROCESSING  
11.3.1.3  
Comparison Instructions  
Each comparison instruction (see Table 11-3) analyzes the stack top element, often in relationship  
to another operand. Then it reports the result in the Status Word condition code. The basic oper-  
ations are compare, test (compare with zero) and examine (report tag, sign and normalization).  
Table 11-3. 80C187 Comparison Instructions  
FCOM  
Compare real  
FCOMP  
FCOMPP  
FICOM  
Compare real and pop  
Compare real and pop twice  
Integer compare  
FICOMP  
FTST  
Integer compare and pop  
Test  
FXAM  
Examine  
FUCOM  
FUCOMP  
FUCOMPP  
Unordered compare  
Unordered compare and pop  
Unordered compare and pop twice  
11.3.1.4  
Transcendental Instructions  
Transcendental instructions (see Table 11-4) perform the core calculations for common trigono-  
metric, hyperbolic, inverse hyperbolic, logarithmic and exponential functions. Use prologue code  
to reduce arguments to a range accepted by the instruction. Use epilogue code to adjust the result  
to the range of the original arguments. The transcendentals operate on the top one or two stack  
elements and return their results to the stack.  
Table 11-4. 80C187 Transcendental Instructions  
FPTAN  
FPATAN  
F2XM1  
FYL2X  
Partial tangent  
Partial arctangent  
X
2 – 1  
Y log2 X  
FYL2XP1  
FCOS  
Y log2 (X+1)  
Cosine  
FSIN  
Sine  
FSINCOS  
Sine and Cosine  
11-5  
   
MATH COPROCESSING  
11.3.1.5  
Constant Instructions  
Each constant instruction (see Table 11-5) loads a commonly used constant onto the stack. The  
values have full 80-bit precision and are accurate to about 19 decimal digits. Since a temporary  
real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save mem-  
ory space.  
Table 11-5. 80C187 Constant Instructions  
FLDZ  
Load + 0.1  
Load +1.0  
Load  
FLD1  
FLDPI  
FLDL2T  
FLDL2E  
FLDLG2  
FLDLN2  
Load log2 10  
Load log2 e  
Load log10  
2
Load loge 2  
11.3.1.6  
Processor Control Instructions  
Computations do not use the processor control instructions; these instructions are available for  
activities at the operating system level. This group (see Table 11-6) includes initialization, excep-  
tion handling and task switching instructions.  
Table 11-6. 80C187 Processor Control Instructions  
FINIT/FNINIT  
Initialize processor  
Disable interrupts  
Enable interrupts  
Load control word  
Store control word  
Store status word  
Clear exceptions  
Store environment  
FLDENV  
Load environment  
FDISI/FNDISI  
FENI/FNENI  
FSAVE/FNSAVE Save state  
FRSTOR  
FINCSTP  
FDECSTP  
FFREE  
Restore state  
FLDCW  
Increment stack pointer  
Decrement stack pointer  
Free register  
FSTCW/FNSTCW  
FSTSW/FNSTSW  
FCLEX/FNCLEX  
FSTENV/FNSTENV  
FNOP  
No operation  
FWAIT  
CPU wait  
11-6  
   
MATH COPROCESSING  
11.3.2 80C187 Data Types  
The microprocessor/math coprocessor combination supports seven data types:  
Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement  
representation.  
Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s  
complement representation.  
Long Integer — A signed 64-bit numeric value (quad word). All operations assume a 2’s  
complement representation.  
Packed Decimal — A signed numeric value contained in an 80-bit BCD format.  
Short Real — A signed 32-bit floating point numeric value.  
Long Real — A signed 64-bit floating point numeric value.  
Temporary Real — A signed 80-bit floating point numeric value. Temporary real is the  
native 80C187 format.  
Figure 11-1 graphically represents these data types.  
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION  
The 80C187 interfaces directly to the microprocessor (as shown in Figure 11-2) and operates as  
an I/O-mapped slave peripheral device. Hardware handshaking requires connections between the  
80C187 and four special pins on the processor: NCS, BUSY, PEREQ and ERROR. These pins  
are multiplexed with MCS3, TEST, MCS0, and MCS1, respectively. When the processor leaves  
reset, the presence of the 80C187 automatically places the processor in Enhanced Mode and con-  
figures the pins correctly. MCS2 retains its function as a chip-select and the processor retains the  
wait state and ready programming for the entire mid-range memory block, even though MCS0,  
MCS1 and MCS3 are no longer available.  
11-7  
MATH COPROCESSING  
Increasing Significance  
Word  
Integer  
(Two's Complement)  
S Magnitude  
15  
0
Short  
(Two's Complement)  
Magnitude  
S
Integer  
31  
0
(Two's  
Complement)  
Long  
Integer  
Magnitude  
S
63  
0
Magnitude  
Packed  
Decimal  
S
X
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
15  
10  
3
17 16  
14 13  
11  
7
6
5
4
2
1
0
12  
9
8
79  
72  
Short  
Real  
Biased  
S
Significand  
I
Exponent  
31  
0
23  
Long  
Real  
Biased  
Exponent  
Significand  
S
63  
52  
0
I
Temporary  
Real  
Biased  
Exponent  
Significand  
S
I
64 63  
79  
0
NOTES:  
S
d
= Sign bit (0 = positive, 1 = negative)  
= Decimal digit (two per byte)  
n
X
= Bits have no significance; 80C187 ignores when loading, zeros when storing.  
= Position of implicit binary point  
I
= Integer bit of significand; stored in temporary real, implicit in short and long real  
Exponent Bias (normalized values):  
Short Real: 127 (7FH)  
Long Real: 1023 (3FFH)  
Temporary Real: 16383 (FFFH)  
A1257-0A  
Figure 11-1. 80C187-Supported Data Types  
11-8  
 
MATH COPROCESSING  
Latch  
External  
Oscillator  
A1  
A2  
1
AD15:0  
ALE  
EN  
CKM  
CLK  
CLKOUT  
2
80C187  
80C186  
Modular  
Core  
RESET  
NPWR  
RESET  
WR  
RD  
NPRD  
BUSY  
BUSY  
ERROR  
ERROR  
PEREQ  
NPS1  
PEREQ  
NCS  
NPS2  
D15:0  
A1529-0A  
Figure 11-2. 80C186 Modular Core Family/80C187 System Configuration  
11-9  
 
MATH COPROCESSING  
11.4.1 Clocking the 80C187  
The microprocessor and math coprocessor operate asynchronously, and their clock rates may dif-  
fer. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided  
by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input  
from the microprocessor’s CLKOUT pin. Beyond 12.5 MHz, the 80C187 must use a multiply-  
by-two clock input up to a maximum of 32 MHz. The microprocessor and the math coprocessor  
have correct timing relationships, even with operation at different frequencies.  
11.4.2 Processor Bus Cycles Accessing the 80C187  
Data transfers between the microprocessor and the 80C187 occur through the dedicated, 16-bit  
I/O ports shown in Table 11-7. When the processor encounters a numerics opcode, it first writes  
the opcode to the 80C187. The 80C187 decodes the instruction and passes elementary instruction  
information (Opcode Status Word) back to the processor. Since the 80C187 is a slave processor,  
the Modular Core processor performs all loads and stores to memory. Including the overhead in  
the microprocessor’s microcode, each data transfer between memory and the 80C187 (via the mi-  
croprocessor) takes at least 17 processor clocks.  
Table 11-7. 80C187 I/O Port Assignments  
I/O Address  
Read Definition  
Write Definition  
00F8H  
00FAH  
00FCH  
00FEH  
Status/Control  
Data  
Opcode  
Data  
Reserved  
CS:IP, DS:EA  
Reserved  
Opcode Status  
The microprocessor cannot process any numerics (ESC) opcodes alone. If the CPU encounters a  
numerics opcode when the Escape Trap (ET) bit in the Relocation Register is a zero and the  
80C187 is not present, its operation is indeterminate. Even the FINIT/FNINIT initialization in-  
struction (used in the past to test the presence of a coprocessor) fails without the 80C187. If an  
application offers the 80C187 as an option, problems can be prevented in one of three ways:  
Remove all numerics (ESC) instructions, including code that checks for the presence of the  
80C187.  
Use a jumper or switch setting to indicate the presence of the 80C187. The program can  
interrogate the jumper or switch setting and branch away from numerics instructions when  
the 80C187 socket is empty.  
Trick the microprocessor into predictable operation when the 80C187 socket is empty. The  
fix is placing pull-up or pull-down resistors on certain data and handshaking lines so the  
CPU reads a recognizable Opcode Status Word. This solution requires a detailed knowledge  
of the interface.  
11-10  
 
MATH COPROCESSING  
Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with  
respect to the processor’s control pins. See “System Design Tips” for information on integrating  
the 80C187 into the overall system.  
11.4.3 System Design Tips  
All 80C187 operations require that bus ready be asserted. The simplest way to return the ready  
indication is through hardware connected to the processor’s external ready pin. If you program a  
chip-select to cover the math coprocessor port addresses, its ready programming is in force and  
can provide bus ready for coprocessor accesses. The user must verify that there are no conflicts  
from other hardware connected to that chip-select pin.  
A chip-select pin goes active on 80C187 accesses if you program it for a range including the math  
coprocessor I/O ports. The converse is not true — a non-80C187 access cannot activate NCS (nu-  
merics coprocessor select), regardless of programming.  
In a buffered system, it is customary to place the 80C187 on the local bus. Since DTR and DEN  
function normally during 80C187 transfers, you must qualify DEN with NCS (see Figure 11-3).  
Otherwise, contention between the 80C187 and the transceivers occurs on read cycles to the  
80C187.  
The microprocessor’s local bus is available to the integrated peripherals during numerics execu-  
tion whenever the CPU is not communicating with the 80C187. The idle bus allows the processor  
to intersperse DRAM refresh cycles and DMA cycles with accesses to the 80C187.  
The microprocessor’s local bus is available to alternate bus masters during execution of numerics  
instructions when the CPU does not need it. Bus cycles driven by alternate masters (via the  
HOLD/HLDA protocol) can suspend coprocessor bus cycles for an indefinite period.  
The programmer can lock 80C187 instructions. The CPU asserts the LOCK pin for the entire du-  
ration of a numerics instruction, monopolizing the bus for a very long time.  
11-11  
MATH COPROCESSING  
Latch  
External  
A15:0  
A2  
Oscillator  
Buffer  
T OE  
A1  
D15:8  
1
2
AD15:0  
ALE  
EN  
CKM  
CLK  
CLKOUT  
80C187  
80C186  
Modular  
Core  
RESET  
NPWR  
Buffer  
T OE  
RESET  
D7:0  
WR  
RD  
NPRD  
BUSY  
BUSY  
ERROR  
ERROR  
PEREQ  
NPS1  
PEREQ  
NCS  
CS  
DEN  
NPS2  
DT/R  
D15:0  
A1530-0A  
Figure 11-3. 80C187 Configuration with a Partially Buffered Bus  
11-12  
 
MATH COPROCESSING  
11.4.4 Exception Trapping  
The 80C187 detects six error conditions that can occur during instruction execution. The 80C187  
can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor  
tests ERROR at the beginning of numerics instructions, so it traps an exception on the next at-  
tempted numerics instruction after it occurs. When ERROR tests active, the processor executes a  
Type 16 interrupt.  
There is no automatic exception-trapping on the last numerics instruction of a series. If the last  
numerics instruction writes an invalid result to memory, subsequent non-numerics instructions  
can use that result as if it is valid, further compounding the original error. Insert the FNOP in-  
struction at the end of the 80C187 routine to force an ERROR check. If the program is written in  
a high-level language, it is impossible to insert FNOP. In this case, route the error signal through  
an inverter to an interrupt pin on the microprocessor (see Figure 11-4). With this arrangement,  
use a flip-flop to latch BUSY upon assertion of ERROR. The latch gets cleared during the excep-  
tion-handler routine. Use an additional flip-flop to latch PEREQ to maintain the correct hand-  
shaking sequence with the microprocessor.  
11.5 EXAMPLE MATH COPROCESSOR ROUTINES  
Example 11-1 shows the initialization sequence for the 80C187. Example 11-2 is an example of  
a floating point routine using the 80C187. The FSINCOS instruction yields both sine and cosine  
in one operation.  
11-13  
MATH COPROCESSING  
80C186  
Modular Core  
ERROR  
RESET  
CSx  
INTx  
Latch  
BUSY  
PEREQ  
NCS  
ALE  
EN  
A19:A16  
AD15:0  
RD  
WR  
C
CLKOUT  
A
d
d
r
e
s
s
D
Q
Q
'74  
D15:0  
D15:0  
S
CLK  
A2  
A1  
NPWR  
CMD1  
CMD0  
NPRD  
80C187  
A19:0  
C
NPS1  
D
Q
'74  
PEREQ  
CKM  
S
BUSY  
ERROR  
RESET  
NPS2  
A1531-0A  
Figure 11-4. 80C187 Exception Trapping via Processor Interrupt Pin  
11-14  
 
MATH COPROCESSING  
$mod186  
name  
;
example_80C187_init  
;FUNCTION:  
This function initializes the 80C187 numerics coprocessor.  
;
;SYNTAX:  
extern unsigned char far 187_init(void);  
None  
;
;INPUTS:  
;
;OUTPUTS:  
unsigned char - 0000h -> False -> coprocessor not initialized  
ffffh -> True -> coprocessor initialized  
;
;
;NOTE:  
Parameters are passed on the stack as required by  
high-level languages.  
;
;
lib_80186  
segment public ’code’  
assume cs:lib_80186  
public _187_init  
_187_initproc far  
push  
mov  
bp  
bp, sp  
;save caller’s bp  
;get current top of stack  
cli  
;disable maskable interrupts  
fninit  
fnstcw [bp-2]  
;init 80C187 processor  
;get current control word  
sti  
;enable interrupts  
mov  
and  
cmp  
je  
xor  
pop  
ret  
ax, [bp-2]  
ax, 0300h  
ax, 0300h  
Ok  
;mask off unwanted control bits  
;PC bits = 11  
;yes: processor ok  
ax, ax  
bp  
;return false (80C187 not ok)  
;restore caller’s bp  
Ok: and  
[bp-2], 0fffeh  
;unmask possible exceptions  
fldcw [bp-2]  
mov  
pop  
ret  
ax,0ffffh  
bp  
;return true (80C187 ok)  
;restore caller’s bp  
_187_initendp  
lib_80186ends  
end  
Example 11-1. Initialization Sequence for 80C187 Math Coprocessor  
11-15  
 
MATH COPROCESSING  
$mod186  
$modc187  
name  
example_80C187_proc  
;DESCRIPTION: This code section uses the 80C187 FSINCOS transcendental  
;
instruction to convert the locus of a point from polar  
to Cartesian coordinates.  
;
;
;VARIABLES:  
The variables consist of the radius, r, and the angle, theta.  
Both are expressed as 32-bit reals and 0 <= theta <= pi/4.  
;
;
;RESULTS:  
The results of the computation are the coordinates x and y  
expressed as 32-bit reals.  
;
;
;NOTES:  
This routine is coded for Intel ASM86. It is not set up as an  
HLL-callable routine.  
;
;
;
;
This code assumes that the 80C187 has already been initialized.  
assume cs:code, ds:data  
data  
segment at 0100h  
r
dd x.xxxx  
;substitute real operand  
;substitute real operand  
theta dd x.xxxx  
x
dd ?  
dd ?  
y
data  
code  
ends  
segment at 0080h  
convert  
proc far  
ax, data  
ds, ax  
mov  
mov  
fld  
fld  
r
;load radius  
;load angle  
theta  
fsincos  
fmul  
fstp  
fmul  
fstp  
;st=cos, st(1)=sin  
;compute x  
st, st(2)  
x
;store to memory and pop  
;compute y  
y
;store to memory and pop  
convertendp  
code  
ends  
end  
Example 11-2. Floating Point Math Routine Using FSINCOS  
11-16  
 
12  
ONCE Mode  
CHAPTER 12  
ONCE MODE  
ONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, or  
weakly held high/low pins except OSCOUT. To allow device operation with a crystal network,  
OSCOUT does not three-state.  
ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows  
a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing. An  
in-circuit emulation probe uses ONCE Mode to isolate a surface-mounted device from board log-  
ic and essentially “take over” operation of the board (without removing the soldered device from  
the board).  
12.1 ENTERING/LEAVING ONCE MODE  
Forcing UCS and LCS low while RES is asserted (low) enables ONCE Mode (see Figure 12-1).  
Maintaining UCS and LCS and RES low continues to keep ONCE Mode active. Returning UCS  
and LCS high exits ONCE Mode.  
However, it is possible to keep ONCE Mode always active by deasserting RES while keeping  
UCS and LCS low. Removing RES “latches” ONCE Mode and allows UCS and LCS to be driv-  
en to any level. UCS and LCS must remain low for at least one clock beyond the time RES is  
driven high. Asserting RES exits ONCE Mode, assuming UCS and LCS do not also remain low  
(see Figure 12-1).  
12-1  
ONCE MODE  
RES  
UCS  
2
LCS  
3
1
All output,  
bidirectional,  
weakly held  
pins except  
OSCOUT  
NOTES: 1. Entering ONCE Mode.  
2. Latching ONCE Mode.  
3. Leaving ONCE Mode (assuming 2 occurred).  
A1532-0A  
Figure 12-1. Entering/Leaving ONCE Mode  
12-2  
 
A
80C186 Instruction  
Set Additions and  
Extensions  
APPENDIX A  
80C186 INSTRUCTION SET  
ADDITIONS AND EXTENSIONS  
The 80C186 Modular Core family instruction set differs from the original 8086/8088 instruction  
set in two ways. First, several instructions that were not available in the 8086/8088 instruction set  
have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186  
Modular Core family instruction set.  
A.1 80C186 INSTRUCTION SET ADDITIONS  
This section describes the seven instructions that were added to the base 8086/8088 instruction  
set to make the instruction set for the 80C186 Modular Core family. These instructions did not  
exist in the 8086/8088 instruction set.  
Data transfer instructions  
— PUSHA  
— POPA  
String instructions  
— INS  
— OUTS  
High-level instructions  
— ENTER  
— LEAVE  
— BOUND  
A.1.1 Data Transfer Instructions  
PUSHA/POPA  
PUSHA (push all) and POPA (pop all) allow all general-purpose registers to be stacked and un-  
stacked. The PUSHA instruction pushes all CPU registers (except as noted below) onto the stack.  
The POPA instruction pops all registers pushed by PUSHA off of the stack. The registers are  
pushed onto the stack in the following order: AX, CX, DX, BX, SP, BP, SI, DI. The Stack Pointer  
(SP) value pushed is the Stack Pointer value before the AX register was pushed. When POPA is  
executed, the Stack Pointer value is popped, but ignored. Note that this instruction does not save  
segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), the Processor Status Word or  
any integrated peripheral registers.  
A-1  
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
A.1.2 String Instructions  
INS source_string, port  
INS (in string) performs block input from an I/O port to memory. The port address is placed in  
the DX register. The memory address is placed in the DI register. This instruction uses the ES  
segment register (which cannot be overridden). After the data transfer takes place, the pointer reg-  
ister (DI) increments or decrements, depending on the value of the Direction Flag (DF). The  
pointer register changes by one for byte transfers or by two for word transfers.  
OUTS port, destination_string  
OUTS (out string) performs block output from memory to an I/O port. The port address is placed  
in the DX register. The memory address is placed in the SI register. This instruction uses the DS  
segment register, but this may be changed with a segment override instruction. After the data  
transfer takes place, the pointer register (SI) increments or decrements, depending on the value  
of the Direction Flag (DF). The pointer register changes by one for byte transfers or by two for  
word transfers.  
A.1.3 High-Level Instructions  
ENTER size, level  
ENTER creates the stack frame required by most block-structured high-level languages. The first  
parameter, size, specifies the number of bytes of dynamic storage to be allocated for the procedure  
being entered (16-bit value). The second parameter, level, is the lexical nesting level of the pro-  
cedure (8-bit value). Note that the higher the lexical nesting level, the lower the procedure is in  
the nesting hierarchy.  
The lexical nesting level determines the number of pointers to higher level stack frames copied  
into the current stack frame. This list of pointers is called the display. The first word of the display  
points to the previous stack frame. The display allows access to variables of higher level (lower  
lexical nesting level) procedures.  
After ENTER creates a display for the current procedure, it allocates dynamic storage space. The  
Stack Pointer decrements by the number of bytes specified bysize. All PUSH and POP operations  
in the procedure use this value of the Stack Pointer as a base.  
Two forms of ENTER exist: non-nested and nested. A lexical nesting level of 0 specifies the non-  
nested form. In this situation, BP is pushed, then the Stack Pointer is copied to BP and decrement-  
ed by the size of the frame. If the lexical nesting level is greater than 0, the nested form is used.  
Figure A-1 gives the formal definition of ENTER.  
A-2  
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
The following listing gives the formal definition of the  
ENTER instruction for all cases.  
LEVEL denotes the value of the second operand.  
Push BP  
Set a temporary value FRAME_PTR: = SP  
If LEVEL > 0 then  
Repeat (LEVEL - 1) times:  
BP:=BP - 2  
Push the word pointed to by BP  
End Repeat  
Push FRAME_PTR  
End if  
BP:=FRAME_PTR  
SP:=SP - first operand  
Figure A-1. Formal Definition of ENTER  
ENTER treats a reentrant procedure as a procedure calling another procedure at the same lexical  
level. A reentrant procedure can address only its own variables and variables of higher-level call-  
ing procedures. ENTER ensures this by copying only stack frame pointers from higher-level pro-  
cedures.  
Block-structured high-level languages use lexical nesting levels to control access to variables of  
previously nested procedures. For example, assume for Figure A-2 that Procedure A calls Proce-  
dure B, which calls Procedure C, which calls Procedure D. Procedure C will have access to the  
variables of Main and Procedure A, but not to those of Procedure B because Procedures C and B  
operate at the same lexical nesting level.  
The following is a summary of the variable access for Figure A-2.  
1. Main has variables at fixed locations.  
2. Procedure A can access only the fixed variables of Main.  
3. Procedure B can access only the variables of Procedure A and Main.  
Procedure B cannot access the variables of Procedure C or Procedure D.  
4. Procedure C can access only the variables of Procedure A and Main.  
Procedure C cannot access the variables of Procedure B or Procedure D.  
5. Procedure D can access the variables of Procedure C, Procedure A and Main.  
Procedure D cannot access the variables of Procedure B.  
A-3  
 
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
Main Program (Lexical Level 1)  
Procedure A (Lexical Level 2)  
Procedure B (Lexical Level 3)  
Procedure C (Lexical Level 3)  
Procedure D (Lexical Level 4)  
A1001-0A  
Figure A-2. Variable Access in Nested Procedures  
The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but  
no pointers are copied. The only word in the display points to itself because no previous value  
exists to return to after LEAVE is executed (see Figure A-3).  
0
15  
Old BP  
BPM  
BP  
SP  
Display Main  
Dynamic  
Storage  
Main  
*BPM = BP Value for MAIN  
A1002-0A  
a1002
0a pc  
Figure A-3. Stack Frame for Main at Level 1  
After Main calls Procedure A, ENTER creates a new display for Procedure A. The first word  
points to the previous value of BP (BPM). The second word points to the current value of BP  
(BPA). BPM contains the base for dynamic storage in Main. All dynamic variables for Main will  
be at a fixed offset from this value (see Figure A-4).  
A-4  
   
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
15  
0
Old BP  
BPM  
BPM  
BP  
SP  
Display A  
BPM  
BPA*  
Dynamic  
Storage A  
*BPA = BP Value for Procedure A  
A1003-0A  
Figure A-4. Stack Frame for Procedure A at Level 2  
After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word  
of the display points to the previous value of BP (BPA). The second word points to the value of  
BP for MAIN (BPM). The third word points to the BP for Procedure A (BPA). The last word  
points to the current BP (BPB). Procedure B can access variables in Procedure A or Main via the  
appropriate BP in the display (see Figure A-5).  
After Procedure B calls Procedure C, ENTER creates the display for Procedure C. The first word  
of the display points to the previous value of BP (BPB). The second word points to the value of  
BP for MAIN (BPM). The third word points to the value of BP for Procedure A (BPA). The  
fourth word points to the current BP (BPC). Because Procedure B and Procedure C have the same  
lexical nesting level, Procedure C cannot access variables in Procedure B. The only pointer to  
Procedure B in the display of Procedure C exists to allow the LEAVE instruction to collapse the  
Procedure C stack frame (see Figure A-6).  
A-5  
 
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
15  
0
Old BP  
BPM  
BPM  
BPM  
BPA  
BPA  
BP  
BPM  
BPA  
BPB  
Display B  
Dynamic  
Storage B  
SP  
A1004-0A  
Figure A-5. Stack Frame for Procedure B at Level 3 Called from A  
A-6  
 
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
15  
0
Old BP  
BPM  
BPM  
BPM  
BPA  
BPA  
BPM  
BPA  
BPB  
BPB  
BPM  
BP  
Display C  
BPA  
BPC  
Dynamic  
Storage C  
SP  
A1005-0A  
Figure A-6. Stack Frame for Procedure C at Level 3 Called from B  
LEAVE  
LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack  
frame created. First, LEAVE copies the current BP to the Stack Pointer, releasing the stack space  
allocated to the current procedure. Second, LEAVE pops the old value of BP from the stack, to  
return to the calling procedure's stack frame. A RET instruction will remove arguments stacked  
by the calling procedure for use by the called procedure.  
A-7  
 
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
BOUND register, address  
BOUND verifies that the signed value in the specified register lies within specified limits. If the  
value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful  
for checking array bounds before attempting to access an array element. This prevents the pro-  
gram from overwriting information outside the limits of the array.  
BOUND has two operands. The first, register, specifies the register being tested. The second, ad-  
dress, contains the effective relative address of the two signed boundary values. The lower limit  
word is at this address and the upper limit word immediately follows. The limit values cannot be  
register operands (if they are, an invalid opcode exception occurs).  
A.2 80C186 INSTRUCTION SET ENHANCEMENTS  
This section describes ten instructions that were available with the 8086/8088 but have been en-  
hanced for the 80C186 Modular Core family.  
Data transfer instructions  
— PUSH  
Arithmetic instructions  
— IMUL  
Bit manipulation instructions (shifts and rotates)  
— SAL  
— SHL  
— SAR  
— SHR  
— ROL  
— ROR  
— RCL  
— RCR  
A.2.1 Data Transfer Instructions  
PUSH data  
PUSH (push immediate) allows an immediate argument, data, to be pushed onto the stack. The  
value can be either a byte or a word. Byte values are sign extended to word size before being  
pushed.  
A-8  
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
A.2.2 Arithmetic Instructions  
IMUL destination, source, data  
IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate op-  
erand. IMUL requires three operands. The first, destination, is the register where the result will  
be placed. The second, source, is the effective address of the multiplier. The source may be the  
same register as the destination, another register or a memory location. The third, data, is an im-  
mediate value used as the multiplicand. The data operand may be a byte or word. If data is a byte,  
it is sign extended to 16 bits. Only the lower 16 bits of the result are saved. The result must be  
placed in a general-purpose register.  
A.2.3 Bit Manipulation Instructions  
This section describes the eight enhanced bit-manipulation instructions.  
A.2.3.1  
Shift Instructions  
SAL destination, count  
SAL (immediate shift arithmetic left) shifts the destination operand left by an immediate value.  
SAL has two operands. The first, destination, is the effective address to be shifted. The second,  
count, is an immediate byte value representing the number of shifts to be made. The CPU will  
AND count with 1FH before shifting, to allow no more than 32 shifts. Zeros shift in on the right.  
SHL destination, count  
SHL (immediate shift logical left) is physically the same instruction as SAL (immediate shift  
arithmetic left).  
SAR destination, count  
SAR (immediate shift arithmetic right) shifts the destination operand right by an immediate val-  
ue. SAL has two operands. The first, destination, is the effective address to be shifted. The sec-  
ond, count, is an immediate byte value representing the number of shifts to be made. The CPU  
will AND count with 1FH before shifting, to allow no more than 32 shifts. The value of the orig-  
inal sign bit shifts into the most-significant bit to preserve the initial sign.  
SHR destination, count  
SHR (immediate shift logical right) is physically the same instruction as SAR (immediate shift  
arithmetic right).  
A-9  
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS  
A.2.3.2  
Rotate Instructions  
ROL destination, count  
ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL  
has two operands. The first, destination, is the effective address to be rotated. The second, count,  
is an immediate byte value representing the number of rotations to be made. The most-significant  
bit of destination rotates into the least-significant bit.  
ROR destination, count  
ROR (immediate rotate right) rotates the destination byte or word right by an immediate value.  
ROR has two operands. The first, destination, is the effective address to be rotated. The second,  
count, is an immediate byte value representing the number of rotations to be made. The least-sig-  
nificant bit of destination rotates into the most-significant bit.  
RCL destination, count  
RCL (immediate rotate through carry left) rotates the destination byte or word left by an imme-  
diate value. RCL has two operands. The first, destination, is the effective address to be rotated.  
The second, count, is an immediate byte value representing the number of rotations to be made.  
The Carry Flag (CF) rotates into the least-significant bit of destination. The most-significant bit  
of destination rotates into the Carry Flag.  
RCR destination, count  
RCR (immediate rotate through carry right) rotates the destination byte or word right by an im-  
mediate value. RCR has two operands. The first, destination, is the effective address to be rotated.  
The second, count, is an immediate byte value representing the number of rotations to be made.  
The Carry Flag (CF) rotates into the most-significant bit of destination. The least-significant bit  
of destination rotates into the Carry Flag.  
A-10  
B
Input  
Synchronization  
APPENDIX B  
INPUT SYNCHRONIZATION  
Many input signals to an embedded processor are asynchronous. Asynchronous signals do not re-  
quire a specified setup or hold time to ensure the device does not incur a failure. However, asyn-  
chronous setup and hold times are specified in the data sheet to ensure recognition. Associated  
with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchro-  
nous signal and synchronizes it to the internal operating clock. The output of the synchronizing  
circuit is then safely routed to the logic units.  
Synchronized  
Output  
Asynchronous  
Input  
D
Q
D
Q
First  
Latch  
Second  
Latch  
2
1
NOTES:  
1. First latch sample clock, can be phase 1 or phase 2 depending on pin function.  
2. Second latch sample clock, opposite phase of first latch sample clock  
(e.g., if first latch is sampled with phase 1, the second latch is sampled with phase 2).  
A1007-0A  
Figure B-1. Input Synchronization Circuit  
B.1 WHY SYNCHRONIZERS ARE REQUIRED  
Every data latch requires a specific setup and hold time to operate properly. The duration of the  
setup and hold time defines a window during which the device attempts to latch the data. If the  
input makes a transition within this window, the output may not attain a stable state. The data  
sheet specifies a setup and hold window larger than is actually required. However, variations in  
device operation (e.g., temperature, voltage) require that a larger window be specified to cover  
all conditions.  
Should the input to the data latch make a transition during the sample and hold window, the out-  
put of the latch eventually attains a stable state. This stable state must be attained before the sec-  
ond stage of synchronization requires a valid input. To synchronize an asynchronous signal, the  
circuit in Figure B-1 samples the input into the first latch, allows the output to stabilize, then sam-  
ples the stabilized value into a second latch. With the asynchronous signal resolved in this way,  
the input signal cannot cause an internal device failure.  
B-1  
 
INPUT SYNCHRONIZATION  
A synchronization failure can occur when the output of the first latch does not meet the setup and  
hold requirements of the input of the second latch. The rate of failure is determined by the actual  
size of the sampling window of the data latch and by the amount of time between the strobe sig-  
nals of the two latches. As the sampling window gets smaller, the number of times an asynchro-  
nous transition occurs during the sampling window drops.  
B.2 ASYNCHRONOUS PINS  
The 80C186XL/80C188XL inputs that use the two-stage synchronization circuit are TMR IN 0,  
TMR IN 1, NMI, TEST/BUSY, INT3:0, HOLD, DRQ0 and DRQ1.  
B-2  
C
Instruction Set  
Descriptions  
APPENDIX C  
INSTRUCTION SET DESCRIPTIONS  
This appendix provides reference information for the 80C186 Modular Core family instruction  
set. Tables C-1 through C-3 define the variables used in Table C-4, which lists the instructions  
with their descriptions and operations.  
Table C-1. Instruction Format Variables  
Variable  
Description  
dest  
src  
A register or memory location that may contain data operated on by the instruction,  
and which receives (is replaced by) the result of the operation.  
A register, memory location or immediate value that is used in the operation, but is not  
altered by the instruction  
target  
disp8  
A label to which control is to be transferred directly, or a register or memory location  
whose content is the address of the location to which control is to be transferred  
indirectly.  
A label to which control is to be conditionally transferred; must lie within –128 to +127  
bytes of the first byte of the next instruction.  
accum  
port  
Register AX for word transfers, AL for bytes.  
An I/O port number; specified as an immediate value of 0–255, or register DX (which  
contains port number in range 0–64K).  
src-string  
Name of a string in memory that is addressed by register SI; used only to identify  
string as byte or word and specify segment override, if any. This string is used in the  
operation, but is not altered.  
dest-string  
count  
Name of string in memory that is addressed by register DI; used only to identify string  
as byte or word. This string receives (is replaced by) the result of the operation.  
Specifies number of bits to shift or rotate; written as immediate value 1 or register CL  
(which contains the count in the range 0–255).  
interrupt-type  
Immediate value of 0–255 identifying interrupt pointer number.  
optional-pop-value Number of bytes (0–64K, ordinarily an even number) to discard from the stack.  
external-opcode  
Immediate value (0–63) that is encoded in the instruction for use by an external  
processor.  
C-1  
 
INSTRUCTION SET DESCRIPTIONS  
Table C-2. Instruction Operands  
Operand  
Description  
reg  
An 8- or 16-bit general register.  
An 16-bit general register.  
A segment register.  
reg16  
seg-reg  
accum  
Register AX or AL  
immed  
A constant in the range 0–FFFFH.  
A constant in the range 0–FFH.  
An 8- or 16-bit memory location.  
A 16-bit memory location.  
A 32-bit memory location.  
Name of 256-byte translate table.  
immed8  
mem  
mem16  
mem32  
src-table  
src-string  
dest-string  
short-label  
near-label  
far-label  
near-proc  
far-proc  
memptr16  
Name of string addressed by register SI.  
Name of string addressed by register DI.  
A label within the –128 to +127 bytes of the end of the instruction.  
A lavel in current code segment.  
A label in another code segment.  
A procedure in current code segment.  
A procedure in another code segment.  
A word containing the offset of the location in the current code segment to which  
control is to be transferred.  
memptr32  
regptr16  
repeat  
A doubleword containing the offset and the segment base address of the location in  
another code segment to which control is to be transferred.  
A 16-bit general register containing the offset of the location in the current code  
segment to which control is to be transferred.  
A string instruction repeat prefix.  
C-2  
INSTRUCTION SET DESCRIPTIONS  
Table C-3. Flag Bit Functions  
Name  
Function  
AF  
Auxiliary Flag:  
Set on carry from or borrow to the low order four bits of AL; cleared otherwise.  
CF  
DF  
Carry Flag:  
Set on high-order bit carry or borrow; cleared otherwise.  
Direction Flag:  
Causes string instructions to auto decrement the appropriate index register  
when set. Clearing DF causes auto increment.  
IF  
Interrupt-enable Flag:  
When set, maskable interrupts will cause the CPU to transfer control to an  
interrupt vector specified location.  
OF  
PF  
Overflow Flag:  
Set if the signed result cannot be expressed within the number of bits in the  
destination operand; cleared otherwise.  
Parity Flag:  
Set if low-order 8 bits of result contain an even number of 1 bits; cleared  
otherwise.  
SF  
TF  
Sign Flag:  
Set equal to high-order bit of result (0 if positive, 1 if negative).  
Single Step Flag:  
Once set, a single step interrupt occurs after the next instruction executes. TF  
is cleared by the single step interrupt.  
ZF  
Zero Flag:  
Set if result is zero; cleared otherwise.  
C-3  
 
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set  
Flags  
Affected  
Name  
AAA  
Description  
Operation  
ASCII Adjust for Addition:  
if  
AF  
((AL) and 0FH) > 9 or (AF) = 1  
then  
(AL) (AL) + 6  
CF  
DF –  
IF  
OF ?  
PF ?  
SF ?  
TF –  
ZF ?  
AAA  
Changes the contents of register AL to  
a valid unpacked decimal number; the  
high-order half-byte is zeroed.  
(AH) (AH) + 1  
(AF) 1  
(CF) (AF)  
Instruction Operands:  
(AL) (AL) and 0FH  
none  
AAD  
ASCII Adjust for Division:  
(AL) (AH) × 0AH + (AL)  
(AH) 0  
AF ?  
CF ?  
DF –  
AAD  
Modifies the numerator in AL before  
dividing two valid unpacked decimal  
operands so that the quotient  
produced by the division will be a valid  
unpacked decimal number. AH must  
be zero for the subsequent DIV to  
produce the correct result. The  
IF  
OF ?  
PF  
SF  
TF –  
ZF  
quotient is returned in AL, and the  
remainder is returned in AH; both high-  
order half-bytes are zeroed.  
Instruction Operands:  
none  
AAM  
ASCII Adjust for Multiply:  
(AH) (AL) / 0AH  
(AL) (AL) % 0AH  
AF ?  
CF ?  
DF –  
AAM  
Corrects the result of a previous multi-  
plication of two valid unpacked  
IF  
OF ?  
PF  
SF  
TF –  
ZF  
decimal operands. A valid 2-digit  
unpacked decimal number is derived  
from the content of AH and AL and is  
returned to AH and AL. The high-order  
half-bytes of the multiplied operands  
must have been 0H for AAM to  
produce a correct result.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-4  
 
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
AAS  
Description  
Operation  
ASCII Adjust for Subtraction:  
if  
AF  
((AL) and 0FH) > 9 or (AF) = 1  
then  
(AL) (AL) – 6  
CF  
AAS  
DF –  
IF –  
OF ?  
PF ?  
SF ?  
TF –  
ZF ?  
Corrects the result of a previous  
subtraction of two valid unpacked  
decimal operands (the destination  
operand must have been specified as  
register AL). Changes the content of  
AL to a valid unpacked decimal  
number; the high-order half-byte is  
zeroed.  
(AH) (AH) – 1  
(AF) 1  
(CF) (AF)  
(AL) (AL) and 0FH  
Instruction Operands:  
none  
ADC  
Add with Carry:  
ADC dest, src  
if  
AF  
CF  
(CF) = 1  
then  
(dest) (dest) + (src) + 1  
else  
(dest) (dest) + (src)  
DF –  
IF –  
OF  
PF  
SF  
Sums the operands, which may be  
bytes or words, adds one if CF is set  
and replaces the destination operand  
with the result. Both operands may be  
signed or unsigned binary numbers  
(see AAA and DAA). Since ADC incor-  
porates a carry from a previous  
operation, it can be used to write  
routines to add numbers longer than  
16 bits.  
TF –  
ZF  
Instruction Operands:  
ADC reg, reg  
ADC reg, mem  
ADC mem, reg  
ADC reg, immed  
ADC mem, immed  
ADC accum, immed  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-5  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
ADD  
Description  
Operation  
Addition:  
(dest) (dest) + (src)  
AF  
CF  
DF –  
ADD dest, src  
Sums two operands, which may be  
bytes or words, replaces the  
destination operand. Both operands  
may be signed or unsigned binary  
numbers (see AAA and DAA).  
IF  
OF  
PF  
SF  
TF –  
ZF  
Instruction Operands:  
ADD reg, reg  
ADD reg, mem  
ADD mem, reg  
ADD reg, immed  
ADD mem, immed  
ADD accum, immed  
AND  
And Logical:  
(dest) (dest) and (src)  
(CF) 0  
(OF) 0  
AF ?  
CF  
DF –  
AND dest, src  
Performs the logical "and" of the two  
operands (byte or word) and returns  
the result to the destination operand. A  
bit in the result is set if both corre-  
sponding bits of the original operands  
are set; otherwise the bit is cleared.  
IF  
OF  
PF  
SF  
TF –  
ZF  
Instruction Operands:  
AND reg, reg  
AND reg, mem  
AND mem, reg  
AND reg, immed  
AND mem, immed  
AND accum, immed  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-6  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
BOUND  
Detect Value Out of Range:  
if  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
((dest) < (src) or (dest) > ((src) + 2)  
then  
BOUND dest, src  
Provides array bounds checking in  
hardware. The calculated array index  
is placed in one of the general purpose  
registers, and the upper and lower  
bounds of the array are placed in two  
consecutive memory locations. The  
contents of the register are compared  
with the memory location values, and if  
the register value is less than the first  
location or greater than the second  
memory location, a trap type 5 is  
generated.  
(SP) (SP) – 2  
((SP) + 1 : (SP)) FLAGS  
(IF) 0  
(TF) 0  
(SP) (SP) – 2  
((SP) + 1 : (SP)) (CS)  
(CS) (1EH)  
(SP) (SP) – 2  
((SP) + 1 : (SP)) (IP)  
(IP) (1CH)  
Instruction Operands:  
BOUND reg, mem  
CALL  
Call Procedure:  
if  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Inter-segment  
then  
CALL procedure-name  
Activates an out-of-line procedure,  
saving information on the stack to  
permit a RET (return) instruction in the  
procedure to transfer control back to  
the instruction following the CALL. The  
assembler generates a different type  
of CALL instruction depending on  
whether the programmer has defined  
the procedure name as NEAR or FAR.  
(SP) (SP) – 2  
((SP) +1:(SP)) (CS)  
(CS) SEG  
(SP) (SP) – 2  
((SP) +1:(SP)) (IP)  
(IP) dest  
Instruction Operands:  
CALL near-proc  
CALL far-proc  
CALL memptr16  
CALL regptr16  
CALL memptr32  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-7  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
CBW  
Description  
Operation  
Convert Byte to Word:  
if  
AF –  
CF –  
DF –  
(AL) < 80H  
then  
(AH) 0  
else  
(AH) FFH  
CBW  
Extends the sign of the byte in register  
AL throughout register AH. Use to  
produce a double-length (word)  
dividend from a byte prior to  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
performing byte division.  
Instruction Operands:  
none  
CLC  
Clear Carry flag:  
CLC  
(CF) 0  
AF –  
CF  
DF –  
Zeroes the carry flag (CF) and affects  
no other flags. Useful in conjunction  
with the rotate through carry left (RCL)  
and the rotate through carry right  
(RCR) instructions.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
none  
CLD  
Clear Direction flag:  
(DF) 0  
AF –  
CF –  
DF  
CLD  
Zeroes the direction flag (DF) causing  
the string instructions to auto-  
increment the source index (SI) and/or  
destination index (DI) registers.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-8  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
CLI  
Description  
Operation  
Clear Interrupt-enable Flag:  
(IF) 0  
AF –  
CF –  
DF –  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
CLI  
Zeroes the interrupt-enable flag (IF).  
When the interrupt-enable flag is  
cleared, the 8086 and 8088 do not  
recognize an external interrupt request  
that appears on the INTR line; in other  
words maskable interrupts are  
disabled. A non-maskable interrupt  
appearing on NMI line, however, is  
honored, as is a software interrupt.  
Instruction Operands:  
none  
CMC  
Complement Carry Flag:  
if  
AF –  
CF  
(CF) = 0  
then  
(CF) 1  
else  
CMC  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Toggles complement carry flag (CF) to  
its opposite state and affects no other  
flags.  
(CF) 0  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-9  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
CMP  
Description  
Operation  
Compare:  
(dest) – (src)  
AF  
CF  
DF –  
CMP dest, src  
Subtracts the source from the desti-  
nation, which may be bytes or words,  
but does not return the result. The  
operands are unchanged, but the flags  
are updated and can be tested by a  
subsequent conditional jump  
IF  
OF  
PF  
SF  
TF –  
ZF  
instruction. The comparison reflected  
in the flags is that of the destination to  
the source. If a CMP instruction is  
followed by a JG (jump if greater)  
instruction, for example, the jump is  
taken if the destination operand is  
greater than the source operand.  
Instruction Operands:  
CMP reg, reg  
CMP reg, mem  
CMP mem, reg  
CMP reg, immed  
CMP mem, immed  
CMP accum, immed  
CMPS  
Compare String:  
(dest-string) – (src-string)  
if  
(DF) = 0  
AF  
CF  
DF –  
IF  
OF  
PF  
SF  
TF –  
ZF  
CMPS dest-string, src-string  
Subtracts the destination byte or word  
from the source byte or word. The  
destination byte or word is addressed  
by the destination index (DI) register  
and the source byte or word is  
addresses by the source index (SI)  
register. CMPS updates the flags to  
reflect the relationship of the  
then  
(SI) (SI) + DELTA  
(DI) (DI) + DELTA  
else  
(SI) (SI) – DELTA  
(DI) (DI) – DELTA  
destination element to the source  
element but does not alter either  
operand and updates SI and DI to  
point to the next string element.  
Instruction Operands:  
CMP dest-string, src-string  
CMP (repeat) dest-string, src-string  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-10  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
CWD  
Description  
Operation  
Convert Word to Doubleword:  
if  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
(AX) < 8000H  
then  
(DX) 0  
else  
(DX) FFFFH  
CWD  
Extends the sign of the word in register  
AX throughout register DX. Use to  
produce a double-length (doubleword)  
dividend from a word prior to  
performing word division.  
Instruction Operands:  
none  
DAA  
Decimal Adjust for Addition:  
if  
AF  
((AL) and 0FH) > 9 or (AF) = 1  
then  
(AL) (AL) + 6  
(AF) 1  
CF  
DAA  
DF –  
IF –  
OF ?  
PF  
SF  
TF –  
ZF  
Corrects the result of previously  
adding two valid packed decimal  
operands (the destination operand  
must have been register AL). Changes  
the content of AL to a pair of valid  
packed decimal digits.  
if  
(AL) > 9FH or (CF) = 1  
then  
(AL) (AL) + 60H  
Instruction Operands:  
(CF) 1  
none  
DAS  
Decimal Adjust for Subtraction:  
if  
AF  
((AL) and 0FH) > 9 or (AF) = 1  
then  
(AL) (AL) – 6  
CF  
DAS  
DF –  
IF –  
OF ?  
PF  
SF  
TF –  
ZF  
Corrects the result of a previous  
subtraction of two valid packed  
decimal operands (the destination  
operand must have been specified as  
register AL). Changes the content of  
AL to a pair of valid packed decimal  
digits.  
(AF) 1  
if  
(AL) > 9FH or (CF) = 1  
then  
(AL) (AL) – 60H  
(CF) 1  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-11  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
DEC  
Description  
Operation  
(dest) (dest) – 1  
Decrement:  
AF  
CF –  
DF –  
DEC dest  
Subtracts one from the destination  
operand. The operand may be a byte  
or a word and is treated as an  
unsigned binary number (see AAA and  
DAA).  
IF  
OF  
PF  
SF  
TF –  
ZF  
Instruction Operands:  
DEC reg  
DEC mem  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-12  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
DIV  
Description  
Operation  
Divide:  
When Source Operand is a Byte:  
AF ?  
CF ?  
DF –  
IF –  
OF ?  
PF ?  
SF ?  
TF –  
ZF ?  
DIV src  
(temp) (byte-src)  
if  
Performs an unsigned division of the  
accumulator (and its extension) by the  
source operand.  
(temp) / (AX) > FFH  
then (type 0 interrupt is generated)  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
If the source operand is a byte, it is  
divided into the two-byte dividend  
assumed to be in registers AL and AH.  
The byte quotient is returned in AL,  
and the byte remainder is returned in  
AH.  
(TF) 0  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CS)  
(CS) (2)  
If the source operand is a word, it is  
divided into the two-word dividend in  
registers AX and DX. The word  
quotient is returned in AX, and the  
word remainder is returned in DX.  
(SP) (SP) – 2  
((SP) + 1:(SP)) (IP)  
(IP) (0)  
else  
(AL) (temp) / (AX)  
(AH) (temp) % (AX)  
If the quotient exceeds the capacity of  
its destination register (FFH for byte  
source, FFFFH for word source), as  
when division by zero is attempted, a  
type 0 interrupt is generated, and the  
quotient and remainder are undefined.  
Nonintegral quotients are truncated to  
integers.  
When Source Operand is a Word:  
(temp) (word-src)  
if  
(temp) / (DX:AX) > FFFFH  
then (type 0 interrupt is generated)  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
Instruction Operands:  
(TF) 0  
DIV reg  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CS)  
(CS) (2)  
DIV mem  
(SP) (SP) – 2  
((SP) + 1:(SP)) (IP)  
(IP) (0)  
else  
(AX) (temp) / (DX:AX)  
(DX) (temp) % (DX:AX)  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-13  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
ENTER  
Procedure Entry:  
(SP) (SP) – 2  
((SP) + 1:(SP)) (BP)  
(FP) (SP)  
AF –  
CF –  
DF –  
ENTER locals, levels  
Executes the calling sequence for a  
high-level language. It saves the  
current frame pointer in BP, copies the  
frame pointers from procedures below  
the current call (to allow access to  
local variables in these procedures)  
and allocates space on the stack for  
the local variables of the current  
procedure invocation.  
if  
IF  
level > 0  
then  
OF –  
PF –  
SF –  
TF –  
ZF –  
repeat (level – 1) times  
(BP) (BP) – 2  
(SP) (SP) – 2  
((SP) + 1:(SP)) (BP)  
end repeat  
(SP) (SP) – 2  
((SP) + 1:(SP)) (FP)  
end if  
Instruction Operands:  
ENTER locals, level  
(BP) (FP)  
(SP) (SP) – (locals)  
ESC  
Escape:  
if  
AF –  
CF –  
DF –  
mod 11  
then  
ESC  
Provides a mechanism by which other  
processors (coprocessors) may  
receive their instructions from the 8086  
or 8088 instruction stream and make  
use of the 8086 or 8088 addressing  
modes. The CPU (8086 or 8088) does  
a no operation (NOP) for the ESC  
instruction other than to access a  
memory operand and place it on the  
bus.  
data bus (EA)  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
ESC immed, mem  
ESC immed, reg  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-14  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
HLT  
Description  
Operation  
Halt:  
None  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
HLT  
Causes the CPU to enter the halt  
state. The processor leaves the halt  
state upon activation of the RESET  
line, upon receipt of a non-maskable  
interrupt request on NMI, or upon  
receipt of a maskable interrupt request  
on INTR (if interrupts are enabled).  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-15  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
IDIV  
Description  
Integer Divide:  
Operation  
When Source Operand is a Byte:  
AF ?  
CF ?  
DF –  
IDIV src  
(temp) (byte-src)  
if  
Performs a signed division of the  
accumulator (and its extension) by the  
source operand. If the source operand  
is a byte, it is divided into the double-  
length dividend assumed to be in  
registers AL and AH; the single-length  
quotient is returned in AL, and the  
single-length remainder is returned in  
AH. For byte integer division, the  
maximum positive quotient is +127  
(7FH) and the minimum negative  
quotient is –127 (81H).  
IF  
(temp) / (AX) > 0 and  
(temp) / (AX) > 7FH or  
(temp) / (AX) < 0 and  
(temp) / (AX) < 0 – 7FH – 1  
then (type 0 interrupt is generated)  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
OF ?  
PF ?  
SF ?  
TF –  
ZF ?  
(TF) 0  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CS)  
(CS) (2)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (IP)  
(IP) (0)  
If the source operand is a word, it is  
divided into the double-length dividend  
in registers AX and DX; the single-  
length quotient is returned in AX, and  
the single-length remainder is returned  
in DX. For word integer division, the  
maximum positive quotient is +32,767  
(7FFFH) and the minimum negative  
quotient is –32,767 (8001H).  
else  
(AL) (temp) / (AX)  
(AH) (temp) % (AX)  
When Source Operand is a Word:  
(temp) (word-src)  
if  
If the quotient is positive and exceeds  
the maximum, or is negative and is  
less than the minimum, the quotient  
and remainder are undefined, and a  
type 0 interrupt is generated. In  
particular, this occurs if division by 0 is  
attempted. Nonintegral quotients are  
truncated (toward 0) to integers, and  
the remainder has the same sign as  
the dividend.  
(temp) / (DX:AX) > 0 and  
(temp) / (DX:AX) > 7FFFH or  
(temp) / (DX:AX) < 0 and  
(temp) / (DX:AX) < 0 – 7FFFH – 1  
then (type 0 interrupt is generated)  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
(TF) 0  
(SP) (SP) – 2  
Instruction Operands:  
((SP) + 1:(SP)) (CS)  
(CS) (2)  
(SP) (SP) – 2  
IDIV reg  
IDIV mem  
((SP) + 1:(SP)) (IP)  
(IP) (0)  
else  
(AX) (temp) / (DX:AX)  
(DX) (temp) % (DX:AX)  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-16  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
IMUL  
Description  
Integer Multiply:  
Operation  
When Source Operand is a Byte:  
AF ?  
CF  
DF –  
IF –  
OF  
PF ?  
SF ?  
TF –  
ZF ?  
IMUL src  
(AX) (byte-src) × (AL)  
if  
Performs a signed multiplication of the  
source operand and the accumulator.  
If the source is a byte, then it is  
(AH) = sign-extension of (AL)  
then  
(CF) 0  
else  
multiplied by register AL, and the  
double-length result is returned in AH  
and AL. If the source is a word, then it  
is multiplied by register AX, and the  
double-length result is returned in  
registers DX and AX. If the upper half  
of the result (AH for byte source, DX  
for word source) is not the sign  
(CF) 1  
(OF) (CF)  
When Source Operand is a Word:  
(DX:AX) (word-src) × (AX)  
if  
(DX) = sign-extension of (AX)  
extension of the lower half of the  
result, CF and OF are set; otherwise  
they are cleared. When CF and OF are  
set, they indicate that AH or DX  
then  
(CF) 0  
else  
(CF) 1  
(OF) (CF)  
contains significant digits of the result.  
Instruction Operands:  
IMUL reg  
IMUL mem  
IMUL immed  
IN  
Input Byte or Word:  
When Source Operand is a Byte:  
(AL) (port)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
IN accum, port  
Transfers a byte or a word from an  
input port to the AL register or the AX  
register, respectively. The port number  
may be specified either with an  
immediate byte constant, allowing  
access to ports numbered 0 through  
255, or with a number previously  
placed in the DX register, allowing  
variable access (by changing the value  
in DX) to ports numbered from 0  
through 65,535.  
When Source Operand is a Word:  
(AX) (port)  
Instruction Operands:  
IN AL, immed8  
IN AX, DX  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-17  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
INC  
Description  
Operation  
Increment:  
(dest) (dest) + 1  
AF  
CF –  
DF –  
INC dest  
Adds one to the destination operand.  
The operand may be byte or a word  
and is treated as an unsigned binary  
number (see AAA and DAA).  
IF  
OF  
PF  
SF  
Instruction Operands:  
TF –  
ZF  
INC reg  
INC mem  
INS  
In String:  
(dest) (src)  
AF –  
CF –  
DF –  
INS dest-string, port  
Performs block input from an I/O port  
to memory. The port address is placed  
in the DX register. The memory  
address is placed in the DI register.  
This instruction uses the ES register  
(which cannot be overridden). After the  
data transfer takes place, the DI  
register increments or decrements,  
depending on the value of the direction  
flag (DF). The DI register changes by 1  
for byte transfers or 2 for word  
transfers.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
INS dest-string, port  
INS (repeat) dest-string, port  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-18  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
INT  
Description  
Operation  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
(TF) 0  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CS)  
(CS) (interrupt-type × 4 + 2)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (IP)  
(IP) (interrupt-type × 4)  
Interrupt:  
AF –  
CF –  
DF –  
IF  
OF –  
PF –  
SF –  
TF  
INT interrupt-type  
Activates the interrupt procedure  
specified by the interrupt-type  
operand. Decrements the stack pointer  
by two, pushes the flags onto the  
stack, and clears the trap (TF) and  
interrupt-enable (IF) flags to disable  
single-step and maskable interrupts.  
The flags are stored in the format used  
by the PUSHF instruction. SP is  
decremented again by two, and the CS  
register is pushed onto the stack.  
ZF –  
The address of the interrupt pointer is  
calculated by multiplying interrupt-  
type by four; the second word of the  
interrupt pointer replaces CS. SP  
again is decremented by two, and IP is  
pushed onto the stack and is replaced  
by the first word of the interrupt pointer.  
If interrupt-type = 3, the assembler  
generates a short (1 byte) form of the  
instruction, known as the breakpoint  
interrupt.  
Instruction Operands:  
INT immed8  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-19  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
INTO  
Description  
Operation  
Interrupt on Overflow:  
if  
AF –  
CF –  
DF –  
(OF) = 1  
then  
(SP) (SP) – 2  
((SP) + 1:(SP)) FLAGS  
(IF) 0  
INTO  
Generates a software interrupt if the  
overflow flag (OF) is set; otherwise  
control proceeds to the following  
instruction without activating an  
interrupt procedure. INTO addresses  
the target interrupt procedure (its type  
is 4) through the interrupt pointer at  
location 10H; it clears the TF and IF  
flags and otherwise operates like INT.  
INTO may be written following an  
arithmetic or logical operation to  
activate an interrupt procedure if  
overflow occurs.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
(TF) 0  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CS)  
(CS) (12H)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (IP)  
(IP) (10H)  
Instruction Operands:  
none  
IRET  
Interrupt Return:  
IRET  
(IP) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(CS) ((SP) + 1:(SP))  
(SP) (SP) + 2  
FLAGS ((SP) + 1:(SP))  
(SP) (SP) + 2  
AF  
CF  
DF  
IF  
OF  
PF  
SF  
TF  
ZF  
Transfers control back to the point of  
interruption by popping IP, CS, and the  
flags from the stack. IRET thus affects  
all flags by restoring them to previously  
saved values. IRET is used to exit any  
interrupt procedure, whether activated  
by hardware or software.  
Instruction Operands:  
none  
JA  
JNBE  
Jump on Above:  
Jump on Not Below or Equal:  
if  
AF –  
CF –  
DF –  
((CF) = 0) or ((ZF) = 0)  
then  
disp8  
JA  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
JNBE disp8  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition ((CF=0) or  
(ZF=0)) is true.  
Instruction Operands:  
JA short-label  
JNBE short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-20  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
JAE  
Description  
Operation  
Jump on Above or Equal:  
Jump on Not Below:  
if  
AF –  
CF –  
DF –  
JNB  
(CF) = 0  
then  
JAE disp8  
JNB disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition (CF = 0) is true.  
Instruction Operands:  
JAE short-label  
JNB short-label  
JB  
Jump on Below:  
if  
AF –  
JNAE  
Jump on Not Above or Equal:  
(CF) = 1  
then  
CF –  
DF –  
JB disp8  
JNAE disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition (CF = 1) is true.  
Instruction Operands:  
JB short-label  
JNAE short-label  
JBE  
JNA  
Jump on Below or Equal:  
Jump on Not Above:  
if  
AF –  
CF –  
DF –  
((CF) = 1) or ((ZF) = 1)  
then  
JBE disp8  
JNA disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition ((C =1) or  
(ZF=1)) is true.  
Instruction Operands:  
JBE short-label  
JNA short-label  
JC  
Jump on Carry:  
if  
AF –  
(CF) = 1  
then  
CF –  
DF –  
JC disp8  
Transfers control to the target location  
if the tested condition (CF=1) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JC short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-21  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
JCXZ  
Description  
Operation  
Jump if CX Zero:  
if  
AF –  
CF –  
DF –  
(CX) = 0  
then  
JCXZ disp8  
Transfers control to the target location  
if CX is 0. Useful at the beginning of a  
loop to bypass the loop if CX has a  
zero value, i.e., to execute the loop  
zero times.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JCXZ short-label  
JE  
JZ  
Jump on Equal:  
Jump on Zero:  
if  
AF –  
CF –  
DF –  
(ZF) = 1  
then  
JE disp8  
JZ disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the condition tested (ZF = 1) is true.  
Instruction Operands:  
JE short-label  
JZ short-label  
JG  
JNLE  
Jump on Greater Than:  
Jump on Not Less Than or Equal:  
if  
AF –  
CF –  
DF –  
((SF) = (OF)) and ((ZF) = 0)  
then  
JG disp8  
JNLE disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the condition tested (SF = OF) and  
(ZF=0) is true.  
Instruction Operands:  
JG short-label  
JNLE short-label  
JGE  
JNL  
Jump on Greater Than or Equal:  
Jump on Not Less Than:  
if  
AF –  
CF –  
DF –  
(SF) = (OF)  
then  
JGE disp8  
JNL disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the condition tested (SF=OF) is true.  
Instruction Operands:  
JGE short-label  
JNL short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-22  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
JL  
Description  
Jump on Less Than:  
Operation  
if  
AF –  
CF –  
DF –  
JNGE  
Jump on Not Greater Than or Equal:  
(SF) (OF)  
then  
JL disp8  
JNGE disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the condition tested (SFOF) is true.  
Instruction Operands:  
JL short-label  
JNGE short-label  
JLE  
Jump on Less Than or Equal:  
if  
AF –  
JNG  
Jump on Not Greater Than:  
((SF) (OF)) or ((ZF) = 1)  
then  
CF –  
DF –  
JGE disp8  
JNL disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
If the condition tested ((SF OF) or  
(ZF=0)) is true.  
Instruction Operands:  
JGE short-label  
JNL short-label  
JMP  
Jump Unconditionally:  
JMP target  
if  
AF –  
Inter-segment  
then  
(CS) SEG  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location.  
Instruction Operands:  
(IP) dest  
JMP short-label  
JMP near-label  
JMP far-label  
JMP memptr  
JMP regptr  
JNC  
Jump on Not Carry:  
if  
AF –  
CF –  
DF –  
(CF) = 0  
JNC disp8  
then  
Transfers control to the target location  
if the tested condition (CF=0) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JNC short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-23  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
JNE  
Description  
Operation  
Jump on Not Equal:  
Jump on Not Zero:  
if  
AF –  
CF –  
DF –  
JNZ  
(ZF) = 0  
then  
JNE disp8  
JNZ disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition (ZF = 0) is true.  
Instruction Operands:  
JNE short-label  
JNZ short-label  
JNO  
Jump on Not Overflow:  
if  
AF –  
CF –  
DF –  
(OF) = 0  
then  
JNO disp8  
Transfers control to the target location  
if the tested condition (OF = 0) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JNO short-label  
JNS  
Jump on Not Sign:  
if  
AF –  
CF –  
DF –  
(SF) = 0  
then  
JNS disp8  
Transfers control to the target location  
if the tested condition (SF = 0) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JNS short-label  
JNP  
JPO  
Jump on Not Parity:  
Jump on Parity Odd:  
if  
AF –  
CF –  
DF –  
(PF) = 0  
then  
JNO disp8  
JPO disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition (PF=0) is true.  
Instruction Operands:  
JNO short-label  
JPO short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-24  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
JO  
Description  
Jump on Overflow:  
Operation  
if  
AF –  
CF –  
DF –  
(OF) = 1  
then  
JO disp8  
Transfers control to the target location  
if the tested condition (OF = 1) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
JO short-label  
JP  
Jump on Parity:  
if  
AF –  
JPE  
Jump on Parity Equal:  
(PF) = 1  
then  
CF –  
DF –  
JP disp8  
JPE disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Transfers control to the target location  
if the tested condition (PF = 1) is true.  
Instruction Format:  
JP short-label  
JPE short-label  
JS  
Jump on Sign:  
if  
AF –  
(SF) = 1  
then  
CF –  
DF –  
JS disp8  
Transfers control to the target location  
if the tested condition (SF = 1) is true.  
(IP) (IP) + disp8 (sign-ext to 16 bits) IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Format:  
JS short-label  
LAHF  
Load Register AH From Flags:  
(AH) (SF):(ZF):X:(AF):X:(PF):X:(CF)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
LAHF  
Copies SF, ZF, AF, PF and CF (the  
8080/8085 flags) into bits 7, 6, 4, 2 and  
0, respectively, of register AH. The  
content of bits 5, 3, and 1 are  
undefined. LAHF is provided primarily  
for converting 8080/8085 assembly  
language programs to run on an 8086  
or 8088.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-25  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
LDS  
Description  
Operation  
Load Pointer Using DS:  
(dest) (EA)  
AF –  
CF –  
DF –  
(DS) (EA + 2)  
LDS dest, src  
Transfers a 32-bit pointer variable from  
the source operand, which must be a  
memory operand, to the destination  
operand and register DS. The offset  
word of the pointer is transferred to the  
destination operand, which may be  
any 16-bit general register. The  
segment word of the pointer is  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
transferred to register DS.  
Instruction Operands:  
LDS reg16, mem32  
Load Effective Address:  
LEA dest, src  
LEA  
(dest) EA  
AF –  
CF –  
DF –  
Transfers the offset of the source  
operand (rather than its value) to the  
destination operand.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
LEA reg16, mem16  
LEAVE  
Leave:  
(SP) (BP)  
(BP) ((SP) + 1:(SP))  
(SP) (SP) + 2  
AF –  
CF –  
DF –  
LEAVE  
Reverses the action of the most recent  
ENTER instruction. Collapses the last  
stack frame created. First, LEAVE  
copies the current BP to the stack  
pointer releasing the stack space  
allocated to the current procedure.  
Second, LEAVE pops the old value of  
BP from the stack, to return to the  
calling procedure's stack frame. A  
return (RET) instruction will remove  
arguments stacked by the calling  
procedure for use by the called  
procedure.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-26  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
LES  
Description  
Operation  
Load Pointer Using ES:  
(dest) (EA)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
(ES) (EA + 2)  
LES dest, src  
Transfers a 32-bit pointer variable from  
the source operand to the destination  
operand and register ES. The offset  
word of the pointer is transferred to the  
destination operand. The segment  
word of the pointer is transferred to  
register ES.  
Instruction Operands:  
LES reg16, mem32  
Lock the Bus:  
LOCK  
LOCK  
none  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Causes the 8088 (configured in  
maximum mode) to assert its bus  
LOCK signal while the following  
instruction executes. The instruction  
most useful in this context is an  
exchange register with memory.  
The LOCK prefix may be combined  
with the segment override and/or REP  
prefixes.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-27  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
LODS  
Description  
Operation  
Load String (Byte or Word):  
When Source Operand is a Byte:  
AF –  
CF –  
DF –  
LODS src-string  
(AL) (src-string)  
if  
Transfers the byte or word string  
element addressed by SI to register AL  
or AX and updates SI to point to the  
next element in the string. This  
instruction is not ordinarily repeated  
since the accumulator would be  
overwritten by each repetition, and  
only the last element would be  
retained.  
IF  
(DF) = 0  
OF –  
PF –  
SF –  
TF –  
ZF –  
then  
(SI) (SI) + DELTA  
else  
(SI) (SI) – DELTA  
When Source Operand is a Word:  
(AX) (src-string)  
if  
Instruction Operands:  
(DF) = 0  
then  
LODS src-string  
(SI) (SI) + DELTA  
else  
LODS (repeat) src-string  
(SI) (SI) – DELTA  
LOOP  
Loop:  
(CX) (CX) – 1  
AF –  
CF –  
DF –  
if  
LOOP disp8  
(CX) 0  
then  
Decrements CX by 1 and transfers  
control to the target location if CX is  
not 0; otherwise the instruction  
following LOOP is executed.  
IF  
(IP) (IP) + disp8 (sign-ext to 16 bits) OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
LOOP short-label  
LOOPE  
LOOPZ  
Loop While Equal:  
Loop While Zero:  
(CX) (CX) – 1  
AF –  
CF –  
DF –  
if  
(ZF) = 1 and (CX) 0  
then  
(IP)(IP) + disp8 (sign-ext to 16 bits)  
LOOPE disp8  
LOOPZ disp8  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Decrements CX by 1 and transfers  
control is to the target location if CX is  
not 0 and if ZF is set; otherwise the  
next sequential instruction is executed.  
Instruction Operands:  
LOOPE short-label  
LOOPZ short-label  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-28  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
LOOPNE Loop While Not Equal:  
LOOPNZ Loop While Not Zero:  
(CX) (CX) – 1  
if  
(ZF) = 0 and (CX) 0  
then  
AF –  
CF –  
DF –  
IF –  
LOOPNE disp8  
LOOPNZ disp8  
(IP) (IP) + disp8 (sign-ext to 16 bits) OF –  
Decrements CX by 1 and transfers  
PF –  
SF –  
TF –  
ZF –  
control to the target location if CX is  
not 0 and if ZF is clear; otherwise the  
next sequential instruction is executed.  
Instruction Operands:  
LOOPNE short-label  
LOOPNZ short-label  
MOV  
Move (Byte or Word):  
(dest)(src)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
MOV dest, src  
Transfers a byte or a word from the  
source operand to the destination  
operand.  
Instruction Operands:  
MOV mem, accum  
MOV accum, mem  
MOV reg, reg  
MOV reg, mem  
MOV mem, reg  
MOV reg, immed  
MOV mem, immed  
MOV seg-reg, reg16  
MOV seg-reg, mem16  
MOV reg16, seg-reg  
MOV mem16, seg-reg  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-29  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
MOVS  
Move String:  
(dest-string) (src-string)  
AF –  
CF –  
DF –  
MOVS dest-string, src-string  
Transfers a byte or a word from the  
source string (addressed by SI) to the  
destination string (addressed by DI)  
and updates SI and DI to point to the  
next string element. When used in  
conjunction with REP, MOVS  
performs a memory-to-memory block  
transfer.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
MOVS dest-string, src-string  
MOVS (repeat) dest-string, src-string  
MUL  
Multiply:  
When Source Operand is a Byte:  
AF ?  
CF  
DF –  
MUL src  
(AX) (AL) × (src)  
if  
(AH) = 0  
then  
(CF) 0  
else  
(CF) 1  
(OF) (CF)  
Performs an unsigned multiplication of  
the source operand and the accumu-  
lator. If the source is a byte, then it is  
multiplied by register AL, and the  
double-length result is returned in AH  
and AL. If the source operand is a  
word, then it is multiplied by register  
AX, and the double-length result is  
returned in registers DX and AX. The  
operands are treated as unsigned  
binary numbers (see AAM). If the  
upper half of the result (AH for byte  
source, DX for word source) is non-  
zero, CF and OF are set; otherwise  
they are cleared.  
IF  
OF  
PF ?  
SF ?  
TF –  
ZF ?  
When Source Operand is a Word:  
(DX:AX) (AX) × (src)  
if  
(DX) = 0  
then  
(CF) 0  
else  
(CF) 1  
(OF) (CF)  
Instruction Operands:  
MUL reg  
MUL mem  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-30  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
NEG  
Description  
Operation  
Negate:  
When Source Operand is a Byte:  
AF  
CF  
NEG dest  
(dest) FFH – (dest)  
(dest) (dest) + 1 (affecting flags)  
DF –  
IF –  
OF  
PF  
SF  
Subtracts the destination operand,  
which may be a byte or a word, from 0 When Source Operand is a Word:  
and returns the result to the desti-  
nation. This forms the two's  
complement of the number, effectively  
reversing the sign of an integer. If the  
operand is zero, its sign is not  
(dest) FFFFH – (dest)  
(dest) (dest) + 1 (affecting flags)  
TF –  
ZF  
changed. Attempting to negate a byte  
containing –128 or a word containing –  
32,768 causes no change to the  
operand and sets OF.  
Instruction Operands:  
NEG reg  
NEG mem  
NOP  
No Operation:  
NOP  
None  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Causes the CPU to do nothing.  
Instruction Operands:  
none  
NOT  
Logical Not:  
When Source Operand is a Byte:  
(dest) FFH – (dest)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
NOT dest  
Inverts the bits (forms the one's  
complement) of the byte or word  
operand.  
When Source Operand is a Word:  
(dest) FFFFH – (dest)  
Instruction Operands:  
NOT reg  
NOT mem  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-31  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
OR  
Description  
Operation  
Logical OR:  
(dest) (dest) or (src)  
(CF) 0  
AF ?  
CF  
DF –  
OR dest,src  
(OF) 0  
Performs the logical "inclusive or" of  
the two operands (bytes or words) and  
returns the result to the destination  
operand. A bit in the result is set if  
either or both corresponding bits in the  
original operands are set; otherwise  
the result bit is cleared.  
IF  
OF  
PF  
SF  
TF –  
ZF  
Instruction Operands:  
OR reg, reg  
OR reg, mem  
OR mem, reg  
OR accum, immed  
OR reg, immed  
OR mem, immed  
OUT  
Output:  
(dest) (src)  
AF –  
CF –  
DF –  
OUT port, accumulator  
Transfers a byte or a word from the AL  
register or the AX register, respec-  
tively, to an output port. The port  
number may be specified either with  
an immediate byte constant, allowing  
access to ports numbered 0 through  
255, or with a number previously  
placed in register DX, allowing variable  
access (by changing the value in DX)  
to ports numbered from 0 through  
65,535.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
OUT immed8, AL  
OUT DX, AX  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-32  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
OUTS  
Description  
Operation  
Out String:  
(dst) (src)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
OUTS port, src_string  
Performs block output from memory to  
an I/O port. The port address is placed  
in the DX register. The memory  
address is placed in the SI register.  
This instruction uses the DS segment  
register, but this may be changed with  
a segment override instruction. After  
the data transfer takes place, the  
pointer register (SI) increments or  
decrements, depending on the value  
of the direction flag (DF). The pointer  
register changes by 1 for byte  
transfers or 2 for word transfers.  
Instruction Operands:  
OUTS port, src_string  
OUTS (repeat) port, src_string  
POP  
Pop:  
(dest) ((SP) + 1:(SP))  
(SP) (SP) + 2  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
POP dest  
Transfers the word at the current top of  
stack (pointed to by SP) to the  
destination operand and then  
increments SP by two to point to the  
new top of stack.  
Instruction Operands:  
POP reg  
POP seg-reg (CS illegal)  
POP mem  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-33  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
POPA  
Description  
Operation  
Pop All:  
(DI) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(SI) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(BP) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(BX) ((SP) + 1:(SP))  
(SP) (SP) + 2  
AF –  
CF –  
DF –  
POPA  
Pops all data, pointer, and index  
registers off of the stack. The SP value  
popped is discarded.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
none  
(DX) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(CX) ((SP) + 1:(SP))  
(SP) (SP) + 2  
(AX) ((SP) + 1:(SP))  
(SP) (SP) + 2  
POPF  
Pop Flags:  
Flags ((SP) + 1:(SP))  
(SP) (SP) + 2  
AF  
CF  
DF  
IF  
OF  
PF  
SF  
TF  
ZF  
POPF  
Transfers specific bits from the word at  
the current top of stack (pointed to by  
register SP) into the 8086/8088 flags,  
replacing whatever values the flags  
previously contained. SP is then  
incremented by two to point to the new  
top of stack.  
Instruction Operands:  
none  
PUSH  
Push:  
(SP) (SP) – 2  
((SP) + 1:(SP)) (src)  
AF –  
CF –  
DF –  
PUSH src  
Decrements SP by two and then  
transfers a word from the source  
operand to the top of stack now  
pointed to by SP.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
PUSH reg  
PUSH seg-reg (CS legal)  
PUSH mem  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-34  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
PUSHA  
Push All:  
temp (SP)  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
(SP) (SP) – 2  
PUSHA  
((SP) + 1:(SP)) (AX)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (CX)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (DX)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (BX)  
(SP) (SP) – 2  
Pushes all data, pointer, and index  
registers onto the stack . The order in  
which the registers are saved is: AX,  
CX, DX, BX, SP, BP, SI, and DI. The  
SP value pushed is the SP value  
before the first register (AX) is pushed.  
Instruction Operands:  
((SP) + 1:(SP)) (temp)  
(SP) (SP) – 2  
none  
((SP) + 1:(SP)) (BP)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (SI)  
(SP) (SP) – 2  
((SP) + 1:(SP)) (DI)  
PUSHF  
Push Flags:  
(SP) (SP) – 2  
((SP) + 1:(SP)) Flags  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
PUSHF  
Decrements SP by two and then  
transfers all flags to the word at the top  
of stack pointed to by SP.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-35  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
RCL  
Description  
Operation  
Rotate Through Carry Left:  
(temp) count  
do while (temp) 0  
(tmpcf) (CF)  
(CF) high-order bit of (dest)  
(dest) (dest) × 2 + (tmpcf)  
AF –  
CF  
DF –  
RCL dest, count  
Rotates the bits in the byte or word  
destination operand to the left by the  
number of bits specified in the count  
operand. The carry flag (CF) is treated  
as "part of" the destination operand;  
that is, its value is rotated into the low-  
order bit of the destination, and itself is  
replaced by the high-order bit of the  
destination.  
IF  
OF  
(temp) (temp) – 1  
PF –  
SF –  
TF –  
ZF –  
if  
count = 1  
then  
if  
high-order bit of (dest) (CF)  
then  
Instruction Operands:  
(OF) 1  
else  
RCL reg, n  
(OF) 0  
else  
(OF) undefined  
RCL mem, n  
RCL reg, CL  
RCL mem, CL  
RCR  
Rotate Through Carry Right:  
(temp) count  
AF –  
CF  
DF –  
do while (temp) 0  
RCR dest, count  
(tmpcf) (CF)  
Operates exactly like RCL except that  
the bits are rotated right instead of left.  
(CF) low-order bit of (dest)  
IF  
(dest) (dest) / 2  
OF  
Instruction Operands:  
high-order bit of (dest) (tmpcf)  
PF –  
SF –  
TF –  
ZF –  
(temp) (temp) – 1  
RCR reg, n  
if  
RCR mem, n  
RCR reg, CL  
RCR mem, CL  
count = 1  
then  
if  
high-order bit of (dest) ≠  
next-to-high-order bit of (dest)  
then  
(OF) 1  
else  
(OF) 0  
else  
(OF) undefined  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-36  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
REP  
REPE  
REPZ  
Description  
Operation  
Repeat:  
do while (CX)  
0
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Repeat While Equal:  
Repeat While Zero:  
Repeat While Not Equal:  
Repeat While Not Zero:  
service pending interrupts (if any)  
execute primitive string  
Operation in succeeding byte  
(CX) (CX) – 1  
REPNE  
REPNZ  
if  
Controls subsequent string instruction  
repetition. The different mnemonics  
are provided to improve program  
clarity.  
primitive operation is CMPB,  
CMPW, SCAB, or SCAW and  
(ZF)  
then  
exit from while loop  
≠ 0  
REP is used in conjunction with the  
MOVS (Move String) and STOS (Store  
String) instructions and is interpreted  
as "repeat while not end-of-string" (CX  
not 0).  
REPE and REPZ operate identically  
and are physically the same prefix byte  
as REP. These instructions are used  
with the CMPS (Compare String) and  
SCAS (Scan String) instructions and  
require ZF (posted by these instruc-  
tions) to be set before initiating the  
next repetition.  
REPNE and REPNZ are mnemonics  
for the same prefix byte. These  
instructions function the same as  
REPE and REPZ except that the zero  
flag must be cleared or the repetition is  
terminated. ZF does not need to be  
initialized before executing the  
repeated string instruction.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-37  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
RET  
Description  
Operation  
Return:  
(IP) ((SP) = 1:(SP))  
(SP) (SP) + 2  
if  
AF –  
CF –  
DF –  
RET optional-pop-value  
Transfers control from a procedure  
back to the instruction following the  
CALL that activated the procedure.  
The assembler generates an intra-  
segment RET if the programmer has  
defined the procedure near, or an  
intersegment RET if the procedure has  
been defined as far. RET pops the  
word at the top of the stack (pointed to  
by register SP) into the instruction  
pointer and increments SP by two. If  
RET is intersegment, the word at the  
new top of stack is popped into the CS  
register, and SP is again incremented  
by two. If an optional pop value has  
been specified, RET adds that value to  
SP.  
inter-segment  
then  
(CS) ((SP) + 1:(SP))  
(SP) (SP) + 2  
if  
add immed8 to SP  
then  
(SP) (SP) + data  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
RET immed8  
ROL  
Rotate Left:  
(temp) count  
AF –  
CF  
DF –  
do while (temp) 0  
ROL dest, count  
(CF) high-order bit of (dest)  
(dest) (dest) × 2 + (CF)  
Rotates the destination byte or word  
left by the number of bits specified in  
the count operand.  
IF  
(temp) (temp) – 1  
OF  
if  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
count = 1  
then  
if  
high-order bit of (dest) (CF)  
then  
ROL reg, n  
ROL mem, n  
ROL reg, CL  
ROL mem CL  
(OF) 1  
else  
(OF) 0  
else  
(OF) undefined  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-38  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
ROR  
Description  
Rotate Right:  
Operation  
(temp) count  
do while (temp) 0  
AF –  
CF  
DF –  
IF –  
OF  
PF –  
SF –  
TF –  
ZF –  
ROR dest, count  
(CF) low-order bit of (dest)  
Operates similar to ROL except that  
the bits in the destination byte or word  
are rotated right instead of left.  
(dest) (dest) / 2  
high-order bit of (dest) (CF)  
(temp) (temp) – 1  
Instruction Operands:  
if  
count = 1  
ROR reg, n  
then  
ROR mem, n  
ROR reg, CL  
ROR mem, CL  
if  
high-order bit of (dest) ≠  
next-to-high-order bit of (dest)  
then  
(OF) 1  
else  
(OF) 0  
else  
(OF) undefined  
SAHF  
Store Register AH Into Flags:  
(SF):(ZF):X:(AF):X:(PF):X:(CF) (AH)  
AF  
CF  
SAHF  
DF –  
IF –  
OF –  
PF  
Transfers bits 7, 6, 4, 2, and 0 from  
registerAH intoSF, ZF, AF, PF,andCF,  
respectively, replacing whatever  
values these flags previously had.  
SF  
Instruction Operands:  
TF –  
ZF  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-39  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
Description  
Operation  
SHL  
SAL  
Shift Logical Left:  
Shift Arithmetic Left:  
(temp) count  
do while (temp)  
AF ?  
CF  
0
(CF) high-order bit of (dest)  
DF –  
SHL dest, count  
SAL dest, count  
(dest) (dest) × 2  
IF  
(temp) (temp) – 1  
OF  
PF  
SF  
TF –  
ZF  
Shifts the destination byte or word left  
by the number of bits specified in the  
count operand. Zeros are shifted in on  
the right. If the sign bit retains its  
original value, then OF is cleared.  
if  
count = 1  
then  
if  
high-order bit of (dest) (CE)  
then  
(OF) 1  
else  
(OF) 0  
else  
Instruction Operands:  
SHL reg, n  
SHL mem, n  
SHL reg, CL  
SAL reg, n  
SAL mem, n  
SAL reg, CL  
SHL mem, CL SAL mem, CL  
(OF) undefined  
SAR  
Shift Arithmetic Right:  
(temp) count  
AF ?  
CF  
DF –  
do while (temp) 0  
SAR dest, count  
(CF) low-order bit of (dest)  
(dest) (dest) / 2  
Shifts the bits in the destination  
operand (byte or word) to the right by  
the number of bits specified in the  
count operand. Bits equal to the  
original high-order (sign) bit are shifted  
in on the left, preserving the sign of the  
original value. Note that SAR does not  
produce the same result as the  
dividend of an "equivalent" IDIV  
instruction if the destination operand is  
negative and 1 bits are shifted out. For  
example, shifting –5 right by one bit  
yields –3, while integer division –5 by 2  
yields –2. The difference in the instruc-  
tions is that IDIV truncates all numbers  
toward zero, while SAR truncates  
positive numbers toward zero and  
negative numbers toward negative  
infinity.  
IF  
(temp) (temp) – 1  
OF  
PF  
SF  
TF –  
ZF  
if  
count = 1  
then  
if  
high-order bit of (dest) ≠  
next-to-high-order bit of (dest)  
then  
(OF) 1  
else  
(OF) 0  
else  
(OF) 0  
Instruction Operands:  
SAR reg, n  
SAR mem, n  
SAR reg, CL  
SAR mem, CL  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-40  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
SBB  
Description  
Operation  
Subtract With Borrow:  
if  
AF  
(CF) = 1  
then  
(dest) = (dest) – (src) – 1  
else  
(dest) (dest) – (src)  
CF  
SBB dest, src  
DF –  
IF –  
OF  
PF  
SF  
Subtracts the source from the desti-  
nation, subtracts one if CF is set, and  
returns the result to the destination  
operand. Both operands may be bytes  
or words. Both operands may be  
signed or unsigned binary numbers  
(see AAS and DAS)  
TF –  
ZF  
Instruction Operands:  
SBB reg, reg  
SBB reg, mem  
SBB mem, reg  
SBB accum, immed  
SBB reg, immed  
SBB mem, immed  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-41  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
SCAS  
Description  
Operation  
Scan String:  
When Source Operand is a Byte:  
AF  
CF  
DF –  
IF  
OF  
PF  
SF  
TF –  
ZF  
SCAS dest-string  
(AL) – (byte-string)  
if  
(DF) = 0  
then  
(DI) (DI) + DELTA  
else  
(DI) (DI) – DELTA  
Subtracts the destination string  
element (byte or word) addressed by  
DI from the content of AL (byte string)  
or AX (word string) and updates the  
flags, but does not alter the destination  
string or the accumulator. SCAS also  
updates DI to point to the next string  
element and AF, CF, OF, PF, SF and  
ZF to reflect the relationship of the  
scan value in AL/AX to the string  
element. If SCAS is prefixed with  
REPE or REPZ, the operation is  
interpreted as "scan while not end-of-  
string (CX not 0) and string-element =  
scan-value (ZF = 1)." This form may be  
used to scan for departure from a  
given value. If SCAS is prefixed with  
REPNE or REPNZ, the operation is  
interpreted as "scan while not end-of-  
string (CX not 0) and string-element is  
not equal to scan-value (ZF = 0)."  
When Source Operand is a Word:  
(AX) – (word-string)  
if  
(DF) = 0  
then  
(DI) (DI) + DELTA  
else  
(DI) (DI) – DELTA  
Instruction Operands:  
SCAS dest-string  
SCAS (repeat) dest-string  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-42  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
SHR  
Description  
Shift Logical Right:  
Operation  
(temp) count  
AF ?  
CF  
DF –  
IF –  
OF  
PF  
SF  
TF –  
ZF  
do while (temp)  
0
SHR dest, src  
(CF) low-order bit of (dest)  
(dest) (dest) / 2  
Shifts the bits in the destination  
operand (byte or word) to the right by  
the number of bits specified in the  
count operand. Zeros are shifted in on  
the left. If the sign bit retains its original  
value, then OF is cleared.  
(temp) (temp) – 1  
if  
count = 1  
then  
if  
Instruction Operands:  
high-order bit of (dest)  
next-to-high-order bit of (dest)  
then  
(OF) 1  
else  
(OF) 0  
else  
SHR reg, n  
SHR mem, n  
SHR reg, CL  
SHR mem, CL  
(OF) undefined  
STC  
Set Carry Flag:  
STC  
(CF) 1  
AF –  
CF  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
Sets CF to 1.  
Instruction Operands:  
none  
STD  
Set Direction Flag:  
(DF) 1  
AF –  
CF –  
DF  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
STD  
Sets DF to 1 causing the string instruc-  
tions to auto-decrement the SI and/or  
DI index registers.  
Instruction Operands:  
none  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-43  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
STI  
Description  
Operation  
Set Interrupt-enable Flag:  
(IF) 1  
AF –  
CF –  
DF –  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
STI  
Sets IF to 1, enabling processor  
recognition of maskable interrupt  
requests appearing on the INTR line.  
Note however, that a pending interrupt  
will not actually be recognized until the  
instruction following STI has executed.  
Instruction Operands:  
none  
STOS  
Store (Byte or Word) String:  
STOS dest-string  
When Source Operand is a Byte:  
AF –  
CF –  
DF –  
(DEST) (AL)  
if  
(DF) = 0  
then  
(DI) (DI) + DELTA  
else  
(DI) (DI) – DELTA  
Transfers a byte or word from register  
AL or AX to the string element  
addressed by DI and updates DI to  
point to the next location in the string.  
As a repeated operation.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
When Source Operand is a Word:  
STOS dest-string  
STOS (repeat) dest-string  
(DEST) (AX)  
if  
(DF) = 0  
then  
(DI) (DI) + DELTA  
else  
(DI) (DI) – DELTA  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-44  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
SUB  
Description  
Operation  
(dest) (dest) – (src)  
Subtract:  
AF  
CF  
DF –  
IF –  
OF  
PF  
SF  
TF –  
ZF  
SUB dest, src  
The source operand is subtracted from  
the destination operand, and the result  
replaces the destination operand. The  
operands may be bytes or words. Both  
operands may be signed or unsigned  
binary numbers (see AAS and DAS).  
Instruction Operands:  
SUB reg, reg  
SUB reg, mem  
SUB mem, reg  
SUB accum, immed  
SUB reg, immed  
SUB mem, immed  
TEST  
Test:  
(dest) and (src)  
(CF ) 0  
(OF) 0  
AF ?  
CF  
DF –  
IF –  
OF  
PF  
SF  
TF –  
ZF  
TEST dest, src  
Performs the logical "and" of the two  
operands (bytes or words), updates  
the flags, but does not return the  
result, i.e., neither operand is  
changed. If a TEST instruction is  
followed by a JNZ (jump if not zero)  
instruction, the jump will be taken if  
there are any corresponding one bits  
in both operands.  
Instruction Operands:  
TEST reg, reg  
TEST reg, mem  
TEST accum, immed  
TEST reg, immed  
TEST mem, immed  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-45  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
WAIT  
Description  
Operation  
Wait:  
None  
AF –  
CF –  
DF –  
WAIT  
Causes the CPU to enter the wait state  
while its test line is not active.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
none  
XCHG  
Exchange:  
(temp) (dest)  
(dest) (src)  
(src) (temp)  
AF –  
CF –  
DF –  
XCHG dest, src  
Switches the contents of the source  
and destination operands (bytes or  
words). When used in conjunction with  
the LOCK prefix, XCHG can test and  
set a semaphore that controls access  
to a resource shared by multiple  
processors.  
IF  
OF –  
PF –  
SF –  
TF –  
ZF –  
Instruction Operands:  
XCHG accum, reg  
XCHG mem, reg  
XCHG reg, reg  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-46  
INSTRUCTION SET DESCRIPTIONS  
Table C-4. Instruction Set (Continued)  
Flags  
Affected  
Name  
XLAT  
Description  
Operation  
AL ((BX) + (AL))  
Translate:  
AF –  
CF –  
DF –  
IF –  
OF –  
PF –  
SF –  
TF –  
ZF –  
XLAT translate-table  
Replaces a byte in the AL register with  
a byte from a 256-byte, user-coded  
translation table. Register BX is  
assumed to point to the beginning of  
the table. The byte in AL is used as an  
index into the table and is replaced by  
the byte at the offset in the table corre-  
sponding to AL's binary value. The first  
byte in the table has an offset of 0. For  
example, if AL contains 5H, and the  
sixth element of the translation table  
contains 33H, then AL will contain 33H  
following the instruction. XLAT is  
useful for translating characters from  
one code to another, the classic  
example being ASCII to EBCDIC or  
the reverse.  
Instruction Operands:  
XLAT src-table  
XOR  
Exclusive Or:  
(dest) (dest) xor (src)  
(CF) 0  
(OF) 0  
AF ?  
CF  
DF –  
IF –  
OF  
PF  
SF  
TF –  
ZF  
XOR dest, src  
Performs the logical "exclusive or" of  
the two operands and returns the  
result to the destination operand. A bit  
in the result is set if the corresponding  
bits of the original operands contain  
opposite values (one is set, the other  
is cleared); otherwise the result bit is  
cleared.  
Instruction Operands:  
XOR reg, reg  
XOR reg, mem  
XOR mem, reg  
XOR accum, immed  
XOR reg, immed  
XOR mem, immed  
NOTE: The three symbols used in the Flags Affected column are defined as follows:  
– the contents of the flag remain unchanged after the instruction is executed  
? the contents of the flag is undefined after the instruction is executed  
the flag is updated after the instruction is executed  
C-47  
D
Instruction Set  
Opcodes and Clock  
Cycles  
APPENDIX D  
INSTRUCTION SET OPCODES  
This appendix provides reference information for the 80C186 Modular Core family instruction  
set. Table D-1 defines the variables used in Table D-2, which lists the instructions with their for-  
mats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is  
a guide for encoding instruction mnemonics, and Table D-5 defines Table D-4 abbreviations.  
Table D-1. Operand Variables  
Variable  
Description  
mod  
r/m  
mod and r/m determine the Effective Address (EA).  
r/m and mod determine the Effective Address (EA).  
reg represents a register.  
reg  
MMM  
PPP  
TTT  
MMM and PPP are opcodes to the math coprocessor.  
PPP and MMM are opcodes to the math coprocessor.  
TTT defines which shift or rotate instruction is executed.  
r/m  
EA Calculation  
mod  
Effect on EA Calculation  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
(BX) + (SI) + DISP  
(BX) + (DI) + DISP  
0 0  
0 0  
0 1  
1 0  
1 1  
if r/m 110, DISP = 0; disp-low and disp-high are absent  
if r/m = 110, EA = disp-high:disp-low  
(BP) + (SI) + DISP  
(BP) + (DI) + DISP  
(SI) + DISP  
DISP = disp-low, sign-extended to 16 bits; disp-high is absent  
DISP = disp-high:disp-low  
r/m is treated as a reg field  
(DI) + DISP  
DISP follows the second byte of the instruction (before any required data).  
(BP) + DISP, if mod 00  
Physical addresses of operands addressed by the BP register are computed  
using the SS segment register. Physical addresses of destination operands of  
string primitives (addressed by the DI register) are computed using the ES seg-  
ment register, which cannot be overridden.  
disp-high:disp-low, if mod =00  
1 1 1  
(BX) + DISP  
reg  
16-bit (w=1)  
8-bit (w=0)  
TTT  
Instruction  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
AX  
CX  
DX  
BP  
SP  
BP  
SI  
AL  
CL  
DL  
BL  
AH  
CH  
DH  
BH  
0 0 0  
ROL  
ROR  
RCL  
RCR  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
SHL/SAL  
SHR  
DI  
SAR  
D-1  
 
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary  
Function  
Format  
Clocks  
Notes  
DATA TRANSFER INSTRUCTIONS  
MOV = Move  
register to register/memory  
1 0 0 0 1 0 0 w  
1 0 0 0 1 0 1 w  
1 1 0 0 0 1 1 w  
1 0 1 1 w reg  
1 0 1 0 0 0 0 w  
1 0 1 0 0 0 1 w  
1 0 0 0 1 1 1 0  
1 0 0 0 1 1 0 0  
mod reg r/m  
2/12  
2/9  
12/13  
3/4  
9
register/memory to register  
immediate to register/memory  
immediate to register  
mod reg r/m  
mod 000 r/m  
data  
data  
data if w=1  
(1)  
(1)  
data if w=1  
addr-high  
addr-high  
memory to accumulator  
addr-low  
accumulator to memory  
addr-low  
8
register/memory to segment register  
segment register to register/memory  
mod 0 reg r/m  
mod 0 reg r/m  
2/9  
2/11  
PUSH = Push  
memory  
1 1 1 1 1 1 1 1  
0 1 0 1 0 reg  
0 0 0 reg 1 1 0  
0 1 1 0 1 0 s 0  
mod 110 r/m  
16  
10  
9
register  
segment register  
immediate  
data  
data if s=0  
10  
POP = Pop  
memory  
1 0 0 0 1 1 1 1  
0 1 0 1 1 reg  
0 0 0 reg 1 1 1  
0 1 1 0 0 0 0 0  
0 1 1 0 0 0 0 1  
mod 000 r/m  
(reg ?01)  
20  
10  
8
register  
segment register  
PUSHA = Push all  
36  
51  
POPA = Pop all  
XCHG = Exchange  
register/memory with register  
1 0 0 0 0 1 1 w  
1 0 0 1 0 reg  
1 1 0 1 0 1 1 1  
mod reg r/m  
4/17  
3
register with accumulator  
XLAT = Translate byte to AL  
11  
IN = Input from  
fixed port  
1 1 1 0 0 1 0 w  
1 1 1 0 1 1 0 w  
port  
port  
10  
8
variable port  
OUT = Output from  
fixed port  
1 1 1 0 0 1 0 w  
1 1 1 0 1 1 0 w  
9
7
variable port  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-2  
 
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
DATA TRANSFER INSTRUCTIONS (Continued)  
LEA = Load EA to register  
LDS = Load pointer to DS  
LES = Load pointer to ES  
1 0 0 0 1 1 0 1  
mod reg r/m  
6
1 1 0 0 0 1 0 1  
1 1 0 0 0 1 0 0  
1 1 0 0 1 0 0 0  
mod reg r/m  
mod reg r/m  
data-low  
(mod ?11)  
(mod ?11)  
data-high  
18  
18  
ENTER = Build stack frame  
L
L = 0  
15  
L = 1  
L > 1  
25  
22+16(n-1)  
LEAVE = Tear down stack frame  
LAHF = Load AH with flags  
SAHF = Store AH into flags  
PUSHF = Push flags  
1 1 0 0 1 0 0 1  
1 0 0 1 1 1 1 1  
1 0 0 1 1 1 1 0  
1 0 0 1 1 1 0 0  
1 0 0 1 1 1 0 1  
8
2
3
9
8
POPF = Pop flags  
ARITHMETIC INSTRUCTIONS  
ADD = Add  
reg/memory with register to either  
0 0 0 0 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 0 0 1 0 w  
mod reg r/m  
mod 000 r/m  
data  
3/10  
4/16  
3/4  
immediate to register/memory  
immediate to accumulator  
data  
data if sw=01  
data if sw=01  
data if w=1  
(1)  
(1)  
ADC = Add with carry  
reg/memory with register to either  
0 0 0 1 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 0 1 0 w  
mod reg r/m  
mod 010 r/m  
data  
3/10  
4/16  
3/4  
immediate to register/memory  
immediate to accumulator  
data  
data if w=1  
INC = Increment  
register/memory  
1 1 1 1 1 1 1 w  
0 1 0 0 0 reg  
0 0 1 1 0 1 1 1  
0 0 1 0 0 1 1 1  
mod 000 r/m  
3/15  
register  
3
8
4
AAA = ASCII adjust for addition  
DAA = Decimal adjust for addition  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-3  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
ARITHMETIC INSTRUCTIONS (Continued)  
SUB = Subtract  
reg/memory with register to either  
0 0 1 0 1 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 1 1 0 w  
mod reg r/m  
3/10  
4/16  
3/4  
immediate from register/memory  
immediate from accumulator  
mod 101 r/m  
data  
data  
data if sw=01  
data if sw=01  
data if w=1  
(1)  
(1)  
SBB = Subtract with borrow  
reg/memory with register to either  
0 0 0 1 1 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 1 1 0 w  
mod reg r/m  
mod 011 r/m  
data  
3/10  
4/16  
3/4  
immediate from register/memory  
immediate from accumulator  
data  
data if w=1  
DEC = Decrement  
register/memory  
1 1 1 1 1 1 1 w  
0 1 0 0 1 reg  
1 1 1 1 0 1 1 w  
mod 001 r/m  
mod reg r/m  
3/15  
3
register  
NEG = Change sign  
3
CMP = Compare  
register/memory with register  
0 0 1 1 1 0 1 w  
0 0 1 1 1 0 0 w  
1 0 0 0 0 0 s w  
0 0 1 1 1 1 0 w  
0 0 1 1 1 1 1 1  
0 0 1 0 1 1 1 1  
1 1 1 1 0 1 1 w  
mod reg r/m  
mod reg r/m  
mod 111 r/m  
data  
3/10  
3/10  
3/10  
3/4  
7
register with register/memory  
immediate with register/memory  
immediate with accumulator  
data  
data if sw=01  
data if w=1  
(1)  
AAS = ASCII adjust for subtraction  
DAS = Decimal adjust for subtraction  
4
MUL = multiply (unsigned)  
mod 100 r/m  
mod 101 r/m  
mod reg r/m  
register-byte  
26-28  
35-37  
32-34  
41-43  
register-word  
memory-byte  
memory-word  
IMUL = Integer multiply (signed)  
1 1 1 1 0 1 1 w  
register-byte  
25-28  
34-37  
31-34  
40-43  
22-25/  
29-32  
register-word  
memory-byte  
memory-word  
integer immediate multiply (signed)  
0 1 1 0 1 0 s 1  
data  
data if s=0  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-4  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
ARITHMETIC INSTRUCTIONS (Continued)  
AAM = ASCII adjust for multiply  
1 1 0 1 0 1 0 0  
1 1 1 1 0 1 1 w  
0 0 0 0 1 0 1 0  
19  
DIV = Divide (unsigned)  
mod 110 r/m  
mod 111 r/m  
0 0 0 0 1 0 1 0  
mod 010 r/m  
register-byte  
29  
38  
35  
44  
register-word  
memory-byte  
memory-word  
IDIV = Integer divide (signed)  
1 1 1 1 0 1 1 w  
register-byte  
29  
38  
35  
44  
15  
2
register-word  
memory-byte  
memory-word  
AAD = ASCII adjust for divide  
CBW = Convert byte to word  
1 1 0 1 0 1 0 1  
1 0 0 1 1 0 0 0  
1 0 0 1 1 0 0 1  
CWD = Convert word to double-word  
4
BIT MANIPULATION INSTRUCTIONS  
NOT= Invert register/memory  
1 1 1 1 0 1 1 w  
3
AND = And  
reg/memory and register to either  
0 0 1 0 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 0 0 1 0 w  
mod reg r/m  
mod 100 r/m  
data  
3/10  
4/16  
3/4  
immediate to register/memory  
immediate to accumulator  
data  
data if w=1  
data if w=1  
(1)  
OR = Or  
reg/memory and register to either  
0 0 0 0 1 0 d w  
1 0 0 0 0 0 0 w  
0 0 0 0 1 1 0 w  
mod reg r/m  
mod 001 r/m  
data  
3/10  
4/10  
3/4  
immediate to register/memory  
immediate to accumulator  
data  
data if w=1  
data if w=1  
data if w=1  
(1)  
(1)  
XOR = Exclusive or  
reg/memory and register to either  
0 0 1 1 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 1 0 1 0 w  
mod reg r/m  
mod 110 r/m  
data  
3/10  
4/10  
3/4  
immediate to register/memory  
immediate to accumulator  
data  
data if w=1  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-5  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
BIT MANIPULATION INSTRUCTIONS (Continued)  
TEST= And function to flags, no result  
register/memory and register  
1 0 0 0 0 1 0 w  
mod reg r/m  
3/10  
4/10  
3/4  
immediate data and register/memory  
immediate data and accumulator  
1 1 1 1 0 1 1 w  
1 0 1 0 1 0 0 w  
mod 000 r/m  
data  
data  
data if w=1  
data if w=1  
(1)  
Shifts/Rotates  
register/memory by 1  
1 1 0 1 0 0 0 w  
1 1 0 1 0 0 1 w  
1 1 0 0 0 0 0 w  
mod TTT r/m  
mod TTT r/m  
mod TTT r/m  
2/15  
register/memory by CL  
5+n/17+n  
5+n/17+n  
register/memory by Count  
count  
STRING MANIPULATION INSTRUCTIONS  
MOVS = Move byte/word  
1 0 1 0 0 1 0 w  
0 1 1 0 1 1 0 w  
0 1 1 0 1 1 1 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
14  
14  
14  
22  
15  
INS = Input byte/word from DX port  
OUTS = Output byte/word to DX port  
CMPS = Compare byte/word  
SCAS = Scan byte/word  
STRING MANIPULATION INSTRUCTIONS (Continued)  
LODS = Load byte/word to AL/AX  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
12  
10  
STOS = Store byte/word from AL/AX  
Repeated by count in CX:  
MOVS = Move byte/word  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 0  
1 1 1 1 0 1 0 0  
1 0 1 0 0 1 0 w  
0 1 1 0 1 1 0 w  
0 1 1 0 1 1 1 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
0 1 0 1 0 0 1 w  
0 1 0 1 0 0 1 w  
8+8n  
8-8n  
INS = Input byte/word from DX port  
OUTS = Output byte/word to DX port  
CMPS = Compare byte/word  
SCAS = Scan byte/word  
8+8n  
5+22n  
5+15n  
6+11n  
6+9n  
LODS = Load byte/word to AL/AX  
STOS = Store byte/word from AL/AX  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-6  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
PROGRAM TRANSFER INSTRUCTIONS  
Conditional Transfers — jump if:  
JE/JZ= equal/zero  
0 1 1 1 0 1 0 0  
0 1 1 1 1 1 0 0  
0 1 1 1 1 1 1 0  
0 1 1 1 0 0 1 0  
0 1 1 1 0 0 1 0  
0 1 1 1 0 1 1 0  
0 1 1 1 1 0 1 0  
0 1 1 1 0 0 0 0  
0 1 1 1 1 0 0 0  
0 1 1 1 0 1 0 1  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
JL/JNGE = less/not greater or equal  
JLE/JNG = less or equal/not greater  
JB/JNAE = below/not above or equal  
JC = carry  
JBE/JNA = below or equal/not above  
JP/JPE = parity/parity even  
JO = overflow  
JS = sign  
JNE/JNZ = not equal/not zero  
JNL/JGE = not less/greater or equal  
JNLE/JG = not less or equal/greater  
JNB/JAE = not below/above or equal  
JNC = not carry  
0 1 1 1 1 1 0 1  
0 1 1 1 1 1 1 1  
0 1 1 1 0 0 1 1  
0 1 1 1 0 0 1 1  
0 1 1 1 0 1 1 1  
0 1 1 1 1 0 1 1  
0 1 1 1 0 0 0 1  
0 1 1 1 1 0 0 1  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
5/15  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
(2)  
JNBE/JA = not below or equal/above  
JNP/JPO = not parity/parity odd  
JNO = not overflow  
JNS = not sign  
Unconditional Transfers  
CALL = Call procedure  
direct within segment  
1 1 1 0 1 0 0 0  
1 1 1 1 1 1 1 1  
1 1 1 1 1 1 1 1  
1 0 0 1 1 0 1 0  
disp-low  
disp-high  
15  
13/19  
38  
reg/memory indirect within segment  
indirect intersegment  
mod 010 r/m  
mod 011 r/m  
segment offset  
selector  
(mod ?11)  
direct intersegment  
23  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-7  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
PROGRAM TRANSFER INSTRUCTIONS (Continued)  
RET = Return from procedure  
within segment  
1 1 0 0 0 0 1 1  
16  
18  
22  
25  
within segment adding immed to SP  
1 1 0 0 0 0 1 0  
data-low  
data-low  
data-high  
intersegment  
1 1 0 0 1 0 1 1  
intersegment adding immed to SP  
1 1 0 0 1 0 1 0  
data-high  
JMP = Unconditional jump  
short/long  
1 1 1 0 1 0 1 1  
1 1 1 0 1 0 0 1  
1 1 1 1 1 1 1 1  
1 1 1 1 1 1 1 1  
1 1 1 0 1 0 1 0  
disp-low  
14  
14  
direct within segment  
disp-low  
disp-high  
reg/memory indirect within segment  
indirect intersegment  
mod 100 r/m  
mod 101 r/m  
segment offset  
selector  
26  
(mod ?11)  
11/17  
14  
direct intersegment  
Iteration Control  
LOOP = Loop CX times  
1 1 1 0 0 0 1 0  
disp  
disp  
disp  
6/16  
5/16  
5/16  
(2)  
(2)  
(2)  
LOOPZ/LOOPE =Loop while zero/equal 1 1 1 0 0 0 0 1  
LOOPNZ/LOOPNE =  
1 1 1 0 0 0 0 0  
Loop while not zero/not equal  
JCXZ = Jump if CX = zero  
1 1 1 0 0 0 1 1  
disp  
6/16  
(2)  
Interrupts  
INT = Interrupt  
Type specified  
1 1 0 0 1 1 0 1  
1 1 0 0 1 1 0 0  
1 1 0 0 1 1 1 0  
0 1 1 0 0 0 1 0  
1 1 0 0 1 1 1 1  
type  
47  
45  
Type 3  
INTO = Interrupt on overflow  
BOUND = Detect value out of range  
IRET = Interrupt return  
48/4  
33-35  
28  
(3)  
mod reg r/m  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
D-8  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-2. Instruction Set Summary (Continued)  
Function  
Format  
Clocks  
Notes  
PROCESSOR CONTROL INSTRUCTIONS  
CLC = Clear carry  
1 1 1 1 1 0 0 0  
1 1 1 1 0 1 0 1  
1 1 1 1 1 0 0 1  
1 1 1 1 1 1 0 0  
1 1 1 1 1 1 0 1  
1 1 1 1 1 0 1 0  
1 1 1 1 1 0 1 1  
1 1 1 1 0 1 0 0  
1 0 0 1 1 0 1 1  
1 1 1 1 0 0 0 0  
1 1 0 1 1 M M M  
1 0 0 1 0 0 0 0  
2
2
2
2
2
2
2
2
6
2
6
3
CMC = Complement carry  
STC = Set carry  
CLD = Clear direction  
STD = Set direction  
CLI = Clear interrupt  
STI = Set interrupt  
HLT = Halt  
WAIT = Wait  
(4)  
LOCK = Bus lock prefix  
ESC = Math coprocessor escape  
NOP = No operation  
mod PPP r/m  
SEGMENT OVERRIDE PREFIX  
CS  
0 0 1 0 1 1 1 0  
0 0 1 1 0 1 1 0  
0 0 1 1 1 1 1 0  
0 0 1 0 0 1 1 0  
2
2
2
2
SS  
DS  
ES  
NOTES:  
1. Clock cycles are given for 8-bit/16-bit operations.  
2. Clock cycles are given for jump not taken/jump taken.  
3. Clock cycles are given for interrupt taken/interrupt not taken.  
4. If TEST = 0  
Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186  
Instruction Set Additions and Extensions,” for details.  
Table D-3. Machine Instruction Decoding Guide  
Byte 1  
Byte 2  
Bytes 3–6  
(disp-lo),(disp-hi)  
ASM-86 Instruction Format  
Hex  
00  
Binary  
0000 0000  
0000 0001  
0000 0010  
0000 0011  
0000 0100  
0000 0101  
0000 0110  
0000 0111  
0000 0100  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
add  
add  
add  
add  
add  
add  
push  
pop  
or  
reg8/mem8, reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
01  
02  
03  
04  
05  
06  
07  
08  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
data-lo  
data-hi  
AX,immed16  
ES  
ES  
mod reg r/m  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
D-9  
 
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
(disp-lo),(disp-hi)  
ASM-86 Instruction Format  
Hex  
09  
0000 1001  
0000 1010  
0000 1011  
0000 1100  
0000 1101  
0000 1110  
0000 1111  
0001 0000  
0001 0001  
0001 0010  
0001 0011  
0001 0100  
0001 0101  
0001 0110  
0001 0111  
0001 1000  
0001 1001  
0001 1010  
0001 1011  
0001 1100  
0001 1101  
0001 1110  
0001 1111  
0010 0000  
0010 0001  
0010 0010  
0010 0011  
0010 0100  
0010 0101  
0010 0110  
0010 0111  
0010 1000  
0010 1001  
0010 1010  
0010 1011  
0010 1100  
0010 1101  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
or  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL, immed8  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
or  
or  
or  
data-lo  
data-hi  
or  
AX,immed16  
CS  
push  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
adc  
adc  
adc  
adc  
adc  
adc  
push  
pop  
sbb  
sbb  
sbb  
sbb  
sbb  
sbb  
push  
pop  
and  
and  
and  
and  
and  
and  
ES:  
daa  
sub  
sub  
sub  
sub  
sub  
sub  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
data-lo  
data-hi  
AX,immed16  
SS  
SS  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
data-lo  
data-hi  
AX,immed16  
DS  
DS  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
data-lo  
data-hi  
AX,immed16  
(segment override prefix)  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
data-lo  
data-hi  
AX,immed16  
D-10  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
2E  
0010 1110  
0010 1111  
0011 0000  
0011 0001  
0011 0010  
0011 0011  
0011 0100  
0011 0101  
0011 0110  
0011 0111  
0011 1000  
0011 1001  
0011 1010  
0011 1011  
0011 1100  
0011 1101  
0011 1110  
0011 1111  
0100 0000  
0100 0001  
0100 0010  
0100 0011  
0100 0100  
0100 0101  
0100 0110  
0100 0111  
0100 1000  
0100 1001  
0100 1010  
0100 1011  
0100 1100  
0100 1101  
0100 1110  
0100 1111  
0101 0000  
0101 0001  
0101 0010  
DS:  
das  
xor  
xor  
xor  
xor  
xor  
xor  
SS:  
aaa  
xor  
xor  
xor  
xor  
xor  
xor  
DS:  
aas  
inc  
(segment override prefix)  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
data-lo  
data-hi  
AX,immed16  
(segment override prefix)  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
data-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg8/mem8,reg8  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
AL,immed8  
data-lo  
data-hi  
AX,immed16  
(segment override prefix)  
AX  
CX  
DX  
BX  
SP  
BP  
SI  
inc  
inc  
inc  
inc  
inc  
inc  
inc  
DI  
dec  
dec  
dec  
dec  
dec  
dec  
dec  
dec  
push  
push  
push  
AX  
CX  
DX  
BX  
SP  
BP  
SI  
DI  
AX  
CX  
DX  
D-11  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
53  
0101 0011  
0101 0100  
0101 0101  
0101 0110  
0101 0111  
0101 1000  
0101 1001  
0101 1010  
0101 1011  
0101 1100  
0101 1101  
0101 1110  
0101 1111  
0110 0000  
0110 0001  
0110 0010  
0110 0011  
0110 0100  
0110 0101  
0110 0110  
0110 0111  
0110 1000  
0110 1001  
0111 0000  
0111 0001  
0111 0010  
0111 0011  
0111 0100  
0111 0101  
0111 0110  
0111 0111  
0111 1000  
0111 1001  
0111 1010  
0111 1011  
0111 1100  
0111 1101  
push  
push  
push  
push  
push  
pop  
pop  
pop  
pop  
pop  
pop  
pop  
pop  
pusha  
popa  
bound  
BX  
SP  
BP  
SI  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
DI  
AX  
CX  
DX  
BX  
SP  
BP  
SI  
DI  
mod reg r/m  
reg16,mem16  
data-lo  
data-hi  
data-lo, data-hi  
push  
imul  
jo  
immed16  
immed16  
short-label  
short-label  
short-label  
mod reg r/m  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
IP-inc-8  
jno  
jb/jnae/jc  
jnb/jae/jnc  
je/jz  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
short-label  
jne/jnz  
jbe/jna  
jnbe/ja  
js  
jns  
jp/jpe  
jnp/jpo  
jl/jnge  
jnl/jge  
D-12  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
IP-inc-8  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
7E  
0111 1110  
0111 1111  
1000 0000  
jle/jng  
jnle/jg  
add  
or  
short-label  
7F  
80  
IP-inc-8  
short-label  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
(disp-lo),(disp-hi), data-8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg8/mem8,immed8  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg16/mem16,immed16  
reg8/mem8,immed8  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
adc  
sbb  
and  
sub  
xor  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
cmp  
add  
or  
81  
1000 0001  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-lo,data-hi  
(disp-lo),(disp-hi), data-8  
adc  
sbb  
and  
sub  
xor  
81  
82  
1000 0001  
1000 0010  
cmp  
add  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-8  
adc  
sbb  
reg8/mem8,immed8  
reg8/mem8,immed8  
(disp-lo),(disp-hi), data-8  
sub  
reg8/mem8,immed8  
(disp-lo),(disp-hi), data-8  
(disp-lo),(disp-hi), data-SX  
cmp  
add  
reg8/mem8,immed8  
83  
1000 0011  
reg16/mem16,immed8  
(disp-lo),(disp-hi), data-SX  
(disp-lo),(disp-hi), data-SX  
adc  
sbb  
reg16/mem16,immed8  
reg16/mem16,immed8  
(disp-lo),(disp-hi), data-SX  
sub  
reg16/mem16,immed8  
(disp-lo),(disp-hi), data-SX  
(disp-lo),(disp-hi)  
cmp  
test  
test  
xchg  
reg16/mem16,immed8  
reg8/mem8,reg8  
84  
85  
86  
1000 0100  
1000 0101  
1000 0110  
(disp-lo),(disp-hi)  
reg16/mem16,reg16  
reg8,reg8/mem8  
(disp-lo),(disp-hi)  
D-13  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
(disp-lo),(disp-hi)  
ASM-86 Instruction Format  
Hex  
87  
1000 0111  
1000 0100  
1000 1001  
1000 1010  
1000 1011  
1000 1100  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod reg r/m  
mod OSR r/m  
mod 1 - r/m  
mod reg r/m  
mod OSR r/m  
mod 1 - r/m  
xchg  
mov  
mov  
mov  
mov  
mov  
reg16,reg16/mem16  
reg8/mem8,reg8  
88  
89  
8A  
8B  
8C  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg16/mem16,reg16  
reg8,reg8/mem8  
reg16,reg16/mem16  
reg16/mem16,SEGREG  
8D  
8E  
1000 1101  
1000 1110  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
lea  
reg16,mem16  
mov  
SEGREG,reg16/mem16  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
1000 1111  
1001 0000  
1001 0001  
1001 0010  
1001 0011  
1001 0100  
1001 0101  
1001 0110  
1001 0111  
1001 1000  
1001 1001  
1001 1010  
1001 1011  
1001 1100  
1001 1101  
1001 1110  
1001 1111  
1010 0000  
1010 0001  
1010 0010  
1010 0011  
1010 0100  
1010 0101  
1010 0110  
1010 0111  
1010 1000  
1010 1001  
pop  
mem16  
(xchg AX,AX)  
AX,CX  
AX,DX  
AX,BX  
nop  
xchg  
xchg  
xchg  
xchg  
xchg  
xchg  
xchg  
cbw  
cwd  
call  
AX,SP  
AX,BP  
AX,SI  
AX,DI  
disp-lo  
disp-hi,seg-lo,seg-hi  
far-proc  
wait  
pushf  
popf  
sahf  
lahf  
addr-lo  
addr-lo  
addr-lo  
addr-lo  
addr-hi  
addr-hi  
addr-hi  
addr-hi  
mov  
mov  
mov  
mov  
movs  
movs  
cmps  
cmps  
test  
AL,mem8  
AX,mem16  
mem8,AL  
mem16,AL  
dest-str8,src-str8  
dest-str16,src-str16  
dest-str8,src-str8  
dest-str16,src-str16  
AL,immed8  
data-8  
data-lo  
data-hi  
test  
AX,immed16  
D-14  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
AA  
1010 1010  
1010 1011  
1010 1100  
1010 1101  
1010 1110  
1010 1111  
1011 0000  
1011 0001  
1011 0010  
1011 0011  
1011 0100  
1011 0101  
1011 0110  
1011 0111  
1011 1000  
1011 1001  
1011 1010  
1011 1011  
1011 1100  
1011 1101  
1011 1110  
1011 1111  
1100 0000  
stos  
stos  
lods  
lods  
scas  
scas  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
mov  
rol  
dest-str8  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
C0  
dest-str16  
src-str8  
src-str16  
dest-str8  
dest-str16  
data-8  
AL,immed8  
data-8  
CL,immed8  
data-8  
DL,immed8  
data-8  
BL,immed8  
data-8  
AH,immed8  
data-8  
CH,immed8  
data-8  
DH,immed8  
data-8  
BH,immed8  
data-lo  
data-hi  
data-hi  
data-hi  
data-hi  
data-hi  
data-hi  
data-hi  
data-hi  
data-8  
data-8  
data-8  
data-8  
data-8  
data-8  
AX,immed16  
CX,immed16  
DX,immed16  
BX,immed16  
SP,immed16  
BP,immed16  
SI,immed16  
data-lo  
data-lo  
data-lo  
data-lo  
data-lo  
data-lo  
data-lo  
DI,immed16  
reg8/mem8, immed8  
reg8/mem8, immed8  
reg8/mem8, immed8  
reg8/mem8, immed8  
reg8/mem8, immed8  
reg8/mem8, immed8  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
ror  
rcl  
rcr  
shl/sal  
shr  
data-8  
data-8  
data-8  
data-8  
data-8  
data-8  
data-8  
sar  
reg8/mem8, immed8  
C1  
1100 0001  
rol  
reg16/mem16, immed8  
reg16/mem16, immed8  
reg16/mem16, immed8  
reg16/mem16, immed8  
reg16/mem16, immed8  
reg16/mem16, immed8  
ror  
rcl  
rcr  
shl/sal  
shr  
D-15  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
mod 111 r/m  
data-lo  
data-8  
data-hi  
sar  
ret  
ret  
les  
lds  
mov  
reg16/mem16, immed8  
immed16 (intrasegment)  
(intrasegment)  
C2  
1100 0010  
1100 0011  
1100 0100  
1100 0101  
1100 0110  
C3  
C4  
C5  
C6  
mod reg r/m  
mod reg r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
data-lo  
(disp-lo),(disp-hi)  
reg16,mem16  
(disp-lo),(disp-hi)  
reg16,mem16  
(disp-lo),(disp-hi),data-8  
mem8,immed8  
C6  
C7  
1100 0110  
1100 0111  
(disp-lo),(disp-hi),data-lo,data-hi  
mov  
mem16,immed16  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
1100 1000  
1100 1001  
1100 1010  
1100 1011  
1100 1100  
1100 1101  
1100 1110  
1100 1111  
1101 0000  
data-hi, level  
data-hi  
enter  
leave  
ret  
immed16, immed8  
data-lo  
data-8  
immed16 (intersegment)  
ret  
int  
(intersegment)  
3
int  
immed8  
into  
iret  
rol  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
reg8/mem8,1  
reg8/mem8,1  
reg8/mem8,1  
reg8/mem8,1  
reg8/mem8,1  
reg8/mem8,1  
ror  
rcl  
rcr  
sal/shl  
shr  
(disp-lo),(disp-hi)  
sar  
reg8/mem8,1  
D-16  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
(disp-lo),(disp-hi)  
ASM-86 Instruction Format  
Hex  
D1  
1101 0001  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
0000 1010  
rol  
reg16/mem16,1  
reg16/mem16,1  
reg16/mem16,1  
reg16/mem16,1  
reg16/mem16,1  
reg16/mem16,1  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
ror  
D1  
1101 0001  
rcl  
rcr  
sal/shl  
shr  
(disp-lo),(disp-hi)  
sar  
rol  
reg16/mem16,1  
reg8/mem8,CL  
reg8/mem8,CL  
reg8/mem8,CL  
reg8/mem8,CL  
reg8/mem8,CL  
reg8/mem8,CL  
D2  
1101 0010  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
ror  
rcl  
rcr  
sal/shl  
shr  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
sar  
rol  
reg8/mem8,CL  
D3  
1101 0011  
reg16/mem16,CL  
reg16/mem16,CL  
reg16/mem16,CL  
reg16/mem16,CL  
reg16/mem16,CL  
reg16/mem16,CL  
ror  
rcl  
rcr  
sal/shl  
shr  
(disp-lo),(disp-hi)  
sar  
aam  
aad  
reg16/mem16,CL  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
1101 0100  
1101 0101  
1101 0110  
1101 0111  
1101 1000  
1101 1001  
1101 1010  
1101 1011  
1101 1100  
1101 1101  
1101 1110  
1101 1111  
1110 0000  
0000 1010  
xlat  
esc  
esc  
esc  
esc  
esc  
esc  
esc  
esc  
source-table  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
IP-inc-8  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
opcode,source  
opcode,source  
opcode,source  
opcode,source  
opcode,source  
opcode,source  
opcode,source  
opcode,source  
loopne/loopnz  
short-label  
D-17  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
IP-inc-8  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
E1  
1110 0001  
1110 0010  
1110 0011  
1110 0100  
1110 0101  
1110 0110  
1110 0111  
1110 1000  
1110 1001  
1110 1010  
1110 1011  
1110 1100  
1110 1101  
1110 1110  
1110 1111  
1111 0000  
1111 0001  
1111 0010  
1111 0011  
1111 0100  
1111 0101  
1111 0110  
loope/loopz  
short-label  
short-label  
short-label  
AL,immed8  
AX,immed8  
AL,immed8  
AX,immed8  
near-proc  
near-label  
far-label  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
IP-inc-8  
IP-inc-8  
data-8  
data-8  
loop  
jcxz  
in  
in  
data-8  
data-8  
IP-inc-lo  
IP-inc-lo  
IP-lo  
out  
out  
IP-inc-hi  
IP-inc-hi  
call  
jmp  
jmp  
jmp  
in  
IP-hi,CS-lo,CS-hi  
IP-inc-8  
short-label  
AL,DX  
in  
AX,DX  
out  
AL,DX  
out  
AX,DX  
lock  
(prefix)  
repne/repnz  
rep/repe/repz  
hlt  
cmc  
test  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
(disp-lo),(disp-hi),data-8  
reg8/mem8,immed8  
(disp-lo),(disp-hi)  
not  
reg8/mem8  
(disp-lo),(disp-hi)  
neg  
mul  
imul  
div  
reg8/mem8  
(disp-lo),(disp-hi)  
reg8/mem8  
(disp-lo),(disp-hi)  
reg8/mem8  
(disp-lo),(disp-hi)  
reg8/mem8  
(disp-lo),(disp-hi)  
idiv  
test  
reg8/mem8  
F7  
1111 0111  
(disp-lo),(disp-hi),data-lo,data-hi  
reg16/mem16,immed16  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
not  
reg16/mem16  
reg16/mem16  
reg16/mem16  
reg16/mem16  
reg16/mem16  
reg16/mem16  
neg  
mul  
imul  
div  
idiv  
D-18  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-3. Machine Instruction Decoding Guide (Continued)  
Byte 1  
Binary  
Byte 2  
Bytes 3–6  
ASM-86 Instruction Format  
Hex  
F8  
1111 1000  
1111 1001  
1111 1010  
1111 1011  
1111 1100  
1111 1101  
1111 1110  
clc  
stc  
cli  
F9  
FA  
FB  
FC  
FD  
FE  
sti  
cld  
std  
inc  
dec  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
(disp-lo),(disp-hi)  
mem16  
mem16  
(disp-lo),(disp-hi)  
FE  
1111 1110  
FF  
1111 1111  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
(disp-lo),(disp-hi)  
inc  
dec  
call  
call  
jmp  
jmp  
push  
mem16  
mem16  
reg16/mem16 (intrasegment)  
mem16 (intersegment)  
reg16/mem16 (intrasegment)  
mem16 (intersegment)  
mem16  
D-19  
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-4. Mnemonic Encoding Matrix (Left Half)  
x0  
x1  
x2  
x3  
x4  
x5  
x6  
x7  
ADD  
ADD  
ADD  
ADD  
ADD  
ADD  
PUSH  
POP  
0x  
1x  
2x  
3x  
4x  
5x  
6x  
7x  
8x  
9x  
Ax  
Bx  
Cx  
Dx  
Ex  
Fx  
b,f,r/m  
ADC  
w,f,r/m  
ADC  
b,t,r/m  
ADC  
w,t,r/m  
ADC  
b,ia  
ADC  
w,ia  
ADC  
ES  
PUSH  
ES  
POP  
b,f,r/m  
AND  
w,f,r/m  
AND  
b,t,r/m  
AND  
w,t,r/m  
AND  
b,i  
AND  
w,i  
AND  
SS  
SEG  
SS  
DAA  
b,f,r/m  
XOR  
w,f,r/m  
XOR  
b,t,r/m  
XOR  
w,t,r/m  
XOR  
b,i  
XOR  
w,i  
XOR  
=ES  
SEG  
AAA  
INC  
b,f,r/m  
INC  
w,f,r/m  
INC  
b,t,r/m  
INC  
w,t,r/m  
INC  
b,i  
INC  
w,i  
INC  
=SS  
INC  
AX  
PUSH  
CX  
PUSH  
DX  
PUSH  
BX  
PUSH  
SP  
PUSH  
BP  
PUSH  
SI  
PUSH  
DI  
PUSH  
AX  
PUSHA  
CX  
POPA  
DX  
BOUND  
BX  
SP  
BP  
SI  
DI  
w,f,r/m  
JB/  
JNAE/  
JC  
JO  
JNO  
JNB/  
JAE/  
JNC  
JE/  
JZ  
JNE/  
JNZ  
JBE/  
JNA  
JNBE/  
JA  
Immed  
Immed  
Immed  
Immed  
TEST  
TEST  
XCHG  
XCHG  
b,r/m  
NOP  
(XCHG)  
AX  
w,r/m  
XCHG  
b,r/m  
XCHG  
is,r/m  
XCHG  
b,r/m  
XCHG  
w,r/m  
XCHG  
b,r/m  
XCHG  
w,r/m  
XCHG  
CX  
MOV  
DX  
MOV  
BX  
MOV  
SP  
MOVS  
BP  
MOVS  
SI  
CMPS  
DI  
CMPS  
MOV  
mAL  
MOV  
mAX  
MOV  
ALm  
MOV  
AXm  
MOV  
MOV  
MOV  
MOV  
MOV  
iAL  
Shift  
iCL  
Shift  
iDL  
RET  
iBL  
RET  
iAH  
LES  
iCH  
LDS  
iDH  
MOV  
iBH  
MOV  
b,i  
Shift  
w,i  
Shift  
(i+SP)  
Shift  
b,i,r/m  
OUT  
w,i,r/m  
XLAT  
Shift  
AAM  
IN  
AAD  
IN  
b
w
b,v  
LOOP  
w,v  
JCXZ  
LOOPNZ/  
LOOPNE  
LOOPZ/  
LOOPE  
OUT  
LOCK  
REP  
REP  
z
HLT  
CMC  
Grp1  
b,r/m  
Grp1  
w,r/m  
NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.  
D-20  
 
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-4. Mnemonic Encoding Matrix (Right Half)  
x8  
x9  
xA  
xB  
xC  
xD  
xE  
xF  
OR  
OR  
OR  
OR  
OR  
OR  
PUSH  
0x  
1x  
2x  
3x  
4x  
5x  
6x  
7x  
8x  
9x  
Ax  
Bx  
Cx  
Dx  
Ex  
Fx  
b,f,r/m  
SBB  
w,f,r/m  
SBB  
b,t,r/m  
SBB  
w,t,r/m  
SBB  
b,i  
SBB  
w,i  
SBB  
CS  
PUSH  
POP  
b,f,r/m  
SUB  
w,f,r/m  
SUB  
b,t,r/m  
SUB  
w,t,r/m  
SUB  
b,i  
SUB  
w,i  
SUB  
DS  
SEG  
DS  
DAS  
b,f,r/m  
CMP  
w,f,r/m  
CMP  
b,t,r/m  
CMP  
w,t,r/m  
CMP  
b,i  
CMP  
w,i  
CMP  
=CS  
SEG  
AAS  
DEC  
b,f,r/m  
DEC  
w,f,r/m  
DEC  
b,t,r/m  
DEC  
w,t,r/m  
DEC  
b,i  
DEC  
w,i  
DEC  
=DS  
DEC  
AX  
POP  
CX  
POP  
DX  
POP  
BX  
POP  
SP  
POP  
BP  
POP  
SI  
POP  
DI  
POP  
AX  
PUSH  
CX  
IMUL  
DX  
PUSH  
BX  
IMUL  
SP  
INS  
BP  
INS  
SI  
OUTS  
DI  
OUTS  
w,i  
JS  
w,i  
JNS  
b,i  
JP/  
JPE  
w,i  
JNP/  
JPO  
b
JL/  
JNGE  
w
JNL/  
JGE  
b
JLE/  
JNG  
w
JNLE/  
JG  
MOV  
MOV  
MOV  
MOV  
MOV  
LEA  
POPF  
LODS  
MOV  
MOV  
POP  
b,f,r/m  
CBW  
w,f,r/m  
CWD  
b,t,r/m  
CALL  
w,t,r/m  
WAIT  
sr,f,r/m  
PUSHF  
sr,t,r/m  
SAHF  
r/m  
LAHF  
L,D  
STOS  
TEST  
TEST  
STOS  
MOV  
LODS  
MOV  
SCAS  
MOV  
SCAS  
MOV  
b,ia  
MOV  
w,ia  
MOV  
MOV  
iAX  
ENTER  
iCX  
LEAVE  
iDX  
RET  
iBX  
RET  
iSP  
INT  
iBP  
INT  
iSI  
INTO  
iDI  
IRET  
l(i+SP)  
ESC  
l
type 3  
ESC  
(any)  
ESC  
ESC  
ESC  
ESC  
ESC  
ESC  
0
1
JMP  
2
JMP  
3
JMP  
4
IN  
5
IN  
6
OUT  
7
OUT  
CALL  
CLC  
STC  
CLI  
STI  
CLS  
STD  
Grp2  
b,r/m  
Grp2  
w,r/m  
NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.  
D-21  
 
INSTRUCTION SET OPCODES AND CLOCK CYCLES  
Table D-5. Abbreviations for Mnemonic Encoding Matrix  
Abbr  
Definition  
byte operation  
direct  
Abbr  
ia  
Definition  
immediate to accumulator  
indirect  
Abbr  
m
Definition  
memory  
Abbr  
Definition  
to CPU register  
variable  
b
d
t
id  
r/m  
EA is second byte  
v
f
i
from CPU register  
immediate  
is  
l
immediate byte, sign extended  
long (intersegment)  
si  
short intrasegment  
segment register  
w
z
word operation  
zero  
sr  
Byte 2  
Immed  
Shift  
ROL  
Grp1  
TEST  
Grp2  
INC  
mod 000 r/m  
mod 001 r/m  
mod 010 r/m  
mod 011 r/m  
mod 100 r/m  
mod 101 r/m  
mod 110 r/m  
mod 111 r/m  
ADD  
OR  
ROR  
RCL  
DEC  
ADC  
SBB  
AND  
SUB  
XOR  
CMP  
NOT  
NEG  
MUL  
IMUL  
DIV  
CALL id  
CALL l, id  
JMP id  
JMP i, id  
PUSH  
RCR  
SHL/SAL  
SHR  
SAR  
IDIV  
mod and r/m determine the Effective Address (EA) calculation. See Table D-1 for definitions.  
D-22  
 
Index  
INDEX  
80C187 Math Coprocessor, 10-2–10-8  
accessing, 10-10–10-11  
based index, 2-34, 2-35  
direct, 2-29  
arithmetic instructions, 10-3–10-4  
bus cycles, 10-11  
clocking, 10-10  
immediate operands, 2-28  
indexed, 2-32, 2-33  
indirect, 2-36  
code examples, 10-13–10-16  
comparison instructions, 10-5  
constant instructions, 10-6  
data transfer instructions, 10-3  
data types, 10-7–10-8  
memory operands, 2-28  
register indirect, 2-30, 2-31  
register operands, 2-27  
AH register, 2-5  
AL register, 2-5, 2-18, 2-23  
design considerations, 10-10–10-11  
example floating point routine, 10-16  
exceptions, 10-13  
ApBUILDER files, obtaining from BBS, 1-5  
Application BBS, 1-5  
Architecture  
I/O port assignments, 10-10  
initialization example, 10-13–10-16  
instruction set, 10-2  
CPU block diagram, 2-2  
device feature comparisons, 1-2  
family introduction, 1-1  
interface, 10-7–10-13  
overview, 1-1, 2-1  
and chip-selects, 6-17, 10-11  
and PCB location, 4-7  
ARDY, See READY  
Arithmetic  
exception trapping, 10-13  
generating READY, 10-11  
processor control instructions, 10-6  
testing for presence, 10-10  
transcendental instructions, 10-5  
8259A Programmable Interrupt Controllers, 8-1  
and special fully nested mode, 8-8  
cascading, 8-7, 8-8  
instructions, 2-19–2-20  
interpretation of 8-bit numbers, 2-20  
Arithmetic Logic Unit (ALU), 2-1  
Array bounds trap (Type 5 exception), 2-44  
ASCII, defined, 2-37  
Auxiliary Flag (AF), 2-7, 2-9  
AX register, 2-1, 2-5, 2-18, 2-23, 3-6  
interrupt type, 8-9  
priority structure, 8-8  
B
Base Pointer (BP)‚ See BP register  
BBS, 1-5  
BCD, defined, 2-37  
82C59A Programmable Interrupt Controller  
interfacing with, 3-25–3-27  
Bit manipulation instructions, 2-21–2-22  
BOUND instruction, 2-44, A-8  
BP register, 2-1, 2-13, 2-30, 2-34  
Breakpoint interrupt (Type 3 exception), 2-44  
Bulletin board system (BBS), 1-5  
Bus cycles, 3-20–3-45  
address/status phase, 3-10–3-12  
and 80C187, 10-11  
A
Address and data bus, 3-1–3-6  
16-bit, 3-1–3-5  
considerations, 3-7  
8-bit, 3-5–3-6  
considerations, 3-7  
See also Bus cycles‚ Data transfers  
Address bus, See Address and data bus  
Address space, See Memory space‚ I/O space  
Addressing modes, 2-27–2-36  
and string instructions, 2-34  
based, 2-30, 2-31, 2-32  
and CSU, 6-17  
and PCB accesses, 4-4  
and T-states, 3-9  
data phase, 3-13  
HALT cycle, 3-28–3-33  
Index-1  
INDEX  
and chip-selects, 6-5  
HALT state, exiting, 3-30  
idle states, 3-18  
instruction prefetch, 3-20  
interrupt acknowledge (INTA) cycles, 3-6,  
3-25–3-26, 8-9  
examples, 6-18–6-22  
features and benefits, 6-1  
functional overview, 6-2–6-5  
programming, 6-6–6-17  
registers, 6-6–6-12  
system diagram, 6-19  
See also Chip selects  
and chip-selects, 6-5  
interrupt acknowledge cycles, 8-29  
operation, 3-7–3-20  
Chip-selects  
activating, 6-5  
priorities, 3-44–3-45, 7-2  
read cycles, 3-20–3-21  
refresh cycles, 3-22, 7-4, 7-5  
control signals, 7-5, 7-6  
during HOLD, 3-41–3-43, 7-12–7-13  
wait states, 3-13–3-18  
and 80C187 interface, 6-17, 10-11  
and bus hold protocol, 6-18  
and DMA acknowledge signal, 10-22  
and DRAM controllers, 7-1  
and reserved I/O locations, 6-17  
initializing, 6-6–6-18  
write cycles, 3-22–3-25  
See also Data transfers  
Bus hold protocol, 3-39–3-44  
and CLKOUT, 5-6  
methods for generating, 6-1  
overlapping, 6-16–6-17  
programming considerations, 6-17  
start address, 6-17  
and CSU, 6-18  
timing, 6-4  
and refresh cycles, 3-41–3-43, 7-12–7-13  
and reset, 5-9  
CL register, 2-5, 2-21, 2-22  
CLKOUT  
latency, 3-40–3-41  
and bus hold, 5-6  
Bus Interface Unit (BIU), 2-1, 2-3, 2-11, 3-1–3-45  
and DMA, 10-8  
and power management modes, 5-6  
and reset, 5-6  
and DRAM refresh requests, 7-4  
and TCU, 9-1  
Clock divider, 5-11  
control register, 5-12  
buffering the data bus, 3-34–3-36  
modifying interface, 3-33–3-36, 3-36  
relationship to RCU, 7-1  
synchronizing software and hardware events,  
3-36–3-37  
Clock generator, 5-6–5-10  
and system reset, 5-6–5-7  
output, 5-6  
synchronizing CLKOUT and RESOUT, 5-6–  
5-7  
using a locked bus, 3-37–3-38  
using multiple bus masters, 3-39–3-44  
using the queue status signals, 3-38–3-39  
BX register, 2-1, 2-5, 2-30  
Clock sources, TCU, 9-12  
Code (programs)‚ See Software  
Code segment, 2-5  
CompuServe forums, 1-6  
Counters‚ See Timer Counter Unit (TCU)  
CPU, block diagram, 2-2  
Crystal‚ See Oscillator  
CS register, 2-1, 2-5, 2-6, 2-13, 2-23, 2-39, 2-41  
Customer service, 1-4  
CX register, 2-1, 2-5, 2-23, 2-25, 2-26  
C
Carry Flag (CF), 2-7, 2-9  
Chip-Select Unit (CSU), 6-1  
and DMA, 10-8  
and DMA acknowledge signal, 10-22  
and HALT bus cycles, 3-28  
and READY, 6-15–6-16  
and wait states, 6-15–6-16  
block diagram, 6-3  
D
Data, 3-6  
Data bus, See Address and data bus  
Data segment, 2-5  
bus cycle decoding, 6-17  
Index-2  
INDEX  
Data sheets, obtaining from BBS, 1-5  
Data transfers, 3-1–3-6  
instructions, 2-18  
synchronization  
destination-synchronized, 10-5  
selecting, 10-18  
PCB considerations, 4-5  
PSW flag storage formats, 2-19  
See also Bus cycles  
source-synchronized, 10-5  
unsynchronized, 10-6  
timed DMA transfer example, 10-22–10-27  
transfers, 10-1–10-27  
Data types, 2-37–2-38  
DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,  
2-34  
Digital one-shot, code example, 9-17–9-23  
Direct Memory Access (DMA) Unit, 10-1–10-27  
and BIU, 10-8  
count, 10-7  
programming, 10-18–10-19  
direction, 10-3  
rates, 10-21  
size, 10-3  
and CSU, 10-8  
selecting, 10-14  
and PCB, 10-3  
suspending, 10-7, 10-20  
terminating, 10-7  
Direction Flag (DF), 2-7, 2-9, 2-23  
Display, defined, A-2  
arming channel, 10-18  
DMA acknowledge signal, 10-2, 10-22  
DRQ timing, 10-20  
examples, 10-22–10-27  
HALT bit, 8-22, 8-23, 10-20  
hardware considerations, 10-20–10-22  
initialization code, 10-22–10-27  
initializing, 10-20  
Divide Error trap (Type 0 exception), 2-43  
DMA Control Register (DxCON), 10-15  
DMA Destination Pointer Register, 10-13, 10-14  
DMA Source Pointer Register, 10-11, 10-12  
Documents, related, 1-3  
interrupts, 10-8  
DRAM controllers  
generating on terminal count, 10-19  
introduction, 10-1  
and wait state control, 7-5  
clocked, 7-5  
latency, 10-21  
design guidelines, 7-5  
modules, 10-8–10-9  
unclocked, 7-5  
overview, 10-1–10-10  
pointers, programming, 10-10–10-14  
priority  
See also Refresh Control Unit  
DS register, 2-1, 2-5, 2-6, 2-13, 2-30, 2-34, 2-43  
DX register, 2-1, 2-5, 2-36, 3-6  
channel, 10-8–10-9, 10-19  
fixed, 10-8–10-10  
rotating, 10-10  
E
Effective Address (EA), 2-13  
calculation, 2-28  
Emulation mode, 11-1  
programming, 10-17–10-20  
arming channel, 10-18  
channel priority, 10-19  
initializing, 10-20  
End-of-Interrupt (EOI)  
command, 8-21  
interrupts, 10-19  
register, 8-21, 8-22, 8-27, 8-28  
ENTER instruction, A-2  
ES register, 2-1, 2-5, 2-6, 2-13, 2-30, 2-34  
Escape opcode fault (Type 7 exception), 2-44, 10-2  
Exceptions, 2-43–2-44  
priority, 2-46–2-49  
suspending transfers, 10-20  
synchronization, 10-18  
transfer count, 10-18–10-19  
programming, pointers, 10-10–10-14  
requests, 10-3  
external, 10-4  
internal, 10-6  
Execution Unit (EU), 2-1, 2-2  
Extra segment, 2-5  
software, 10-6  
Timer 2, 10-6  
selecting source, 10-17  
Index-3  
INDEX  
rotate instructions, A-10  
shift instructions, A-9  
string instructions, 2-22–2-23, A-2  
INT instruction, single-byte‚ See Breakpoint  
interrupt  
F
Fault exceptions, 2-43  
FaxBack service, 1-4  
F-Bus  
and PCB, 4-5  
operation, 4-5  
INT0 instruction, 2-44  
INTA bus cycle‚ See Bus cycles  
Integer, defined, 2-37, 10-7  
Interrupt Control register, 8-28  
Interrupt Control registers, 8-12  
for external pins, 8-14, 8-15  
for internal sources, 8-13  
Flags‚ See Processor Status Word (PSW)  
Floating Point, defined, 2-37  
H
HALT bus cycle‚ See Bus cycles  
HOLD/HLDA protocol‚ See Bus hold protocol  
Hypertext manuals, obtaining from BBS, 1-5  
Interrupt Control Unit (ICU), 8-1–8-31  
block diagram, 8-2, 8-24  
cascade mode, 8-7  
initializing, 8-30, 8-31  
I
I/O devices  
interfacing with an 82C59A Programmable  
Interrupt Controller, 3-25–3-27  
master mode, 8-1, 8-2–8-23  
initializing, 8-30  
operation in slave mode, 8-29  
operation with nesting, 8-4  
programming, 8-11, 8-25  
interfacing with, 3-6–3-7  
memory-mapped, 3-6  
I/O ports  
addressing, 2-36  
I/O space, 3-1–3-7  
accessing, 3-6  
reserved locations, 2-15, 6-17  
Idle states  
registers, 8-11, 8-25  
master mode, 8-11  
and bus cycles, 3-18  
slave mode, 8-1, 8-23–8-30  
special fully nested mode, 8-8  
with cascade mode, 8-8  
Immediate operands, 2-28  
IMUL instruction, A-9  
Inputs, asynchronous, synchronizing, B-1  
INS instruction, A-2  
In-Service register, 8-5, 8-7, 8-18, 8-19, 8-28  
Instruction Pointer (IP), 2-1, 2-6, 2-13, 2-23, 2-39,  
2-41  
without cascade mode, 8-8  
typical interrupt sequence, 8-5  
Interrupt Enable Flag (IF), 2-7, 2-9, 2-41  
Interrupt Mask register, 8-16, 8-17, 8-28  
Interrupt Request register, 8-16, 8-28  
Interrupt Status register, 8-7, 8-22, 8-23, 8-28  
Interrupt Vector register, 8-26, 8-27  
Interrupt Vector Table, 2-39, 2-40  
Interrupt-on-overflow trap (Type 4 exception),  
2-44  
reset status, 2-6  
Instruction prefetch bus cycle‚ See Bus cycles  
Instruction set, 2-17, A-1, D-1  
additions, A-1  
arithmetic instructions, 2-19–2-20, A-9  
bit manipulation instructions, 2-21–2-22, A-9  
data transfer instructions, 2-18–2-20, A-1,  
A-8  
data types, 2-37–2-38  
enhancements, A-8  
high-level instructions, A-2  
nesting, A-2  
processor control instructions, 2-27  
program transfer instructions, 2-23–2-24  
reentrant procedures, A-2  
Interrupts, 2-39–2-43  
and CSU initialization, 6-6  
controlling priority, 8-12  
edge- and level-sensitive, 8-10  
and external 8259As, 8-10  
enabling cascade mode, 8-12  
enabling special fully nested mode, 8-12  
latency, 2-45  
reducing, 3-28  
latency and response times, 8-10, 8-11, 8-30  
Index-4  
INDEX  
maskable, 2-43  
masking, 8-3, 8-12, 8-16  
priority-based, 8-17  
logical, 2-10, 2-12  
offset value, 2-10, 2-13  
overriding, 2-11, 2-13  
multiplexed, 8-7  
nesting, 8-4  
NMI, 2-42  
physical, 2-3, 2-10, 2-12  
and dynamic code relocation, 2-13  
Memory space, 3-1–3-6  
nonmaskable, 2-45  
overview, 8-1, 8-2  
priority, 2-46–2-49, 8-3  
default, 8-3  
resolution, 8-5, 8-6  
processing, 2-39–2-42  
reserved, 2-39  
N
Normally not-ready signal‚ See Ready  
Normally ready signal‚ See Ready  
Numerics coprocessor fault (Type 16 exception),  
2-44, 10-13  
response time, 2-46  
O
selecting edge- or level-triggering, 8-12  
slave mode sources, 8-25  
software, 2-45  
ONCE mode, 11-1  
One-shot, code example, 9-17–9-23  
Ordinal, defined, 2-37  
Oscillator  
timer interrupts, 9-16  
types, 8-9, 8-26, 8-27  
See also Exceptions, Interrupt Control Unit  
INTn instruction, 2-45  
Invalid opcode trap (Type 6 exception), 2-44  
IRET instruction, 2-41  
external  
selecting crystal, 5-5  
using canned, 5-6  
internal crystal, 5-1–5-10  
operation, 5-2–5-3  
selecting C and L components, 5-3–  
1
1
L
5-6  
Latency‚ See Bus hold protocol‚ Direct Memory  
Access (DMA) Unit‚ Interrupts  
LEAVE instruction, A-7  
Local bus, 3-1, 3-39, 10-11  
Long integer, defined, 10-7  
Long real, defined, 10-7  
OUTS instruction, A-2  
Overflow Flag (OF), 2-7, 2-9, 2-44  
P
Packed BCD, defined, 2-37  
Packed decimal, defined, 10-7  
Parity Flag (PF), 2-7, 2-9  
PCB Relocation Register, 4-1, 4-3, 4-6  
and math coprocessing, 10-2  
Peripheral Control Block (PCB), 4-1  
accessing, 4-4  
M
Manuals, online, 1-5  
Math coprocessing, 10-1  
hardware support, 10-1  
overview, 10-1  
and DMA Unit, 10-3  
and F-Bus operation, 4-5  
base address, 4-6–4-7  
Memory  
addressing, 2-28–2-36  
operands, 2-28  
bus cycles, 4-4  
reserved locations, 2-15  
Memory devices‚ interfacing with, 3-6–3-7  
Memory segments, 2-8  
accessing, 2-5, 2-10, 2-11, 2-13  
address  
READY signals, 4-4  
reserved locations, 4-6  
wait states, 4-4  
Peripheral control registers, 4-1, 4-6  
Pointer, defined, 2-37  
Poll register, 8-9, 8-19, 8-20  
Poll Status register, 8-9, 8-19, 8-20, 8-21  
base value, 2-10, 2-11, 2-12  
Effective Address (EA), 2-13  
Index-5  
INDEX  
Polling, 8-1, 8-9  
POPA instruction, A-1  
Refresh Base Address Register (RFBASE), 7-8  
Refresh bus cycle‚ See Bus cycles  
Refresh Clock Interval Register (RFTIME), 7-7,  
7-8  
Refresh Control Register (RFCON), 7-9, 7-10  
Refresh Control Unit (RCU), 7-1–7-13  
and bus hold protocol, 7-12–7-13  
and Powerdown mode, 7-2  
and Power-Save mode, 7-2, 7-7  
block diagram, 7-1  
Power consumption‚ reducing, 3-28  
Power management, 5-10–5-14  
Power management modes  
and HALT bus cycles, 3-30  
Powerdown mode, 7-2  
Power-Save mode, 5-11–5-14, 7-2  
and DRAM refresh rate, 5-13  
and refresh interval, 7-7  
control register, 5-12  
bus latency, 7-7  
entering, 5-11  
exiting, 5-13  
calculating refresh interval, 7-7  
control registers, 7-7–7-10  
initialization code, 7-10  
operation, 7-2  
initialization code, 5-13–5-14  
Power-Save Register, 5-12  
Priority Mask register, 8-17, 8-18, 8-28  
Processor control instructions, 2-27  
Processor Status Word (PSW), 2-1, 2-7, 2-41  
bits defined, 2-7, 2-9  
overview, 7-2–7-4  
programming, 7-7–7-11  
relationship to BIU, 7-1  
Register operands, 2-27  
Registers, 2-1  
flag storage formats, 2-19  
reset status, 2-7  
control, 2-1  
Program transfer instructions, 2-23–2-24  
conditional transfers, 2-24, 2-26  
interrupts, 2-26  
data, 2-4, 2-5  
general, 2-1, 2-4, 2-5  
H & L group, 2-4  
iteration control, 2-25  
index, 2-5, 2-13, 2-34  
unconditional transfers, 2-24  
PUSH instruction, A-8  
PUSHA instruction, A-1  
P & I group, 2-4  
pointer, 2-1, 2-5, 2-13  
pointer and index, 2-4  
segment, 2-1, 2-5, 2-11, 2-12  
status, 2-1  
Q
Relocation Register‚ See PCB Relocation Register  
Reset  
Queue status signals, 3-38  
and bus hold protocol, 5-6  
and clock synchronization, 5-6–5-10  
cold, 5-7, 5-8  
RC circuit for reset input, 5-7  
warm, 5-7, 5-9  
R
RCL instruction, A-10  
RCR instruction, A-10  
Read bus cycles‚ See Bus cycles  
READY  
ROL instruction, A-10  
ROR instruction, A-10  
and chip-selects, 6-15  
and normally not-ready signal, 3-17–3-18  
and normally ready signal, 3-16–3-17  
and PCB accesses, 4-4  
and wait states, 3-13–3-18  
implementation approaches, 3-13  
timing concerns, 3-17  
S
SAL instruction, A-9  
SAR instruction, A-9  
SHL instruction, A-9  
Short integer, defined, 10-7  
Short real, defined, 10-7  
SHR instruction, A-9  
Real, defined, 10-7  
Real-time clock, code example, 9-17–9-20  
Refresh address, 7-4  
Index-6  
INDEX  
SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,  
2-34  
Sign Flag (SF), 2-7, 2-9  
Single-step trap (Type 1 exception), 2-43  
Software  
Timer Count Registers (TxCNT), 9-10  
Timer Counter Unit (TCU), 9-1–9-23  
application examples, 9-17–9-23  
block diagram, 9-2  
clock sources, 9-12  
code example  
configuring a digital one-shot, 9-17–9-23  
configuring a real-time clock, 9-17–9-19  
configuring a square-wave generator, 9-17–  
9-22  
counting sequence, 9-12–9-13  
dual maxcount mode, 9-13–9-14  
enabling and disabling counters, 9-15–9-16  
frequency, maximum, 9-17  
initializing, 9-11  
80C187 floating-point routine, 10-16  
80C187 initialization, 10-13–10-15  
digital one-shot, 9-17–9-23  
DMA initialization, 10-22–10-27  
ICU initialization, 8-31  
real-time clock, 9-17–9-19  
square-wave generator, 9-17–9-22  
TCU configurations, 9-17–9-23  
timed DMA transfers, 10-22–10-27  
data types, 2-37, 2-38  
input synchronization, 9-17  
interrupts, 9-16  
dynamic code relocation, 2-13, 2-14  
interrupts, 2-45  
overview, 2-17  
overview, 9-1–9-6  
programming, 9-6–9-16  
considerations, 9-16  
See also Addressing modes, Instruction set  
Square-wave generator, code example, 9-17–9-22  
SRDY, See READY  
SS register, 2-1, 2-5, 2-6, 2-13, 2-15, 2-30, 2-45  
Stack frame pointers, A-2  
Stack Pointer, 2-1, 2-5, 2-13, 2-15, 2-45  
Stack segment, 2-5  
pulsed output, 9-14–9-15  
retriggering, 9-13–9-14  
setup and hold times, 9-16  
single maxcount mode, 9-13, 9-14–9-16  
timer delay, 9-1  
timing, 9-1  
and BIU, 9-1  
Stacks, 2-15  
considerations, 9-16  
START registers, CSU, 6-6, 6-7  
STOP registers, CSU, 6-6, 6-8  
String instructions, 2-22–2-23  
and addressing modes, 2-34  
and memory-mapped I/O ports, 2-36  
operand locations, 2-13  
TxOUT signal, 9-15  
variable duty cycle output, 9-14–9-15  
Timer Maxcount Compare Registers (TxCMPA,  
TxCMPB), 9-11  
Timers‚ See Timer Counter Unit (TCU)  
Training, 1-7  
operands, 2-36  
Trap exceptions, 2-43  
Strings  
Trap Flag (TF), 2-7, 2-9, 2-43, 2-48  
T-state  
accessing, 2-13, 2-34  
defined, 2-37  
and bus cycles, 3-9  
Synchronizing asynchronous inputs, B-1  
and CLKOUT, 3-8  
defined, 3-7  
T
W
Wait states  
Technical support, 1-6  
Temporary real, defined, 10-7  
Terminology  
and bus cycles, 3-13  
and bus ready inputs, 3-13  
and chip-selects, 6-15–6-17  
and DRAM controllers, 7-1  
"above" vs "greater", 2-26  
"below" vs "less", 2-26  
device names, 1-2  
Timer Control Registers (TxCON), 9-7, 9-8  
Index-7  
INDEX  
and PCB accesses, 4-4  
and READY input, 3-13  
Word integer, defined, 10-7  
World Wide Web, 1-6  
Write bus cycle, 3-22  
Z
Zero Flag (ZF), 2-7, 2-9, 2-23  
Index-8  

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