Intel 8086 User Manual

8086  
16-BIT HMOS MICROPROCESSOR  
8086/8086-2/8086-1  
Y
Y
Y
Direct Addressing Capability 1 MByte  
of Memory  
Range of Clock Rates:  
5 MHz for 8086,  
8 MHz for 8086-2,  
10 MHz for 8086-1  
Architecture Designed for Powerful  
Assembly Language and Efficient High  
Level Languages  
Y
Y
MULTIBUS System Compatible  
Interface  
Y
14 Word, by 16-Bit Register Set with  
Symmetrical Operations  
Available in EXPRESS  
Ð Standard Temperature Range  
Ð Extended Temperature Range  
Y
Y
Y
24 Operand Addressing Modes  
Bit, Byte, Word, and Block Operations  
Y
Available in 40-Lead Cerdip and Plastic  
Package  
8 and 16-Bit Signed and Unsigned  
Arithmetic in Binary or Decimal  
Including Multiply and Divide  
Ý
(See Packaging Spec. Order 231369)  
The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is  
implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin  
CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations  
to achieve high performance levels.  
231455–2  
40 Lead  
Figure 2. 8086 Pin  
Configuration  
231455–1  
Figure 1. 8086 CPU Block Diagram  
September 1990  
Order Number: 231455-005  
8086  
Table 1. Pin Description (Continued)  
Name and Function  
Symbol  
Pin No.  
Type  
READY  
22  
I
READY: is the acknowledgement from the addressed memory or I/O  
device that it will complete the data transfer. The READY signal from  
memory/IO is synchronized by the 8284A Clock Generator to form  
READY. This signal is active HIGH. The 8086 READY input is not  
synchronized. Correct operation is not guaranteed if the setup and hold  
times are not met.  
INTR  
18  
I
INTERRUPT REQUEST: is a level triggered input which is sampled  
during the last clock cycle of each instruction to determine if the  
processor should enter into an interrupt acknowledge operation. A  
subroutine is vectored to via an interrupt vector lookup table located in  
system memory. It can be internally masked by software resetting the  
interrupt enable bit. INTR is internally synchronized. This signal is  
active HIGH.  
TEST  
NMI  
23  
17  
I
I
TEST: input is examined by the ‘‘Wait’’ instruction. If the TEST input is  
LOW execution continues, otherwise the processor waits in an ‘‘Idle’’  
state. This input is synchronized internally during each clock cycle on  
the leading edge of CLK.  
NON-MASKABLE INTERRUPT: an edge triggered input which causes  
a type 2 interrupt. A subroutine is vectored to via an interrupt vector  
lookup table located in system memory. NMI is not maskable internally  
by software. A transition from LOW to HIGH initiates the interrupt at the  
end of the current instruction. This input is internally synchronized.  
RESET  
CLK  
21  
19  
I
I
RESET: causes the processor to immediately terminate its present  
activity. The signal must be active HIGH for at least four clock cycles. It  
restarts execution, as described in the Instruction Set description, when  
RESET returns LOW. RESET is internally synchronized.  
CLOCK: provides the basic timing for the processor and bus controller.  
It is asymmetric with a 33% duty cycle to provide optimized internal  
timing.  
a
5V power supply pin.  
V
40  
1, 20  
33  
V
CC  
:
CC  
GND  
GROUND  
MN/MX  
I
MINIMUM/MAXIMUM: indicates what mode the processor is to  
operate in. The two modes are discussed in the following sections.  
e
The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MX  
V
).  
SS  
Only the pin functions which are unique to maximum mode are described; all other pin functions are as  
described above.  
S , S , S  
1
2628  
O
STATUS: active during T , T , and T and is returned to the passive state  
2
0
4
1
(1, 1, 1) during T or during T when READY is HIGH. This status is used  
2
3
W
by the 8288 Bus Controller to generate all memory and I/O access control  
signals. Any change by S , S , or S during T is used to indicate the  
beginning of a bus cycle, and the return to the passive state in T or T is  
2
1
0
4
3
W
used to indicate the end of a bus cycle.  
3
8086  
Table 1. Pin Description (Continued)  
Name and Function  
Symbol  
S , S , S  
(Continued)  
Pin No. Type  
2628  
O
These signals float to 3-state OFF in ‘‘hold acknowledge’’. These status  
lines are encoded as shown.  
2
1
0
S
S
S
0
Characteristics  
2
1
0 (LOW)  
0
0
0
Interrupt Acknowledge  
Read I/O Port  
Write I/O Port  
Halt  
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1 (HIGH)  
Code Access  
Read Memory  
Write Memory  
Passive  
1
1
1
RQ/GT ,  
0
RQ/GT  
30, 31  
I/O  
REQUEST/GRANT: pins are used by other local bus masters to force  
the processor to release the local bus at the end of the processor’s  
current bus cycle. Each pin is bidirectional with RQ/GT having higher  
1
0
priority than RQ/GT . RQ/GT pins have internal pull-up resistors and  
1
may be left unconnected. The request/grant sequence is as follows  
(see Page 2-24):  
1. A pulse of 1 CLK wide from another local bus master indicates a local  
bus request (‘‘hold’’) to the 8086 (pulse 1).  
2. During a T or T clock cycle, a pulse 1 CLK wide from the 8086 to  
4
1
the requesting master (pulse 2), indicates that the 8086 has allowed the  
local bus to float and that it will enter the ‘‘hold acknowledge’’ state at  
the next CLK. The CPU’s bus interface unit is disconnected logically  
from the local bus during ‘‘hold acknowledge’’.  
3. A pulse 1 CLK wide from the requesting master indicates to the 8086  
(pulse 3) that the ‘‘hold’’ request is about to end and that the 8086 can  
reclaim the local bus at the next CLK.  
Each master-master exchange of the local bus is a sequence of 3  
pulses. There must be one dead CLK cycle after each bus exchange.  
Pulses are active LOW.  
If the request is made while the CPU is performing a memory cycle, it  
will release the local bus during T of the cycle when all the following  
4
conditions are met:  
1. Request occurs on or before T .  
2
2. Current cycle is not the low byte of a word (on an odd address).  
3. Current cycle is not the first acknowledge of an interrupt acknowledge  
sequence.  
4. A locked instruction is not currently executing.  
If the local bus is idle when the request is made the two possible events  
will follow:  
1. Local bus will be released during the next clock.  
2. A memory cycle will start within 3 clocks. Now the four rules for a  
currently active memory cycle apply with condition number 1 already  
satisfied.  
LOCK  
29  
O
LOCK: output indicates that other system bus masters are not to gain  
control of the system bus while LOCK is active LOW. The LOCK signal  
is activated by the ‘‘LOCK’’ prefix instruction and remains active until the  
completion of the next instruction. This signal is active LOW, and floats  
to 3-state OFF in ‘‘hold acknowledge’’.  
4
8086  
Table 1. Pin Description (Continued)  
Name and Function  
Symbol  
QS , QS  
Pin No.  
Type  
24, 25  
O
QUEUE STATUS: The queue status is valid during the CLK cycle after  
which the queue operation is performed.  
QS and QS provide status to allow external tracking of the internal  
1
0
1
8086 instruction queue.  
0
QS  
QS  
Characteristics  
No Operation  
1
0
0 (LOW)  
0
0
1
0
1
First Byte of Op Code from Queue  
Empty the Queue  
Subsequent Byte from Queue  
1 (HIGH)  
1
e
functions which are unique to minimum mode are described; all other pin functions are as described above.  
The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX  
V
). Only the pin  
CC  
M/IO  
28  
29  
O
O
STATUS LINE: logically equivalent to S in the maximum mode. It is used to  
2
distinguish a memory access from an I/O access. M/IO becomes valid in  
the T preceding a bus cycle and remains valid until the final T of the cycle  
4
4
LOW). M/IO floats to 3-state OFF in local bus ‘‘hold  
e
acknowledge’’.  
e
(M  
HIGH, IO  
WR  
WRITE: indicates that the processor is performing a write memory or write  
I/O cycle, depending on the state of the M/IO signal. WR is active for T , T  
and T of any write cycle. It is active LOW, and floats to 3-state OFF in  
2
3
W
local bus ‘‘hold acknowledge’’.  
INTA  
ALE  
24  
25  
O
O
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active  
LOW during T , T and T of each interrupt acknowledge cycle.  
2
3
W
ADDRESS LATCH ENABLE: provided by the processor to latch the  
address into the 8282/8283 address latch. It is a HIGH pulse active during  
T
1
of any bus cycle. Note that ALE is never floated.  
DT/R  
DEN  
27  
26  
O
O
DATA TRANSMIT/RECEIVE: needed in minimum system that desires to  
use an 8286/8287 data bus transceiver. It is used to control the direction of  
data flow through the transceiver. Logically DT/R is equivalent to S in the  
1
e
LOW.) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’.  
e
maximum mode, and its timing is the same as for M/IO. (T  
HIGH, R  
DATA ENABLE: provided as an output enable for the 8286/8287 in a  
minimum system which uses the transceiver. DEN is active LOW during  
each memory and I/O access and for INTA cycles. For a read or INTA cycle  
it is active from the middle of T until the middle of T , while for a write cycle  
2
it is active from the beginning of T until the middle of T . DEN floats to 3-  
4
2
state OFF in local bus ‘‘hold acknowledge’’.  
4
HOLD,  
HLDA  
31, 30  
I/O  
HOLD: indicates that another master is requesting a local bus ‘‘hold.’’ To be  
acknowledged, HOLD must be active HIGH. The processor receiving the  
‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the  
middle of a T or T clock cycle. Simultaneous with the issuance of HLDA  
4
i
the processor will float the local bus and control lines. After HOLD is  
detected as being LOW, the processor will LOWer the HLDA, and when the  
processor needs to run another cycle, it will again drive the local bus and  
control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up  
resistors.  
The same rules as for RQ/GT apply regarding when the local bus will be  
released.  
HOLD is not an asynchronous input. External synchronization should be  
provided if the system cannot otherwise guarantee the setup time.  
5
8086  
bytes, addressed as 00000(H) to FFFFF(H). The  
memory is logically divided into code, data, extra  
data, and stack segments of up to 64K bytes each,  
with each segment falling on 16-byte boundaries.  
(See Figure 3a.)  
FUNCTIONAL DESCRIPTION  
General Operation  
The internal functions of the 8086 processor are  
partitioned logically into two processing units. The  
first is the Bus Interface Unit (BIU) and the second is  
the Execution Unit (EU) as shown in the block dia-  
gram of Figure 1.  
All memory references are made relative to base ad-  
dresses contained in high speed segment registers.  
The segment types were chosen based on the ad-  
dressing needs of programs. The segment register  
to be selected is automatically chosen according to  
the rules of the following table. All information in one  
segment type share the same logical attributes (e.g.  
code or data). By structuring memory into relocat-  
able areas of similar characteristics and by automati-  
cally selecting segment registers, programs are  
shorter, faster, and more structured.  
These units can interact directly but for the most  
part perform as separate asynchronous operational  
processors. The bus interface unit provides the func-  
tions related to instruction fetching and queuing, op-  
erand fetch and store, and address relocation. This  
unit also provides the basic bus control. The overlap  
of instruction pre-fetching provided by this unit  
serves to increase processor performance through  
improved bus bandwidth utilization. Up to 6 bytes of  
the instruction stream can be queued while waiting  
for decoding and execution.  
Word (16-bit) operands can be located on even or  
odd address boundaries and are thus not con-  
strained to even boundaries as is the case in many  
16-bit computers. For address and data operands,  
the least significant byte of the word is stored in the  
lower valued address location and the most signifi-  
cant byte in the next higher address location. The  
BIU automatically performs the proper number of  
memory accesses, one if the word operand is on an  
even byte boundary and two if it is on an odd byte  
boundary. Except for the performance penalty, this  
double access is transparent to the software. This  
performance penalty does not occur for instruction  
fetches, only word operands.  
The instruction stream queuing mechanism allows  
the BIU to keep the memory utilized very efficiently.  
Whenever there is space for at least 2 bytes in the  
queue, the BIU will attempt a word fetch memory  
cycle. This greatly reduces ‘‘dead time’’ on the  
memory bus. The queue acts as a First-In-First-Out  
(FIFO) buffer, from which the EU extracts instruction  
bytes as required. If the queue is empty (following a  
branch instruction, for example), the first byte into  
the queue immediately becomes available to the EU.  
Physically, the memory is organized as a high bank  
(D D ) and a low bank (D D ) of 512K 8-bit  
The execution unit receives pre-fetched instructions  
from the BIU queue and provides un-relocated oper-  
and addresses to the BIU. Memory operands are  
passed through the BIU for processing by the EU,  
which passes results to the BIU for storage. See the  
Instruction Set description for further register set  
and architectural descriptions.  
15  
8
7
0
bytes addressed in parallel by the processor’s ad-  
dress lines A A . Byte data with even addresses  
is transferred on the D D bus lines while odd ad-  
19  
1
7
0
dressed byte data (A HIGH) is transferred on the  
D
0
–D bus lines. The processor provides two en-  
15  
able signals, BHE and A , to selectively allow read-  
8
0
ing from or writing into either an odd byte location,  
even byte location, or both. The instruction stream is  
fetched from memory as words and is addressed  
internally by the processor to the byte level as nec-  
essary.  
MEMORY ORGANIZATION  
The processor provides a 20-bit address to memory  
which locates the byte being referenced. The memo-  
ry is organized as a linear array of up to 1 million  
Memory  
Segment Register  
Used  
Segment  
Reference Need  
Selection Rule  
Instructions  
Stack  
CODE (CS)  
STACK (SS)  
Automatic with all instruction prefetch.  
All stack pushes and pops. Memory references relative to BP  
base register except data references.  
Local Data  
DATA (DS)  
Data references when: relative to stack, destination of string  
operation, or explicitly overridden.  
External (Global) Data EXTRA (ES)  
Destination of string operations: explicitly selected using a  
segment override.  
6
8086  
address FFFF0H through FFFFFH are reserved for  
operations including a jump to the initial program  
loading routine. Following RESET, the CPU will al-  
ways begin execution at location FFFF0H where the  
jump must be. Locations 00000H through 003FFH  
are reserved for interrupt operations. Each of the  
256 possible interrupt types has its service routine  
pointed to by a 4-byte pointer element consisting of  
a 16-bit segment address and a 16-bit offset ad-  
dress. The pointer elements are assumed to have  
been stored at the respective places in reserved  
memory prior to occurrence of interrupts.  
MINIMUM AND MAXIMUM MODES  
The requirements for supporting minimum and maxi-  
mum 8086 systems are sufficiently different that  
they cannot be done efficiently with 40 uniquely de-  
fined pins. Consequently, the 8086 is equipped with  
a strap pin (MN/MX) which defines the system con-  
figuration. The definition of a certain subset of the  
pins changes dependent on the condition of the  
strap pin. When MN/MX pin is strapped to GND, the  
8086 treats pins 24 through 31 in maximum mode.  
An 8288 bus controller interprets status information  
231455–3  
Figure 3a. Memory Organization  
In referencing word data the BIU requires one or two  
memory cycles depending on whether or not the  
starting byte of the word is on an even or odd ad-  
dress, respectively. Consequently, in referencing  
word operands performance can be optimized by lo-  
cating data on even address boundaries. This is an  
especially useful technique for using the stack, since  
odd address references to the stack may adversely  
affect the context switching time for interrupt pro-  
cessing or task multiplexing.  
coded into S , S , S to generate bus timing and  
2
0
2
control signals compatible with the MULTIBUS ar-  
chitecture. When the MN/MX pin is strapped to V  
,
CC  
the 8086 generates bus control signals itself on pins  
24 through 31, as shown in parentheses in Figure 2.  
Examples of minimum mode and maximum mode  
systems are shown in Figure 4.  
BUS OPERATION  
The 8086 has a combined address and data bus  
commonly referred to as a time multiplexed bus.  
This technique provides the most efficient use of  
pins on the processor while permitting the use of a  
standard 40-lead package. This ‘‘local bus’’ can be  
buffered directly and used throughout the system  
with address latching provided on memory and I/O  
modules. In addition, the bus can also be demulti-  
plexed at the processor with a single set of address  
latches if a standard non-multiplexed bus is desired  
for the system.  
Each processor bus cycle consists of at least four  
CLK cycles. These are referred to as T , T , T and  
1
2
3
(see Figure 5). The address is emitted from the  
T
4
processor during T and data transfer occurs on the  
1
bus during T and T . T is used primarily for chang-  
231455–4  
3
4
2
ing the direction of the bus during read operations. In  
the event that a ‘‘NOT READY’’ indication is given  
by the addressed device, ‘‘Wait’’ states (T ) are in-  
Figure 3b. Reserved Memory Locations  
W
Certain locations in memory are reserved for specific  
CPU operations (see Figure 3b). Locations from  
serted between T and T . Each inserted ‘‘Wait’’  
3
state is of the same duration as a CLK cycle. Periods  
4
7
8086  
231455–5  
Figure 4a. Minimum Mode 8086 Typical Configuration  
231455–6  
Figure 4b. Maximum Mode 8086 Typical Configuration  
8
8086  
can occur between 8086 bus cycles. These are re-  
ferred to as ‘‘Idle’’ states (T ) or inactive CLK cycles.  
S
S
S
0
Characteristics  
2
1
i
The processor uses these cycles for internal house-  
keeping.  
0 (LOW)  
0
0
Interrupt Acknowledge  
Read I/O  
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
During T of any bus cycle the ALE (Address Latch  
1
0
Write I/O  
Enable) signal is emitted (by either the processor or  
the 8288 bus controller, depending on the MN/MX  
strap). At the trailing edge of this pulse, a valid ad-  
dress and certain status information for the cycle  
may be latched.  
0
Halt  
1 (HIGH)  
Instruction Fetch  
Read Data from Memory  
Write Data to Memory  
Passive (no bus cycle)  
1
1
1
Status bits S , S , and S are used, in maximum  
0
1
2
mode, by the bus controller to identify the type of  
bus transaction according to the following table:  
231455–8  
Figure 5. Basic System Timing  
9
8086  
Status bits S through S are multiplexed with high-  
3
NMI asserted prior to the 2nd clock after the end of  
RESET will not be honored. If NMI is asserted after  
that point and during the internal reset sequence,  
the processor may execute one instruction before  
responding to the interrupt. A hold request active  
immediately after RESET will be honored before the  
first instruction fetch.  
7
order address bits and the BHE signal, and are  
therefore valid during T through T . S and S indi-  
2
4
3
4
cate which segment register (see Instruction Set de-  
scription) was used for this bus cycle in forming the  
address, according to the following table:  
S
S
Characteristics  
Alternate Data (extra segment)  
Stack  
4
3
All 3-state outputs float to 3-state OFF during  
RESET. Status is active in the idle state for the first  
clock after RESET becomes active and then floats  
to 3-state OFF. ALE and HLDA are driven low.  
0 (LOW)  
0
0
1
0
1
1 (HIGH)  
1
Code or None  
Data  
INTERRUPT OPERATIONS  
S
S
is a reflection of the PSW interrupt enable bit.  
e
5
6
Interrupt operations fall into two classes; software or  
hardware initiated. The software initiated interrupts  
and software aspects of hardware interrupts are  
specified in the Instruction Set description. Hard-  
ware interrupts can be classified as non-maskable or  
maskable.  
0 and S is a spare status bit.  
7
I/O ADDRESSING  
In the 8086, I/O operations can address up to a  
maximum of 64K I/O byte registers or 32K I/O word  
registers. The I/O address appears in the same for-  
mat as the memory address on bus lines A A .  
Interrupts result in a transfer of control to a new pro-  
gram location. A 256-element table containing ad-  
dress pointers to the interrupt service program loca-  
tions resides in absolute locations 0 through 3FFH  
(see Figure 3b), which are reserved for this purpose.  
Each element in the table is 4 bytes in size and  
corresponds to an interrupt ‘‘type’’. An interrupting  
device supplies an 8-bit type number, during the in-  
terrupt acknowledge sequence, which is used to  
‘‘vector’’ through the appropriate element to the new  
interrupt service program location.  
15  
0
The address lines A A are zero in I/O opera-  
19  
16  
tions. The variable I/O instructions which use regis-  
ter DX as a pointer have full address capability while  
the direct I/O instructions directly address one or  
two of the 256 I/O byte locations in page 0 of the  
I/O address space.  
I/O ports are addressed in the same manner as  
memory locations. Even addressed bytes are trans-  
ferred on the D D bus lines and odd addressed  
7
0
bytes on D D . Care must be taken to assure that  
15  
each register within an 8-bit peripheral located on  
the lower portion of the bus be addressed as even.  
8
NON-MASKABLE INTERRUPT (NMI)  
The processor provides a single non-maskable inter-  
rupt pin (NMI) which has higher priority than the  
maskable interrupt request pin (INTR). A typical use  
would be to activate a power failure routine. The  
NMI is edge-triggered on a LOW-to-HIGH transition.  
The activation of this pin causes a type 2 interrupt.  
(See Instruction Set description.)  
External Interface  
PROCESSOR RESET AND INITIALIZATION  
Processor initialization or start up is accomplished  
with activation (HIGH) of the RESET pin. The 8086  
RESET is required to be HIGH for greater than 4  
CLK cycles. The 8086 will terminate operations on  
the high-going edge of RESET and will remain dor-  
mant as long as RESET is HIGH. The low-going  
transition of RESET triggers an internal reset se-  
quence for approximately 10 CLK cycles. After this  
interval the 8086 operates normally beginning with  
the instruction in absolute location FFFF0H (see Fig-  
ure 3b). The details of this operation are specified in  
the Instruction Set description of the MCS-86 Family  
User’s Manual. The RESET input is internally syn-  
chronized to the processor clock. At initialization the  
HIGH-to-LOW transition of RESET must occur no  
sooner than 50 ms after power-up, to allow complete  
initialization of the 8086.  
NMI is required to have a duration in the HIGH state  
of greater than two CLK cycles, but is not required to  
be synchronized to the clock. Any high-going tran-  
sition of NMI is latched on-chip and will be serviced  
at the end of the current instruction or between  
whole moves of a block-type instruction. Worst case  
response to NMI would be for multiply, divide, and  
variable shift instructions. There is no specification  
on the occurrence of the low-going edge; it may oc-  
cur before, during, or after the servicing of NMI. An-  
other high-going edge triggers another response if it  
occurs after the start of the NMI procedure. The sig-  
nal must be free of logical spikes in general and be  
free of bounces on the low-going edge to avoid trig-  
gering extraneous responses.  
10  
8086  
MASKABLE INTERRUPT (INTR)  
HALT  
The 8086 provides a single interrupt request input  
(INTR) which can be masked internally by software  
with the resetting of the interrupt enable FLAG  
status bit. The interrupt request signal is level trig-  
gered. It is internally synchronized during each clock  
cycle on the high-going edge of CLK. To be re-  
sponded to, INTR must be present (HIGH) during  
the clock period preceding the end of the current  
instruction or the end of a whole move for a block-  
type instruction. During the interrupt response se-  
quence further interrupts are disabled. The enable  
bit is reset as part of the response to any interrupt  
(INTR, NMI, software interrupt or single-step), al-  
though the FLAGS register which is automatically  
pushed onto the stack reflects the state of the proc-  
essor prior to the interrupt. Until the old FLAGS reg-  
ister is restored the enable bit will be zero unless  
specifically set by an instruction.  
When a software ‘‘HALT’’ instruction is executed the  
processor indicates that it is entering the ‘‘HALT’’  
state in one of two ways depending upon which  
mode is strapped. In minimum mode, the processor  
issues one ALE with no qualifying bus control sig-  
nals. In maximum mode, the processor issues ap-  
propriate HALT status on S , S , and S ; and the  
2
1
0
8288 bus controller issues one ALE. The 8086 will  
not leave the ‘‘HALT’’ state when a local bus ‘‘hold’’  
is entered while in ‘‘HALT’’. In this case, the proces-  
sor reissues the HALT indicator. An interrupt request  
or RESET will force the 8086 out of the ‘‘HALT’’  
state.  
READ/MODIFY/WRITE (SEMAPHORE)  
OPERATIONS VIA LOCK  
The LOCK status information is provided by the  
processor when directly consecutive bus cycles are  
required during the execution of an instruc-  
tion. This provides the processor with the capability  
of performing read/modify/write operations on  
memory (via the Exchange Register With Memory  
instruction, for example) without the possibility of an-  
other system bus master receiving intervening mem-  
ory cycles. This is useful in multi-processor system  
configurations to accomplish ‘‘test and set lock’’ op-  
erations. The LOCK signal is activated (forced LOW)  
in the clock cycle following the one in which the soft-  
ware ‘‘LOCK’’ prefix instruction is decoded by the  
EU. It is deactivated at the end of the last bus cycle  
of the instruction following the ‘‘LOCK’’ prefix in-  
struction. While LOCK is active a request on a RQ/  
GT pin will be recorded and then honored at the end  
of the LOCK.  
During the response sequence (Figure 6) the proc-  
essor executes two successive (back-to-back) inter-  
rupt acknowledge cycles. The 8086 emits the LOCK  
signal from T of the first bus cycle until T of the  
2
2
second. A local bus ‘‘hold’’ request will not be hon-  
ored until the end of the second bus cycle. In the  
second bus cycle a byte is fetched from the external  
interrupt system (e.g., 8259A PIC) which identifies  
the source (type) of the interrupt. This byte is multi-  
plied by four and used as a pointer into the interrupt  
vector lookup table. An INTR signal left HIGH will be  
continually responded to within the limitations of the  
enable bit and sample period. The INTERRUPT RE-  
TURN instruction includes a FLAGS pop which re-  
turns the status of the original interrupt enable bit  
when it restores the FLAGS.  
231455–9  
Figure 6. Interrupt Acknowledge Sequence  
11  
8086  
EXTERNAL SYNCHRONIZATION VIA TEST  
SYSTEM TIMINGÐMINIMUM SYSTEM  
As an alternative to the interrupts and general I/O  
capabilities, the 8086 provides a single software-  
testable input known as the TEST signal. At any time  
the program may execute a WAIT instruction. If at  
that time the TEST signal is inactive (HIGH), pro-  
gram execution becomes suspended while the proc-  
essor waits for TEST to become active. It must  
remain active for at least 5 CLK cycles. The WAIT  
instruction is re-executed repeatedly until that time.  
This activity does not consume bus cycles. The  
processor remains in an idle state while waiting. All  
8086 drivers go to 3-state OFF if bus ‘‘Hold’’ is en-  
tered. If interrupts are enabled, they may occur while  
the processor is waiting. When this occurs the proc-  
essor fetches the WAIT instruction one extra time,  
processes the interrupt, and then re-fetches and re-  
executes the WAIT instruction upon returning from  
the interrupt.  
The read cycle begins in T with the assertion of the  
1
Address Latch Enable (ALE) signal. The trailing (low-  
going) edge of this signal is used to latch the ad-  
dress information, which is valid on the local bus at  
this time, into the address latch. The BHE and A  
signals address the low, high, or both bytes. From T  
0
1
to T the M/IO signal indicates a memory or I/O  
4
operation. At T the address is removed from the  
2
local bus and the bus goes to a high impedance  
state. The read control signal is also asserted at T .  
2
The read (RD) signal causes the addressed device  
to enable its data bus drivers to the local bus. Some  
time later valid data will be available on the bus and  
the addressed device will drive the READY line  
HIGH. When the processor returns the read signal to  
a HIGH level, the addressed device will again 3-  
state its bus drivers. If a transceiver is required to  
buffer the 8086 local bus, signals DT/R and DEN  
are provided by the 8086.  
A write cycle also begins with the assertion of ALE  
and the emission of the address. The M/IO signal is  
again asserted to indicate a memory or I/O write  
Basic System Timing  
Typical system configurations for the processor op-  
erating in minimum mode and in maximum mode are  
shown in Figures 4a and 4b, respectively. In mini-  
operation. In the T immediately following the ad-  
2
dress emission the processor emits the data to be  
written into the addressed location. This data re-  
mains valid until the middle of T . During T , T , and  
mum mode, the MN/MX pin is strapped to V  
and  
CC  
the processor emits bus control signals in a manner  
similar to the 8085. In maximum mode, the MN/MX  
pin is strapped to V and the processor emits cod-  
4
2
3
T
W
the processor asserts the write control signal.  
The write (WR) signal becomes active at the begin-  
ning of T as opposed to the read which is delayed  
somewhat into T to provide time for the bus to float.  
SS  
ed status information which the 8288 bus controller  
uses to generate MULTIBUS compatible bus control  
signals. Figure 5 illustrates the signal timing relation-  
ships.  
2
2
The BHE and A signals are used to select the prop-  
0
er byte(s) of the memory/IO word to be read or writ-  
ten according to the following table:  
BHE  
A0  
Characteristics  
0
0
0
1
Whole word  
Upper byte from/to  
odd address  
Lower byte from/to  
even address  
None  
1
1
0
1
I/O ports are addressed in the same manner as  
memory location. Even addressed bytes are trans-  
ferred on the D D bus lines and odd addressed  
7
0
bytes on D D .  
15  
8
The basic difference between the interrupt acknowl-  
edge cycle and a read cycle is that the interrupt ac-  
knowledge signal (INTA) is asserted in place of the  
read (RD) signal and the address bus is floated.  
(See Figure 6.) In the second of two successive  
INTA cycles, a byte of information is read from bus  
23145510  
Figure 7. 8086 Register Model  
12  
8086  
lines D D as supplied by the inerrupt system logic  
7
acknowledge, or software halt. The 8288 thus issues  
control signals specifying memory read or write, I/O  
read or write, or interrupt acknowledge. The 8288  
provides two types of write strobes, normal and ad-  
vanced, to be applied as required. The normal write  
strobes have data valid at the leading edge of write.  
The advanced write strobes have the same timing  
as read strobes, and hence data isn’t valid at the  
leading edge of write. The transceiver receives the  
usual DIR and G inputs from the 8288’s DT/R and  
DEN.  
0
(i.e., 8259A Priority Interrupt Controller). This byte  
identifies the source (type) of the interrupt. It is multi-  
plied by four and used as a pointer into an interrupt  
vector lookup table, as described earlier.  
BUS TIMINGÐMEDIUM SIZE SYSTEMS  
For medium size systems the MN/MX pin is con-  
nected to V and the 8288 Bus Controller is added  
SS  
to the system as well as a latch for latching the sys-  
tem address, and a transceiver to allow for bus load-  
ing greater than the 8086 is capable of handling.  
Signals ALE, DEN, and DT/R are generated by the  
8288 instead of the processor in this configuration  
although their timing remains relatively the same.  
The pointer into the interrupt vector table, which is  
passed during the second INTA cycle, can derive  
from an 8259A located on either the local bus or the  
system bus. If the master 8259A Priority Interrupt  
Controller is positioned on the local bus, a TTL gate  
is required to disable the transceiver when reading  
from the master 8259A during the interrupt acknowl-  
edge sequence and software ‘‘poll’’.  
The 8086 status outputs (S , S , and S ) provide  
2
1
0
type-of-cycle information and become 8288 inputs.  
This bus cycle information specifies read (code,  
data, or I/O), write (data or I/O), interrupt  
13  
8086  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This is a production data sheet. The specifi-  
cations are subject to change without notice.  
Ambient Temperature Under Bias ÀÀÀÀÀÀ0 C to 70 C  
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
§
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
a
§
§
Voltage on Any Pin with  
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1.0V to 7V  
b
a
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5W  
e
e
e
e
e
e
g
D.C. CHARACTERISTICS (8086:  
T
(8086-1: T  
0 C to 70 C, V  
§
5V 10%)  
§
A
A
A
CC  
CC  
CC  
g
0 C to 70 C, V  
§
5V 5%)  
§
g
5V 5%)  
(8086-2: T  
0 C to 70 C, V  
§
§
Symbol  
Parameter  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
Min  
Max  
Units  
Test Conditions  
(Note 1)  
b
a
0.8  
V
V
V
V
0.5  
V
V
V
V
IL  
a
2.0  
V
0.5  
(Notes 1, 2)  
IH  
CC  
e
0.45  
I
I
2.5 mA  
OL  
OH  
OL  
e b  
2.4  
400 mA  
OH  
I
Power Supply Current: 8086  
8086-1  
8086-2  
340  
360  
350  
CC  
e
s
mA  
T
25 C  
§
A
s
g
g
a
I
I
Input Leakage Current  
Output Leakage Current  
Clock Input Low Voltage  
Clock Input High Voltage  
10  
10  
mA  
mA  
V
0V  
V
IN  
V
(Note 3)  
CC  
LI  
s
s
0.45V  
V
OUT  
V
CC  
LO  
b
V
V
0.5  
0.6  
CL  
a
3.9  
V
1.0  
V
CH  
CC  
e
e
C
Capacitance of Input Buffer  
(All input except  
AD AD , RQ/GT)  
15  
pF  
fc  
fc  
1 MHz  
1 MHz  
IN  
IO  
0
15  
C
Capacitance of I/O Buffer  
(AD AD , RQ/GT)  
15  
pF  
0
15  
NOTES:  
1. V tested with MN/MX Pin  
e
e
0V. V tested with MN/MX Pin  
IH  
5V. MN/MX Pin is a Strap Pin.  
IL  
2. Not applicable to RQ/GT0 and RQ/GT1 (Pins 30 and 31).  
e
e
3. HOLD and HLDA I min  
LI  
30 mA, max  
500 mA.  
14  
8086  
e
e
e
e
e
e
g
A.C. CHARACTERISTICS (8086:  
T
0 C to 70 C, V  
§
5V 10%)  
§
A
A
A
CC  
CC  
CC  
g
(8086-1: T  
(8086-2: T  
0 C to 70 C, V  
§
5V 5%)  
§
g
5V 5%)  
0 C to 70 C, V  
§
§
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS  
8086  
8086-1  
8086-2  
Symbol  
Parameter  
Units  
Test Conditions  
Min Max  
Min  
100  
53  
Max Min Max  
TCLCL  
TCLCH  
TCHCL  
CLK Cycle Period  
CLK Low Time  
CLK High Time  
200  
118  
69  
500  
500  
125  
68  
500  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
39  
44  
TCH1CH2 CLK Rise Time  
10  
10  
10  
10  
10  
10  
From 1.0V to 3.5V  
From 3.5V to 1.0V  
TCL2CL1  
TDVCL  
CLK Fall Time  
Data in Setup Time  
Data in Hold Time  
30  
10  
35  
5
20  
10  
35  
TCLDX  
10  
35  
TR1VCL  
RDY Setup Time  
into 8284A (See  
Notes 1, 2)  
TCLR1X  
RDY Hold Time  
into 8284A (See  
Notes 1, 2)  
0
0
0
ns  
TRYHCH  
TCHRYX  
TRYLCL  
READY Setup  
Time into 8086  
118  
30  
53  
20  
68  
20  
ns  
ns  
ns  
READY Hold Time  
into 8086  
b
b
b
8
READY Inactive to  
CLK (See Note 3)  
8
10  
THVCH  
TINVCH  
HOLD Setup Time  
35  
30  
20  
15  
20  
15  
ns  
ns  
INTR, NMI, TEST  
Setup Time (See  
Note 2)  
TILIH  
TIHIL  
Input Rise Time  
(Except CLK)  
20  
12  
20  
12  
20  
12  
ns  
ns  
From 0.8V to 2.0V  
From 2.0V to 0.8V  
Input Fall Time  
(Except CLK)  
15  
8086  
A.C. CHARACTERISTICS (Continued)  
TIMING RESPONSES  
8086  
8086-1  
Min  
8086-2  
Min  
Test  
Symbol  
Parameter  
Units  
Conditions  
Min  
10  
Max  
Max  
Max  
TCLAV Address Valid Delay  
TCLAX Address Hold Time  
110  
10  
10  
10  
50  
10  
10  
60  
ns  
ns  
ns  
10  
TCLAZ Address Float  
Delay  
TCLAX  
80  
40  
TCLAX  
50  
TLHLL  
ALE Width  
TCLCH-20  
TCLCH-10  
TCLCH-10  
ns  
ns  
ns  
ns  
TCLLH ALE Active Delay  
TCHLL ALE Inactive Delay  
80  
85  
40  
45  
50  
55  
TLLAX Address Hold Time TCHCL-10  
TCHCL-10  
10  
TCHCL-10  
10  
e
TCLDV Data Valid Delay  
TCHDX Data Hold Time  
10  
10  
110  
50  
60  
ns *C  
20–100 pF  
L
for all 8086  
Outputs (In  
addition to 8086  
selfload)  
10  
10  
ns  
ns  
TWHDX Data Hold Time  
After WR  
TCLCH-30  
TCLCH-25  
TCLCH-30  
TCVCTV Control Active  
Delay 1  
10  
10  
10  
0
110  
110  
110  
10  
10  
10  
0
50  
45  
50  
10  
10  
10  
0
70  
60  
70  
ns  
ns  
ns  
ns  
TCHCTV Control Active  
Delay 2  
TCVCTX Control Inactive  
Delay  
TAZRL Address Float to  
READ Active  
TCLRL RD Active Delay  
TCLRH RD Inactive Delay  
10  
10  
165  
150  
10  
10  
70  
60  
10  
10  
100 ns  
80  
ns  
ns  
TRHAV RD Inactive to Next TCLCL-45  
Address Active  
TCLCL-35  
TCLCL-40  
TCLHAV HLDA Valid Delay  
TRLRH RD Width  
10  
160  
10  
60  
10  
100 ns  
2TCLCL-75  
2TCLCL-60  
TCLCH-60  
2TCLCL-40  
2TCLCL-35  
TCLCH-35  
2TCLCL-50  
2TCLCL-40  
TCLCH-40  
ns  
ns  
ns  
TWLWH WR Width  
TAVAL Address Valid to  
ALE Low  
TOLOH Output Rise Time  
TOHOL Output Fall Time  
20  
12  
20  
12  
20  
12  
ns From 0.8V to 2.0V  
ns From 2.0V to 0.8V  
NOTES:  
1. Signal at 8284A shown for reference only.  
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.  
3. Applies only to T2 state. (8 ns into T3).  
16  
8086  
A.C. TESTING INPUT, OUTPUT WAVEFORM  
A.C. TESTING LOAD CIRCUIT  
231455-11  
A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V  
for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both  
a Logic ‘‘1’’ and ‘‘0’’.  
23145512  
C
Includes Jig Capacitance  
L
WAVEFORMS  
MINIMUM MODE  
23145513  
17  
8086  
WAVEFORMS (Continued)  
MINIMUM MODE (Continued)  
23145514  
SOFTWARE HALTÐ  
e
DT/R  
RD, WR, INTA  
e
V
OH  
INDETERMINATE  
NOTES:  
1. All signals switch between V  
and V unless otherwise specified.  
OL  
OH  
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.  
2
3
W
W
3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control  
signals shown for second INTA cycle.  
4. Signals at 8284A are shown for reference only.  
5. All timing measurements are made at 1.5V unless otherwise noted.  
18  
8086  
A.C. CHARACTERISTICS  
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)  
TIMING REQUIREMENTS  
8086  
8086-1  
8086-2  
Test  
Symbol  
Parameter  
Units  
Conditions  
Min Max  
Min  
100  
53  
Max Min Max  
TCLCL  
TCLCH  
TCHCL  
CLK Cycle Period  
CLK Low Time  
CLK High Time  
200  
118  
69  
500  
500  
125  
68  
500  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
39  
44  
TCH1CH2 CLK Rise Time  
10  
10  
10  
10  
10  
10  
From 1.0V to 3.5V  
From 3.5V to 1.0V  
TCL2CL1  
TDVCL  
CLK Fall Time  
Data in Setup Time  
Data in Hold Time  
30  
10  
35  
5
20  
10  
35  
TCLDX  
10  
35  
TR1VCL  
RDY Setup Time  
into 8284A  
(Notes 1, 2)  
TCLR1X  
RDY Hold Time  
into 8284A  
(Notes 1, 2)  
0
0
0
ns  
TRYHCH  
TCHRYX  
TRYLCL  
TINVCH  
READY Setup  
Time into 8086  
118  
30  
53  
20  
68  
20  
ns  
ns  
ns  
ns  
READY Hold Time  
into 8086  
b
b
b
8
READY Inactive to  
CLK (Note 4)  
8
10  
Setup Time for  
Recognition (INTR,  
NMI, TEST)  
30  
15  
15  
(Note 2)  
TGVCH  
TCHGX  
TILIH  
RQ/GT Setup Time  
(Note 5)  
30  
40  
15  
20  
15  
30  
ns  
ns  
ns  
ns  
RQ Hold Time into  
8086  
Input Rise Time  
(Except CLK)  
20  
12  
20  
12  
20  
12  
From 0.8V to 2.0V  
From 2.0V to 0.8V  
TIHIL  
Input Fall Time  
(Except CLK)  
19  
8086  
A.C. CHARACTERISTICS (Continued)  
TIMING RESPONSES  
8086  
8086-1  
8086-2  
Test  
Symbol  
TCLML  
TCLMH  
Parameter  
Units  
ns  
Conditions  
Min  
Max Min Max  
Min  
Max  
Command Active  
Delay (See Note 1)  
10  
35  
10  
35  
35  
45  
10  
35  
Command Inactive  
Delay (See Note 1)  
10  
35  
10  
10  
35  
65  
ns  
TRYHSH READY Active to  
Status Passive (See  
Note 3)  
110  
ns  
TCHSV  
TCLSH  
Status Active Delay  
10  
10  
110  
130  
10  
10  
45  
55  
10  
10  
60  
70  
ns  
ns  
Status Inactive  
Delay  
TCLAV  
TCLAX  
TCLAZ  
TSVLH  
Address Valid Delay  
Address Hold Time  
10  
10  
110  
10  
10  
10  
50  
10  
10  
60  
ns  
ns  
ns  
ns  
Address Float Delay TCLAX  
80  
15  
40  
15  
TCLAX  
50  
15  
Status Valid to ALE  
High (See Note 1)  
TSVMCH Status Valid to  
MCE High (See  
Note 1)  
15  
15  
15  
ns  
e
TCLLH  
CLK Low to ALE  
Valid (See Note 1)  
15  
15  
15  
15  
15  
15  
50  
15  
15  
15  
15  
60  
ns  
ns  
ns  
ns  
C
L
20100 pF  
for all 8086  
Outputs (In  
addition to 8086  
self-load)  
TCLMCH CLK Low to MCE  
High (See Note 1)  
TCHLL  
ALE Inactive Delay  
(See Note 1)  
15  
TCLMCL MCE Inactive Delay  
(See Note 1)  
15  
TCLDV  
TCHDX  
TCVNV  
Data Valid Delay  
Data Hold Time  
10  
10  
5
110  
10  
10  
5
10  
10  
5
ns  
ns  
ns  
Control Active  
Delay (See Note 1)  
45  
45  
45  
45  
45  
45  
TCVNX  
TAZRL  
Control Inactive  
Delay (See Note 1)  
10  
0
10  
0
10  
0
ns  
ns  
Address Float to  
READ Active  
TCLRL  
TCLRH  
RD Active Delay  
RD Inactive Delay  
10  
10  
165  
150  
10  
10  
70  
60  
10  
10  
100  
80  
ns  
ns  
20  
8086  
A.C. CHARACTERISTICS (Continued)  
TIMING RESPONSES (Continued)  
8086  
8086-1  
Min  
8086-2  
Min  
Test  
Conditions  
Symbol  
Parameter  
Units  
ns  
Min  
Max  
Max  
Max  
TRHAV RD Inactive to Next TCLCL-45  
Address Active  
TCLCL-35  
TCLCL-40  
e
TCHDTL Direction Control  
Active Delay  
(Note 1)  
50  
30  
50  
30  
50  
30  
ns  
C
20100 pF  
L
for all 8086  
Outputs (In  
addition to 8086  
self-load)  
TCHDTH Direction Control  
Inactive Delay  
(Note 1)  
ns  
TCLGL GT Active Delay  
TCLGH GT Inactive Delay  
TRLRH RD Width  
0
85  
85  
0
38  
45  
0
50  
50  
ns  
ns  
ns  
0
0
0
2TCLCL-75  
2TCLCL-40  
2TCLCL-50  
TOLOH Output Rise Time  
TOHOL Output Fall Time  
20  
12  
20  
12  
20  
12  
ns From 0.8V to 2.0V  
ns From 2.0V to 0.8V  
NOTES:  
1. Signal at 8284A or 8288 shown for reference only.  
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.  
3. Applies only to T3 and wait states.  
4. Applies only to T2 state (8 ns into T3).  
21  
8086  
WAVEFORMS  
MAXIMUM MODE  
23145515  
22  
8086  
WAVEFORMS (Continued)  
MAXIMUM MODE (Continued)  
23145516  
NOTES:  
1. All signals switch between V  
and V unless otherwise specified.  
OL  
OH  
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.  
3. Cascade address is valid between first and second INTA cycle.  
2
3
W
W
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for  
pointer address is shown for second INTA cycle.  
5. Signals at 8284A or 8288 are shown for reference only.  
6. The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN)  
lags the active high 8288 CEN.  
7. All timing measurements are made at 1.5V unless otherwise noted.  
8. Status inactive in state just prior to T .  
4
23  
8086  
WAVEFORMS (Continued)  
ASYNCHRONOUS SIGNAL RECOGNITION  
23145517  
NOTE:  
1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.  
BUS LOCK SIGNAL TIMING (MAXIMUM MODE  
ONLY)  
RESET TIMING  
23145518  
23145519  
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)  
23145520  
NOTE:  
The coprocessor may not drive the buses outside the region shown without risking contention.  
24  
8086  
WAVEFORMS (Continued)  
HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)  
23145521  
25  
8086  
Table 2. Instruction Set Summary  
Mnemonic and  
Description  
Instruction Code  
DATA TRANSFER  
e
MOV  
Move:  
7 6 5 4 3 2 1 0  
1 0 0 0 1 0 d w  
1 1 0 0 0 1 1 w  
1 0 1 1 w reg  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
Register/Memory to/from Register  
Immediate to Register/Memory  
Immediate to Register  
mod reg r/m  
mod 0 0 0 r/m  
data  
e
data  
data if w  
1
e
data if w  
1
Memory to Accumulator  
1 0 1 0 0 0 0 w  
1 0 1 0 0 0 1 w  
1 0 0 0 1 1 1 0  
1 0 0 0 1 1 0 0  
addr-low  
addr-high  
addr-high  
Accumulator to Memory  
addr-low  
Register/Memory to Segment Register  
Segment Register to Register/Memory  
mod 0 reg r/m  
mod 0 reg r/m  
e
PUSH  
Push:  
Register/Memory  
Register  
1 1 1 1 1 1 1 1  
0 1 0 1 0 reg  
0 0 0 reg 1 1 0  
mod 1 1 0 r/m  
Segment Register  
e
POP  
Pop:  
Register/Memory  
Register  
1 0 0 0 1 1 1 1  
0 1 0 1 1 reg  
0 0 0 reg 1 1 1  
mod 0 0 0 r/m  
Segment Register  
e
XCHG  
Exchange:  
Register/Memory with Register  
Register with Accumulator  
1 0 0 0 0 1 1 w  
1 0 0 1 0 reg  
mod reg r/m  
e
IN  
Input from:  
Fixed Port  
1 1 1 0 0 1 0 w  
1 1 1 0 1 1 0 w  
port  
Variable Port  
e
OUT  
Output to:  
Fixed Port  
1 1 1 0 0 1 1 w  
1 1 1 0 1 1 1 w  
1 1 0 1 0 1 1 1  
1 0 0 0 1 1 0 1  
1 1 0 0 0 1 0 1  
1 1 0 0 0 1 0 0  
1 0 0 1 1 1 1 1  
1 0 0 1 1 1 1 0  
1 0 0 1 1 1 0 0  
1 0 0 1 1 1 0 1  
port  
Variable Port  
e
XLAT  
Translate Byte to AL  
e
LEA  
LDS  
LES  
Load EA to Register  
Load Pointer to DS  
Load Pointer to ES  
mod reg r/m  
mod reg r/m  
mod reg r/m  
e
e
e
LAHF  
SAHF  
Load AH with Flags  
Store AH into Flags  
e
e
PUSHF  
Push Flags  
Pop Flags  
e
POPF  
©
Mnemonics  
Intel, 1978  
26  
8086  
Table 2. Instruction Set Summary (Continued)  
Mnemonic and  
Description  
Instruction Code  
ARITHMETIC  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
e
ADD  
Add:  
Reg./Memory with Register to Either  
Immediate to Register/Memory  
Immediate to Accumulator  
0 0 0 0 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 0 0 1 0 w  
mod reg r/m  
mod 0 0 0 r/m  
data  
e
e
data  
data if s: w  
01  
e
e
data if w  
1
1
e
ADC  
Add with Carry:  
Reg./Memory with Register to Either  
Immediate to Register/Memory  
Immediate to Accumulator  
0 0 0 1 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 0 1 0 w  
mod reg r/m  
mod 0 1 0 r/m  
data  
data  
data if s: w  
01  
data if w  
e
INC  
Increment:  
Register/Memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 0 reg  
mod 0 0 0 r/m  
e
e
e
AAA  
BAA  
SUB  
ASCII Adjust for Add  
Decimal Adjust for Add  
Subtract:  
0 0 1 1 0 1 1 1  
0 0 1 0 0 1 1 1  
Reg./Memory and Register to Either  
Immediate from Register/Memory  
Immediate from Accumulator  
0 0 1 0 1 0 d w  
1 0 0 0 0 0 s w  
0 0 1 0 1 1 0 w  
mod reg r/m  
mod 1 0 1 r/m  
data  
e
e
data  
data if s w  
01  
01  
e
e
data if w  
1
1
e
SSB  
Subtract with Borrow  
Reg./Memory and Register to Either  
Immediate from Register/Memory  
Immediate from Accumulator  
0 0 0 1 1 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 1 1 w  
mod reg r/m  
mod 0 1 1 r/m  
data  
data  
data if s w  
data if w  
e
DEC  
Decrement:  
Register/memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 1 reg  
1 1 1 1 0 1 1 w  
mod 0 0 1 r/m  
mod 0 1 1 r/m  
e
e
NEG  
CMP  
Change sign  
Compare:  
Register/Memory and Register  
Immediate with Register/Memory  
Immediate with Accumulator  
0 0 1 1 1 0 d w  
1 0 0 0 0 0 s w  
0 0 1 1 1 1 0 w  
0 0 1 1 1 1 1 1  
0 0 1 0 1 1 1 1  
1 1 1 1 0 1 1 w  
1 1 1 1 0 1 1 w  
1 1 0 1 0 1 0 0  
1 1 1 1 0 1 1 w  
1 1 1 1 0 1 1 w  
1 1 0 1 0 1 0 1  
1 0 0 1 1 0 0 0  
1 0 0 1 1 0 0 1  
mod reg r/m  
mod 1 1 1 r/m  
data  
e
data  
data if s w  
01  
e
data if w  
1
e
e
e
AAS  
DAS  
MUL  
ASCII Adjust for Subtract  
Decimal Adjust for Subtract  
Multiply (Unsigned)  
mod 1 0 0 r/m  
mod 1 0 1 r/m  
0 0 0 0 1 0 1 0  
mod 1 1 0 r/m  
mod 1 1 1 r/m  
0 0 0 0 1 0 1 0  
e
IMUL  
AAM  
Integer Multiply (Signed)  
ASCII Adjust for Multiply  
e
e
DIV  
Divide (Unsigned)  
e
IDIV  
AAD  
CBW  
CWD  
Integer Divide (Signed)  
e
e
e
ASCII Adjust for Divide  
Convert Byte to Word  
Convert Word to Double Word  
©
Mnemonics  
Intel, 1978  
27  
8086  
Table 2. Instruction Set Summary (Continued)  
Mnemonic and  
Description  
Instruction Code  
LOGIC  
7 6 5 4 3 2 1 0  
1 1 1 1 0 1 1 w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
1 1 0 1 0 0 v w  
7 6 5 4 3 2 1 0  
mod 0 1 0 r/m  
mod 1 0 0 r/m  
mod 1 0 1 r/m  
mod 1 1 1 r/m  
mod 0 0 0 r/m  
mod 0 0 1 r/m  
mod 0 1 0 r/m  
mod 0 1 1 r/m  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
e
NOT  
Invert  
e
SHL/SAL  
Shift Logical/Arithmetic Left  
e
e
e
e
e
e
SHR  
SAR  
ROL  
ROR  
RCL  
RCR  
Shift Logical Right  
Shift Arithmetic Right  
Rotate Left  
Rotate Right  
Rotate Through Carry Flag Left  
Rotate Through Carry Right  
e
AND  
And:  
Reg./Memory and Register to Either  
Immediate to Register/Memory  
Immediate to Accumulator  
0 0 1 0 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 0 0 1 0 w  
mod reg r/m  
mod 1 0 0 r/m  
data  
e
e
data  
data if w  
1
1
e
e
data if w  
1
1
e
TEST  
And Function to Flags, No Result:  
Register/Memory and Register  
1 0 0 0 0 1 0 w  
mod reg r/m  
Immediate Data and Register/Memory  
Immediate Data and Accumulator  
1 1 1 1 0 1 1 w  
1 0 1 0 1 0 0 w  
mod 0 0 0 r/m  
data  
data  
data if w  
data if w  
e
OR  
Or:  
Reg./Memory and Register to Either  
Immediate to Register/Memory  
Immediate to Accumulator  
0 0 0 0 1 0 d w  
1 0 0 0 0 0 0 w  
0 0 0 0 1 1 0 w  
mod reg r/m  
mod 0 0 1 r/m  
data  
e
e
data  
data if w  
1
1
e
e
data if w  
1
1
e
XOR  
Exclusive or:  
Reg./Memory and Register to Either  
Immediate to Register/Memory  
Immediate to Accumulator  
0 0 1 1 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 1 0 1 0 w  
mod reg r/m  
mod 1 1 0 r/m  
data  
data  
data if w  
data if w  
STRING MANIPULATION  
e
REP  
Repeat  
1 1 1 1 0 0 1 z  
1 0 1 0 0 1 0 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
e
MOVS  
CMPS  
SCAS  
LODS  
STOS  
Move Byte/Word  
e
e
e
e
Compare Byte/Word  
Scan Byte/Word  
Load Byte/Wd to AL/AX  
Stor Byte/Wd from AL/A  
CONTROL TRANSFER  
e
CALL  
Call:  
Direct within Segment  
Indirect within Segment  
Direct Intersegment  
1 1 1 0 1 0 0 0  
1 1 1 1 1 1 1 1  
1 0 0 1 1 0 1 0  
disp-low  
mod 0 1 0 r/m  
offset-low  
disp-high  
offset-high  
seg-high  
seg-low  
Indirect Intersegment  
1 1 1 1 1 1 1 1  
mod 0 1 1 r/m  
©
Mnemonics  
28  
Intel, 1978  
8086  
Table 2. Instruction Set Summary (Continued)  
Mnemonic and  
Description  
Instruction Code  
e
JMP  
Unconditional Jump:  
7 6 5 4 3 2 1 0  
1 1 1 0 1 0 0 1  
1 1 1 0 1 0 1 1  
1 1 1 1 1 1 1 1  
1 1 1 0 1 0 1 0  
7 6 5 4 3 2 1 0  
disp-low  
7 6 5 4 3 2 1 0  
Direct within Segment  
Direct within Segment-Short  
Indirect within Segment  
Direct Intersegment  
disp-high  
disp  
mod 1 0 0 r/m  
offset-low  
seg-low  
offset-high  
seg-high  
Indirect Intersegment  
1 1 1 1 1 1 1 1  
mod 1 0 1 r/m  
e
RET  
Return from CALL:  
Within Segment  
1 1 0 0 0 0 1 1  
1 1 0 0 0 0 1 0  
1 1 0 0 1 0 1 1  
1 1 0 0 1 0 1 0  
0 1 1 1 0 1 0 0  
0 1 1 1 1 1 0 0  
Within Seg Adding Immed to SP  
Intersegment  
data-low  
data-high  
data-high  
Intersegment Adding Immediate to SP  
data-low  
disp  
e
JE/JZ  
Jump on Equal/Zero  
e
JL/JNGE  
Jump on Less/Not Greater  
or Equal  
disp  
e
JLE/JNG  
Jump on Less or Equal/  
Not Greater  
0 1 1 1 1 1 1 0  
0 1 1 1 0 0 1 0  
disp  
disp  
e
e
JB/JNAE  
JBE/JNA  
Jump on Below/Not Above  
or Equal  
Jump on Below or Equal/  
Not Above  
0 1 1 1 0 1 1 0  
0 1 1 1 1 0 1 0  
0 1 1 1 0 0 0 0  
0 1 1 1 1 0 0 0  
0 1 1 1 0 1 0 1  
disp  
disp  
disp  
disp  
disp  
e
JP/JPE  
Jump on Parity/Parity Even  
Jump on Overflow  
Jump on Sign  
e
e
JO  
JS  
e
e
JNE/JNZ  
JNL/JGE  
Jump on Not Equal/Not Zero  
Jump on Not Less/Greater  
or Equal  
0 1 1 1 1 1 0 1  
0 1 1 1 1 1 1 1  
0 1 1 1 0 0 1 1  
disp  
disp  
disp  
e
e
e
e
JNLE/JG  
JNB/JAE  
JNBE/JA  
JNP/JPO  
Jump on Not Less or Equal/  
Greater  
Jump on Not Below/Above  
or Equal  
Jump on Not Below or  
Equal/Above  
0 1 1 1 0 1 1 1  
0 1 1 1 1 0 1 1  
0 1 1 1 0 0 0 1  
0 1 1 1 1 0 0 1  
1 1 1 0 0 0 1 0  
1 1 1 0 0 0 0 1  
disp  
disp  
disp  
disp  
disp  
disp  
Jump on Not Par/Par Odd  
e
e
JNO  
JNS  
Jump on Not Overflow  
Jump on Not Sign  
e
LOOP  
Loop CX Times  
e
LOOPZ/LOOPE  
Loop While Zero/Equal  
e
LOOPNZ/LOOPNE  
Loop While Not  
Zero/Equal  
1 1 1 0 0 0 0 0  
1 1 1 0 0 0 1 1  
disp  
disp  
e
JCXZ  
Jump on CX Zero  
Interrupt  
e
INT  
Type Specified  
Type 3  
1 1 0 0 1 1 0 1  
1 1 0 0 1 1 0 0  
1 1 0 0 1 1 1 0  
1 1 0 0 1 1 1 1  
type  
e
e
INTO  
IRET  
Interrupt on Overflow  
Interrupt Return  
29  
8086  
Table 2. Instruction Set Summary (Continued)  
Mnemonic and  
Description  
Instruction Code  
7 6 5 4 3 2 1 0  
7 6 5 4 3 2 1 0  
PROCESSOR CONTROL  
e
e
e
e
e
CLC  
CMC  
STC  
CLD  
STD  
Clear Carry  
1 1 1 1 1 0 0 0  
1 1 1 1 0 1 0 1  
1 1 1 1 1 0 0 1  
1 1 1 1 1 1 0 0  
1 1 1 1 1 1 0 1  
1 1 1 1 1 0 1 0  
1 1 1 1 1 0 1 1  
1 1 1 1 0 1 0 0  
1 0 0 1 1 0 1 1  
1 1 0 1 1 x x x  
1 1 1 1 0 0 0 0  
Complement Carry  
Set Carry  
Clear Direction  
Set Direction  
e
CLI  
STI  
Clear Interrupt  
Set Interrupt  
e
e
HLT  
Halt  
e
WAIT  
Wait  
e
ESC  
Escape (to External Device)  
mod x x x r/m  
e
LOCK  
Bus Lock Prefix  
e
e
NOTES:  
if s w  
and  
if s w  
01 then 16 bits of immediate data form the oper-  
11 then an immediate data byte is sign extended  
e
e
e
e
e
AL  
AX  
CX  
DS  
ES  
8-bit accumulator  
16-bit accumulator  
Count register  
Data segment  
Extra segment  
to form the 16-bit operand  
e
e
e
if v  
0 then ‘‘count’’  
don’t care  
z is used for string primitives for comparison with ZF FLAG  
1; if v  
1 then ‘‘count’’ in (CL)  
e
x
Above/below refers to unsigned value  
e
Less  
Greater  
e
more positive;  
less positive (more negative) signed values  
SEGMENT OVERRIDE PREFIX  
e
e
1 then word instruction; if w  
if d  
if w  
1 then ‘‘to’’ reg; if d  
0 then ‘‘from’’ reg  
e
0 0 1 reg 1 1 0  
e
0 then byte instruc-  
REG is assigned according to the following table:  
tion  
if mod  
if mod  
e
e
11 then r/m is treated as a REG field  
e
e
e
16-Bit (w  
1)  
8-Bit (w  
0)  
Segment  
00 then DISP  
0*, disp-low and disp-high are  
absent  
000 AX  
001 CX  
010 DX  
011 BX  
100 SP  
101 BP  
110 SI  
111 DI  
000 AL  
001 CL  
010 DL  
011 BL  
100 AH  
101 CH  
110 DH  
111 BH  
00 ES  
01 CS  
10 SS  
11 DS  
e
16 bits, disp-high is absent  
e
if mod  
01 then DISP  
disp-low sign-extended to  
e
e
(BX)  
if mod  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
10 then DISP  
disp-high; disp-low  
e
e
a
a
a
a
a
a
a
a
000 then EA  
001 then EA  
010 then EA  
011 then EA  
100 then EA  
101 then EA  
110 then EA  
111 then EA  
(SI)  
(DI)  
(SI)  
(DI)  
DISP  
DISP  
DISP  
DISP  
e
e
e
e
e
e
e
e
e
e
e
e
e
e
(BX)  
(BP)  
(BP)  
(SI)  
(DI)  
(BP)  
(BX)  
a
DISP  
DISP  
DISP*  
DISP  
a
a
a
Instructions which reference the flag register file as a 16-bit  
object use the symbol FLAGS to represent the file:  
DISP follows 2nd byte of instruction (before data if re-  
quired)  
e
FLAGS  
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)  
e
e
e
*except if mod  
disp-low.  
00 and r/m  
110 then EA  
disp-high;  
©
Mnemonics  
Intel, 1978  
DATA SHEET REVISION REVIEW  
The following list represents key differences between this and the -004 data sheet. Please review this summa-  
ry carefully.  
1. The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III).  
2. Delete all ‘‘changes from 1985 Handbook Specification’’ sentences.  
30  

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