®
ICP-PIII
High-Performance
CPU Boards
Comp
USER’S MANUAL
Publication Number: PD00581013.004 AB
MAN-ICP-PIII
ICP-PIII
Preface
®
Preface
Contents
Unpacking and Special Handling Instruc-
tions............................................... 6
Revision History............................... 7
Three Year Limited Warranty.............. 8
1.0 ICP-PIII CPU ........................... 1-2
1.01 Interfacing ............................................................................................... 1-3
1.02 Peripherals ............................................................................................... 1-3
1.03 Software .................................................................................................. 1-3
1.04 Graphics .................................................................................................. 1-3
1.1 Specifications ......................... 1-4
1.2 Configuration.......................... 1-6
Table 1.20 ‘Processor Overview.................................................................................................. 1-6
Figure 1.20 ICP-PIII Overview..................................................................................................... 1-7
1.3 Software................................ 1-8
1.31 Linux........................................................................................................ 1-8
1.32 VentureCom............................................................................................. 1-8
1.33 Windows 2000......................................................................................... 1-8
1.34 Windows CE............................................................................................. 1-9
1.35 VxWorks................................................................................................... 1-9
1.36 OS-9 x86 ................................................................................................. 1-9
1.37 QNX ........................................................................................................ 1-9
1.38 Jbed ......................................................................................................... 1-9
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ICP-PIII
1.4 Hardware ............................. 1-10
1.41 Block Diagram........................................................................................ 1-10
Figure 1.41 Block Diagram....................................................................................................... 1-10
1.42 Connector Location ............................................................................... 1-11
Figure 1.42 Connector Locations .............................................................................................. 1-11
1.43 Connector Description ........................................................................... 1-11
Table 1.43 Connector Description ............................................................................................ 1-11
Table 1.43 Continued .............................................................................................................. 1-12
1.44 Front-Panel Features............................................................................... 1-12
Table 1.44 Front Panels ........................................................................................................... 1-12
Figure 1.44 Front-Panel Options .............................................................................................. 1-13
1.45 Interface Positions .................................................................................. 1-14
Figure 1.45 Interfaces .............................................................................................................. 1-14
2.0 Memory Map........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
Table 2.00 UMB Reservations for ISA ......................................................................................... 2-3
Table 2.01 Port Addressing ........................................................................................................ 2-3
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
2.2 Memory Mapped Peripherals ..... 2-5
2.3 Interrupt Routing .................... 2-5
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-6
2.4 Inova PIII Device List................ 2-7
Table 2.40 Legacy I/O Map (ISA Compatible) ............................................................................ 2-7
2.5 Interrupt Configuration ............ 2-8
Table 2.50 CompactPCI Bus Interrupts ....................................................................................... 2-8
2.6 Timer / Counter....................... 2-9
2.7 Watchdog............................... 2-9
3.0 CompactPCI J1/J2 Connector... 3-3
3.01 CompactPCI Connector ........................................................................... 3-3
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector ...................................................... 3-3
3.02 ICP-PIII Connector J1 and J2 ..................................................................... 3-3
Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment ............................................... 3-4
Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ............................ 3-5
Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..................... 3-6
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)...................... 3-7
Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) ..................... 3-8
Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration .......................................................... 3-9
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ICP-PIII
Preface
3.1 CompactPCI Backplane .......... 3-10
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ................................ 3-11
®
3.2 Interfaces............................. 3-12
3.21 J7 & J12 Fast Ethernet ............................................................................ 3-12
Figure 3.21 RJ45 Pinout ........................................................................................................... 3-12
Table 3.21 Ethernet Connector Signals ..................................................................................... 3-12
3.22 J17 VGA Interface ................................................................................... 3-13
Figure 3.22 High-Density D-Sub VGA Interface Pinout .............................................................. 3-13
Table 3.22 Video Output Connector Signals ............................................................................. 3-13
Table 3.22b Video Resolutions ................................................................................................. 3-14
3.23 J16 PanelLink Interface ........................................................................... 3-15
Figure 3.23 PanelLink Interface Connector ............................................................................... 3-15
Table 2.12 PanelLink Interface ................................................................................................. 3-15
2.24 J16 GigaSTAR Interface........................................................................... 3-16
Figure 2.24 GigaSTAR D-Sub Interface Pinout........................................................................... 3-16
Table 2.11 GigaSTAR Interface................................................................................................ 3-16
3.25 J19 USB Interface ................................................................................... 3-17
Figure 3.25 USB Interface Pinout.............................................................................................. 3-17
Table 3.25 USB Connector Signals ........................................................................................... 3-17
3.26 J15 FireWire Interface ............................................................................. 3-18
Figure 3.26 FireWire Interface Pinout........................................................................................ 3-18
Table 3.26 FireWire Connector Signals ..................................................................................... 3-18
3.27 J20 Infrared (iRdA) Interface ................................................................... 3-19
3.28 J20 Reset Button..................................................................................... 3-19
3.29 J14 FLASH Interface ................................................................................ 3-19
3.30 J18 Floppy Disk Interface........................................................................ 3-19
3.31 Connecting the PIII to the Inova IPB-FPE8 .............................................. 3-20
Figure 3.31 CPU to IPB-FPE8 Connection .................................................................................. 3-20
3.32 Connecting the PIII to the Inova ICP-HD-1 ............................................. 3-21
Figure 3.32 CPU to ICP-HD-1 Connection................................................................................. 3-21
3.33 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-22
Figure 3.33 CPU to IPB-FPE12 Connection ................................................................................ 3-22
3.34 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-23
Figure 3.34 CPU to IPB-FPE12 Connection ................................................................................ 3-23
3.35 Connecting the PIII to the ICP-FD-1 ....................................................... 3-24
Figure 3.35 CPU to Slim-Line Floppy Disk Connection ............................................................... 3-24
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ICP-PIII
A1 IPB-FPE8 CPU Extension ......... A-2
A1.1 J11 Interface for COM1, Mouse & Keyboard ............................................ A-2
A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)....................................................... A-2
Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU .......................................................... A-2
A1.3 Stand-Alone IPB-FPE8............................................................................... A-3
Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8 ............................................................... A-3
A1.4 IPB-FPE8MS (Theme Variation) ................................................................. A-4
Figure A1.4 Piggyback Interface IPB-FPE8MS .............................................................................. A-4
Table A1.4 IPB-FPE8MS Connector Description ........................................................................... A-4
A1.5 IPB-FPE8MS Description ........................................................................... A-5
Figure A1.5 Top & Bottom Views of the IPB-FPE8MS ................................................................... A-5
Table A1.5 Standard Hard-Disk & Floppy Disk Connectors .......................................................... A-5
A1.6 Keyboard Interface................................................................................... A-6
Figure A1.6 Keyboard Interface Pinout ...................................................................................... A-6
Table A1.6 Keyboard Connector Signals ..................................................................................... A-6
A1.7 Mouse Interface ....................................................................................... A-6
Figure A1.7 Mouse Interface Pinout............................................................................................ A-6
Table A1.7 Mouse Connector Signals ......................................................................................... A-6
A1.8 COM1 Interface ....................................................................................... A-7
Figure A1.8 COM1 Interface Pinout............................................................................................ A-7
Table A1.8 COM1 Connector Signals ......................................................................................... A-7
B1 ICP-HD CPU Extension ............. B-2
B1.1 J11, J13 Interfaces .................................................................................... B-2
B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)...................................................... B-2
Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU......................................................... B-2
B1.3 IDE Carrier Board ICP-HD-1 ...................................................................... B-3
Figure B1.3 IDE Carrier Board ICP-HD1 ...................................................................................... B-3
Table B1.3 ICP-HD-1 Connector Description ............................................................................... B-4
B1.4 ICP-HDE8MS (Theme Variation) ............................................................... B-4
Figure B1.4 IDE Carrier ICP-HDE8MS.......................................................................................... B-4
Table B1.4 IPB-HDE8MS Connector Description .......................................................................... B-5
B1.5 ICP-HDE8MS Description ......................................................................... B-6
Figure B1.5 Top & Bottom Views of the ICP-HDE8MS.................................................................. B-6
B1.6 Keyboard Interface ................................................................................... B-7
Figure B1.6 Keyboard Interface Pinout....................................................................................... B-7
Table B1.6 Keyboard Connector Signals ..................................................................................... B-7
B1.7 Mouse Interface ....................................................................................... B-7
Figure B1.7 Mouse Interface Pinout ............................................................................................ B-7
Table B1.7 Mouse Connector Signals.......................................................................................... B-7
B1.8 COM1 & COM 2 Interfaces...................................................................... B-8
Figure B1.8 COM1 & COM2 Interface Pinout ............................................................................. B-8
Table B1.8 COM1 & COM2 Connector Signals........................................................................... B-8
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ICP-PIII
Preface
B1 IPM-ATA CPU Extension ........... B-2
B1.1 J1 Interfaces ............................................................................................. B-2
Figure B1.1a Dedicated IPM-ATA Backplane................................................................................ B-2
B1.1 J1 Interfaces (Contd.) ............................................................................... B-3
Figure B1.1b The Complete Connection Picture........................................................................... B-3
®
B1.2 IPM-ATA-HD............................................................................................. B-4
Figure B1.2 IPM-ATA-HD Board Layout ....................................................................................... B-4
Table B1.2 IPM-ATA-HD Jumper Description ............................................................................... B-4
B1.3 IPM-ATA-CF.............................................................................................. B-5
Figure B1.3 IPM-ATA-CF Board Layout ........................................................................................ B-5
Table B1.3 IPM-ATA-CF Jumper Description................................................................................. B-5
B1.4 IPM-ATA-PCMCIA ..................................................................................... B-6
Figure B1.4 IPM-ATA-PCMCIA Board Layout ............................................................................... B-6
Table B1.4 IPM-ATA-PCMCIA Jumper Description ........................................................................ B-6
B1.5 Device Compatibility................................................................................ B-7
Table B1.5 Compatibility List...................................................................................................... B-7
C1 IPB-FPE12 CPU Extension ........ C-2
C1.1 J13 Interface for LPT1 & COM2 ............................................................... C-2
C1.2 IPB-FPE12 & Front-panel (4HP or 12HP) .................................................. C-2
Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ C-2
C1.3 LPT1 & COM2 Piggyback ........................................................................ C-3
Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12 .............................................................. C-3
Table C1.3 IPB-FPE12 Connector Description .............................................................................. C-4
C1.4 LPT1 Interface.......................................................................................... C-5
Figure C1.6 LPT1 Interface Pinout .............................................................................................. C-5
Table C1.6 LPT1 Connector Signals ............................................................................................ C-5
C1.5 COM2 Interface....................................................................................... C-6
Figure C1.5 COM2 Interface Pinout ........................................................................................... C-6
Table C1.5 COM2 Connector Signals ......................................................................................... C-6
D1 IPB-RIO CPU Extension............ D-2
D1.1 IPB-RIO-HD-FD ....................................................................................... D-2
Figure D1.1 IPB-RIO-HD-FD ....................................................................................................... D-2
D1.2 IPB-RIO-HD-LPT-(FLEX) ........................................................................... D-3
Figure D1.2 IPB-RIO-HD-LPT-(FLEX)............................................................................................ D-3
D1.3 IPB-RIO-C-SHORT ................................................................................... D-4
Figure D1.3 IPB-RIO-C-SHORT ................................................................................................... D-4
Table D1.3 Rear I/O Type ‘C’ ..................................................................................................... D-4
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D1.4 IPB-RIO-C-80MM.................................................................................... D-5
Figure D1.4 IPB-RIO-C-80MM.................................................................................................... D-5
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Preface
ICP-PIII
Unpacking and Special Handling
Instructions
This product has been designed for a long and fault-free life; nonetheless, its life expectancy can
be severely reduced by improper treatment during unpacking and installation.
Observe standard antistatic precautions when changing piggybacks, ROM devices, jumper set-
tings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not
placed on conductive surfaces as these can cause short circuits, damage the batteries or disrupt
the conductive tracks on the board.
Do not exceed the specified operational temperature ranges of the board version ordered. If
batteries are present, their temperature restrictions must be taken into account.
Keep all the original packaging material for future storage or warranty shipments. If it is necessary
to store or ship the board, re-pack it as it was originally packed.
Before returning this product for repair, please ask for an RMA (Returned Material Authorization)
number and supply the following information:
í
í
í
í
Company name, contact person, shipping address and invoice address
Product name and serial number
Failure or fault description
Clearly write the RMA number on the outside of the transportation carton.
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ICP-PIII
Preface
Revision History
®
Revision History
Manual
Publication Number PD00581013.XXX
Issue Brief Description of Changes
MAN-ICP-PIII
Date of Issue
31/11/2000
15/08/2001
21/09/2001
15/02/2002
Author
AB
PD00581013.001 Preliminary, First Release; All pages revised
PD00581013.002 Updated to include Radeon VE and Rear I/O options
PD00581013.003 Final Version - Included Appendix A-D I/O Modules
PD00581013.004 Specs. Updated & Rear I/O Table Corrected
AB
AB
AB
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Preface
ICP-PIII
Three Year Limited Warranty
Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware
warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are
valid unless the consumer has the expressed written consent of Inova.
Inova warrants their own products (excluding software) to be free from defects in workmanship
and materials for a period of 36 consecutive months from the date of purchase. This warranty is
not transferable nor extendible to cover any other consumers or long term storage of the product.
This warranty does not cover products which have been modified, altered, or repaired by any
other party than Inova or their authorized agents. Furthermore, any product which has been, or
is suspected of being damaged as a result of negligence, misuse, incorrect handling, servicing or
maintenance; or has been damaged as a result of excessive current/voltage or temperature; or has
had its serial number(s), any other markings, or parts thereof altered, defaced, or removed will
also be excluded from this warranty.
A customer who has not excluded his eligibility for this warranty may, in the event of any claim,
return the product at the earliest possible convenience, together with a copy of the original proof
of purchase, a full description of the application it is used on, and a description of the defect; to
the original place of purchase.
Pack the product in such a way as to ensure safe transportation (we recommend the original
packing materials), whereby Inova undertakes to repair or replace any part, assembly or sub-
assembly at our discretion; or, to refund the original cost of purchase, if appropriate.
In the event of repair, refund, or replacement of any part, the ownership of the removed or
replaced parts reverts to Inova, and the remaining part of the original guarantee, or any new
guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired
items. Any extensions to the original guarantee are considered gestures of goodwill, and will be
defined in the “Repair Report” returned from Inova with the repaired or replaced item.
Other than the repair, replacement, or refund specified above, Inova will not accept any liability
for any further claims which result directly or indirectly from any warranty claim. We specifically
exclude any claim for damage to any system or process in which the product was employed, or
any loss incurred as a result of the product not functioning at any given time. The extent of
Inova’s liability to the customer shall not be greater than the original purchase price of the item
for which any claim exists.
Inova makes no warranty or representation, either expressed or implied, with respect to its prod-
ucts, reliability, fitness, quality, marketability or ability to fulfil any particular application or pur-
pose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for
any given task remains the purchaser’s. In no event will Inova be liable for direct, indirect, or
consequential damages resulting from the use of our hardware or software products, or docu-
mentation; even if we were advised of the possibility of such claims prior to the purchase of, or
during any period since the purchase of the product. Please remember that no Inova employee,
dealer, or agent are authorized to make any modification or addition to the above terms, either
verbally or in any other form written or electronically transmitted, without consent.
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ICP-PIII
Product Overview
®
1
Product Overview
Overview Contents
1.0 ICP-PIII CPU ........................... 1-2
1.01 Interfacing ............................................................................................... 1-3
1.02 Peripherals ............................................................................................... 1-3
1.03 Software .................................................................................................. 1-3
1.04 Graphics .................................................................................................. 1-3
1.1 Specifications ......................... 1-4
1.2 Configuration.......................... 1-6
Table 1.20 ‘Processor Overview.................................................................................................. 1-6
Figure 1.20 ICP-PIII Overview..................................................................................................... 1-7
1.3 Software................................ 1-8
1.31 Linux........................................................................................................ 1-8
1.32 VentureCom............................................................................................. 1-8
1.33 Windows 2000......................................................................................... 1-8
1.34 Windows CE............................................................................................. 1-9
1.35 VxWorks................................................................................................... 1-9
1.36 OS-9 x86 ................................................................................................. 1-9
1.37 QNX ........................................................................................................ 1-9
1.38 Jbed ......................................................................................................... 1-9
1.4 Hardware ............................. 1-10
1.41 Block Diagram........................................................................................ 1-10
Figure 1.41 Block Diagram....................................................................................................... 1-10
1.42 Connector Location ............................................................................... 1-11
Figure 1.42 Connector Locations .............................................................................................. 1-11
C
1.43 Connector Description ........................................................................... 1-11
Table 1.43 Connector Description ............................................................................................ 1-11
Table 1.43 Continued .............................................................................................................. 1-12
1.44 Front-Panel Features............................................................................... 1-12
Table 1.44 Front Panels ........................................................................................................... 1-12
Figure 1.44 Front-Panel Options .............................................................................................. 1-13
1.45 Interface Positions .................................................................................. 1-14
Figure 1.45 Interfaces .............................................................................................................. 1-14
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Product Overview
1.0 ICP-PIII CPU
ICP-PIII
The ICP-PIII is a high-performance 3U CompactPCI single-board Socket 370 based universal CPU
that satisfies the needs of a wide range of industrial automation, military, medical, aerospace,
imaging, telecommunications, process control and embedded/OEM applications. The powerhouse
in any application, Inova’s Socket 370 based high-performance 3U CompactPCI CPU is packed
with a feature set unheard of on such a small scale. With 128MByte on-board SDRAM with BIOS
controlled ECC, the ICP-PIII suits the demands placed by modern operating systems. In addition,
performance scalability is assured through the broad selection of Intel Pentium III and Celeron
BGA2 (mobile) and FC-PGA devices.
Conforming to the latest PICMG CompactPCI specification the ICP-PIII has a colourful feature set
of rear I/O options and supports basic hot-swap. Being of a universal design, both 5.0 and 3.3V
I/O signalling voltages are possible without modification.
Although the CPU measures just 160mm by 100mm it is fabricated using the latest 12-layer PCB
technology and with over 4800 PCB links and 6550 solder points the ICP-PIII is truly a miracle of
engineering achievement.
Inova’s high-performance, high-density 3U PIII board provides support on all three major serial
networking levels that include Fast Ethernet, FireWire and USB. To enable so much functionality to
exist in such a small footprint, the ICP-PIII is able to host the I/O on either the front-panel or in the
form of rear I/O or even both. Implementing the latest Intel chipsets and processors available for
the embedded market the ICP-PIII is adequately equipped to provide support for all major operat-
ing systems and off-the-shelf application software.
The built-in graphic solution not only saves space within a rack that would otherwise be taken-up
by an additional graphics board, but due to its extremely efficient use of hardware real-estate,
costs can be cut too. Modularity is further assured through the use of dedicated plug-in SDRAM
modules.
On-board peripheral connectors allow the CPU to be enhanced to include mouse, keyboard,
COM and LPT functions. Slim-line 1.44MByte floppy disk and EIDE interfaces provide the mass-
storage possibilities and due to the rear I/O possibilities, one of the EIDE channels (2 devices) can
be used for remote connection of hard disks or CD-ROM drive etc.
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ICP-PIII
Product Overview
1.01 Interfacing
®
For maximum communication flexibility, multiple interfaces satisfying different industrial stand-
ards are implemented. LAN applications can take advantage of Inova’s 10BaseT/100BaseTx (dual)
Ethernet implementation or, if high-speed system-level serial interfacing is required, the built-in
400/100 Mbit/s FireWire port is available. Peripherals may be connected to the standard USB or,
as an option, the on-board PCI bus allows support of custom I/O piggybacks conforming to
Inova’s open specification.
1
The Intel 21554 non-transparent PCI/PCI bridge is utilised for multiprocessing applications equipped
with a Master and Slave CPU in the same system.
1.02 Peripherals
The ICP-PIII supports standard PC peripherals like floppy disk, hard disk and CD ROM. Notebook
style hard disks may be connected directly to the base-board (2-slot) and possess their own front-
panel offering COM ports and PS-2 style connectors for mouse and keyboard.
1.03 Software
The following operating systems have been verified with Inova’s PIII, 3U CompactPCI CPU:
{
{
{
{
{
{
{
{
{
Linux
Windows® NT® & VenturCom RTX® (Real-Time Extension)
Windows® 2000
Windows ® CE
Windows 9x
Windriver VxWorks®
QNX®
Esmeralda Technology Jbed® (under development)
Solaris x86
®
All readily available application software designed for operation on the standard x86 architecture
will execute without modification.
C
1.04 Graphics
The Lynx3DM graphic controller is a highly integrated 128-bit GUI (Graphical User Interface)
engine supporting dual independent graphic displays. Screen resolutions up to 1600 x 1200
pixels with 24-bit (True Colour) are supported.
The introduction of the ATI Radeon VE, with its 16MByte video RAM and superior 3D acceleration
& hardware MPEG-2 support, enables screen resolutions up to 2048 x 1536 pixels to be driven.
Dual video and TFT dual-scan/single-scan colour panels are supported with configurable colour
Ȣ
depths. In addition, Inova’s ICP-PIII caters for the needs of the GigaST R, PanelLink™ and LVDS
user.
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Product Overview
1.1 Specifications
ICP-PIII
Processor
Socket 370 BGA (mobile) or FC-PGA based Intel Pentium III or Celeron
Pentium III
Up to 1000MHz
(100MHz PSB, 256kByte L2 cache)
Mobile PIII
Up to 700MHz BGA2 package with interposer
(100MHz PSB, 256kByte L2 cache)
Mobile Celeron BGA2 package with interposer
(100Mz PSB, 128kByte L2 cache)
L2 Cache
Memory
128/256kByte L2 cache depending on processor
128MByte soldered synchronous DRAM with optional BIOS activated
ECC feature. Additional Piggyback provides additional 128MByte,
or 384MByte
FLASH-Disk
Battery
Available as an option (Disk-on-Chip™) providing up to 500MByte FLASH
Lithium cell for RTC (NV-RAM) with a lifetime > 8 years
North Bridge
440BX North Bridge 82443BX supporting:
Ī 100MHz system bus DRAM controller with 64bit, 100MHz
SDRAM interface
Ī ECC support
Ī AGP 2X interface (66/133MHz)
Ī Power management
South Bridge
M1543C:
Ī PCI/ISA Bridge
Ī Super I/O: 1 Floppy Disk Controller, 1 Parallel Port, 2 Serial Ports
Ī Fast IR
Ī IDE Controller (4 devices)
Ī Ultra 66 DMA support
Ī 12Mbit/s USB controller
Ī Interrupt controller
Ī Power Management Unit
Ī Full support for ACPI and OS directed power management
Ī Mouse & keyboard controller
Graphics
Lynx3DM or Radeon VE graphic accelerator
Ī 8/16Mbyte SGRAM/SDRAM
Ī 3D graphics, DVD & MPEG-2 support
Ī Multi-Display
Ī Dual View support under Microsoft Windows®9x, Windows®NT®
& Windows®2000
Ī CRT / TFT resolutions up to 2048x1536
Ȣ
Ī GigaST R / PanelLink™ or TFT Piggyback
Dual display option or TFT will require dedicated front-panel.
Recovery BIOS FLASH Recovery BIOS
Watchdog Programmable up to 10 minutes; issues NMI or Reset
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ICP-PIII
Product Overview
®
1
PCI/PCI
Intel 21150 transparent bridge (Master) or Intel 21554 non-transpar-
ent PCI/PCI bridge for multiprocessing (Slave) operation with Basic
Hot-Swap support (PICMG 2.1 R1.0), Serialized interrupts and univer-
sal (3.3/5.0V) V I/O support
On-Board I/O
Rear I/O
Ī 10/100 MBit/s Ethernet (Intel 82559)
Ī optional 2nd independent Fast Ethernet
Ī Up to 2x 12Mbit/s USB
Ī Up to 2x 400Mbit/s FireWire interfaces
Standard to all CPU variants is option ‘C’ which provides 2nd FireWire
channel, 2nd USB channel, LPT1 (Floppy), EIDE and loudspeaker.
Other I/O configurations including customized are possible.
Mass Storage
Front-Panels
1.44MByte 3.5” floppy drive and EIDE (flex cable/rear I/O) support-
ing 2 pairs (Master/Slave) hard-disks or CD ROMs
Optional 4TE front-panel extension provides:
COM1, COM2, keyboard, PS-2 mouse
Extended front-panel (4TE) provides:
COM2, LPT1
Connectors
USB (USB), RJ45 (Ethernet), 6-pin FireWire (FireWire), 15-pin D-Sub
(PanelLink), 15-pin high-density D-Sub (VGA), 9-pin D-Sub
(GigaST R)
Ȣ
CompactPCI
Mechanics
PICMG 2.0 R3.0, 32-bit, 33MHz system slot interface with 7 Master
(DMA) support. Dual-slot operation
3U (100 x 160 x 21mm) 4 TE
3U (100 x 160 x 42mm) 8 TE
3U (100 x 160 x 63mm) 12 TE
Power Cons.
25W typ. PIII @ 850MHz (Lynx)
21W typ. PIII @ 700MHz (Lynx)
12W typ. Mobile PIII @ 500MHz (Lynx)
Software
Support
Windows® NT®, Windows® 2000, Windows® 9x, Linux,
VxWorks®, QNX®
Mass
220g (4TE)
C
Oper. Temp.
0°C to +60°C (Ambient)*
Storage Temp. -40°C to +85°C (400MHz Mobile [Lynx] only)
Extended Temp. -40 to +85°C (Seleted CPUs only)
Humidity
5% to 95% (non-condensing)
Three-year limited warranty
Warranty
Conformance
PICMG 2.0 R3.0
CE
*Note: Any CPU fitted with HD, FD or CD-ROM etc. has a max. operational temperature of 50
CPUs without HD or PC inter faces ar e single-slot (4TE) for ‘pr ocessor speeds ≤ 700MHz.
Mobile processors are passively cooled - installation MUSThave >0.3m/s air flow!
°C
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Page1-5
Product Overview
1.2 Configuration
ICP-PIII
Inova’s high-performance, high-density 3U PIII board supports functionality and connectivity on
all three major serial networking levels like Fast Ethernet, FireWire and USB as well as most state-of-
the-art fieldbus standards such as PROFIBUS, CAN, Interbus, and LON.
Three CPU groups exist to cater for the needs of all aspects of CompactPCI integration: The high-
end typically supports 128MBytes on-board soldered SDRAM, Lynx3DM graphic controller with
8MByte SGRAM and all I/O. For standard applications, the same base layout is utilized however,
the soldered SDRAM, graphic controller and many of the peripheral connections are absent for
use in typical embedded applications. Finally, for multiprocessing applications, the PCI/PCI trans-
parent bridge is replaced by the 21554 non-transparent version.
Table 1.20 ‘Processor Overview
CPU Family
Processor
Intel PIII
CPU Speed(s)
400 to 850MHz
400 to 850MHz
400 to 700MHz
Multi-Processing
Package
FC-PGA
ICP-PIII-fegsm
No
Yes
ICP-SPIII-fegsm
ICP-xxPIII-fegsm
Intel PIII
FC-PGA
Mobile PIII/Celeron
Yes / No
BGA2 (Interposer)
All CPU family members can possess up to 512MByte SDRAM with BIOS controlled ECC through
a combination of soldered memory units and plug-in modules. FLASH up to 512MByte may be
realised in a similar manner. All CPUs are equipped with a shielded front-panel with typically VGA,
USB, FireWire and Fast Ethernet interfaces installed. Other front-panels are available with mouse,
keyboard, COM, LPT, TFT, PanelLink or dual Ethernet interfaces. The choice of Lynx 3DM or ATI
Radeon VE graphic controller complete with 8/16MByte video RAM is available as an option as is
multiprocessing.
Page1-6
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Product Overview
Figure 1.20 ICP-PIII Overview
®
1
100/10Mbit
Ethernet
FireWire
USB
VGA,
Ȣ
GigaST R
PanelLink
LVDS,
FLASH Extension:
Up to 512MByte
Socket 370 or
BGA2 based
Intel Pentium III
or Celeron
TFT,
GigaST R,
PanelLink or LVDS
Ȣ
Optional Lynx3DM or
Radeon VE Graphic
Controller (Under-
side)
North-Bridge
PCI Interface for
Piggyback Extensions
128MB or 384MB
SDRAM Extension
512MByte in Development
Optional
Multiprocessing
C
Inova’s CPUs have been prepared for rear I/O operation. Currently (RIO-C), EIDE, FireWire2, USB2,
LPT1 and the loudspeaker signals are present on the backplane (if requested at time of order.)
Other options may also be available (including customer specific) but are not referred to in this
user’s handbook. In order to take full advantage of the rear I/O features, the CompactPCI back-
plane needs to support them. Inova provides two standard versions; one has the J2 connector at
the CPU location extended to the rear of the backplane while the other version has all slots fitted
with the J2 connector on both the front and rear.
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Page1-7
Product Overview
ICP-PIII
1.3 Software
1.31 Linux
Being a modern operating system, Linux executes a 32-bit architecture, uses pre-emptive multi-
tasking, has protected memory, supports multiple users, and has rich support for networking,
including TCP/IP. Linux was originally written for Intel’s 386 architecture, but now runs on a wide
variety of hardware platforms including the full x86 family of processors as well as Alpha, SPARC,
and PowerPC.
Linux’s architecture also creates a more reliable and inherently stable system through the use of
protected memory and pre-emptive multitasking. Protected memory prevents an error in one
application from bringing down the entire system, and genuine multitasking means that a bottle-
neck in one application does not hold up the entire system. Linux also maintains a very clean
separation between user processes and kernel processes. While other server class operating sys-
tems use protected memory this feature is prone to failure if faulty applications are allowed to
invade kernel space with their processes.
1.32 VentureCom
Hard, real-time scalability and embedded operation extensions are required for Windows NT by
HAL modification for deterministic interrupt handling at multiple priority levels. This approach
achieves response times in the µs range and reduces hardware resource requirements while main-
taining full compatibility with the enormous range of standard software and device drivers written
for the Windows NT operating system.
1.33 Windows 2000
Windows 2000 is highly reliable and available 32-bit OS.
Support for USB devices allows connection of peripherals without the need to reboot the system
and unlike Windows NT 4.0 support is also provided for the IEE1394a (FireWire) devices. Finally,
secure, wireless communication between two Windows 2000-based computers is possible using
the popular IrDA infrared protocol.
Removable storage devices such as DVD and Device Bay are supported as are new display devices
such as Accelerated Graphics Port (AGP), multiple video cards and monitors, OpenGL 1.2, DirectX®
7.0 API, and Video Port Extensions.
With Plug and Play automatic installation of new hardware is possible with only minimal configu-
ration. More than 12,000 devices now support this functionality.
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Doc. PD00581013.004
ICP-PIII
Product Overview
1.34 Windows CE
®
Microsoft® Windows CE is an operating system designed for a wide variety of embedded systems
and products, from hand-held PCs and consumer electronic devices to specialized industrial con-
trollers and embedded communications devices. The Windows CE operating system has proved
itself capable of handling the most demanding 32-bit embedded applications by bringing the full
power of the Microsoft's 32-bit programming and operating systems technology to the embed-
ded systems designer. Windows CE is actually a collection of operating system modules and com-
ponents that can be selected and configured to meet the needs of a specific embedded applica-
tion or product.
1
1.35 VxWorks
WindRiver’s run-time system solution is a high-performance RTOS with a scalable microkernel and
sophisticated networking facilities - like TCP/IP networking across various media.
The open architecture provides efficient support of PC-based architectures. Flexible, intertask com-
munication, µs interrupt handling, POSIX 1003.1b real-time extensions, fast and flexible I/O sys-
tem etc. are some of the many key features.
1.36 OS-9 x86
Microware’s real-time operating system has a track record that has been proved in the industrial/
embedded market and has continued to provide reliable intelligence to sophisticated applica-
tions. OS-9 x86’s flexibility, modularity and reliability in conjunction with a rich driver structure
allow its use in I/O intensive applications.
1.37 QNX
This solution ports the Win32 API to a QNX kernel. The Win32 API aims to define a standard for
developing open systems applications that are optimized to run on ‘Wintel’ platforms. This oper-
ating system evolves around a small microkernel RTOS that produces a protected-mode, POSIX-
certified API. Being fully modular and scalable, this technology creates the smallest footprint that
is beneficial to high-end server applications.
C
1.38 Jbed
Esmertec’s Jbed is a new generation of real-time operating system. Java-based innovation provides
unprecedented safety and ease of use without compromising resource efficiency (native processor
speed) or hard real-time performance. In addition, advanced features are implemented such as
modularity, hot updates, deadline-driven scheduling admission testing as well as a fast and pro-
ductive cross-development.
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Page1-9
Product Overview
1.4 Hardware
ICP-PIII
1.41 Block Diagram
Figure 1.41 Block Diagram
x86 ‘processor
Pentium III,
Celeron
Silicon Motion
VGA
Lynx3DM
Ȣ
PanelLink
TFT
GigaST
R
Socket
FC-PGA 370
or
or
AGP
ATI Radeon VE
Graphics
SDRAM (ECC)
BGA2 (Mobile)
8/16 MByte
SGRAM
128 MByte
On-Board
10/100 Mbit/s
Ethernet
Intel 82559 Ethernet
Intel 82559 Ethernet
128/384 MByte
Piggyback
North Bridge
PC100
Intel 82443BX
Extension
10/100 Mbit/s
Ethernet
PCI/PCI Bridge
System Slot
or
PCI Bus
400 Mbit/s
FireWire
PL
TSB 12LV23
Peripheral Device
USB
IRQ
2x USB
Mouse/Key.
COM1/2
LPT1
South
Bridge
PS/2
COM 1/2
LPT 1
FDC
EIDE
Power
Floppy
ALi 1543C
Hard-Disk
(2 Channels. 4 Devices)
PCI2ISA
Piggyback
ISA Bus
Up to 512 MByte
M-Systems
Disk-On-Chip™
RTC
FLASH (BIOS)
This block diagram is applicable to all Inova’s PIII-based CPUs. Components and/or functionality
may change without notice. An extra PCI load can be attached to the on-board 80-pin header. An
open specification is available allowing developers to manufacture their own PCI device.
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Doc. PD00581013.004
ICP-PIII
Product Overview
1.42 Connector Location
®
Figure 1.42 Connector Locations
1
J4
J3
J1
KEY
J6
CPCI-CONNECTOR
J2
J16
PENTIUM III
J18
J11
J13
J10
J14
J9
J17
J19
J15
J7
J20
1.43 Connector Description
C
Table 1.43 Connector Description
Connector
Description
J1, J2
J3, J4
J6
CompactPCI Interface Connector
SDRAM Piggyback Expansion Interface Connector for up 384MBytes
PCI Expansion Slot
J7
10BaseT/100BaseTx Fast Ethernet Interface
J12
Optional Independent 10BaseT/100BaseTx Fast Ethernet Interface
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Product Overview
ICP-PIII
Table 1.43 Continued
Connector
Description
J9, J10
J11
J13
J141)
J15
J16
J17
J18
J19
J20
1)
Hard Disk Interface
COM1, Keyboard and Mouse Interfaces
COM2 and LPT1 Interfaces
FLASH Extension Piggyback Connector for up to 288MBytes
FireWire Interface
TFT Flat-Panel, PanelLink™ or GigaSTAR Interface
15-Pin High Density D-Sub VGA Graphics Interface
1.4 MByte Slim-Line Floppy Drive Interface
USB Interface
iRDA, Reset
DOC FLASH greater than 288MByte may be available
1.44 Front-Panel Features
Table 1.44 Front Panels
Interface
Ethernet
FireWire
USB
Description & Location
RJ45 Connector Common to all 4TE CPU Front-Panels
Firewire Connector on 4TE CPU Front-Panel
USB Connector on 4TE CPU Front-Panel
VGA
15-Pin High-Density D-Sub Connector on 4TE CPU Front-Panel
PS-2 Style on 8TE CPU Front-Panel
Keyboard
Mouse
COM1
PS-2 Style on 8TE CPU Front-Panel
9-Pin D-Sub on 8TE CPU Front-Panel
COM21)
LPT1
9-Pin D-Sub on 8TE CPU Front-Panel or 4/12TE CPU Extension
25-Pin D-Sub on 4/12TE CPU Extension
PanelLink2) 15-Pin D-Sub on 4TE CPU Front-Panel or 8TE CPU Front-Panel
GigaSTAR2) 9-Pin D-Sub on 4TE CPU Front-Panel or 8TE CPU Front-Panel
1) The physical COM2 interface is missing on Inova’s IPB-FPE8 piggyback allowing a PCI piggyback
device to be installed.
2) If this piggyback is installed the hard-disk (IDE FLASH) must be installed as stand-alone
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Doc. PD00581013.004
ICP-PIII
Product Overview
Figure 1.44 Front-Panel Options
®
1
The front-panels shown in Figure 1.44 show the tremendous flexibility built into Inova’s CPU
concept. From left, the standard CPU is 4TE with Ethernet, FireWire, USB and VGA graphic con-
nections. If, instead of VGA graphics, PanelLink is required then the piggyback is installed on J14
for this purpose. TFT graphics are realised in a similar way except an extra 4TE front-panel is
required (not shown) to carry the flat-band ribbon cables.
C
If the application requires the mouse, keyboard and COM ports or if the CPU is equipped with a
hard disk or FLASH that is greater than 144MByte1) then an 8TE front-panel is selected. Both COM
ports are installed on Inova’s HD or IDE FLASH carrier board. A piggyback with COM1, mouse and
keyboard is also available allowing the lower 9-pin D-Sub connector position to be used for a PCI-
based piggyback.
LPT and COM2 interfaces are available on a dedicated panel shown to the right of Figure 1.44.
If a high-profile DOC FLASH is installed and a hard disk is required, the HD is mounted separately
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Product Overview
ICP-PIII
1.45 Interface Positions
Figure 1.45 Interfaces
SDRAM EXTENSION
KEY
CPCI-CONNECTOR
PENTIUM III
FLASH-DISK
FLASH-MEMORY
Figure 1.45 shows the typical positioning of the front panel extension modules for mouse, key-
board, COM1, COM2, LPT1 and COM2/Fieldbus interfaces.
Note
A hard disk, if installed, will generally
be fitted to the piggyback containing
the mouse, keyboard, COM1 and
COM2 interfaces.
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Doc. PD00581013.004
ICP-PIII
Configuration
®
Configuration
2
Configuration Con-
tents
2.0 Memory Map........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
Table 2.00 UMB Reservations for ISA ......................................................................................... 2-3
Table 2.01 Port Addressing ........................................................................................................ 2-3
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
2.2 Memory Mapped Peripherals ..... 2-5
2.3 Interrupt Routing .................... 2-5
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-6
2.4 Inova PIII Device List................ 2-7
Table 2.40 Legacy I/O Map (ISA Compatible) ............................................................................ 2-7
2.5 Interrupt Configuration ............ 2-8
Table 2.50 CompactPCI Bus Interrupts ....................................................................................... 2-8
2.6 Timer / Counter....................... 2-9
2.7 Watchdog............................... 2-9
C
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Configuration
ICP-PIII
2.0 Memory Map
Figure 2.00 System Architecture
Memory
Addressable Memory
Address
Limit
Area
4 GByte
Memory
Extension
64/128/
Extended Memory
(Above 1 MByte)
256MByte
FFFFFh
1 MByte
BIOS
128 kByte
E0000h
Free
Upper
Memory
Blocks
D0000h
CC000h
C0000h
B8000h
B0000h
16 kByte FLASH Disk
48 kByte VGA BIOS
CGA Screen Memory
MDA Screen Memory
(UMBs)
VGA Screen Memory
A0000h
Free User
Memory
640 kByte
Conventional
Memory
System Data
00000h
The UMB reservation may be set up with the BIOS
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ICP-PIII
Configuration
Table 2.00 UMB Reservations for ISA
®
UMB Reservations for ISA
Start Address Finish Address
0CC00h
0D000h
0D400h
0D800h
0DC00h
0CFFFh
2
0D3FFh
0D7FFh
0DBFFh
0DFFFh
Table 2.01 Port Addressing
Port Addressing
Port
Address
3F8h
COM1
COM2
LPT1
2F8h
378h
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Configuration
ICP-PIII
2.1 I/O Mapped Peripherals
The original PC-XT and PC-AT desktop computer (ISA bus) specification allows for 10-bit I/O
addressed peripherals. This permits peripheral boards to be I/O mapped from 0h to 3FFh.
CompactPCI systems permit the full 16-bit addressing capability of the Intel 80x86 ‘processors,
from 0h to 0FFFFh.
All Inova CPU boards include peripheral devices requiring I/O address space on board and hence
the BIOS automatically assigns the I/O address required by peripheral boards and PCI devices at
boot time based on the requirements of each device. The assigned addresses can be determined
by reading the configuration address space registers using special software tools.
Table 2.10 Legacy I/O Map (ISA Compatible)
I/O Address
$000 - $00F
$020 - $021
$040 - $043
$060 - $06F
$070 – $071
$080 - $08B
$0A0 - $0BF
$0C0 – $0DF
$0F0
Description
8237 DMA controller #1
8259 Master Interrupt Controller
8254 Programmable Interrupt Timer
8042 Keyboard Controller
CMOS RAM, NMI Mask Reg., RTC
DMA page registers
8259 Slave Interrupt Controller
8237 DMA Controller #2
Coprocessor Error Ignored Register
*) Secondary Hard Disk Controller
*) Primary Hard Disk Controller
Reserved (Game Port)
$170 - $177
$1F0 - $1F8
$200 - $207
$238 - $23B
$2E0 - $2E7
$2E8 - $2EF
$2F8 - $2FF
$CF8
Bus Mouse
Reserved (GPIB)
Reserved (Serial Port)
*) Serial Port (COM2)
PCI Configuration Address
PCI Configuration Data
$CFC
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Doc. PD00581013.004
ICP-PIII
Configuration
Note:
®
*) Denotes Plug ‘n’ Play devices that
are configured during the BSP POST.
Values shown are ISA compatible I/O
addresses for reference only.
2
2.2 Memory Mapped Peripherals
PC-AT desktop computers (ISA bus) allow 24-bit memory addressed peripherals. This decoding
permits peripheral boards to be mapped in the Intel 80x86 memory map from 0h to 0FFFFFFh.
Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium/Celeron
range of ‘processors so that memory mapped peripheral devices may be mapped locally to the
‘processor board at any location in the memory map not being used by other devices (e.g. system
RAM.)
The BIOS automatically assigns memory addresses required by peripheral boards and PCI devices
at boot time based on the requirements of each device. The assigned addresses can be deter-
mined by reading the configuration address space registers using PCI software tools.
Note:
Devices not located on the CPU side of
the PCI/PCI bridge are not normally
accessible by DOS.
C
2.3 Interrupt Routing
The IBM-compatible architecture includes one (PC-XT) or two (PC-AT) programmable interrupt
controllers (Intel 8259A-compatible ‘PICs’) configured to set the priority of interrupt requests to
the CPU.
In the PC-AT architecture, one PIC is programmed as the ‘master’ with one input (IRQ2) being the
‘cascaded’ interrupt from the second ‘slave’ PIC.
This configuration allows for a total of 15 interrupt sources to the CPU. Table 2.3 shows the
interrupts with their corresponding vectors and sources as defined for AT PCs.
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Configuration
ICP-PIII
Table 2.30 PC-AT Interrupt Definitions
Interrupt Request Interrupt Vector
Function/Assignment
IRQ0
IRQ1
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
70h
71h
72h
73h
74h
75h
76h
77h
Timer
Keyboard
Slave 8259
COM 2/4
IRQ2
IRQ31)
IRQ41)
IRQ51)
IRQ6
COM 1/3
LPT2
Floppy
IRQ71)
IRQ8
LPT1
Real-Time Clock
Redirected IRQ2
USB
IRQ91)
IRQ10
IRQ111)
IRQ12
IRQ13
IRQ141)
IRQ151)
Ethernet/FireWire
Reserved
Co-processor
Hard Disk (IDE 0)
IDE 1
1)
Entries may be reserved for ISA devices with the BIOS
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ICP-PIII
Configuration
2.4 Inova PIII Device List
®
Table 2.40 shows the available PCI devices both on-board and off-board (CompactPCI backplane).
It should be noted that the interrupt routing assumes a standard Inova backplane configuration
with a right-hand system slot.
Table 2.40 Legacy I/O Map (ISA Compatible)
2
PCI Bus
Number
Device
Number
PCI Interrupt
Routing
Description
0 (On-board PCI)
0x00
0x01
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x10
0x11
0x14
0x00
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Host-PCI Bridge (82443BX)
PCI-PCI Bridge (82443BX)
PCI-ISA Bridge (Ali 1543C B1)
PCI-PCI Bridge (Intel 21150 or 21154)
IEEE1394 (TI TSB12LV26) FireWire
Ethernet (Intel 82559)
N/A
0
N/A
0
N/A
0
INTD#
INTB#
INTA#
INTD#
INTC#
INTB#
N/A
0
0
0
Optional 2nd Ethernet (Intel 82559)
PCI Extension, Device 0
0
0
PCI Extension, Device 1
0
IDE (Ali 1543C B1)
0
PMU (Ali 1543C B1)
N/A
0
USB (Ali 1543C B1)
N/A
1 (On-board AGP)
Graphics (ATI Radeon or SMI Lynx3DM) INTC#
1)
2 (cPCI Backplane)
CompactPCI Slot 1
INTD#
INTC#
INTB#
INTA#
INTD#
INTC#
INTB#
2
2
2
2
2
2
CompactPCI Slot 2
CompactPCI Slot 3
C
CompactPCI Slot 4
CompactPCI Slot 5
CompactPCI Slot 6
CompactPCI Slot 7 [next to Master]
1)
CompactPCI backplane numeration is based on a 7-slot backplane
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Configuration
ICP-PIII
2.5 Interrupt Configuration
The CompactPCI specification defines a total of six interrupt signals on the backplane. INTA#
through INTD# are used to route interrupts from the CompactPCI boards to the PIC on the ‘proc-
essor board. The interrupt request level generated by the device depends on the backplane slot
number which the board is plugged into, and the interrupt signal which is driven by the particular
PCI device.
Note:
CompactPCI interrupts may be shared
by multiple sources
Table 2.50 CompactPCI Bus Interrupts
CompactPCI
CompactPCI
Bus Interrupts
Bus Interrupts
INTA#
INTB#
INTC#
INTD#
INTP
( IRQ14 )
Serialized Interrupt
Refer to BIOS
INTS
Documentation
ENUM#
( IRQ5 )
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ICP-PIII
Configuration
2.6 Timer / Counter
®
The IBM-compatible architecture configures the programmable timer / counter (Intel 8254-com-
patible) devices for system-specific functions as shown in Table 2.50.
The BIOS programs Timer 0 to generate an interrupt approximately every 55ms (18.2 times per
second.) This interrupt, known as the system timer tick, updates the BIOS clock and turns off the
floppy disk motor drive after a few seconds of inactivity for example.
2
The BIOS featured in Inova’s CPUs programs the system timer tick for PC compatibility. The inter-
rupt generated by the timer creates an interrupt request on IRQ0 of the programmable interrupt
controller (PIC) which is serviced by the CPU as interrupt vector 08h.
In addition, Timer 1 and Timer 2 are also initialised by the BIOS as necessary for the specific
‘processor board functions.
Table 2.50 Timer and Counter Functions
Timer
Timer 0
Timer 1
Timer 2
Function/Assignment
System Timer, Periodic Interrupt (55 ms)
SDRAM Refresh
Speaker Frequency Generator
2.7 Watchdog
A three tier watchdog function with configurable timer is implemented in the ICP-PIII. Once the
timer has been set (between 64ms and 64x5min) the interrupt mode may be set. Either a Reset,
INIT, NMI or SMI interrupt is issued upon timeout.
C
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Configuration
ICP-PIII
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ICP-PIII
Interfaces
®
Interfaces
Interfaces Contents
3
3.0 CompactPCI J1/J2 Connector... 3-3
3.01 CompactPCI Connector ........................................................................... 3-3
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector ...................................................... 3-3
3.02 ICP-PIII Connector J1 and J2 ..................................................................... 3-3
Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment ............................................... 3-4
Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ............................ 3-5
Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..................... 3-6
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)...................... 3-7
Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) ..................... 3-8
Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration .......................................................... 3-9
3.1 CompactPCI Backplane .......... 3-10
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ................................ 3-11
3.2 Interfaces............................. 3-12
3.21 J7 & J12 Fast Ethernet ............................................................................ 3-12
Figure 3.21 RJ45 Pinout ........................................................................................................... 3-12
Table 3.21 Ethernet Connector Signals ..................................................................................... 3-12
3.22 J17 VGA Interface ................................................................................... 3-13
Figure 3.22 High-Density D-Sub VGA Interface Pinout .............................................................. 3-13
Table 3.22 Video Output Connector Signals ............................................................................. 3-13
Table 3.22b Video Resolutions ................................................................................................. 3-14
3.23 J16 PanelLink Interface ........................................................................... 3-15
Figure 3.23 PanelLink Interface Connector ............................................................................... 3-15
Table 2.12 PanelLink Interface ................................................................................................. 3-15
C
2.24 J16 GigaSTAR Interface........................................................................... 3-16
Figure 2.24 GigaSTAR D-Sub Interface Pinout........................................................................... 3-16
Table 2.11 GigaSTAR Interface................................................................................................ 3-16
3.25 J19 USB Interface ................................................................................... 3-17
Figure 3.25 USB Interface Pinout.............................................................................................. 3-17
Table 3.25 USB Connector Signals ........................................................................................... 3-17
3.26 J15 FireWire Interface ............................................................................. 3-18
Figure 3.26 FireWire Interface Pinout........................................................................................ 3-18
Table 3.26 FireWire Connector Signals ..................................................................................... 3-18
3.27 J20 Infrared (iRdA) Interface ................................................................... 3-19
3.28 J20 Reset Button..................................................................................... 3-19
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-1
Interfaces
ICP-PIII
3.29 J14 FLASH Interface ................................................................................ 3-19
3.30 J18 Floppy Disk Interface ........................................................................ 3-19
3.31 Connecting the PIII to the Inova IPB-FPE8 .............................................. 3-20
Figure 3.31 CPU to IPB-FPE8 Connection .................................................................................. 3-20
3.32 Connecting the PIII to the Inova ICP-HD-1 ............................................. 3-21
Figure 3.32 CPU to ICP-HD-1 Connection................................................................................. 3-21
3.33 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-22
Figure 3.33 CPU to IPB-FPE12 Connection ................................................................................ 3-22
3.34 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-23
Figure 3.34 CPU to IPB-FPE12 Connection ................................................................................ 3-23
3.35 Connecting the PIII to the ICP-FD-1 ....................................................... 3-24
Figure 3.35 CPU to Slim-Line Floppy Disk Connection ............................................................... 3-24
Page3-2
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.0 CompactPCI J1/J2 Connector
®
The CompactPCI standard is electrically identical to the PCI local bus standard but has been en-
hanced to support rugged industrial environments and up to 8 slots. The standard is based upon
a 3U board size and uses a rugged pin-in-socket hard 2mm connector (IEC-1076-4-101.)
3.01 CompactPCI Connector
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector
3
1
11
15
25
e
d
c
b
a
PCB
3.02 ICP-PIII Connector J1 and J2
Inova’s ICP-PIII CPU board has been designed as a 32-bit system slot device able to operate in
either +5V or +3.3V (I/O) systems. The CompactPCI backplane connector is keyed accordingly
(yellow for +3.3V and blue for +5V.)
C
Note:
Do not remove the keys. An I/O board
operating at 5.0V and keyed accordingly
will cause a 3.3V configured system to fail
if the keys are removed.
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-3
Interfaces
ICP-PIII
Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment
Pin Nr
J1-25
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-15
J1-14
J1-13
J1-12
J1-11
J1-10
J1-09
J1-08
J1-07
J1-06
J1-05
J1-04
J1-03
J1-02
J1-01
Row A
+5V
Row B
REQ64# Pull-
Up V( I / O )
Row C
ENUM#
V( I / O )
AD[3]
Row D
+3.3V
AD[0]
+5V
Row E
+5V
ACK64# Pull-
Up V( I / O )
AD[1]
+5V
AD[4]
+3.3V
AD[7]
AD[2]
AD[5]
GND
+3.3V
AD[6]
+3.3V
AD[12]
+3.3V
SERR#
+3.3V
DEVSEL#
+3.3V
AD[9]
AD[8]
M66EN – Gnd C / BE[0]#
GND
V( I / O )
AD[14]
+3.3V
AD[11]
GND
AD[10]
AD[13]
AD[15]
GND
PAR
C / BE[1]#
PERR#
LOCK#
TRDY#
IPMB-SCL
GND
IPMB-SDA
V( I / O )
IRDY#
GND
STOP#
BD-SEL#
FRAME#
KEY AREA
AD[18]
AD[21]
C / BE[3]
AD[26]
AD[30]
REQ#
-
AD[17]
GND
AD[16]
+3.3V
AD[23]
V( I / O )
AD[28]
+3.3V
RST#
V( I / O )
INTC
GND
AD[20]
GND
AD[25]
GND
CLK
C / BE[2]#
AD[19]
AD[22]
AD[24]
AD[27]
AD[31]
GNT#
INTS
-
GND
AD[29]
GND
-
GND
INTP
+5V
UPS1)
INTA#
-
HEALTHY#
INTB#
+5V
INTD#
-
-
-
+5V
-12V
-
+12V
+5V
1)
Reserved for use for Inova’s Uninterruptible Power Supply (UPS)
Page3-4
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)
®
Pin Nr
J2-22
J2-21
J2-20
J2-19
J2-18
J2-17
J2-16
J2-15
J2-14
J2-13
J2-12
J2-11
J2-10
J2-09
J2-08
J2-07
J2-06
J2-05
J2-04
J2-03
J2-02
J2-01
Row A
Row B
Row C
Row D
Row E
-
-
GND
GND
GND
-
-
-
-
-
CLK6
-
-
CLK5
-
GND
-
-
GND
-
-
-
-
GND
REQ6#
GND
REQ5#
GND
-
-
3
-
GND
-
PRST#
GNT6#
-
-
(UBAT)5)
-
GND
-
-
GNT5#
-
-
-
-
GND
-
V(I/O)
-
-
-
V(I/O)
-
GND
-
-
-
GND
-
-
-
GND
-
-
-
GND
-
V(I/O)
-
-
-
GND
-
-
-
GND
-
V(I/O)
-
-
-
GND
-
-
-
GND
SPEAKER4)
GND
CLK3
GND
V(I/O)
-
-
V(I/O)
CLK4
CLK2
CLK1
GND
REQ4#
GNT2#
GNT1#
-
GNT3#
SYSEN#
REQ1#
GNT4#
GNT3#
REQ2#
C
4)
5)
:
:
5V open collector signal (5V/100mA)
Option “External Battery” (Note: battery must be removed from CPU board)
Ubat = +3.4V to +3.6V
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-5
Interfaces
ICP-PIII
Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)
Pin Nr
J2-22
J2-21
J2-20
J2-19
J2-18
J2-17
J2-16
J2-15
J2-14
J2-13
J2-12
J2-11
J2-10
J2-09
J2-08
J2-07
J2-06
J2-05
J2-04
J2-03
J2-02
J2-01
Row A
Row B
Row C
Row D
-
Row E
-
-
GND
GND
GND
-
-
-
CLK6
ETH_TxF+
ETH_TxF-
GND
ETH_RxF+
GND
REQ6#
GND
REQ5#
GND
-
ETH_R45
CLK5
COM 2-6)
ETH_R78
GND
COM 2+6)
ETH_RxF-
-
COM 1-6)
COM 1+6)
-
GND
-
PRST#
GNT6#
-
-
(UBAT)5)
-
GND
-
-
GNT5#
-
-
-
-
GND
-
V(I/O)
-
-
-
V(I/O)
-
GND
-
-
-
GND
-
-
-
GND
-
-
-
GND
-
V(I/O)
-
-
-
GND
-
-
-
GND
-
V(I/O)
-
-
-
GND
-
-
-
GND
SPEAKER4)
GND
CLK3
GND
V(I/O)
-
-
V(I/O)
CLK4
CLK2
CLK1
GND
REQ4#
GNT2#
GNT1#
-
GNT3#
SYSEN#
REQ1#
GNT4#
GNT3#
REQ2#
4)
5)
:
:
5V open collector signal (5V/100mA)
Option “External Battery” (Note: battery must be removed from CPU board)
Ubat = +3.4V to +3.6V
RS485 signals
6)
:
Page3-6
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)
®
Pin Nr
J2-22
J2-21
J2-20
J2-19
J2-18
J2-17
J2-16
J2-15
J2-14
J2-13
J2-12
J2-11
J2-10
J2-09
J2-08
J2-07
J2-06
J2-05
J2-04
J2-03
J2-02
J2-01
Row A
-
Row B
-
Row C
Row D
-
Row E
-
-
CLK6
GND
ETH_TxF+
ETH_TxF-
GND
ETH_R45
ETH_R78
ETH_RxF-
-
CLK5
GND
-
GND
GND
-
ETH_RxF+
GND
LPT-STP3)
LPT-AFD3)
LPT-D03)
LPT-ERR3)
LPT-D13)
LPT-INIT3)
LPT-D23)
LPT-SLIN3)
LPT-D33)
LPT-D43)
LPT-D53)
LPT-BUSY3)
LPT-D63)
LPT-D73)
V(I/O)
LPT-PE3)
GND
-
3
PRST#
REQ6#
GND
GNT6#
(UBAT)5)
GNT5#
RI11)
LPT-ACK3) USB1-DATA+2)
GND
USB1-DATA-2)
H5V(1A)
V(I/O)
REQ5#
GND
LPT-SLCT3)
GND
DTR11)
GND
CTS11)
TxD11)
RxD11)
DSR11)
RI21)
-
GND
-
USB2-DATA+2)
V(I/O)
RTS11)
GND
USB2-DATA-2)
V(I/O)
GND
-
DCD11)
GND
-
DTR21)
TxD21)
RTS21)
DSR21)
DCD21)
GNT4#
GNT3#
REQ2#
GND
-
V(I/O)
CTS21)
GND
-
GND
SPEAKER4)
GND
CLK3
GND
V(I/O)
RxD21)
GND
-
CLK4
GNT3#
SYSEN#
REQ1#
REQ4#
GNT2#
GNT1#
CLK2
C
CLK1
1)
2)
:
:
5V TTL signals from serial I/O controller
Termination of USB lines on CPU. The +5V and GND signals need fuses and inductors for
decoupling (USB specification).
The 5V LPT signals need decoupling and pull-up resistors near the backplane LPT 1
3)
:
connector.
5V open collector signal (5V/100mA)
Option “External Battery” (Note: battery must be removed from CPU board)
4)
5)
:
:
Ubat = +3.4V to +3.6V
RS485 signals
6)
:
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-7
Interfaces
ICP-PIII
Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)
Pin Nr
J2-22
J2-21
J2-20
J2-19
J2-18
J2-17
J2-16
J2-15
J2-14
J2-13
J2-12
J2-11
J2-10
J2-09
J2-08
J2-07
J2-06
J2-05
J2-04
J2-03
J2-02
J2-01
Row A
-
Row B
-
Row C
-
Row D
-
Row E
-
CLK6
GND
FW_TPA+
HADR0
HADR1
HADR2
PRST#
FW_TPA-
GND
HCS0#
HRST#
FW_TPB-
HCS1#
GNT6#
(UBAT)5)
GNT5#
HD0
CLK5
GND
GND
GND
FW_TPB+
GND
LPT-STP3)
LPT-AFD3)
LPT-D03)
LPT-ERR3)
LPT-D13)
LPT-INIT3)
LPT-D23)
LPT-SLIN3)
LPT-D33)
LPT-D43)
LPT-D53)
LPT-BUSY3)
LPT-D63)
LPT-D73)
V(I/O)
LPT-PE3)
GND
REQ6#
GND
[DEG# = LPT-
D0]
[FAL# = LPT-
D1]
LPT-ACK3)
GND
REQ5#
GND
LPT-SLCT3)
GND
H5V(1A)
V(I/O)
HD1
HD2
HIOW#
GND
USB2-DATA+2)
GND
HD3
V(I/O)
HD4
HD5
HIOR#
GND
USB2-DATA-2)
V(I/O)
GND
HD6
HD7
HD8
HIRQ15
GND
HDMARQ
V(I/O)
GND
HD9
HD10
GND
HD11
HD12
HD14
HD15
GNT4#
GNT3#
REQ2#
-
HDMACK
V(I/O)
GND
HD13
GND
SPEAKER4)
HIORDY#
GNT3#
CLK4
GND
REQ4#
GNT2#
GNT1#
CLK2
CLK3
GND
SYSEN#
REQ1#
CLK1
1)
2)
:
:
5V TTL signals from serial I/O controller
Termination of USB lines on CPU. The +5V and GND signals need fuses and inductors for
decoupling (USB specification).
The 5V LPT signals need decoupling and pull-up resistors near the backplane LPT 1
3)
:
connector.
5V open collector signal (5V/100mA)
Option “External Battery” (Note: battery must be removed from CPU board)
4)
5)
:
:
Ubat = +3.4V to +3.6V
RS485 signals
6)
:
Page3-8
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration
®
REAR I/O
OPTION
Rear I/O
STANDARD
A
B
C
ETHERNET
COM 1/2
USB 1/2
FireWire 2
LPT 1
No
Yes
Yes
No
Both
(RS485)
No
No
No
No
Yes
No
No
Both (TTL)
Both
No
No
USB 2
Yes
Yes
Yes
No
No
No
No
Yes
No
No
3
Yes
SPEAKER
BATTERY
EIDE
Yes
No
No
Yes
Currently three forms of rear I/O are available and, depending on the version currently in use,
decides which (if any) of the J2 signals are available to the rear J2 connector.
The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification.
C
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-9
Interfaces
ICP-PIII
3.1 CompactPCI Backplane
The form factor defined for CompactPCI boards is based upon the Euro-card industry standard.
Both 3U (100 mm by 160 mm) and 6U (233 mm by 100 mm) board sizes are defined. A Com-
pactPCI system is composed of up to eight CompactPCI cards. The CompactPCI backplane con-
sists of one System Slot, and up to seven Peripheral Slots.
The System Slot provides arbitration, clock distribution, and reset functions for all boards on the
bus. The System Slot is responsible for performing system initialization by managing each local
board’s IDSEL signal.
Physically, the System Slot may be located at either end of the backplane but Inova have placed
theirs on the right to cater for physical expansion due to heat-sink, hard disk, extended function-
ality etc. The Peripheral Slots may contain simple boards, intelligent slaves, or PCI bus masters.
Note:
Inova’s 3U CompactPCI CPU boards
can be used as either master or slave
boards i.e. occupying either the system
slot or the peripheral slot. The choice
of PCI/PCI bridge (multiprocessing or
standard) decides which of the slots is
used.
Page3-10
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
®
3
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
Z
A
B
C
D
E
F
C
Note:
The logical slots are different to the
physical slots. The slot marked with the
‘̅‘ is the System Slot and always as-
signed logical ‘0’. The neighbouring slot
is logical ‘0xF’!
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-11
Interfaces
ICP-PIII
3.2 Interfaces
3.21 J7 & J12 Fast Ethernet
J7 is available as standard on the CPU front-panel and, as an option, J12 may also be available but
at the expense of the FireWire interface. The RJ45 interface supports both the 10BaseT and
100BaseTX twisted pair standard.
Figure 3.21 RJ45 Pinout
Activity
Link
8
1
Table 3.21 Ethernet Connector Signals
Pin No.
Signal
1
2
TXF+
TXF-
RXF+
R45
3
4,5
6
RXF-
R78
7, 8
9, 10
11, 12
13, 14
Link LED; not accessible on pins
Active LED; not accessible on pins
PE; not accessible on pins
Note:
Users taking advantage of the CPU’s rear
I/O options are advised not to use the
front-panel interface if the rear interface is
being used. Possible damage to the board
could occur and data integrity cannot be
assured.
Page3-12
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.22 J17 VGA Interface
®
J17 is available on the CPU front-panel if this option is required and if this position is not already
occupied by a PCI, PanelLink or GigaST R piggyback. The 15-pin high-density D-Sub connector
Ȣ
forms the physical interface for the video on the ICP-PIII which is based on either the Silicon
Motion Lynx3DM graphic accelerator equipped with 8MByte RAM or the Radeon VE controller
with 16MByte RAM. In both cases, the controller is a highly integrated 128-bit GUI (Grahpical
User Interface) engine that has been optimized for handling graphic-intensive environments like
those found in Windows NT.
The controller uses a 64-bit data path to the RAM video memory, a 24-bit high-performance 135
MHz RAMDAC and a flat-panel interface capable of controlling the latest STN and TFT panels.
3
All ICP-PIII CPUs, if prepared for graphics, are equipped with 8/16MByte high-speed RAM sup-
porting resolutions up to 1600 x 1200 pixels with 24-bit (True Colour) depth or 2048 x 1536
pixels with 16-bit (Hi-Colour) depth. VGA, SVGA, XGA, XSGA Composite video and TFT dual-
scan/single-scan colour panels are supported with configurable colour depths.
Figure 3.22 High-Density D-Sub VGA Interface Pinout
5
1
10
6
15
11
Table 3.22 Video Output Connector Signals
Pin No.
Signal
1
2
3
4
Analog RED
Analog GREEN
Analog BLUE
N/C
C
5, 6, 7, 8 CRT Ground
9, 11
10
N/C
CRT Ground
DDC-SDA
HSYNC
12
13
14
VSYNC
15
DDC-SCL
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-13
Interfaces
ICP-PIII
Table 3.22b Video Resolutions
Lynx3DM Controller
Colour Depth
65, 000
VGA
Resolution
256
16.7M
640x480
800x600
60/72/75/85 60/72/75/85 60/72/75/85
60/72/75/85 60/72/75/85 60/72/75/85
43I/60/70/
75/85
43I/60/70/
75/85
43I/60/70/
75/85
1024x768
1280x1024
1600x1200
43I/60/75
43I
43I/60/75
N/A
N/A
43I (not 65k)
Note: 32k colours are not selectable in Microsoft's Windows 9
Note: 32k colours are not selectable in Microsoft’s Windows 98
'I' in the above table refers to interlaced monitors
‘I’ in the above table refers to interlaced monitors.
ATI Radeon VE Controller
Colour Depth
VGA
Resolution
256
65, 000
60 to 200
60 to 200
60 to 200
43 to 160
60 to 120
52 to 100
60 to 80
60 to 85
60/75
16.7M
60 to 200
60 to 200
60 to 200
43 to 160
60 to 120
52 to 100
60 to 80
60 to 85
60/75
640x480
60 to 200
60 to 200
60 to 200
43 to 160
60 to 120
52 to 100
60 to 80
60 to 85
60/75
800x600
1024x768
1152x864
1280x1024
1600x1200
1920x1080
1920x1200
1920x1440
2048x1536
60
60
60
Colour Depth
TFT
Resolution
256
60
65, 000
16.7M
60
640x480
60
60
60
60
800x600
60
60
1024x768
1280x1024
60
60
60
60
Page3-14
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.23 J16 PanelLink Interface
®
J16 is available if requested at time of order and replaces the standard VGA connector on the front-
panel.
Figure 3.23 PanelLink Interface Connector
5
1
3
10
6
15
11
Table 2.12 PanelLink Interface
Pin No.
Signal
1
2
3
4
5
Tx2-
Tx1-
Tx0-
TxC-
DDC Data
6, 7, 8, 9 GND
10
11
12
13
14
15
+5V (<100mA)
Tx2+
Tx1+
Tx0+
C
TxC+
DDC Clock
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-15
Interfaces
ICP-PIII
2.24 J16 GigaSTAR Interface
The standard 9-pin D-Sub connector is used for GigaSTAR video transmission.
Figure 2.24 GigaSTAR D-Sub Interface Pinout
1
5
6
9
Table 2.11 GigaSTAR Interface
Pin No.
Signal
1
2
3
4
5
6
7
8
9
GigaSTAR Tx+
N/C
N/C
N/C
N/C
GigaSTAR Tx-
N/C
N/C
N/C
Page3-16
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.25 J19 USB Interface
®
J19 is located as standard on the front panel
Figure 3.25 USB Interface Pinout
3
1
2
3
4
Table 3.25 USB Connector Signals
Pin No.
Signal
1
+5V
2
USB P0-
USB P0+
GND
3
4
Housing
PE
C
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-17
Interfaces
ICP-PIII
3.26 J15 FireWire Interface
J15 is located on the front panel (if this option is available)
Figure 3.26 FireWire Interface Pinout
2
1
4
3
6
5
Table 3.26 FireWire Connector Signals
Pin No.
Signal
1
IEEE 1394 S +12V ( 1A Fuse)
IEEE 1394 S GND
IEEE 1294 S TPB-
IEEE 1394 S TPB+
IEEE 1394 S TPA-
IEEE 1394 S TPA+
PE
2
3
4
5
6
Housing
Page3-18
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.27 J20 Infrared (iRdA) Interface
®
This option is proprietary and not documented here.
3.28 J20 Reset Button
The reset button allows the CPU to be rest in the event that it ‘hangs’ Performing a reset in this
manner is known as a ‘warm’ start as power is not removed from the peripherals (IDE etc.) This
reset button is also used when recovering a corrupt BIOS image - refer to the PIII BIOS user’s
manual for details.
3
3.29 J14 FLASH Interface
J14 is proprietary and not documented here
3.30 J18 Floppy Disk Interface
J18 is proprietary and not documented here but observes the standard slim-line floppy pin-out.
C
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-19
Interfaces
ICP-PIII
3.31 Connecting the PIII to the Inova IPB-FPE8
Appendix A provides more information on the IPB-FPE8 and its derivatives. Figure 3.31 shows how
the CPU connects to the piggyback by a length of flex-cable.
Figure 3.31 CPU to IPB-FPE8 Connection
J4
J6
J3
J18
PENTIUM III
J13
J11
J14
J10
J9
Page3-20
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.32 Connecting the PIII to the Inova ICP-HD-1
®
Appendix B provides more information on the ICP-HD-1 and its derivatives. Figure 3.32 shows
how the CPU connects to the piggyback by lengths of flex-cable.
Figure 3.32 CPU to ICP-HD-1 Connection
3
J10A
J9A
J10
J11
J9
J13A
J13
J4
J6
J3
C
J18
PENTIUM III
J13
J11
J14
J10
J9
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-21
Interfaces
ICP-PIII
3.33 Connecting the PIII to the Inova IPB-FPE12
Appendix C provides more information on the IPB-FPE12 and its derivatives. Figure 3.33 shows
how the CPU connects to the piggyback by a length of flex-cable. The illustration also shows the
IPB-FPE8 connection (Appendix A)
Figure 3.33 CPU to IPB-FPE12 Connection
J13
J4
J6
J3
J18
PENTIUM III
J13
J11
J14
J10
J9
Page3-22
©2002 Inova Computers GmbH
Doc. PD00581013.004
ICP-PIII
Interfaces
3.34 Connecting the PIII to the Inova IPB-FPE12
®
Appendix C provides more information on the IPB-FPE12 and its derivatives. Figure 3.34 shows
how the CPU connects to the piggyback by a length of flex-cable. The illustration also shows the
ICP-HD-1 connection (Appendix B)
Figure 3.34 CPU to IPB-FPE12 Connection
J13
3
J10A
J9A
J10
J9
J13A
J13
J11
J4
C
J6
J3
J18
PENTIUM III
J13
J11
J14
J10
J9
Doc. PD00581013.004
©2002 Inova Computers GmbH
Page3-23
Interfaces
ICP-PIII
3.35 Connecting the PIII to the ICP-FD-1
Figure 3.35 shows how the CPU connects to the slim-line floppy disk unit.
Figure 3.35 CPU to Slim-Line Floppy Disk Connection
Floppy
J4
J6
J3
J18
PENTIUM III
J13
J11
J14
J10
J9
Page3-24
©2002 Inova Computers GmbH
Doc. PD00581013.004
Appendix A
IPB-FPE8
®
IPB-FPE8
IPB-FPE8 Contents
A1 IPB-FPE8 CPU Extension ......... A-2
A1.1 J11 Interface for COM1, Mouse & Keyboard ............................................ A-2
A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)....................................................... A-2
Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU .......................................................... A-2
A1.3 Stand-Alone IPB-FPE8............................................................................... A-3
Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8 ............................................................... A-3
A1.4 IPB-FPE8MS (Theme Variation) ................................................................. A-4
Figure A1.4 Piggyback Interface IPB-FPE8MS .............................................................................. A-4
Table A1.4 IPB-FPE8MS Connector Description ........................................................................... A-4
A1.5 IPB-FPE8MS Description ........................................................................... A-5
Figure A1.5 Top & Bottom Views of the IPB-FPE8MS ................................................................... A-5
Table A1.5 Standard Hard-Disk & Floppy Disk Connectors .......................................................... A-5
A
A1.6 Keyboard Interface................................................................................... A-6
Figure A1.6 Keyboard Interface Pinout ...................................................................................... A-6
Table A1.6 Keyboard Connector Signals ..................................................................................... A-6
A1.7 Mouse Interface ....................................................................................... A-6
Figure A1.7 Mouse Interface Pinout............................................................................................ A-6
Table A1.7 Mouse Connector Signals ......................................................................................... A-6
A1.8 COM1 Interfaces...................................................................................... A-7
Figure A1.8 COM1 Interface Pinout............................................................................................ A-7
Table A1.8 COM1 Connector Signals ......................................................................................... A-7
C
CPUAppendix-A
©2001 Inova Computers GmbH
PageA-1
IPB-FPE8
Appendix A
A1 IPB-FPE8 CPU Extension
The IPBFPE8 provides additional CPU functionality in the form of PS-2 style mouse and keyboard
connectors and a serial COM1 port.
A1.1 J11 Interface for COM1, Mouse & Keyboard
The control of the mouse, keyboard and COM1 interfaces is performed through the J11 connec-
tor on the CPU base board. The location of this connector may be determined by referring to
Section 1 - Product Overview of the CPU User’s Manual. A flex cable from J11 connects to a
number of interface boards - all of which are discussed in this section.
A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)
The Inova IPB-FPE8 interface is a small piggyback either as stand-alone with its own 4HP front-
panel or integrated with the CPU as in figure A1.2.
Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU
PageA-2
©2001 Inova Computers GmbH
CPUAppendix-A
Appendix A
IPB-FPE8
A1.3 Stand-Alone IPB-FPE8
Figure A1.3 illustrates the construction of the stand-alone IPB-FPE8 piggyback and the underside
location of the J11 connector. Care should be taken to ensure that pin 1 of J11 on the CPU base
board is linked by an appropriate length of flex cable to pin 1 on the piggyback. To help with the
orientation, the connector flanks that are blue indicate the blue face of the flex-cable. Unmarked
flanks indicate the metallic connection of the flex-cable. Also, pin 1 has been highlighted by a red
triangle.
®
Note:
Damage to the CPU board or the
piggyback may result if the flex cable
is positioned incorrectly. Inova will not
accept responsibility for negligent
actions!
Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8
A
Pin 1
J11
C
Note:
The physical connection of the IPB-
FPE8 is electrically identical regardless
of the nature of connection (stand-
alone or integrated!)
CPUAppendix-A
©2001 Inova Computers GmbH
PageA-3
IPB-FPE8
Appendix A
A1.4 IPB-FPE8MS (Theme Variation)
Figure A1.4 illustrates the construction of the IPB-FPE8MS - a variation of the IPB-FPE8 but with a
number of extra features. The electrical connection to the CPU base board is still via the underside
connector J11 and again, the precautions mentioned for the IPB-FPE8 are valid here.
Figure A1.4 Piggyback Interface IPB-FPE8MS
J9B
J18A
J18B
J10B
J9A
J10A
J11
Note that the IPB-FPE8 module does not allow a HD to be connected behind it and the lower 9-
pin D-Sub slot may be used for remote connection of PanelLink for example. The IPB-FPE8MS
shown in figure A1.4 enables connection of floppy, a CD-ROM and other peripherals. The connector
names and descriptions are declared in table A1.4.
Table A1.4 IPB-FPE8MS Connector Description
Connector
J9A, J10A
J9B, J10B
J11
Description
IDE Primary (Master or Slave)
IDE Primary (Master or Slave)*
Mouse, Keyboard and COM1
J18A, J18B Floppy Disk (either a standard slim-line floppy connector or flex cable)
* If connectors 9a and 10a are configured as Master then 9b and 10b must be Slave.
PageA-4
©2001 Inova Computers GmbH
CPUAppendix-A
Appendix A
IPB-FPE8
A1.5 IPB-FPE8MS Description
As mentioned previously, the IPB-FPE8MS has a number of additional features compared to the
standard IPB-FPE8 module. These extra features include HD and FD connection with both standard
connectors and the Inova flex cables. This provides the user with system flexibility.
®
Figure A1.5 Top & Bottom Views of the IPB-FPE8MS
Keyboard
J11
Mouse
2
4
COM1
5
3
A
PCB Cut-out: 1 DiskOnChip FLASH
2 For LPT1 Flex Cable
3 Flying Lead / Connector
4 Piggyback Flying Lead
5 IDE Flex-Cables [J9a, J10a] to CPU
Note:
Damage to the CPU board or the
piggyback may result if the cables are
incorrectly positioned. Inova will not
accept responsibility for negligent
actions!
C
Figure A1.5 makes reference to two standard PC-style connectors (J5 and J6). The function of
these connectors is given in table A1.5.
Table A1.5 Standard Hard-Disk & Floppy Disk Connectors
Connector
Description
J5
J6
PC-Style Floppy Disk Connector
Standard Primary IDE Connector (Master or Slave)
CPUAppendix-A
©2001 Inova Computers GmbH
PageA-5
IPB-FPE8
Appendix A
A1.6 Keyboard Interface
A front-panel with COM1, COM2 mouse and keyboard interfaces is either integrated into an 8HP
standard CPU front-panel or available as a separate 4HP unit. The piggyback located behind these
interfaces connects to the CPU-mounted J11 connector.
Figure A1.6 Keyboard Interface Pinout
5
3
6
4
1
2
Table A1.6 Keyboard Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
5
Data
GND
CLK
2
4
6
N/C
+5V
N/C
A1.7 Mouse Interface
A front-panel with COM1, COM2 mouse and keyboard interfaces is either integrated into an 8HP
standard CPU front-panel or available as a separate 4HP unit. The piggyback located behind these
interfaces connects to the CPU-mounted J11 connector.
Figure A1.7 Mouse Interface Pinout
5
3
6
4
1
2
Table A1.7 Mouse Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
5
Data
GND
CLK
2
4
6
N/C
+5V
N/C
PageA-6
©2001 Inova Computers GmbH
CPUAppendix-A
Appendix A
IPB-FPE8
A1.8 COM1 Interface
The COM1 port features a complete set of handshaking and modem control signals, maskable
interrupt generation and high-speed data transfer rates. A front-panel with COM1, mouse and
keyboard interfaces is either integrated into an 8HP standard CPU front-panel or available as a
separate 4HP unit. The piggyback located behind these interfaces connects to the CPU-mounted
J11 connector.
®
Figure A1.8 COM1 Interface Pinout
1
6
5
9
Table A1.8 COM1 Connector Signals
Signal
Pin No.
RS232
DCD
RxD
TxD
RS485
A
1
2
3
4
5
6
7
8
9
Note:
RxD, TxD +
RxD, TxD -
The standard CPU configuration has
COM1 set for RS232 communication.
DTR
GND
DSR
RTS
CTS
RI
However, this device can be configured to
observe a two-wire, non galvanically
separated, RS485 protocol. The data
direction is governed by controlling the
UART’s RTS signal. Writing a hex value of
0B to this register allows data to be
transmitted. Writing 1B to this register
configures the device to receive data.
C
CPUAppendix-A
©2001 Inova Computers GmbH
PageA-7
IPB-FPE8
Appendix A
This page has been left blank intentionally.
PageA-8
©2001 Inova Computers GmbH
CPUAppendix-A
Appendix B
ICP-HD
®
ICP-HD
ICP-HD Contents
B1 ICP-HD CPU Extension ............. B-2
B1.1 J11, J13 Interfaces .................................................................................... B-2
B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)...................................................... B-2
Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU......................................................... B-2
B1.3 IDE Carrier Board ICP-HD-1 ...................................................................... B-3
Figure B1.3 IDE Carrier Board ICP-HD1 ...................................................................................... B-3
Table B1.3 ICP-HD-1 Connector Description ............................................................................... B-4
B1.4 ICP-HDE8MS (Theme Variation) ............................................................... B-4
Figure B1.4 IDE Carrier ICP-HDE8MS.......................................................................................... B-4
Table B1.4 IPB-HDE8MS Connector Description .......................................................................... B-5
B1.5 ICP-HDE8MS Description ......................................................................... B-6
Figure B1.5 Top & Bottom Views of the ICP-HDE8MS.................................................................. B-6
B1.6 Keyboard Interface ................................................................................... B-7
Figure B1.6 Keyboard Interface Pinout....................................................................................... B-7
Table B1.6 Keyboard Connector Signals ..................................................................................... B-7
B1.7 Mouse Interface ....................................................................................... B-7
Figure B1.7 Mouse Interface Pinout ............................................................................................ B-7
Table B1.7 Mouse Connector Signals.......................................................................................... B-7
B1.8 COM1 & COM 2 Interfaces...................................................................... B-8
Figure B1.8 COM1 & COM2 Interface Pinout ............................................................................. B-8
Table B1.8 COM1 & COM2 Connector Signals ........................................................................... B-8
B
C
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-1
ICP-HD
Appendix B
B1 ICP-HD CPU Extension
Several hard-disk connection possibilities exist of which two are documented here. Both of these
provide additional CPU functionality in the form of PS-2 style mouse and keyboard connectors
and serial COM1 and COM2 ports.
B1.1 J11, J13 Interfaces
The control of the mouse, keyboard, COM1 & COM2 interfaces is performed through the J11 and
J13 connectors respectively on the CPU base board. The location of these connectors may be
determined by referring to Section 1 - Product Overview of the CPU User’s Manual. A flex cable
from J11 and J13 connects to the interface boards discussed in this section.
B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)
The Inova ICP-HD-1 interface is an IDE device carrier board available as a stand-alone device with
its own 4HP front-panel or integrated with the CPU as in figure B1.2.
Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU
PageB-2
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
ICP-HD
B1.3 IDE Carrier Board ICP-HD-1
Figure B1.3 illustrates the construction of the stand-alone ICP-HD1 carrier and the underside loca-
tion of the J11 & J13 connectors. The same mechanical construction applies to the integrated
version. Care should be taken to ensure that pin 1 of J11/J13 on the CPU base board is linked by
an appropriate length of flex cable to pin 1 on the carrier. To help with the orientation, the
connector flanks that are blue indicate the blue face of the flex-cable. Unmarked flanks indicate
the metallic connection of the flex-cable. Also, pin 1 has been highlighted by a red triangle.
®
Note:
Damage to the CPU board or the
piggyback may result if the flex cable
is positioned incorrectly. Inova will not
accept responsibility for negligent
actions!
Figure B1.3 IDE Carrier Board ICP-HD1
J10A
J10
J9A
J9
B
J13
J13A
J11
C
Note:
The physical connection of the ICP-
HD-1 is electrically identical regardless
of the nature of connection (stand-
alone or integrated!)
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-3
ICP-HD
Appendix B
Table B1.3 ICP-HD-1 Connector Description
Connector
J9, J10
J9a, J10a
J11
Description
Primary IDE (Master / Slave)
Primary IDE (Master / Slave)
COM1, Mouse & Keyboard
LPT1 & COM2
J13
J13a
LPT1 & COM2*
B1.4 ICP-HDE8MS (Theme Variation)
Figure B1.4 illustrates the construction of the ICP-HDE8MS - a variation of the ICP-HD-1 but with
a number of extra features. The electrical connection to the CPU base board is still via the under-
side connectors J11 and J13 and again, the precautions mentioned for the ICP-HD-1 are valid
here.
Figure B1.4 IDE Carrier ICP-HDE8MS
J2
J9A
J1
J10A
J18A
J18
J10
J9
J11
J13
J13A
The ICP-HDE8MS shown in figure B1.4 enables connection of floppy, a CD-ROM and other pe-
ripherals. The connector names and descriptions are declared in table B1.4.
PageB-4
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
ICP-HD
Table B1.4 IPB-HDE8MS Connector Description
®
Connector
Description
J1
Standard Floppy Disk Connector - To Floppy Disk
Standard IDE Connector - To Hard Disk / FLASH
Primary HD (Master / Slave)
J2
J9, J10
J9a, J10A
J11
Primary HD (Master / Slave)
COM1, Mouse & Keyboard
J13
LPT1 & COM2
J13A
J18
LPT1 & COM2*
Slim-Line Floppy Disk Connector - To CPU Base Board
Slim-Line Floppy Disk Connector - To Floppy Disk
J18A
* If connectors 9 and 10 are connected to a Master device then 9a and 10a must be connected to a
Slave.
Note:
* Tables B1.3 and B1.4 refer to J13
and J13a for the connection of COM2
and LPT1. Both the ICP-HD-1 and ICP-
HDE8 possess COM2 which is accessed
through J13 connected to the CPU
board. If the Inova IPB-FPE12 piggy-
back is used and connected to J13a
then the COM2 on the IDE carriers
ICP-HD-1 and ICP-HDE8MS will be
disabled.
B
C
Note:
Damage to the CPU board or the
piggyback may result if the cables are
incorrectly positioned. Inova will not
accept responsibility for negligent
actions!
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-5
ICP-HD
Appendix B
B1.5 ICP-HDE8MS Description
As mentioned previously, the ICP-HDE8MS has a number of additional features compared to the
standard ICP-HD-1 module. These extra features include HD and FD connection with both stand-
ard connectors and the Inova flex cables. This provides the user with additional system flexibility.
Figure B1.5 Top & Bottom Views of the ICP-HDE8MS
Keyboard
Mouse
COM1
J18A
J1
COM2
J10A
J9A
J2
J13A
J13
J11
J18
J9
J10
PageB-6
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
ICP-HD
B1.6 Keyboard Interface
A front-panel with COM1, COM2 mouse and keyboard interfaces is either integrated into an 8HP
standard CPU front-panel or available as a separate 4HP unit. The piggyback located behind these
interfaces connects to the CPU-mounted J11 connector.
®
Figure B1.6 Keyboard Interface Pinout
5
3
6
4
1
2
Table B1.6 Keyboard Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
5
Data
GND
CLK
2
4
6
N/C
+5V
N/C
B1.7 Mouse Interface
A front-panel with COM1, COM2 mouse and keyboard interfaces is either integrated into an 8HP
standard CPU front-panel or available as a separate 4HP unit. The piggyback located behind these
interfaces connects to the CPU-mounted J11 connector.
B
Figure B1.7 Mouse Interface Pinout
5
3
6
4
C
1
2
Table B1.7 Mouse Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
5
Data
GND
CLK
2
4
6
N/C
+5V
N/C
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-7
ICP-HD
Appendix B
B1.8 COM1 & COM 2 Interfaces
The two COM ports feature a complete set of handshaking and modem control signals, maskable
interrupt generation and high-speed data transfer rates. A front-panel with COM1, COM2, mouse
and keyboard interfaces is either integrated into an 8HP standard CPU front-panel or available as
a separate 4HP unit. The IDE carrier board located behind these interfaces connects to the CPU-
mounted J11 and J13 connectors.
Figure B1.8 COM1 & COM2 Interface Pinout
1
5
9
6
Table B1.8 COM1 & COM2 Connector Signals
Signal
Pin No.
RS232
DCD
RxD
TxD
RS485
1
2
3
4
5
6
7
8
9
Note:
RxD, TxD +
RxD, TxD -
The standard CPU configuration has both
COM ports set for RS232 communication.
DTR
GND
DSR
RTS
CTS
RI
However, this device can be configured to
observe a two-wire, non galvanically
separated, RS485 protocol. The data
direction is governed by controlling the
UART’s RTS signal. Writing a hex value of
0B to this register allows data to be
transmitted. Writing 1B to this register
configures the device to receive data.
PageB-8
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
IPM-ATA
®
IPM-ATA
IPM-ATA
B1 IPM-ATA CPU Extension ........... B-2
B1.1 J1 Interfaces ............................................................................................. B-2
Figure B1.1a Dedicated IPM-ATA Backplane................................................................................ B-2
B1.1 J1 Interfaces (Contd.) ............................................................................... B-3
Figure B1.1b The Complete Connection Picture........................................................................... B-3
B1.2 IPM-ATA-HD............................................................................................. B-4
Figure B1.2 IPM-ATA-HD Board Layout ....................................................................................... B-4
Table B1.2 IPM-ATA-HD Jumper Description ............................................................................... B-4
B1.3 IPM-ATA-CF.............................................................................................. B-5
Figure B1.3 IPM-ATA-CF Board Layout ........................................................................................ B-5
Table B1.3 IPM-ATA-CF Jumper Description................................................................................. B-5
B1.4 IPM-ATA-PCMCIA ..................................................................................... B-6
Figure B1.4 IPM-ATA-PCMCIA Board Layout ............................................................................... B-6
Table B1.4 IPM-ATA-PCMCIA Jumper Description ........................................................................ B-6
B1.5 Device Compatibility................................................................................ B-7
Table B1.5 Compatibility List...................................................................................................... B-7
B
C
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-1
IPM-ATA
Appendix B
B1 IPM-ATA CPU Extension
Inova Plug-In Module (IPM-) offers the user the ability to exchange a hard-disk for example with-
out having to remove the CPU from the CompactPCI enclosure and then dismantle it etc. Cur-
rently, three units exist that provide industry with hard-disk, Compact FLASH, MicroDrive or ATA
PCMCIA mass storage capability.
B1.1 J1 Interfaces
All IPM-ATA modules possess J1 for data communication between the CompactPCI backplane and
the mass storage unit(s) in question. Figure B1.1a illustrates the dedicated IPM-ATA backplane and
connectors.
Note:
The IPM-ATA modules can only be
used in CompactPCI systems that have
been prepared for rear I/O (C) or have
the IDE signals available on the rear
J2 connector that are in accordance
with the specification for RIO(C). In
addition, the rear J2 CompactPCI
connector must be present.
Figure B1.1a Dedicated IPM-ATA Backplane
PageB-2
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
IPM-ATA
B1.1 J1 Interfaces (Contd.)
®
Standard IDE ribbon-cable is used to connect J2 of the IPB-RIO-HD-FD module to the IPM’s dedi-
cated backplane. The use of ribbon cable permits the mass-storage device(s) to be positioned at
any convenient location within the CompactPCI enclosure. Figure B1.1b shows the complete
configuration (CompactPCI to IPM-)
Figure B1.1b The Complete Connection Picture
B
KEY:
C
1. IPM-ATA carrier board
2. Dedicated backplane with standard IDE ribbon cable and power cord interfaces
3. Y-Cable for bringing the power from the CompactPCI backplane and to this and another device
4. Standard IDE ribbon cable (30cm)
5. Inova rear I/O module (IPB-RIO-IDE-FD) with IDE and slim-line FD connections
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-3
IPM-ATA
Appendix B
B1.2 IPM-ATA-HD
The IPM-ATA-HD has provision for one standard notebook (2.5”) EIDE device (FLASH or hard-disk)
and one Compact FLASH or MicroDrive site. Figure B1.2 illustrates the significant connectors for
this device while Table B1.2 indicates the jumper positions for the various Master/Slave device
configurations.
Figure B1.2 IPM-ATA-HD Board Layout
1
2
3
Table B1.2 IPM-ATA-HD Jumper Description
Compact FLASH
or MicroDrive in J3
Jumper J6
Master
Slave
X
-
-
X
-
2-3
Open
-
-
It should be noted that the secondary IDE channel only is available for use by the IPB-ATA-HD (the
primary is on the CPU board itself). A Master device must be present either in the form of a hard-
disk, Compact FLASH, MicroDrive or CD-ROM etc. Slave only configurations and multi Master
configurations are not supported and will not work!
PageB-4
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
IPM-ATA
B1.3 IPM-ATA-CF
The IPM-ATA-CF has provision for one or two standard Compact FLASH or MicroDrive devices.
Figure B1.3 illustrates the significant connectors for this device while Table B1.3 indicates the
jumper settings for the various Master/Slave device configurations.
®
Figure B1.3 IPM-ATA-CF Board Layout
1
2
3
B
Table B1.3 IPM-ATA-CF Jumper Description
Compact FLASH
or MicroDrive in J3
Compact FLASH
or MicroDrive in J4
C
Jumper J6
Jumper J7
Master
Slave
Master
Slave
X
-
-
X
-
2-3
Open
-
X
-
-
X
-
2-3
Open
-
-
-
It should be noted that the secondary IDE channel only is available for use by the IPB-ATA-CF (the
primary is on the CPU board itself). A Master device must be present either in the form of an
external hard-disk, Compact FLASH, MicroDrive or CD-ROM etc. Slave only configurations and
multi Master configurations are not supported and will not work!
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-5
IPM-ATA
Appendix B
B1.4 IPM-ATA-PCMCIA
The IPM-ATA-PCMCIA has provision for one standard ATA PCMCIA device and one Compact
FLASH or MicroDrive site. Figure B1.4 illustrates the significant connectors for this device while
Table B1.4 indicates the jumper settings for the various Master/Slave device configurations.
Figure B1.4 IPM-ATA-PCMCIA Board Layout
1
2
3
Table B1.4 IPM-ATA-PCMCIA Jumper Description
Compact FLASH
or MicroDrive in J3
PCMCIA Device in J5
Jumper J8
Jumper J6
Master
Slave
Master
Slave
X
-
-
X
-
2-3
Open
-
X
-
-
X
-
2-3
Open
-
-
-
It should be noted that the secondary IDE channel only is available for use by the IPB-ATA-PCMCIA
(the primary is on the CPU board itself). A Master device must be present either in the form of an
external hard-disk, PCMCIA device, Compact FLASH, MicroDrive or CD-ROM etc. Slave only con-
figurations and multi Master configurations are not supported and will not work!
PageB-6
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix B
IPM-ATA
B1.5 Device Compatibility
Because of the diversity of Compact FLASH devices available with different architectures and error
recovery routines etc. there is a strong possibility that some Master / Slave combinations will fail to
be recognised by the BIOS. To help highlight the problem, Inova have provided the test report
shown in Table B1.5 which should be regarded as a guide when choosing to pick-and-mix de-
vices. Should devices other than those from the manufacturers indicated in the table be chosen,
then it may be prudent that Inova be contacted prior to commissioning.
®
Table B1.5 Compatibility List
Position
Compact FLASH Card
IBM Microdrive DMDM-10340
Empty
Result
Test
Jumper
Master
-
J3
J4
J3
J4
J3
J4
J3
J4
J3
J4
J3
J4
1
Windows NT4.0 Passed
M-Systems 64MByte Compact FLASH
Empty
Master
-
2
3
4
5
6
Windows NT4.0 Passed
IBM Microdrive DMDM-10340
IBM Microdrive DMDM-10340
IBM Microdrive DMDM-10340
M-Systems 64MByte Compact FLASH
IBM Microdrive DMDM-10340
M-Systems 64MByte Compact FLASH
M-Systems 64MByte Compact FLASH
IBM Microdrive DMDM-10340
Slave
Master
Slave
Master
Master
Slave
Master
Slave
Windows NT4.0 Passed
(incl. Strip Set Config.)
Windows NT4.0 Passed
Failed: M-Systems not
detected in BIOS
B
Windows NT4.0 Passed
C
CPUAppendix-B
©2001 Inova Computers GmbH
PageB-7
IPM-ATA
Appendix B
This page has been left blank intentionally.
PageB-8
©2001 Inova Computers GmbH
CPUAppendix-B
Appendix C
IPB-FPE12
®
IPB-FPE12
IPB-FPE12 Contents
C1 IPB-FPE12 CPU Extension ........ C-2
C1.1 J13 Interface for LPT1 & COM2 ............................................................... C-2
C1.2 IPB-FPE12 & Front-panel (4HP or 12HP) .................................................. C-2
Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ C-2
C1.3 LPT1 & COM2 Piggyback ........................................................................ C-3
Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12 .............................................................. C-3
Table C1.3 IPB-FPE12 Connector Description .............................................................................. C-4
C1.4 LPT1 Interface.......................................................................................... C-5
Figure C1.6 LPT1 Interface Pinout .............................................................................................. C-5
Table C1.6 LPT1 Connector Signals ............................................................................................ C-5
C1.5 COM2 Interface....................................................................................... C-6
Figure C1.5 COM2 Interface Pinout ........................................................................................... C-6
Table C1.5 COM2 Connector Signals ......................................................................................... C-6
C
C
CPUAppendix-C
©2001 Inova Computers GmbH
PageC-1
IPB-FPE12
Appendix C
C1 IPB-FPE12 CPU Extension
The Inova IPB-FPE12 adds LPT and COM2 functionality to any Inova CPU. The piggyback is avail-
able as a stand-alone device with its own 4HP front-panel or integrated within a 12HP K6 or PPC
front-panel. The information documented here is valid regardless of the connection choice.
C1.1 J13 Interface for LPT1 & COM2
The control of the LPT and COM2 interfaces is performed through the J13 connector on the CPU
base board. The location of this connector may be determined by referring to Section 1 - Product
Overview of the CPU User’s Manual. A flex cable from J13 connects to the interface board dis-
cussed in this section.
C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)
The Inova IPB-FPE12 interface is a small piggyback available as a stand-alone device with its own
4HP front-panel or integrated with the CPU as in figure C1.2.
Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
PageC-2
©2001 Inova Computers GmbH
CPUAppendix-C
Appendix C
IPB-FPE12
C1.3 LPT1 & COM2 Piggyback
Figure C1.3 illustrates the construction of the stand-alone IPB-FPE12 piggyback and the upperside
location of the J13 connector. The same mechanical construction applies to the integrated ver-
sion. Care should be taken to ensure that pin 1 of J13 on the CPU base board is linked by an
appropriate length of flex cable to pin 1 on the piggyback. To help with the orientation, the
connector flanks that are blue indicate the blue face of the flex-cable. Unmarked flanks indicate
the metallic connection of the flex-cable. Also, pin 1 has been highlighted by a red triangle.
®
Note:
Damage to the CPU board or the
piggyback may result if the flex cable
is positioned incorrectly. Inova will not
accept responsibility for negligent
actions!
Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12
J13
C
C
Note:
The physical connection of the IPB-
FPE12 is electrically identical regard-
less of the nature of connection
(stand-alone or integrated!)
CPUAppendix-C
©2001 Inova Computers GmbH
PageC-3
IPB-FPE12
Appendix C
Table C1.3 IPB-FPE12 Connector Description
Connector
Description
J13
LPT1 & COM2
Note:
Other Inova piggybacks (ICP-HD-1 & ICP-
HDE8) provide J13a to “daisy-chain” the
LPT1 / COM2 interfaces. If these connec-
tors are used for the integration of the
IPB-FPE12 then the COM2 port on these
piggybacks is disabled.
PageC-4
©2001 Inova Computers GmbH
CPUAppendix-C
Appendix C
IPB-FPE12
C1.4 LPT1 Interface
A front-panel with LPT1 and COM2 interfaces is either integrated into a 12HP standard CPU front-
panel or available as a separate 4HP unit. The piggyback located behind these interfaces connects
to the CPU-mounted J13 connector.
®
Figure C1.6 LPT1 Interface Pinout
13
25
1
14
Table C1.6 LPT1 Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
STROBE
PD1
2
4
PD0
PD2
5
PD3
6
PD4
7
PD5
8
PD6
9
PD7
10
12
14
16
18-25
ACK
PE
C
11
13
15
17
BUSY
SLCT
ERROR
SLCTIN
AUTOED
INIT
C
GND
CPUAppendix-C
©2001 Inova Computers GmbH
PageC-5
IPB-FPE12
Appendix C
C1.5 COM2 Interface
The COM2 port features a complete set of handshaking and modem control signals, maskable
interrupt generation and high-speed data transfer rates. A front-panel with LPT1 and COM2 inter-
faces is either integrated into a 12HP standard CPU front-panel or available as a separate 4HP unit.
The piggyback located behind these interfaces connects to the CPU-mounted J13 connector.
Figure C1.5 COM2 Interface Pinout
1
6
5
9
Table C1.5 COM2 Connector Signals
Signal
Pin No.
RS232
DCD
RxD
TxD
RS485
1
2
3
4
5
6
7
8
9
Note:
RxD, TxD +
RxD, TxD -
The standard piggyback configuration
has COM2 set for RS232 communication.
DTR
GND
DSR
RTS
CTS
RI
However, this device can be configured to
observe a two-wire non galvanically
separated RS485 protocol. The data
direction is governed by controlling the
UART’s RTS signal. Writing a hex value of
0B to this register allows data to be
transmitted. Writing 1B to this register
configures the device to receive data.
PageC-6
©2001 Inova Computers GmbH
CPUAppendix-C
Appendix D
IPB-RIO
®
IPB-RIO
IPB-RIO Contents
D1 IPB-RIO CPU Extension............ D-2
D1.1 IPB-RIO-HD-FD ....................................................................................... D-2
Figure D1.1 IPB-RIO-HD-FD ....................................................................................................... D-2
D1.2 IPB-RIO-HD-LPT-(FLEX) ........................................................................... D-3
Figure D1.2 IPB-RIO-HD-LPT-(FLEX)............................................................................................ D-3
D1.3 IPB-RIO-C-SHORT ................................................................................... D-4
Figure D1.3 IPB-RIO-C-SHORT ................................................................................................... D-4
Table D1.3 Rear I/O Type ‘C’ ..................................................................................................... D-4
D1.4 IPB-RIO-C-80MM.................................................................................... D-5
Figure D1.4 IPB-RIO-C-80MM.................................................................................................... D-5
C
D
CPUAppendix-D
©2001 Inova Computers GmbH
PageD-1
IPB-RIO
Appendix D
D1 IPB-RIO CPU Extension
To enhance the I/O and serviceability of their CPUs, Inova have introduced rear I/O modules that
connect to a CompactPCI connector on the rear of the Master Slot on the backplane. All standard
Inova backplanes are equipped with this R2 connector so that even if the rear I/O functionality is
not requested at time of order, it can be implemented at a later stage.
Currently, Inova have 4 rear I/O transition modules in their product range. Three of these are
documented here.
D1.1 IPB-RIO-HD-FD
As its name suggests, this transition module recovers the embedded IDE and floppy signals from
the CompactPCI backplane and presents them in a form ready for device connection. One of the
advantages of this module is its ability to attach an IDE device without direct flex-cable connection
to the CPU base board. This facilitates servicing and allows a CPU for example, to be switched
without touching the software stored on the HD. Likewise, a hard-disk can be exchanged without
having to disassemble the CPU!
Figure D1.1 IPB-RIO-HD-FD
IDE-Connection
Floppy
PageD-2
©2001 Inova Computers GmbH
CPUAppendix-D
Appendix D
IPB-RIO
D1.2 IPB-RIO-HD-LPT-(FLEX)
Similar to the IPB-RIO-HD-FD, this transition module recovers the embedded IDE and LPT signals
from the CompactPCI backplane and presents them in a form ready for device connection. This
time, instead of a standard IDE header, the IDE device is connected using the familiar Inova flex
cables. Also, a slim-line floppy disk may be attached using a suitable cable to the LPT connector
(J13). A switch in BIOS allows the user to ‘redefine’ the signals!
®
Figure D1.2 IPB-RIO-HD-LPT-(FLEX)
J4
(HARD DISK J10)
J3
(HARD DISK J9)
J2
(LPT J13)
C
D
Note:
If the LPT device is connected to this
transition module then a connection
cannot be made to the CPU base board.
Doing so could render the hardware
useless or cause any data communication
to fail.
CPUAppendix-D
©2001 Inova Computers GmbH
PageD-3
IPB-RIO
Appendix D
D1.3 IPB-RIO-C-SHORT
All Inova -RIO(C) compatible CPUs can take advantage of this transition module as it allows the
signals shown in table D1.3 to be recovered (used). Figure D1.3 illustrates this piggyback and
points to the available interfaces.
Figure D1.3 IPB-RIO-C-SHORT
Table D1.3 Rear I/O Type ‘C’
REAR I/O
Rear I/O - 'C'
OPTION
ETHERNET
USB
Note:
Second Channel*
Second Channel
Second Channel
Yes
The Inova PIII CPU can have both
Ethernet channels routed to the front-
panel. Utilising the rear I/O option while
communicating via the second Ethernet
channel on the front-panel will result in
data conflict.
FireWire
LPT 1 / FD
SPEAKER
EIDE
Yes
Yes
PageD-4
©2001 Inova Computers GmbH
CPUAppendix-D
Appendix D
IPB-RIO
D1.4 IPB-RIO-C-80MM
Similar to the -SHORT version, this transition module extends the signals shown in table D1.3 to a
rear panel. Naturally, not all enclosures are suitable for this type of connection and the following
must be considered.
®
{
{
{
Inova Desktop systems have an integrated fan - will the transition module interfere with it?
84HP Inova CoolBreeze systems are too short to accept an 80mm transition module.
Inova Industrial enclosures are available in 2 standard configurations:
{
{
WallMounting
RackMounting
{
Wall mounted racks are not suitable for rear I/O
The Inova rack mounted industrial enclosure must be delivered without rear panelling as
position of the transition module will vary depending on the chosen enclosure and
{
the
backplane.
Figure D1.4 IPB-RIO-C-80MM
C
D
CPUAppendix-D
©2001 Inova Computers GmbH
PageD-5
IPB-RIO
Appendix D
This page has been left blank intentionally.
PageD-6
©2001 Inova Computers GmbH
CPUAppendix-D
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