CM25-10153-2E
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
2
F MC-8L
8-BIT MICROCONTROLLER
MB89202/F202RA Series
HARDWARE MANUAL
2
F MC-8L
8-BIT MICROCONTROLLER
MB89202/F202RA Series
HARDWARE MANUAL
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL:http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
FUJITSU LIMITED
PREFACE
■ Purpose of This Manual and Intended Reader
The MB89202/F202RA series was developed as one of the general-purpose products of the
2
F MC-8L family, which contains original 8-bit one-chip microcontrollers for use with ASICs
(application specific ICs). The MB89202/F202RA series can be used in a wide range of
products from consumer products to industrial products.
This manual explains the functions and operations of the MB89202/F202RA series for product
development.
2
The F MC-8L Programming Manual contains details of the programming instructions.
2
Note: F MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of
FUJITSU LIMITED.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■ Structure of This Manual
This manual consists of the following 17 chapters and appendix.
This chapter describes the features and basic specification of the MB89202/F202RA series.
This chapter describes the precautions to be taken when handling the MB89202/F202RA
series.
This chapter describes the functions and operation of the CPU.
This chapter describes the functions and operation of the I/O ports.
This chapter describes the functions and operation of the time-base timer.
This chapter describes the functions and operation of the watchdog timer.
This chapter describes the functions and operation of the 8-bit PWM timer.
This chapter describes the functions and operation of the 8/16-bit capture timer/counter.
This chapter describes the functions and operation of the 12-bit PPG timer.
i
This chapter describes the functions and operation of external interrupt circuit 1 (edge).
This chapter describes the functions and operation of external interrupt circuit 2 (level).
This chapter describes the functions and operation of the A/D converter.
This chapter describes the functions and operation of UART.
This chapter describes the functions and operation of the 8-bit serial I/O.
This chapter describes the functions and operation of the buzzer output.
This chapter describes the functions and operation of the wild registers.
This chapter describes the functions and operation of the flash memory.
This appendix shows the I/O map and instructions list.
ii
•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;
FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out
of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the
information.
•
•
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed
as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right
of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property
right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air
traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
•
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
•
Exportation/release of any products described in this document may require necessary procedures in accordance with
the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
•
Copyright© 2005-2008 FUJITSU LIMITED All rights reserved
iii
READING THIS MANUAL
■ Example Notation of Register Names and Pin Names
❍ Example notation of register names and bit names
By writing 1 into the sleep bit of the standby control register (STBC : SLP), ...
Bit abbreviation
Register abbreviation
Bit name
Register name
Prohibit the output of interrupt request of the time-base timer (TBTC : TBIE = 0).
Setting data
Bit abbreviation
Register abbreviation
If interrupt enabled (CCR : I = 1) is specified, the interrupt is accepted.
Current state
Bit abbreviation
Register abbreviation
❍ Example notation of multi-use pins
P33/EC pin
Some pins can switch functions according to a setting made by a program or other method.
These pins are called multi-use pins. For multi-use pins, the names corresponding to
functions are listed and divided by /.
iv
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
Features of MB89202/F202RA Series ................................................................................................ 2
MB89202/F202RA Series Product Lineup .......................................................................................... 4
Differences between Models .............................................................................................................. 6
Block Diagram of MB89202/F202RA Series ....................................................................................... 7
Pin Assignment ................................................................................................................................... 8
Package Dimensions ........................................................................................................................ 10
Pin Functions Description ................................................................................................................. 12
I/O Circuit Types ............................................................................................................................... 14
CHAPTER 2 HANDLING DEVICES ................................................................................ 17
Precautions on Handling Devices ..................................................................................................... 18
CHAPTER 3 CPU ............................................................................................................ 21
Memory Space .................................................................................................................................. 22
Specific-purpose Areas ............................................................................................................... 24
Location of 16-bit Data on Memory ............................................................................................. 26
Dedicated Register ........................................................................................................................... 27
Condition Code Register (CCR) .................................................................................................. 29
Register Bank Pointer (RP) ......................................................................................................... 31
General-Purpose Registers .............................................................................................................. 32
Interrupts ........................................................................................................................................... 34
Interrupt Level Setting Registers (ILR1 to ILR4) .......................................................................... 36
Steps in the Interrupt Operation .................................................................................................. 37
Multiple Interrupts ........................................................................................................................ 39
Interrupt Processing Time ........................................................................................................... 40
Stack Operation at Interrupt Processing ...................................................................................... 41
Stack Area for Interrupt Processing ............................................................................................. 42
Reset Flag Register (RSFR) ........................................................................................................ 45
External Reset Pin ....................................................................................................................... 47
Reset Operation .......................................................................................................................... 48
State of Each Pin at Reset .......................................................................................................... 50
Clock ................................................................................................................................................. 51
Clock Generator .......................................................................................................................... 53
Clock Controller ........................................................................................................................... 54
System Clock Control Register (SYCC) ...................................................................................... 56
Clock Mode .................................................................................................................................. 58
Oscillation Stabilization Wait Time .............................................................................................. 60
Standby Mode (Low-Power Consumption Mode) ............................................................................. 62
Operations in Standby Mode ....................................................................................................... 63
Sleep Mode ................................................................................................................................. 64
Stop Mode ................................................................................................................................... 65
v
Standby Control Register (STBC) ............................................................................................... 66
Diagram for State Transition in Standby Mode ............................................................................ 68
Notes on Standby Mode .............................................................................................................. 70
Memory Access Mode ...................................................................................................................... 72
CHAPTER 4 I/O PORTS .................................................................................................. 75
Overview of I/O Ports ........................................................................................................................ 76
Port 0 ................................................................................................................................................ 78
Registers of Port 0 (PDR0, DDR0, and PUL0) ............................................................................ 80
Operations of Port 0 Functions .................................................................................................... 82
Port 3 ................................................................................................................................................ 84
Registers of Port 3 (PDR3, DDR3, PUL3) ................................................................................... 86
Operations of Port 3 Functions .................................................................................................... 88
Port 4 ................................................................................................................................................ 90
Registers of Port 4 (PDR4) .......................................................................................................... 92
Operations of Port 4 Functions .................................................................................................... 93
Port 5 ................................................................................................................................................ 94
Registers of Port 5 (PDR5, DDR5, PUL5) ................................................................................... 96
Operations of Port 5 Functions .................................................................................................... 98
Port 6 .............................................................................................................................................. 100
Registers of Port 6 (PDR6, DDR6, PUL6) ................................................................................. 103
Operations of Port 6 Functions .................................................................................................. 105
Port 7 .............................................................................................................................................. 107
Registers of Port 7 (PDR7, DDR7, PUL7) ................................................................................. 109
Operations of Port 7 Functions .................................................................................................. 111
Programming Example of I/O Port .................................................................................................. 113
CHAPTER 5 TIME-BASE TIMER .................................................................................. 115
Overview of Time-base Timer ......................................................................................................... 116
Configuration of Time-base Timer .................................................................................................. 118
Time-base Timer Control Register (TBTC) ..................................................................................... 119
Interrupt of Time-base Timer .......................................................................................................... 121
Operations of Time-base Timer Functions ..................................................................................... 122
Notes on Using Time-base Timer ................................................................................................... 124
Program Example for Time-base Timer .......................................................................................... 125
CHAPTER 6 WATCHDOG TIMER ................................................................................ 127
Overview of Watchdog Timer ......................................................................................................... 128
Configuration of Watchdog Timer ................................................................................................... 129
Watchdog Control Register (WDTC) .............................................................................................. 130
Operations of Watchdog Timer Functions ...................................................................................... 131
Notes on Using Watchdog Timer .................................................................................................... 132
Program Example for Watchdog Timer .......................................................................................... 133
vi
CHAPTER 7 8-BIT PWM TIMER ................................................................................... 135
Overview of 8-bit PWM Timer ......................................................................................................... 136
Configuration of 8-bit PWM Timer .................................................................................................. 139
Pin of 8-bit PWM Timer ................................................................................................................... 141
Registers of 8-bit PWM Timer ......................................................................................................... 142
PWM Control Register (CNTR) ................................................................................................. 143
PWM Compare Register (COMR) ............................................................................................. 145
Interrupt of 8-bit PWM Timer .......................................................................................................... 147
Operations of the Interval Timer Functions ..................................................................................... 148
Operations of the 8-bit PWM Timer Functions ................................................................................ 150
States in Each Mode During Operation .......................................................................................... 152
Notes on Using 8-bit PWM Timer ................................................................................................... 155
7.10 Program Example for PWM Timer .................................................................................................. 157
Overview of 8/16-bit Capture Timer/Counter .................................................................................. 162
Configuration of 8/16-bit Capture Timer/Counter ............................................................................ 166
Pins of 8/16-bit Capture Timer/Counter .......................................................................................... 168
Registers of 8/16-bit Capture Timer/Counter .................................................................................. 170
Capture Control Register (TCCR) ............................................................................................. 171
Timer 0 Control Register (TCR0) ............................................................................................... 173
Timer 1 Control Register (TCR1) ............................................................................................... 175
Timer Output Control Register (TCR2) ...................................................................................... 177
Timer 0 Data Register (TDR0) ................................................................................................... 178
Timer 1 Data Register (TDR1) ................................................................................................... 180
Capture Data Registers H and L (TCPH and TCPL) ................................................................. 182
8/16-bit Capture Timer/Counter of Interrupts .................................................................................. 183
Explanation of Operations of Interval Timer Functions ................................................................... 185
Operation of Counter Functions ...................................................................................................... 189
Functions of Operations of Capture Functions ............................................................................... 193
8/16-bit Capture Timer/Counter Operation in Each Mode .............................................................. 197
8.10 Notes on Using 8/16-bit Capture Timer/Counter ............................................................................ 198
8.11 Program Example for 8/16-bit Capture Timer/Counter ................................................................... 200
CHAPTER 9 12-BIT PPG TIMER .................................................................................. 205
Overview of 12-bit PPG Timer ........................................................................................................ 206
Configuration of 12-bit PPG Timer Circuit ...................................................................................... 209
Pin of 12-bit PPG Timer .................................................................................................................. 211
Registers of 12-bit PPG Timer ........................................................................................................ 213
12-bit PPG Control Register 1 (RCR21) .................................................................................... 214
12-bit PPG Control Register 2 (RCR22) .................................................................................... 215
12-bit PPG Control Register 3 (RCR23) .................................................................................... 216
12-bit PPG Control Register 4 (RCR24) .................................................................................... 218
Operations of 12-bit PPG Timer Functions ..................................................................................... 219
Notes on Using 12-bit PPG Timer .................................................................................................. 221
Program Example for 12-bit PPG Timer ......................................................................................... 223
vii
10.1 Overview of External Interrupt Circuit 1 .......................................................................................... 226
10.2 Configuration of External Interrupt Circuit 1 .................................................................................... 227
10.3 Pins of External Interrupt Circuit 1 .................................................................................................. 229
10.4 Registers of External Interrupt Circuit 1 .......................................................................................... 231
10.4.1 External Interrupt Control Register 1 (EIC1) .............................................................................. 232
10.4.2 External Interrupt Control Register 2 (EIC2) .............................................................................. 235
10.5 Interrupt of External Interrupt Circuit 1 ............................................................................................ 237
10.6 Operations of External Interrupt Circuit 1 ....................................................................................... 239
10.7 Program Example for External Interrupt Circuit 1 ........................................................................... 241
11.1 Overview of External Interrupt Circuit 2 .......................................................................................... 244
11.2 Configuration of External Interrupt Circuit 2 .................................................................................... 245
11.3 Pins of External Interrupt Circuit 2 .................................................................................................. 246
11.4 Registers of External Interrupt Circuit 2 .......................................................................................... 249
11.4.1 External Interrupt 2 Control Register (EIE2) .............................................................................. 250
11.4.2 External Interrupt 2 Flag Register (EIF2) ................................................................................... 252
11.5 Interrupt of External Interrupt Circuit 2 ............................................................................................ 253
11.6 Operations of External Interrupt Circuit 2 ....................................................................................... 254
11.7 Program Example for External Interrupt Circuit 2 ........................................................................... 256
CHAPTER 12 A/D CONVERTER .................................................................................... 259
12.1 Overview of A/D Converter ............................................................................................................. 260
12.2 Configuration of A/D Converter ....................................................................................................... 261
12.3 Pins of A/D Converter ..................................................................................................................... 263
12.4 Registers of A/D Converter ............................................................................................................. 265
12.4.1 A/D Control Register 1 (ADC1) .................................................................................................. 266
12.4.2 A/D Control Register 2 (ADC2) .................................................................................................. 268
12.4.3 A/D Data Register (ADDH and ADDL) ...................................................................................... 270
12.4.4 A/D Enable Register (ADEN) ..................................................................................................... 271
12.5 Interrupt of A/D Converter ............................................................................................................... 272
12.6 Operations of A/D Converter Functions .......................................................................................... 273
12.7 Notes on Using A/D Converter ....................................................................................................... 275
12.8 Program Example for A/D Converter .............................................................................................. 277
CHAPTER 13 UART ........................................................................................................ 279
13.1 Overview of UART .......................................................................................................................... 280
13.2 Configuration of UART .................................................................................................................... 284
13.3 Pins of UART .................................................................................................................................. 287
13.4 Registers of UART .......................................................................................................................... 289
13.4.1 Serial Mode Control Register (SMC) ......................................................................................... 290
13.4.2 Serial Rate Control Register (SRC) ........................................................................................... 292
13.4.3 Serial Status and Data Register (SSD) ..................................................................................... 294
13.4.4 Serial Input Data Register (SIDR) ............................................................................................. 297
13.4.5 Serial Output Data Register (SODR) ......................................................................................... 298
13.4.6 Clock Divider Selection Register (UPC) .................................................................................... 299
viii
13.4.7 Serial Switch Register (SSEL) ................................................................................................... 301
13.5 Interrupt of UART ............................................................................................................................ 303
13.6 Operations of UART Functions ....................................................................................................... 304
13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3) ....................................................... 306
13.6.2 Reception Operations (Operating Mode 0, 1, or 3) ................................................................... 307
13.6.3 Reception Operations (Operating Mode 2 Only) ....................................................................... 309
13.7 Program Example for UART ........................................................................................................... 311
CHAPTER 14 8-BIT SERIAL I/O ..................................................................................... 313
14.1 Overview of 8-Bit Serial I/O ............................................................................................................ 314
14.2 Configuration of 8-Bit Serial I/O ...................................................................................................... 315
14.3 Pins of 8-Bit Serial I/O .................................................................................................................... 317
14.4 Registers of 8-Bit Serial I/O ............................................................................................................ 319
14.4.1 Serial Mode Register (SMR) ...................................................................................................... 320
14.4.2 Serial Data Register (SDR) ....................................................................................................... 323
14.5 Interrupt of 8-Bit Serial I/O .............................................................................................................. 324
14.6 Operations of Serial Output Functions ............................................................................................ 325
14.7 Operations of Serial Input Functions .............................................................................................. 327
14.8 8-Bit Serial I/O Operation in Each Mode ......................................................................................... 329
14.9 Notes on Using 8-Bit Serial I/O ....................................................................................................... 333
14.10 Example of 8-Bit Serial I/O Connection .......................................................................................... 334
14.11 Program Example for 8-Bit Serial I/O ............................................................................................. 336
CHAPTER 15 BUZZER OUTPUT .................................................................................... 339
15.1 Overview of the Buzzer Output ....................................................................................................... 340
15.2 Configuration of the Buzzer Output ................................................................................................ 341
15.3 Pin of the Buzzer Output ................................................................................................................. 342
15.4 Buzzer Register (BZCR) ................................................................................................................. 343
15.5 Program Example for Buzzer Output .............................................................................................. 345
CHAPTER 16 WILD REGISTER FUNCTION .................................................................. 347
16.1 Overview of the Wild Register Function .......................................................................................... 348
16.2 Configuration of the Wild Register Function ................................................................................... 349
16.3 Registers of the Wild Register Function ......................................................................................... 350
16.3.1 Data Setting Registers (WRDR0 and WRDR1) ......................................................................... 351
16.3.2 Higher Address Set Registers (WRARH0 and WRARH1) ......................................................... 352
16.3.3 Lower Address Set Registers (WRARL0 and WRARL1) ........................................................... 353
16.3.4 Address Comparison EN Register (WREN) .............................................................................. 354
16.3.5 Data Test Set Register (WROR) ............................................................................................... 355
16.4 Operations of the Wild Register Functions ..................................................................................... 356
ix
CHAPTER 17 FLASH MEMORY ..................................................................................... 357
17.1 Overview of Flash Memory ............................................................................................................. 358
17.2 Flash Memory Control Status Register (FMCS) ............................................................................. 359
17.3 Starting the Flash Memory Automatic Algorithm ............................................................................ 361
17.4 Confirming the Automatic Algorithm Execution State ..................................................................... 362
17.4.1 Data Polling Flag (DQ7) ............................................................................................................ 363
17.4.2 Toggle Bit Flag (DQ6) ................................................................................................................ 364
17.4.3 Timing Limit Exceeded Flag (DQ5) ........................................................................................... 365
17.4.4 Toggle Bit-2 Flag (DQ2) ............................................................................................................ 366
17.5 Detailed Explanation of Writing to Erasing Flash Memory .............................................................. 367
17.5.1 Setting The Read/Reset State ................................................................................................... 368
17.5.2 Writing Data ............................................................................................................................... 369
17.5.3 Erasing All Data (Erasing Chips) ............................................................................................... 371
17.6 Flash Security Feature .................................................................................................................... 372
17.7 Notes on using Flash Memory ........................................................................................................ 373
APPENDIX A I/O Map ............................................................................................................................... 376
APPENDIX B Overview of the Instructions ................................................................................................ 380
B.1 Addressing ..................................................................................................................................... 383
B.2 Special Instructions ........................................................................................................................ 387
B.3 Bit Manipulation Instructions (SETB and CLRB) ............................................................................ 391
B.4 F MC-8L Instructions List ............................................................................................................... 392
B.5 Instruction Map ............................................................................................................................... 399
APPENDIX C Mask Options ...................................................................................................................... 400
APPENDIX D Programming EPROM with Evaluation Chip ........................................................................ 401
APPENDIX E Pin State of the MB89202/F202RA Series .......................................................................... 402
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
-
The followings product name is changed.
(MB89202 →MB89202/F202RA)
The followings term is changed.
(source oscillation →oscillation frequency)
6
1.3 Differences between
Models
"Notes:" is changed.
(The followings sentence is deleted.
"• At turning on the power, when the device is used without inputting the external
reset, select "reset output supported" and "power-on reset supported" by mask
option.")
The followings package is changed in Table 1.3-1.
(FPT-34P-M03 →FPT-32P-M03)
12
19
1.7 Pin Functions
RST pin in Table 1.7-1 is changed.
2.1 Precautions on
Handling Devices
"● External pull-up for the External Reset Pin (RST) of MB89F202/F202RA" is
changed.
24
3.1.1 Specific-purpose
Areas
The summary is changed.
"■ General-purpose Register Area (address: 0100 to 01FF )" is changed.
H
H
"■ Vector Table Area (Address: FFC0 to FFFF )" is changed.
H
H
44
3.5 Reset
"● Power-on reset" is changed.
"Note:" is deleted.
56
57
3.6.3 System Clock
Control Register (SYCC)
Figure 3.6-5 is changed.
Table 3.6-1 is changed.
Figure 6.3-1 is changed.
130
6.3 Watchdog Control
Register (WDTC)
186
8.6 Explanation of
Operations of Interval
Timer Functions
"● 8-bit mode"is changed.
(The followings sentence is deleted.
"The initial value of the square wave output is "L" level. The square wave output is
initialized by writing "0" to the TSTR bit of the timer control register (TCR).")
264
308
12.3 Pins of A/D
Converter
"■ Block Diagram of the Pins Related to the A/D Converter" is changed.
("Note:" is deleted.)
13.6.2 Reception
Operations (Operating
Mode 0, 1, or 3)
"■ Reception Operations (Operating Mode 0, 1, or 3)" is changed.
("Note:" is changed.)
xi
Page
Changes (For details, refer to main body.)
310
13.6.3 Reception
Operations (Operating
Mode 2 Only)
"■ Reception Operations (Operating Mode 2 Only)" is changed.
("Note:" is changed.)
358
370
17.1 Overview of Flash
Memory
"■ High voltage supply on RST pin (applicable to MB89F202RA only)" is added.
17.5.2 Writing Data
Figure 17.5-1 is changed.
(F555 →F554)
2
394
Table B.4-2 is changed.
B.4 F MC-8L
("No.22 DECW A" is changed.)
Instructions List
The vertical lines marked in the left side of the page show the changes.
xii
CHAPTER 1 OVERVIEW
1.1
Features of MB89202/F202RA Series
The MB89202/F202RA series contains general-purpose single-chip microcontrollers that
incorporate a full range of peripheral functions such as A/D converter, UART, PWM
timer, PPG, capture timer/counter and external interrupts as well as a compact
instruction set.
■ Features of MB89202/F202RA Series
2
● F MC-8L CPU core
•
•
•
•
•
Instruction set most suitable for controllers
Multiplication and division instruction
16-bit operation
Branch instruction by bit test
Bit operation instruction, and others
● 4-system timers
•
•
•
•
8/16-bit capture timer/counter (8-bit capture timer/counter + 8-bit timer or 16-bit capture timer/counter)
8-bit PWM timer (also available as an interval timer)
21-bit time-base timer
Watchdog timer
● 10-bit A/D converter
•
•
10-bit A/D × 8 channels
Activation by 8/16-bit capture timer/counter output is possible.
● Programmable pulse generator (PPG)
•
Pulse width and cycle are software selectable (12-bit PPG).
● UART
•
6, 7, or 8 transfer data length
● 8-bit serial I/O
•
•
Available when switched from UART
LSB first/MSB first selectability
● External interrupts
External interrupt 1 (edge detection × 3 pins) has three independent inputs and can be used for wake-up
•
from low-power consumption mode. (The edge detection can be selected from rising-edge, falling-edge,
and both-edge modes.)
2
CHAPTER 1 OVERVIEW
•
External interrupt 2 (level detection × 8 pins, 1 channel) has eight independent inputs and can be used
for wake-up from low-power consumption mode. (L level detection function is supported.)
● Low-power consumption modes (standby modes)
•
•
Stop mode (The oscillation is stopped so that current consumption is minimal.)
Sleep mode (The CPU is stopped so that the current consumption is reduced by one-third of normal
consumption.)
● Up to 26 pins of I/O ports
•
General-purpose I/O ports (CMOS): 26 pins (4 of which can be used as N-ch open-drain I/O ports.)
● Wild registers
•
•
2-byte data at two addresses are available.
When a specific address or data is used on a wild register, the data in the ROM area is changed.
● 16 KB Flash with read protection
Once the protection code is written in the specified address, the FLASH content cannot be read by
parallel/serial programmer.
•
3
CHAPTER 1 OVERVIEW
1.2
MB89202/F202RA Series Product Lineup
Four MB89202 series models are available. Table 1.2-1 shows the models and Table 1.2-
2 shows the CPU and peripheral functions.
■ MB89202/F202RA Series Models
Table 1.2-1 MB89202/F202RA Series Models
MB89201
MB89F202/F202RA
MB89V201
Evaluation product
(for development)
Flash memory product
(read protection)
Mask ROM product
Classification
32K × 8 bits
(External EPROM )
16K × 8 bits
16K × 8 bits
(Internal mask ROM)
ROM size
RAM size
*2
(Internal Flash)
512 × 8 bits
Low-power consumption
(standby mode)
Sleep mode and stop mode
Process
CMOS
*1
2.7V to 5.5V
3.5V to 5.5V
2.2V to 5.5V
Operating voltage
*1: The minimum operating voltage varies with conditions such as operating frequency, functions, and connecting
ICE.
*2: MBM27C256A is used as the external ROM.
4
CHAPTER 1 OVERVIEW
Table 1.2-2 CPU and Peripheral Functions of MB89202/F202RA Series
Item
Specification
Number of basic instructions:
Instruction bit length:
Instruction length:
136 instructions
8 bits
1 to 3 bytes
1, 8, or 16 bits
CPU function
Data bit length:
Minimum instruction execution time: 0.32 to 5.1 µs (at 12.5 MHz)
Interrupt processing time: 2.88 to 46.1 µs (at 12.5 MHz)
General-purpose I/O port: 26 pins (Also serve as peripherals. 4 of which can be used as N-ch
open-drain I/O ports.)
Port
21-bit
21 bits
time-base
Interrupt cycle: 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5MHz main clock
timer
Watchdog
timer
Reset occurrence cycle: When the main clock is at 12.5 MHz (minimum 335.5 ms)
8-bit interval timer operation (Square wave output is supported. Operating clock cycle:
8-bit
PWM
timer
1 t
, 16 t
, 64 t
, and 8/16-bit capture timer/counter output)
INST
INST
INST
8-bit resolution PWM operation (Conversion cycle:
256 t , 4096 t , 16384 t and 256 times 8/16-bit capture timer/counter output)
INST
INST
INST
8/16-bit
capture
timer/
8-bit capture timer/counter × 1 channel + 8-bit timer or 16-bit capture timer/counter × 1 channel
When timer 0 or a 16-bit counter is operating, event-counting operation by external clock input
and square wave output are supported.
counter
UART
Transfer data length: 6, 7, or 8 bits
Periphera
l function
8 bits length, LSB first/MSB first selectability
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks: 2 t
8-bitserial
I/O
, 8 t
, 32 t
)
INST
INST
INST
12-bit
Output frequency: Pulse width and cycle are selectable.
PPG timer
External
3 channels (interrupt vector, request flag, and request output enable)
interrupt 1 Edge selectability (selectable from rising edge, falling edge, and both-edge modes)
(wake-up) Also available for wake-up from stop or sleep (Edge detection is also available in stop mode.)
External
8 inputs 1 channel (L level interrupt and input enable are independent.)
interrupt 2 Also available for wake-up from stop or sleep (Level detection is also available in stop mode.)
(wake-up)
10-bit resolution × 8 channels
10-bit A/D
converter
A/D conversion function (Conversion time: 38 t
)
INST
Continuous activation by 8/16-bit capture timer/counter output or time-base timer output.
Wild
register
8-bit × 2
Note:
The oscillation is 12.5 MHz unless another condition such as the main clock maximum speed, the clock
cycle value, or conversion time is stated.
5
CHAPTER 1 OVERVIEW
1.3
Differences between Models
This section describes the precautions to be taken when selecting a MB89202/F202RA
series model.
■ Precautions when Selecting a Model
Table 1.3-1 Differences between Models
Package
MB89201
MB89F202/F202RA
MB89V202
DIP-32P-M06
FPT-32P-M03
FPT-64P-M03
● Current consumption
•
When operated at a low speed, the current consumption of a model with a flash is greater than that of a
model with a mask ROM, though the current consumption in sleep or stop mode is the same.
Notes:
•
•
For details on current consumption and electrical characteristics of A/D converter, see the electrical
characteristics in the Data Sheet.
6
CHAPTER 1 OVERVIEW
1.4
Block Diagram of MB89202/F202RA Series
Figure 1.4-1 shows the block diagram of the MB89202/F202RA series.
■ Block Diagram of MB89202/F202RA Series
Figure 1.4-1 Block Diagram of MB89202/F202RA Series
X0
Main clock
Time-base timer
oscillator
X1
Clock controller
CMOS I/O port
Reset circuit
RST
8-bit PWM
P50 / PWM
2
P60, P61
CMOS I/O port
UART prescaler
*1P70
to
3
CMOS I/O port
*1P72
UART
P04 / INT24
CMOS I/O port
4
P30 / UCK / SCK
P31 / UO / SO
P32 / UI / SI
to
P07 / INT27
External
interrupt2
(wake-up)
8
2
2
P02 / INT22 / AN6,
P03 / INT23 / AN7
8-bit
serial I/O
4
P00 / INT20 / AN4,
P01 / INT21 / AN5
P33 / EC
8/16-bit
capture timer/
counter
10-bit A/D
converter
4
P34 / TO / INT10
*1P40 / AN0
to
4
*1P43 / AN3
3
P35 / INT11
P36 / INT12
External interrupt1
CMOS I/O port
(N-ch OD)
2
*
512 or 256 bytes RAM
12-bit PPG
F2MC - 8 L CPU
P37 / BZ / PPG
Other pins
Buzzer output
2
*
VCC, VSS, C
16K or 8K bytes ROM
CMOS I/O port
Wild register
*1: Large-current drive type
*2 : Check section "3.1 Memory Space"
7
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
Figure 1.5-1 and Figure 1.5-2 show the pin assignment of the MB89202/F202RA series.
■ Pin Assignment of DIP-32P-M06
Figure 1.5-1 Pin Assignment of DIP-32P-M06
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P60
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
2
P03/INT23/AN7
P02/INT22/AN6
P01/INT21/AN5
P00/INT20/AN4
P43/AN3*
P42/AN2*
P41/AN1*
P40/AN0*
P72*
3
4
5
P61
6
RST
7
X0
8
X1
9
VSS
10
11
12
13
14
15
16
P37/BZ/PPG
P36/INT12
P35/INT11
P34/TO/INT10
P33/EC
C
P71*
P70*
P50/PWM
P30/UCK/SCK
P31/UO/SO
P32/UI/SI
* : Large-current drive type
8
CHAPTER 1 OVERVIEW
■ Pin Assignment of FPT-34P-M03
Figure 1.5-2 Pin Assignment of FPT-34P-M03
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P60
VCC
1
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
P03/INT23/AN7
P02/INT22/AN6
P01/INT21/AN5
P00/INT20/AN4
3
4
5
*
P61
6
P43/AN3
*
RST
7
P42/AN2
*
X0
8
P41/AN1
*
X1
9
P40/AN0
*
VSS
10
11
12
13
14
15
16
17
P72
*
P37/BZ/PPG
P36/INT12
P35/INT11
P34/TO/INT10
P33/EC
N.C.
P71
*
P70
N.C.
P50/PWM
P30/UCK/SCK
P31/UO/SO
C
P32/UI/SI
* : Large-current drive type
Note: N.C.: Do not use because it is connected internally.
9
CHAPTER 1 OVERVIEW
1.6
Package Dimensions
Two different packages are available for MB89202/F202RA series.
■ Package Dimension of DIP-32P-M06
Figure 1.6-1 Package Dimension of DIP-32P-M06
32-pin plastic SH-DIP
Lead pitch
Low space
1.778 mm
10.16 mm
Sealing method
Plastic mold
(DIP-32P-M06)
32-pin plastic SH-DIP
Note 1) * : These dimensions do not include resin protrusion.
(DIP-32P-M06)
Note 2) Pins width and pins thickness include plating thickness.
+0.20
–0.30
*28.00
+.008
1.102 –.012
INDEX
*8.89±0.25
(.350±.010)
+0.30
–0.20
1.02
.040 +.012
–.008
+0.70
–0.20
4.70
0.51(.020)
MIN.
+.028
.185 –.008
+0.20
–0.30
.130 +–..001028
3.30
+0.03
–0.07
0.27
.011+.001
–.003
10.16(.400)
+0.08
–0.12
1.778(.070)
0.48
1.27(.050)
MAX.
M
0.25(.010)
0~15˚
.019+–..000053
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003 FUJITSU LIMITED D32018S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
10
CHAPTER 1 OVERVIEW
■ Package Dimension of FPT-34P-M03
Figure 1.6-2 Package Dimension of FPT-34P-M03
34-pin plastic SSOP
Lead pitch
0.65 mm
6.10 × 11.00 mm
Gullwing
Package width
package length
×
Lead shape
Sealing method
Plastic mold
Mounting height
1.45 mm MAX
P-SSOP34-6.1×11-0.65
Code
(Reference)
(FPT-34P-M03)
34-pin plastic SSOP
(FPT-34P-M03)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
111.00±0.10(.433±.004)
*
0.17±0.03
(.007±.001)
34
18
Details of "A" part
2 6.10±0.10
(.240±.004) (.319±.008)
8.10±0.20
*
1.25 +0.20
–0.10
–.004
INDEX
(Mounting height)
.049 +.008
0.25(.010)
0~8˚
1
17
"A"
0.24 +0.08
.009 +.003
–0.07
0.65(.0265)
M
0.10(.004)
0.50±0.20
0.10±0.10
–.003
(.020±.008)
(.004±.004)
(Stand off)
0.60±0.15
(.024±.006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003 FUJITSU LIMITED F34003S-c-2-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
11
CHAPTER 1 OVERVIEW
1.7
Pin Functions Description
Table 1.7-1 describes the I/O pins and functions.
The letters in the circuit type column shown in Table 1.7-1 correspond to the letters in
the Circuit Type column shown in Table 1.8-1 .
■ Pin Functions Description
Table 1.7-1 Pin Functions Description (1/2)
Pin No.
Pin
name
Circuit
type
Function
*1
*2
SHDIP32
SSOP34
8
8
X0
A
Pins for connecting the crystal for the main clock. To use an
external clock, input the signal to X0 and leave X1 open.
9
9
X1
5, 6
5, 6
P60,
P61
H / E
C
General-purpose CMOS input port.
7
7
RST
Reset I/O pin.
This pin serves as an N-ch open-drain reset output and a reset input
as well. The reset is a hysteresis input.
It outputs the "L" signal in response to an internal reset request.
Also, it initializes the internal circuit upon input of the "L" signal.
28, 29
30, 31
P00/
G
G
D
General-purpose CMOS I/O ports.
INT20/
AN4,
P01/
INT21/
AN5
These pins also serve as an input (wake-up input) of external
interrupt 2 or as an 10-bit A/D converter analog input. The input of
external interrupt 2 is a hysteresis input.
30, 31
32, 33
P02/
General-purpose CMOS I/O ports.
INT22/
AN6,
P03/
INT23/
AN7
These pins also serve as an input (wake-up input) of external
interrupt 2 or as an 10-bit A/D converter analog input. The input of
external interrupt 2 is a hysteresis input.
1 to 4
1 to 4
P04/
INT24
to
General-purpose CMOS I/O ports.
These pins also serve as an input (wake-up input) of external
interrupt 2. The input of external interrupt 2 is a hysteresis input.
P07/
INT27
19
18
20
19
P30/
UCK/
SCK
B
E
General-purpose CMOS I/O ports.
This pin also serves as the clock I/O pin for the UART or 8-bit
serial I/O. The resource is a hysteresis input.
P31/
UO/SO
General-purpose CMOS I/O ports.
This pin also serves as the data output pin for the UART or 8-bit
serial I/O.
12
CHAPTER 1 OVERVIEW
Table 1.7-1 Pin Functions Description (2/2)
Pin No.
Pin
name
Circuit
type
Function
*1
*2
SHDIP32
SSOP34
17
18
P32/UI/
SI
B
General-purpose CMOS I/O ports.
This pin also serves as the data input pin for the UART or 8-bit
serial I/O. The resource is a hysteresis input.
15
14
15
14
P33/EC
B
B
General-purpose CMOS I/O ports.
This pin also serves as the external clock input pin for the 8/16-bit
capture timer/counter. The resource is a hysteresis input.
P34/
General-purpose CMOS I/O ports.
TO/
INT10
This pin also serves as the output pin for the 8/16-bit capture timer/
counter or as the input pin for external interrupt 1. The resource is a
hysteresis input.
13
12
11
20
13
12
11
21
P35/
INT11
B
B
E
General-purpose CMOS I/O ports.
These pins also serve as the input pin for external interrupt 1. The
resource is a hysteresis input.
P36/
INT12
General-purpose CMOS I/O ports.
These pins also serve as the input pin for external interrupt 1. The
resource is a hysteresis input.
P37/
BZ/
PPG
General-purpose CMOS I/O ports.
This pin also serves as the buzzer output pin or the 12-bit PPG
output pin.
P50/
PWM
E
F
General-purpose CMOS I/O ports.
This pin also serves as the 8-bit PWM timer output pin.
24 to 27
26 to 29
P40/
General-purpose CMOS I/O ports.
AN0 to
P43/
These pins can also be used as N-ch open-drain ports.
These pins also serve as 10-bit A/D converter analog input pins.
AN3
21 to 23
23 to 25
P70 to
P72
E
General-purpose CMOS I/O ports.
32
10
16
34
10
17
V
V
C
--
--
--
Power supply pin
Power (GND) pin
CC
SS
MB89F202/F202RA:
Capacitance pin for regulating the power supply.
Connect an external ceramic capacitor of about 0.1µF.
MB89202:
This pin is not internally connected. It is unnecessary to connect
a capacitor.
--
16, 22
N.C.
--
Internally connected pins
Be sure to leave it open.
*1 : DIP-32P-M06
*2 : FPT-34P-M03
13
CHAPTER 1 OVERVIEW
1.8
I/O Circuit Types
Table 1.8-1 describes the I/O circuit types.
The letters in the circuit column shown in Table 1.8-1 correspond to the letters in the
circuit type column shown in Table 1.7-1 .
■ I/O Circuit Types
Table 1.8-1 I/O Circuit Types (1/2)
Types
Circuit
Remarks
A
At an oscillation feedback resistance of
approximately 500 kΩ
X1
X0
Standby control signal
B
CMOS output
Hysteresis input
Pull-up resistor optional
P-ch
P-ch
N-ch
Port / Resource
Input enable
C
At an output pull-up resistor (P-ch) of
approximately 50 kΩ/5.0 V
(not available for MB89F202/F202RA)
N-ch open-drain reset output
P-ch with pull-up, not
available for
MB89F202/F202RA
Hysteresis input
High voltage input tolerable in MB90F202RA
N-ch
Reset
14
CHAPTER 1 OVERVIEW
Table 1.8-1 I/O Circuit Types (2/2)
Types
Circuit
Remarks
D
CMOS output
CMOS input
P-ch
Hysteresis input (Resource input)
Pull-up resistor optional
P-ch
N-ch
Port
Input enable
Input enable
Resource
E
CMOS output
CMOS input
Pull-up resistor optional
P70 to P72 are large current drive type
P-ch
P-ch
N-ch
Port
Input enable
F
CMOS output
CMOS input
P-ch
N-ch
Analog input
N-ch open-drain output available
P40 to P43 are large current drive type
Open-drain control
Analog input
Input enable
Port
A/D enable
P-ch
G
CMOS output
CMOS input
Hysteresis input (Resource input)
Analog input
P-ch
N-ch
Input enable
Input enable
Port
Resource
Analog input
A/D enable
H
CMOS input
Port
Input enable
15
CHAPTER 1 OVERVIEW
16
CHAPTER 2 HANDLING DEVICES
2.1
Precautions on Handling Devices
This section describes the precautions to be taken when handling the power supply
voltage, pins, and other device items.
■ Precautions on Handling Devices
● Ensure that the voltage does not exceed the maximum ratings. (Preventing latch-up)
A latch-up may occur if a voltage higher than Vcc or lower than Vss is applied to input or output pins other
than middle- or high-level resistant pins, or if voltage exceeding the rated value is applied between Vcc and
Vss.
When a latch-up occurs, the supply current increases rapidly, occasionally resulting in overheating.
Therefore, ensure that the voltage does not exceed the maximum ratings when using the microcontrollers.
● Stabilize the supply voltage as much as possible
Although the specified Vcc supply voltage operating range is assured, a sudden change in the supply
voltage within the specified range may result in a malfunction.
The following stabilization guidelines are recommended: The Vcc ripple (P-P value) at the supply
frequency (50 Hz to 60 Hz) should be less than 10% of the typical Vcc value, and the transient fluctuation
rate should be less than 0.1 V/ms at the time of momentary fluctuation when switching the power supply.
● Handling unused input pins
Leaving unused input pins open may result in a malfunction or equipment damage due to a latch-up.
Therefore, set these pins to pull-up or pull-down via resistors of 2 kΩor higher.
● Handling the N.C. pins
Ensure that the N.C. (internally connected) pins are opened before using.
● Precautions on using an external clock
When an external clock is used, the oscillation stabilization wait time is also provided for power-on reset
and stop mode release.
● Wild register function
Because wild registers cannot be debugged on MB89V201, check operation on an actual MB89F202/
F202RA.
● Program execution on RAM
When MB89V201 is used, a program cannot be executed on RAM.
18
CHAPTER 2 HANDLING DEVICES
● Note to Noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause
malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external
reset pin (RST).
● External pull-up for the External Reset Pin (RST) of MB89F202/F202RA
Internal pull-up control for RST is not available for MB89F202/F202RA. To ensure proper external reset
control in MB89F202/F202RA, an external pull-up (recommend 100 kΩ) for RST pin must be required.
For MB89F202RA only, high voltage must be applied to RST during flash memory program / erase. The
typical high voltage is 10 V.
● Step-down circuit stabilization time
The MB89202/F202RA series consists of the products listed in Table 2.1-1 "Pin Processing for the
Products with and without a Step-down Circuit". The operation characteristic depends on whether a product
contains a step-down circuit.
Table 2.1-1 Pin Processing for the Products with and without a Step-down Circuit
Product name
Operating voltage
Step-down circuit
Not contained
MB89V201
MB89202
2.7 V to 5.5 V
2.2 V to 5.5 V
3.5 V to 5.5 V
Not contained
Contained
MB89F202/F202RA
These products use the same internal resources. However, the operation sequence after power-on reset
depends on whether a product contains a step-down circuit. Figure 2.1-1 shows the sequence of operations
after the power-on reset for each model.
19
CHAPTER 2 HANDLING DEVICES
Figure 2.1-1 Operation Sequences after Power-on Reset between Product Types
Power supply (VCC
)
Step-down circuit stabilization time (217/FCH) +
Oscillation stabilization wait time (218/FCH
)
CPU operation of
product with a step-down
circuit (MB89F202/F202RA)
Oscillation stabilization
wait time (218/FCH
)
CPU operation of
product without a
step-down circuit
(MB89202 and MB89V201)
Start of CPU operation of
product without a step-down
circuit (reset vector)
Start of the CPU operation of
product with a step-down
circuit (reset vector)
F
CH: Main oscillation frequency
As shown in Figure 2.1-1 , the start of CPU operation of a product with a step-down circuit is slower than
that of the product without a step-down circuit. This is because time is required for the step-down circuit to
stabilize prior to normal operation of the step-down circuit.
20
CHAPTER 3 CPU
3.1
Memory Space
The MB89202/F202RA series has 64-KB memory space that consists of the I/O area,
RAM area, ROM area, and external area. Part of the memory space is applied for specific
use such as general-purpose registers or a vector table.
■ Configuration of Memory Space
● I/O area (address: 0000 to 007F )
H
H
The control registers and data registers for built-in peripheral functions are assigned.
The I/O area is assigned as part of the memory space, thus access to the I/O area can be obtained in the
same manner as access to memory. Also, direct addressing provides high-speed access.
● RAM area
Static RAM is equipped as the internal data area.
The size of internal RAM depends on the model.
Direct addressing allows high-speed access to an area from 80 to FF . (Some models restrict the usable
H
H
range of the area.)
100 to 1FF can be used as the general-purpose register area.
H
H
If a reset occurs while data is being written into RAM, the data being written cannot be guaranteed.
● ROM area
ROM is equipped as the internal program area.
The size of internal ROM depends on the model.
FFC0 to FFFF are usable as a vector table or another feature.
H
H
22
CHAPTER 3 CPU
■ Memory Map
Figure 3.1-1 Memory Map
MB89V201
MB89202
MB89F202/F202RA
0000H
0000H
0000H
I/O
I/O
I/O
0080H
0080H
0080H
RAM 512 bytes
RAM 512 bytes
RAM 512 bytes
0100H
0100H
0100H
0200H
0200H
0200H
0280H
0280H
0280H
Not available
Not available
Not available
8000H
C000H
C000H
FFFFH
External EPROM
32 KB
ROM 16 KB
FFFFH
Flash 16 KB
FFFFH
23
CHAPTER 3 CPU
3.1.1
Specific-purpose Areas
In addition to the I/O area, the general-purpose register area and vector table area are
available as areas for specific applications.
■ General-purpose Register Area (Address: 0100 to 01FF )
H
H
•
•
•
This area is used for 8-bit arithmetic operations and transfer. Supplementary registers are provided.
Since this area is allocated to a part of the RAM area, it can also be used as normal RAM.
When this area is used as a general-purpose register, it can be accessed faster using shorter instructions
by general-purpose register addressing.
For details, see Section "3.2.2 Register Bank Pointer (RP) " and Section "3.3 General-Purpose Registers ".
■ Vector Table Area (Address: FFC0 to FFFF )
H
H
•
•
This area is used as vector tables of the vector call instructions, interrupts, and reset.
This area is allocated to the highest ranges of the ROM area, and the start address of the corresponding
processing routine is set to the address of each vector table.
Table 3.1-1 provides the reference addresses in the vector table that correspond to the vector instructions,
interrupts, and reset.
Table 3.1-1 Vector Table (1/2)
Address in the vector table
Vector call instruction
Upper digits
Lower digits
FFC0
FFC1
CALLV #0
CALLV #1
CALLV #2
CALLV #3
CALLV #4
CALLV #5
CALLV #6
H
H
FFC2
FFC3
H
H
FFC4
FFC5
H
H
FFC6
FFC7
H
H
FFC8
FFC9
H
H
FFCA
FFCB
H
H
FFCC
FFCE
FFCD
FFCF
H
H
H
CALLV #7
IRQF
H
FFDC
FFDE
FFDD
H
H
H
H
H
H
H
H
IRQE
FFDF
IRQD
FFE0
FFE2
FFE1
FFE3
IRQC
24
CHAPTER 3 CPU
Table 3.1-1 Vector Table (2/2)
Address in the vector table
Upper digits Lower digits
Vector call instruction
IRQB
IRQA
IRQ9
FFE4
FFE5
H
H
H
H
H
H
FFE6
FFE8
FFE7
FFE9
IRQ8
FFEA
FFEC
FFEB
FFED
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
IRQ7
IRQ6
FFEE
FFEF
IRQ5
FFF0
FFF2
FFF4
FFF6
FFF8
FFF1
FFF3
FFF5
FFF7
FFF9
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
FFFA
- *
FFFB
H
H
Mode data
Reset vector
FFFD
H
H
FFFE
FFFF
H
*: For MB89202 / MB89V201, FFFC is prohibited. (Use "FF ".)
H
H
For MB89F202/F202RA, write "01 " to FFFC to activate read protection,
H
H
otherwise write "FF ".
H
25
CHAPTER 3 CPU
3.1.2
Location of 16-bit Data on Memory
Upper digits of 16-bit data and stack data are stored in lower addresses on memory.
■ 16-bit Data Storage State on RAM
When 16-bit data is written into RAM, the upper byte of the data is stored with a lower address and the
lower byte of the data is stored with the next address. 16-bit data is read in the same manner.
Figure 3.1-2 shows the location of 16-bit data on RAM.
Figure 3.1-2 Location of 16-bit Data on RAM
After
Before
written
written
Memory
Memory
MOVW 0081H, A
0080H
0081H
0082H
0083H
0080H
0081H
0082H
0083H
12H
1234H
A
A
1234H
34H
■ 16-bit Operand Storage State
When 16 bits are specified for operands in instructions, upper bytes are also stored in addresses close to
operation codes (instructions) and lower bytes are stored in the following addresses.
Operands that indicate memory addresses and 16-bit immediate data are handled in the same manner as
stated above.
Figure 3.1-3 shows the locations of 16-bit data in instructions.
Figure 3.1-3 Location of 16-bit Data in Instructions
[Example] MOV A, 5678H
; Extend address
MOV W A, #1234H
; 16-bit immediate data
Processed through assembler
.
.
.
XXX0H XX XX
; Extend address
; 16-bit immediate data
XXX2H 60
XXX5H E4
XXX8H XX
78
56
12 34
.
.
.
■ 16-bit Data Storage State in Stack
The upper byte of data for a 16-bit register put in the stack due to an interrupt is also stored with a lower
address.
26
CHAPTER 3 CPU
3.2
Dedicated Register
The dedicated register in the CPU consists of a program counter (PC), two arithmetic
operation registers (A and T), three address pointers (IX, EP, and SP), and program
status (PS) register. The size of each register is 16 bits.
■ Dedicated Register Configuration
The dedicated register in the CPU consists of seven 16-bit registers. Some registers allow only the lower 8
bits to be used.
Figure 3.2-1 shows the configuration of the dedicated register.
Figure 3.2-1 Configuration of Dedicated Register
16 bits
PC
Initial value
FFFDH
:
:
:
:
:
:
:
Program counter
Indicates the current instruction stored position.
Undefined
A
T
Accumulator
Temporary register that handles arithmetic operations and
data transfer.
Undefined
Undefined
Undefined
Temporary accumulator
Handles arithmetic operations together with the accumulator.
IX
Index register
Indicates index address.
EP
SP
Extra-pointer
Indicates memory address.
Undefined
Stack pointer
Indicates the current position in the stack.
Flag I = 0
IL1 and IL0 = 11
The other bits are undefined.
RP
CCR
Program status register
Stores the register bank pointer and condition code.
PS
■ Functions of the Dedicated Register
● Program counter (PC)
The size of the program counter is 16 bits. It indicates the memory address at which the CPU is currently
handling an instruction. The program counter is updated with an instruction executed, interrupt, or reset.
The initial value specified after the reset operation is the mode data read address (FFFD ).
H
● Accumulator (A)
The accumulator is a 16-bit arithmetic operation register. It handles arithmetic operations or data transfer
using data on memory or data in another register such as temporary accumulator (T). The accumulator
allows data in it to be used as a word (16 bits) or bytes (8 bits). When arithmetic operations or data transfer
is handled in the unit of a byte, only the lower 8 bits (AL) of the accumulator are used; the upper 8 bits
(AH) remain unchanged. The initial value specified after the reset operation is undefined.
27
CHAPTER 3 CPU
● Temporary Accumulator (T)
The temporary accumulator is an auxiliary 16-bit arithmetic operation register. It handles arithmetic
operations using data in the accumulator (A). When arithmetic operations in the accumulator (A) are
handled in word units (16 bits), data in the temporary accumulator is handled in word units. Otherwise, it is
handled in byte units (8 bits). When arithmetic operations are handled in byte units, only the lower 8 bits
(TL) in the temporary accumulator are used; the upper 8 bits (TH) are not used.
When an MOV instruction is used to transfer data into the accumulator (A), data stored in the accumulator
is automatically transferred to the temporary accumulator before it is transferred. For data transfer in byte
units, the upper 8 bits of the temporary accumulator (TH) does not change. The initial value of the
temporary accumulator specified after the reset operation is undefined.
● Index register (IX)
The index register is a 16-bit register that stores an index address. The index register is used together with a
1-byte offset (-128 to +127). It generates a memory address for accessing data by adding a sign-extended
offset to the index address. The initial value of the index register specified after the reset operation is
undefined.
● Extra-pointer (EP)
The extra-pointer is a 16-bit register. Data in the extra-pointer is handled as the memory address for
accessing data. The initial value of the extra-pointer specified after the reset operation is undefined.
● Stack pointer (SP)
The stack pointer is a 16-bit register that stores an address that is used to call an interrupt or subroutine, or
to which a stack/recovery instruction makes a reference. While a program is being executed, the value of
the stack pointer indicates the address of the latest data put in the stack. The initial value of the stack
pointer specified after the reset operation is undefined.
● Program status (PS) register
The program status is a 16-bit control register. The upper 8 bits of the program status register is the register
bank pointer (RP) used to indicate the address of a general-purpose register bank.
The lower 8 bits are the condition code register (CCR) that composes flags for indicating the CPU status.
Because these 8-bit registers comprise the program status register, they cannot be accessed. (Only
instructions MOVW A, PS and MOVW PS, A access the program status register.)
Note:
2
For details on how to use the dedicated register, see the F MC-8L MB89600 Series Programming
Manual.
28
CHAPTER 3 CPU
3.2.1
Condition Code Register (CCR)
The condition code register (CCR) is the lower 8 bits of the program status register
(PS). The condition code register consists of bits (C, V, Z, N, and H) for indicating the
results of arithmetic operations or data to be transferred and control bits (I, IL1, and IL0)
for controlling the acceptance of interrupt requests.
■ Configuration of the Condition Code Register (CCR)
Figure 3.2-2 Configuration of Condition Code Register
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CCR initial value
PS R4 R3 R2 R1 R0
-
-
-
H
I
IL1 IL0
N
Z
V
C
X011XXXXB
Half carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
X: Undefined
■ Bits for Indicating Arithmetic Operation Results
● Half carry flag (H)
When a carry from bit3 to bit4 or a borrow from bit4 to bit3 occurs as a result of an arithmetic operation,
the half carry flag is set to "1". Otherwise, the half carry flag is cleared with "0". The half carry flag is
intended only for decimal adjustment instructions, and thus should not be used for operations other than
addition or subtraction.
● Negative flag (N)
When the highest bit becomes "1" as a result of an arithmetic operation, the negative flag is set to "1".
When it becomes "0", it is cleared with "0".
● Zero flag (Z)
When the result of an arithmetic operation is "0", the zero flag is set to "1". Otherwise, the zero flag is
cleared with "0".
● Overflow flag (V)
When a complement on 2 overflow occurs as a result of an arithmetic operation, the overflow flag is set to
"1". Otherwise, the overflow flag is cleared with "0".
● Carry flag (C)
When a carry from bit7 or a borrow to bit7 occurs as a result of an arithmetic operation, the carry flag is set
to "1". Otherwise, the carry flag is cleared with "0". The shift instruction causes the value to be shifted out.
29
CHAPTER 3 CPU
Figure 3.2-3 shows how the shift commands change the carry flag.
Figure 3.2-3 Change of the Carrier Flag by the Shift Commands
-
Shift to the left (ROLC)
bit7
-
Shift to the right (RORC)
bit0
bit7
bit0
C
C
Note:
The condition code register is part of the program status register (PS), and thus is not allowed to access
only the condition code register.
It is uncommon to fetch and use only some of the flag bits directly. Normally, branch instructions (such as
BNZ) or decimal adjustment instructions (such as DAA and DAS) use them indirectly. The initial values of
these flags specified after the reset operation are undefined.
■ Bits for Controlling Acceptance of Interrupts
● Interrupt enable flag (I)
When this flag is "1", interrupts are allowed and the CPU accepts interrupts.
When this flag is "0", interrupts are prohibited and the CPU does not accept interrupts.
The initial value of the interrupt enable flag after the reset operation is "0".
Normally, the SETI instruction sets the interrupt enable flag to "1", and the CLRI instruction sets it to "0"
to clear.
● Interrupt level bits (IL1 and IL0)
These bits indicate the level of an interrupt the CPU is accepting, then it is compared with the values in the
interrupt level setting registers (ILR1 to 4) which is specified as the level of interrupt requests of peripheral
functions (IRQ0 to IRQF).
When the interrupt enable flag is turned on (I = 1), and if an interrupt is requested with an interrupt level
value lower than that of these bits, the CPU accepts the interrupt. Table 3.2-1 provides interrupt level
intensities. The initial value of the interrupt level specified after the reset operation is 11 .
B
Table 3.2-1 Interrupt Levels
IL1
IL0
Interrupt level
Intensity
0
0
1
1
0
1
0
1
High
1
2
3
Low (no interrupts allowed)
Note:
When the CPU is not handling an interrupt (handling the main program), the interrupt level bits (IL1
and IL0) are normally set to 11 .
B
30
CHAPTER 3 CPU
3.2.2
Register Bank Pointer (RP)
The register bank pointer (RP) is the upper 8 bits of the program status register (PS).
The register bank pointer indicates the general-purpose register bank address being
used, and the address is converted to the actual address in general-purpose register
addressing.
■ Configuration of the Register Bank Pointer (RP)
Figure 3.2-4 shows the configuration of the register bank pointer.
Figure 3.2-4 Configuration of Register Bank Pointer
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10
bit6 bit5
IL1
bit4
IL0
bit3 bit2
bit1
V
bit0
C
RP initial value
XXXXXXXXB
bit9
-
bit8
-
bit7
H
-
PS
R4
R3
R2
R1
R0
I
N
Z
X: Undefined
The register bank pointer indicates the address of the register bank being used. Figure 3.2-5 shows the rule
of conversion from the register bank pointer bits to the actual address.
Figure 3.2-5 Rule of Conversion from the RP Bits to the Actual Address
RP upper bits
R3 R2 R1
Lower bits of operation code
R4
R0
b2
b1
b0
"0"
"0"
"0"
"0"
"0"
"0"
"1"
A8
"0"
A9
Address
A15 A14 A13 A12 A11 A10
A7
A6
A5
A4
A3
A2
A1
A0
generated
The register bank pointer specifies a memory block (register bank) used as a general-purpose register in the
RAM area. There are 32 register banks. Setting a value (from 0 to 31) in the upper five bits of the register
bank pointer specifies a register bank. One register bank contains eight 8-bit general-purpose registers that
are selected with the lower 3 bits of an operation code.
The register bank pointer allows a range of 0100 to 01FF (maximum) to be used as the general-purpose
H
H
register area. However, some models restrict the usable range when only internal RAM is used. The initial
value of the register bank pointer specified after the reset operation is undefined.
Note:
Be sure to set up the register bank pointer (RP) before using general-purpose registers.
The register bank pointer is part of the program status register (PS), and thus is not allowed to access
only the register bank pointer.
31
CHAPTER 3 CPU
3.3
General-Purpose Registers
The general-purpose registers are memory blocks. Eight 8-bits comprise a bank.
The register bank pointer (RP) specifies a register bank.
Although up to 32 banks can be used, some banks can be expanded onto external RAM
if the capacity of internal RAM is not sufficient for all 32 banks.
The general-purpose registers are effective for processing interrupts, vector calls, or
subroutine calls.
■ Configuration of the General-purpose Registers
•
•
•
Each general-purpose register consists of 8 bits. The general-purpose registers are placed in the register
banks at the general-purpose register area (on RAM).
One bank contains eight registers (R0 to R7), and up to 32 banks can be used. However, some models
restrict the number of usable banks when only internal RAM is used.
The register bank pointer (RP) specifies the register bank being used. The lower three bits of an
operation code indicate general-purpose register 0 (R0) to general-purpose register 7 (R7).
Figure 3.3-1 shows the configuration of the register banks.
Figure 3.3-1 Configuration of Register Bank
100H*
R0
R1
R2
R3
R4
R5
R6
R7
000
001
010
011
100
101
110
111
Bank 0
(RP=00000---B
)
108H*
R0
R1
000
001
32 banks (on the RAM area)
Bank 1
(RP=00001---B
The number of usable banks
is dependent on the size
of the usable RAM area.
.
.
.
.
)
R7
111
.
.
.
.
.
.
.
.
.
.
Bank 2
to
Bank 30
1F8H*
R0
000
.
.
Ban 31
(RP=11111---B
.
.
)
R7
111
1FFH*
*: Address at the top of the register banks = 0100H + 8 × (upper 5 bits of RP)
For details on the general-purpose register area on each model, see Section "3.1.1 Specific-purpose Areas ".
32
CHAPTER 3 CPU
■ Features of the General-purpose Registers
The general-purpose registers have the following features:
•
•
High-speed access with short instructions (general-purpose register addressing)
Register banks (in blocks) that allow data to be easily conserved and partitioned in the unit of function
The general-purpose registers allow specific register banks to be statically assigned with the interrupt
processing routine or vector call (CALLV #0 to #7) processing routine. For example, it can be used such
that the fourth register bank is always used for the second interrupt.
For interrupts, unless data in a specific register bank that corresponds to an interrupt processing is
incorrectly overwritten by another routine, simply specifying the specific register bank at the beginning of
the interrupt processing routine stores the data contained in the general-purpose registers before
interruption. This feature allows data in general-purpose registers to avoid being put in the stack and allows
interrupts to be handled efficiently at high speed.
For subroutine calls, in addition to conservation of data in general-purpose registers, the register banks can
implement re-entrant programs (reloadable programs with variable addresses unfixed) that are usually
created using the index register (IX) or another function.
Note:
A program must be created so that the values of the interrupt level bits in the condition code register
(CCR: IL1 and IL0) do not change when the register bank pointer (RP) is rewritten to specify a register
bank in the interrupt processing routine.
33
CHAPTER 3 CPU
3.4
Interrupts
The MB89202/F202RA series supports 12 interrupt request inputs corresponding to
peripheral functions and allows an interrupt level to be assigned to each of the inputs.
The interrupt controller compares levels of interrupts generated by peripheral functions
when output of interrupt requests is allowed for peripheral functions. The CPU performs
the interrupt operation according to its interrupt acceptance settings. The CPU cancels
standby mode on reception of an interrupt request, then returns to the interrupt
operation or normal operation.
■ Interrupt Requests from Peripheral Functions
Table 3.4-1 lists the interrupt requests that correspond to peripheral functions. When the CPU accepts an
interrupt, the CPU takes a branch to the interrupt processing routine using the address in the interrupt
vector table corresponding to the interrupt request as the branch address.
The interrupt level setting registers (ILR1, 2, 3, and 4) allow one of four interrupt processing intensities to
be assigned to each interrupt request.
Interrupt requests with levels equal to or less than that of an interrupt request being handled in the interrupt
processing routine are usually handled after the current interrupt processing routine ends. If interrupt
requests with the same assigned level are generated simultaneously, IRQ0 has priority.
Table 3.4-1 Interrupt Requests and Interrupt Vectors (1/2)
Address in the
Names of bits in Priority at
vector table
the interrupt
level setting
registers
identical level (at
simultaneous
occurrence)
Interrupt request
Upper
digits
Lower
digits
IRQ0 (External interrupt INT10)
IRQ1 (External interrupt INT11)
IRQ2 (External interrupt INT12)
IRQ3 (8/16-bit capture timer/counter’s timer)
IRQ4 (8/16-bit capture timer/counter’s capture)
IRQ5 (Transmission with UART)
IRQ6 (Reception with UART)
IRQ7 (Time-base timer)
FFFA
FFFB
L01, L00
L11, L10
L21, L20
L31, L30
L41, L40
L51, L50
L61, L60
L71, L70
L81, L80
L91, L90
LA1, LA0
H
H
High
FFF8
FFF9
H
H
FFF6
FFF7
H
H
FFF4
FFF5
H
H
FFF2
FFF3
H
H
FFF0
FFF1
H
H
FFEE
FFEF
H
H
FFEC
FFED
H
H
IRQ8 (A/D converter)
FFEA
FFEB
H
H
H
H
H
H
IRQ9 (8-bit PWM)
FFE8
FFE6
FFE9
FFE7
Low
IRQA (External interrupt 2)
34
CHAPTER 3 CPU
Table 3.4-1 Interrupt Requests and Interrupt Vectors (2/2)
Address in the
vector table
Names of bits in Priority at
the interrupt
level setting
registers
identical level (at
simultaneous
occurrence)
Interrupt request
Upper
digits
Lower
digits
IRQB (Flash interface)
FFE4
FFE2
FFE0
FFE5
FFE3
FFE1
LB1, LB0
LC1, LC0
LD1, LD0
LE1, LE0
LF1, LF0
H
H
H
H
H
H
High
Low
IRQC (8-bit serial I/O)
IRQD (Unused)
IRQE (Unused)
FFDE
FFDF
H
H
H
IRQF (Unused)
FFDC
FFDD
H
35
CHAPTER 3 CPU
3.4.1
Interrupt Level Setting Registers (ILR1 to ILR4)
For the interrupt level setting registers (ILR1, 2, 3, and 4), 16 two-bit data items
corresponding to interrupt requests sent from peripheral functions are assigned.
Interrupt levels can be specified in these 2-bits (interrupt level setting bits).
■ Configuration of the Interrupt Level Setting Registers (ILR1 to ILR4)
Figure 3.4-1 Configuration of Interrupt Level Setting Register
Register Address
bit7
L31
(W)
bit6
L30
bit5
L21
(W)
bit4
L20
bit3
L11
(W)
bit2
L10
(W)
bit1
L01
(W)
bit0
L00
(W)
(Initial value)
1111 1111B
ILR1
ILR2
007BH
007CH
(W)
(W)
L71
(W)
L70
(W)
L61
(W)
L60
(W)
L51
(W)
L50
(W)
L41
(W)
L40
(W)
1111 1111B
ILR3
ILR4
007DH
007EH
LB1
(W)
LB0
(W)
LA1
(W)
LA0
(W)
L91
(W)
L90
L81
L80
(W)
1111 1111B
1111 1111B
(W) (W)
LF1
(W)
LF0
(W)
LE1
(W)
LE0
(W)
LD1
(W)
LD0
(W)
LC1
(W)
LC0
(W)
W: Write only
For each interrupt request, 2 bits of the interrupt level setting registers are assigned. The values specified in
the interrupt level setting registers are the intensities for processing the interrupts (interrupt levels 1 to 3).
Interrupt level setting bits are compared with interrupt level bits in the condition code register (CCR: IL1
and IL0).
When interrupt level 3 is specified, the CPU does not accept interrupt requests.
Table 3.4-2 provides the relationship between interrupt level setting bits and interrupt levels.
Table 3.4-2 Relationship between Interrupt Level Setting Bits and Interrupt Levels
L01 to LF1
L00 to LF0
Requested interrupt level
Priority
0
0
1
1
0
1
0
1
High
1
2
3
Low (no interrupt)
Notes:
•
When the main program is being executed, the interrupt level bits in the condition code register
(CCR: IL1 and IL0) are normally set to 11 .
B
•
The ILR1 to ILR4 registers are write-only enabled, and thus the bit manipulation instructions (SETB
and CLRB) cannot be used.
36
CHAPTER 3 CPU
3.4.2
Steps in the Interrupt Operation
When an interrupt request is generated in a peripheral function, the interrupt controller
notifies the CPU of its interrupt level. If the CPU can accept an interrupt, the CPU
temporarily stops the program that is handling and starts the interrupt processing
routine.
■ Steps in the Interrupt Operation
The steps for processing an interrupt are: occurrence of a source of an interrupt in a peripheral function,
designation of the interrupt request flag bit (request F/F), check on the interrupt request enable bit (enable
F/F), check on the interrupt level (ILR1, 2, 3, or 4, and CCR: IL1 and IL0), check on another request with
the same level, and check on the interrupt enable flag (CCR: I).
Figure 3.4-2 shows the steps in the interrupt operation.
Figure 3.4-2 Steps in the Interrupt Operation
Main
Interrupt
processing
routine
program
PS
I
IL
Update of IL
Operation
Unit
Cancellation
of a reset
PC and
Com-
Request
cleared
Check
PS saved
parator
MB89202 CPU
Level
Interrupt
Initial setting
for interrupt
check
processing
RAM
PC and PS
restored
.
.
.
Execution
of main
Interrupt
controller
Enable
Occur-
program
RETI
rence of
interrupt
F/F
AND
Source
F/F
PC and PS
restored
Peripheral
➀ After a reset, all interrupt requests are prohibited.
Initialize the peripheral functions that generate interrupts using a initialization program for peripheral
functions, specify interrupt levels in the interrupt level setting registers (ILR1 to ILR4) concerned, then
start up the peripheral functions.
Interrupt levels 1, 2, and 3 can be specified. Level 1 is the highest level, and level 2 is the second
highest level. Level 3 prohibits interrupts from the peripheral functions to which it is assigned.
➁ Run the main program. (For a multiple-interrupt, run the interrupt processing routine.)
➂ When a peripheral function generates a source of an interrupt, the interrupt request flag bit for
peripheral function (request F/F) is set to "1". If the interrupt request enable bit for a peripheral function
is turned on (enable F/F = 1) at that time, an interrupt request is output to the interrupt controller.
37
CHAPTER 3 CPU
➃ The interrupt controller is always monitoring interrupt requests from peripheral functions. The interrupt
controller notifies the CPU of the highest interrupt level interrupt among levels corresponding to
interrupt requests currently generated. If different requests are made with the same interrupt level, the
interrupt controller also determines their priorities.
➄ The CPU checks the value in the interrupt enable flag (CCR: I) when the priority of the interrupt level
that is received is higher (the level value is lower) than the level specified in the interrupt level bits in
the condition code register (CCR: IL1 and IL0). The CPU then accepts the interrupt when the enable
flag is turned on (CCR: I = 1).
➅ Put the values in the program counter (PC) and program status (PS) in the stack, fetch the start address
of the interrupt processing routine from the interrupt vector table concerned, change the value of the
interrupt level bits in the condition code register (CCR: IL1 and IL0) to the value of the interrupt level
accepted, and then start the interrupt processing routine.
➆ Finally, restore the values of the program counter (PC) and program status (PS) put into the stack with
the RETI instruction, then execute an instruction following the instruction executed immediately before
the interruption.
Standby mode (low-power consumption mode) is cancelled by an interrupt. For details, see Section "3.7
Notes:
• An interrupt request flag bit for a peripheral function is not automatically cleared even if the
interrupt request is accepted. Therefore, it is necessary to clear the bit using a program in the
interrupt processing routine (by writing "0" into the interrupt request flag bit normally).
• Clearing an interrupt request flag bit at the beginning of the interrupt processing routine allows the
peripheral function that generated the interrupt to re-generate an interrupt (set an interrupt request
flag bit again) while the interrupt processing routine is being executed. However, the re-generated
interrupt is normally accepted after the interrupt processing routine ends its current cycle.
38
CHAPTER 3 CPU
3.4.3
Multiple Interrupts
Multiple interrupts are allowed by setting different levels into the interrupt level setting
registers (ILR1 to ILR4) for multiple interrupt requests from peripheral functions.
■ Multiple Interrupts
When an interrupt request with a higher interrupt level is generated while the interrupt processing routine is
operating, the current interrupt processing cycle is stopped to accept the higher-level interrupt request.
Interrupt levels 1, 2, and 3 can be specified. Level 3 prohibits the CPU from accepting interrupts.
● Example of multiple interrupts
As an example of multiple-interrupt processing, suppose a case in which a timer interrupt has precedence
using the A/D interrupt, and the A/D interrupt level is set to level 2 and the timer interrupt level is set to
level 1. Figure 3.4-3 shows the sequence performed when an external interrupt is generated while an A/D
interrupt is being processed.
Figure 3.4-3 Example of Multiple Interrupts
Timer interrupt
processing
A/D interrupt
processing
Main program
Interrupt
level 1
Initializes
peripherals
Interrupt
level 2
Timer interrupt
Timer interrupt
processed
generated
Stop
process-
ing
A/D interrupt
generated
Resumes
processing
Return from
timer interrupt
processing
A/D interrupt
processed
Main
program
restarts
Return from A/D
interrupt processing
•
•
In the A/D interrupt processing, the interrupt level bits in the condition code register (CCR: IL1 and
IL0) are set to the same value as the value in the interrupt level setting register corresponding to the A/
D interrupt (ILR1, 2, 3, or 4) (i.e., 2 in this example). If an interrupt request with a higher interrupt level
specified is generated (1 in this example), processing for the higher interrupt level is effected first.
To temporarily prohibit multiple interrupts in the A/D interrupt processing, turn off the interrupt enable
flag (CCR: I = 0) in the condition code register, or set 00 to the interrupt level bits (IL1 and IL0).
B
•
•
Executing the return instruction (RETI) after interrupt processing restores the values of the program
counter (PC) and program status (PS) and ensures resumption of the interrupted program.
The value in the condition code register (CCR) is returned to the value used before interruption when
the program status (PS) value is restored.
39
CHAPTER 3 CPU
3.4.4
Interrupt Processing Time
From when an interrupt request is generated to when control is transferred to the
interrupt processing routine, both the time to quit the instruction being executed and
the time to manage the interrupt (required to prepare interrupt processing) are required.
The total time must be within 30 instruction cycles.
■ Interrupt Processing Time
From when an interrupt request is generated and accepted to when the interrupt processing routine starts,
sufficient time is required to wait for an interrupt request sample and to manage the interrupt.
● Interrupt request sample wait time
Generation of an interrupt request is checked by sampling an interrupt request at the last cycle of each
instruction. Therefore, the CPU cannot identify an interrupt request while it is executing an instruction. The
wait time becomes maximum when an interrupt request is generated immediately after the CPU executes
the DIVU instruction (21 instruction cycles) with the longest instruction cycle.
● Interrupt handling time
After accepting an interrupt, the CPU needs 9 instruction cycles for interrupt processing preparation to:
•
•
•
Save the values in the program counter (PC) and program status (PS)
Set the address at the beginning of the interrupt processing routine (interrupt vector) into the PC
Update the interrupt level bits (PS: CCR: IL1 and IL0) in the program status (PS).
Figure 3.4-4 shows the interrupt processing time.
Figure 3.4-4 Interrupt Processing Time
Execution of
general instruction
Interrupt processing
routine
Interrupt handling
CPU performs
Interrupt wait
time
Interrupt handling time
(9 instruction cycles)
Interrupt request
sample wait time
Interrupt request is generated
: Last instruction in which an interrupt is sampled
When an interrupt request is generated immediately after the DIVU instruction having the longest
instruction cycle (21 instruction cycles), 30 instruction cycles (21 instructions + 9 instructions) are required
for the interrupt processing time. However, if the DIVU instruction and MULU instruction are not used in
the program, a maximum of 15 (6 instructions + 9 instructions) instructions are required for the instruction
processing time.
An instruction cycle is changed by clock speed switching (gears). For details, see Section "3.6 Clock ".
40
CHAPTER 3 CPU
3.4.5
Stack Operation at Interrupt Processing
This section describes how values in registers are saved and restored at interrupt
processing.
■ Stack Operation at the Beginning of Interrupt Processing
After accepting an interrupt, the CPU automatically saves the values in the program counter (PC) and
program status (PS) in the stack.
Figure 3.4-5 shows the stack operation at the beginning of interrupt processing.
Figure 3.4-5 Stack Operation at the Beginning of Interrupt Processing
Immediately before
interruption
Immediately after
interruption
Address
Memory
Memory
08H
Address
027CH
SP
027CH
027CH
027DH
027EH
027FH
0280H
0281H
XXH
XXH
XXH
XXH
XXH
XXH
PS
0870H
PS
PC
027DH 70H
027EH
027FH
0280H
0281H
E0H
00H
XXH
XXH
PS 0870H
PC E000H
SP
PC
0280H
E000H
■ Stack Operation at the End of Interrupt Processing
When the return instruction (RETI) is executed at the end of interrupt processing, the values in the program
status (PS) and the program counter (PC) are restored from the stack in that order (which is opposite to that
at the beginning of interrupt processing). This operation restores the values in the PS and PC to those
values used before interruption.
Note:
Values in the accumulator (A) and temporary accumulator (T) are not automatically saved in the stack.
Therefore, save and restore the values using the PUSHW and POPW instructions.
41
CHAPTER 3 CPU
3.4.6
Stack Area for Interrupt Processing
A stack area on RAM is used for interrupt processing. The value in the stack pointer
(SP) is used as the start address of the stack area.
■ Stack Area for Interrupt Processing
The stack area is used to save/restore the value in the program counter (PC) when executing the subroutine
call instruction (CALL) or vector call instruction (CALLV) or temporarily save and restore values in
registers or other storage with the PUSHW and POPW instruction.
•
•
Locate the stack area on RAM together with the data area.
It is recommended that the initial settings be specified such that the stack pointer (SP) indicates the
highest address of RAM and that the data area be set up from the lowest address of RAM.
Figure 3.4-6 is an example showing the stack area.
Figure 3.4-6 Stack Area for Interrupt Processing
0000H
0080H
I/O
Data area
RAM
General-
purpose
register
Stack
area
Value recommended for SP
(When the highest RAM address
is 027FH)
0280H
Access
prohibited
ROM
FFFFH
Note:
For the stack area, interrupts, subroutine calls, or PUSHW instruction use addresses in descending
order, and the return instructions (RETI and RET) or the POPW instruction releases addresses in the
stack area in ascending order. When a lower address is used in the stack area due to multiple interrupts
or subroutine calls, make arrangements so that the stack area does not overlap with the data area and
general-purpose register area containing other data.
42
CHAPTER 3 CPU
3.5
Reset
There are four sources of reset:
• External reset
• Software reset
• Watchdog reset
• Power-on reset
Oscillation stabilization wait time is not applied in some operating modes when a reset
occurs or in some option settings.
■ Reset Sources
Table 3.5-1 Reset Sources
Reset source
Reset condition
The external reset pin is "L" level.
External reset
"0" is written into the software reset bit in the standby control register (STBC:
RST).
Software reset
Watchdog reset
Power-on reset
The watchdog timer overflows.
Power is turned on.
● External reset
External reset occurs when "L" level is input to the external reset pin (RST). When the reset pin becomes
"H" level, the external reset is cancelled.
For external reset when power is turned on or in stop mode, the reset operation is performed after
oscillation stabilization wait time is up or the external reset is cancelled.
The external reset pin functions as the reset output pin in accordance with option settings.
● Software reset
Software reset generates a 4-instruction cycle reset by writing "0" into the software reset bit in the standby
control register (STBC: RST). Software reset does not wait until oscillation stabilization wait time has
expired.
● Watchdog reset
Watchdog reset generates a 4-instruction cycle reset when no data is written into the watchdog control
register (WDTC) within a specified time after the watchdog timer is activated. Watchdog reset does not
wait until oscillation stabilization wait time is up.
43
CHAPTER 3 CPU
● Power-on reset
Power-on reset occurs when power is turned on. Power-on reset occurs after oscillation stabilization wait
time has expired.
Power-on reset requires an external reset circuit.
■ Reset Sources and Oscillation Stabilization Wait Time
Operations in oscillation stabilization wait time depend on the operating mode used when a reset occurs.
After a reset, active mode is set regardless of the operating mode applied before the reset (standby mode)
and reset source. Therefore, if a reset occurs while oscillation is being stopped or within the oscillation
stabilization wait time, the oscillation stabilization wait reset mode is set.
Software reset and watchdog reset do not apply oscillation stabilization wait time.
Table 3.5-2 shows the relationship between reset sources, oscillation stabilization wait time, and the reset
operation (mode fetch).
Table 3.5-2 Relationship between the Reset Sources and Oscillation Stabilization Wait Time
Reset source
Operating mode
Reset operation and oscillation stabilization wait time
When power is
turned on or stop
mode
The reset operation is performed when external reset is cancelled after
oscillation stabilization wait time has expired.
*
External reset
Software reset and
watchdog reset
The reset operation is performed following the generation of a 4-
instruction cycle reset.
Active mode
When power is
turned on
The reset operation is performed after power is turned on and
oscillation stabilization wait time has expired.
Power-on reset
* External reset in active mode does not apply oscillation stabilization wait time. The reset operation is performed after
cancellation of external reset.
44
CHAPTER 3 CPU
3.5.1
Reset Flag Register (RSFR)
The reset flag register (RSFR) allows confirmation of the source for a generated reset.
■ Configuration of the Reset Flag Register (RSFR)
Figure 3.5-1 Configuration of Reset Flag Register (RSFR)
Address
000EH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
XXXX----B
PONR
WDOG
ERST
R
SFTR
R
R
R
Software reset flag bit
SFTR
When written
When read
0
1
Does not affect
operations
The source is software reset.
Watchdog reset flag bit
WDOG
When read
When written
0
1
Does not affect
operations
The source is watchdog reset.
External reset flag bit
ERST
When written
When read
0
1
Does not affect
operations
The source is external reset.
Power-on reset flag bit
PONR
When read
When written
0
1
Does not affect
operations
The source is power-on reset.
R : Read only
: Unused
X : Undefined
45
CHAPTER 3 CPU
Table 3.5-3 Explanation of Functions of Each Bit in the Reset Flag Register (RSFR)
Bit name
Description
"1" is set to this bit when power-on reset occurs.
"1" is set to this bit after power is turned on.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
PONR:
Power-on reset flag
bit
bit7
bit6
"1" is set to this bit when external reset occurs.
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the external reset flag is set.
This bit is cleared with "0" after being read.
ERST:
External reset flag bit
Writing a value to this bit has no significance.
"1" is set to this bit when watchdog reset occurs.
WDOG:
Watchdog reset flag
bit
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the watchdog reset flag is set.
This bit is cleared with "0" after being read.
bit5
bit4
Writing a value to this bit has no significance.
"1" is set to this bit when software reset occurs.
SFTR:
Software reset flag
bit
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the software reset flag is set.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
bit3
to
bit0
The values read out are undefined.
Writing data to these bits does not affect operations.
Unused bits
Note:
A reset source flag is set when a reset source is generated. When the reset source flag register is read, all
bits in the reset source flag register are cleared. Therefore, to determine the source of a reset, read this
register using the initial value setting routine after the reset.
46
CHAPTER 3 CPU
3.5.2
External Reset Pin
The external reset pin generates a reset by "L" level input. When an option setting for
enabling reset output is selected, the "L" level signal is output depending on the
internal reset source.
■ Block Diagram of External Reset Pin
The external reset pin (RST) on models with supported reset output has hysteresis input and pull-up N-ch
open drain output.
The external reset pin on models without supported reset output is used only as the pin dedicated to reset
input.
Figure 3.5-2 is a block diagram of the external reset pin.
Figure 3.5-2 Block Diagram of External Reset Pin
Pull-up resistor
Approx. 50kΩ for 5 V
(Not available for
MB89F202)
P-ch
Pin
Internal reset source
Internal reset signal
RST
N-ch
■ Function of the External Reset Pin
The external reset pin (RST) generates an internal reset signal by making use of "L" level input.
The RST outputs the "L" level signal according to the internal reset source and oscillation stabilization wait
time applied following a reset. The internal reset source may be software reset, watchdog reset, or power-
on reset.
Note:
External reset input is accepted asynchronously regardless of the internal clock.
Initialization of the internal circuits requires a clock. In particular, for operations with an external clock,
the clock must be input when a reset signal is input.
Internal pull-up control for RST is not available for MB89F202/F202RA. To ensure proper external
reset control in MB89F202/F202RA, an external pull-up (recommend 100 kΩ) for RST pin must be
required.
47
CHAPTER 3 CPU
3.5.3
Reset Operation
The CPU reads the mode data (mode fetch) and reset vector from internal ROM
according to the mode pin settings following the cancellation of a reset. For a return
triggered by a reset when power is turned on and in stop mode, the CPU fetches the
mode after oscillation stabilization wait time has expired. When a reset occurs, the
contents in RAM cannot be guaranteed.
■ Overview of the Reset Operation
Figure 3.5-3 Reset Operation Flow
Software reset
Watchdog reset
Power-on reset
External reset input
Power-on
reset selected?
YES
Being reset
NO
When power
is turned on or in stop
mode?
YES
State of reset wait-
ing for stabilization
of oscillation
State of reset wait-
ing for stabilization
of oscillation
State of reset wait-
ing for stabilization
of oscillation
External reset
state cancelled?
NO
YES
Mode fetch
(reset operation)
Mode data fetch
Reset vector fetch
Normal operation
(RUN mode)
Instruction code fetched from the address that
indicates the reset vector; the instruction is then
executed.
48
CHAPTER 3 CPU
■ Mode Fetch
The CPU reads the mode data and reset vector from internal ROM following the cancellation of the reset.
● Mode data (address: FFFD )
H
Set single-chip mode (00 ) to the mode data.
H
● Reset vector (address: FFFE (highest)/FFFF (lowest))
H
H
Specify the address at which execution is to be started after the reset operation is completed. The CPU
starts executing instructions from the specified address.
■ State of Reset Waiting for Stabilization of Oscillation
The CPU performs a reset operation for a reset when power is turned on or an external reset in stop mode
when the oscillation stabilization wait time specified with option settings has expired. In this case, if the
external reset input is not cancelled, the CPU performs the reset operation following cancellation of the
external reset.
When an external clock is used, oscillation stabilization wait time is applied, and thus input of an external
clock is required at a reset.
The time-base timer generates oscillation stabilization wait time.
■ Influence from a Reset of Contents in RAM
When reset conditions occur, the CPU stops handling the current instruction, then enters the reset state. The
contents in RAM does not change even after a reset. However, if a reset occurs while 16-bit data is being
written, the upper byte (only) is written; the lower byte may be unwritten. If a reset occurs immediately
after, immediately before, or while data is written, the contents in the address to which data is written at
that time is not guaranteed.
49
CHAPTER 3 CPU
3.5.4
State of Each Pin at Reset
The state of each pin is initialized by a reset.
■ States of Pins during Reset
When a reset occurs, most I/O pins (resource pins) become Hi-Z, and the CPU reads the mode data from
internal ROM.
■ States of Pins after the CPU Reads the Mode Data
Most of the I/O pins remain Hi-Z immediately after the CPU reads the mode data.
For pin states established by something other than a reset, see "APPENDIX E Pin State of the MB89202/
F202RA Series " for details.
Note:
For pins that are Hi-Z when a reset source is generated, set up the devices connected with the pins such
that they do not malfunction.
50
CHAPTER 3 CPU
3.6
Clock
The clock generator includes the oscillation circuit. A high-speed clock is generated by
connecting an external resonator for oscillation frequency. Alternatively, when the
clock is supplied from an external source, a clock signal can be connected to the clock
input pin.
The clock controller manages the speed and supply of the clock in active mode and
standby mode.
■ Clock Supply Map
The clock controller manages oscillation of the clock and provision of the clock to the CPU and peripheral
circuits (peripheral functions). Thus, the operating clock for the CPU or peripheral circuits is affected by
clock speed switching (gears) and setting in standby mode (sleep/stop).
To peripheral functions, a divided frequency output of the free-run counter operating with the clock for
peripheral circuits is provided.
However, the divided frequency output of the time-base timer operating with 1/2 frequency of the
oscillation frequency is not affected by the gear.
Figure 3.6-1 shows the clock supply map.
51
CHAPTER 3 CPU
Figure 3.6-1 Clock Supply Map
(*1)
(*2)
Watchdog timer
FCH
(*3)
Time-base timer
X0 pin
X1 pin
7
8/16-bit capture
timer/counter
EC pin
T0 pin
Oscillation
circuit
1/2
frequency
(*2)
3
Stop mode
8-bit PWM timer
(*4)
PWM pin
AN pin
Clock controller
Gears
8
Continuous
1/4 frequency
1/8 frequency
1/16 frequency
1/64 frequency
conversion
A/D converter
Continuous
Oscillation
control
conversion
Conversion/
comparison
(*2)
UART
prescaler
UART
UCK/SCK pin
Sleep, stop, oscillation
stabilization wait
U0/S0 pin
(*2)
Supplied to
CPU
3
UI/SI pin
8-bit serial I/O
(*1)
4
4
1tINST
Stop
BZ pin
PPG pin
INT1 pin
INT2 pin
Buzzer
Supplied to
peripheral circuits
(*2)
(*2)
12-bit PPG
1tINST
3
8
(*2)
External interrupt 1
(*2)
Free-run counter
External interrupt 2
(*1)
Oscillation
stabilization
wait time
FCH
tINST
: Oscillation frequency
: Instruction cycle
: Not affected by the gear.
: The gear affects the operating speed or other settings.
: The time-base timer stops when the oscillation frequency clock halts.
*1
*2
*3
: Output of the time-base timer is selectable when the A/D converter is activated continuously.
Other operations are affected by the gear.
*4
52
CHAPTER 3 CPU
3.6.1
Clock Generator
The clock generator enables oscillation in active mode and disables oscillation in stop
mode.
■ Clock Generator
● For a crystal resonator or ceramic resonator
Figure 3.6-2 Example of Connecting a Crystal Resonator or Ceramic Resonator
MB89202/F202RA series
Oscillation circuit
X0
X1
● For an external clock
Figure 3.6-3 Example of Connecting an External Clock
MB89202/F202RA series
Oscillation circuit
X0
X1
Open
53
CHAPTER 3 CPU
3.6.2
Clock Controller
The clock controller consists of the following six blocks:
• Oscillation circuit
• System clock selector
• Clock controller
• Oscillation stabilization wait time selector
• System clock control register (SYCC)
• Standby control register (STBC)
■ Block Diagram of Clock Controller
Figure 3.6-4 is a block diagram of the clock controller.
Figure 3.6-4 Block Diagram of Clock Controller
Standby control register (STBC)
SLP SPL RST
STP
Pin control
Stop
Sleep
Clock for time-base
1/2 frequency
timer
System clock selector
Supplied to the CPU
Pre-scaler
Clock
control
circuit
1/4 frequency
Clock
generator
Selector
1/8 frequency
1/16 frequency
1/64 frequency
1tINST
Supplied to peripheral
circuits
1tINST
214/F
CH
Oscillation
stabilization
wait time
selector
From the
time-base
timer
217/F
CH
218/F
CH
SCM
WT0
CS1 CS0
WT1
System clock control register (SYCC)
FCH
: Oscillation frequency
: Instruction cycle
tINST
54
CHAPTER 3 CPU
● Oscillator
Oscillation circuit that halts oscillation in stop mode.
● System clock selector
Selects one of four frequency-divided source clocks to be supplied to the clock control circuit.
● Clock controller
Controls the operating clock supplied to the CPU and peripheral circuits according to the active (RUN)
mode and standby mode (sleep, stop).
It also stops supply of the clock to the CPU until the clock supply stop signal for the oscillation
stabilization wait time selector is cancelled.
● Oscillation stabilization wait time selector
Selects one of three oscillation stabilization wait time periods generated by the time-base timer according to
the standby mode or a reset, then outputs the clock supply stop signal to the CPU by using the selected time
period.
● System clock control register (SYCC)
Selects the clock speed and oscillation stabilization wait time setting, then checks the clock state.
● Standby control register (STBC)
Controls transition from active (RUN) mode to standby mode, pin state settings at stop mode, and software
reset.
55
CHAPTER 3 CPU
3.6.3
System Clock Control Register (SYCC)
The system clock control register (SYCC) manages clock settings such as selection of
the clock speed and oscillation stabilization wait time.
■ Configuration of the System Clock Control Register (SYCC)
Figure 3.6-5 Configuration of System Clock Control Register (SYCC)
Address
bit7
bit6 bit5
bit4 bit3 bit2 bit1
WT0 CS1
bit0
CS0 1--MM-00B
Initial value
0007H
SCM
R
WT1
R/W R/W
R/W R/W
Clock speed selection bits
CS1 CS0
Instruction cycle (when FCH is 12.5 MHz)
0
0
1
1
0
1
0
1
64/FCH (5.12 µs)
16/FCH (1.28 µs)
8/FCH (0.64 µs)
4/FCH (0.32 µs)
Oscillation stabilization wait time selection bits
Oscillation stabilization wait time according to
WT1 WT0
output of the time-base timer (when FCH is 12.5 MHz)
0
0
1
1
0
1
0
1
Setting prohibited
Approx. 214/FCH (approx. 1.31 ms)
Approx. 217/FCH (approx. 10.5 ms)
Approx. 218/FCH (approx. 21.0 ms)
System clock monitor bit
SCM
Clock stopping or waiting for stabilization of oscillation
0
1
Active mode
R/W : Readable/Writable
R
: Read only
: Unused
: Mask option
: Initial value
M
56
CHAPTER 3 CPU
Table 3.6-1 Explanation of Functions of Each Bit in the System Clock Control Register (SYCC)
Bit name
Description
Used to check the current clock mode.
When this bit is 0, the clock is stopping or waiting for stabilization of oscillation.
SCM: System clock
monitor bit
When this bit is 1, operations are performed in active mode.
Note:
bit7
This bit is read-only enabled. Writing a value to this bit does not affect
operation.
bit6,
bit5
Values in these bits are undefined when read.
Writing values into these bits does not affect operation.
Unused bits
Used to select an oscillation stabilization wait time setting.
When external interrupt causes a return from stop mode to active mode, the
oscillation stabilization wait time setting selected by these bits is applied.
The initial values of these bits are determined by options. Therefore, when an
oscillation stabilization wait time setting is to be applied for a reset, it is selected by
options.
WT1, WT0:
Oscillation
stabilization wait time
selection bits
bit4,
bit3
Note:
Change values in these bits after confirming that the clock is not waiting for
stabilization of oscillation using the SCM bit.
This bit is always "1" when read.
bit2
Unused bit
Note:
Specify "1".
Used to select the clock speed in active mode.
CS1, CS0:
Clock speed selection
bits
bit1,
bit0
One of four operating clock speeds (gears) can be specified for the CPU and
peripheral functions. However, these bits do not affect the operating clock for the
time-base timer.
■ Instruction Cycle (t
)
INST
For instruction cycles (minimum instruction run time), a 1/4, 1/8, 1/16, or 1/64 frequency can be selected
using the clock speed selection bits (CS1 and CS0).
In active mode, when the oscillation frequency (F ) is 12.5 MHz, the instruction cycle for the maximum
CH
speed (SYCC: CS1 and CS0 = 11 ) is 4/F (= about 0.32 µs).
B
CH
57
CHAPTER 3 CPU
3.6.4
Clock Mode
The clock speed is switched by selecting one of four frequency-divided source clocks
(gears).
■ Operations in Each Clock Mode
Table 3.6-2 Operations in Each Clock Mode
Clock speed
Operating clock in each block
Cause that cancels
standby mode
(excepting reset)
Standby
mode
SYCC register
(SYCC: CS1
and CS0)
Clock
time-base
timer
Peripheral
function
CPU
F
/4
Interrupt request
RUN
Sleep
Stop
CH
High
speed
F
/2
F
/4
CH
Generated
Stopped
CH
(1, 1)
Stopped
/8
Stopped
/2
Stopped
/8
External interrupt
Interrupt request
F
RUN
Sleep
Stop
CH
F
F
Generated
Stopped
CH
CH
(1, 0)
(0, 1)
Stopped
/16
Stopped
/2
Stopped
/16
External interrupt
Interrupt request
F
RUN
Sleep
Stop
CH
F
F
Generated
Stopped
CH
CH
Stopped
/64
Stopped
/2
Stopped
/64
External interrupt
Interrupt request
F
RUN
Sleep
Stop
CH
F
F
Generated
Stopped
CH
CH
(0, 0)
Low
Stopped
speed
Stopped
Stopped
External interrupt
Each clock mode allows transition to a corresponding standby (sleep/stop) mode. For details of standby
■ Gears (Clock Speed Switching Function)
Writing one of 00 to 11 into the clock speed selection bits (SYCC: CS1 and CS0) in the system clock
B
B
control register selects one of four clock speeds.
The CPU and peripheral circuits operate using the clock speed selected. However, the gear does not affect
the time-base timer.
Power consumption can be reduced by lowering the clock speed.
58
CHAPTER 3 CPU
■ Operations in Active Mode
In active (RUN) mode, the oscillator is generating a clock. The CPU, time-base timer, and other peripheral
circuits operate using the clock.
In active mode, all clock speeds except the time-base timer clock speed can be changed (using gears). In
active mode, specifying standby mode results in a transition to sleep mode or stop mode.
Operations always start in RUN mode after a reset (any type). (Operating modes are cancelled by a reset.)
Note:
Do not rewrite the values in the oscillation stabilization wait time selection bits (SYCC: WT1 and WT0)
while the clock is waiting for stabilization of oscillation. Using the system clock monitor bits, change
the values in these bits after checking that SYCC: SCM is "1".
59
CHAPTER 3 CPU
3.6.5
Oscillation Stabilization Wait Time
Oscillation stabilization wait time is to be applied when power is turned on to start the
clock in RUN mode while the clock is stopped in stop mode.
■ Oscillation Stabilization Wait Time
A ceramic or crystal resonator normally requires several or several tens of milli-seconds from oscillation
start to oscillation stabilization at a specific cycle (oscillation frequency).
Thus, CPU operation must be prohibited immediately after the start of oscillation, and the clock is to be
supplied to the CPU when oscillation is stable following the expiration of oscillation stabilization wait
time.
The period during which oscillation becomes stable is dependent on the type of oscillator (such as crystal or
ceramic) connected to the oscillation circuit (clock generator). Therefore, an oscillation stabilization wait
time setting appropriate to the oscillator used must be selected.
Figure 3.6-6 shows changes in a frequency generated by an resonator from generation to stabilization.
Figure 3.6-6 Changes of a Frequency after Generation
Normal operation
Return from stop mode
or reset operation
Duration required for a resonator
starts oscillation
Oscillation
stabilization wait time
X1
Start of oscillation
Oscillation stabilizes
■ Oscillation Stabilization Wait Time
Oscillation stabilization wait time is to be applied to start the clock in active mode while the clock is
stopped.
Oscillation stabilization wait time is the duration from when the counter of the time-base timer is cleared to
when the specified bits overflow.
● Oscillation stabilization wait time during operation
For oscillation stabilization wait time applied for a return from stop mode to active (RUN) mode due to
external interrupt, one of three oscillation stabilization wait time settings can be selected using the
oscillation stabilization wait time selection bits in the system clock control register (SYCC: WT1 and
WT0).
60
CHAPTER 3 CPU
● Oscillation stabilization wait time at a reset
Option settings specify oscillation stabilization wait time at a reset (initial values of WT1 and WT0).
Cancellation of stop mode by external reset also applies oscillation stabilization wait time.
Table 3.6-3 shows the relationship between the active mode operation start conditions and oscillation
stabilization wait time.
Table 3.6-3 Active Mode Operation Start Conditions and Oscillation Stabilization Wait Time
Cancellation of stop mode
Active mode operation start
condition
When power is turned
on
External reset
External interrupt
Selection of oscillation stabilization wait
time
Option settings
SYCC: WT1, WT0
61
CHAPTER 3 CPU
3.7
Standby Mode (Low-Power Consumption Mode)
The MB89202/F202RA series supports sleep mode and stop mode in standby mode.
Transition to standby mode is controlled by the standby control register (STBC)
settings.
In active mode, transition to sleep mode or stop mode is allowed.
In standby mode, operation of the CPU and peripheral functions is stopped to reduce
power consumption.
This section describes the relationship between standby mode and clock mode and
explains block operations in standby mode.
■ Standby Mode
In active mode, power consumption is reduced by lowering the speed of the operating clock for the CPU
and peripheral circuits using clock speed switching (gears). However, in standby mode, the clock controller
stops supply of the clock to the CPU (sleep mode) or stops oscillation of the source (stop mode) to reduce
power consumption.
● Sleep mode
In sleep mode, the CPU and watchdog timer are stopped. Peripheral functions operate using the normal
clock.
● Stop mode
In stop mode, the CPU and peripheral functions are stopped, and the clock does not oscillate. All the
functions except for external interrupt halt.
62
CHAPTER 3 CPU
3.7.1
Operations in Standby Mode
This section describes CPU and peripheral function operation in standby mode.
■ Operations in Standby Mode
Table 3.7-1 Operations of the CPU and Peripheral Functions in Standby Mode
Stop
(SPL=0)
Stop
(SPL=1)
Function
RUN
Sleep
Clock
Active
Active
Active
Stopped
Stopped
Stopped
Stopped
Instruction
Stopped
CPU
ROM
Active
Holding
Holding
Holding
RAM
I/O port
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Holding
Active
Stopped
Active
Active
Active
Active
Active
Active
Active
Active
Holding
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Active
Hi-Z
Time-base timer
Watchdog timer
8-bit PWM timer/counter
8/16-bit capture timer/counter
UART
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Active
Peripheral
function
8-bit serial I/O
12-bit PPG
Buzzer
External interrupt 1 and 2
A/D converter
Stopped
Stopped
● State of pins in standby mode
The state of most I/O pins can remain the same as those set immediately before transition to stop mode or
set to Hi-Z using the pin state setting bit in the standby control register (STBC: SPL), regardless of clock
mode.
Note:
63
CHAPTER 3 CPU
3.7.2
Sleep Mode
This section describes sleep mode.
■ Operations Relating to Sleep Mode
● Transition to sleep mode
In sleep mode, the operating clock for CPU is stopped. Although the CPU stops storing data in the registers
and RAM used immediately before transition to sleep mode, peripheral functions, excepting the watchdog
timer, continue to operate.
Writing "1" to the sleep bit in the standby control register (STBC: SLP) results in a transition to sleep
mode. Any attempt to write "1" into the SLP bit while an interrupt request is being generated fails,
transition to sleep mode cannot be made, and instructions are processed continuously. (Even after the
interrupt is processed completely, transition to sleep mode is not possible.)
● Cancellation of sleep mode
Sleep mode is cancelled by a reset or interrupt from a peripheral function.
Pin states are initialized by the reset operation.
When an interrupt request with an interrupt level higher than 11 is generated in a peripheral function or
B
external interrupt circuit in sleep mode, sleep mode is cancelled regardless of the CPU interrupt enable flag
(CCR: I) or interrupt level bits (CCR: IL1 and IL0).
When sleep mode is cancelled, a normal interrupt operation is performed, and if interrupts are acceptable,
interrupt processing is performed. Otherwise, if interrupts are unacceptable, the processing resumes starting
from an instruction next to the instruction which was issued immediately before transition to sleep mode.
64
CHAPTER 3 CPU
3.7.3
Stop Mode
This section describes the stop mode.
■ Operations Relating to Stop Mode
● Transition to stop mode
In stop mode, the oscillation frequency is stopped. Most functions stop storing data in the registers and
RAM used immediately before transition to stop mode.
The clock circuit stops oscillating, the peripheral functions and CPU stop operating, but the external
interrupt circuit continues to operate.
Writing "1" to the stop bit in the standby control register (STBC: STP) causes a transition to stop mode. At
that time, if the pin state setting bit (STBC: SPL) is "0", the states of the external pins are maintained. If the
pin state setting bit is "1", the states of the external pins are set to Hi-Z (the states of pins for which a pull-
up resistor is specified in the pull-up setting resistor are set to level "H").
An attempt to write "1" into the STP bit while an interrupt request is being generated fails, transition to stop
mode cannot made, and instructions are processed continuously. (Even after the interrupt is processed
completely, transition to stop mode is not made.)
For a transition to stop mode, prohibit the time-base timer interrupt request output (TBTC: TBIE = 0) when
necessary.
● Cancellation of stop mode
Stop mode is cancelled by a reset or external interrupt.
When a reset occurs in stop mode, the reset operation is performed after oscillation stabilization wait time.
pin states are initialized by the reset operation.
When an interrupt request with an interrupt level higher than 11 is generated in an external interrupt
B
circuit in stop mode, stop mode is cancelled regardless of the CPU interrupt enable flag (CCR: I) or
interrupt level bits (CCR: IL1 and IL0).
When stop mode is cancelled and oscillation stabilization wait time has expired, a normal interrupt
operation is performed. Then, if interrupts are acceptable, interrupt processing is performed. Otherwise, an
instruction following the instruction immediately before transition to stop mode is managed.
When an external interrupt cancels stop mode, part of the peripheral functions are restarted with data stored
before the beginning of sleep mode. Therefore, the initial interval of the interval timer and other similar
settings are rendered unknown. The peripheral functions must be initialized after returning from stop mode.
Note:
Among interrupts, only an interrupt request from the external interrupt circuit cancels the stop mode.
65
CHAPTER 3 CPU
3.7.4
Standby Control Register (STBC)
The standby control register (STBC) controls transition to sleep /stop modes, pin state
settings in stop mode, and software reset.
■ Standby Control Register (STBC)
Figure 3.7-1 Standby Control Register (STBC)
Initial value
00010---B
Address bit7
bit6 bit5
STP SLP SPL RST RESV
R/W R/W R/W R/W
bit4
bit3
bit2
bit1 bit0
0008H
R
Reserved bit
When read
RESV
When written
0
1
Always "0"
Does not affect operations
Software reset bit
RST
When written
When read
4-instruction reset signal
generated.
0
1
Does not affect operations
Always "1"
Pin state setting bit
SPL
0
Pin states applied are maintained in stop mode.
Pin states are set to Hi-Z in stop mode.
1
Sleep bit
SLP
When written
When read
Always "0"
Does not affect operations
Transition to sleep mode
0
1
Stop bit
STP
When read
Always "0"
When written
0
1
Does not affect operations
Transition to stop mode
: Readable/Writable
R/W
R
:
Read only
: Unused
: Initial value
66
CHAPTER 3 CPU
Table 3.7-2 Explanation of Functions of Each Bit in the Standby Control Register (STBC)
Bit name
Description
This bit specifies transition to stop mode.
STP:
Stop bit
Writing "1" into this bit allows transition to stop mode.
Writing "0" into this bit does not affect operations.
This bit is always read with the value of "0".
bit7
bit6
This bit specifies transition to sleep mode.
SLP:
Sleep bit
Writing "1" into this bit allows transition to sleep mode.
Writing "0" into this bit does not affect operations.
This bit is always read with the value of "0".
This bit specifies external pin states in stop mode.
Writing "0" into this bit maintains states (levels) of the external pins at transition to
stop mode.
Writing "1" into this bit sets states of the external pins to Hi-Z (states of pins for
which a pull-up resistor is specified are set to level "H").
This bit becomes "0" after a reset.
SPL:
pin state setting bit
bit5
bit4
This bit specifies software reset.
RST:
Software reset bit
Writing "0" into this bit generates a source of 4-instruction cycle internal reset.
Writing "1" into this bit does not affect operations.
This bit is always read with the value of "1".
RESV:
Reserved bit
This bit is always read with the value of "0".
Writing a value into this bit does not affect operations.
bit3
Values read out of these bits are undefined.
Writing values into these bits does not affect operations.
bit2 to bit0
Unused bits
67
CHAPTER 3 CPU
3.7.5
Diagram for State Transition in Standby Mode
Figure 3.7-2 shows the state transition diagram in standby mode.
■ Diagram for State Transition in Standby Mode
Figure 3.7-2 State Transition Diagram
Power turned on
Power-on reset
Oscillation
(9)
stabilization wait
Reset mode
(1) (2)
RUN mode
reset mode
(4)
(3)
(11)
Sleep mode
(10)
(6)
(8)
(5)
(7)
Oscillation
stabilization wait
Stop mode
(1)
: Cancellation of reset input
(2)
: Reset sources (multiple)
: Transition to sleep mode by the standby control register (STBC: SLP = 1)
(3)
: External reset input
(4)
: Transition to stop mode by the standby control register (STBC: STP = 1)
: Interrupt request
(5)
(6)
: External interrupt request
(7)
(8) (9)
(10) (11)
: Time-base timer overflow (end of oscillation stabilization wait time)
: External reset input
68
CHAPTER 3 CPU
● Transition to and cancellation of clock mode (non-standby mode)
Table 3.7-3 Transition to and Cancellation of Clock Mode
State transition
Transition conditions
(9) End of oscillation stabilization wait time (output of time-base timer)
Transition to active mode after
power-on reset
(1) Cancellation of reset input
Reset in RUN mode
(2) External reset, software reset, or watchdog reset
● Transition to and cancellation of standby mode
Table 3.7-4 Transition to and Cancellation of Standby Mode
State transition
Transition conditions
Transition to sleep mode
(3) STBC: SLP=1
(6) Interrupt (each type)
(4) External reset
Cancellation of sleep mode
Transition to stop mode
(5) STBC: STP=1
(7) External interrupt
(8) End of oscillation stabilization wait time (output of the time-base timer)
(10) External reset
Cancellation of stop mode
(11) External reset (during oscillation stabilization wait)
Note:
In standby mode, the CPU and watchdog timer stop. Thus, software and watchdog resets do not occur.
69
CHAPTER 3 CPU
3.7.6
Notes on Standby Mode
Even if the standby control register (STBC) sets standby mode, transition to standby
mode is not allowed when a peripheral function generates an interrupt request. When
an interrupt causes a return from standby mode to active mode, subsequent operations
depend on whether interrupt requests are acceptable.
■ Transition to Standby Mode and Interrupt
When an interrupt request with an interrupt level higher than 11 is generated in a peripheral function to
B
the CPU, an attempt to write "1" into the stop bit (STBC: STP) or sleep bit (SLP) in the standby control
register is ignored. Therefore, any attempt at transition to standby mode fails. (Even after the interrupt is
processed, transition to standby mode is not allowed.)
This type of rejection does not depend on whether the CPU can accept interrupts.
Even if the CPU is processing an interrupt, transition to standby mode is allowed when the request flag bit
for the interrupt has been cleared and there are no other interrupt requests to be processed.
■ Cancellation of Standby Mode by an Interrupt
When an interrupt request with an interrupt level higher than 11 is generated in a peripheral function or
B
another component in sleep mode or stop mode, standby mode is cancelled. This operation does not depend
on whether the CPU can accept interrupts.
After cancellation of standby mode, the CPU normally takes a branch to the interrupt processing routine if
the priority of the interrupt level setting register (ILR1 to ILR4) corresponding to the interrupt request is
higher than the level specified in the interrupt level bits (CCR: IL1 and IL0) in the condition code register
and if the interrupt enable flag is turned on (CCR: I = 1). Otherwise, an instruction is managed following
the instruction causing standby mode to be set.
To prohibit a branch to the interrupt processing routine immediately after return, interrupts must be
prohibited before standby mode is set.
■ Notes on Setting Standby Mode
For setting standby mode using the standby control register (STBC), use the settings specified in Table 3.7-
5 . When 1 is set to both bits at the same time, stop mode has precedence over sleep mode. However, it is
recommended that "1" not be set to the bits at the same time.
Table 3.7-5 Low-power Consumption Mode Established using the Standby Control
Register (STBC)
STBC register
Mode
STP(bit7)
SLP(bit6)
0
0
1
0
1
0
Active
Sleep
Stop
70
CHAPTER 3 CPU
■ Oscillation Stabilization Wait Time
The oscillator for oscillation frequency stops in stop mode, thus oscillation stabilization wait time must be
applied after the oscillator is activated.
Use one of three clock oscillation stabilization wait time settings generated by the time-base timer.
If the interval selected for the time-base timer is shorter than the oscillation stabilization wait time, an
interval timer interrupt request is generated during oscillation stabilization wait time. To prevent this from
occurring, disable output of time-base timer interrupt requests (TBTC: TBIE = 0) before transition to stop
mode when necessary.
71
CHAPTER 3 CPU
3.8
Memory Access Mode
The MB89202/F202RA series supports only single-chip mode for access to memory.
■ Single-chip Mode
In single-chip mode, only internal RAM and ROM are used. The CPU can access only the internal I/O area,
RAM area, and ROM area.
■ Mode Data
Set 00 into the mode data in internal ROM to select single-chip mode.
H
Figure 3.8-1 Configuration of Mode Data
Address
FFFDH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Operation
Value
00H
Selects single-chip mode.
Other than 00H
Reserved. Do not specify this value.
■ Operations for Selecting Memory Access Mode
Only single-chip mode is selectable.
Table 3.8-1 provides the settings for the mode pins and mode data.
Table 3.8-1 Settings for Mode Data
Memory access mode
Single-chip mode
Other modes
Mode data
00
H
Prohibited
Figure 3.8-2 shows the operations for selecting memory access.
72
CHAPTER 3 CPU
Figure 3.8-2 Operations for Selecting Memory Access
Source of a reset is generated.
I/O pins are high
impedance.
Wait for cancellation of
the reset source
(external reset or
oscillation stabilization
wait time)
Being reset
Mode data and reset vector are
fetched from internal ROM.
Mode fetch
Other
settings
Check of the mode data
Prohibited
Mode data
Single-chip mode (00H)
Setup of I/O pin
functions at execution
of program (RUN mode)
I/O settings for each I/O pin using
the port direction register (DDR)
and other measures
I/O pins are available
as ports.
73
CHAPTER 3 CPU
74
CHAPTER 4 I/O PORTS
4.1
Overview of I/O Ports
Six I/O ports (comprising 26 pins) are available as general-purpose I/O ports (parallel I/O
ports).
These ports also serve peripherals (as I/O pins for specific peripheral functions).
■ Functions of I/O Ports
The I/O ports function to output data from the CPU to I/O pins via their port data register (PDR) and send
signals input to I/O pins to the CPU. For some ports, the I/O direction of I/O pins can be set by optionally
setting the bits of the port data direction register (DDR), with the bits corresponding to the pins.
The functions of the ports and peripherals for which the ports may serve are summarized below.
•
•
Port 0:General-purpose I/O port may also serve peripherals (external interrupt 2 and analog input pins)
Port 3:General-purpose I/O port may also serve peripherals (12-bit PPG, external interrupt 1, UART, 8-
bit serial I/O, 8/16-bit timers, and buzzer output pin)
•
Port 4:General-purpose I/O port of a type switched between CMOS push-pull and N-ch open-drain may
also serve peripherals (analog input pins)
•
•
•
Port 5:General-purpose I/O port may also serve peripherals (8-bit PWM pin)
Port 6:General-purpose I/O port (for MB89F202/F202RA, P61, P60 are input port)
Port 7:General-purpose I/O port
Table 4.1-1 lists the functions of the ports, and Table 4.1-2 lists the register of ports.
Table 4.1-1 Functions of Ports
Port
name
Input
form
Output
form
Pin name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P07
P06
P05
P04
P03
AN7
INT23
P33
P02
AN6
INT22
P32
P01
AN5
INT21
P31
P00
AN4
INT20
P30
P00/INT20/
AN4 to
P07/INT27
Hysteresis
CMOS
analog
Port 0
Port 3
INT27
INT26
INT25
INT24
P34
CMOS
push-pull
P37
P36
P35
P30/UCK/SCK
to
P37/BZ/PPG
CMOS
hysteresis
BZ/
PPG
TO/
INT10
UCK/
SCK
INT12
INT11
EC
UI/SI
P42
UO/SO
P41
CMOS
push-pull
or N-ch
P43
P40
P40/AN0
to
P43/AN3
CMOS
analog
Port 4
Port 5
-
-
-
-
AN3
-
AN2
-
AN1
AN0
open-drain
P50
PWM
P60
CMOS
hysteresis
CMOS
push-pull
P50/PWM
-
-
-
-
-
-
-
-
-
P61
-
CMOS
push-pull
or N-ch
-
-
-
P60,
P61
CMOS
hysteresis
Port 6
Port 7
-
open-drain
P70
to
CMOS
CMOS
-
-
-
-
P72
P71
P70
P72
76
CHAPTER 4 I/O PORTS
Initial value
Table 4.1-2 Registers of Ports
Register name
Read/Write
Address
Port 0 data register
(PDR0)
(DDR0)
(PUL0)
(PDR3)
(DDR3)
(PUL3)
(PDR4)
(DDR4)
(OUT4)
(PDR5)
(DDR5)
(PUL5)
(PDR6)
(DDR6)
(PUL6)
(PDR7)
(DDR7)
(PUL7)
R/W
0000
0001
0070
XXXXXXXX
H
H
H
B
*1
Port 0 data direction register
Port 0 pull-up setting register
Port 3 data register
W
00000000
00000000
B
B
R/W
R/W
000C
000D
XXXXXXXX
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
B
*1
Port 3 data direction register
Port 3 pull-up setting register
Port 4 data register
W
00000000
00000000
B
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0071
000F
0010
0011
0012
0013
0072
0060
0061
0062
0063
0064
0065
----XXXX
B
Port 4 data direction register
Port 4 output form setting register
Port 5 data register
----0000
----0000
B
B
-------X
B
Port 5 data direction register
Port 5 pull-up setting register
Port 6 data register
-------0
-------0
B
B
------XX
B
*2
Port 6 data direction register
------00
------00
B
Port 6 pull-up setting register
Port 7 data register
B
-----XXX
B
Port 7 data direction register
Port 7 pull-up setting register
R/W : Readable and Writable
-----000
B
-----000
B
W
X
: Write only
: Undefined
*1 : DDR0 and DDR3 cannot be used for bit manipulation instructions.
*2 : DDR6 is not used in MB89F202/F202RA.
77
CHAPTER 4 I/O PORTS
4.2
Port 0
Port 0 is a general-purpose I/O port and may also serve as peripheral inputs. The pins of
this port can be used for peripherals or normal port function that can be selected
according to the setting of a bit corresponding to the pin on a specific register.
This section mainly explains the general-purpose I/O function of the port.
This section also describes the structure, pins, and associated registers of port 0 and
provides a block diagram of pins.
■ Structure of Port 0
Port 0 comprises the following four elements:
•
•
•
•
General-purpose I/O pins, external interrupt 2, and analog input pins (P00/INT20/AN4 to P07/INT27)
Port 0 data register (PDR0)
Port 0 data direction register (DDR0)
Port 0 pull-up setting register (PUL0)
■ Pins of Port 0
Port 0 has eight general-purpose I/O pins. When used as input pins at the same time, these pins can be also
used as external interrupt input pins.
Table 4.2-1 lists the pins of port 0.
Table 4.2-1 Pins of Port 0
Input and output form
Port
name
Peripherals for which a pin
may serve
Circuit
type
Pin name
Function
Input
Output
P00 general-
purpose I/O
INT20 : external interrupt input 20
AN4 : analog input 4
P00/INT20/AN4
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
P04/INT24
P01 general-
purpose I/O
INT21 : external interrupt input 21
AN5 : analog input 5
Analog CMOS
hysteresis
G
P02 general-
purpose I/O
INT22 : external interrupt input 22
AN6 : analog input 6
P03 general-
purpose I/O
INT23 : external interrupt input 23
AN7 : analog input 7
Port 0
CMOS
P04 general-
purpose I/O
INT24 : external interrupt input 24
INT25 : external interrupt input 25
INT26 : external interrupt input 26
INT27 : external interrupt input 27
P05 general-
purpose I/O
P05/INT25
CMOS
hysteresis
D
P06 general-
purpose I/O
P06/INT26
P07 general-
purpose I/O
P07/INT27
78
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 0
Figure 4.2-1 Block Diagram of Port 0
A/D converter A/D converter
channel select enable bit
A/D input occurring
To A/D
converter's
analog input
From external
interrupt enable
External
interrupt
Stop mode
(SPL=1)
External
interrupt
No A/D input
PDR
PDR read
PDR read
Pull-up
resistor
(when read-modify-write is
performed)
Pch
Nch
Output latch
PDR write
Pins
DDR
DDR write
Stop mode
(SPL=1)
PUL read
PUL
PUL write
SPL: Pin status setting bit of standby control register (STBC)
Note:
When the A/D converter is used, deselect pull-up action for pins P03/INT23/AN7 to P00/INT20/AN4.
Pins set to be used as analog input pins must not be used as an output port.
■ Registers PDR0, DDR0, and PUL0 of Port 0
Registers PDR0, DDR0, and PUL0 are associated with port 0.
The bits of these registers correspond to the pins of port 0 in one-to-one correspondence.
Table 4.2-2 Correspondence between the Pins and the Bits of the Port 0 Registers
Port name
Bits of associated registers and corresponding pins
PDR0, DDR0, PUL0
bit7
P07
bit6
P06
bit5
P05
bit4
P04
bit3
P03
bit2
P02
bit1
P01
bit0
P00
Port 0
Pin corresponding to bit
79
CHAPTER 4 I/O PORTS
4.2.1
Registers of Port 0 (PDR0, DDR0, and PUL0)
This section describes the registers associated with port 0.
■ Functions of Port 0 Registers
● Port 0 data register (PDR0)
The PDR0 register indicates the state of the output latch. For a pin set to function as an output port, the
same value ("0" or "1") as the value state of the output pin can be read from this register. If the pin is set to
function as an input port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, other than those for bits to be manipulated, do not
change.
● Port 0 data direction register (DDR0)
The DDR0 register sets the I/O direction of each pin per bit.
When a bit of the DDR0 register corresponding to a pin of port 0 is set to "1", the pin functions as an output
port. When the bit is set to "0", the pin functions as an input port.
Note:
Because the DDR0 register is write only, bit manipulation instructions (SETB, CLRB) do not apply.
● Setting a port pin to serve external interrupt inputs
If a pin of port 0 is used as an external interrupt input pin, enable the external interrupt circuit operation and
set the pin to function as an input port. When the pin is set in this mode, its output latch value has no
significance.
● Setting a port pin to serve analog inputs
If a pin of port 0 is used as an analog input pin, write "0" for the bit corresponding to the pin on the DDR0
register. The output transistor is then set to OFF and the pin is set in the Hi-Z state.
Set the bit of the ADEN register of the A/D converter to "1", the bit corresponding to the analog input pin
in use.
● Setting the input to a peripheral enable
If a peripheral with an input pin is used, set the pin of port 0 for the input to the peripheral to function as an
input port. In this mode, the corresponding output latch value has no significance.
80
CHAPTER 4 I/O PORTS
Table 4.2-3 Functions of Port 0 Registers
Register
name
When being
read
Read/
Write
Data
When being written
Address
Initial value
Output latch of "0" is set and
"L" level is output to the pin
in output port mode.
Pin state is
"L" level.
0
Port 0 data
register (PDR0)
R/W
0000
0001
XXXXXXXX
B
H
Output latch of "1" is set and
"H" level is output to the pin
in output port mode.
Pin state is
"H" level.
1
0
1
Output transistor operation
is disabled and the pin is set
to serve as an input pin.
Port 0 data
direction
register (DDR0)
Read
prohibited
(write only)
W
00000000
B
H
Output transistor operation
is enabled and the pin is set
to serve as output pin.
R/W : Readable/Writable
W
X
: Write only
: Undefined
● Port 0 pull-up setting register (PUL0)
The bits of the pull-up setting register correspond to the pins of port 0 in one-to-one correspondence. When
the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level (pull-up
state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and the pin
remains at Hi-Z.
Figure 4.2-2 shows the pull-up resistor settings assigned to the values of the bits of the port 0 pull-up
register.
Figure 4.2-2 Pull-up Resistor Settings (PUL0)
Initial value
PUL04 PUL03 PUL02 PUL01 PUL00 00000000B
Address
0070H PUL07
bit7
bit6 bit5
PUL06
bit4 bit3
bit2
bit1
bit0
PUL05
R/W R/W R/W R/W R/W R/W R/W R/W
PUL00
P02 pull-up OFF P01 pull-up OFF P00 pull-up OFF
PUL02
PUL01
PUL03
0
1
P03 pull-up OFF
P03 pull-up ON
P02 pull-up ON
P01 pull-up ON
P00 pull-up ON
PUL04
PUL07
PUL06
PUL05
0
1
P07 pull-up OFF P06 pull-up OFF P05 pull-up OFF P04 pull-up OFF
P05 pull-up ON P04 pull-up ON
P07 pull-up ON
P06 pull-up ON
R/W
: Readable/Writable
: Initial value
81
CHAPTER 4 I/O PORTS
4.2.2
Operations of Port 0 Functions
This section describes the operation of port 0.
■ Operation of Port 0
● Operation in output port mode
When "1" is written to a bit of the DDR0 register, the bit corresponding to a pin of port 0, the pin functions
as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the pin.
Once data has been written into the PDR0 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR0 register.
● Operation in input port mode
When "0" is written to a bit of the DDR0 register, the bit corresponding to a pin of port 0, the pin functions
as an input port.
In input port mode, the output transistor is OFF and the pin status is Hi-Z.
Once data has been written into the PDR0 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR0 register.
● Operation in external interrupt input mode
Set a bit of the DDR0 register to "0", the bit corresponding to a pin of port 0 that is to serve as an external
interrupt input pin, to set the pin to function as an input port.
The value state of the pin can be read by reading the PDR0 register regardless of whether external interrupt
inputs or interrupt request outputs are enabled or disabled.
● Operation in analog input mode
To use a pin of port 0 as analog input and to inhibit output transistor operation, set the bit corresponding to
the analog input pin to "0" on the DDR0 register. The value state of the pin can be read by reading the
PDR0 register.
Set the bit of the ADEN register of the A/D converter to "1", the bit corresponding to the analog input pin
in use.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR0 register are initialized to "0". Thus, all output transistors
become OFF and the pins become Hi-Z.
However, CPU resets do not initialize the PDR0 register. If a pin is used as an output port after the reset,
reinitialize the PDR0 register to contain new output data in the bit position corresponding to the pin and
then set the corresponding bit of the DDR0 register so that the pin will function as an output port.
82
CHAPTER 4 I/O PORTS
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is "1" and when the stop mode is
entered, the output transistor is turned OFF and the pin becomes Hi-Z because the output transistor is
forcibly turned OFF without respect to the value existing on the DDR0 register in the bit position
corresponding to the pin.
Input remains fixed to prevent leaks by input open.
Table 4.2-4 Operating Modes of Pins of Port 0
Pin name
Normal operation, sleep, stop (SPL = 0)
Stop (SPL = 1)
At a reset
P00/INT20/AN4
to
P03/INT23/AN7
General-purpose I/O port may also serve
external interrupt inputs or analog inputs
Hi-Z
Hi-Z
(External interrupt input)
P04/INT24
to
P07/INT27
General-purpose I/O port may also serve
external interrupt inputs
SPL : Pin state setting bit of standby control register (STBC: SPL)
Hi-Z: High impedance
Note:
When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level
instead of Hi-Z in stop mode (SPL = 1). During a reset, however, the pull-up is invalid with the pin
remaining at Hi-Z.
83
CHAPTER 4 I/O PORTS
4.3
Port 3
Port 3 is a general-purpose I/O port and may also serve as input pins for external
interrupts as well as input and output pins for peripherals.
This section mainly explains the general-purpose I/O function of the port.
This section also describes port 3 concerning to the structure, pins, a block diagram of
pins, and associated registers.
■ Structure of Port 3
Port 3 comprises the following four elements:
•
General-purpose I/O pins, external interrupt 1 input pins, and input/output pins for peripherals (P30/
UCK/SCK to P37/BZ/PPG)
•
•
•
Port 3 data register (PDR3)
Port 3 data direction register (DDR3)
Port 3 pull-up setting register (PUL3)
■ Pins of Port 3
Port 3 has eight CMOS I/O pins. These pins can be used as both input pins and external interrupt input pins
at the same time. These pins cannot be used as a general-purpose I/O port when being used for peripherals.
Table 4.3-1 Pins of Port 3
Input and output form
Port
name
Circuit
type
Pin name
Function
Peripherals for which the pin may serve
Input
Output
P30 general-purpose
I/O
UCK
SCK
UART clock I/O
8-bit serial I/O clock I/O
CMOS
hysteresis
P30/UCK/SCK
P31/UO/SO
P32/UI/SI
B
E
P31 general-purpose
I/O
UO
SO
UART data output
8-bit serial I/O data output
CMOS
P32 general-purpose
I/O
UI
SI
UART data input
8-bit serial I/O data input
CMOS
hysteresis
P33 general-purpose
I/O
P33/EC
EC
8/16-bit timer and counter clock inputs
Port 3
CMOS
P34 general-purpose
I/O
TO
INT10
8/16-bit timer and counter timer outputs
External interrupt input 10
P34/TO/INT10
P35/INT11
P36/INT12
P37/BZ/PPG
B
CMOS
hysteresis
P35 general-purpose
I/O
INT11
INT12
External interrupt input 11
External interrupt input 12
P36 general-purpose
I/O
P37 general-purpose
I/O
BZ
PPG
Buzzer output
12-bit PPG output
CMOS
E
84
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 3
Figure 4.3-1 Block Diagram of Port 3
External interrupt
enable
External
External interrupt
interrupt
occurring
Input to
peripheral
Hysteresis input
Input to
PDR
PDR read
PDR read
CMOS input
peripheral
Stop mode
Output from peripheral
Output
(SPL = 1)
Pull-up resistor
from
peripheral
enable
Output occurring
from peripheral
(when read-modify-write is
performed)
Pch
Output latch
PDR write
Pins
Nch
DDR
DDR write
Stop mode
(SPL = 1)
PUL read
PUL
PUL write
Note:
Because the value states of the pins are always input to the external interrupt circuit, when a pin is used
as a normal I/O port, the operation of the external interrupt circuit corresponding to the pin must be
■ Registers PDR3, DDR3, and PUL3 of Port 3
The registers PDR3, DDR3, and PUL3 are associated with port 3.
The bits of these registers correspond to the pins of port 3 in one-to-one correspondence.
Table 4.3-2 Correspondence between the Pins and the Bits of Port 3 Registers
Port name
Bits of associated registers and corresponding pins
PDR3, DDR3, PUL3
bit7
P37
bit6
P36
bit5
P35
bit4
P34
bit3
P33
bit2
P32
bit1
P31
bit0
P30
Port 3
Pin corresponding to bit
85
CHAPTER 4 I/O PORTS
4.3.1
Registers of Port 3 (PDR3, DDR3, PUL3)
This section describes the registers associated with port 3.
■ Functions of Port 3 Registers
● Port 3 data register (PDR3)
The PDR3 register indicates the state of the pins. For a pin set to function as an output port, the same value
("0" or "1") as held by the output latch can be read from this register. If the pin is set to function as an input
port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, excepting those for bits to be manipulated, do not
change.
● Port 3 data direction register (DDR3)
The DDR3 register sets the I/O direction of each pin per bit.
When a bit of the DDR3 corresponding to a pin of port 3 is set to "1", the pin functions as an output port.
When the bit is set to "0", the pin functions as an input port.
Note:
Because the DDR3 register is write only, bit manipulation instructions (SETB, CLRB) do not apply.
● Setting a port pin to serve external interrupts
If a pin of port 3 is used as an external interrupt input pin, enable the external interrupt circuit operation and
set the pin to function as an input port.
When the pin is set in this mode, its output latch value has no significance.
● Setting the output from a peripheral enable
If a peripheral with an output pin is used, set the output enable bit of the peripheral enable.
Because the output from the peripheral has priority, the values set on the PDR3 and DDR3 registers in the
bit position corresponding to the output pin for the peripheral have no significance, regardless of the value
output from the peripheral and the output enabled.
● Setting the input to a peripheral enable
If a peripheral with an input pin is used, set the pin of port 3 for the input to the peripheral to function as an
input port. In this mode, the corresponding output latch value has no significance.
86
CHAPTER 4 I/O PORTS
Table 4.3-3 Functions of Port 3 Registers
Register
name
When being
read
Read/
Write
Data
When being written
Address
Initial value
Output latch of "0" is set and
"L" level is output to the pin in
output port mode.
Pin state is
"L" level.
0
Port 3 data
register
R/W
000C
XXXXXXXX
B
H
Output latch of "1" is set and
"H" level is output to the pin in
output port mode.
(PDR3)
Pin state is
"H" level.
1
0
1
Output transistor operation is
disabled and the pin is set to
serve as an input pin.
Port 3 data
direction
register
Read
prohibited
(write only)
W
000D
00000000
B
H
Output transistor operation is
enabled and the pin is set to
serve as an output pin.
(DDR3)
R/W : Readable and Writable
W
X
: Write only
: Undefined
● Port 3 pull-up setting register (PUL3)
The bits of the pull-up setting register correspond to the pins of port 3 in one-to-one correspondence. When
the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level (pull-up
state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and the pin
remains at Hi-Z.
Figure 4.3-2 shows the pull-up resistor settings assigned to the values of the bits of the port 3 pull-up
register.
Figure 4.3-2 Pull-up Setting Register (PUL3)
Address bit7
bit6 bit5
bit4
bit3
bit2 bit1
bit0
Initial value
PUL33
0071H PUL37 PUL36 PUL35 PUL34
PUL32 PUL31 PUL30 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
PUL32
PUL33
PUL31
PUL30
P32 pull-up OFF
P32 pull-up ON
P30 pull-up OFF
0
1
P33 pull-up OFF
P33 pull-up ON
P31 pull-up OFF
P31 pull-up ON
P30 pull-up ON
PUL36
PUL37
PUL35
PUL34
P37 pull-up OFF P36 pull-up OFF P35 pull-up OFF P34 pull-up OFF
P37 pull-up ON P36 pull-up ON P34 pull-up ON
0
1
P35 pull-up ON
R/W : Readable and Writable
: Initial value
87
CHAPTER 4 I/O PORTS
4.3.2
Operations of Port 3 Functions
This section describes the operation of port 3.
■ Operation of Port 3
● Operation in output port mode
When "1" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, the pin functions
as an output port.
In output port mode, output transistor operation is enabled and output latch data is output to the pin.
Once data has been written into the PDR3 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR3 register.
● Operation in input port mode
When "0" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, the pin functions
as an input port.
In input port mode, the output transistor is OFF and the pin state is Hi-Z.
Once data has been written into the PDR3 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR3 register.
● Operation in external interrupt input mode
Set a bit of the DDR3 register to "0", the bit corresponding to a pin of port 3 that is to serve as an external
interrupt input pin, to set the pin to function as an input port.
The value state of the pin can be read by reading the PDR3 register regardless of whether or not the
external interrupt inputs or interrupt request outputs are enabled.
● Operation in mode enabling the output from a peripheral
When the output enable bit for a peripheral is set to enable, the corresponding pin is set to serve the output
from the peripheral.
Because the value state of the pin can be read from the PDR3 register even when the output from the
peripheral is enabled, the value output from the peripheral can be read.
● Operation in mode enabling the input to a peripheral
Set a bit of the DDR3 register to "0", the bit corresponding to the pin of port 3 assigned for the input to the
desired peripheral, for the pin to function as an input port.
The value state of the pin is always input to the peripheral (except during stop mode).
The value state of the pin can be read by reading the PDR3 register regardless of whether or not the
peripheral is using the input pin.
88
CHAPTER 4 I/O PORTS
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR3 register are initialized to "0", at which time the output
transistors become OFF (input port mode) and the pins become Hi-Z.
However, CPU resets do not initialize the PDR3 register. If a pin is used as an output port after the reset,
reinitialize the PDR3 register to contain new output data in the bit position corresponding to the pin and
then set the corresponding bit of the DDR3 register so that the pin will function as an output port.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is set to "1" and when the stop
mode is entered, the pin becomes Hi-Z because the output transistor is turned OFF regardless of the value
existing on the DDR3 register in the bit position corresponding to the pin.
Table 4.3-4 Operating Modes of Pins of Port 3
Normal operation, sleep, stop
(SPL = 0)
Pin name
Stop (SPL = 1)
At a reset
P30/UCK/SCK
to
P33/EC, P37/BZ/PPG
General-purpose I/O port may also
serve I/O for peripherals
Hi-Z
Hi-Z
P34/TO/INT10
to
P36/INT12
General-purpose I/O port may also
serve outputs from peripherals and
external interrupt inputs
Hi-Z
(External interrupt input)
SPL : Pin state setting bit of standby control register (STBC: SPL)
Hi-Z: High impedance
Note:
When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level
instead of Hi-Z in stop mode (SPL = 1). During a reset, however, the pull-up is invalid with the pin
remaining at Hi-Z.
89
CHAPTER 4 I/O PORTS
4.4
Port 4
Port 4 is a type of I/O port that is switched between CMOS push-pull and N-ch open-
drain and may also serve analog inputs. Each pin of this port can be used for
peripherals or normal port function that can be selected according to the setting of the
bit corresponding to the pin on a specific register.
This section explains the I/O port function of CMOS push-pull/ N-ch open-drain type.
This section also describes port 4 concerning to the structure, pins, a block diagram of
pins, and associated registers.
■ Structure of Port 4
Port 4 comprises the following four elements:
•
Type of I/O pins that are switched between CMOS push-pull and N-ch open-drain and analog input pins
(P40/AN0 to P43/AN3)
•
•
•
Port 4 data register (PDR4)
Port 4 data direction register (DDR4)
Port 4 output format setting register (OUT4)
■ Pins of Port 4
Port 4 has four I/O pins of CMOS push-pull/N-ch open-drain.
These pins can also be used as analog input pins.
Those pins that are used for analog inputs cannot be used as a general-purpose I/O port. Table 4.4-1 lists
the pins of port 4.
Table 4.4-1 Pins of Port 4
Peripherals for
which the pin
may serve
Input and output form
Port
name
Pin
name
Circuit
type
Function
Input
Output
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P40 I/O
P41 I/O
P42 I/O
P43 I/O
AN0 analog input 0
AN1 analog input 1
AN2 analog input 2
AN3 analog input 3
CMOS push-
pull/N-ch open-
drain
CMOS
analog
Port 4
F
90
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 4
Figure 4.4-1 Block Diagram of Port 4
A/D converter
channel select
A/D converter enable bit
To A/D
converter's
analog input
PDR
Stop mode (SPL = 1)
PDR read
PDR read
(when read-modify-write is
performed)
Pch
Nch
Output latch
PDR write
Pins
DDR
OUT
DDR write
Stop mode
(SPL = 1)
DDR read
OUT read
OUT write
■ Registers of Port 4
The registers PDR4, DDR4, and OUT4 are associated with port 4.
The bits of these registers correspond to the pins of port 4 in one-to-one correspondence.
Table 4.4-2 Correspondence between the Pins and the Bits of the Port 4 Register
Port name
Bits of associated registers and corresponding pins
PDR4, DDR4, OUT4
bit7
-
bit6
-
bit5
-
bit4
-
bit3
P43
bit2
P42
bit1
P41
bit0
P40
Port 4
Pin corresponding to bit
91
CHAPTER 4 I/O PORTS
4.4.1
Registers of Port 4 (PDR4)
This section describes the registers associated with port 4.
■ Functions of Port 4 Registers
● Port 4 data register (PDR4)
The PDR4 register indicates the state of the pins. For a pin set to function as an output port, the same value
("0"or "1") as held by the output latch can be read from this register. If the pin is set to function as an input
port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, excepting those for bits to be manipulated, do not
change.
Table 4.4-3 Functions of Port 4 Registers
Register
name
Read/
Write
Initial
value
Data
When being read
Pin state is "L" level.
N-ch open-
When being written
Address
Output latch of "0" is set and
"L" level is output to the pin
in output port mode.
0
Port 4
data
register
Output latch of "1" is set and
the pin in output port mode
is set at Hi-Z.
R/W
000F
----XXXX
H
B
drain type
Pin state
(PDR4)
1
0
is "H"
level.
CMOS
push-pull
type
Output latch of "1" is set and
"H" level is output to the pin
in output port mode.
The pin is set to function as
input pin with output
transistor operation disabled.
Port 4
data
Input port pin
direction
register
(DDR4)
R/W
R/W
0010
0011
----0000
----0000
H
H
B
The pin is set to function as
output pin with output
transistor operation enabled.
1
0
1
Output port pin
N-ch open-drain type
CMOS push-pull type
Port 4
Output format of the pin is
set to N-ch open-drain type.
output
format
setting
register
(OUT4)
B
Output format of the pin is
set to CMOS push-pull type.
R/W : Readable and Writable
: Undefined
X
92
CHAPTER 4 I/O PORTS
4.4.2
Operations of Port 4 Functions
This section describes the operation of port 4.
■ Operation of Port 4
● Operation in output port mode
When "1" is written for a bit of the DDR4 register, the bit corresponding to a pin of port 4, the pin functions
as an output port.
In output port mode, the output transistor operation is enabled and output latch data is output to the pin.
By setting the bit corresponding to the pin on the OUT4 register, N-ch open-drain or CMOS push-pull type
can be selected as the output format of the pin.
Once data has been written into the PDR4 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR4 register.
● Analog input mode setting
Set a bit of the DDR4 register to "0", the bit corresponding to a pin of port 4 assigned for desired analog
input, so that its output transistor is set to OFF and the pin is set at Hi-Z.
Its output latch value can be read by reading the PDR4 register.
Set the bit of the ADEN register of the A/D converter to "1", the bit corresponding to the analog input pin
in use.
● Operation when a reset is performed
When the CPU is reset, the bits of the PDR4 register are initialized to "1". Thus, the output transistors
become OFF (input port mode) and the pins become Hi-Z.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is set to "1" and when the stop
mode is entered, the pin becomes Hi-Z because the output transistor is turned OFF regardless of the value
existing on the DDR4 register in the bit position corresponding to the pin. Input remains fixed to prevent
leaks by input open.
Table 4.4-4 Operating Modes of Pins of Port 4
Pin name
Normal operation, sleep, stop (SPL = 0)
Stop (SPL = 1)
At a reset
General-purpose I/O port may also serve I/O
for peripherals
P40/AN0 to P43/AN3
Hi-Z
Hi-Z
SPL : Pin state setting bit of standby control register (STBC: SPL)
Hi-Z: High impedance
93
CHAPTER 4 I/O PORTS
4.5
Port 5
Port 5 is a general-purpose I/O port and may also serve the input/output for peripherals.
The pins of this port can be used for peripherals or normal port function that can be
selected according to the setting of the bit corresponding to the pin on a specific
register.
This section explains the general-purpose I/O function of the port.
This section also describes port 5 concerning to the structure, pins, a block diagram of
pins, and associated registers.
■ Structure of Port 5
Port 5 comprises the following four elements:
•
•
•
•
General-purpose I/O pins (P50/PWM)
Port 5 data register (PDR5)
Port 5 data direction register (DDR5)
Port 5 pull-up setting register (PUL5)
■ Pins of Port 5
Port 5 has one CMOS I/O pin.
Table 4.5-1 Pin of Port 5
Input and output
form
Port
name
Peripherals for which the
pin may serve
Circuit
type
Pin name
Function
Input
Output
P50 general-
purpose I/O
PWM (8-bit PWM/timer
output)
Port 5
P50/PWM
CMOS
CMOS
E
94
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 5
Figure 4.5-1 Block Diagram of Port 5
PDR
Stop mode (SPL = 1)
Pull-up resistor
PDR read
Output from
peripheral
Output
enable
from
peripheral
PDR read
(when read-modify-write is
performed)
P-ch
N-ch
Output latch
PDR write
Pin
DDR
DDR write
Stop mode (SPL = 1)
DDR read
PUL read
PUL
PUL write
■ Registers of Port 5
The registers PDR5, DDR5, and PUL5 are associated with port 5.
One of the bits of these registers corresponds to one pin of port 5.
Table 4.5-2 Correspondence between the Pin and a Bit of the Port 5 Registers
Port name
Bits of associated registers and corresponding pins
PDR5, DDR5, PUL5
bit7
-
bit6
-
bit5
-
bit4
-
bit3
-
bit2
-
bit1
-
bit0
P50
Port 5
Pin corresponding to bit
95
CHAPTER 4 I/O PORTS
4.5.1
Registers of Port 5 (PDR5, DDR5, PUL5)
This section describes the registers associated with port 5.
■ Functions of Port 5 Registers
● Port 5 data register (PDR5)
The PDR5 register indicates the state of pins. For a pin set to function as an output port, the same value
("0" or "1") as held by the output latch can be read from this register. If the pin is set to function as an input
port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, excepting those for bits to be manipulated, do not
change.
● Port 5 data direction register (DDR5)
A bit of the DDR5 register sets the I/O direction of the pin corresponding to the bit.
When the bit of the DDR5 register is set to "1", the pin functions as an output port. When the bit is set to
"0", the pin functions as an input port.
● Setting the output from a peripheral enable
If a peripheral with an output pin is used, set the output enable bit of the peripheral enable.
As it is apparent from the block diagram, the pin in this mode serves output from the peripheral, thereby
superseding its general-purpose port function.
Because the output from the peripheral has priority, the values set on the PDR5 and DDR5 registers for the
output pin used for the peripheral have no significance, regardless of the value output from the peripheral
and the output enabled.
Table 4.5-3 lists the functions of the port 5 registers.
96
CHAPTER 4 I/O PORTS
Table 4.5-3 Functions of Port 5 Registers
Register
name
When being
read
When being
written
Data
Read/Write
Address
Initial value
Output latch of "0" is
set and "L" level is
output to the pin in
output port mode.
Pin state is "L"
level.
0
Port 5 data
register
R/W
00012
-------X
B
H
Output latch of "1" is
set and the pin in
output port mode is
set at Hi-Z.
(PDR5)
Pin state is "H"
level.
1
0
The pin is set to
function as an input
pin with output
transistor operation
disabled.
Input port pin
Port 5 data
direction
register
R/W
0013
-------0
B
H
The pin is set to
function as an output
pin with output
transistor operation
enabled.
(DDR5)
1
Output port pin
R/W : Readable/Writable
: Undefined
X
● Port 5 pull-up setting register (PUL5)
When the ON setting of the pull-up resistor is selected by using the pull-up setting register, the pin state
will be "H" level (pull-up state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up
is invalid and the pin remains at Hi-Z.
Figure 4.5-2 Pull-up Setting Register (PUL5)
Address
0072H
bit7
bit6 bit5
bit4 bit3
bit2 bit1
bit0
PUL50
R/W
Initial value
-------0B
PUL50
0
1
P50 pull-up OFF
P50 pull-up ON
R/W : Readable/Writable
: Unused
: Initial value
97
CHAPTER 4 I/O PORTS
4.5.2
Operations of Port 5 Functions
This section describes the operation of port 5.
■ Operation of Port 5
● Operation in output port mode
When "1" is written for a bit of the DDR5 register, the bit corresponding to the pin of port 5, the pin
functions as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the pin.
Once data has been written into the PDR5 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR5 register.
● Operation in input port mode
When "0" is written for a bit of the DDR5 register, the bit corresponding to the pin of port 5, the pin
functions as an input port.
In input port mode, the output transistor is OFF and the pin state is Hi-Z.
Once data has been written into the DDR5 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR5 register.
● Operation in mode enabling the output from a peripheral
When the output enable bit for a peripheral is set enable, the corresponding pin is set to serve the output
from the peripheral.
Because the value state of the pin can be read from the PDR5 register even when the output from the
peripheral is enabled, the value output from the peripheral can be read.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR5 register are initialized to "0". Thus, the output transistor
becomes OFF (input port mode) and the pin becomes Hi-Z.
However, CPU resets do not initialize the PDR5 register. If the pin is used as an output port after the reset,
reinitialize the PDR5 register to contain new output data in the bit position corresponding to the pin and
then set the corresponding bit of the DDR5 register so that the pin will function as an output port.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is set to "1" and when the stop
mode is entered, the pin becomes Hi-Z because the output transistor is turned OFF regardless of the value
existing on the DDR5 register in the bit position corresponding to the pin. Input remains fixed to prevent
leaks by input open.
98
CHAPTER 4 I/O PORTS
Table 4.5-4 Operating Modes of Pin of Port 5
Pin name
Normal operation, sleep, stop (SPL = 0)
Stop (SPL = 1)
Hi-Z
At a reset
P50/PWM
General-purpose I/O port further may serve I/O for peripherals
Hi-Z
SPL : Pin state setting bit of standby control register (STBC: SPL)
Hi-Z: High impedance
Note:
If the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level
(pull-up state) instead of Hi-Z in stop mode (SPL = 1). During a reset, however, the pull-up is invalid
with the pin remaining at Hi-Z.
99
CHAPTER 4 I/O PORTS
4.6
Port 6
Port 6 is a general-purpose I/O port.
This section describes the port function when operating as general-purpose I/O port.
This section also describes the structure, pins, the block diagram of pins, and
associated registers of port 6.
■ Structure of Port 6
Port 6 comprises the following four elements:
•
General-purpose I/O pins (input pins P61-P60 for MB89F202/F202RA)
Port 6 data register (PDR6)
•
•
Port 6 data direction register (DDR6, not used in MB89F202/F202RA)
Port 6 pull-up setting register (PUL6)
•
■ Pins of Port 6
Port 6 has 2 I/O pins of CMOS input type (they are input only pins for MB89F202/F202RA).
Table 4.6-1 Pins of Port 6
Peripherals for
which a pin may
serve
Input and output form
Circuit
type
Port name
Pin name
Function
Input
Output
P60 general-
purpose I/O*
P60
P61
-
-
CMOS
-
H / E
H / E
Port 6
P61 general-
purpose I/O*
CMOS
-
*: P61 and P60 are general-purpose input port for MB89F202/F202RA.
100
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 6
Figure 4.6-1 Block Diagram of Port6
For MB89202/V201
PDR
Stop mode (SPL = 1)
Pull-up resistor
PDR read
PDR read
(when read-modify-write is
performed)
P-ch
N-ch
Output latch
PDR write
Pin
DDR
DDR write
Stop mode (SPL = 1)
DDR read
PUL read
PUL
SPL: Pin state setting bit of standby control register (STBC: SPL)
PUL write
For MB89F202/F202RA
PDR
Stop mode (SPL = 1)
Pin
PDR read
PDR read
(when read-modify-write is
performed)
Output latch
PDR write
DDR read
DDR
DDR read
PUL read
PUL
SPL: Pin state setting bit of standby control register (STBC: SPL)
PUL write
101
CHAPTER 4 I/O PORTS
■ Registers PDR6, DDR6, and PUL6 of Port 6
Registers PDR6, DDR6, and PUL6 are associated with port 6.
The bits of these registers correspond to the pins of port 6 in one-to-one correspondence.
Table 4.6-2 Correspondence between the Pins and the Bits of Port 6 Registers
Port name
Bits of associated registers and corresponding pins
PDR6, DDR6, PUL6
bit7
-
bit6
-
bit5
-
bit4
-
bit3
-
bit2
-
bit1
bit0
Port 6
Pin corresponding to bit
P61*
P60*
*: DDR control is not used for this bit in MB89F202/F202RA.
102
CHAPTER 4 I/O PORTS
4.6.1
Registers of Port 6 (PDR6, DDR6, PUL6)
This section describes the registers associated with port 6.
■ Functions of Port 6 Registers
● Port 6 data register
The PDR6 register indicates the state of the output latch. For a pin set to function as an output port, the
same value ("0" or "1") as the value state of the output pin can be read from this register. If the pin is set
to function as an input port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, other than those for bits to be manipulated, do not
change.
● Port 6 data direction register (DDR6 for P60, P61)
The DDR6 register sets the I/O direction of each pin per bit.
When a bit of the DDR6 corresponding to a pin of port 6 is set to "1", the pin functions as an output
port. When the bit is set to "0", the pin functions as an input port.
Table 4.6-3 lists the functions of the port 6 registers.
Table 4.6-3 Functions of Port 6 Registers
Register
name
When being
read
Read/
Write
Data
When being written
Address
Initial value
Output latch of "0" is set and
"L" level is output to the pin
in output port mode.
Pin state is
"L" level.
0
Port 6 data
register (PDR6)
R/W
R/W
0060
0061
------XX
B
H
Output latch of "1" is set and
"H" level is output to the pin
in output port mode.
Pin state is
"H" level.
1
0
1
Output transistor operation
is disabled and the pin is set
to serve as an input pin.
Input port
Port 6 data
direction
register (DDR6)
------00
B
H
Output transistor operation
is enabled and the pin is set
to serve as output pin.
Output port
R/W : Readable/Writable
: Undefined
X
103
CHAPTER 4 I/O PORTS
● Port 6 pull-up setting register (PUL6)
The bits of the pull-up setting register correspond to the pins of port 6 in one-to-one correspondence.
When the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level
(pull-up state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and
the pin remains at Hi-Z.
Figure 4.6-2 shows the pull-up resistor settings assigned to the values of the bits of the port 6 pull-up
setting register.
Figure 4.6-2 Pull-up Resistor Settings (PUL6)
Initial value
Address
0062H
bit7
bit6 bit5
bit4 bit3
bit2
bit1
bit0
-
-
------00B
-
-
-
PUL61 PUL60
R/W R/W
-
-
-
-
-
-
-
PUL60
PUL61
0
1
P61 pull-up OFF P60 pull-up OFF
P61 pull-up ON P60 pull-up ON
R/W
: Readable/Writable
: Initial value
104
CHAPTER 4 I/O PORTS
4.6.2
Operations of Port 6 Functions
This section describes the operation of port 6.
■ Operation of Port 6
● Operation in output port mode
When "1" is written for a bit of the DDR6 register, the bit corresponding to a pin of port 6, the pin
functions as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the
pin.
Once data has been written into the PDR6 register, the written data is held in the output latch and output
to the pin as it is.
The value state of the pin can be read by reading the PDR6 register.
● Operation in input port mode
When "0" is written for a bit of the DDR6 register, the bit corresponding to a pin of port 6, the pin
functions as an input port.
In input port mode, the output transistor is OFF and the pin status is Hi-Z.
Once data has been written into the PDR6 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR6 register.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR6 register are initialized to "0". Thus, all output transistors
become OFF and the pins become Hi-Z.
However, CPU resets do not initialize the PDR6 register. If a pin is used as an output port after the
reset, reinitialize the PDR6 register to contain new output data in the bit position corresponding to the
pin and then set the corresponding bit of the DDR6 register so that the pin will function as an output
port.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is "1" and when the stop
mode is entered, the output transistor is turned OFF and the pin becomes Hi-Z because the output
transistor is forcibly turned OFF without respect to the value existing on the DDR6 register in the bit
position corresponding to the pin.
Input remains fixed to prevent leaks by input open.
105
CHAPTER 4 I/O PORTS
Table 4.6-4 Operating Modes of Pins of Port 6
Pin name
Normal operation, sleep, stop (SPL = 0)
General-purpose I/O port
Stop (SPL = 1)
At a reset
P60, P61
Hi-Z
Hi-Z
Note:
When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level
instead of Hi-Z in stop mode (SPL = 1). During a reset, however, the pull-up is invalid with the pin
remaining at Hi-Z.
106
CHAPTER 4 I/O PORTS
4.7
Port 7
Port 7 is a general-purpose I/O port.
This section describes the port function when operating as general-purpose I/O port.
This section also describes the port structure, pins, the pin block diagram associated
registers of port 7.
■ Structure of Port 7
Port 7 comprises the following four elements:
•
General-purpose I/O pin (P70 to P72)
Port 7 data register (PDR7)
•
•
Port 7 data direction register (DDR7)
Port 7 pull-up setting register (PUL7)
•
■ Pins of Port 7
Port 7 has 3 CMOS I/O pin.
Table 4.7-1 Pins of Port 7
Input and output form
Circuit
type
Port name
Pin name
Function
Input
Output
Port 7
P70 to P72
General-purpose I/O
CMOS
CMOS
E
107
CHAPTER 4 I/O PORTS
■ Block Diagram of Port 7
Figure 4.7-1 Block Diagram of Port 7
PDR
Stop mode (SPL = 1)
Pull-up resistor
PDR read
PDR read
(when read-modify-write is
performed)
Pch
Nch
Output latch
PDR write
Pin
DDR
DDR write
Stop mode (SPL = 1)
DDR read
PUL read
PUL
PUL write
■ Registers PDR7, DDR7, and PUL7 of Port 7
Registers PDR7, DDR7, and PUL7 are associated with port 7.
The bits of these registers correspond to the pins of port 7 in one-to-one correspondence.
Table 4.7-2 Correspondence between the Pins and the Bits of the Port 7 Registers
Port name
Bits of associated registers and corresponding pins
PDR7, DDR7, PUL7
bit7
-
bit6
-
bit5
-
bit4
-
bit3
-
bit2
P72
bit1
P71
bit0
P70
Port 7
Pin corresponding to bit
108
CHAPTER 4 I/O PORTS
4.7.1
Registers of Port 7 (PDR7, DDR7, PUL7)
This section describes the registers associated with port 7.
■ Functions of Port 7 Registers
● Port 7 data register (PDR7)
The PDR7 register indicates the state of the output latch. For a pin set to function as an output port, the
same value ("0" or "1") as the value state of the output pin can be read from this register. If the pin is set
to function as an input port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, other than those for bits to be manipulated, do not
change.
● Port 7 data direction register (DDR7)
The DDR7 register sets the I/O direction of each pin per bit.
When a bit of the DDR7 corresponding to a pin of port 7 is set to "1", the pin functions as an output
port. When the bit is set to "0", the pin functions as an input port.
Table 4.7-3 Functions of Port 7 Registers
Register
name
When being
read
Read/
Write
Data
When being written
Address
Initial value
Output latch of "0" is set and
"L" level is output to the pin
in output port mode.
Pin state is
"L" level.
0
Port 7 data
register (PDR7)
R/W
R/W
0063
0064
-----XXX
B
H
Output latch of "1" is set and
"H" level is output to the pin
in output port mode.
Pin state is
"H" level.
1
0
1
Output transistor operation
is disabled and the pin is set
to serve as an input pin.
Input port
Port 7 data
direction
register (DDR7)
-----000
B
H
Output transistor operation
is enabled and the pin is set
to serve as output pin.
Output port
R/W : Readable and Writable
: Undefined
X
109
CHAPTER 4 I/O PORTS
● Port 7 pull-up setting register (PUL7)
The bits of the pull-up setting register correspond to the pins of port 7 in one-to-one correspondence.
When the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level
(pull-up state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and
the pin remains at Hi-Z.
Figure 4.7-2 shows the pull-up resistor settings assigned to the values of the bits of the port 7 pull-up
register.
Figure 4.7-2 Pull-up Resistor Settings (PUL7)
Initial value
Address
0065H
bit7
bit6 bit5
bit4 bit3
bit2
bit1
bit0
-
-----000B
-
-
-
PUL72 PUL71 PUL70
R/W R/W R/W
-
-
-
-
-
-
PUL70
PUL72
PUL71
0
1
P72 pull-up OFF P71 pull-up OFF P70 pull-up OFF
P72 pull-up ON
R/W
: Readable/Writable
: Initial value
P71 pull-up ON
P70 pull-up ON
110
CHAPTER 4 I/O PORTS
4.7.2
Operations of Port 7 Functions
This section describes the operation of port 7.
■ Operation of Port 7
● Operation in output port mode
When "1" is written for a bit of the DDR7 register, the bit corresponding to a pin of port 7, the pin
functions as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the
pin.
Once data has been written into the PDR7 register, the written data is held in the output latch and output
to the pin as it is.
The value state of the pin can be read by reading the PDR7 register.
● Operation in input port mode
When "0" is written for a bit of the DDR7 register, the bit corresponding to a pin of port 7, the pin
functions as an input port.
In input port mode, the output transistor is OFF and the pin status is Hi-Z.
Once data has been written into the PDR7 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR7 register.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR7 register are initialized to "0". Thus, all output transistors
become OFF and the pins become Hi-Z.
However, CPU resets do not initialize the PDR7 register. If a pin is used as an output port after the
reset, reinitialize the PDR7 register to contain new output data in the bit position corresponding to the
pin and then set the corresponding bit of the DDR7 register so that the pin will function as an output
port.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is "1" and when the stop
mode is entered, the output transistor is turned OFF and the pin becomes Hi-Z because the output
transistor is forcibly turned OFF without respect to the value existing on the DDR7 register in the bit
position corresponding to the pin.
Input remains fixed to prevent leaks by input open.
111
CHAPTER 4 I/O PORTS
Table 4.7-4 Operating Modes of Pins of Port 7
Pin name
Normal operation, sleep, stop (SPL = 0)
General-purpose I/O port
Stop (SPL = 1)
At a reset
P70 to P72
Hi-Z
Hi-Z
Note:
When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level
instead of Hi-Z in stop mode (SPL = 1). During a reset, however, the pull-up is invalid with the pin
remaining at Hi-Z.
112
CHAPTER 4 I/O PORTS
4.8
Programming Example of I/O Port
This section provides an example of programming with I/O ports.
■ I/O Port Programming Example
● Processing specification
Ports 0 and 3 are used to light all seven segments of LED (eight segments if the decimal point is included).
Pin P00 is connected to the anode common pin of LED and pins P30 to P37 are connected to the pins of the
segments.
Figure 4.8-1 Example of the Pins and the 8-segment LED Connected
MB89202/V201/F202/F202RA
P00
P37
P36
.
.
.
P30
113
CHAPTER 4 I/O PORTS
● Coding example
PDR0 EQU 0000H
; Address of port 0 data register
DDR0 EQU 0001H
PDR3 EQU 000CH
DDR3 EQU 000DH
; Address of port 0 data direction register
; Address of port 3 data register
; Address of port 3 data direction register
;------------------------------Main program-----------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
:
CLRB PDR0:0
; Set P00 at "L" level.
MOV PDR3,#11111111B
MOV DDR0,#11111111B
; Set all pins of port 3 at "H" level.
; Set P00 to function as an output port by coding
#XXXXXXX1B.
MOV DDR3,#11111111B
; Set all bits of DDR3 such that all pins of port 3 function
as an output port.
:
ENDS
;---------------------------------------------------------------------------------------------------------------------
END
114
CHAPTER 5 TIME-BASE TIMER
5.1
Overview of Time-base Timer
The time-base timer functions as an interval timer. The time-base timer is a 21-bit free-
run counter that counts up in synchronization with the internal count clock (at the
oscillation frequency divided by 2). The timer also has an interval timer function to
select one of four time intervals. In addition, it provides timer output for oscillation
stabilization time and an operation clock for the watchdog timer.
The time-base timer stops operating in modes in which oscillation stops.
■ Interval Timer Function
The interval timer function is used to continuously generate interrupts at specified intervals.
•
•
An interrupt occurs when the interval timer bits of the time-base timer counter overflow.
One of four time intervals can be selected by setting the interval timer bits.
Table 5.1-1 lists the time intervals for the time-base timer.
Table 5.1-1 Time Intervals for Time-base Timer
Internal count clock cycle
Time interval
13
2 /F (Approximately 0.66 ms)
CH
15
2 /F (Approximately 2.6 ms)
CH
2/F (0.16 µs)
CH
18
2 /F (Approximately 21.0 ms)
CH
22
2 /F (Approximately 335.5 ms)
CH
F
: Oscillation frequency
CH
The values enclosed in parentheses are time intervals when the oscillation frequency is 12.5 MHz.
■ Clock Supply Function
The clock supply function is used to provide one of three timer outputs for the oscillation stabilization wait
time and the operation clock for the resource function.
Table 5.1-2 lists cycles of the clock that the time-base timer supplies to peripherals.
Table 5.1-2 Clock Cycles Supplied by Time-base Timer (1/2)
Clock supplied to
Clock cycle
Remarks
14
2 /F (Approximately 1.31 ms)
CH
Selected by the oscillation stabilization time
selection bits (SYCC: WT1, WT0) of the clock
control section system clock control register.
Oscillation
stabilization time
17
2 /F (Approximately 10.49 ms)
CH
18
2 /F (Approximately 20.97 ms)
CH
116
CHAPTER 5 TIME-BASE TIMER
Table 5.1-2 Clock Cycles Supplied by Time-base Timer (2/2)
Clock supplied to
Watchdog timer
A/D converter
Clock cycle
Remarks
Watchdog timer count up clock
Continuous activation clock
22
2 /F (Approximately 335.5 ms)
CH
8
2 /F (Approximately 20.5 µs)
CH
F
: Oscillation frequency
CH
The values enclosed in parentheses are time intervals when the oscillation frequency is 12.5 MHz.
Note:
Because oscillation cycles vary immediately after oscillation starts, the oscillation stabilization wait
time is listed for reference.
117
CHAPTER 5 TIME-BASE TIMER
5.2
Configuration of Time-base Timer
The time-base timer consists of the following four function blocks.
• Time-base counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of Time-base Timer
Figure 5.2-1 Block Diagram of Time-base Timer
To A/D converter
To watchdog timer
Time-base timer counter
X22 X23 X26
FCH
divided
by two
X27
X28 X29 X210 X211 X212 13 X214 X215 X216 X217
X2
X220 X221
X21
To clock control
section oscillation
stabilization time
selector
Clearing counter
Clearing watchdog timer
OF
OF
OF
OF
Power-on reset
Counter
clear
Interval timer
Starting stop mode
selector
circuit
(in normal mode)
IRQ7 (time-base timer interrupt)
TB0F TBIE
TBC1 TBC0 TBR
OF: Overflow
FCH
:
Oscillation frequency
Time-base timer control register (TBTC)
● Time-base timer counter
A 21-bit up counter that accepts the oscillation frequency divided by two as the count clock and stops
operating when oscillation stops.
● Counter clear circuit
Clears the counter when the TBTC register is set (TBR = 0), stop mode is entered (STBC: STP = 1), or a
power-on reset occurs.
● Interval timer selector
Selects 1 bit for the interval timer from four bits in the time-base counter. When the specified bit overflows,
an interrupt occurs.
● Time-base timer control register (TBTC)
Selects a time interval, clears the counter, controls interrupts, or checks the status.
118
CHAPTER 5 TIME-BASE TIMER
5.3
Time-base Timer Control Register (TBTC)
The time-base timer control register (TBTC) selects a time interval, clears the counter,
controls interrupts, or checks the status.
■ Time-base Timer Control Register (TBTC)
Figure 5.3-1 Time-base Timer Control Register (TBTC)
Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
000A TBOF TBIE
TBC1 TBC0
TBR
R/W R/W R/W
00---000
H
B
R/W R/W
Time-base timer initialization bit
TBR
Read
Write
0
1
The time-base timer counter is cleared.
"1" is always read.
Nothing is changed and affected.
TBC1 TBC0
Time interval selection bits
213
/FCH
0
0
1
1
0
215
218
222
/
/
/
FCH
FCH
FCH
1
0
1
F
CH: Oscillation frequency
Interrupt request enable bit
The interrupt request output is disabled.
The interrupt request output is enabled.
TBIE
0
1
Overflow interrupt request flag bit
TBOF
Read
Write
0
1
The specified bit has not overflowed.
The specified bit has overflowed.
This bit is cleared.
Nothing is changed and affected.
R/W : Readable/Writable
: Unused
: Initial value
119
CHAPTER 5 TIME-BASE TIMER
Table 5.3-1 Explanation of Functions of Each Bit in Time-base Timer Control Register (TBTC)
Bit name
Description
•
•
•
This bit is set to "1" when the specified bit of the time-base timer counter
overflows.
An interrupt request is sent when this bit and the interrupt request enable bit
(TBIE) are both "1".
While this bit is written, it is cleared when "0" is specified, and nothing is
changed and affected when "1" is specified.
TBOF:
Overflow interrupt request
flag bit
bit7
bit6
This bit enables or disables an interrupt request to be output to the CPU. An
interrupt request is output when this bit and the overflow interrupt request flag bit
(TBOF) are both "1".
TBIE:
Interrupt request enable bit
bit5
to
bit3
•
•
These bits are undefined when they are read.
Nothing is affected when they are written.
Unused bits
•
•
•
These bits specify a time interval for the interval timer.
The interval timer bits of the time-base timer counter are specified.
One of four time intervals can be selected.
bit2, TBC1, TBC0:
bit1
bit0
Time interval selection bits
•
•
This bit clears the time-base timer counter.
The counter is cleared to 000000 when "0" is written to this bit, nothing is
TBR:
Time-base timer
initialization bit
H
changed and affected when "1" is written.
Note:
This bit is always "1" at the beginning of reading.
120
CHAPTER 5 TIME-BASE TIMER
5.4
Interrupt of Time-base Timer
The time-base timer counter generates an interrupt when the specified bit of the counter
overflows (interval timer function).
■ Interrupts when the Interval Timer Function is Enabled
The counter counts up with the internal count clock. When the specified interval timer bit overflows, the
overflow interrupt request flag bit (TBTC: TBOF) is set to "1". Then if the interrupt request enable bit is
enabled (TBTC: TBIE = 1), an interrupt request (IRQ7) is sent to the CPU. When this occurs, use the
interrupt handling routine and set the TBOF bit to "0" to clear the interrupt request. The TBOF bit is set to
"1" when the specified bit overflows regardless of the value of the TBIE bit.
Note:
When the interrupt request is allowed to be output (TBIE = 1) after a reset is released, clear the TBOF bit
(TBOF = 0) at the same time.
Note:
•
An interrupt request is generated immediately after the TBIE bit is set from 0 (disable) to 1 (enable) if
the TBOF bit is "1".
•
When the counter is cleared (TBTC: TBR = 0) and the specified bit overflows at the same time, the
TBOF bit is not set.
■ Oscillation Stabilization Time and Time-base Timer Interrupts
If a time interval is set the time shorter than the oscillation stabilization time, the interval interrupt request
(TBTC: TBOF = 1) is generated from the time-base timer upon the start of normal mode. In this case,
interrupts from the time-base timer must be disabled (TBTC: TBIE = 0) when switching to stop mode in
which an oscillation is stopped.
■ Register and Vector Table Related to Interrupts from Time-base Timer
Table 5.4-1 Register and Vector Table Related to Time-base Timer Interrupts
Interrupt level setting register
Register Bits to be set
ILR2 (007C )
Address of vector table
Interrupt name
High-order
Low-order
FFEC
FFED
IRQ7
L71 (bit7) L70 (bit6)
H
H
H
121
CHAPTER 5 TIME-BASE TIMER
5.5
Operations of Time-base Timer Functions
The time-base timer functions as an interval timer or supplies clocks to some
peripherals.
■ Operations of Interval Timer Function (Time-base Timer)
To use as an interval timer, the settings shown below must be made.
Figure 5.5-1 Setting Interval Timer Function
bit7
bit6
TBIE
1
bit5
bit4
bit3
bit2 bit1
TBC1
bit0
TBOF
TBR
TBC0
TBTC
0
0
: Used bit
: Set to "1"
: Set to "0"
1
0
The counter in the time-base timer continues to count up in synchronization with the internal count clock
(at the oscillation frequency divided by two) as long as the clock oscillates.
The counter counts from "0" upon being cleared (TBR = 0). When the interval timer bit overflows, the
overflow interrupt request flag bit (TBOF) is set to "1". In other words, interrupts are generated at specified
intervals, starting from when the counter is cleared.
■ Operations of Clock Supply Function
The time-base timer is often used to make oscillation stabilization wait time. The oscillation stabilization
time is measured from when the time-base timer counter is cleared to when the oscillation stabilization bit
overflows. One of three oscillation stabilization time can be selected by the oscillation stabilization time
selection bits of the system clock control register (SYCC: WT1, WT0).
The time-base timer supplies clocks to the watchdog timer and A/D converter. Clearing the time-base timer
counter affects the operation of continuous activation cycles. In addition, when the time-base timer is
cleared, the counter in the watchdog timer is also cleared.
■ Operations of Time-base Timer
Figure 5.5-2 shows the operation of the time-base timer when:
•
•
•
•
power-on reset occurs.
sleep mode is entered while the interval timer function is being performed in normal mode.
stop mode is entered.
a counter clear request is generated.
In stop mode, the time-base timer is cleared and stops operating. When returning from stop mode, the time-
base timer counts the oscillation stabilization time.
122
CHAPTER 5 TIME-BASE TIMER
Figure 5.5-2 Operations of Time-base Timer
Counter value
1FFFFFH
Cleared by switching to stop mode
Oscillation
stabilization
overflow
000000H
Interval cycle
(TBTC:TBC1,TBC0=11 )
B
Counter clear
(TBTC:TBR=0)
CPU
operation start
Power-on reset (optional)
Cleared by interrupt handling routine
TBOF bit
TBIE bit
Sleep
SLP bit
(STBC register)
Exit stop state by IRQ7
Stop
STP bit
(STBC register)
Exit stop state by an external interrupt
Note: When the interval time selection bits of time-base timer control register (TBTC : TBC1, TBC0)
are set to 11 (222/FCH).
: Oscillation stabilization time
123
CHAPTER 5 TIME-BASE TIMER
5.6
Notes on Using Time-base Timer
Notes on using the time-base timer are shown below.
■ Notes on Using Time-base Timer
● Notes on using programs to set time-base timer
When the interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit is enabled
(TBTC: TBIE = 1), a return from interrupt handling is not possible. The TBOF bit must be cleared.
● Clearing time-base timer
The time-base timer is cleared when the time-base timer initialization bit is set to 0 (TBTC: TBR = 0) or
when the oscillation stabilization time is required. Because the time-base timer is used as the count clock
for the watchdog timer, clearing the time-base timer also clears the watchdog timer.
● Using time-base timer as oscillation stabilization time timer
Oscillation has not yet started in stop mode or when the power is turned on. Therefore, the time-base timer
makes oscillation stabilization wait time after the resonator starts operating.
The appropriate oscillation stabilization time must be selected according to the type of resonator connected
to the resonator (clock generator).
● Notes on peripheral functions the time-base timer supplies to the clock
When entering the modes in which oscillation stops, the counter is cleared and the time-base timer stops
operating. The clock from the time-base timer may have a shorter "H" level period or longer "L" level
period (up to half the clock cycle) when the counter of the time-base timer is cleared because the clock
starts operating from the initial state. The clock for the watchdog timer also starts operating from the initial
state, but the watchdog timer operates at a normal cycle because the watchdog timer counter is cleared at
the same time.
124
CHAPTER 5 TIME-BASE TIMER
5.7
Program Example for Time-base Timer
Programming examples for the time-base timer are shown below.
■ Programming Examples for Time-base Timer
● Processing specification
18
Repeatedly generate an interval timer interrupt at intervals of 2 /F (F : oscillation frequency). The
CH
CH
time interval is approximately 21.0 ms (operating at 12.5 MHz).
● Coding examples
TBTC
EQU
EQU
EQU
0000AH
TBTC:7
007CH
; Address of time-base timer control register
; Definition of interrupt request flag bit
; Address of interrupt level setting register 2
; [DATA SEGMENT]
TBOF
ILR2
INT_V
DSEG
ORG
DW
ABS
0FFECH
WARI
IRQ7
; Setting interrupt vector
INT_V
ENDS
;------------------------Main program---------------------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
; Stack pointer (SP) or other registers are assumed to
have been initialized.
:
CLRI
MOV
MOV
; Interrupt disable
ILR2,#01111111B
; Setting interrupt level (level 1)
TBTC,#01000100B ; Clearing interrupt request flag, enabling interrupt
18
request output, selecting 2 /F , and clearing
CH
time-base timer
SETI
:
; Interrupt enable
;------------------------Interrupt processing routine------------------------------------------------------------------
WARI CLRB TBOF ; Clearing interrupt request flag
PUSHW A
XCHW A,T
PUSHW A
:
User processing:
:
POPW
A
XCHW A, T
125
CHAPTER 5 TIME-BASE TIMER
POPW
A
RETI
ENDS
; --------------------------------------------------------------------------------------------------------------------
END
126
CHAPTER 6 WATCHDOG TIMER
6.1
Overview of Watchdog Timer
The watchdog timer is a 1-bit counter that uses output from the time-base timer, based
on oscillation frequency, as the count clock. The watchdog timer resets the CPU when
not cleared within a specified period after activation.
■ Watchdog Timer Function
The watchdog timer is a counter for preventing programs from hanging up. The timer must be cleared at
specified intervals after being activated. If the timer is not cleared within a specified period of time
because, for example, a program goes into an endless loop, the timer sends to the CPU a watchdog reset
having a period of four instruction cycles.
The watchdog timer uses the output from the time-base timer as the count clock.
The time intervals for the watchdog timer are listed in Table 6.1-1 . When the watchdog timer is not
cleared, a watchdog reset occurs following the time between the minimum time interval and the maximum
time interval. The counter must be cleared before the time of the minimum time interval.
Table 6.1-1 Watchdog Timer Time Intervals
Count clock
Time-base timer output (Oscillation frequency: 12.5 MHz)
Minimum time interval
Maximum time interval
Approximately 335.5 ms *
Approximately 671.0 ms
22
*: (number of counts of time-base timer (2 )) × (oscillation frequency (F ) divided by 2)
CH
time intervals of the watchdog timer.
Notes:
•
The watchdog timer counter is cleared when the time-base counter is cleared (TBTC : TBR = 0)
while output from the time-base timer is selected. Therefore, if the time-base timer counter
supplying the count clock is cleared repeatedly within the time interval of the watchdog timer, the
watchdog timer does not function correctly.
•
When switching to sleep or stop mode, the watchdog timer counter is cleared and stops operating
until returning to normal operation (RUN state).
128
CHAPTER 6 WATCHDOG TIMER
6.2
Configuration of Watchdog Timer
The watchdog timer consists of the following four function blocks.
• Watchdog timer counter
• Reset control circuit
• Counter clear control circuit
• Watchdog control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 6.2-1 Block Diagram of Watchdog Timer
Watchdog control register (WDTC)
WTE1 WTE0
WTE3 WTE2
Watchdog timer
Clear
Start
222/FCH
(Time-
base timer
output)
Reset
control
circuit
Overflow
RST
1-bit counter
● Watchdog timer counter (1-bit counter)
A 1-bit counter that operates by accepting output from the time-base timer as the count clock.
● Reset control circuit
Sends the reset signal to the CPU when the watchdog timer counter overflows.
● Counter clear control circuit
Controls the clearing and stopping of the watchdog timer counter.
● Watchdog control register (WDTC)
Activates and clears the watchdog timer counter. Because this register is write-only, bit manipulation
instructions cannot be used.
129
CHAPTER 6 WATCHDOG TIMER
6.3
Watchdog Control Register (WDTC)
The watchdog control register (WDTC) activates and clears the watchdog timer.
■ Watchdog Control Register (WDTC)
Figure 6.3-1 Watchdog Control Register (WDTC)
Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
0009H
WTE3 WTE2
WTE1 WTE0
R/W R/W R/W R/W
RESV
R/W
0---XXXXB
Watchdog control bit
WTE3 WTE2 WTE1
WTE0
1
Starts the watchdog timer
(upon first writing after reset)
0
1
0
Clears the watchdog timer
(upon second or subsequent writing after a
reset)
Other than above
No operation
RESV
Reserved bit
Write "0" to this bit.
0
R/W : Readable/writable
: Unused
X
: Undefined
Table 6.3-1 Explanation of Functions of Each Bit in Watchdog Control Register (WDTC)
Bit name
Description
bit7
RESV: Reserved bit
•
Write "0" to this bit.
bit6
to
bit4
•
•
Undefined when it is read.
Writing values does not affect operation.
Unused bits
•
•
Writing "0101 " activates (for first writing) or clears (for second
B
or subsequent writing) the watchdog timer.
bit3
to
bit0
WTE3, WTE2,
WTE1, WTE0:
Watchdog control bits
Writing other than "0101 " does not affect operation.
B
Note:
These bits indicate "1111 " when read. Bit manipulation
B
instructions cannot be used.
130
CHAPTER 6 WATCHDOG TIMER
6.4
Operations of Watchdog Timer Functions
The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
■ Operations of Watchdog Timer
● Activating watchdog timer
The watchdog timer is activated when the first time "0101 " is written to the watchdog control bits
B
(WDTC: WTE3 to WTE0) of the watchdog control register.
The watchdog timer cannot be stopped without accepting a reset upon activation.
● Clearing watchdog timer
The watchdog timer counter is cleared the second or subsequent time "0101 " is written to the watchdog
B
control bits (WDTC: WTE3 to WTE0) of the watchdog control register.
When the counter is not cleared within the time interval of the watchdog timer, the counter overflows and
the timer generates the internal reset signal having a period of four instruction cycles.
● Time intervals of watchdog timer
The time interval varies depending on the timing at which the watchdog timer is cleared. Figure 6.4-1
shows the relationship between the clear timings and time intervals of the watchdog timer when output
from the time-base timer is used as the count clock (oscillation frequency: 12.5 MHz).
Figure 6.4-1 Clearing Watchdog Timer and Time Interval
Minimum time interval
335.5 ms
Count clock output from
time-base timer
Overflow
Watchdog clear
Watchdog 1-bit counter
Watchdog reset
Maximum time interval
671.0 ms
Count clock output from
time-base timer
Watchdog clear
Overflow
Watchdog 1-bit counter
Watchdog reset
131
CHAPTER 6 WATCHDOG TIMER
6.5
Notes on Using Watchdog Timer
Notes on using the watchdog timer are provided below.
■ Notes on Using Watchdog Timer
● Stopping watchdog timer
The watchdog timer cannot be stopped without accepting a reset upon activation.
● Clearing watchdog timer
Clearing the time-base timer counter that supplies the count clock to the watchdog timer also clears the
watchdog timer counter at the same time.
Switching to sleep or stop mode clears the watchdog timer counter.
● Notes on creating programs
When creating a program that repeatedly clears the watchdog timer in the main loop, ensure that the time
necessary for main loop processing, including interrupt handling, is shorter than the minimum time interval
of the watchdog timer.
132
CHAPTER 6 WATCHDOG TIMER
6.6
Program Example for Watchdog Timer
Programming examples for the watchdog timer are provided below.
■ Programming Examples of Watchdog Timer
● Processing specification
•
•
•
Activate the watchdog timer immediately after the program starts.
Clear the watchdog timer whenever the loop of the main program is run.
Ensure that the time necessary for running the main loop once, including interrupt handling, is shorter
than the minimum time interval (approximately 335.5 ms: operating at 12.5 MHz) of the watchdog
timer.
● Coding example
WDTC EQU
WDT_CLR EQU 00000101B
0009H
;
Address of watchdog control register
VECT DSEG
ORG
ABS
;
;
[DATA SEGMENT]
Setting reset vector
0FFFEH
PROG
RST_V DW
VECT ENDS
;------------------------Main program---------------------------------------------------------------------------------
CSEG
;
;
;
[CODE SEGMENT]
PROG
Initialization routine upon reset
Setting initial value of stack pointer (for interrupt)
MOVW SP,#0280H
:
Initializing interrupt or other peripheral functions
:
INIT
MOV
WDTC,#WDT_CLR
;
Activating watchdog timer
MAIN MOV
:
WDTC,#WDT_CLR
;
Clearing watchdog timer
User processing (interrupt may occur in this processing.)
:
JMP
MAIN
;
Ensure that the time necessary for running the loop is
shorter than the minimum time interval of the watchdog
timer.
ENDS
;---------------------------------------------------------------------------------------------------------------------
END
133
CHAPTER 6 WATCHDOG TIMER
134
CHAPTER 7 8-BIT PWM TIMER
7.1
Overview of 8-bit PWM Timer
An 8-bit PWM timer has the interval timer functions and the PWM timer functions of an
8-bit resolution. A counter is incremented using interval timer functions in
synchronization with three types of internal count clocks or the output of 8/16-bit
capture timer/counter. The user can select one of these functions. Therefore, the 8-bit
interval timer can be set and the square wave of any frequency can be output using the
set output. In addition, if a low-pass filter is connected to the PWM output, the D/A
converter can be used.
■ Interval Timer Functions (Functions to Output the Square Wave)
Interrupts are generated repeatedly at any interval by the interval timer functions.
Because the output level of the pin (P50/PWM pin) can be inverted for each interrupt, the square wave of
any frequency can also be output.
8
•
•
An interval timer operation from the cycle of the count clock to 2 -times cycle is possible.
The count clock can be selected from four types.
Table 7.1-1 shows the range of intervals and square wave output.
Table 7.1-1 Range of Intervals and Square Wave Output
Count clock cycle Interval
1t
Square wave output (Hz)
8
9
1
2
3
INST
1t
to 2 t
1/ (2t
) to 1/ (2 t
)
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
Internal count
clock
4
12
5
13
16t
64t
INST
INST
INST
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
)
)
)
)
INST
INST
INST
INST
INST
INST
INST
6
14
7
15
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
17
2
10
2t
32t
2t
to 2 t
1/ (2 t
) to 1/ (2 t
5
21
6
14
INST
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
EXT
INST
INST
EXT
8/16-bit timer
count clock
4
9
25
10
18
512t
INST
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
)
INST
INST
16
9
1t
EXT
1t
to 2 t
1/ (2t
) to 1/ (2 t
)
EXT
EXT
t
t
: Instruction cycle (Affected by the clock mode and others.)
: Output cycle of an 8/16-bit capture timer
INST
EXT
136
CHAPTER 7 8-BIT PWM TIMER
Note:
Calculation example of intervals and square wave frequency
The following expression is the interval when the count clock cycle is set to 1 t
and when an
INST
oscillation frequency (F ) of 12.5 MHz and a PWM compare register (COMR) value of DD (221)
CH
H
are set. Another expression is the frequency of the square wave output from the PWM pin that is
operated continuously without changing the COMR register value.
However, the values are true when the maximum speed clock of the normal mode is selected (CS1,
CS0 = 11 , 1 instruction cycle = 4/F ) with the system clock control register (SYCC).
B
CH
Interval
= (1 × 4/FCH ) × (COMR register value + 1)
= (4/12.5 MHz) × (221 + 1)
= 71.0 µs
Output frequency = FCH / (1 × 8 × (COMR register value + 1))
= 12.5 MHz/ (8 × (221 + 1))
7.04 kHz
■ PWM Timer Functions
The PWM timer functions have an 8-bit resolution and can control the "H" level width and "L" level width
of one cycle.
Because the resolution is 1/256, a pulse can be output at a duty ratio of 0 to 99.6%.
The frequency of the PWM wave can be selected from four types.
The low-pass filter can be connected to the output and used as the D/A converter.
Table 7.1-2 shows the frequency of the PWM wave that can be set by PWM timer functions. Figure 7.1-1 is
a configuration example of the D/A converter.
Table 7.1-2 Frequencies of the PWM Wave that can be Set by the PWM Timer Functions
1
2
3
4
Internal clock
Output of an 8/16-bit capture timer/counter
2
6
10
1t
to
2 t
to
2 t
to
2 t
to
EXT
8
INST
INST
INST
1t
16t
64t
Count clock cycle
PWM wave cycle
INST
INST
INST
10
14
18
2 t
2 t
2 t
2 t
INST
EXT
INST
INST
10
14
18
8
2 t
to
2 t
to
2 t
to
2 t
to
INST
INST
INST
EXT
16
8
12
14
2 t
2 t
2 t
INST
INST
INST
18
22
26
2 t
2 t
2 t
2 t
EXT
INST
INST
INST
t
t
: Instruction cycle (Affected by the clock mode and others.)
INST
: Output frequency of an 8/16-bit capture timer
EXT
137
CHAPTER 7 8-BIT PWM TIMER
Figure 7.1-1 Configuration Example of the D/A Converter with the PWM Output and a Low-Pass Filter
PWM output
Analog output (Va)
PWM pin
R
C
Analog output waveform
Relationship between analog output
voltage and PWM output waveform
Va
Va
Vcc
Va/Vcc = T
H/T
Tr represents the amount required to
stabilize output.
t
Tr
PWM output waveform
Vcc
TH
T
L
T
Note:
While PWM timer functions are enabled, no interrupt request occurs.
138
CHAPTER 7 8-BIT PWM TIMER
7.2
Configuration of 8-bit PWM Timer
An 8-bit PWM timer consists of the following six blocks.
• Count clock selector
• 8-bit counter
• Comparator
• PWM generation and output control circuit
• PWM compare register (COMR)
• PWM control register (CNTR)
■ Block Diagram of an 8-bit PWM Timer
Figure 7.2-1 Block Diagram of an 8-bit PWM Timer
Internal data bus
CNTR
P/TX
COMR
PWM compare register
P0
TIR
TIE
P1
TPE
OE
IRQ9
(Output of an 8/16-bit
capture timer/counter)
Count
clock
8
8-bit counter
Start
CLK
selector
ECLK
1
TO
8
Comparator
Clear
16
64
Latch
1tINST
Overflow
Timer/
PWM
PWM generation
circuit and output
control circuit
Output pin control
Output
Pin
P50/PWM
t
INST : Instruction cycle
139
CHAPTER 7 8-BIT PWM TIMER
● Count clock selector
The count clock selector selects one of three types of internal counter clock. The selector also selects an 8/
16-bit capture timer or counter and uses it to increment the count of the 8-bit counter.
● 8-bit counter
This counter is incremented by the count clock selected by the count clock selector.
● Comparator
A latch in the comparator holds the COMR register value when the value of the 8-bit counter is 00 and
H
then compares the 8-bit counter with the COMR register value latched and detects a match.
● PWM generation circuit and PWM output control circuit
During the interval timer operation, once a match is detected, an interrupt request occurs. And when the bit
to control the output pin (CNTR: OE) is "1", the output level of the P50/PWM pin is inverted by the output
control circuit, at which time the 8-bit counter is cleared.
During the PWM timer operation, once a match is detected, the output level of the P50/PWM pin is
changed from "H" level to "L" level by the PWM generation circuit. Thereafter, when the 8-bit counter
overflows, the output level is returned to "H" level.
● COMR register
This register is used to set a value for comparison with the counter value of the 8-bit counter.
● CNTR register
This register is used to select the operation mode, enable and disable operations, set the count clock, control
interrupts, and check status.
When the operation mode is the PWM timer mode (P/TX = 0), the 8-bit counter cannot be cleared (by the
match detection signal from the comparator) and the interrupt request (IRQ9) is disabled.
140
CHAPTER 7 8-BIT PWM TIMER
7.3
Pin of 8-bit PWM Timer
This section describes the pin and provides a block diagram of the pin related to the 8-
bit PWM timer.
■ Pin Related to the 8-bit PWM Timer
The pin related to the 8-bit PWM timer is the P50/PWM pin.
● P50/PWM pin
This pin can be used as a general-purpose I/O port (P50) and for output of the interval timer or PWM timer
(PWM).
PWM:
While the pin functions as the interval timer, the square wave is output to the pin.
While the pin functions as the PWM timer, the PWM wave is output to the pin.
When the bit to control the output pin is set to the dedicated pin (CNTR: OE = 1), the P50/PWM pin
automatically functions as an output pin, regardless of the value of the port 5 data direction register
(DDR5: bit0), and as the PWM pin.
■ Block Diagram of the Pin Related to the 8-bit PWM Timer
Figure 7.3-1 Block Diagram of the Pin Related to the 8-bit PWM Timer
PDR
Stop mode (SPL=1)
Pull-up resistor
PDR read
Resource output
Resource
output is
enabled
PDR read
(At read-modify-write)
Pch
Nch
Output latch
PDR write
Pin
P50/PWM
DDR
DDR write
DDR read
PUL read
Stop mode
(SPL=1)
PUL
PUL write
141
CHAPTER 7 8-BIT PWM TIMER
7.4
Registers of 8-bit PWM Timer
This section describes the registers related to the 8-bit PWM timer.
■ Registers Related to the 8-bit PWM Timer
Figure 7.4-1 Registers Related to the 8-bit PWM Timer
CNTR (PWM control register)
Address
bit7
bit6
bit5
P1
bit4
P0
bit3
bit2
TIR
R/W
bit1
OE
bit0
TIE
R/W
Initial value
0-000000B
0022H
P/TX
R/W
TPE
R/W
R/W
R/W
R/W
COMR (PWM compare register)
bit7
bit6
bit5
W
bit4
W
bit3
W
bit2
W
bit1
W
bit0
W
Address
Initial value
XXXXXXXXB
0023H
W
W
: Readable/Writable
R/W
W
: Write only
: Unused
X
: Undefined
Note:
Because the PWM compare register (COMR) is a write-only register, an instruction to operate bits
cannot be used.
142
CHAPTER 7 8-BIT PWM TIMER
7.4.1
PWM Control Register (CNTR)
The PWM control register (CNTR) is used to select the operation mode (interval timer
operation or PWM timer operation) of the 8-bit PWM timer, switch the resolution of the
PWM timer functions, and select the count clock.
■ PWM Control Register (CNTR)
Figure 7.4-2 PWM Control Register (CNTR)
Address
0022H
Initial value
0-000000B
bit7 bit6 bit5 bit4 bit3 bit2 bit1
bit0
P1
P0
P/TX
R/W
TPE TIR
OE TIE
R/W R/W R/W R/W R/W R/W
TIE
0
Bit to enable an interrupt request
Disables interrupt request output.
Enables interrupt request output.
1
OE
0
Bit to control the output pin
Used as the general-purpose port (P50)
1
Used as the output pin for the interval timer or PWM timer (PWM)
Interrupt request flag bit
Read
TIR
Write
The PWM
timer used
The interval timer used
The counter value does not
match the settings.
Clears this bit.
0
1
Not changed
Not changed. Does
not affect other settings.
The counter value matches
the settings.
TPE
0
Bit to enable the counter operation
Stops the counter operation.
Starts the counter operation.
1
P1 P0
Bits to select a clock
1 tINST
0
1
0
1
0
0
1
Internal
count
clock
16 tINST
64 tINST
1
Outputs an 8/16-bit capture timer/counter.
Bit to select the operation mode
P/TX
Operates as the interval timer.
Operates as the PWM timer.
0
1
tINST : Instruction cycle
R/W
: Readable/Writable
: Initial value
143
CHAPTER 7 8-BIT PWM TIMER
Table 7.4-1 Explanation of the Functions of Each Bit in the PWM Control Register (CNTR)
Bit name
Function
This bit is used to select the interval timer operation (P/TX = 0) or PWM timer
operation (P/TX = 1).
P/TX:
bit7
bit6
Bit to select the
operation mode
Note:
Before writing into this bit, stop the counter operation (TPE = 0), disable an
interrupt (TIE = 0), and clear the interrupt request flag bit (TIR = 0).
The value during a read is undetermined.
A write does not affect operations.
Unused bit
This bit is used to select the count clock of the interval timer functions or PWM
timer functions.
bit5,
bit4
P1, P0:
Bits to select the clock
One of three types of internal count clock or the output of the 8/16-bit capture
timer or counter can be selected.
Note:
When the counter is operating (TPE = 1), do not switch P1 and P0.
This bit is used to start and stop the interval timer functions or PWM timer
functions.
To start the count operation, write "1" to this bit. When "0" is written to this bit,
TPE:
bit3
bit2
Bit to enable the counter
operation
the counter is cleared (setting 00 ) and then stopped.
H
While the internal timer functions are enabled:
When the counter value matches the PWM compare register (COMR) value, "1" is
set to this bit.
When this bit and the bit to enable an interrupt request (TIE) are "1", an interrupt
request to the CPU is output.
TIR:
Interrupt request flag bit
While the PWM timer functions are enabled, an interrupt request does not occur.
When this bit is written, it is cleared (setting "0"). Writing "1" does not affect this
bit in any way.
When this bit is "0", the P50/PWM pin is used as a general-purpose port (P50).
When the bit is "1", it is used as a dedicated pin (PWM).
OE:
bit1
bit0
Bit to control the output
pin
When the interval timer functions are enabled, the square wave is output to the
PWM pin. When the PWM timer functions are enabled, the PWM wave is output
to the PWM pin.
TIE:
This bit is used to enable and disable the output of an interrupt request to the CPU.
Bit to enable an interrupt When this bit and the interrupt request flag bit (TIR) are both "1", an interrupt
request request is output.
144
CHAPTER 7 8-BIT PWM TIMER
7.4.2
PWM Compare Register (COMR)
The PWM compare register (COMR) is used to set an interval while the internal timer
functions are enabled. In addition, the register becomes the "H" level width of a pulse
while the PWM timer functions are enabled.
■ PWM Compare Register (COMR)
Figure 7.4-3 shows the bit configuration of a PWM compare register. Because this register is a write-only
register, an instruction to operate bits cannot be used.
Figure 7.4-3 PWM Compare Register (COMR)
Address
0023H
Initial value
bit7
W
bit6
W
bit5
W
bit4
W
bit3
W
bit2
W
bit1
W
bit0
XXXXXXXXB
W
: Write only
: Undefined
W
X
● While the interval timer is operating:
Specify an interval in the register to which the value compared with the counter value is to be set.
When the settings written to this register match the counter value, the counter is cleared and "1" is set to the
interrupt request flag bit (CNTR: TIR = 1).
If a value is written to the COMR register while the counter is operating, the value takes effect at the next
cycle (after detection of a match).
Note:
The settings of the COMR register, while the interval timer is operating, can be calculated using the
following formula. The gear function, however, affects the instruction cycle.
COMR register value = interval/(count clock cycle × instruction cycle) - 1
145
CHAPTER 7 8-BIT PWM TIMER
● While the PWM timer is operating:
Specify the "H" level width of a pulse in the register to which the value that is compared with the counter
value is to be set.
Until the settings written to this register match the counter value, "H" is output from the PWM pin. When a
match is found, "L" is output until the counter value overflows.
If a value is written to the COMR register while the counter is operating, the value takes effect at the next
cycle (after overflow).
Note:
The settings and cycle of the COMR register, while the PWM timer is operating, can be calculated
using the following formula. The gear function, however, affects the instruction cycle.
COMR register value = duty ratio (%) × 256
PWM wave cycle = count clock cycle × instruction cycle × 256
146
CHAPTER 7 8-BIT PWM TIMER
7.5
Interrupt of 8-bit PWM Timer
An interrupt factor of an 8-bit PWM timer can be a match between the counter value and
the PWM compare register value while interval timer functions are operating. While the
PWM timer functions are enabled, an interrupt request does not occur.
■ Interrupts while Interval Timer Functions are Enabled
When the counter value is incremented from 00 using the selected count clock and matches the PWM
H
compare register (COMR) value, "1" is set to the corresponding interrupt request flag bit (CNTR: TIR).
At this time, if the bit to enable an interrupt request is enabled (CNTR: TIE = 1), an interrupt request
(IRQ9) to the CPU occurs. Write "0" to the TIR bit using the interrupt handling routine to clear the
interrupt request.
The TIR bit is set to "1" when the counter value matches the settings regardless of the value of the TIE bit.
Note:
When a match is found between the counter value and the COMR register value concurrently with the
stop of the counter (CNTR: TPE = 0), the TIR bit is not set.
When the TIR bit is "1", if the TIE bit is changed from disabled to enabled (changed from "0" to "1"),
an interrupt request occurs immediately.
■ Register and Vector Table Related to the Interrupts of an 8-bit PWM Timer
Table 7.5-1 Register and Vector Table Related to the Interrupts of an 8-bit PWM Timer
Interrupt level setting register
Bits to be set
Address of vector table
High-order Low-order
FFE8 FFE9
Interrupt
name
Register
ILR3(007D )
IRQ9
L91(bit3)
L90(bit2)
H
H
H
147
CHAPTER 7 8-BIT PWM TIMER
7.6
Operations of the Interval Timer Functions
This section describes the operations of the interval timer functions of an 8-bit PWM
timer.
■ Operations of the Interval Timer Functions
To make an 8-bit PWM timer operate as an interval timer, set registers as shown in Figure 7.6-1 .
Figure 7.6-1 Setting Interval Timer Functions
bit7
P/TX
0
bit6
bit5
P1
bit4
P0
bit3
TPE
1
bit2
TIR
bit1
OE
bit0
TIE
CNTR
Set an interval (compare value)
COMR
: Used bit
1 : Set "1".
: Set "0".
0
When the counter is activated, the counter is incremented from 00 at the start-up of the selected count
H
clock. When the counter value matches the value set in the COMR register (comparison value), the timer
inverts the level of the PWM pin, clears the counter, sets the interrupt request flag bit (CNTR: TIR = 1),
and starts incrementing again from 00 at the next start-up of the count clock.
H
Figure 7.6-2 shows the operations of an 8-bit PWM timer.
148
CHAPTER 7 8-BIT PWM TIMER
Figure 7.6-2 Operations of an 8-bit PWM Timer
(FF )
(80 )
Comparison value
Comparison value
H
H
Counter value
FFH
80H
00H
Time
Timer cycle
(FFH)
Change of the COMR value
Clear in the program
*
(FFH
80H)
COMR value
TIR bit
TPE bit
OE bit
PWM pin
When the bit to control the output pin (OE) is "0", the pin functions as a
general-purpose I/O port pin (P50).
*:
If the PWM compare register (COMR) value is changed during counter operation, the value
takes effect at the next cycle.
Notes:
• While interval timer functions are enabled (CNTR: TPE = 1), do not change the count clock cycle
(CNTR: P1, P0).
• When 00 is set to the COMR register, the output of the PWM pin is inverted in the cycle of the
H
count clock.
While interval timer functions are enabled, the output level of the PWM pin in the counter stop state
(CNTR: TPE = 0) is at "L" level.
149
CHAPTER 7 8-BIT PWM TIMER
7.7
Operations of the 8-bit PWM Timer Functions
This section describes the operations of the 8-bit PWM timer functions.
■ Operations of the 8-bit PWM Timer Functions
Figure 7.7-1 Setting 8-bit PWM Timer Functions
bit7
P/TX
1
bit6
bit5
P1
bit4
P0
bit3
TPE
1
bit2
TIR
bit1
OE
1
bit0
TIE
CNTR
Set an H-level pulse width (compare value).
COMR
: Used bit
: Unused bit
: Set "1".
1
When the counter is activated, the counter is incremented from 00 at the start-up of the selected count
H
clock. The output (PWM waveform) of the PWM pin is "H" until a match between the counter value and
the value set in the COMR register is found. Once a match is found, the output is "L" until the counter
value overflows (FF →00 ).
H
H
Figure 7.7-2 shows the PWM waveform output to the PWM pin.
150
CHAPTER 7 8-BIT PWM TIMER
Figure 7.7-2 Output Example of the PWM Waveform of 8-bit PWM Timer Functions
When the COMR Register Value is 00H (0% duty ratio):
Counter value
00
FF 00
H
H
H
"H"
"L"
PWM waveform
When the COMR register value is 80H (50% duty ratio):
00
80
H
Counter value
FF 00
H
H
H
"H"
"L"
PWM waveform
When the COMR register value is FFH (99.6% duty ratio):
00
FF 00
H
H
H
Counter value
"H"
PWM waveform
"L"
For one count
Notes:
• While PWM timer functions are enabled (CNTR: TPE = 1), do not change the count clock cycle
(CNTR: P1, P0).
• While PWM timer functions are enabled, the level immediately before the stop is held as the output
level of the PWM pin in the counter stop state (CNTR: TPE = 0).
151
CHAPTER 7 8-BIT PWM TIMER
7.8
States in Each Mode During Operation
This section describes the operations for a move to the sleep mode, a move to the stop
mode, and the occurrence of a suspend request during the operation of an 8-bit PWM
timer.
■ Operations in the Standby Mode and at a Suspension
When the mode is moved to sleep and stop modes, and when a suspend request occurs, the counter value
status in which interval timer functions are enabled is shown in the Figure 7.8-1 , and the counter value
When switched to the stop mode, the counter holds a value and stops. When the stop mode is released by
an external interrupt, the counter starts operation from the held value. Therefore, the first interval and the
first cycle of the PWM waveform are not the values that are set. After the release of the stop mode,
initialize the 8-bit PWM timer.
152
CHAPTER 7 8-BIT PWM TIMER
● While interval timer functions are enabled:
Figure 7.8-1 Operation of the Counter in the Standby Mode and during Suspension (while Interval
Functions are Enabled)
Counter value
Clear by stopping operation
COMR value (FFH)
FFH
00H
Time
Time to wait
Timer cycle
Clear by the program
Stop
request
for oscillation
stabilization
Stopping
operation
Restarting
operation
TIR bit
TPE bit
*
"L" level while operation
is being stopped
PWM pin
(OE = 1)
Sleep
SLP bit
(STBC
register)
Stop
Release of
sleep by IRQ9
STP bit
(STBC
register)
Release of stop by an external interrupt
*: When the bit to specify the pin state (STBC: SPL) of the standby control register is "1", and
the PWM pin is not pulled up, the PWM pin in the stop mode is Hi-Z. When the SPL bit is "0", the
value immediately before the move to the stop mode is held.
153
CHAPTER 7 8-BIT PWM TIMER
● While PWM timer functions are enabled:
Figure 7.8-2 Operation in the Standby Mode and during Suspension (while PWM Timer Functions are
Enabled)
00H
00H
00H
00H
00H
PWM pin
(PWM waveform)
*
The level
immediately
before stop
is held.
TPE bit
Sleep
Stopping
Restarting
operation
operation
SLP bit
(STBC register)
Release of sleep by
something other than
IRQ9 (IRQ9 does
not occur.)
Stop
STP bit
(STBC register)
Time to wait for oscillation
stabilization
Release of stop by an
external interrupt
*:
When the bit to specify the pin state (STBC: SPL) of the standby control register is "1",
and the PWM pin is not pulled up, the PWM pin in the stop mode is Hi-Z. When the SPL
bit is "0", the value immediately before the move to the stop mode is held.
154
CHAPTER 7 8-BIT PWM TIMER
7.9
Notes on Using 8-bit PWM Timer
This section provides notes on using 8-bit PWM timer.
■ Notes on Using 8-bit PWM Timer
● Error
The activation of the counter by a program does not synchronize the start of an increment by the selected
count clock. Therefore, as an error until a match between the counter value and the PWM compare register
(COMR) value is detected, the time may be shortened by up to one cycle of the count clock cycle. Figure
7.9-1 shows an error until the count operation is started.
Figure 7.9-1 Error until the Count Operation is Started
Counter value
Count clock
00H
01H
02H
03H
04H
One cycle
Error Cycle of 00H
Activating the counter
● Notes on setting by a program
•
While interval timer functions or PWM timer functions are enabled (CNTR: TPE = 1), do not change
the count clock cycle (CNTR: P1, P0).
•
If the user wants to switch between the interval timer function and the PWM timer function (CNTR: P/
TX), proceed when the counter is stopped (CNTR: TPE = 0), interrupts are disabled (CNTR: TIE = 0),
and interrupt requests are cleared (CNTR: TIR = 0).
•
When the interrupt request flag bit (CNTR: TIR) is "1" and the bit to enable an interrupt request is
enabled (CNTR: TIE = 1), recovery from interrupt handling is no longer possible. The TIR bit must be
cleared.
•
•
When the counter value matches the COMR register value concurrently with the counter stop (CNTR:
TPE = 0), the TIR bit is not set.
Depending on how to set TPE, P/TX, and OE, the PWM output waveform varies as shown below. Be
careful when using a program to set TPE, P/TX, and OE.
(1) When TPE, P/TX, and OE are set at the same time:
155
CHAPTER 7 8-BIT PWM TIMER
MOV CNTR, #11001010B ; Starts PWM operations, internal clocks, and count operations.
; Enables the PWM output.
1/4 instruction cycle
"H"
Depending on the port
state
"L"
Executing the instruction to enable PWM output
(2) When OE is set after TPE and P/TX are set:
MOV CNTR, #11001000B ; Starts PWM operations, internal clocks, and count operations.
; Uses the general-purpose port.
Check
MOV CNTR, #11001010B ; Enables PWM output.
Check
"H"
Depending on the port state
"L"
Executing the instruction to enable the PWM output
156
CHAPTER 7 8-BIT PWM TIMER
7.10
Program Example for PWM Timer
This section describes program examples of an 8-bit PWM timer.
■ Program Example of Interval Timer Functions
● Processing specifications
•
•
•
5 ms interval timer interrupts occur repeatedly.
The square waveform that inverts at an interval is output to the P50/PWM pin.
The following expression yields the COMR register value for which the interval is about 5 ms when the
top speed of the gear (one instruction cycle = 4/F ) is obtained at an oscillation frequency of 12.5
CH
MHz. The count clock is 64 t
of the internal count clock.
INST
COMR register value = 5 ms/(64 × 4/12.5 MHz) - 1 = 244.1 (0F4 )
H
● Coding example
CNTR
EQU
0022H
0023H
CNTR:3
CNTR:2
007D
; Address of the PWM control register
; Address of the PWM compare register
; Defining the bit to enable the counter operation
; Defining the interrupt request flag bit
; Address of the register to set the interrupt level
; [DATA SEGMENT]
COMR EQU
TPE
TIR
EQU
EQU
EQU
ILR3
INT_V DSEG
ORG
ABS
0FFF8H
WARI1
IRQ9
INT_V ENDS
;------------------------Main program---------------------------------------------------------------------------------
DW
; Setting the interrupt vector
CSEG
; [CODE SEGMENT]
; The stack pointer (SP) and others are assumed to have
been initialized.
:
CLRI
CLRB
MOV
MOV
MOV
; Disabling interrupts
TPE
; Stopping the counter operation
; Setting the interrupt level (level 1)
; Comparison value with the counter value (interval)
ILR3,#11110111B
COMR,#0F4H
CNTR,#00101011B ; Enabling the output of the PWM
; Interval timer operation, selection of 64 t
INST
; Starting the counter operation and enabling the output
of interrupt requests
SETI
:
; Enabling interrupts
;------------------------Interrupt program----------------------------------------------------------------------------
WARI1 CLRB
PUSHW
TIR
A
; Clearing the interrupt request flag
XCHW
A,T
A
; Saving A and T
PUSHW
157
CHAPTER 7 8-BIT PWM TIMER
:
User processing
:
POPW
XCHW
POPW
RETI
ENDS
A
A,T
A
; Restoring A and T
; --------------------------------------------------------------------------------------------------------------------
158
CHAPTER 7 8-BIT PWM TIMER
■ Program Example of PWM Timer Functions
● Processing specifications
•
•
•
A PWM wave with a duty ratio of 50% is generated. The duty ratio is then changed to 25%.
No interrupt occurs.
When the count clock is 16 t
of an internal count clock, the cycle of the PWM wave is 16 × 4/12.5
INST
MHz × 256 = 1.3107 ms, which occurs when the top speed of the gear (one instruction cycle = 4/F ) is
CH
obtained at an oscillation frequency of 12.5 MHz.
•
The COMR register value with a duty ratio of 50% is shown below.
COMR register value = 50/100 × 256 = 128 (080 )
H
● Coding example
CNTR EQU
COMR EQU
TPE EQU
0022H
0023H
CNTR:3
; Address of the PWM control register
; Address of the PWM compare register
; Defining the bit to enable the counter operation
;------------------------Main program---------------------------------------------------------------------------------
CSEG
:
; [CODE SEGMENT]
CLRB
MOV
TPE
; Stopping the counter operation
COMR,#80H
; Specification of the H-level width of a pulse, 50% duty
ratio
MOV
CNTR,#10011010B ; PWM timer operation, selection of 16 t
INST
; Starting the counter operation, clearing the interrupt
request flag
; Enabling the output of the PWM pin, disabling the output
of interrupt requests
:
:
MOV
COMR,#40H
; Changing the duty ratio to 25% (Takes effect at the next
cycle of the PWM wave.)
:
ENDS
;---------------------------------------------------------------------------------------------------------------------
END
159
CHAPTER 7 8-BIT PWM TIMER
160
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.1
Overview of 8/16-bit Capture Timer/Counter
The 8/16-bit capture timer/counter consists of two 8-bit counters (timer 0 and timer 1).
These counters can be used separately (8-bit mode) or in combination (16-bit mode).
Timer 0 provides seven internal count clocks. This timer can select the interval timer
function or counter function. The interval timer function increments the counter value in
synchronization with one of the seven internal clocks. The counter function increments
the counter value according to the clock to be input to an external pin. Timer 0 can
output square waves of any frequency according to outputs from the interval timer and
counter.
Timer 1 provides seven internal count clocks. This timer can output square waves of
any frequency but can use only the interval timer function that increments the timer
value in synchronization with one of the seven internal counter clocks. For the 16-bit
mode, timer 0 and timer 1 are connected in series to serve as a 16-bit timer.
■ Interval Timer Function
The interval timer function generates interrupt requests repeatedly at any time interval.
This function can also invert the output level of P34/TO/INT10 pin per time interval and output square
waves of any frequency.
•
In the 8-bit mode, the interval timer function operates as two independent timers: timer 0 (8-bit capture
8
timer/counter) and timer 1 (8-bit timer). Interval timer operation from each count clock cycle to a 2
times cycle is possible.
•
•
The interval timer function can select and output square waves to the TO pin according to the timer 0 or
1 output.
In the 16-bit mode, the interval timer function operates as a 16-bit capture timer/counter in which timer
0 is concatenated as the lower counter and timer 1 is concatenated as the upper counter. Interval timer
16
operation from the count clock cycle to the 2 times cycle is possible.
•
•
The count clock can be selected from the seven internal clock cycles (if timer 0 selects an external
clock, the interval timer function operates as the capture/counter function).
The timer 0 output cycle can be used as the clock for starting A/D converters continuously or as the 8-
bit PWM timer count clock.
162
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.1-1 to Table 8.1-3 show the interval time and square wave output range in each operation mode.
Table 8.1-1 Timer 0 Interval Time and Square Wave Output Range in 8-bit Mode
Count clock cycle
2t
Interval time
Square wave output range (Hz)
9
2
10
2t
to 2 t
1/ (2 t
) to 1/ (2 t
)
)
)
)
)
)
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
2
10
3
11
4t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
INST
INST
INST
4
12
5
13
16t
64t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
6
14
7
15
Internal count clock
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
7
15
8
16
128t
256t
512t
1t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
8
16
9
17
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
9
17
10
18
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
)
INST
INST
8
9
External clock
1t to 2 t
1/ (2t ) to 1/ (2 t
)
ext
ext
ext
ext
ext
Table 8.1-2 Timer 1 Interval Time and Square Wave Output Range in 8-bit Mode
Count clock cycle
2t
Interval time
Square wave output range (Hz)
9
2
10
2t
to 2 t
1/ (2 t
) to 1/ (2 t
)
)
)
)
)
)
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
2
10
3
11
4t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
INST
INST
INST
4
12
5
13
16t
64t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
6
14
7
15
Internal count clock
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
7
15
8
16
128t
256t
512t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
8
16
9
17
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
9
17
10
18
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
)
INST
INST
163
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.1-3 Interval Time and Square Wave Output Range in 16-bit Mode
Count clock cycle
2t
Interval time
Square wave output range (Hz)
17
2
18
2t
to 2 t
1/ (2 t
) to 1/ (2 t
)
)
)
)
)
)
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
INST
2
18
3
19
4t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
INST
INST
INST
EXT
INST
INST
INST
INST
INST
INST
4
20
5
21
16t
64t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
6
22
7
23
Internal count clock
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
7
23
8
24
128t
256t
512t
1t
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
INST
INST
INST
8
24
9
25
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
9
25
10
26
2 t
to 2 t
1/ (2 t
) to 1/ (2 t
)
INST
INST
16
17
External clock
1t
to 2 t
1/ (2t
) to 1/ (2 t
)
EXT
EXT
EXT
EXT
t
t
: Instruction cycle (this cycle is affected by the clock mode, etc.)
INST
: External clock cycle (1t
greater than or equal to 4t
)
INST
EXT
EXT
Note:
Example of calculating interval time and square wave frequency
If the oscillation (F ) is set to 12.5 MHz, the timer 0 data register (TDR0) value is set to DD (221),
CH
H
and the count clock cycle is set to 2t
8-bit mode operation, the interval time of timer 0 and the
INST
square wave frequency output from the TO pin when the interval timer function is operated
continuously without modifying the TDR0 register value are calculated from the following expressions:
However, the values calculated from these expressions are valid when the highest speed clock of the
normal mode (CS1, CS0 = 11 , 1 instruction cycle = 4/F ) is selected according to the system clock
B
CH
control register (SYCC).
Interval time = (2 × 4/FCH) × (TDR0#1 register value + 1)
= (8/12.5 MHz) × (221 + 1)
142.1 µs
Output frequency = FCH/(2 × 8 × (TDR0#1 register value + 1))
= 12.5 MHz/(16 × (221 + 1))
3.53 kHz
164
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
■ Counter Function
The counter function counts the falling edges of the external clocks input to the P33/EC external pin. The 8/
16-bit capture timer/counter can operate independently because the EC pin acts as an external clock input
pin. Only timer 0 can select the external clock. The counter function operates using timer 0 with the 8-bit
mode or with the 16-bit mode.
•
The counter function counts the number of edges of the external clocks selected by the count clock
selection bit (CINV) of the timer 0 control register (TCR0). When the number of edges equals the
setting value, the counter function generates an interrupt request and inverts the output level of the
square wave output pin.
8
•
In timer 0 for the 8-bit mode, a count operation up to 2 is possible.
16
•
•
In the 16-bit mode, a count operation up to 2 is possible.
Inputting an external clock whose cycle is constant enables the counter to be used as a device whose
function is similar to an interval timer.
165
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.2
Configuration of 8/16-bit Capture Timer/Counter
The 8/16-bit capture timer/counter consists of the following seven blocks:
• Count clock selectors 0/1
• Counter circuits 0/1
• Square wave output control circuit
• Timer 0/1 data registers (TDR0, TDR1)
• Timer 0/1 control registers (TCR0, TCR1)
• Capture data registers (TCPL, TCPH)
• Timer output control register (TCR2)
■ Block Diagram of 8/16-bit Capture Timer/Counter
Figure 8.2-1 Block Diagram of 8/16-bit Capture Timer/Counter
TSTR0 TCS00 TCS01 TCS02 CINV T0IEN TFCR0 TIF0
TCR0
IRQ3
TCCR
3
RESV EDGS0 EDGS1 TCMSK CCMSK
CFCLR
CPIF
CPIEN
Counter clear
mask (capture clr)
Counter clear mask (identity clr)
Counter clear
IRQ4
Capture latch
P34/TO/
INT10
P33/EC
Q
Pin
Pin
M
P
X
TFF
CK
CLR 8-bit counter "L"
CO
EQ
CK6
to
CK0
Comparator
LOAD comparator latch
TCPL
TDR0
TDR1
Capture register "L"
Data register "L"
Capture register "H"
TCPH
Data register "H"
LOAD comparator latch
EQ
Comparator
CK6
to
CLR
CK
M
P
X
8-bit counter "H"
CK0
8-bit mode
3
TCR1
TSTR1
TCS10 TCS11 TCS12
T1IEN TFCR1 TIF1
Port output enable
Timer0, Timer1
output selection
PEN TSEL
TCR2
166
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● Count clock selectors 0/1
Circuits that select input clocks. In timer 0 for the 8-bit mode or in the 16-bit mode, count clock selector 0/
1 can select seven internal clocks and one external clock. In timer 1 for the 8-bit mode, the selector can
select only seven internal clocks.
● Counter circuits 0/1
Counter circuit 0 and counter circuit 1 each consist of an 8-bit counter, a comparator, a comparator data
latch, and data registers (TDR0, TDR1).
The 8-bit counter is incremented according to the selected count clock and clock edge (rising/falling). The
comparator compares the counter value with the comparator data latch value. When these values match, the
counter is cleared and the data register value is set in (loaded to) the comparator data latch.
In the 8-bit mode, counter circuits 0 and 1 operate independently as timer 0 and timer 1, respectively. In the
16-bit mode, counter circuits 0 and 1 operate as the 16-bit counter in which counter circuit 0 is
concatenated as lower 8 bits and counter circuit 1 is concatenated as higher 8 bits.
● Square wave output control circuit
When the comparator detects that the counter value matches the comparator data latch value in the 8- or 16-
bit mode, an interrupt request is generated. In this case, if square wave output is allowed, the corresponding
output control circuit inverts the output of the square wave output pin.
● Timer 0/1 data registers (TDR0, TDR1)
TDR0 and TDR1 are used to set the data to be compared with each 8-bit counter value at write.
● Timer 0/1 control registers (TCR0, TCR1)
TCR0 and TCR1 are used to select functions, allow and prohibit operations, control interrupts, and check
interrupt states.
● 8/16-bit capture timer/counter interrupt
IRQ3: If the interrupt request output is allowed when the counter value equals the value set in the data
register in the interval timer or counter function, an IRQ3 interrupt request is generated. (In timer 0
for the 8-bit mode or in the 16-bit mode, the interrupt request output is allowed when TCR0:
T0IEN=1. In timer 1 for the 8-bit mode, the interrupt request output is allowed when TCR1: T1IEN =1.)
● 8/16-bit capture counter interrupt
IRQ4: If the interrupt request output is allowed each time a capture input edge is detected, an IRQ4
interrupt request is generated. (In timer 0 for the 8-bit mode or in the 16-bit mode, the interrupt
request output is allowed when TCCR: TCEN=1.)
● Capture data registers (TCPL, TCPH)
TCPL and TCPH store the number of events detected in the capture mode.
When capture data is read in the timer mode, the counter value is also read.
● Timer output control register (TCR2)
TCR2 is used to allow and prohibit square wave output and select timer 0 output/timer 1 output.
167
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.3
Pins of 8/16-bit Capture Timer/Counter
This section provides pins of 8/16-bit capture timer/counter and a block diagram for
these pins.
■ Pins of 8/16-bit Capture Timer/Counter
8/16-bit capture timer/counter pins include P33/EC and P34/TO/INT10.
● P33/EC pin
The P33/EC pin shares functions of the general-purpose I/O port (P33) and the external clock for the timer
or capture input pin (EC).
EC:
When external clock input is selected (TCR0: TCS02, TCS01, TCS00=111 ) in timer 0 for the 8-bit
B
mode or in the 16-bit mode, the clocks input to this pin are counted. In the capture function, this pin is
also used as an input pin. When using this pin as the EC pin, set 0 in the port data 3-direction register
(DDR3: bit3) and set the output transistor to OFF to enable the EC pin to be used as an input port.
● P34/TO/INT10 pin
The P34/TO/INT10 pin shares functions of the general-purpose I/O port (P34) and the square wave output
pin for the timer (TO). It also shares a function of the input pin for external interrupt 1 (INT10).
TO:
In timer 0 or 1 (switching allowed) for the 8-bit mode or in the 16-bit mode, a square wave is output
from this pin. If square wave output is enabled (TCR2: PEN = 1), the P34/TO/INT10 pin automatically
functions as an output pin without reference to the port 3-direction register (DDR3: bit4); it functions as
the TO pin. The TCR2: TSEL is used to select whether timer 0 output or timer 1 output is to be used.
168
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
■ Block Diagram for 8/16-bit Capture Timer/Counter Pins
Figure 8.3-1 Block Diagram for 8/16-bit Capture Timer/Counter Pins
External interrupt allowed
INT10
EC
P34/TO/INT10
P33/EC
PDR
Stop mode
PDR read
Resource input
(SPL = 1)
Pull-up resistor
Resource
output
Resource output
available
enable
PDR read
(At read-modify-write)
P-ch
N-ch
Output
latch
PDR write
DDR write
Pin
P33/EC
DDR
P34/TO/INT10
Stop mode
(SPL = 1)
PUL read
PUL
PUL write
Note:
When "pull-up resistor available" is selected in the pull-up setting register, the pin state in the stop
mode (SPL = 1) becomes high (pull-up state), not Hi-Z. During the reset, however, pull-up becomes
ineffective and the pin state becomes Hi-Z.
169
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4
Registers of 8/16-bit Capture Timer/Counter
This section shows registers of 8/16-bit capture timer/counter.
■ Registers of 8/16-bit Capture Timer/Counter
Figure 8.4-1 Registers of 8/16-bit Capture Timer/Counter
TCCR (capture control register)
Initial value
Address
0019
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV 00000000
H
B
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR1 (timer 1 control register)
Address
001A
bit7
TIF1
R
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
TFCR1 T1IEN
TCS12 TCS11 TCS10 TSTR1 000-0000
H
B
R/W
R/W
R/W
R/W
R/W
R/W
TCR0 (timer 0 control register)
Address
bit7
TIF0
R
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
001B
TFCR0 T0IEN
CINV
R/W
TCS02 TCS01 TCS00 TSTR0 00000000
H
B
R/W
R/W
R/W
R/W
R/W
R/W
TDR1 (timer 1 data register)
Address
001C
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R/W
Initial value
XXXXXXXX
H
B
B
B
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR0 (timer 0 data register)
Address
001D
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
XXXXXXXX
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCPH (capture data register H)
Address
001E
bit7
bit6
bit5
R
bit4
R
bit3
R
bit2
R
bit1
R
bit0
R
Initial value
XXXXXXXX
H
R
R
TCPL (capture data register L)
Address
Initial value
XXXXXXXX
bit7
R
bit6
R
bit5
R
bit4
R
bit3
R
bit2
R
bit1
R
bit0
R
001F
H
TCR2 (timer output control register)
Address
0020
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
PEN TSEL ------00
B
H
R/W
R/W
R/W : Readable/Writable
: Read only
: Undefined
: Unused
R
X
170
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.1
Capture Control Register (TCCR)
The capture control register (TCCR) is used to select functions and detection edges,
control interrupts, and check interrupt states in timer 0 for the 8-bit mode of the 8/16 bit
capture timer/counter or in capture mode (16-bit mode).
■ Capture Control Register (TCCR)
Figure 8.4-2 Capture Control Register (TCCR)
Address
0019H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CPIF CFCLR CPIEN CCMSK TCMSK
RESV
00000000B
EDGS1 EDGS0
R
R/W R/W R/W R/W R/W R/W R/W
RESV
0
Capture input selection bit
Operation is not affected at all.
1
EDGS1 EDGS0
Capture mode enable/edge detection selection bit
Capture input prohibition
0
0
1
0
1
0
Operation in timer/counter mode
Falling edge selection
Rising edge selection
Operation in capture mode
Selection of both falling
and rising edges
1
1
TCMSK
Compare match counter clear mask bit
0
1
The counter is cleared per compare match.
The counter is not cleared at compare match.
CCMSK
Counter clear mask bit (at capture operation)
The counter is cleared when a capture edge is detected.
The counter is not cleared when a capture edge is detected.
0
1
CPIEN
Capture interrupt request enable bit
Capture interrupt request output is prohibited.
Capture interrupt request output is allowed.
0
1
CFCLR
Capture edge detection flag clear bit
Not affected (at read, always "0")
0
1
The capture edge detection flag is cleared.
Capture edge detection flag bit
No capture edge was detected.
CPIF
0
1
A capture edge was detected.
R/W : Readable/Writable
R
: Read only
: Initial value
171
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.4-1 Explanation of Functions of Each Bit in Capture Control Register (TCCR)
Bit name
Function
•
This bit is set to "1" when the edge specified by EDGS1 and EDGS0 is
detected.
An interrupt request is output when this bit and the capture interrupt request
enable bit (CPIEN) are "1".
CPIF:
Capture edge detection
flag bit
bit7
CFCLR:
Capture edge detection
flag clear bit
•
•
This bit is used to clear the capture edge detection flag.
When this bit is "1" at write, the capture edge detection flag is cleared. When
"0", the capture edge detection flag is not affected (remains unchanged).
bit6
bit5
bit4
bit3
CPIEN:
Capture interrupt request
enable bit
•
•
This bit is used to allow and prohibit interrupt request output to the CPU.
An interrupt request is output when this bit and the capture edge detection flag
bit (CPIF) are "1".
CCMSK:
Counter clear mask bit
(at capture operation)
•
•
The counter state when a capture match is detected is set.
When this bit is "0", the counter is cleared. When this bit is "1", the counter is
not cleared.
TCMSK:
Compare match counter
clear mask bit
•
•
The counter state when a compare edge is detected is set.
When this bit is "0", the counter is cleared. When this bit is "1", the counter is
not cleared.
•
•
These bits are used to allow and prohibit the capture function and select
capture edges.
When using the 8/16-bit capture timer/counter in the capture mode, set these
EDGS1 and EDGS0:
Capture mode enable/
edge detection selection
bits
bit2,
bit1
bits to a value other than "00 ".
B
•
•
When the edge set by these bits is input, the capture edge detection flag bit
(CPIF) is set to "1".
Even if this bit is set to "0" or "1", the operation is not affected. The value
previously written becomes the read value.
bit0
RESV: Reserved bit
172
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.2
Timer 0 Control Register (TCR0)
The timer 0 control register (TCR0) is used to select functions, allow and prohibit
operation, control interrupts, and check interrupt states in timer 0 for the 8-bit mode of
the 8/16-bit capture timer/counter or in the 16-bit mode. Even if only timer 0 is used in
the 8-bit mode, the timer 1 control register (TCR1) must be initialized.
■ Timer 0 Control Register (TCR0)
Figure 8.4-3 Timer 0 Control Register (TCR0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
TCS00 TSTR0
R/W R/W R/W
bit0
Address
001B
Initial value
00000000
TIF0 TFCR0 T0IEN CINV TCS02 TCS01
H
B
R
R/W
R/W
R/W
R/W
TSTR0
Timer start bit
0
1
The counter operation is stopped.
The counter is cleared and increment starts.
TCS02 TCS01 TCS00
Clock source selection bits (oscillation: 12.5 MHz)
2tINST [0.64 µs]
0
0
0
0
0
1
0
1
4tINST [1.28 µs]
16tINST [5.12 µs]
64tINST [20.48 µs]
128tINST [40.96 µs]
256tINST [81.92 µs]
512tINST [163.84 µs]
External clock
0
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
tINST : Instruction cycle (Affected by the clock mode and others.)
CINV
Count clock selection bit
The counter is incremented at the falling edge of a selected
0
1
clock source.
The counter is incremented at the rising edge of a selected
clock source.
T0IEN
Interrupt request enable bit
Interrupt request output is prohibited.
Interrupt request output is allowed.
0
1
TFCR0
Compare match detection flag clear bit
Not affected (at read, always "0")
0
1
The compare match detection flag is cleared.
TIF0
Compare match detection flag bit
No compare match has occurred.
A compare match occurred.
0
1
R/W : Readable/Writable
R
: Read only
: Initial value
173
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.4-2 Explanation of Functions of Each Bit in Timer 0 Control Register (TCR0)
Bit name
Function
•
•
8-bit mode
When the counter value of timer 0 matches the value (comparator data latch)
set in the timer 0 data register (TDR0), this bit is set to "1".
16-bit mode
When the counter value of timer 0 matches the value set in TDR0 and the
counter value of timer 1 matches the value set in TDR1, this bit is set to "1".
An interrupt request is output when this bit and the interrupt request enable bit
(T0IEN) are "1".
TIF0:
Compare match
detection flag bit
bit7
•
•
TFCR0:
Compare match
detection flag clear bit
This bit is used to clear the compare match detection flag bit (TIF0). When this
bit is set to "1", the compare match detection flag is cleared. The flag is not
affected even if this bit is set to "0".
bit6
bit5
T0IEN:
Interrupt request enable
bit
•
•
This bit is used to allow and prohibit interrupt request output to the CPU.
An interrupt request is output when this bit and the interrupt request enable bit
(T0IEN) are "1".
•
This bit is used to select whether to increment the counter at the rising or
falling edge of a clock. When this bit is "0", the counter is incremented at the
falling edge of the clock. When "1", the counter is incremented at the rising
edge.
CINV:
Count clock selection bit
bit4
•
•
•
These bits are used to select the count clocks to be supplied to the counter.
Select one clock from the seven internal clocks and one external clock.
When these bits are 111 , the external clock is input. In this case, timer 0 can
bit3
to
bit1
TCS02, TCS01, TCS00:
Clock source selection
bits
B
operate as the counter function.
Note:
When external clock input is selected (TCS02, TCS01, TCS00 = 111 ), the
B
P33/EC pin must be set in the input port.
•
•
This bit is used to start and stop the counter.
When this bit is set to "1", the counter is cleared and incremented according to
the selected count clock. When this bit is set to "0", the counter stops its
operation.
TSTR0:
Timer start bit
bit0
•
When the timer is started (TSTR0 = 0 →1) in the 16-bit mode, the counters of
both timer 0 and timer 1 are cleared.
Note:
When using only timer 0 of the 8/16-bit capture timer/counter in the 8-bit mode, set a value other than
111 in the count clock selection bits (TCS12, TCS11, TCS10) of the timer 1 control register (TCR1).
B
Using timer 0 with setting value TCS12, TCS11, TCS10 = 111 results in a malfunction.
B
174
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.3
Timer 1 Control Register (TCR1)
The timer 1 control register (TCR1) is used to select functions, allow and prohibit
operation, control interrupts, and check interrupt states in timer 1 for the 8-bit mode of
the 8/16-bit capture timer/counter. When used in the 16-bit mode, TCR1 is controlled by
the timer 0 control register (TCR0), but TCR1 setting is required.
■ Timer 1 Control Register (TCR1)
Figure 8.4-4 Timer 1 Control Register (TCR1)
Address
bit7
TIF1
R
bit6 bit5
TFCR1 T1IEN
R/W R/W
bit4 bit3 bit2
bit1
bit0
Initial value
001AH
TCS12 TCS11
TCS10 TSTR1
000-0000B
R/W R/W R/W R/W
Timer start bit
TSTR1
0
1
The counter operation is stopped.
The counter is cleared and increment is started.
TCS12 TCS11 TCS10
Clock source selection bits (oscillation: 12.5 MHz)
2tINST [0.64 µs]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4tINST [1.28 µs]
16tINST [5.12 µs]
64tINST [20.48 µs]
128tINST [40.96 µs]
256tINST [81.92 µs]
512tINST [163.84 µs]
16-bit mode
tINST : Instruction cycle (Affected by the clock mode and others.)
T1IEN
Interrupt request enable bit
Interrupt request output is prohibited.
Interrupt request output is allowed.
0
1
TFCR1
Compare match detection flag clear bit
Not affected (at read, always "0")
0
1
The compare match detection flag is cleared.
TIF1
0
Compare match detection flag bit
A compare match has not occurred.
A compare match has occurred.
1
R/W : Readable/Writable
R
: Read only
: Initial value
175
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.4-3 Explanation of Functions of Each Bit in Timer 1 Control Register (TCR1)
Bit name
Function
•
•
This bit is set to "1" when the counter value of timer 1 matches the value
(comparator data latch) set in the timer 1 data register (TDR1).
An interrupt request is output when this bit and the interrupt request enable bit
(T1IEN) are "1".
TIF1:
Compare match
detection flag bit
bit7
bit6
Note:
In the 16-bit mode, the TIF0 bit of TCR0 is valid. The TIF1 bit is unrelated to
operation.
TFCR1:
Compare match
detection flag clear bit
•
This bit is used to clear the compare match detection flag bit (TIF1). When this
bit is set to "1", the compare match detection flag is cleared. The flag is not
affected even if this bit is set to "0".
T1IEN:
Interrupt request enable
bit
•
•
This bit is used to allow and prohibit interrupt request output to the CPU.
An interrupt request is output when this bit and the interrupt request enable bit
(T0IEN) are "1".
bit5
bit4
•
•
This bit is undefined at read.
At write, this bit does not affect operation.
Not used
•
•
•
These bits are used to select the count clocks to be supplied to the counter.
Of seven internal clocks, select one.
bit3
to
bit1
TCS12, TCS11, TCS10:
Clock source selection
bits
When 111 is written to these bits, timer 1 operates as the 16-bit mode.
B
Note:
In the 16-bit mode, the TCS02, TCS01, and TCS00 bits are valid. The TCS12,
TCS11, and TCS10 bits are used to select the 16-bit mode only.
•
•
This bit is used to start and stop the counter.
When this bit is set to "1", the counter is cleared and incremented according to
the selected count clock. When this bit is set to "0", the counter stops its
operation.
TSTR1:
Timer start bit
bit0
•
In the 16-bit mode, only the TSTR0 bit can be used to start the timer. The
TSTR1 bit is unrelated to operation.
Note:
When using timer 1 in the 16-bit mode, write 111 to the TCS12, TCS11, and TCS10 bits and then
B
control timer 1 with TCR0.
176
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.4
Timer Output Control Register (TCR2)
The timer output control register (TCR2) is used to allow and prohibit the square wave
output of the 8/16-bit capture timer/counter and select timer 0 output and timer 1 output.
■ Timer Output Control Register (TCR2)
Figure 8.4-5 Timer Output Control Register (TCR2)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
0020H
Initial value
------00B
TSEL
PEN
R/W R/W
Timer output selection bit
TSEL
Timer 0 output in the 8-bit mode or output in the 16-bit mode
is selected.
0
1
Timer 1 output in the 8-bit mode is selected.
Port output enable bit
PEN
0
The P34/TO/INT10 pin acts as the general-purpose port (P34).
R/W : Readable/Writable
: Initial value
The P34/TO/INT10 pin acts as the square wave output pin
of the 8/16-bit capture timer/counter.
1
Table 8.4-4 Explanation of Functions of Each Bit in Timer Output Control Register (TCR2)
Bit name
Function
bit7
to
bit2
•
•
At read, the values of these bits are undefined.
At write, these bits do not affect operation.
Unused bits
•
When this bit is "0", the P34/TO/INT10 pin acts as the general-
purpose port (P34). When "1", it acts as the square wave output pin
(TO).
PEN:
Port output enable bit
bit1
bit0
•
When this bit is "0", timer 0 output in the 8-bit mode or output in the
16-bit mode is selected. In this case, data is output from the TO pin.
When "1", timer 1 output in the 8-bit mode is selected. In this case,
data is also output from the TO pin.
TSEL:
Timer output selection bit
177
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.5
Timer 0 Data Register (TDR0)
The timer 0 data register (TDR0) is used to set the timer 0 value in the 8-bit mode of the
8/16-bit capture timer/counter or the interval timer value (interval timer function) or
counter value (counter function) of the lower 8 bits in 16-bit mode.
■ Timer 0 Data Register (TDR0)
The values set in this register are compared with those set in the counter. Figure 8.4-6 shows the bit
structure of timer 0 data register (TDR0).
Figure 8.4-6 Timer 0 Data Register (TDR0)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0 Initial value
001D
XXXXXXXX
B
H
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
: Undefined
X
● 8-bit mode (timer 0)
The values set in this register are compared with those set in the counter. When the interval timer function
is used, an interval timer value is set. When the counter function is used, the count value to be detected is
set. When the count operation is allowed (TCR0: TSTR0 = 0 →1), the value in TDR0 is set in (loaded to)
the comparator data latch and the counter is incremented.
When the values in the comparator data latch match those in the counter as a result of the increment, the
values in the TDR0 are reset in the comparator data latch, the counter is cleared, and the count operation is
continued.
The comparator data latch is reset when a match is detected, thus, the values written to the TDR0 when the
counter is in operation become valid from the next cycle (after match detection).
Note:
The values set in TDR0 when the interval timer is in operation can be calculated from the expression
shown below. However, the instruction cycle is affected by the clock mode and gear function.
Values set in TDR0 = interval time/(count clock cycle × instruction cycle) - 1
178
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● 16-bit mode
The values in TDR0 are compared with the counter values in the lower 8 bits of the 16-bit timer.
When the interval timer function is used, the lower 8 bits of the interval time are set. When the counter
function is used, the lower 8 bits of the count value to be detected are set. The values in TDR0 are loaded to
the lower 8 bits of the comparator data latch when matching the counter values of the 16-bit timer or when
the count operation is started. The values written to TDR0 when the 16-bit counter is in operation become
valid after match detection.
For the values set in TDR1 when the interval timer function is used, see Section "8.4.6 Timer 1 Data
179
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.6
Timer 1 Data Register (TDR1)
The timer 1 data register (TDR1) is used to set the timer 1 value in the 8-bit mode of the
8/16-bit capture timer/counter or the interval timer value (interval timer function) or
counter value (counter function) of the higher 8 bits in the 16-bit mode.
■ Timer 1 Data Register (TDR1)
The values set in this register are compared with those set in the counter.
Figure 8.4-7 shows the bit structure of timer 1 data register (TDR1).
Figure 8.4-7 Timer 1 Data Register (TDR1)
Address
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
001C
XXXXXXXX
H
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
: Undefined
X
● 8-bit mode (timer 1)
The values set in this register are compared with those set in the counter. When the interval timer function
is used, an interval timer value is set. When the counter function is used, the count value to be detected is
set. The values in TDR1 are reset in (loaded to) the comparator data latch when they match the values in
the counter or when the count operation is started.
The values written to TDR1 when the counter is operating become valid from the next cycle (after match
detection).
Note:
The values set in TDR1 when the interval timer is operating can be calculated from the expression
shown below. However, the instruction cycle is affected by the clock mode and gear function.
Values set in TDR1 = interval time/(count clock cycle × instruction cycle) - 1
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● 16-bit mode
The values in TDR1 are compared with the counter values in the higher 8 bits of the 16-bit timer.
When the interval timer function is used, the higher 8 bits of the interval time are set. When the counter
function is used, the higher 8 bits of the count value to be detected are set. The values in TDR1 are loaded
to the higher 8 bits of the comparator data latch when matching the counter values of the 16-bit timer or
when the count operation is started. The values written to TDR1 when the 16-bit counter is operating
become valid after match detection. In the 16-bit mode, the count operation is controlled by the timer 0
control register (TCR0).
Note:
The values set in TDR0 and TDR1 when the interval function is used can be calculated from the
expression shown below. However, the instruction cycle is affected by the clock mode and gear
function.
16-bit data value = interval time/(count clock cycle × instruction cycle) - 1
The higher 8 bits of the 16-bit data value are set in TDR1 and the lower 8 bits are set in TDR0.
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.7
Capture Data Registers H and L (TCPH and TCPL)
The capture data register H (TCPH) stores the number of events of the higher 8 bits in
the 16-bit capture mode of the 8/16-bit capture timer/counter.
The capture data register L (TCPL) stores the number of events in the 8-bit capture
mode of the 8/16-bit capture timer/counter or the number of events of the lower 8 bits in
the 16-bit capture mode.
In the read operation in the timer/counter mode, counter values are read.
■ Capture Data Registers H and L (TCPH and TCPL)
The number of events detected in the capture mode is stored in TCPH and TCPL. Data cannot be written to
these registers because the registers are read-only.
Figure 8.4-8 shows the bit structures of capture data registers H and L.
Figure 8.4-8 Bit Structures of Capture Data Registers H and L (TCPH and TCPL)
Address
Initial value
bit7
R
bit6 bit5
bit4 bit3
bit2
R
bit1
R
bit0
R
001E
H
TCPH
TCPL
XXXXXXXX
B
B
R
R
R
R
R
R
R
R
001F
H
XXXXXXXX
R
R
R
R
R
X
: Read only
: Undefined
182
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.5
8/16-bit Capture Timer/Counter of Interrupts
The 8/16-bit capture timer/counter generates an interrupt if the values set in a data
register match those set in the counter when the interval timer or counter is operating.
The interrupt level is IRQ3 when generated by the 8/16-bit capture timer/counter. When
the capture is in operation and a capture edge is detected, IRQ4 is generated.
■ 8/16-bit Capture Timer/Counter of Interrupts
Table 8.5-1 shows the interrupt request flag bit, interrupt flag clear bit, interrupt request enable bit, and the
cause of the 8/16-bit capture timer/counter interruption.
Table 8.5-1 Interrupt Control Bits and the Cause of the 8/16-bit Capture Timer/Counter Interrupt
8-bit mode
16-bit mode
Capture mode
Timer 0 or timer 0 +
timer 1
Timer 0
Timer 1
Timer 0 + timer 1
Interrupt request flag bit
Interrupt flag clear bit
TCR0 : TIF0
TCR0 : TFCR0
TCR0 : T0IEN
TCR1 : TIF1
TCR1 : TFCR1
TCR1 : T1IEN
TCR0 : TIF0
TCR0 : TFCR0
TCR0 : T0IEN
TCCR : CPIF
TCCR : CFCLR
TCCR : CPIEN
Interrupt request enable bit
The values in
TDR0 match
those in the 8-bit
counter.
The values in
TDR1 match
those in the 8-bit
counter.
The values in
TDR0 and TDR1
match those in the
16-bit counter.
A capture edge is
detected.
Interrupt cause
In the 8-bit mode, timer 0 and timer 1 independently generats the interrupt request for 8/16-bit capture
timer/counter. In the 16-bit mode, timer 0 generates the interrupt request. All basic operations are the same.
Timer 0 interrupt operation in the 8-bit mode is explained here.
● Timer 0 interrupt operation in the 8-bit mode
The counter value is incremented according to the selected count clock, starting at 00 . When the counter
H
value matches the value set in the comparator data latch (timer 0 data register (TDR0)) corresponding to the
timer 0 data register (TDR0), the compare match detection flag bit (TCR0: TIF0) is set to "1".
In this case, when the interrupt request flag bit is allowed (when TCR0: T0IEN = 1), timer 0 generates an
interrupt request (IRQ3) to the CPU. Set the TFCR0 bit to "1" and clear the interrupt request with the
interrupt processing routine.
When the counter value matches the value set in the comparator data latch, the TIF0 bit is set to "1"
regardless of the TFCR0 bit value.
In the 8-bit mode, timer 0 and timer 1 operate independently, and because they generate the same interrupt
request (IRQ3), determination of the interrupt request flag by software may be required.
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Notes:
•
When the counter value matches the TDR0 value and at the same time the counter stops (TCR0:
TSTR0 = 0), the TIF0 bit is not set.
If the T0IEN bit is set to "1" (enable) when the TIF0 bit is "1", an interrupt request is generated
immediately.
•
If the compare register value is 0000 or 00 , the 8/16-bit capture timer/counter cannot generate an
H
H
interrupt. Therefore, when using interrupts, set a value greater than or equal to 0001 or 01 . The 8/
H
H
16-bit capture timer/counter also cannot generate an interrupt if the counter function detects the
0000 or 00 width.
H
H
■ Register and Vector Table Related to 8/16-bit Capture Timer/Counter of Interrupts
Table 8.5-2 Register and Vector Table Related to 8/16-bit Capture Timer/counter of Interrupts
Interrupt level setting register
Register Setting bit
Vector table address
Interrupt
name
Higher
Lower
Timer/counter
function
ILR1 (007B )
FFF4
FFF5
IRQ3
IRQ4
L31 (bit7)
L41 (bit1)
L30 (bit6)
L40 (bit0)
H
H
H
Capture function
ILR2 (007C )
FFF2
FFF3
H
H
H
184
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.6
Explanation of Operations of Interval Timer Functions
This section describes the interval timer function operation of the 8/16-bit capture timer/
counter.
■ Interval Timer Function Operation
● 8-bit mode
To operate timer 0 as the interval timer function in the 8-bit mode, the function must be set as shown in
Figure 8.6-1 Setting of Interval Timer Function (Timer 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CFCLR CPIEN
EDGS0
TCCR
TCR1
TCR0
TCR2
TDR0
CPIF
CCMSK TCMSK EDGS1
RESV
Setting of 00
TIF1
TFCR1
TCS11 TCS10
T1IEN
TCS12
TSTR1
Setting of a value
other than 111
TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0
Setting of a value
other than 111
PEN
TSEL
Setting of interval time
: Used bit
: Unused bit
To operate timer 1 as the interval timer function in the 8-bit mode, the function must be set as shown in
185
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Figure 8.6-2 Setting of Interval Timer Function (Timer 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
EDGS0 RESV
Setting of 00
bit0
CCMSK
CPIF CFCLR CPIEN
TCMSK EDGS1
TCCR
TCR1
TCR0
TCR2
TDR1
TFCR1
TCS12
TCS11
TIF1
TIF0
T1IEN
TSTR1
TSTR0
TSEL
TCS10
Setting of a value
other than 111
TFCR0 T0IEN CINV TCS02 TCS01 TCS00
Setting of a value
other than 111
PEN
Setting of interval time
: Used bit
: Unused bit
When the counter is activated in the 8-bit mode, increment begins at the rising or falling edge of the
selected clock, starting at 00 . When the counter value matches the value set in the data register
H
(comparator data latch), the interrupt request bit (TCR0: TIF0 or TCR1: TIF1) of the timer 0 control
register is set to "1" and the count operation is started at 00 . If the counter value matches the value set in
H
the data register when timer 0 is being used, the output of the square wave output control circuit toggles.
When square wave output is allowed (TCR2: PEN) and timer 0 is set to output selection (TCR2: TSEL =
0), a square wave is output from the timer output pin (TO). If the counter value matches the value set in the
data register when timer 1 is being used, the output of the square wave output control circuit toggles. When
square wave output is allowed (TCR2: PEN) and timer 1 is set to output selection (TCR2: TSEL = 1), a
square wave is output from the timer output pin (TO).
Figure 8.6-3 shows interval timer function operation in the 8-bit mode.
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Figure 8.6-3 Interval Timer Function Operation in 8-bit Mode (Timer 0)
Comparison
value
Counter value
Comparison value (FFH)
(E0H)
FFH
E0H
80H
00H
Time
TDR0 value
(E0H
(*1)
)
FFH
TDR0
value
(E0H)
Clear by program
TIF0 bit
Match
Start
Match
Match
(*2)
Counter clear
TSTR0 bit
TO pin
If the data register is rewritten when the counter is in operation, the interval timer
function becomes valid from the next cycle.
When timer 0 is started or when a match is detected, the counter is cleared and the
values in the data register are loaded to the comparator data latch.
*1:
*2:
187
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● 16-bit mode
To operate timer 0 as the interval timer function in the 16-bit mode, the function must be set as shown in
Figure 8.6-4 Setting of Interval Timer Function in 16-bit Mode
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CFCLR
TCMSK EDGS1 EDGS0
Setting of 00
TCCR
TCR1
TCR0
TCR2
CPIF
CPIEN CCMSK
RESV
TIF1 TFCR1 T1IEN
TCS12 TCS11 TCS10
TSTR1
1
1
1
TFCR0 T0IEN
TCS01
TCS00 TSTR0
TIF0
CINV TCS02
Setting of a value
other than 111
PEN TSEL
0
Setting of higher 8 bits of interval time
Setting of lower 8 bits of interval time
TDR1
TDR0
: Used bit
: Unused bit
: Set "0"
0
1
: Set "1"
In the 16-bit mode, timers are controlled by the timer 0 control register (TCR0), but the timer 1 control
register (TCR1) must be initialized. The values to be set in the data register are the higher 8 bits of TDR1
and the lower 8 bits of TDR0 (16 bits in total). The values are compared with the 16-bit counter value. The
16 bits of the counter are cleared at the same time. Other operations in the 16-bit mode are the same as
timer 0 operation in the 8-bit mode.
188
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.7
Operation of Counter Functions
This section describes the operation of the 8/16-bit capture timer/counter function.
■ Counter Function Operation
● 8-bit mode
To operate timer 0 as the counter function in the 8-bit mode, the function must be set as shown in Figure
Figure 8.7-1 Setting of Counter Function in 8-bit Mode
bit7
bit6
bit5
bit4
bit3
0
bit2
bit1
bit0
DDR3
TCCR
TCR1
TCR0
TCR2
CPIEN
T1IEN
CPIF CFCLR
CCMSK TCMSK EDGS1
EDGS0 RESV
TCS11
TCS10 TSTR1
Setting of 00
TFCR1
TIF1
TCS12
Setting of a value
other than 111
TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0
1
1
1
PEN TSEL
Number of detected events
TCDL
TDR0
Setting of the counter value to be compared
: Used bit
: Unused bit
: Set "0"
0
1
: Set "1"
Counter function operation in the 8-bit mode is the same as interval timer function (timer 0 in
8-bit mode) operation except that the external clock is used instead of the internal clock.
The number of events can be known by reading the capture data register (TCPL). A specific number of
events can be known by the event count detection function.
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● Detection of the number of events
In the external clock mode, counter clear can be prohibited by the compare match counter clear mask bit
(TCMSK) of the capture control register (TCCR) when a match is detected. Setting the compare match
counter clear mask bit to "1" enables the event count detection function to be used. In this case, a compare
match does not cause data to be re-loaded to the compare latch. To update the compare latch value, stop
and restart the timer.
Figure 8.7-2 shows counter function operation in the external clock mode in which TCMSK is used.
Figure 8.7-2 Counter Function Operation in External Clock Mode
EC
TSTR0=1
TDR0
FFH
55H
FFH
7FH
01H
01H
TCMSK=0
Compare latch
7FH
Counter clear
Un-
00
00
00H
02H
03H
7EH
7FH
00H
01H
Counter value
defined
TCMSK=1
Compare latch
7F
Counter clear
Un-
00H
02H
03H
7EH
7FH
80H
81H
Counter value
defined
TIF0
TFCR0=1 (W)
190
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● 16-bit mode
To operate timer 0 as the counter function in the 16 bit mode, the function must be set as shown in Figure
Figure 8.7-3 Setting of Counter Function in 16-bit Mode
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DDR3
TCCR
TCR1
TCR0
TCR2
0
CFCLR
TFCR1
TCMSK EDGS1
EDGS0 RESV
CPIF
TIF1
TIF0
CPIEN CCMSK
T1IEN
Setting of 00
TCS12 TCS11
TCS10 TSTR1
1
1
1
TFCR0 T0IEN
CINV TCS02 TCS01 TCS00 TSTR0
1
1
1
PEN
TSEL
Setting of the higher 8 bits of the counter value to be compared
Setting of the lower 8 bits of the counter value to be compared
TDR1
TDR0
TCPH
TCPL
Higher 8 bits of the number of detected events
Lower 8 bits of the number of detected events
: Used bit
: Unused bit
: Set "0"
0
1
: Set "1"
Counter function operation in the 16-bit mode is the same as interval timer function operation in the 16-bit
mode, except that the external clock is used instead of the internal clock.
Figure 8.7-4 shows counter function operation in 16-bit mode.
191
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Figure 8.7-4 Counter Function Operation in 16-bit Mode
External clock
Counter clear
TSTR0 bits
0000H
0001H
0002H
0003H
88H
13H
1388H
0000H
0001H
34H
Counter value
Comparator data latch 1
(lower 8-bit comparison value)
Comparator data latch 2
(higher 8-bit comparison value)
12H
Load
Load
*
TDR0
88H
13H
34H
12H
(lower 8-bit setting value)
*
TDR1
(higher 8-bit setting value)
Data setting (1234H)
TIF0
Clear by program
A value can be set according to any timing. When the counter is started or when a match is detected,
the data register setting value is loaded to the comparator data latch. In this case, the counter is cleared.
*:
Note:
Confirm the validity of the values set in the counter operating in 16-bit mode.
192
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.8
Functions of Operations of Capture Functions
This section describes the capture function operation of the 8/16-bit capture timer/
counter.
■ Capture Function Operation
● 8-bit mode
To operate the capture function in the 8-bit mode, the function must be set as shown in Figure 8.8-1 .
Figure 8.8-1 Setting of Capture Function in 8-bit Mode
bit7
bit6
bit5
bit4
bit3
0
bit2
bit1
bit0
DDR3
TCCR
TCR1
TCR0
TCR2
TCPL
CPIF
TIF1
TIF0
CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV
Setting of a value
other than 00
TFCR1 T1IEN
TFCR0 T0IEN
TCS12 TCS11 TCS10 TSTR1
Setting of a value other
than 111
CINV
TCS02 TCS01 TCS00 TSTR0
Setting of a value other
than 111
PEN
TSEL
Number of detected events
: Used bit
: Unused bit
: Set "0"
0
The 8-bit capture mode is allowed by the capture mode enable/edge detection selection bits (EDGS1 and
EDGS0) of the capture control register (TCCR). "1" is written to the timer start bit (TSTR0) after the clock
source selection bits (TCS02, TCS01, and TCS00) of the timer 0 control register (TCR0) have been set.
In the capture mode, the count value is captured to the capture data register (TCPL) each time a capture
input edge is detected and the capture edge detection flag (CPIF) is set to "1". In this case, if the capture
interrupt enable bit (CPIEN) is already set to "1", an interrupt request is output to the CPU.
The capture mode is divided into free-run mode and clear mode.
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● Free-run mode
Setting the clear mask bits (CCMSK and TCMSK) of TCCR to 11 enables the capture function to operate
B
as the free-run timer.
● Clear mode
Setting the clear mask bits (CCMSK and TCMSK) of TCCR to a value other than 11 enables the capture
B
function to operate as a clear mode.
The clear mode enables the measurement of signal pulse widths and cycles. In this case, using the clear
mode with the compare match detection function also enables the determination of signal availability.
Note:
The capture input pin also serves as the external clock input pin. The external clock mode cannot be
used in the capture mode.
Table 8.8-1 shows the relationship between the counter mode and the compare latch operation according to
the clear mask bit value.
Table 8.8-1 Relationship between Counter Mode and Compare Latch Operation
Data load to compare latch and counter clear
(provided/not provided)
CCMSK
TCMSK
Counter mode
At capture edge detection
At compare match
Data load
Counter clear
Data load
Counter clear
0
0
1
1
0
1
0
1
Provided
Provided
Provided
Provided
Provided
Not provided
Provided
Provided
Not provided
Provided
Clear mode
Not provided
Not provided
Not provided
Not provided
Free-run mode
Not provided
Not provided
194
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Figure 8.8-2 Capture Mode Operation
EQ CAP
CAP
Counter clear
FFFFH
TDR0
Compare latch
Count value
0000H
Capture latch
Capture input (EC)
TSTR0
TIF0
TFCR0 = 1 (W)
TFCR0 = 1 (W)
CPIF
CFCLR= 1 (W)
CFCLR = 1 (W)
CCMSK=0
TCMSK=0
CCMSK=1
TCMSK=1
CCMSK=1
TCMSK=0
195
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
● 16-bit mode
To operate the capture function in the 16-bit mode, the function must be set as shown in Figure 8.8-3 .
Figure 8.8-3 Setting of Capture Function in 16-bit Mode
bit7
bit6
bit5
bit4
bit3
0
bit2
bit1
bit0
DDR3
TCCR
TCR1
TCR0
TCR2
CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV
Setting of a value
other than 00
T1IEN
TCS10 TSTR1
TIF1 TFCR1
TCS12 TCS11
0
Setting of 111
TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0
Setting of a value
other than 111
PEN TSEL
Higher 8 bits of the number of detected events
Lower 8 bits of the number of detected events
TCPH
TCPL
: Used bit
: Unused bit
: Set "0"
0
To set the 16-bit capture mode, set the TCS12, TCS11, and TCS10 bits of the timer 1 control register
(TCR1) to 111 .
B
In the 16-bit mode, timers are controlled by the timer 0 control register (TCR0). The higher 8 bits of the
number of detected events are stored in the capture data register H (TCPH), and the lower 8 bits are stored
in the capture data register L (TCPL).
For operation in the 16-bit mode, see operation in the 8-bit mode.
196
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.9
8/16-bit Capture Timer/Counter Operation in Each Mode
This section describes the operation of the 8/16-bit capture timer/counter when it
switches to the sleep or stop mode or when a halfway stop request is issued during the
operation of the interval timer or counter function.
■ Operation in Standby Mode and at Halfway Stop
Figure 8.9-1 shows the counter value states if the 8/16-bit capture timer/counter switches to the sleep or
stop mode or when a halfway stop request is issued when the interval timer or counter function is in
operation (at timer 0 operation).
When the counter switches to the stop mode, it retains the value and stops. If the stop mode is released by
an external interrupt, the counter starts its operation at the retained value, and so the first interval time and
external clock count are incorrect. When the stop mode is released, the 8/16-bit capture timer/counter must
be initialized.
When the counter is temporarily stopped (TSTR0 = 0), it retains its value and stops. If the subsequent
operation is continued (TSTR0 = 1), the count value is cleared and the counter is restarted.
Figure 8.9-1 Counter Operation in Standby Mode and at Halfway Stop
Counter value
Value set in data
register
0000H
Time
Match
Match
Start
Match
Match
Match
Counter clear
TSTR0 bit
TIF0 bit
Temporary stop
Clear by program
*
TO pin
Sleep
SLP bit
(STBC register)
Sleep release by IRQ3
Stop
STP bit
(STBC register)
External interrupt
When the pin state specification bit (SPL) of the standby control register (STBC) is "1" and the TO pin is not
pulled up, the TO pin in the stop mode becomes Hi-Z. When the pin state specification bit (SPL) is "0", the value
immediately before the 8/16-bit capture timer/counter switches to the stop mode is retained.
*:
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.10
Notes on Using 8/16-bit Capture Timer/Counter
This section provides notes on using the 8/16-bit capture timer/counter.
■ Notes on Using the 8/16-bit Capture Timer/Counter
● Error
The start of the 8/16-bit capture timer/counter by a program is asynchronous with the start of the counter
incremented by the selected count clock, and therefore, the error (a time difference) continues until the
counter value matches the set data. Such a time difference may shorten the total count duration by a
maximum of one count clock cycle. Figure 8.10-1 shows the error (a time difference) that prolongs the
actual start of count operation.
Figure 8.10-1 Error Occurring until the Count Operation is Started
Counter value
Count clock
0
1
2
3
4
1 cycle
Count 0
cycle
Error
Counter start
● Using only timer 0 in 8-bit mode
When using only timer 0 of the 8/16-bit capture timer/counter in the 8-bit mode, set a value other than 111
B
in the count clock selection bits (TCS12, TCS11, TCS10) of the timer 1 control register (TCR1). Using
timer 0 without setting 111 results in a malfunction.
B
● Note on setting by program
When using the 8/16-bit capture timer/counter in the 16-bit mode, set the count clock selection bits
(TCS12, TCS11, TCS10) of TCR1 to 111 .
B
Before using the counter values when the counter is in operation with 16-bit mode, be sure to read the
counter values twice and confirm that the values are valid.
Even if square wave output is initialized when the timer is in operation (TCR0: TSTR0 = 1), the output
value is not modified. The output state is initialized when the timer operation stops.
When the interrupt request flag bits (TCCR: CPIF, TCR0: TIF0, TCR1: TIF1) are "1" and the interrupt
request enable bits are allowed (TCCR: CPIEN, TCR0: T0IEN, and TCR1: T1IEN = 1), return from an
interrupt is impossible. In this case, clear the interrupt request flag bits (TCCR: CFCLR = 1, TCR0: TFCR0 =
1, and TCR1: TFCR1 = 1).
198
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
When the counter operation stops according to the timer start bits (TCR0: TSTR0 = 0 and TCR1: TSTR1 =
0) and the interrupt source occurs at the same time, the interrupt request flag bits (TCR0: TIF0 and TCR1:
TIF1) are not set.
In the capture mode, no external clock can be selected; set the count clock bits (TCS12,TCS11, and TCR1:
TCS10) to a value other than 111 .
B
● Note on using interrupts
If the compare register value is 0000 or 00 , the 8/16-bit capture timer/counter cannot generate interrupts.
H
H
For this reason, when using interrupts, set a value greater than or equal to 0001 or 01 . The 8/16-bit
H
H
capture timer/counter cannot generate interrupts if the capture counter function detects the 0000 or 00
H
H
width.
199
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.11
Program Example for 8/16-bit Capture Timer/Counter
This section provides program examples of the 8/16-bit capture timer/counter.
■ Program Example of Interval Timer Function
● Processing specifications
•
•
•
In the 8-bit mode, only timer 0 is used to generate a 20 ms interval timer interrupt.
When the interval time has elapsed, the square wave to be inverted is output to the TO pin.
At 12.5-MHz oscillation (F ), the TDR0 value whose interval time becomes 20 ms at the maximum
CH
gear speed (1 instruction cycle = 4/F ) is shown below. The count clock is 256t
of the internal
INST
CH
count clock.
TDR0 value = 20 ms/(256 × 4/12.5 MHz) - 1 = 244 (F4 )
H
● Coding example
TCCR EQU
0019H
001AH
001BH
0020H
001CH
001DH
; Address of capture control register
; Address of timer 1 control register
; Address of timer 0 control register
TCR1 EQU
TCR0 EQU
TCR2 EQU
TDR1 EQU
TDR0 EQU
; Address of timer output control register
; Address of timer 1 data register
; Address of timer 0 data register
TIF0
ILR1
EQU
EQU
TCR0:7
007BH
ABS
; Defines the timer 0 interrupt request flag bit.
; Address of interrupt request setting register
; [DATA SEGMENT]
INT_V DSEG
ORG
0FFF0H
WARI
IRQD DW
ENDS
; Sets an interrupt vector.
;------------------------Main program---------------------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
; The stack pointer (SP), etc., is already initialized.
:
CLRI
MOV
MOV
; Disables the interrupt.
ILR1,#10111111B
TCR0,#01001010B
; Sets the interrupt level to 2.
; Clears the timer 0 interrupt request flag, increments the
counter at a rising edge, selects 256t
operation.
, and stops the
INST
MOV
MOV
TCR1,#01000010B
TDR0,#F4H
; Clears the timer 1 interrupt request flag, prohibits
interrupt request output, sets a mode other than the 16-
bit mode, and stops the operation.
; Sets the value (interval time) to be compared with the
counter value.
200
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
MOV
MOV
TCR2,#00000010B
TCR0,#10101011B
; Outputs a square wave (TO) from the P34 pin.
; Allows timer 0 interrupt request output, clears the
counter, and starts the timer.
SETI
:
; Enables the CPU interrupt.
;------------------------Interrupt program----------------------------------------------------------------------------
WARI CLRB
PUSHW
TIF0
A
; Clears the interrupt request flag.
XCHW
PUSHW
:
A,T
A
User processing
POPW
XCHW
POPW
RETI
A
A,T
A
ENDS
; --------------------------------------------------------------------------------------------------------------------
END
201
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
■ Program Example of Counter Function
● Processing specifications
•
In the 16-bit mode, timer 0 and timer 1 are used to generate an interrupt whenever the external clock to
be input to the EC pin is counted 5,000 times (1388 ).
H
•
The sample program for reading the 16-bit counter value when the counter is in operation is shown
below (READ16).
● Coding example
DDR3
TCCR
TCR1
TCR0
TDR1
TDR0
TIF0
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000DH
0019H
001AH
001BH
001CH
001DH
TCR0:7
007CH
ABS
; Address of port 3-direction register
; Address of capture control register
; Address of timer 1 control register
; Address of timer 0 control register
; Address of timer 1 data register
; Address of timer 0 data register
; Defines the timer 0 interrupt request flag bit.
; Address of interrupt level setting register 2
; [DATA SEGMENT]
ILR1
INT_V DSEG
ORG
0FFF0H
WARI
IRQD
DW
; Sets the interrupt vector.
ENDS
;------------------------Main program---------------------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
; The stack pointer (SP), etc., is already initialized.
:
MOV
CLRI
MOV
MOV
DDR3,#00000000B ; Sets the EC pin to input.
; Disables the interrupt.
ILR1,#10111111B ; Sets the interrupt level to 2.
TDR0,#088H
; Sets the counter value and the lower 8 bits of the
compare value.
MOV
TDR1,#013H
; Sets the counter value and the higher 8 bits of the
compare value.
MOV
MOV
TCR1,#00001110B ; Sets timer 1 to 16-bit mode.
TCR0,#01101111B ; Clears the timer 0 interrupt request flag, allows interrupt
request output, selects an external clock, clears the
counter, starts the operation, and increments the counter
at a rising edge.
SETI
; Enables a CPU interrupt.
;------------------------Data read subroutine-------------------------------------------------------------------------
READ16
MOVW
MOVW
A,TDR1
A,TDR1
; Reads 16 bits from TDR1 and TDR0.
; Reads 16 bits from TDR1 and TDR0 and stores the old
value in the T register.
CMPW
BEQ
A
; Executes double read check and compares A with T.
; Match and return
RET16
202
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
XCHW
INCW
CMPW
BNE
A,T
A
; Old value + 1
A
READ16
; Jumps to re-read when a mismatch is detected.
; Restarts the count operation and begins counting 10,000
pulses.
RET16 RET
;------------------------Interrupt program----------------------------------------------------------------------------
WARI
CLRB
PUSHW
XCHW
PUSHW
:
TIF0
A
; Clears the interrupt request flag.
A,T
A
User processing
:
POPW
XCHW
POPW
RETI
A
A,T
A
ENDS
; --------------------------------------------------------------------------------------------------------------------
END
203
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
204
CHAPTER 9 12-BIT PPG TIMER
9.1
Overview of 12-bit PPG Timer
The 12-bit PPG timer is a 12-bit binary counter, enabling the selection of one of four
types of internal count clocks. The timer is capable of setting a cycle period and "H"
width of output pulse waveforms and can also be used as a remote control
transmission frequency generator or 12-bit PPG.
■ Functions of 12-bit PPG Timer
•
•
•
The timer generates a frequency for remote control and outputs signals to a PPG pin.
The timer is capable of setting a cycle period and "H" width of output pulse waveforms separately.
The timer enables the selection of a count clock from four types of internal clocks.
12
•
The timer can generate a frequency in a range from twice to 2 -1 times as fast as the counter clock.
Table 9.1-1 lists the ranges in which the output pulse cycle period and "H" width are variable.
Table 9.1-1 Ranges in which the Output Pulse Cycle Period and "H" Width are Variable
Internal count clock
Output pulse cycle period
4t to 8190t
Output pulse "H" width
2t to 8188t
cycle period
2t
4t
INST
INST
INST
INST
INST
INST
8t
to 16380t
4t
to 16376t
INST INST
INST
INST
16t
32t
to 65520t
16t
to 65504t
INST
INST
INST
INST INST
256t
512t
to 1048.32kt
256t
to 1048.064kt
INST
INST
INST
INST INST
t
Instruction cycle (to be affected by a gear function)
INST:
Note:
An example of calculating the output pulse cycle period and "H" width as executed by a 12-bit PPG
function is given below.
When an oscillation (F ) of 12.5 MHz and a count clock cycle period of 2 t
are set, and if:
CH
INST
Compare value for cycle period = 011110 (30-clock period)
B
Compare value for "H" width = 001010 (10-clock width)
B
Then, "H" width and the cycle period of output pulse waveforms are calculated as given below. These
calculations are obtained provided the system clock control register (SYCC) selects the fastest clock
(CS1, CS0 = 11 with one instruction cycle = 4/F ).
B
CH
206
CHAPTER 9 12-BIT PPG TIMER
Cycle period = Compare value for cycle period × Count clock cycle period
= 011110H (30-clock period) × 2 × 4/FCH
= 30 × 2 × 0.32 µs = 19.2 µs
"H" width = Compare value for "H" width × Count clock cycle period
= 001010B (10-clock width) × 2 × 4/FCH
=10 × 2 × 0.32 µs
=6.4 µs
If the set "H" width is equal to or greater than the set cycle period, "H" level outputs occur.
■ 12-bit PPG Function
The timer’s programmable pulse output generator function can be used as a 12-bit PPG because it can set a
cycle period and "H" pulse width of output pulse waveforms separately. A range of controllable duty cycles
is 0.02% to 100%. However, the smaller the compare value for the cycle period, the lower the resolution
(the greater a minimum-step duty cycle).
If the compare value for the cycle period is "2", a comparative setting of "H" pulse width is 1 or 2 (a duty
cycle of 50% or 100%) and the resolution is 1/2.
An output frequency and a duty cycle can be calculated using the following equations:
Output pulse cycle period = Compare value for cycle period × Count clock cycle period
Duty cycle = Compare value for "H" width/Compare value × 100(%)
Table 9.1-2 lists available resolution values, minimum-step duty cycles, and output pulse cycle periods.
Table 9.1-2 Resolutions and Output Pulse Cycle Periods Supported when the Timer is Used as a 12-bit
PPG (1/2)
Range of
available
compare
values for
"H" width
Output pulse cycle period
Compare
value for
cycle
Minimum-
step duty
cycle
Resolution
Count clock
Count clock
Count clock
Count clock
= 2 t
= 4 t
= 16 t
= 256 t
period
INST
INST
INST
INST
0
1
2
-
-
Unavailable
4 t
8 t
32 t
48 t
64 t
80 t
96 t
512 t
INST
1, 2
1/2
1/3
1/4
1/5
1/6
1/7
1/8
50.0%
33.3%
25.0%
20.0%
16.7%
14.3%
12.5%
INST
INST
INST
INST
INST
INST
INST
6 t
12 t
768 t
INST
3
4
5
6
7
8
1 to 3
1 to 4
1 to 5
1 to 6
1 to 7
1 to 8
INST
INST
8 t
16 t
1024 t
INST
INST
INST
10 t
20 t
1280 t
INST
INST
INST
12 t
24 t
1536 t
INST
INST
INST
14 t
28 t
112 t
128 t
1792 t
INST
INST
INST
INST
INST
16 t
32 t
2048 t
INST
INST
INST
207
CHAPTER 9 12-BIT PPG TIMER
Table 9.1-2 Resolutions and Output Pulse Cycle Periods Supported when the Timer is Used as a 12-bit
PPG (2/2)
Range of
available
compare
values for
"H" width
Output pulse cycle period
Compare
value for
cycle
Minimum-
step duty
cycle
Resolution
Count clock
Count clock
Count clock
Count clock
= 2 t
= 4 t
= 16 t
= 256 t
period
INST
INST
INST
INST
18 t
36 t
144 t
INST
2304 t
INST
9
1 to 9
1/9
11.1%
10.0%
INST
INST
20 t
40 t
160 t
INST
2560 t
INST
10
1 to 10
1/10
INST
INST
:
:
:
:
1 to 20
1 to 100
1 to 500
1 to 1000
1 to 2000
1 to 3000
1 to 4095
40 t
80 t
320 t
INST
5120 t
INST
1/20
20
5.0%
1.0%
INST
INST
:
:
:
:
200 t
INST
400 t
INST
1600 t
INST
25600 t
INST
100
1/100
:
:
:
:
1000 t
INST
2000 t
INST
8000 t
INST
128000 t
INST
500
1/500
0.2%
:
:
:
:
2000 t
INST
4000 t
INST
16000 t
INST
256000 t
INST
1000
2000
3000
4095
1/1000
1/2000
1/3000
1/4095
0.1%
:
:
:
:
4000 t
INST
8000 t
INST
32000 t
INST
512000 t
INST
0.05%
0.03%
0.02%
:
:
:
:
6000 t
INST
12000 t
INST
48000 t
INST
768000 t
INST
:
:
:
:
8190 t
INST
16380 t
INST
65520 t
INST
1048320 t
INST
t
: Instruction cycle
INST
208
CHAPTER 9 12-BIT PPG TIMER
9.2
Configuration of 12-bit PPG Timer Circuit
The 12-bit PPG timer comprises the following seven blocks:
• Count clock selector
• 12-bit counter
• Comparator
• 12-bit PPG control register 1 (RCR21)
• 12-bit PPG control register 2 (RCR22)
• 12-bit PPG control register 3 (RCR23)
• 12-bit PPG control register 4 (RCR24)
■ Block Diagram of 12-bit PPG Timer
Figure 9.2-1 Block Diagram of 12-bit PPG Timer
Internal data bus
RCR21
HSC0
RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1
HSC11 HSC10 HSC9
Compare value for "H" width
HSC6
RCR22
HSC8 HSC7
Count
clock
selector
12
12-bit counter
CLK
2
4
P37/BZ/PPG pin
Comparator
16
256
Clear
1t
INST
12
Compare value for cycle period
SCL9
RCR24
SCL11 SCL10
SCL8 SCL7 SCL6
RCR23
SCL5
RCEN
SCL4 SCL3 SCL2 SCL1 SCL0
Internal data bus
t
INST: Instruction cycle
209
CHAPTER 9 12-BIT PPG TIMER
● Count clock selector
This selector circuit selects one of four types of internal count clocks as the count-up clock for a 12-bit
counter.
● 12-bit counter
The 12-bit counter executes a count-up operation based on the count clock selected by the count clock
selector.
This counter may be cleared according to the value of the output enable bit of the RCR23 register
(RCR23:RCEN=0).
● Comparator
The comparator maintains outputs at "H" until a count by the 12-bit counter has been synchronized with the
value of the register containing the compare value for "H" width. The comparator then maintains outputs at
"L" until a count by the counter is synchronized with the value of the register containing the set cycle
period. At this time, the 12-bit counter is cleared and restarts to count from "00 ".
H
● 12-bit PPG control registers 1 (RCR21) and 2 (RCR22)
These registers comprise bits for count clock selection and bits for setting a compare value for the "H"
width.
● 12-bit PPG control registers 3 (RCR23) and 4 (RCR24)
These registers comprise a bit for specifying whether to enable or disable the 12-bit PPG output and bits for
setting a compare value for the cycle period.
210
CHAPTER 9 12-BIT PPG TIMER
9.3
Pin of 12-bit PPG Timer
This section describes the pin associated with the 12-bit PPG timer and illustrates a
block diagram of circuitry terminating at the pin.
■ Pin Associated with the 12-bit PPG Timer
The pin associated with the 12-bit PPG timer is P37/BZ/PPG pin.
● P37/BZ/PPG pin
This pin functions as a CMOS type (P37) general-purpose I/O port, further functioning as 12-bit PPG timer
output (PPG).
PPG:
By setting the output enable bit of the appropriate 12-bit PPG control register (RCR23:RCEN) to "1",
the pin functions as the PPG output pin through which the set cycle period and "H" width of PPG
pulse waveforms are output.
211
CHAPTER 9 12-BIT PPG TIMER
■ Block Diagram of Circuitry Terminating at the Pin Associated with the 12-bit PPG
Timer
Figure 9.3-1 Block Diagram of Circuitry Terminating at the P37/BZ/PPG Pin
PDR
Stop mode (SPL = 1)
Pull-up resistor
PDR read
Output from
peripheral
Output
enabl
from
peripheral
PDR read
(when read-modify-write is
performed)
P-ch
N-ch
Output latch
PDR write
Pin
P37/BZ/PPG
DDR
DDR write
Stop mode (SPL = 1)
PUL read
PUL
PUL write
Notes:
• If the ON setting of the pull-up resistor is selected by the pull-up setting register, the pin state will be
the "H" level (pull-up state) in stop mode (SPL = 1).
• Because buzzer outputs to the P37/BZ/PPG pin precede 12-bit PPG outputs to this pin, if the pin is
used as the PPG pin, turn the buzzer outputs off and set the RCEN bit such that PPG outputs are
enabled.
212
CHAPTER 9 12-BIT PPG TIMER
9.4
Registers of 12-bit PPG Timer
This section describes the registers associated with the 12-bit PPG timer.
■ Registers Associated with 12-bit PPG Timer
Figure 9.4-1 Registers Associated with 12-bit PPG Timer
RCR21 (12-bit PPG control register 1)
Address
0014H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00000000B
RCK1
R/W
HSC1
R/W
RCK0 HSC5 HSC4 HSC3 HSC2
HSC0
R/W
R/W
R/W
R/W
R/W
R/W
RCR22 (12-bit PPG control register 2)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
HSC11
0015H
HSC10 HSC9 HSC8
HSC6 --000000B
R/W
HSC7
R/W
R/W
R/W
R/W
R/W
RCR23 (12-bit PPG control register 3)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0016H
RCEN
R/W
SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0-000000B
R/W
R/W
R/W
R/W
R/W
R/W
RCR24 (12-bit PPG control register 4)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
SCL7
R/W
bit0
Address
0017H
SCL11 SCL10 SCL9
R/W R/W R/W
SCL8
R/W
SCL6 --000000B
R/W
R/W : Readable and Writable
: Unused
213
CHAPTER 9 12-BIT PPG TIMER
9.4.1
12-bit PPG Control Register 1 (RCR21)
The 12-bit PPG control register 1 comprises bits for count clock selection of the 12-bit
PPG timer and bits for setting the "H" width.
■ 12-bit PPG Control Register 1 (RCR21)
Figure 9.4-2 12-bit PPG Control Register 1 (RCR21)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0014H RCK1
HSC1
00000000B
RCK0 HSC5 HSC4 HSC3 HSC2
HSC0
R/W R/W R/W R/W R/W R/W R/W R/W
"H" width setting bits
HSC5 to HSC0
Compare value for the "H" width of 12-bit PPG outputs.
XXXXXX
RCK1
RCK0
Count clock selection bits
0
0
1
1
0
1
0
1
2 tINST
4 tINST
16 tINST
256 tINST
R/W : Readable/Writable
: Initial value
Table 9.4-1 Explanation of Functions of Each Bit in 12-bit PPG Control Register 1 (RCR21)
Bit name
RCK1, RCK0:
Function
bit7,
bit6
These bits are used to select a count clock of the 12-bit PPG timer from four types of
internal count clocks.
Count clock
selection bits
These bits are used to set the number of counts corresponding to the "H" width of
12-bit PPG timer outputs (the compare value for the "H" width), and the contents of
these bits and the HSC6 to HSC11 bits of the RCR22 register are compared with a
count by the counter.
bit5
to
bit0
HSC5 to HSC0:
"H" width setting
bits
214
CHAPTER 9 12-BIT PPG TIMER
9.4.2
12-bit PPG Control Register 2 (RCR22)
The 12-bit PPG control register 2 comprises bits for setting the "H" width of 12-bit PPG
pulse waveforms.
■ 12-bit PPG Control Register 2 (RCR22)
Figure 9.4-3 12-bit PPG Control Register 2 (RCR22)
Address
0015H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
--000000B
HSC6
HSC11 HSC10 HSC9 HSC8 HSC7
R/W R/W R/W R/W R/W R/W
HSC11 to HSC6
XXXXXX
"H" width setting bits
Compare value for the "H" width of 12-bit PPG outputs
R/W
:
Readable/Writable
: Unused
Table 9.4-2 Explanation of Functions of Each Bit in 12-bit PPG Control Register 2 (RCR22)
Bit name Function
Unused bits
bit7,
bit6
•
•
Bit value is undefined when being read.
Written value does not affect other operations.
These bits are used to set the number of counts corresponding to the "H" width of
12-bit PPG timer outputs (the compare value for the "H" width), and the contents of
these bits and the HSC0 to HSC5 bits of the RCR21 register are compared with a
count by the counter.
bit5
to
bit0
HSC11 to HSC6:
"H" width setting
bits
215
CHAPTER 9 12-BIT PPG TIMER
9.4.3
12-bit PPG Control Register 3 (RCR23)
The 12-bit PPG control register 3 comprises a bit for enabling 12-bit PPG waveform
outputs and bits for setting a cycle period of outputs.
■ 12-bit PPG Control Register 3 (RCR23)
Figure 9.4-4 12-bit PPG Control Register 3 (RCR23)
Address
0016H
bit7
RCEN
R/W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
SCL5
SCL4 SCL3 SCL2 SCL1 SCL0 0-000000B
R/W R/W R/W R/W R/W R/W
Cycle period setting bits
SCL5 to SCL0
XXXXXX
Compare value for the cycle period of 12-bit PPG output
Output enable bit
Output disabled, counter cleared
RCEN
0
1
Output enabled with count operation starting
: Readable/Writable
: Unused
R/W
: Initial value
216
CHAPTER 9 12-BIT PPG TIMER
Table 9.4-3 Explanation of Functions of Each Bit in 12-bit PPG Control Register 3 (RCR23)
Bit name
Function
When this bit is "0", the P37/BZ/PPG pin functions as a general-purpose port (P37);
when the bit is "1", the pin functions as a 12-bit PPG output pin (PPG).
When "0" is written for this bit, the counter is cleared and its operation stops; when
"1" is written, the count operation starts.
Even if PPG outputs are enabled by this bit setting, buzzer outputs, if enabled, have
priority.
RCEN:
Output enable bit
bit7
bit6
•
•
Bit value is undefined when being read.
Written value does not affect other operations.
Unused bit
These bits are used to set the number of counts corresponding to the cycle period of
12-bit PPG waveform outputs (the compare value for the cycle period), and the
contents of these bits and the SCL6 to SCL11 bits of RCR24 are compared with a
count by the counter.
bit5
to
bit0
SCL5 to SCL0:
Cycle period
setting bits
Note:
Set a value that falls within the range of "000000000010 " to "111111111111 "
B
B
(002 to FFF ).
H
H
Note:
Because buzzer outputs to the P37/BZ/PPG pin precede 12-bit PPG outputs to this pin, if the pin is used
as the PPG pin, turn the buzzer outputs off and set the RCEN bit such that PPG outputs are enabled.
217
CHAPTER 9 12-BIT PPG TIMER
9.4.4
12-bit PPG Control Register 4 (RCR24)
The 12-bit PPG control register 4 comprises bits for setting a cycle period of 12-bit PPG
waveform outputs.
■ 12-bit PPG Control Register 4 (RCR24)
Figure 9.4-5 12-bit PPG Control Register 4 (RCR24)
Address
0017H
bit7
bit6
bit5
bit4
SCL10
R/W
bit3
bit2
bit1
bit0
Initial value
SCL11
R/W
SCL9 SCL8 SCL7 SCL6 --000000B
R/W
R/W
R/W
R/W
SCL11 to SCL6
XXXXXX
Cycle period setting bits
Compare value for the cycle period of 12-bit PPG outputs
R/W: Readable/Writable
: Unused
Table 9.4-4 Explanation of Functions of Each Bit in 12-bit PPG Control Register 4 (RCR24)
Bit name Function
Unused bits
bit7,
bit6
•
•
Bit value is undefined when being read.
Written value does not affect other operations.
These bits are used to set the number of counts corresponding to the cycle period of
12-bit PPG waveform outputs (the compare value for cycle period), and the contents
of these bits and the SCL0 to SCL5 bits of RCR23 are compared with a count by the
counter.
Note:
bit5
to
bit0
SCL11 to SCL6:
Cycle period
setting bits
Set a value that falls within the range of "000000000010 " to "111111111111 "
B
B
(002 to FFF ).
H
H
218
CHAPTER 9 12-BIT PPG TIMER
9.5
Operations of 12-bit PPG Timer Functions
The 12-bit PPG timer can be used as a 12-bit PPG because the output pulse cycle period
and "H" pulse width can be set separately.
■ Example of Operations of 12-bit PPG Timer Functions
Figure 9.5-1 Setting 12-bit PPG Timer
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RCR21
RCR22
RCR23
RCR24
RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0
HSC11 HSC10 HSC9 HSC8 HSC7 HSC6
SCL5 SCL4 SCL3 SCL2 SCL1 SCL0
RCK1
RCEN
1
SCL10 SCL9 SCL8 SCL7 SCL6
SCL11
: Used bit
: Set "1"
1
When 12-bit PPG outputs are enabled, the 12-bit counter starts counting from" 000 in synchronization
H"
with the selected count clock and the PPG pin is maintained at "H" level until a count by the counter is
synchronized with the compare value for the "H" width. The PPG pin is then maintained at "L" level until a
count by the counter is synchronized with the compare value for the cycle period. At this time, the 12-bit
counter is cleared and restarts counting from "000 . Because the "H" width and cycle period can be set
H"
separately, the timer can be used as a 12-bit PPG.
219
CHAPTER 9 12-BIT PPG TIMER
Figure 9.5-2 illustrates the operation of the 12-bit PPG timer.
Figure 9.5-2 Operation of 12-bit PPG Timer
Count by counter
Cycle period setting
(RCR23, 24:SCL0 to SCL11)
"H" width setting
(RCR21, 22:HSC0 to HSC11)
"000H"
Cycle period (*1)
"H" width (*2)
PPG output pulse waveform
If internal count clock cycle period is 2, 4, 16, or 256 tINST, cycle period = compare value for cycle
*1:
*2:
period multiplied by the count clock cycle period.
If internal count clock cycle period is 2, 4, 16, or 256 tINST, "H" width = compare value for the "H"
width multiplied by the count clock cycle period.
220
CHAPTER 9 12-BIT PPG TIMER
9.6
Notes on Using 12-bit PPG Timer
This section provides notes on using the 12-bit PPG timer.
■ Notes on Using 12-bit PPG Timer
● Output pin changeover
The P37/BZ/PPG pin shares functions of a general-purpose port and a 12-bit PPG output. Because its
buzzer output (BZ) function precedes the 12-bit PPG output function, if buzzer outputs are enabled, it
functions as the buzzer output (BZ) pin even if PPG outputs are enabled by the RCR23 (RCEN bit). To use
it as the 12-bit PPG output (PPG) pin, turn the buzzer outputs OFF.
● Limitation of "H" width setting
Using the "H" width setting bits of the 12-bit PPG control registers 1 and 2 (RCR21:HSC5 to HSC0 and
RCR22:HSC11 to HSC6), set a value that falls within the range of "000000000001 " to "111111111111 "
B
B
(001 to FFF ). If "000 " is set, "H" level outputs are delivered through the PPG pin. Furthermore, set the
H
H
H
value of the "H" width so as to be smaller than the value given by the cycle period setting bits of 12-bit
PPG control registers 3 and 4 (RCR23:SCL5 to SCL0 and RCR24:SCL11 to SCL6). If the "H" width is
equal to or greater than the cycle period, "H" level outputs are always delivered through the PPG pin.
● Resolution
When the cycle period is set at "111111111111 " (FFF ), a maximum "H" width resolution of 1/4095 is
B
H
obtained. This resolution is reduced as the cycle period setting becomes smaller and limited to a minimum
of 1/2 when the cycle period is set at "000000000010 " (002 ).
B
H
● Setting change during operation
The "H" width setting bits (RCR21:HSC5 to HSC0 and RCR22:HSC11 to HSC6) and the cycle period
setting bits (RCR23:SCL5 to SCL0 and RCR24:SCL11 to SCL6) are compared with the 12-bit counter for
generating a frequency of 12-bit PPG waveforms. If the set values given by these bits are changed to
smaller values during the operation of the counter, a counter overflow occurs, which may extend the cycle
period until synchronization with a count by the counter is detected again. Similarly, this may extend the
"H" width until synchronization with a count by the counter is detected in the next cycle (cycle period).
Figure 9.6-1 illustrates setting change during the operation of the 12-bit PPG timer.
221
CHAPTER 9 12-BIT PPG TIMER
Figure 9.6-1 Setting Change during 12-bit PPG Timer Operation
Count by counter
Overflow
"FFF"H
*1
*2
Cycle period setting
(RCR23,24:SCL0 to SCL11)
*1
* 3
"H" width setting
(RCR21,22:HSC0 to HSC11)
"00"H
PPG output pulse waveform
1 period
Extend by overflow
*1:
Because the count interval of the operating counter is less than the changed setting, the setting is
effective only within the cycle.
*2:
Because a cycle period less than the count interval of the operating counter is set, synchronization
is not detected and the counter overflows.
*3:
Because an "H" width less the count interval of the operating counter is set, synchronization is not
detected until the next cycle.
● Error
Because the counter start by program is asynchronous with the count-up start by the selected count clock,
an error (a time difference) may occur until detection of synchronization of compare values for the "H"
width and for the cycle period with a count by the counter. A major error may shorten the time before the
above synchronization to one count clock cycle.
Figure 9.6-2 illustrates an error (a time difference) before the count operation start.
Figure 9.6-2 Error before Count Operation Start
Count by counter
0
1
2
3
4
Count clock
1 cycle
Count 0
Error
period
(time
difference)
Counter start
222
CHAPTER 9 12-BIT PPG TIMER
9.7
Program Example for 12-bit PPG Timer
An example of 12-bit PPG timer programming is given below.
■ Program Example for 12-bit PPG Timer
● Processing specification
•
A remote control transmission frequency with a period of about 38 µs and a duty cycle of approx. 33%
is generated.
•
The compare value for the PPG output pulse cycle period giving the above period of about 38 µs at the
maximum gear speed with oscillation of 12.5 MHz (F ) is determined as below. The count clock is
CH
assumed to be 4 t
.
INST
Compare value for cycle period (RCR23:SCL5 to SCL0 and RCR24:SCL11 to SCL6) = 38 µs/ (4 × 4/
10MHz) = 30
•
The compare value for the "H" width of the PPG output pulse giving the duty cycle of approx. 33% is
determined as below. At this time, the "H" width is about 3 µs.
Compare value for the "H" width (RCR21:HSC5 to HSC0 and RCR22:HSC11 to HSC6) =33/100 ×
Compare value for the cycle period = 0.33 × 30 = 10
● Coding example
RCR21 EQU
0014H
0015H
0016H
0017H
;
;
;
;
Address of 12-bit PPG control register 1
Address of 12-bit PPG control register 2
Address of 12-bit PPG control register 3
Address of 12-bit PPG control register 4
RCR22 EQU
RCR23 EQU
RCR24 EQU
;------------------------Main program---------------------------------------------------------------------------------
CSEG
:
MOV
;
;
;
;
;
[CODE SEGMENT]
RCR21,#01001010B
RCR22,#00H
Select count clock of 4 t
value for "H" width.
and set the above compare
INST
MOV
MOV
RCR23,#10011110B
RCR24,#00H
Specify outputs enabled and counter operation start and
set the above compare value for cycle period.
MOV
:
ENDS
;---------------------------------------------------------------------------------------------------------------------
END
223
CHAPTER 9 12-BIT PPG TIMER
224
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.1
Overview of External Interrupt Circuit 1
External interrupt circuit 1 detects a predetermined edge or edges of a signal input to
any of three external interrupt pins and then generates and issues an interrupt request
to the CPU.
■ Functions of External Interrupt Circuit 1
The external interrupt circuit 1 functions to detect an optionally selected edge or edges of a signal input to
any of the external interrupt pins and then generate and issue an interrupt request to the CPU. This interrupt
ensures recovery from standby mode and enables transition to a normal operating state (main clock
operation mode).
•
•
External interrupt pins: Three pins (P34/TO/INT10 to P36/INT12)
External interrupt triggering: Input of a signal with an optionally selected edge or edges (rising and/or
falling edges) to one of the above external interrupt pins triggers an
external interrupt.
•
Interrupt control: Interrupt request outputs are enabled or disabled according to the content of an
interrupt request enable bit of external interrupt 1 control registers 1 and 2 (EIC1,
EIC2).
•
•
Interrupt flag:Detection of specified edge or edges is indicated by an external interrupt request flag bit
of external interrupt 1 control registers 1 and 2 (EIC1, EIC2).
Interrupt request: An interrupt request is generated according to the pin at which the input of the signal
triggering an external interrupt is detected (IRQ0, IRQ1, IRQ2).
226
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.2
Configuration of External Interrupt Circuit 1
External interrupt circuit 1 comprises the following two blocks:
• Edge detecting circuits (0 to 2)
• External interrupt control 1 registers 1, 2 (EIC1, EIC2)
■ Block Diagram of External Interrupt Circuit 1
Figure 10.2-1 Block Diagram of External Interrupt Circuit 1 (EIC1, EIC2)
Pin
P34/TO/INT10
Edge detecting circuit 1
10
Edge detecting circuit 0
10
01
11
01
11
Pin
P35/INT11
External interrupt 1
control register 1
(EIC1)
EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0
Interrupt request
(IRQ0)
Interrupt request
(IRQ1)
Pin
P36/INT12
Edge detecting circuit 2
10
01
11
External interrupt 1
control register 2
(EIC2)
EIR2 SL21 SL20 EIE2
Interrupt request (IRQ2)
227
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
● Edge detecting circuits
When the edge polarity of a signal input to one of the pins (INT10 to INT12) for external interrupt circuit 1
matches the selected edge polarity for the pin, stored in either the EIC1 or EIC2 registers in the appropriate
bit position (SL00 to SL21), one of the external interrupt request flag bits (EIR0 to EIR2) corresponding to
the pin is set to "1".
● External interrupt 1 control registers (EIC1, EIC2)
The EIC1 and EIC2 registers comprise bits for edge selection, for enabling or disabling interrupt requests,
and for confirming an interrupt request.
● Triggers that cause external interrupt circuit 1 to generate an interrupt request
•
•
•
IRQ0: When a signal with an edge or edges corresponding to the selected edge polarity is input to the
INT10 pin for external interrupt circuit 1, if interrupt request outputs are enabled (EIC1:EIE0=1),
external interrupt circuit 1 generates an IRQ0 interrupt request.
IRQ1: When a signal with an edge or edges corresponding to the selected edge polarity is input to the
INT11 pin for external interrupt circuit 1, if interrupt request outputs are enabled (EIC1:EIE1=1),
external interrupt circuit 1 generates an IRQ1 interrupt request.
IRQ2: When a signal with an edge or edges corresponding to the selected edge polarity is input to the
INT12 pin for external interrupt circuit 1, if interrupt request outputs are enabled (EIC2:EIE2=1),
external interrupt circuit 1 generates an IRQ2 interrupt request.
228
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.3
Pins of External Interrupt Circuit 1
This section describes the pins associated with external interrupt circuit 1 and
illustrates a block diagram of circuitry terminating at the pins with reference to the
registers and external interrupt triggering.
■ Pins Associated with External Interrupt Circuit 1
The pins associated with external interrupt circuit 1 are the P34/TO/INT10 to P36/INT12 pins.
● P34/TO/INT10 pin
This pin functions as a general-purpose I/O dedicated port and may also serve 8/16-bit capture timer
outputs (TO) and external interrupt inputs (hysteresis inputs) (INT10).
If the timer 1 control register (TCR0) disables 8/16-bit capture timer outputs and, by the port data direction
register (DDR3), the pin is set to function as an input port only. The pin can also function as an external
interrupt input pin (INT10). When external interrupt 1 control register 1 (EIC1) sets edge detection to OFF,
however, no external interrupt requests are generated, and when interrupt request outputs are disabled, no
interrupt requests are output. The pin state can be read directly from the port data register (PDR3) at any
time.
● P35/INT11 and P36/INT12 pins
These pins function as a general-purpose I/O dedicated port (P35, P36) and may also serve external
interrupt inputs (hysteresis inputs) (INT11, INT12).
If, by the port data direction register (DDR3), these pins are set to function as an input port only, they also
function as external interrupt input pins (INT11, INT12). When external interrupt 1 control registers 1 and
2 (EIC1, EIC2) set edge detection to OFF, however, no external interrupt requests are generated, and when
interrupt request outputs are disabled, no interrupt requests are output. The pin state can be read directly
from the port data register (PDR3) at any time.
Table 10.3-1 lists the pins associated with external interrupt circuit 1.
Table 10.3-1 Pins Associated with External Interrupt Circuit 1
Use for input port only
(Interrupt request output or edge detection
disabled)
Use for external interrupt input
(Interrupt request output enabled)
External interrupt pin
INT10 (EIC1:EIE0=1, DDR3:bit4=0,
TCR2:PEN=0)
P34(EIC1:EIE0=0 or SL01, SL00=00 )
P34/TO/INT10
B
P35(EIC1:EIE1=0 or SL11, SL10=00 )
P35/INT11
P36/INT12
INT11 (EIC1:EIE1=1, DDR3:bit5=0)
INT12 (EIC2:EIE2=1, DDR3:bit6=0)
B
P36(EIC2:EIE2=0 or SL21, SL20=00 )
B
INT10 to INT12: When a signal with an edge or edges corresponding to the selected edge polarity is input to these pins,
an interrupt corresponding to the pin is generated.
229
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
■ Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
Circuit 1
Figure 10.3-1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1
External interrupt
INT10,INT11
enable
INT12
PDR
Stop mode
(SPL=1)
Output from
PDR read
peripheral
Pull-up
resistor
Output
from
Output occurring
from peripheral
peripheral
enable
PDR read
(when read-modify-write is
performed)
P-ch
Output
latch
PDR write
Pins
P34/TO/INT10
P35/INT11
P36/INT12
N-ch
DDR
DDR write
Stop mode (SPL=1)
PUL read
PUL
PUL write
Note:
When the ON setting of the pull-up resistor is selected by the pull-up setting register, the pin state will
be "H" level (pull-up state) rather than Hi-Z during stop mode (SPL = 1). During a reset, however, the
pull-up is invalid and the pin remains at Hi-Z.
230
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.4
Registers of External Interrupt Circuit 1
This section describes the registers associated with external interrupt circuit 1.
■ Registers Associated with External Interrupt Circuit 1
Figure 10.4-1 Registers Associated with External Interrupt Circuit 1
EIC1 (External interrupt 1 control register 1)
Address
0024H
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
INT11
EIC2 (External interrupt 1 control register 2)
INT10
Address
0025H
bit7
bit6
bit5
bit4
bit3
bit2 bit1
bit0
Initial value
----0000B
EIR2 SL21 SL20 EIE2
R/W R/W R/W R/W
INT12
R/W : Readable/Writable
: Unused
231
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.4.1
External Interrupt Control Register 1 (EIC1)
External interrupt control register 1 (EIC1) comprises bits for edge polarity selection
and interrupt control for the INT10 and INT11 external interrupt pins.
■ External Interrupt Control Register 1 (EIC1)
Figure 10.4-2 External Interrupt Control Register 1 (EIC1)
Address
0024H
bit7
EIR1 SL11 SL10
R/W R/W R/W R/W R/W R/W R/W R/W
bit6
bit5
bit4
bit3
bit2
bit1 bit0
Initial value
00000000B
EIE1 EIR0 SL01 SL00 EIE0
EIE0
Interrupt request enable bit 0
0
1
Disables interrupt request outputs
Enables interrupt request outputs
SL01
SL00
Edge polarity selection bits 0
Edge detection OFF
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
External interrupt request flag bit 0
When being read
EIR0
When being written
This bit is cleared
Signal input with specified edge
or edges not detected
0
1
No change, does not affect other
operations
Signal input with specified edge
or edges detected
Interrupt request enable bit 1
EIE1
Disables interrupt request outputs
Enables interrupt request outputs
0
1
SL11
SL10
Edge polarity selection bits 1
0
0
1
1
0
1
0
1
Edge detection OFF
Rising edge
Falling edge
Both edges
External interrupt request flag bit 1
EIR1
When being read
When being written
This bit is cleared
Signal input with specified edge
or edges not detected
0
1
No change, does not affect other
operations
Signal input with specified edge
or edges detected
R/W : Readable/Writable
: Initial value
232
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
Table 10.4-1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 (EIC1) (1/2)
Bit name
Function
•
•
When a signal with an edge or edges corresponding to edge polarity selected by
edge polarity selection bits (SL11, SL10) is input to INT11 external interrupt
pin, this bit is set to "1".
When this bit and interrupt request enable bit 1 (EIE1) are "1", the interrupt
request is output.
EIR1:
External interrupt
request flag bit1
bit7
•
•
Writing "0" clears this bit; writing "1" does not affect this bit (no change).
These bits are used to select the polarity of an edge or edges of a signal pulse that
triggers an interrupt when the signal is input to INT11 external interrupt pin.
•
•
When these bits provide a value of "00 ", edge detection is not performed and
B
interrupt requests are not generated.
SL11, SL10:
Edge polarity
selection bits 1
bit6,
bit5
These bits may specify "01 ", indicating a rising edge, "10 ", a falling edge, or
B
B
"11 ", both edges to be detected.
B
Note:
If an edge is selected while edge detection is OFF, edge detection may be
performed unconditionally. Always clear the EIR0 bit after selecting an edge.
This bit enables or disables interrupt request outputs to CPU. When this bit and
external interrupt request flag bit 1 (EIR1) are "1", the interrupt request is output.
Notes:
EIE1:
bit4
bit3
Interrupt request
enable bit 1
•
When using the external interrupt pin, write "0" for bit5 of the port data direction
register (DDR3) so that the pin serves inputs only.
Regardless of the interrupt request enable bit state, the state of the external
interrupt pin can be read directly from the port data register (PDR3).
•
•
•
When a signal with an edge or edges corresponding to edge polarity selected by
edge polarity selection bits (SL01, SL00) is input to INT10 external interrupt
pin, this bit is set to "1".
When this bit and interrupt request enable bit 0 (EIE0) are "1", the interrupt
request is output.
EIR0:
External interrupt
request flag bit 0
•
•
Writing "0" clears this bit, and writing "1" does not affect this bit.
These bits are used to select the polarity of an edge or edges of a signal pulse that
triggers an interrupt when the signal is input to the INT10 external interrupt pin.
•
•
When these bits provide a value of "00 ", edge detection is not performed and
B
interrupt requests are not generated.
SL01, SL00:
Edge polarity
selection bits 0
bit2,
bit1
These bits may specify "01 ", indicating a rising edge, "10 ", a falling edge, or
B
B
"11 ", both edges to be detected.
B
Note:
If edge is selected when edge detection is OFF, edge detection may be performed
unconditionally. Always clear the EIR0 bit after selecting an edge.
233
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
Table 10.4-1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 (EIC1) (2/2)
Bit name
Function
This bit enables or disables interrupt request outputs to the CPU. When this bit and
external interrupt request flag bit 0 (EIR0) are "1", the interrupt request is output.
Notes:
EIE0:
Interrupt request
enable bit 0
•
When using the external interrupt pin, write "0" for bit4 of the port data direction
register (DDR3) so that the pin serves inputs only. Write "0" for bit1 of the timer
output control register (TCR2) for the 8/16-bit capture timer/counter to set the
port input function on.
bit0
•
Regardless of the interrupt request enable bit state, the state of the external
interrupt pin can be read directly from the port data register (PDR3).
234
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.4.2
External Interrupt Control Register 2 (EIC2)
As with external interrupt control register 1 (EIC1), external interrupt control register 2
(EIC2) comprises bits for edge polarity selection and interrupt control for the INT12
external interrupt pin.
■ External Interrupt Control Register 2 (EIC2)
Figure 10.4-3 External Interrupt Control Register 2 (EIC2)
bit7 bit6
bit5
bit4 bit3
bit2
bit1
bit0
Address
Initial value
0025H
EIR2
----0000B
SL21 SL20 EIE2
R/W R/W R/W R/W
Interrupt request enable bit 2
Disables interrupt request outputs
Enables interrupt request outputs
EIE2
0
1
SL21
SL20
Edge polarity selection bits 2
Edge detection OFF
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
External interrupt request flag bit 2
When being written
EIR2
When being read
Signal input with specified edge
0
1
This bit is cleared
or edges not detected
No change, not affecting other
Signal input with specified edge
operation
or edges detected
R/W : Readable/Writable
: Unused
: Initial value
235
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
Table 10.4-2 Explanation of Functions of Each Bit in External Interrupt Control Register 2 (EIC2)
Bit name
Function
bit7
to
bit4
•
•
Bit value is undefined when being read.
Written value does not affect other operations.
Unused bits
•
When a signal with an edge or edges corresponding to edge polarity
selected by edge polarity selection bits 2 (SL21, SL20) is input to the
INT12 external interrupt pin, this bit is set to "1".
When this bit and interrupt request enable bit 2 (EIE2) are "1", the
interrupt request is output.
EIR2:
bit3
External interrupt
request flag bit 2
•
•
Writing "0" clears this bit, and writing "1" does not affect this bit (no
change).
•
These bits are used to select the polarity of an edge or edges of a signal
pulse that triggers an interrupt when the signal is input to the INT12
external interrupt pin.
•
•
When these bits provide a value of "00 ", edge detection is not
B
SL21, SL20:
Edge polarity selection
bits 2
performed and interrupt requests are not generated.
bit2
bit1
These bits may specify "01 ", indicating a rising edge, "10 ", a falling
B
B
edge, or "11 ", both edges to be detected.
B
Note:
If edge is selected while edge detection is OFF, edge detection may be
performed unconditionally. Always clear EIR2 bit after selecting an edge.
This bit enables or disables interrupt request outputs to the CPU. When this
bit and external interrupt request flag bit 2 (EIR2) are "1", the interrupt
request is output.
Notes:
EIE2:
Interrupt request
enable bit 2
bit0
•
When using the external interrupt pin, write "0" for bit6 of the port data
direction register (DDR3) so that the pin serves inputs only.
•
Regardless of the interrupt request enable bit state, the state of external
interrupt pin can be read directly from the port data register (PDR3).
236
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.5
Interrupt of External Interrupt Circuit 1
The detection of a signal with the specified edge or edges, input to any of the external
interrupt pins, triggers external interrupt circuit 1 to generate an interrupt request.
■ Interrupt during the Operation of External Interrupt Circuit 1
When external interrupt circuit 1 detects the specified edge or edges of external interrupt input at a pin, an
external interrupt request flag bit (EIC1, EIC2:EIR0 to EIR2) corresponding to the pin is set to "1". At this
time, if the interrupt request enable bit corresponding to the pin contains the value indicating the enabled
state (EIC1, EIC2:EIE0 to EIE2=1), the external interrupt circuit 1 generates and then issues the
appropriate interrupt request (IRQ0, IRQ1, IRQ2) to the CPU.
Write "0" for the external interrupt request flag bit within the interrupt processing routine for the interrupt
request, thus clearing the interrupt request.
If external interrupts are not used for recovery from stop mode, set the edge polarity selection bits to "00 "
B
and the interrupt enable bits to "0".
Notes:
•
When edge detection OFF is selected and set with edge polarity selection bits, the occurring input is
held as is before entry to the internal edge detecting circuit. If edge is selected during the edge detection
OFF state, edge detection may be performed unconditionally with the external interrupt request flag bit
set to "1".
•
When interrupts are set enabled (EIC1, EIC2:EIE0 to EIE2=1) after the release from the reset state,
clear the appropriate external interrupt request flag bit (EIR0 to EIR2=0) at the same time.
If the external interrupt request flag bit is "1" with the interrupt request enable bit containing a value
indicating enable state, a return from the interrupt processing is not possible. Always clear the external
interrupt request flag bit within the interrupt processing routine.
•
For edge selection during the edge detection OFF state, specify an edge or edges when interrupt request
outputs are disabled and then clear the external interrupt request flag bit.
Regardless of the value of the appropriate interrupt request enable bit (EIE0 to EIE2), the external
interrupt request flag bit is set to "1" whenever edge polarity matching is detected.
Only external interrupt circuits 1 and 2 can execute a release from stop mode by an interrupt.
With the external interrupt request flag bit being set to "1", when the interrupt request enable bit setting
changes from disable to enable (0 →1), an interrupt request is generated immediately.
237
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
■ Register Associated with Interrupt Generation by External Interrupt Circuit 1 and
Vector Table
Table 10.5-1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table
Interrupt level setting register
Register Bit for setting level
Vector table address
Upper Lower
Interrupt designation
IRQ0
IRQ1
IRQ2
L01 (bit1)
L11 (bit3)
L21 (bit5)
L00 (bit0)
L10 (bit2)
L20 (bit4)
FFFA
FFFB
H
H
H
H
H
H
ILR1 (007B )
FFF8
FFF6
FFF9
FFF7
H
■ Exercise Caution when Changing Edge Polarity Selection
When changing edge polarity for INT10 to INT12, always write "0" for the appropriate EIR bit to prevent
unintended interrupt generation.
238
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.6
Operations of External Interrupt Circuit 1
The external interrupt circuit 1 can detect a specified edge or edges of a signal input to
any of the external interrupt pins.
■ Operation of External Interrupt Circuit 1
To operate external interrupt circuit 1, the bits of the registers must be set as shown in Figure 10.6-1 .
Figure 10.6-1 Setting External Interrupt Circuit 1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIC1
EIC2
DDR3
TCR2
EIR1
SL11 SL10 EIE1
EIR0
SL01 SL00 EIE0
EIR2
SL21 SL20 EIE2
0
0
0
PEN TSEL
0
: Used bit
: Unused bit
0
: Set "0"
When the polarity of an edge or edges of a signal input from one of the external interrupt pins 1 (INT10 to
INT12) matches the selected edge polarity for the pin stored in the appropriate external interrupt control
register (EIC1, EIC2:SL00 to SL21), one of the external interrupt request flag bits (EIC1, EIC2:EIR0 to
EIR2) corresponding to the pin is set to "1".
239
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
Figure 10.6-2 shows the operation when an external interrupt is input to the INT10 pin.
Figure 10.6-2 Operation of External Interrupt 1 (INT10)
Pulse waveform
input to INT10 pin
Cleared when EIE0 bit Cleared by
is set program
Interrupt request flag bit is
cleared by the program
EIR0 bit
EIE0 bit
SL01 bit
SL00 bit
IRQ0
Edge detection
OFF
Rising edge
Falling edge
Both edges
Note:
Even when the pin is used as an external interrupt input pin, the pin state can be read directly from the
port data register (PDR3).
240
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
10.7
Program Example for External Interrupt Circuit 1
An example of programming external interrupt circuit 1 is given below.
■ External Interrupt Circuit 1 Programming Example
● Processing specification
External interrupt circuit 1 detects the rising edge of a pulse input to the INT10 pin and generates an
interrupt.
● Coding example
DDR3
EIC1
EQU
EQU
EQU
000DH
0024H
0020H
; Address of port data direction register (DDR)
; External interrupt control register 1
; Address of 8/16-bit capture timer output control
register
TCR2
ILR1
EQU
007BH
; Setting of interrupt level setting register 1
EIR0
SL01
SL00
EIE0
EQU
EQU
EQU
EQU
EIC1:3
EIC1:2
EIC1:1
EIC1:0
ABS
; Definition of external interrupt request flag bit
; Definition of edge polarity selection bits
; Definition of edge polarity selection bits
; Definition of interrupt request enable bit
; [DATA SEGMENT]
INT_V DSEG
ORG
0FFFAH
WARI
IRQ1
INT_V ENDS
;------------------------Main program--------------------------------------------------------------------------------
DW
; Interrupt vector (INT1) setting
CSEG
; [CODE SEGMENT]
; Stack pointer (SP) is assumed to have been initialized.
:
;
CLRI
CLRB
MOV
MOV
MOV
CLRB
SETB
CLRB
SETB
SETI
:
; Disable interrupts.
EIR1
; Clear external interrupt request flag.
TCR2,#00000000B ; Set pin P34/TO/INT10 to serve port inputs.
DDR3,#00000000B ; Set P34 to serve inputs only.
ILR1,#11111110B ; Set interrupt level at 2.
SL01
SL00
EIR0
EIE0
; Select rising edge.
;
; Clear external interrupt request flag.
; Enable interrupt request outputs.
; Enable interrupts.
;------------------------Interrupt processing routing----------------------------------------------------------------
WARI
CLRB
EIE0
A
; Clear external interrupt request flag (INT0).
PUSHW
XCHW
A,T
241
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
PUSHW
:
A
User processing
:
POPW
XCHW
POPW
RETI
A
A,T
A
ENDS
;--------------------------------------------------------------------------------------------------------------------
END
242
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.1
Overview of External Interrupt Circuit 2
External interrupt circuit 2 detects the predetermined level of a signal input to any of the
eight external interrupt pins and generates and issues an interrupt request to the CPU.
■ Functions of External Interrupt Circuit 2 (Level Detection)
External interrupt circuit 2 functions to detect an "L" level signal input to any of the external interrupt pins
and generate and issue an interrupt request to the CPU, thereby enabling recovery from standby mode and a
transition to normal operating state (main clock operation mode).
•
•
External interrupt pins: Eight pins (P00/INT20/AN4 to P03/INT23/AN7, P04/INT24 to P07/INT27)
External interrupt triggering: Input of an "L" level signal to one of the above external interrupt pins
triggers an external interrupt.
•
•
•
Interrupt control: An external interrupt 2 control register (EIE2) enables or disables external interrupt
inputs.
Interrupt flag:Detection of the "L" level is indicated by an external interrupt request flag bit of the
external interrupt 2 flag register (EIF2).
Interrupt request: An interrupt request is generated if the state of one of the above external interrupt pins
is "L" (IRQA).
244
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.2
Configuration of External Interrupt Circuit 2
The external interrupt circuit 2 comprises the following three blocks:
• Interrupt request generating circuit
• External interrupt 2 control register (EIE2)
• External interrupt 2 flag register (EIF2)
■ Block Diagram of External Interrupt Circuit 2
Figure 11.2-1 Block Diagram of External Interrupt Circuit 2
External interrupt 2 control register (EIE2)
IE27 IE26 IE25 IE24 IE23 IE22 IE21
External interrupt 2 flag register (EIF2)
IF20
IE20
Interrupt request generating circuit
Pin
Pin
P00/INT20/AN4
P01/INT21/AN5
Pin
Pin
Pin
Pin
Pin
Pin
P02/INT22/AN6
P03/INT23/AN7
P04/INT24
External interrupt
request
P05/INT25
IRQA
P06/INT26
P07/ INT27
● Interrupt request generating circuit
The interrupt request generating circuit generates an interrupt request signal in accordance with the signal
input to one of the external interrupt pins (INT20 to INT27) and the contents of an external interrupt input
enable bit.
● External interrupt 2 control register (EIE2)
The external interrupt input enable bits (IE20 to IE27) enable or disable "L" level input from the external
interrupt pins, with each bit corresponding to a pin.
● External interrupt 2 flag register (EIF2)
The external interrupt request flag bit (IF20) is used to hold or clear an interrupt request signal.
● Trigger causing external interrupt circuit 2 to generate an interrupt
•
IRQA:When an "L" level signal is input to any of the external interrupt pins INT20 to INT27 and the
external interrupt input enable bit corresponding to the pin is "1", external interrupt circuit 2
generates an interrupt request.
245
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.3
Pins of External Interrupt Circuit 2
This section describes the pins associated with external interrupt circuit 2 and
illustrates a block diagram of circuitry terminating at the pins with reference to the
registers and interrupt triggering.
■ Pins Associated with External Interrupt Circuit 2
The pins associated with external interrupt circuit 2 are eight external interrupt pins.
● P00/INT20/AN4 to P03/INT23/AN7
These external interrupt pins function as external interrupt input pins (hysteresis input) and as the pins of
the general-purpose I/O port and analog inputs.
The P00/INT20/AN4 to P03/INT23/AN7 pins function as external interrupt input pins (INT20 to INT23) if
set to function as an input port by the corresponding bits of the port 0 data direction register (DDR0), if set
to be enabled for external interrupt inputs (ADEN=0) by the corresponding bits of the A/D enable register
(ADEN), and if external interrupt inputs are enabled (EIE2:IE20 to IE27=1) by the external interrupt 2
control register (EIE2). When set to function as an input port by the DDR0 register, the state of these pins
can be read from the port 0 data register (PDR0) at any time.
● P04/INT24 to P07/INT27
These external interrupt pins function as external interrupt input pins (hysteresis input) and also serving as
the pins of the general-purpose I/O port.
The P04/INT24 to P07/INT27 pins function as external interrupt input pins (INT24 to INT27) if set to
function as an input port by the corresponding bits of the port 0 data direction register (DDR0) and if
external interrupt inputs are enabled by the external interrupt 2 control register (EIE2). When set to
function as an input port, the state of these pins can be read from the port 0 data register (PDR0) at any
time.
Table 11.3-1 lists the pins associated with external interrupt circuit 2.
Table 11.3-1 Pins Associated with External Interrupt Circuit 2
External
interrupt pin
Use for external interrupt input
(Interrupt input enabled)
Use for general-purpose I/O port
(Interrupt input disabled)
P00/INT20/AN4
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
P04/INT24
INT20 (EIE2:IE20=1,DDR0:bit0=0,ADEN:ADE4=0)
INT21 (EIE2:IE21=1,DDR0:bit1=0,ADEN:ADE5=0)
INT22 (EIE2:IE22=1,DDR0:bit2=0,ADEN:ADE6=0)
INT23 (EIE2:IE23=1,DDR0:bit3=0,ADEN:ADE7=0)
INT24 (EIE2:IE24=1,DDR0:bit4=0)
P00 (EIE2:IE20=0)
P01 (EIE2:IE21=0)
P02 (EIE2:IE22=0)
P03 (EIE2:IE23=0)
P04 (EIE2:IE24=0)
P05 (EIE2:IE25=0)
P06 (EIE2:IE26=0)
P07 (EIE2:IE27=0)
P05/INT25
INT25 (EIE2:IE25=1,DDR0:bit5=0)
P06/INT26
INT26 (EIE2:IE26=1,DDR0:bit6=0)
P07/INT27
INT27 (EIE2:IE27=1,DDR0:bit7=0)
246
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
■ Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
Circuit 2
Figure 11.3-1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
Circuit 2
P00/INT20/AN4
A/D converter
channel select
A/D converter
enable bit
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
From external
interrupt enable
To A/D
converter's
analog input
INT20, INT21
INT22, INT23
Stop mode
(SPL = 1)
P04/INT24
P05/INT25
P06/INT26
P07/INT27
INT24, INT25
INT26, INT27
PDR
PDR read
Pull-up
resistor
PDR read
(when read-modify-write
is performed)
P-ch
N-ch
Output
latch
PDR write
Pins
P00/INT20/AN4
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
P04/INT24
DDR
DDR write
Stop mode
(SPL = 1)
PUL read
P05/INT25
P06/INT26
PUL
PUL write
P07/INT27
SPL: Pin status setting bit of standby control register (STBC)
Note:
When the ON setting of the pull-up resistor is selected by the pull-up setting register, the pin state will
be "H" level (pull-up state) rather than Hi-Z during stop mode (SPL = 1). During a reset, however, the
pull-up is invalid and the pin remains at Hi-Z.
247
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
■ Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the
External Interrupt Pins
The interrupt enable bits are associated with the external interrupt pins as listed in Table 11.3-2 .
Table 11.3-2 Correspondence between the External Interrupt Enable Bits and the External
Interrupt Pins
Register
Bit name
External interrupt pin
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IE27
IE26
IE25
IE24
IE23
IE22
IE21
IE20
INT27
INT26
INT25
INT24
INT23
INT22
INT21
INT20
EIE2
248
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.4
Registers of External Interrupt Circuit 2
The external interrupt 2 control register (EIE2) is used to enable or disable the external
interrupt pins.
■ Registers Associated with External Interrupt Circuit 2
Figure 11.4-1 Registers Associated with External Interrupt Circuit 2
EIE2 (External interrupt 2 control register)
Address
0036H
bit7
IE27 IE26
R/W R/W
bit6
bit5
bit4
IE24
R/W
bit3
bit2
IE22
R/W
bit1
bit0
Initial value
00000000B
IE25
R/W
IE23
R/W
IE21 IE20
R/W
bit1
R/W
EIF2 (External interrupt 2 flag register)
Address
Initial value
-------0B
bit7
bit6
bit5
bit4
bit3
bit2
bit0
0037H
IF20
R/W
: Readable/Writable
: Unused
R/W
249
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.4.1
External Interrupt 2 Control Register (EIE2)
The external interrupt circuit 2 control register (EIE2) enables or disables the interrupt
inputs to the external interrupt pins INT20 to INT27.
■ External Interrupt Circuit 2 Control Register (EIE2)
Figure 11.4-2 External Interrupt Circuit 2 Control Register (EIE2)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
Initial value
0036H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
External interrupt request enable bits
IE27 to IE20
0
Disables external interrupt request outputs
1
Enables external interrupt request outputs
R/W : Readable/Writable
: Initial value
Table 11.4-1 Correspondence between the Bits of the External Interrupt 2 Control Register
(EIE2) and the External Interrupt Pins
Register
Bit name
External interrupt pin
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IE27
IE26
IE25
IE24
IE23
IE22
IE21
IE20
INT27
INT26
INT25
INT24
INT23
INT22
INT21
INT20
EIE2
250
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Table 11.4-2 Functions of the Bits of the External Interrupt 2 Control Register (EIE2)
Bit name
Function
•
•
These bits enable or disable the interrupt inputs to external
interrupt pins INT20 to INT27.
When one of these bits is set to "1", the corresponding external
interrupt pin functions as an external interrupt input pin and
accepts external interrupt inputs.
•
When the bit is set to "0", the corresponding pin functions as a
general-purpose port, but does not accept external interrupt
inputs.
bit7
to
bit0
IE27 to IE20:
External interrupt
input enable bits
Notes:
• When using a pin as an external interrupt pin, write "0" in the
port 0 data direction register (DDR0) in the bit corresponding to
the pin so that the pin serves inputs only.
• Regardless of the external interrupt input enable bit state, the
state of the external interrupt pin can be read directly from the
port 0 data register (PDR0). For pins INT20 to INT23,
furthermore, write "0" into A/D enable register (ADEN) in the
bits corresponding to the pins to use the pins for external
interrupt inputs.
251
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.4.2
External Interrupt 2 Flag Register (EIF2)
The external interrupt 2 flag register (EIF2) is used to hold the interrupt state by flagging
an interrupt request flag when a level interrupt is detected and then clearing the flag.
■ External Interrupt 2 Flag Register (EIF2)
Figure 11.4-3 External Interrupt 2 Flag Register (EIF2)
Initial value
Address bit7
0037H
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IF20 -------0B
R/W
External interrupt request flag bit
When being read
IF20
When being written
This bit is cleared
No interrupt request
("L" level not detected)
0
1
: Readable/Writable
: Unused
R/W
Interrupt request is generated
("L" level detected)
No change in the bit, does not
affect other operations
: Initial value
Table 11.4-3 Explanation of Functions of Each Bit in External Interrupt 2 Flag Register
(EIF2)
Bit name
Function
bit7
to
bit1
•
•
Bit value is undefined when being read.
The written value does not affect other operations.
Unused bits
•
•
When an "L" level signal is input to one of the external
interrupt pins(INT20 to INT27) for which external
interrupt inputs are enabled, this bit is set to "1".
Writing "0" clears this bit, and writing "1" does not change
this bit state and does not affect other operations.
IF20:
External interrupt
request flag bit
bit0
Note:
The external interrupt enable bits of the external interrupt 2
control register (EIE2:IE20 to IE27) may disable external
interrupt inputs. Interrupt requests continue to be generated
and issued to the CPU until the IF20 bit is cleared to "0".
252
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.5
Interrupt of External Interrupt Circuit 2
An "L" level input signal input to one of the external interrupt pins triggers external
interrupt circuit 2 to generate an interrupt.
■ Interrupt during the Operation of External Interrupt Circuit 2
When an "L" level signal is input to one of the external interrupt pins for which interrupt inputs are
enabled, the external interrupt request flag bit (EIF2:IF20) is set to "1" and external interrupt circuit 2
generates and issues an interrupt request (IRQA) to the CPU. Write "0" for the IF20 bit within the interrupt
processing routine, thus clearing the interrupt request.
When the external interrupt request flag bit (IF20) is set to "1", external interrupt circuit 2 generates the
interrupt request, even if external interrupt inputs to the pin are set to disabled by the bit corresponding to
the pin among the interrupt enable bits (IE20 to IE27) of the external interrupt 2 control register (EIE2),
until the IF20 bit is cleared. Therefore, the IF20 bit must always be cleared.
If the "L" level input to the external interrupt pin continues as it is, even if the IF20 bit is cleared with
external interrupt inputs to the pin remaining enabled, the IF20 bit is immediately set to "1" again. Disable
external interrupt inputs to the pin or remove the cause of the external interrupt as required.
Notes:
•
When enabling interrupts to the CPU following a release from the reset state, clear the IF20 bit in
advance.
•
"L" level inputs to external interrupt pins (INT20 to INT27) trigger external interrupt circuit 2 to
generate the same interrupt request (IRQA). Thus, when an external interrupt input is detected, it is
necessary to identify the pin at which the input occurs by reading the port 0 data register (PDR0)
before the input changes to "H" level.
Only external interrupt circuits 1 and 2 can execute a release from the stop mode by an interrupt.
■ Register Associated with Interrupt Generation by External Interrupt Circuit 2 and
Vector Table
Table 11.5-1 Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector
Table
Interrupt level setting register
Register Bit for setting level
ILR3 (007D )
Vector table address
Interrupt designation
Upper
Lower
FFE6
FFE7
IRQA
LA1 (bit5) LA0 (bit4)
H
H
H
253
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.6
Operations of External Interrupt Circuit 2
External interrupt circuit 2 detects "L" level at any of the external interrupt pins, then
generates and issues an interrupt request to the CPU.
■ Operation of External Interrupt Circuit 2
To operate the external interrupt circuit 2, the bits of the registers must be set as shown in Figure 11.6-1 .
Figure 11.6-1 Setting External Interrupt Circuit 2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EIE2
EIF2
IE27
IE26
IE25
IE24
IE23
IE22
IE21
IE20
IF20
0
DDR0
ADEN
0
0
0
0
0
0
0
0
0
0
0
: Used bit
: Unused bit
: Set "0"
0
When an "L" level signal is input to an external interrupt pin among the pins INT20 to INT27 with external
interrupt inputs being enabled by one of the IE20 to IE27 bits corresponding to the pin, external interrupt
circuit 2 generates and issues an IRQA interrupt request to the CPU.
Figure 11.6-2 shows the operation of external interrupt circuit 2 (when the INT20/AN4 pin is used).
254
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Figure 11.6-2 Operation of External Interrupt 2 (INT20)
Pulse waveform input
to INT20/AN4 pin
(Detection of the "L" level)
External interrupt input enabled state
EIE2:IE20
Clear the bit within interrupt
processing routine.
EIF2:IF20
(IRQA state also
changes accordingly.)
Interrupt processing
RETI
Interrupt processing
Operation of interrupt
processing routine for
IRQA
RETI
Can be read at any time.
PDR0:bit0
Note:
Even when the pin is used as an external interrupt input pin, the pin state can be read directly from the
port 0 data register (PDR0).
255
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.7
Program Example for External Interrupt Circuit 2
An example of programming external interrupt circuit 2 is given below.
■ Program Example for External Interrupt Circuit 2
● Processing specification
The external interrupt circuit 2 detects an "L" level signal input to the P00/INT20/AN4 pin and generates
an interrupt.
● Coding example
DDR0 EQU
ADEN EQU
0001H
0034H
0036H
0037H
; Address of the port data direction register
; Address of the A/D enable register
EIE2
EIF2
EQU
EQU
; Address of the external interrupt 2 control register
; Address of the external interrupt 2 flag register
IF20
EQU
EQU
EIF2:0
007DH
; Definition of the external interrupt request flag bit
; Address of the interrupt level setting register
; [DATA SEGMENT]
ILR3
INT_V DSEG
ORG
ABS
0FFE6H
WARI
IRQA DW
INT_V ENDS
; Interrupt vector setting
;------------------------Main program--------------------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
; Stack pointer (SP) is assumed to have been initialized.
;
:
CLRI
; Disable interrupts.
CLRB IF20
; Clear external interrupt request flag.
; Set interrupt level to 2.
MOV ILR2,#11111110B
MOV DDR0,#00000000B
MOV ADEN,#00000000B
; Set pin INT20/AN4 to serve inputs only.
; Set pin INT20/AN4 to enable external interrupt inputs.
MOV EIE2,#00000001B
; Enable external interrupt inputs to pin INT20/AN4.
; Enable interrupts.
SETI
:
;------------------------Interrupt processing routine----------------------------------------------------------------
WARI MOV
CLRB
EIE2,#00000000B
IF20
; Disable external interrupt inputs to pin INT20/AN4.
; Clear external interrupt request flag.
256
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
PUSHW
XCHW
PUSHW
:
A
A,T
A
User processing
:
POPW
XCHW
POPW
RETI
A
A,T
A
ENDS
;--------------------------------------------------------------------------------------------------------------------
END
257
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
258
CHAPTER 12 A/D CONVERTER
12.1
Overview of A/D Converter
An A/D converter, which is of a 10-bit successive approximation type, selects an input
signal from eight channel analog inputs. The A/D converter can be activated with
software, an internal clock, or the output of an 8/16-bit capture timer/counter (16-bit
mode).
■ A/D Conversion Functions
These functions convert the analog voltage (input voltage) input from an analog input to 10-bit digital
values.
•
•
An analog input can be selected from eight channels.
The conversion speed is 38 instruction cycles (when the main clock oscillation frequency is 12.5 MHz,
the speed is 12.2 µs).
•
•
When A/D conversion is completed, an interrupt occurs.
Software can determine that the conversion has been completed.
To activate A/D conversion functions, follow one of the methods given below.
•
•
Activation with a software program.
Continuous activation through the output of a time-base timer (main clock oscillation frequency divided
8
by 2 ).
•
Continuous activation through the output of an 8/16-bit capture timer/counter (16-bit mode).
260
CHAPTER 12 A/D CONVERTER
12.2
Configuration of A/D Converter
The A/D converter consists of the following nine blocks.
• Clock selector (input clock selector for activation of A/D conversion)
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
• A/D data register (ADDH and ADDL)
• A/D control register 1 (ADC1)
• A/D control register 2 (ADC2)
■ Block Diagram of the A/D Converter
Figure 12.2-1 Block Diagram of the A/D Converter
A/D control register 2 (ADC2)
RESV4
ADCK ADIE RESV2 EXT
RESV1
RESV3
TO (output of an 8/16-bit timer)
Clock
selector
8
(output of a time-base
2 /FCH
timer)
P03/INT23/AN7
P02/INT22/AN6
P01/INT21/AN5
P00/INT20/AN4
P43/AN3
Analog
channel
selector
Sample
hold
circuit
Comparator
Control circuit
P42/AN2
P41/AN1
P40/AN0
A/D data register
(ADDH,ADDL)
D/A
converter
ANS2 ANS1 ANS0 ADI ADMV RESV0 AD
A/D control register 1 (ADC1)
IRQ8
: Output of an 8/16-bit capture timer/counter
: Oscillation
TO
FCH
261
CHAPTER 12 A/D CONVERTER
● Clock selector
The clock selector selects the clock to be used to activate A/D conversion while continuous activation is
enabled (ADC2: EXT = 1).
● Analog channel selector
This circuit selects one out of the eight analog inputs.
● Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector. By performing the sample hold
of the voltage input immediately after the activation of A/D conversion, A/D conversion can be performed
without the variance of the input voltage affecting it during A/D conversion (during comparison).
● D/A converter
This generates the voltage that corresponds to the values set in the ADDH and ADDL registers.
● Comparator
This compares the input voltage for which sample hold is performed, with the output voltage of the D/A
converter to determine which is the greater of the two.
● Control circuit
The control circuit has the following function.
•
For A/D conversion functions, this circuit determines the values in turn from the MSB in the 10-bit A/D
data register toward the LSB based on the large and small signals from the comparator. When the
conversion is completed, it sets the interrupt request flag bit (ADC1: ADI).
● A/D data register (ADDH and ADDL)
The high-order 2 bits of 10-bit A/D data are stored in the ADDH register. The low-order 8 bits of 10-bit
A/D data are stored in the ADDL register.
The ADDH and ADDL registers have the following function.
•
For A/D conversion function, these registers store the results of A/D conversion.
● A/D control register 1 (ADC1)
This register is used to enable and disable functions, select an analog input, check statuses, and control
interrupts.
● A/D control register 2 (ADC2)
This register is used to select an input clock, enable and disable interrupts, select functions, and perform
other activities.
● Interrupts of the A/D converter
When the set conditions are satisfied at the completion of A/D conversion for IRQ8, if an interrupt request
output is enabled (ADC2: ADIE = 1), an interrupt request occurs.
262
CHAPTER 12 A/D CONVERTER
12.3
Pins of A/D Converter
This section describes the pins related to the A/D converter and shows a block diagram
of the pins related to the A/D converter.
■ Pins Related to the A/D Converter
The pins related to the A/D converter are P03/INT23/AN7 to P00/INT20/AN4, and P43/AN3 to P40/AN0
pins.
● P03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0
P03/INT23/AN7 to P00/INT20/AN4, and P43/AN3 to P40/AN0 pins can be used as general-purpose I/O
ports (P03 to P00, and P43 to P40) and as analog inputs (AN7 to AN0).
[AN7 to AN0]
When A/D conversion functions are used, input the analog voltage to be converted to these pins. To
enable a pin as the analog input, set "1" to the bit that corresponds to the A/D enable register (ADEN),
set "0" to the bit that corresponds to the port data direction register (DDR0), and switch the output
transistor to OFF, and select one using the bit for selecting an analog input channel (ADC1: ANS0 to
ANS2). Even when the A/D converter is used, pins not used as analog inputs can be used as general-
purpose I/O ports.
263
CHAPTER 12 A/D CONVERTER
■ Block Diagram of the Pins Related to the A/D Converter
Figure 12.3-1 Block Diagram of P03/INT23/AN7 to P00/INT20/AN4 Pins
A/D converter enable bit
(only P00 to P03)
A/D converter
channel select
To the A/D
converter
analog input
To an external interrupt
PDR
From disabling an
external interrupt
PDR read
Stop mode (SPL = 1)
Pull-up
resistor
PDR read
(At read-modify-write)
Pch
Nch
Output
latch
PDR write
Pins
P00/INT20/AN4
P01/INT21/AN5
P02/INT22/AN6
P03/INT23/AN7
DDR
DDR write
Stop mode (SPL = 1)
PUL read
PUL
PUL write
SPL: Pin status setting bit of the standby control register (STBC)
Figure 12.3-2 Block Diagram of P43/AN3 to P40/AN0 Pins
A/D converter
channel select
A/D converter
enable bit
To the A/D
converter
analog input
PDR
Stop mode (SPL = 1)
PDR read
PDR read
(At read-modify-write)
Pch
Output
latch
PDR write
Pins
P40/AN0
P41/AN1
P42/AN2
P43/AN3
Nch
DDR
DDR write
Stop mode
(SPL = 1)
DDR read
OUT read
OUT
OUT write
264
CHAPTER 12 A/D CONVERTER
12.4
Registers of A/D Converter
Figure 12.4-1 shows the registers related to the A/D converter.
■ Registers Related to the A/D Converter
Figure 12.4-1 Registers Related to the A/D Converter
ADC1 (A/D control register 1)
Address bit7
0030
bit6
ANS2 ANS1
bit5
bit4
bit3
bit2
bit1
bit0 Initial value
-0000000
ANS0 ADI ADMV RESV0 AD
H
B
R/W
R/W
R/W
bit4
R/W
R
R/W
R/W
ADC2 (A/D control register 2)
Address bit7
bit6
bit5
bit3
bit2
bit1
bit0
Initial value
0031
H
EXT
R/W
-0000001
B
RESV4 RESV3 ADCK ADIE RESV2
RESV1
R/W
R/W
R/W
R/W
R/W
R/W
ADDH (A/D data register H)
Address
0032
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
R
bit0
R
------XX
H
B
ADDL (A/D data register L)
Address
0033
Initial value
XXXXXXXX
bit7
bit6
bit5
bit4
R
bit3
R
bit2
R
bit1
R
bit0
R
H
B
R
R
R
ADEN (A/D enable register)
Address bit7
bit6 bit5
0034
bit4
bit3
bit2
bit1
bit0
Initial value
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 00000000
H
B
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable/Writable
R
X
: Read only
: Unused
: Undefined
265
CHAPTER 12 A/D CONVERTER
12.4.1
A/D Control Register 1 (ADC1)
A/D control register 1 (ADC1) is used to set the enabling and disabling functions of the
A/D converter, select an analog input, and check the status.
■ A/D Control Register 1 (ADC1)
Figure 12.4-2 A/D Control Register 1 (ADC1)
Address bit7
bit6
ANS2 ANS1
R/W R/W
bit5
bit4
bit3
ADI
R/W
bit2
ADMV RESV0 AD
R/W R/W
bit1
bit0
Initial value
0030
H
ANS0
R/W
-0000000
B
R
A/D conversion activation bit
This bit is enabled only when software is activated
(ADC2: EXT = 0).
Always 0 for at reading.
AD
0
1
A/D conversion functions are not activated.
A/D conversion functions are activated.
RESV0
Reserved bit
0
1
Not changed. This does not affect others.
Not changed. This does not affect others.
ADMV
Converting flag bit
Not during conversion.
During conversion.
0
1
Interrupt request flag bit
ADI
During write
During read
Conversion has not been
completed.
Conversion has been
completed.
0
1
This bit is cleared.
Not changed. This does not
affect others.
ANS2
ANS1
ANS0
Analog input channel selection bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0 pin (P40/AN0)
AN1 pin (P41/AN1)
AN2 pin (P42/AN2)
AN3 pin (P43/AN3)
AN4 pin (P00/INT20/AN4)
AN5 pin (P01/INT21/AN5)
AN6 pin (P02/INT22 /AN6)
AN7 pin (P03/INT23 /AN7)
R/W : Readable/Writable
R
: Read only
: Initial value
266
CHAPTER 12 A/D CONVERTER
Table 12.4-1 Explanation of Functions of Each Bit in the Bits in A/D Control Register 1 (ADC1)
Bit name
Function
•
•
The value during read is not determined.
Write does not affect operations.
bit7
Unused bit
This bit is used to select which pin to be used as an analog input from AN0 to
AN7.
When software is activated (ADC2: EXT = 0), this bit can be rewritten
concurrently with the activation of A/D conversion (AD = 1).
Note:
bit6
to
bit4
ANS2, ANS1, ANS0:
Analog input channel
selection bits
Pins not used as analog inputs can be used as general-purpose ports.
•
•
•
When A/D conversion functions are enabled:
When A/D conversion is completed, "1" is set to this bit.
When this bit and the bit for enabling an interrupt request (ADC2: ADIE) are
"1", an interrupt request is output.
At write, this bit is cleared with "0". When "1" is set to this bit, nothing is
changed or affected by this.
ADI:
bit3
Interrupt request flag
bit
•
This bit indicates that A/D conversion is being performed, when A/D conversion
functions are enabled.
ADMV:
Convertion flag bit
During conversion (comparison), this bit is set to "1".
Note:
bit2
bit1
This bit is read-only. The written value is ignored and nothing is affected by
the value.
RESV0:
Reserved bit
•
•
The value during read is not determined.
Write does not affect operations.
•
•
This bit is used to activate A/D conversion functions with software.
In the state where continuous activation is not performed (ADC2: EXT = 0),
when "1" is set to this bit, A/D conversion functions are activated.
AD:
bit0
A/D conversion
activation bit
Notes:
• Even if "0" is written to this bit, the operation of A/D conversion functions
cannot be stopped. The read value is always "0".
• During continuous activation, this bit is ignored.
267
CHAPTER 12 A/D CONVERTER
12.4.2
A/D Control Register 2 (ADC2)
A/D control register 2 (ADC2) is used to select an input clock, enable and disable an
interrupt and continuous activation.
■ A/D Control Register 2 (ADC2)
Figure 12.4-3 A/D Control Register 2 (ADC2)
Address
0031H
bit7
bit6
bit5 bit4
bit3
bit2
bit1
EXT
bit0
Initial value
-0000001B
ADIE
RESV4 RESV3 ADCK
RESV2
RESV1
R/W R/W R/W R/W R/W R/W R/W
Reserved bit
RESV1
Be sure to write "1" to this bit.
1
Bit for enabling continuous activation
EXT
0
Enables activation by setting the AD bit in the ADC1 register.
Enables continuous activation through the clock selected in the
ADCK bit.
1
Reserved bit
RESV2
0
Be sure to write "0" to this bit.
ADIE
Enabling an interrupt request bit
0
1
Disables the interrupt request output.
Enables the interrupt request output.
Selecting an input clock bit
Enabled only at continuous activation (EXT = 1)
From the time-base timer output (28/FCH).
ADCK
0
1
From the 8/16-bit capture timer/counter output (TO).
Reserved bits
RESV3 RESV4
Be sure to write 00B to these bits.
0
0
R/W : Readable/Writable
: Unused
: Initial value
268
CHAPTER 12 A/D CONVERTER
Table 12.4-2 Explanation of Functions of Each Bit in A/D Control Register 2 (ADC2)
Bit name
Function
•
•
The value during read is not determined.
Write does not affect operations.
bit7
Unused bit
•
•
This bit is a reserved bit.
bit6,
bit5
RESV4,RESV3:
Reserved bits
Be sure to write 00 to these bits.
B
bit4
ADCK:
Selecting an input
clock bit
This bit is used to select an input clock for activation of A/D conversion
functions in the state where continuous activation is performed (EXT = 1).
When this bit is "0", the internal clock with an oscillation frequency (selected
8
using the output of a time-base timer) divided by 2 is selected. When "1", the
output of an 8/16-bit capture timer/counter (TO: 16-bit mode) is selected.
ADIE:
Enabling an interrupt
request bit
This bit is used to enable and disable the output of an interrupt to the CPU.
When this bit and the interrupt request flag bit (ADC1: ADI) are "1", an
interrupt request is output.
bit3
bit2
RESV2:
Reserved bit
•
•
This bit is a reserved bit.
Be sure to write "0" to this bit.
This bit is used to select whether the A/D conversion functions are to be
activated with software or activated continuously in synchronization with an
input clock.
EXT:
bit1
bit0
Bit for enabling
continuous activation
When this bit is "0", software activation with the bit for activating A/D
conversion (ADC1: AD) is enabled. When "1", continuous activation on the
rising edge of the clock selected using the bit for selecting an input clock
(ADC2: ADCK) is enabled.
RESV1:
Reserved bit
•
•
This bit is a reserved bit.
Be sure to write "1" to this bit.
269
CHAPTER 12 A/D CONVERTER
12.4.3
A/D Data Register (ADDH and ADDL)
A/D data register (ADDH and ADDL) stores the results of A/D conversion at 10-bit A/D
conversion.
The high-order 2 bits of 10-bit data correspond to the ADDH register. The low-order 8
bits correspond to the ADDL register.
■ A/D Data Register (ADDH and ADDL)
Figure 12.4-4 shows the bit configuration of the A/D data registers.
Figure 12.4-4 A/D Data Registers (ADDH and ADDL)
ADDH (A/D data register H)
Address
Initial value
------XXB
bit7 bit6
bit5
bit4
bit3
bit2
bit1 bit0
0032H
R
R
ADDL (A/D data register L)
Address
0033H
bit7
bit6
bit5
bit4
R
bit3 bit2
bit1 bit0 Initial value
XXXXXXXXB
R
R
R
R
R
R
R
R
X
: Read only
: Undefined
Of the 10-bit A/D data, the high-order 2 bits correspond to bits 1 and 0 in the ADDH register. The low-
order 8 bits correspond to bits 7 to 0 in the ADDL register.
● When A/D conversion functions are enabled
When A/D conversion is activated, after about 38 instruction cycles, the data on the conversion results are
fixed and stored to these registers. Therefore, after A/D conversion, read these registers (conversion
results), write "0" to the ADI bit (bit3) in the ADC1 register until the next A/D conversion is completed,
and clear the flags after A/D conversion. During A/D conversion, the values in these registers are not
determined. When A/D conversion functions are enabled, these registers function as read-only registers.
270
CHAPTER 12 A/D CONVERTER
12.4.4
A/D Enable Register (ADEN)
The ADEN register is used to select the analog input port that corresponds to different
pins. Writing "1" to an appropriate ADEN register bit enables analog input.
■ A/D Enable Register (ADEN)
Figure 12.4-5 shows the bit configuration of the A/D enable register.
Figure 12.4-5 A/D Enable Register (ADEN)
bit7
bit6
bit5
bit4
bit3
ADE3 ADE2 ADE1
R/W R/W R/W R/W R/W R/W R/W R/W
bit2
bit1
bit0
Address
Initial value
0034H ADE7 ADE6 ADE5 ADE4
ADE0 00000000B
ADE7 to ADE0
A/D input bits
0
1
Port input
Analog input
R/W : Readable/Writable
: Initial value
An A/D input port can be used as a general-purpose I/O port.
The ADEN register is used to select the port that corresponds to the analog input.
Set "1" to the corresponding bit in the ADEN register for the port to be used for analog input. This prevents
the DC pass when the middle level voltage is applied to the A/D input port.
When this register is to be used as the A/D input port, do not select the bit that indicates use of a pull-up
resistor from the pull-up setting register.
271
CHAPTER 12 A/D CONVERTER
12.5
Interrupt of A/D Converter
A factor for an interrupt of the A/D converter is the following.
• Completion of conversion when A/D conversion functions are enabled
■ Interrupt when A/D Conversion Functions are Enabled
When A/D conversion is completed, the interrupt request flag bit (ADC1: ADI) is set to "1". At this time, if
the bit for enabling an interrupt request is enabled (ADC2: ADIE = 1), an interrupt request to the CPU
(IRQ8) occurs. Write "0" to the ADI bit using the routine for interrupt handling to clear the interrupt
request.
The ADI bit is set when A/D conversion is completed, irrespective of the value of the ADIE bit.
Note:
When the ADI bit is "1", if the ADIE bit is enabled (changed from "0" to "1"), an interrupt request
occurs immediately.
■ Register and Vector Table Related to the Interrupt of the A/D Converter
Table 12.5-1 Register and Vector Table Related to the Interrupt of the A/D Converter
Register to set the interrupt level
Register Bit to be set
ILR3 (007D )
Address of the vector table
Interrupt name
High order
Low order
FFEA
FFEB
IRQ8
L81 (bit1) L80 (bit0)
H
H
H
272
CHAPTER 12 A/D CONVERTER
12.6
Operations of A/D Converter Functions
The A/D converter can be activated with software or activated continuously.
■ Activating the A/D Converter Functions
● Software activation
To activate A/D conversion functions with software, set registers as shown in Figure 12.6-1 .
Figure 12.6-1 Setting A/D Conversion Functions (at Software Activation)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADC1
ADC2
ANS2 ANS1 ANS0 ADI
RESV0 AD
1
ADMV
RESV4 RESV3 ADCK ADIE RESV2 EXT RESV1
0
0
0
0
1
The results of A/D conversion are stored.
The results of A/D conversion are stored.
ADDH
ADDL
ADEN
: Used bit
: Unused bit
1
0
: Set "1"
: Set "0"
: Set "1" to an appropriate bit
When A/D conversion is activated, the operations of A/D conversion functions are started. In addition,
even during conversion, A/D conversion functions can be reactivated.
● Continuous activation
To activate A/D conversion functions continuously, set registers as shown in Figure 12.6-2 .
273
CHAPTER 12 A/D CONVERTER
Figure 12.6-2 Setting A/D Conversion Functions (at Continuous Activation)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADC1
ADC2
ANS2 ANS1 ANS0 ADI ADMV RESV0 AD
RESV4 RESV3 ADCK ADIE RESV2 EXT RESV1
0
0
0
1
1
ADDH
ADDL
ADEN
The results of A/D conversion are stored.
The results of A/D conversion are stored.
: Used bit
: Unused bit
: Set "1"
: Set "0"
1
0
: Set "1" to an appropriate bit
When continuous activation is enabled, A/D conversion is activated on a rising edge of the selected input
clock and the operations of A/D conversion functions are started. When continuous activation is disabled
(ADC2: EXT = 0), continuous activation is stopped and activation with software is possible.
■ Operations of A/D Conversion Functions
The operations of the A/D converter are described here. It takes about 38 instruction cycles from activating
A/D conversion to completing it.
1. When A/D conversion is activated, the conversion in-progress flag bit is set (ADC1: ADMV = 1), and
the analog input set is connected to the sample hold circuit.
2. During about 16 instruction cycles, the voltage of the analog input is captured and held in the capacitor
for internal sample hold. This voltage is held until A/D conversion has been completed.
3. The comparator compares the voltage captured and held in the capacitor for sample hold with the
reference voltage for A/D conversion from the MSB to the LSB. The results are transferred to the
ADDH and ADDL registers in turn.
4. When all the results have been transferred to the ADDH and ADDL registers, the conversion in-
progress flag bit is cleared (ADC1: ADMV = 0), and the interrupt request flag bit is set (ADC1: ADI =
1).
274
CHAPTER 12 A/D CONVERTER
12.7
Notes on Using A/D Converter
This section describes notes on using the A/D converter.
■ Notes on Using the A/D Converter
● Input impedance of the analog input
The A/D converter contains the sample hold circuit as shown in Figure 12.7-1 , captures the voltage of the
analog input, and holds it in the capacitor for sample hold in about 16 instruction cycles, after activation of
A/D conversion. Accordingly, when the output impedance of the external circuit of the analog input is high,
the analog input voltage may not be stabilized during analog input sampling period. Therefore, set the
output impedance of the external circuit to a sufficiently low level (lower than about 4 kΩ). If the output
impedance of the external circuit cannot be set low, it is recommended that a capacitor with about 0.1 µF be
added externally to the analog input.
Figure 12.7-1 Equivalent Circuit of Analog Input
MB89202/F202RA series
Sample hold circuit
AN0 to AN7
Converter
R
C
Selecting
an analog
channel
After activation of A/D conversion,
close 16 instruction cycles
● Notes on setting using a program
•
When A/D conversion functions are enabled, the values in the ADDH and ADDL registers are held
without being changed until the activation of A/D conversion. However, once A/D conversion is
activated, the values in the ADDH and ADDL registers become undefined immediately.
•
When A/D conversion functions are enabled, do not reselect an analog input channel (ADC1: ANS3 to
ANS0). Especially, during continuous activation, disable continuous activation (ADC2: EXT = 0), and
wait for the conversion in-progress flag bit (ADC1: ADMV) to be "0" for reselection.
•
•
The A/D converter is stopped via a reset and activation of the stop mode, and all registers are initialized.
When the interrupt request flag bit (ADC1: ADI) is "1" and an interrupt request is enabled (ADC2:
ADIE = 1), recovery from interrupt handling is no longer possible. Be sure to clear the ADI bit.
Note:
When A/D conversion is completed, if the next conversion is reactivated, the interrupt request flag bit
(ADC1: ADI) is not set.
275
CHAPTER 12 A/D CONVERTER
● Notes on interrupt requests
If A/D conversion is reactivated (ADC1: AD = 1) and terminated at the same time, the interrupt request
flag bit (ADC1: ADI) is not set.
● Conversion time
Changing the oscillation frequency or clock speed (gear functions) affects the conversion speed of A/D
conversion functions.
● Input clock of continuous activation
The output of an 8/16-bit capture timer/counter is affected by gear functions. The output of a time-base
timer is not affected by gear functions. Clearing a time-base timer affects cycles.
Since the output of an 8/16-bit capture timer/counter is the output of the 16-bit mode, the 8-bit mode cannot
be used.
276
CHAPTER 12 A/D CONVERTER
12.8
Program Example for A/D Converter
This section shows a program example of the 10-bit A/D converter.
■ Program Example of the A/D Conversion Functions
● Processing specifications
The analog voltage to be applied to the AN0 pin is converted to digital voltage through software activation.
In this example, completion of conversion is detected in a loop in the program without using interrupts.
● Coding example
PDR4 EQU
ADC1 EQU
ADC2 EQU
ADDH EQU
ADDL EQU
ADEN EQU
000FH
0030H
; Address of port 4 data register 4
; Address of A/D control register 1
; Address of A/D control register 2
; Address of A/D data register H
; Address of A/D data register L
; Enables the A/D input pin.
0031H
0032H
0033H
0034H
AN0
ADE0 EQU
ADI EQU
ADMV EQU
EQU
PDR4:0
ADEN:0
ADC1:3
ADC1:2
ADC1:0
; Defines the AN0 analog input.
; Enables the AN0 analog input.
; Defines the interrupt request flag bit.
; Defines the conversion in-progress flag bit.
; Defines the bit for activating A/D conversion (software
activation).
AD
EQU
EXT
EQU
ADC2:1
; Defines the bit for enabling continuous activation.
;------------------------Main program--------------------------------------------------------------------------------
CSEG
:
; [CODE SEGMENT]
SETB
CLRI
SETB
CLRB
AN0
; Sets the P40/AN0 pin to the analog input.
; Disables interrupts.
ADE0
EXT
; Enables the AN0 pin.
; Disables continuous activation.
AD_WAIT
BBS
ADMV,AD_WAIT ; Loop for verifying that the A/D converter is stopped.
ADC1,#00000000B ; Selects analog input channel 0 (AN0), clears the
interrupt request flag, does not perform software
activation.
MOV
MOV
ADC2,#00000001B ; Disables the interrupt request output, selects A/D
conversion functions, and selects software activation.
; Enables interrupts.
SETI
:
SETB
AD
; Activates software.
AD_CONV
BBS
ADMV,AD_CONV ; Loop for waiting for completion of A/D conversion
(at about 12.2 µs/12.5 MHz)
CLRB
ADI
; Clears the interrupt request flag.
277
CHAPTER 12 A/D CONVERTER
MOV
A,ADDL
A,ADDH
; Reads A/D conversion data (low-order 8 bits).
; Reads A/D conversion data (high-order 2 bits).
MOV
:
:
ENDS
;--------------------------------------------------------------------------------------------------------------------
END
278
CHAPTER 13 UART
13.1
Overview of UART
UART is a general-purpose communication interface for serial data. UART allows
variable-length serial data to be transferred synchronously or asynchronously with a
clock. The transfer format is NRZ. The dedicated baud rate generator, external clock, or
internal timer (8-bit PWM timer) settings determine the data transfer format.
■ Functions of UART
UART supports (serial I/O) functions for sending serial data to, or receiving serial data from a CPU or
peripheral functions.
The full-duplex double-buffer enables bi-directional full-duplex communication.
•
•
Synchronous data transfer mode or asynchronous data transfer mode can be selected.
The internal baud rate generator allows one of 14 baud rates to be selected. Also, external clock input
and 8-bit PWM timer output allow user-defined baud rates to be specified.
•
The length of data is variable. When no parity is used, 7 bits to 9 bits are available. When parity is used,
•
The data transfer format is NRZ (Non Return to Zero).
Table 13.1-2 provides the transfer rates of the dedicated baud rate generator, and Table 13.1-3 provides the
transfer rates of the external clock.
Table 13.1-1 UART Operating Modes
Data length
Operating mode
Synchronization mode
Stop bit length
Parity not used
Parity used
0
1
2
3
7 bits
8 bits
6 bits
7 bits
-
Synchronous/asynchronous
Synchronous/asynchronous
Synchronous/asynchronous
Synchronous/asynchronous
1 bit or 2 bits *
1 bit or 2 bits *
1 bit or 2 bits *
1 bit or 2 bits *
8+1 bits
9 bits
8 bits
*: Only one bit is allowed for the stop bit length when data is received. The second bit is ignored even if it is received.
280
CHAPTER 13 UART
■ Serial Switch
UART and 8-bit serial I/O use the same pins, thus they cannot be simultaneously used. The serial switch
circuit needs be used to select either of them.
When UART is selected using the serial switch, P30/UCK/SCK is used as the UART serial clock I/O pin
(UCK), P31/UO/SO is used as the UART data output pin (UO), and P32/UI/SI is used as the UART data
input pin (UI).
Note:
In this chapter, the pin function switch and register functions are explained on the presupposition that
UART is selected using the serial switch circuit.
■ Choice of the Transfer Clock Rate
Figure 13.1-1 Baud Rate Generator and Serial Clock Generator
PR2 to PR0
UART prescaler
RC2 to RC0
CS1, CS0
SMDE
CR
1/2
1/3
1/4
1/5
1/2
1/4
1
1/13
1/8
n
tINST/2
(1/2)
1
1/16
1/64
Serial
When RC2 and RC1
= 1, the divider is 1
even in asynchronous
mode.
1/2
clock
PWM
output
UCK
tINST : Instruction cycle
● Example of the baud rates selectable when the dedicated baud rate generator is used
Table 13.1-2 lists the baud rates selectable when the dedicated baud rate generator is used.
Table 13.1-2 Transfer Cycles and Transfer Rates Available for the Dedicated Baud Rate Generator
(when F = 12.5 MHz)
CH
Transfer rate (µs/baud)
Clock divider = 2.5 Clock divider = 1
(PR2=0, PR1=1, PR0=0) (PR2=0, PR1=0, PR0=0)
Divider for baud rate
Asynchronous
transfer
Synchronous
Asynchronous
transfer
Synchronous
RC2
RC1
RC0
(multiplier = n)
transfer
transfer
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1(0)
2(1)
83/12019
166/6010
333/3005
666/1503
1331/751
2662/375
13/78125
102/9766
0.8/1.25M
1.6/625k
3.2/313k
6.4/156k
12.8/78k
25.6/39k
1.6/625k
12.8/78k
33/30048
67/15024
133/7512
266/3756
532/1878
1065/939
5.12/195k
41/24k
0.32/3.1M
0.64/1.6M
1.28/781k
2.56/391k
5.12/195k
10.24/98k
0.64/1.6M
5.12/195k
4(2)
8(3)
16(4)
32(5)
2(1)
16(4)
281
CHAPTER 13 UART
Figure 13.1-2 Example of Calculating the Baud Rate
Clock divider
selected
Baud rate
selected
Synchronous/
asynchronous
mode selected
(SMDE)
Divided by 1 or
13
Clock gear
selected
Clock rate
(CR)
1
(RC2,RC1,RC0)
(PR2,PR1,PR0)
=
4/FCH, 8/FCH
Value of baud rate
Divided by 1, 2,
2.5, 3, 4, or 5
Divided by 1, 2,
4, 8, 16, or 32
Divided by 1,
or 8
16/FCH, 64/FCH
Note: When RC2 is
1 and RC1 is 1, the
divider is 1.
Notes:
The baud rate is specified using the clock gear register (CS1 and CS0), clock divider registers (PR2,
PR1, and PR0), or baud rate selection registers (RC2, RC1, and RC0). For the example of calculating
the baud rate, see Table 13.1-2 .
•
•
Asynchronous transfer mode
1/12019bps= 0.8 µs{4/F × 2.5(PR2=0,PR1=1,PR0=0)} × 1(CS1=CS0=1) ×
CH
8(asynchronous) × 1(RC2=RC1=RC0=0) × 13(asynchronous)
Synchronous transfer mode
1/1.25Mbps = 0.8 µs{4/F × 2.5(PR2=0,PR1=1,PR0=0)} × 1(CS1=CS0=1) ×
CH
1(synchronous) × 1(RC2=RC1=RC0=0) × 1(synchronous)
Table 13.1-3 provides an example of the baud rates selectable when an external clock is used.
Table 13.1-3 Transfer Cycles and Transfer Rates Selectable for an External Clock
Asynchronous transfer mode
Synchronous transfer mode
Divider for baud
rate
Transfer rate
(bps) *
Divider for
baud rate
Transfer rate
Transfer cycle
Transfer cycle
(bps) *
256/F or more
CR=0
CR=1
16
64
48828 or less
12207 or less
CH
16/F or more
1
781 k or less
CH
1024/F or more
CH
*: The minimum value of F specified for 12.5 MHz is external clock cycle 16/F = 1.28 µs.
CH
CH
F
: Oscillation frequency
CH
Figure 13.1-3 Example of Calculating the Baud Rate (when an External Clock is Selected)
1
External clock input
(min: 8/FCH
16
64
CR CR=0
CR=1
Value of baud rate
2)
F
CH : Oscillation frequency
282
CHAPTER 13 UART
Table 13.1-4 provides an example of the baud rates selectable when the 8-bit PWM timer is used.
Table 13.1-4 Transfer Cycles and Transfer Rates Selectable for the 8-bit PWM Timer
Asynchronous transfer mode
Synchronous transfer mode
PWM timer
count clock
cycle
Divider for
clock
Divider for clock
Transfer rate (bps)
Transfer rate (bps)
CR=0
CR=1
CR=0
CR=1
CR=0
CR=1
CR=0
CR=1
16
64
16
64
16
64
16
64
97656 to 763
24414 to 191
6103 to 47.8
1526 to 11.9
1526 to 11.9
381.5 to 3
1t
2
2
2
2
781k to 6.1k
INST
16t
48828 to 381.5
12207 to 95.4
391k to 3k
INST
64t
INST
48828 to 381.5
12207 to 95.4
8/16-bit capture
timer/counter
t
: Instruction cycle
INST
The system clock control register (SYCC) selects the maximum clock speed (CS1 and CS0 = 11 , 1 instruction cycle =
B
4/F ) in active mode.
CH
Figure 13.1-4 shows an example of calculating the baud rate when the PWM timer is selected.
Figure 13.1-4 Example of Calculating the Baud Rate (when the PWM Timer is Selected)
Clock gear
selected
Input clock select bit
(PWM)
Compare register
(COMP)
1(P1=0,P0=0)
16(P1=0,P0=1)
64(P1=1,P0=0)
64/FCH
16/FCH
1
CR=0:16
CR=1:64
Value specified in the
compare register + 1
=
2
CR
8/FCH
4/FCH
Value of baud rate
8/16 timer (P1=1,P0=1)
The value of the baud rate is determined by the clock input specified in the clock dividing rate register
(CS1 and CS0). The clock input is determined with an external clock (PWM timer). For calculation, see
•
When an external clock is selected (F = 12.5 MHz)
CH
1/49kbps=1.28 µs (min.) × 16 (CR=0)
•
When the PWM timer is selected (F = 12.5 MHz)
CH
1/98kbps=0.32 µs (4/F ) × 1 (P1=0,P0=0) × 1 (COMR=0) × 2 × 16 (CR=0)
CH
1/24414 bps=0.32 µs (4/F ) × 1 (P1=0,P0=0) × 1 (COMR=0) × 2 × 64 (CR=1)
CH
283
CHAPTER 13 UART
13.2
Configuration of UART
UART consists of the following ten registers and components:
• Serial mode control register (SMC)
• Serial rate control register (SRC)
• Serial status and data register (SSD)
• Serial input data register (SIDR)
• Serial output data register (SODR)
• Baud rate generator
• Reception control circuit
• Transmission control circuit
• Clock divider selection register (UPC)
• UART prescaler
■ Block Diagram of UART
Figure 13.2-1 Block Diagram of UART
Control bus
UART
Reception
interrupt
RIE
interrupt
IRQ6
IRQ5
Transmission
clock
Transmission
interrupt
Transmission
control circuit
P30/UCK/SCK
Reception control
TIE
Pin
circuit
Received
byte
Transmitted
byte counter
Baud rate
generator
counter
Parity
transmission
timing
Start bit
detection
circuit
P31/UO/SO
UART
prescaler
Pin
RP
TP
Parity
Parity
Reception clock
PREN
Clock
PR2,1,0
Shift register
Register
Shift register
Register
Completion
of receipt of
one byte
divider
selection
register
(UPC)
P32/UI/SI
<Serial input data
register (SIDR)>
<Serial output
data register
(SODR)>
Pin
Internal data bus
RDRF
PEN
SBL
ORFE
TDREX
TIE
Serial mode
control
register
(SMC)
Serial rate
control
register
(SRC)
Serial status
and data
register
MC1/0
SMDE
SCKE
SOE
CR
(SSD)
RIE
CS1/0
RC2 to 0
TP
RP
Control bus
284
CHAPTER 13 UART
● Serial mode control register (SMC)
The SMC register controls UART operating mode. This register specifies the parity setting, stop bit length,
operating mode (data length), and synchronous/asynchronous mode, and enables/disables UART serial
clock output and serial data output.
● Serial rate control register (SRC)
The SRC register controls the UART data transfer speed (baud rate). This register selects the input clock
and specifies the transfer rate to be applied when the baud rate generator is used.
● Serial status and data register (SSD)
The SSD register indicates UART transmitting/receiving status, status in an error, parity received, or data
received at bit8. This register also enables/disables interrupts or specifies and confirms parity transmitted or
data transmitted with bit8.
● Serial input data register (SIDR)
The SIDR register stores received data. Serial input is converted, then stored into this register. However,
the most significant bit of 9-bit data is stored in the SSD RD8/RP bit.
● Serial output data register (SODR)
The SODR register specifies data to be transmitted. Data written into this register is converted to serial
format, then output. The most significant bit of 9-bit data is set in the SSD TD8/TP bit.
● Clock generator
The clock generator generates the transmit/receive clock in accordance with the dedicated baud rate
generator, external clock, and 8-bit PWM timer output.
● Reception control circuit
The reception control circuit consists of the received byte counter, start bit detection circuit, and received
parity handling circuit.
The received byte counter takes count of received data. When a unit of data that corresponds to the
specified data length is fully received, an interrupt request is generated.
The start bit detection circuit detects start bits in serial input signals. When the start bit detection circuit
detects a start bit, it writes data into the SIDR with shifts in accordance with the transfer rate.
When parity is used, the received parity handling circuit stores the parity bit in the data received. It also
stores the most significant bit of 9-bit data received.
● Transmission control circuit
The transmission control circuit consists of the transmitted byte counter and transmitted parity handling
circuit.
The transmitted byte counter takes count of data to be transmitted. When a unit of data that corresponds to
the specified data length is fully transmitted, an interrupt request is generated.
When parity is used, the transmitted parity handling circuit generates a parity bit for the data to be
transmitted. It sets the most significant bit for data transmitted when it is made up of 9 bits.
285
CHAPTER 13 UART
● UART interrupt sources
[Reception]
When data with the specified length is correctly received or when the overrun error or framing error
occurs while data is being received, the reception interrupt request (IRQ6) is generated if the reception
interrupt request is enabled (SSD: RIE = 1).
[Transmission]
When data to be transmitted is written into the SODR register, sent to the internal shift register, and the
next data then becomes writable, the transmission interrupt request (IRQ5) is generated if the
transmission interrupt request is allowed (SSD: TIE = 1).
● UART prescaler, baud rate generator, clock divider selection register
The clock input to the baud rate generator is changeable by switching the rate of division using the clock
divider selection registers.
286
CHAPTER 13 UART
13.3
Pins of UART
Pins relating to UART are the clock I/O pin (P30/UCK/SCK), serial data output pin
(P31/UO/SO), and serial data input pin (P32/UI/SI).
■ UART Relating Pins
● P30/UCK/SCK
This pin functions as the general-purpose I/O port (P30), UART clock I/O pin (UCK), or 8-bit serial clock
I/O pin (SCK). When clock output is enabled (SMC: SCKE = 1), this pin functions as the UART clock
output pin (UCK) regardless of the value in the corresponding port direction register. When this pin
functions as the UART clock, do not use any external clock (SRC: CS1 and CS0 must be other than 00 ).
B
When using this pin as the UART clock input pin, disable clock output (SMC: SCKE = 0) and set it as the
input port using the corresponding port direction register (DDR3: bit0 = 0). In this case, be sure to select
the external clock (SRC: CS1 and CS0 = 00 ).
B
● P31/UO/SO
This port functions as the general-purpose I/O port (P31), UART serial data output pin (UO), or 8-bit serial
data output pin (SO). When serial data output is enabled (SMC: SOE = 1), this pin functions as the UART
serial data output pin (UO) regardless of the value in the corresponding port direction register.
● P32/UI/SI
This port functions as the general-purpose I/O port (P32), UART serial data input pin (UI), or 8-bit serial
data input pin (SI). When using this pin as the UART serial data input pin, set this pin as the input port by
using the corresponding port direction register (DDR3: bit2 = 0).
287
CHAPTER 13 UART
■ Block Diagram of the UART-relating Pins
Figure 13.3-1 Block Diagram of UART-relating Pins
P30/UCK/SCK
UCK
UI
PDR
P32/UI/SI
Stop mode
PDR read
(SPL = 1)
Resource output
Resource
Pull-up resistor
Resource
output
output allowed
enable
PDR read
(At read-modify-write)
Pch
Output
latch
PDR write
DDR write
Pin
P30/UCK/SCK
P31/UO/SO
P32/UI/SI
Nch
DDR
Stop mode
(SPL = 1)
PUL read
PUL
PUL write
When use of the pull-up resistor is selected in the pull-up setting register, the pin status does not become
Hi-Z but "H" level (pull-up state) in stop mode (SPL = 1). However, the pull-up resistor is not applied
during reset; accordingly, the pin status becomes Hi-Z.
288
CHAPTER 13 UART
13.4
Registers of UART
■ UART-relating Registers
Figure 13.4-1 UART-relating Registers
SMC (serial mode control register)
Address
Initial value
SOE 00000-00B
R/W
bit7
bit6
bit5
MC1
R/W
bit4
MC0
R/W
bit3
SMDE
R/W
bit2
bit1
SCKE
R/W
bit0
0028H
PEN
R/W
SBL
R/W
SRC (serial rate control register)
Address
bit7
bit6
bit5
CR
R/W
bit4
CS1
R/W
bit3
CS0
R/W
bit2
RC2
R/W
bit1
RC1
R/W
bit0
RC0
R/W
Initial value
--011000B
0029H
SSD (serial status and data register)
Address
002AH
bit7
bit5
TDRE
R/W
bit4
TIE
R/W
bit3
RIE
R/W
bit2
bit1
bit0
Initial value
bit6
RDRF ORFE
R
TD8/TP RD8/RP 00100-1XB
R/W
R
R
SIDR (serial input data register)
Address
002BH
bit7
bit6
bit5
R
bit4
R
bit3
R
bit2
R
bit1
R
bit0
R
Initial value
XXXXXXXXB
R
R
SODR (serial output data register)
Address
Initial value
bit7
W
bit6
W
bit5
W
bit4
W
bit3
W
bit2
W
bit1
W
bit0
W
002BH
XXXXXXXXB
UPC (clock divider selection register)
Address
002CH
bit7
bit6
bit5
bit4
bit3
PREN
R/W
bit2
PR2
R/W
bit1
PR1
R/W
bit0
PR0
R/W
Initial value
----0010B
SSEL (serial switch register)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
003BH
SSEL -------0B
R/W
R/W : Readable/Writable
R
W
: Read only
: Write only
: Unused
X
: Undefined
289
CHAPTER 13 UART
13.4.1
Serial Mode Control Register (SMC)
The serial mode control register (SMC) specifies the parity setting, stop bit length,
operating mode (data length), and synchronous/asynchronous mode, and enables/
disables UART serial clock output and serial data output.
■ Serial Mode Control Register (SMC)
Figure 13.4-2 Serial Mode Control Register (SMC)
Address
bit7
PEN SBL
R/W R/W R/W R/W R/W
bit6
bit5
bit4
bit3
bit2
bit1 bit0
SCKE SOE
R/W R/W
Initial value
0028H
MC1 MC0 SMDE
00000-00B
SOE
Serial data output enable bit
0
1
General-purpose port or 8-bit serial I/O data output pin
UART serial data output pin
Clock output enable bit
SCKE
General-purpose port or clock input pin for UART/8-bit serial I/O
0
1
UART clock output pin
Synchronization mode selection bit
Synchronous transfer mode
SMDE
0
1
Asynchronous transfer mode
Operating mode selection bits
MC1
MC0
Data written:
Without parity
Operating
mode
With parity
(PEN = 1)
(PEN = 0)
6 bits
0
0
1
1
0
1
0
1
0
1
2
3
7 bits
7 bits
8 bits
8+1 bits
9 bits
8 bits
Stop bit length selection bit
SBL
0
2 bits
1
1 bit
Parity enable bit
PEN
0
Parity disabled
Parity enabled (TD8/TP in the SSD register allows choice of
1
even/odd.)
R/W : Readable/Writable
: Unused
: Initial value
290
CHAPTER 13 UART
Table 13.4-1 Explanation of Functions of Each Bit in the Serial Mode Control Register (SMC)
Bit name Description
PEN:
Parity enable bit
This bit selects whether the parity bit is to be added (at transmission) and
detected (at reception) when serial data is input/output.
bit7
bit6
This bit selects the stop bit length for data to be transmitted.
Note:
SBL:
Stop bit length selection bit
When data is received, only the first bit of stop bits is detected and the
second and later bits are ignored.
•
•
These bits specify operating mode (data length).
There are 7 types of data length selectable in combination with a parity
bit.
bit5,
bit4
MC1, MC0:
Operating mode selection bits
SMDE:
•
•
This bit specifies synchronous transfer or asynchronous transfer mode.
When this bit is "0", synchronous transfer mode is set. When this is "1",
asynchronous transfer mode is set.
bit3
bit2
Synchronization mode selection
bit
•
•
The value read out from this bit is undefined.
Writing a value into this bit does not affect any operations.
Unused bit
•
•
This bit controls I/O of the serial clock.
When this bit is "0", P30/UCK/SCK pin functions as the serial clock
input pin. When this bit is "1", it functions as the serial clock output
pin.
Notes:
• When the UCK pin functions as the serial clock input pin (SCKE = 0),
set the P30/UCK/SCK pin as the input port. Also, select the external
SCKE:
Clock output enable bit
clock using the clock input selection bit (SRC: CS1 and CS0 = 00 ).
bit1
B
• When the UCK pin is set as the serial clock output pin (SCKE = 1),
select a clock other than the external clock (SRC: CS1 and CS0 must
not be 00 ).
B
Note:
When the UCK pin is specified as the serial clock output (SCKE = 1), it
functions as the UCK output pin regardless of the state of the general-
purpose port (P30).
When this bit is "0", the P31/UO/SO pin functions as a general-purpose
port (P31). When this bit is "1", it functions as the serial data output pin
(UO).
SOE:
bit0
Serial data output enable bit
Note:
When serial data output is enabled (SOE = 1), the pin functions as the
UO pin regardless of the state of the general-purpose port (P31).
291
CHAPTER 13 UART
13.4.2
Serial Rate Control Register (SRC)
The serial rate control register (SRC) controls the data transfer rate (baud rate) in
asynchronous transfer mode. The SRC selects the input clock and sets the transfer rate
for the dedicated baud rate generator.
■ Serial Rate Control Register (SRC)
Figure 13.4-3 Serial Rate Control Register (SRC)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CS1
CS0
0029H
CR
RC2
--011000B
RC1 RC0
R/W R/W R/W R/W R/W R/W
Baud rate selection bits
Asynchronous s/baud)
RC2 RC1 RC0
(µ
Synchronous (µs/baud)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
83/12019
0.8/1.25M
1.6/625k
3.2/313k
6.4/156k
12.8/78k
25.6/39k
1.6/625k
12.8/78k
166/6010
333/3005
666/1503
1331/751
2662/375
13/78125
102/9766
Clock input selection bits
CS1
Clock frequency divider
CS0
CR bit
Clock input
Asynchronous
Synchronous
0
1
0
1
16
64
16
64
External clock
PWM timer output
Unused
0
0
1
0
1
1
1
0
1
2
0
1
Dedicated baud
rate generator
8
1
Clock rate input selection bit
CR
Effective only in asynchronous transfer mode (SMC: SMDE = 1)*
0
1
1/16 of the clock input
1/64 of the clock input
: Readable/Writable
: Unused
: Initial value
R/W
* : However, when the dedicated baud rate generator is used (CS1 and CS0 = 11B),
it is fixed at 1/8.
292
CHAPTER 13 UART
Table 13.4-2 Explanation of Functions of Each Bit in the Serial Rate Control Register (SRC)
Bit name
Description
bit7,
bit6
•
•
The values read out from these bits are undefined.
Writing values to these bits does not affect any operations.
Unused bits
•
This bit selects the clock rate in asynchronous transfer mode. However, when the
dedicated baud rate generator is used (CS1 and CS0 = 11 ), it is fixed at 1/8
B
CR:
Clock rate input
selection bit
regardless of the value in the CR bit. Specifying an external clock or 8-bit PWM
timer output as the clock input, the baud rate is set to 1/16 or 1/64 of the
corresponding clock frequency, depending on the CR value.
bit5
•
This bit is not significant in synchronous transfer mode.
CS1,CS0:
Clock input selection
bits
•
•
These bits select the clock input.
The clock input can be an external clock (UCK pin), 8-bit PWM timer, or
dedicated baud rate generator.
bit4,
bit3
•
•
There are 8 types of baud rate in asynchronous transfer mode and 6 types of baud
rate in synchronous transfer mode: 14 types of baud rate are selectable in total.
These bits are effective only when the dedicated baud rate generator is used for the
clock input. These bits are not significant when an external clock or 8-bit PWM
timer output is used.
bit2
to
bit0
RC2,RC1,RC0:
Baud rate selection bits
293
CHAPTER 13 UART
13.4.3
Serial Status and Data Register (SSD)
The serial status and data register (SSD) controls data transmission/reception of UART
and status in an error, enables/disables interrupts, and specifies and checks settings
for parity or bit-8 transmitting data.
■ Serial Status and Data Register (SSD)
Figure 13.4-4 Serial Status and Data Register (SSD)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
TD8/TP
R/W
bit0
Address
Initial value
00100-1XB
TIE
RIE
RD8/RP
002AH RDRF ORFE TDRE
R
R
R/W R/W R/W
R
Bit-8 receiving data/parity bit
RD8/
RP
Parity used
(SMC: PEN = 1)
Parity not used
(SMC: PEN = 0)
Detects odd parity.
0
1
Bit-8 receiving data*
Detects even parity.
Bit-8 transmitting data/parity bit
TD8/
TP
Parity used
(SMC: PEN = 1)
Parity not used
(SMC: PEN = 0)
Adds odd parity.
Adds even parity.
0
1
Sets bit-8 transmitting data.*
RIE
0
Reception interrupt request enable bit
Disables output of reception interrupt requests.
1
Enables output of reception interrupt requests.
TIE
0
Transmission interrupt request enable bit
Disables output of transmission interrupt requests.
Enables output of transmission interrupt requests.
1
TDRE
Transmitted data flag bit
Data to be transmitted included
0
1
Data to be transmitted not included
RDRFORFE
Received data flag bit/Overrun/Framing error flag bit
No data
0
0
1
1
0
1
0
1
Framing error
Normal data
Overrun error (previous data remaining)
: Readable/Writable
: Read only
: Unused
R/W
R
X
*
: Undefined
: Initial value
: Effective only when data length is 9 bits (SMC: MC1 and MC0 = 10B and 11B, operating mode is 2 or 3.)
294
CHAPTER 13 UART
Table 13.4-3 Explanation of Functions of Each Bit in the Serial Status and Data Register (SSD)
Bit name
Description
•
•
•
This bit indicates the state of serial input data register (SIDR).
When this bit is "1", reading the SSD register, then the SIDR register clears RDRF.
When this bit and reception interrupt request enable bit (RIE) are "1", the reception
interrupt request is output.
This bit is intended only for read. Writing a value into this bit has no significance
and does not affect any operation.
RDRF:
Received data flag bit
bit7
bit6
•
•
•
This bit indicates that the overrun or framing error occurs.
When an error occurs (ORFE = 1), no data is transferred from the reception shift
register to the SIDR register. Therefore, when an error occurs, the RDRF bit is not
set. When this bit is "1", reading the SSD register then SIDR register clears the
ORFE bit with "0".
When this bit and reception interrupt request enable bit (RIE) are "1", the reception
interrupt request is output.
This bit is intended only for read. Writing a value into this bit has no significance
and does not affect any operation.
ORFE:
Overrun/Framing error
flag bit
•
•
•
•
This bit indicates the state of serial output data register (SODR).
When this bit is "1", reading the SSD register and writing data into the SODR
register output the data to the serial data output pin (UO).
When this bit and transmission interrupt request enable bit (TIE) are "1", the
transmission interrupt request is output.
TDRE:
Transmitted data flag
bit
bit5
bit4
•
TIE:
•
•
This bit enables or disables the transmission interrupt request to the CPU.
When this bit and transmission data flag bit (TDRE) are "1", the transmission
interrupt request is output.
Transmission interrupt
request enable bit
•
•
This bit enables or disables the reception interrupt request to the CPU.
When this bit and reception data flag bit (RDRF) are "1", the reception interrupt
request is output.
When this bit and error flag bit (ORFE) are "1", the reception interrupt request for
an error is output.
RIE:
bit3
bit2
bit1
Reception interrupt
request enable bit
•
•
•
The value read out from this bit is undefined.
Writing a value into this bit does not affect any operations.
Unused bit
•
When parity is not used and operating mode is 2 or 3 (the length of data to be
transmitted/received is 9), this bit is handled as bit8 in the SODR register. When
operating mode is not 2 or 3 and parity is not used, this bit is not significant.
When parity is used, this bit selects even parity or odd parity for the transmitted
data.
TD8/TP:
Bit-8 transmitting data/
parity bit
•
•
When parity is not used and operating mode is 2 or 3 (the length of data to be
transmitted/received is 9), this bit is handled as bit8 in the SIDR register. When
operating mode is not 2 or 3 and parity is not used, this bit is not significant.
When parity is used, this bit indicates the parity of received data.
RD8/RP:
Bit-8 receiving data/
parity bit
bit0
•
295
CHAPTER 13 UART
■ Receiving Status
Figure 13.4-5 shows the states (receiving status) of serial input data obtained from the received data flag bit
(RDRF) and error flag bit (ORFE).
Figure 13.4-5 Receiving Status
RDRF
ORFE
Received data flag bit/Overrun/Framing error flag bit
0
0
1
1
0
1
0
1
No data
Framing error
Normal data
Overrun error (previous data remaining)
: Initial value
296
CHAPTER 13 UART
13.4.4
Serial Input Data Register (SIDR)
The serial input data register (SIDR) is for inputting (receiving) serial data.
■ Serial Input Data Register (SIDR)
Figure 13.4-6 shows the configuration of the serial input data register bits.
Figure 13.4-6 Serial Input Data Register (SIDR)
Address
002BH
bit7
R
bit6
R
bit5
R
bit4
R
bit3
R
bit2
R
bit1
R
bit0
R
Initial value
XXXXXXXXB
: Read only
: Undefined
R
X
The SIDR stores received data. The serial data input pin (UI pin) receives serial data signals, the shift
register converts them, then this register stores them.
● When operating mode is 0, 1, or 3
For both the RDRF (Received data flag bit) and ORFE (Overrun/framing error flag bit), these flags go on
and an interrupt request to the CPU is generated when data is fully transmitted or received, then the stop bit
at the end is detected. When the RDRF is active, the data received is transmitted to the SIDR.
When the received data is correctly stored in this register, "1" is set for the received data flag bit (RDRF). If
the reception interrupt request is allowed, the reception interrupt is generated. When the RDRF bit has been
checked in interrupt processing or the program and the received data has been stored into this register, read
the contents in this register after reading the SSD register, then clear the RDRF flag.
● When operating mode is 2
For both RDRF and ORFE, these flags go on when data is fully transmitted or received with the final data
bit (D8) set to "1" and the stop bit at the end is detected. However, when the framing error occurs, the flag
goes on regardless of the final data bit. An interrupt request to the CPU is generated when the flag goes on
and the interrupt request is allowed.
297
CHAPTER 13 UART
13.4.5
Serial Output Data Register (SODR)
The serial output data register (SODR) sends out (transmits) serial data.
■ Serial Output Data Register (SODR)
Figure 13.4-7 shows the configuration of the serial output data register bits.
Figure 13.4-7 Serial Output Data Register (SODR)
Address
002BH
bit7
W
bit6
bit5
W
bit4
W
bit3
W
bit2
W
bit1
W
bit0
Initial value
XXXXXXXXB
W
W
W
X
: Write only
: Undefined
When transmission is enabled, writing data to be transmitted into this register after reading the SSD register
sends the data to be transmitted to the transmission shift register, converts it into the serial format, then
outputs it from the serial data output pin (UO pin).
When the transmitted data is written into the SODR register, the transmitted data flag bit is cleared with
"0". After the transmitted data is sent to the transmission shift register, the transmitted data flag bit is set to
"1", the data transmitted next then becomes writable. At this time, if the transmission interrupt request is
enabled, an interrupt is generated. Write the data transmitted next when a transmission interrupt occurs or
while the transmitted data flag bit is "1".
298
CHAPTER 13 UART
13.4.6
Clock Divider Selection Register (UPC)
The clock divider selection register is used to generate the UART reference clock by
dividing the oscillation frequency. It also enables/disables operation of the prescaler for
creating the reference clock.
■ Clock Divider Selection Register (UPC)
Figure 13.4-8 Clock Divider Selection Register (UPC)
Address
002CH
Initial value
----0010
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PREN PR2 PR1
B
PR0
R/W
R/W
R/W
R/W
Clock divider selection bits
Divider
PR2
PR1
PR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divides the clock by 1.
Divides the clock by 2.
Divides the clock by 2.5.
Divides the clock by 3.
Divides the clock by 4.
Divides the clock by 5.
Do not specify this setting.
Do not specify this setting.
R/W
: Readable/Writable
: Unused
PREN
0
1
UART prescaler operation enable bit
Disables the prescaler operation.
Enables the prescaler operation.
: Initial value
299
CHAPTER 13 UART
Table 13.4-4 Explanation of Functions of Each Bit in the Clock Divider Selection Register (UPC)
Bit name
Description
bit7
to
bit4
•
•
The values read out from these bits are undefined.
Writing values into these bits does not affect any operation.
Unused bits
•
•
Enables/disables operation of the prescaler that creates the UART reference clock
by dividing the oscillation frequency.
PREN:
UART prescaler
operation enable bit
When this bit is "1", the UART prescaler supplies the reference clock that
corresponds to the frequency selected using the oscillation frequency selection bit
to the baud rate generator. When this bit is "0", the prescaler does not operate, thus
the internal baud rate generator cannot be used for data transfer or data receive
purposes.
bit3
bit2
to
bit0
PR2, PR1, PR0:
Clock divider selection
bits
•
The UART prescaler supplies to the internal baud rate generator, the reference
clock that corresponds to the divider selected using these bits.
Note:
The inside of UART is initialized when it is in synchronization transfer mode, asynchronous transfer
mode, external clock mode, or internal clock mode with the clock from the prescaler. Therefore, turn on
the PREN bit (PREN = 1) to enable operation of the prescaler before using the UART functions.
300
CHAPTER 13 UART
13.4.7
Serial Switch Register (SSEL)
The serial switch register (SSEL) switches the P30/UCK/SCK, P31/UO/SO, and P32/UI/SI
pins between UART and 8-bit serial I/O.
■ Serial Switch Register (SSEL)
Figure 13.4-9 Serial Switch Register (SSEL)
bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0
SSEL
Address
003BH
Initial value
-------0B
R/W
SSEL
Serial switch bit
0
1
Sets UART.
Sets 8-bit serial I/O.
: Readable/Writable
: Unused
R/W
: Initial value
Table 13.4-5 Description of the Serial Switch Register (SSEL) Bits
Bit name
Description
bit7
to
bit1
•
•
The values read out from these bits are undefined.
Writing values to these bits does not affect any operations.
Unused bits
SSEL:
Serial switch bit
•
•
When this bit is "0", UART is used.
When this bit is "1", 8-bit serial I/O is used.
bit0
301
CHAPTER 13 UART
Figure 13.4-10 Block Diagram of Serial Switch Register
Internal data bus
SSEL
register
SSEL bit
UART
8-bit serial I/O
Pin (P30/UCK/SCK)
Pin (P32/UI/SI)
Selector
Port 3
Pin (P31/UO/SO)
Selector
302
CHAPTER 13 UART
13.5
Interrupt of UART
UART supports the interrupt-related error flag bit (ORFE), received data flag bit (RDRF),
and transmitted data flag bit (TDRE), and the following interrupt sources:
• When received data is sent from the reception shift register to the serial input data
register (SIDR). (Reception interrupt)
• When transmitted data is sent from the serial output data register (SODR) to the
transmission shift register. (Transmission interrupt)
■ Transmission Interrupt
When the SSD register is read and the output data is written into the SODR register, the data written into
the SODR register is transferred to the internal transmission shift register. When next data becomes
writable, the TDRE bit is set to "1", then an interrupt request to the CPU (IRQ5) is generated if the
transmission interrupt is enabled (SSD: TIE = 1).
■ Reception Interrupt
● When operating mode is 0, 1, or 3
When data is correctly input up to the stop bit, the RDRF bit is set to "1". If an overrun error or framing
error occurs, the ORFE bit is set to "1".
These bits are set when a stop bit is detected. If the reception interrupt is enabled (SSD: RIE = 1), an
interrupt request to the CPU (IRQ6) is generated.
● When operating mode is 2
For both RDRF and ORFE, data is received or transmitted with the final data bit (D8) set to "1", these flags
go on when the stop bit at the end is detected. However, when the framing error occurs, the flag goes on
regardless of the final data bit. An interrupt request to the CPU is generated when the flag goes on and the
input data becomes "1".
■ UART Interrupt Related Registers and Vector Table Addresses
Table 13.5-1 provides the registers relating to the UART interrupts and vector table addresses. For details
Table 13.5-1 UART Interrupt Related Registers and Vector Table Addresses
Interrupt level setting register
Register Bit
Vector table address
Upper digits Lower digits
FFF0 FFF1
Interrupt name
ILR2 (007C )
IRQ5
IRQ6
L51 (bit3)
L61 (bit5)
L50 (bit2)
L60 (bit4)
H
H
H
ILR2 (007C )
FFEE
FFEF
H
H
H
303
CHAPTER 13 UART
13.6
Operations of UART Functions
UART supports four types of operating mode. Mode 0, mode 1, and mode 3 are general
serial transfer mode in which any data length can be selected in the range of 6 bits with
parity used, to 9 bits without parity used. (See Table 13.1-1 .)
■ Transferred Data Format
UART can handle data in the NRZ (Non Return to Zero) format only. Data to be transferred always begins
with the start bit ("L" level), specified number of data bits are transferred with LSB first, then data transfer
is ended with the stop bit ("H" level). Figure 13.6-1 shows the relationship between the transmit/receive
clock and transferred/received data when operating mode 0 without parity used, two stop bits, synchronous
transfer mode, and transferred data 01001101 (8 bits) are specified. Note that Figure 13.6-1 does not apply
B
to the relationship between the serial clock and serial I/O signal in asynchronous transfer mode.
Figure 13.6-1 Transferred Data Format
Transmit/receive clock
Data to be transmitted/
received
0
1
0
1
1
0
0
1
0
1
1
START LSB
MSB STOP STOP
304
CHAPTER 13 UART
■ Theory of Operation for Operating Mode 0, 1, 2, and 3
In operating mode 0, 1, 2, or 3, UART operates as a general serial communication function. Figure 13.6-2
shows the settings required in UART operating mode 0, 1, 2, or 3.
Figure 13.6-2 Operating Mode 0, 1, 2, or 3
bit7
bit6
bit5
MC1
bit4
MC0
*
bit3
bit2
bit1
bit0
SMC
PEN
SBL
SMDE
SCKE
SOE
*
SRC
CR
CS1
CS0
RC2
RC1
RC0
SSD
RDRF ORFE TDRE
TIE
RIE
TD8/TP RD8/RP
*
*
Stores received data.
SIDR
SODR
DDR3
SSEL
Writes data to be transmitted.
SSEL
0
: Used bit
: Set "0"
0
*
: For MC1 and MC0, set 00B in mode 0, 01B in mode 1, 10B in mode 2, and 11B in
mode 3.
305
CHAPTER 13 UART
13.6.1
Transmission Operations (Operating Mode 0, 1, 2, and 3)
When writing data to be transmitted into the SODR register after reading the SSD
register sends the data written into the SODR register to the transmission shift register,
parallel-serial conversion then starts. The data converted is output at the serial data
output pin from the lowest bit in sequence (with LSB first). When the next data becomes
writable, "1" is set to the TDRE bit, then an interrupt request to the CPU is generated if
the transmission interrupt is allowed (SSD: TIE = 1).
■ Transmission Operations in Operating Mode is 0, 1, 2, or 3
Figure 13.6-3 shows the transmission operations when operating mode is 1, parity is not used, and the
number of stop bits is "1".
Figure 13.6-3 Transmission Operations in Operating Mode 0, 1, 2, or 3
SSD read
SODR write
(interrupt processing
routine)
Transmission buffer full
TDRE
Transmission interrupt
Sent to the transmission shift register
Sent to the transmission shift register
Data transmitted
START
STOP START
0
1
2
3
4
5
6
7
306
CHAPTER 13 UART
13.6.2
Reception Operations (Operating Mode 0, 1, or 3)
When data is received at the serial data input pin, the internal reception shift register
converts it from serial to parallel. If the data is correctly transmitted up to the stop
bit(s), data in the internal shift register is transferred to the SIDR register, then "1" is set
to the RDRF bit.
■ Reception Operations (Operating Mode 0, 1, or 3)
If an overrun error or framing error occurs, the received data is not transmitted to the SIDR register, but the
ORFE bit is set to "1".
Either of the RDRF bit and ORFE bit goes on when the final stop bit is detected after data is fully received.
If the reception interrupt is enabled (SSD: RIE = 1), an interrupt request to the CPU (IRQ6) is generated.
When the RDRF bit goes on, the received data has been transmitted to the SIDR register.
In operating mode 2, when the RIE bit is "1", RDRF bit or ORFE bit is "1", and reception interrupt pin is
"1", the mode 2 UART reception interrupt request is output to the CPU.
Note:
In operating mode 1, the parity bit is read as data in the 7th bit. Set up the program so that the 7th bit is
not read.
Figure 13.6-4 , Figure 13.6-5 , and Figure 13.6-6 show the reception operations when parity is not used and
the number of stop bits is "1" in operating mode 0, 1, or 3.
Figure 13.6-4 Reception Operations in Operating Mode 0, 1, or 3
Data
START
0
1
2
3
4
5
6
7
STOP
RDRF
Reception
interrupt
307
CHAPTER 13 UART
Figure 13.6-5 Operations in Operating Mode 0, 1, or 3 when the Overrun Error Occurs
Data
START
0
1
2
3
4
5
6
7
STOP
RDRF=1
(reception buffer full)
ORFE
Reception interrupt
Figure 13.6-6 Operations in Operating Mode 0, 1, or 3 when the Framing Error Occurs
Data
0
1
2
3
4
5
6
7
START
STOP
RDRF=0
ORFE
Reception interrupt
Note:
After initialization is cancelled due to a reset, time for 11 shift-clock cycles is required to initialize the
internal controller. Therefore, be sure to enable the UART prescaler operation (PREN = 1) using the
oscillation frequency register after a reset.
308
CHAPTER 13 UART
13.6.3
Reception Operations (Operating Mode 2 Only)
When data is received at the serial data input pin, the internal reception shift register
converts it from serial to parallel. If the data is correctly transmitted up to the stop
bit(s), data in the internal shift register is transferred to the SIDR register, then "1" is set
to the RDRF bit.
■ Reception Operations (Operating Mode 2 Only)
If an overrun error or framing error occurs, the received data is not transmitted to the SIDR register, but the
ORFE bit is set to "1".
For both RDRF and ORFE, data is fully received/transmitted with the final data bit (D8) set to "1", these
flags go on when the stop bit at the end is detected. However, when the framing error occurs, the flag goes
on regardless of the final data bit. An interrupt request to the CPU is generated when the flag goes on and
interrupt request is enabled.
If the reception interrupt is enabled (SSD: RIE = 1), an interrupt request to the CPU (IRQ5) is generated.
When the RDRF bit goes on, the received data is transmitted to the SIDR register.
Figure 13.6-7 to Figure 13.6-9 show the reception operations when parity is not used and the number of
stop bits is "1" in operating mode 2.
Figure 13.6-7 Reception Operations in Operating Mode 2
Data
START
0
1
2
3
4
5
6
7
8
STOP
RDRF
Reception
interrupt
Figure 13.6-8 Operations in Operating Mode 2 when the Overrun Error Occurs
Data
0
1
2
3
4
5
6
7
8
STOP
START
RDRF=1
(reception buffer full)
ORFE
Reception interrupt
309
CHAPTER 13 UART
Figure 13.6-9 Operations in Operating Mode 2 when the Framing Error Occurs
Data
START
0
1
2
3
4
5
6
7
8
STOP
RDRF=0
ORFE
Reception
interrupt
Note:
After initialization is cancelled due to a reset, time for 11 shift-clock cycles is required to initialize the
internal controller. Therefore, be sure to enable the UART prescaler operation (PREN = 1) using the
oscillation frequency register after a reset.
310
CHAPTER 13 UART
13.7
Program Example for UART
This section provides program example for UART.
■ Program Example for UART
● Program specifications
•
•
•
•
Serial data transfer is implemented using the UART communication functions.
The P30/UCK/SCK, P31/UO/SO, and P32/UI/SI pins are used for communication.
The transfer rate is set to 300 bps using the internal baud rate generator.
13 is transmitted from the UO pin, and data is received by interrupts.
H
•
The baud rate is the oscillation frequency (F = 12.5 MHz) at the maximum gear speed (1 instruction
CH
cycle = 4/F ). The clock divider is 2.5. (1/375 bps = 8320 t
)
CH
INST
● Coding example
PDR3
DDR3
SSEL
SMC
SRC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000CH
000DH
003BH
0028H
0029H
002AH
002BH
002BH
002CH
007CH
; Port data register address
; Port direction register address
; Serial selection register address
; Serial mode control register address
; Serial rate control register address
; Serial status and data register address
; Serial input data register address
; Serial output data register address
; Clock divider selection register address
; Interrupt level setting register address
; [DATA SEGMENT]
SSD
SIDR
SODR EQU
UPC
ILR2
EQU
EQU
INT_V DSEG ABS
ORG
DW
DW
0FFEEH
IRQ6
IRQ5
WARI2
WARI1
; Reception interrupt vector setting
; Transmission interrupt vector setting
INT_V ENDS
;--------------------Main program---------------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
; The stack pointer (SP) and related components have to be
initialized.
:
CLRI
MOV
MOV
; Disable interrupts.
ILR2,#11101011B ; Set an interrupt level (level 1).
UPC,#11111010B ; Allow operation with the clock whose frequency is divided
by 2.5.
MOV
MOV
MOV
SSEL,#00000000B ; Select UART.
DDR3,#00000000B ; Set the UI pin as the input pin.
SMC,#01011011B ; Set non-parity, the number of stop bits 1, and operating
311
CHAPTER 13 UART
mode 1. Set asynchronous mode, enable clock output
and serial data output.
MOV
MOV
MOV
SRC,#00011101B ; Select the dedicated baud rate generator, and set the baud
rate 375 bps.
SSD,#00001000B ; Disable the transmission interrupt request and enable the
reception interrupt request.
A,SSD
; Required before transmission
(TDRE = 1 enables transmission)
; Clear error flags.
MOV
MOV
A,SIDR
SODR,#13H
; Write the data to be transmitted (13 ).
H
SETI
:
; Enable instruction.
;--------------------Interrupt processing routine-----------------------------------------------------------
WARI PUSHW A
XCHW A,T
; Save A and T.
PUSHW A
MOV
A,SSD
A,SIDR
; Read the data to be transmitted, then clears the input data
flag.
MOV
:
User-defined process
:
POPW
A
; Restore A and T.
XCHW A,T
POPW
RETI
A
ENDS
; --------------------------------------------------------------------------------------------------------------------
END
312
CHAPTER 14 8-BIT SERIAL I/O
14.1
Overview of 8-Bit Serial I/O
The 8-bit serial I/O has a function that serially transfers 8-bit data in synchronization
with a shift clock. It can select one shift clock from three internal shift clocks and one
external shift clock. It can also select LSB first or MSB first as the data shift direction.
■ Serial I/O Function
The 8-bit serial I/O function serially inputs and outputs 8-bit data in synchronization with a shift clock.
•
Converts 8-bit parallel data to 8-bit serial data and outputs it. Also inputs 8-bit serial data, converts the
data to 8-bit parallel data, and stores it.
•
•
•
Can select one shift clock from three internal shift clocks and one external shift clock.
Can control shift clock input/output and output internal shift clocks.
Can select LSB first or MSB first as the data shift direction.
Table 14.1-1 Shift Clock Cycle and Transfer Rate
Transfer rate
(F =12.5MHz, At maximum speed*)
Shift clock
Clock cycle
Frequency (Hz)
CH
2t
1/ (2t
1/ (8t
)
)
1562.5 kbps
390.6 kbps
97.66 kbps
INST
INST
Internal shift clock
(output)
8t
INST
INST
32t
1/ (32t
)
INST
INST
External shift clock
(input)
2t
or lower
1/(2t
) or lower
INST
DC to 1562.5 kbps
INST
F
: Oscillation frequency
: Instruction cycle
CH
t
INST
*
: When the highest speed clock of a general mode is selected with the system clock control register (SYCC)
(CS1 and CS0 bits of SYCC = 11 , 1 instruction cycle = 4/F
)
CH
B
■ Serial Function Switching
The 8-bit serial I/O and UART cannot be used simultaneously because they use the same pin. For this
reason, the serial function switching circuit must be used to switch the 8-bit serial I/O and UART. For more
information on the serial function switching circuit, see Section "13.4.7 Serial Switch Register (SSEL) ".
Selecting the 8-bit serial I/O with this serial function switching circuit enables P30/UCK/SCK to be used as
the serial clock I/O pin (SCK) of the serial I/O, and P31/UO/SO to be used as the data output pin (SO). This
selection also enables P32/UI/SI to be used as the data input pin (SI).
Note:
This chapter describes pin function switching and the register function, etc., on the assumption that the 8-
bit serial I/O is selected with the serial function switching circuit.
314
CHAPTER 14 8-BIT SERIAL I/O
14.2
Configuration of 8-Bit Serial I/O
Each 8-bit serial I/O channel consists of the following four blocks:
• Shift clock control circuit
• Shift clock counter
• Serial data register (SDR)
• Serial mode register (SMR)
■ Block Diagram of 8-bit Serial I/O
Figure 14.2-1 Block Diagram of 8-bit Serial I/O
Internal data bus
Transfer direction
D0 to D7
MSB first
D7 to D0
LSB first
selection
P32/UI/SI
Pin
(Shift direction)
D7 to D0
Serial data register (SDR)
SST
BDS
Output buffer
P31/UO/SO
Pin
CKS0
CKS1
Output
allowance
Output
allowance
SOE
SCKE
Shift clock selection
SIOE
2
SIOF
2tINST
8tINST
Serial mode register (SMR)
32tINST
Shift clock control circuit
P30/UCK/SCK
Pin
Interrupt request
IRQC
Clear
Output buffer
Shift clock counter
tINST
: Instruction cycle
315
CHAPTER 14 8-BIT SERIAL I/O
● Shift clock control circuit
As a shift clock of the shift clock control circuit, one of three internal clocks and one external clock is
selected.
Selecting an internal clock enables the shift clock to be output to the SCK pin. Selecting an external clock
enables the clock to be input from the SCK pin to act as the shift clock. The shift clock control circuit shifts
the SDR in accordance with this shift clock and outputs the shifted-out value to the SO pin. It also captures
the data input from the SI pin while shifting it to the SDR.
● Shift clock counter
The shift clock counter counts the number of times the SDR was shifted using the shift clock. When 8-bit
shift is completed, the counter overflows.
When the counter overflows, the serial I/O transfer start bit of the SMR (SST = 0) is cleared and the
interrupt request flag bit (SIOF = 1) is set. When serial transfer stops (SST = 0), the counter stops its count.
It is cleared when serial transfer is started (SST = 1).
● Serial data register (SDR)
The SDR retains transfer data. The data written to the SDR is converted to serial data and output. Serial
input is converted to parallel data and stored.
● Serial mode register (SMR)
The SMR is a serial I/O control register. It is used to allow and prohibit serial I/O operation, select shift
clocks, and set a transfer (shift) direction. It is also used to control interrupts and check interrupt states.
● 8-bit serial I/O interrupt
IRQC: If the interrupt request output is allowed (SMR: SIOE = 1) when the I/O function of the 8-bit
serial I/O inputs or outputs 8-bit serial data, a interrupt request (IRQC) is generated.
•
316
CHAPTER 14 8-BIT SERIAL I/O
14.3
Pins of 8-Bit Serial I/O
8-bit serial I/O pins include P32/UI/SI, P31/UO/SO, and P30/UCK/SCK pins.
■ Pins of 8-bit Serial I/O
● P32/UI/SI pin
The P32/UI/SI pin functions as the general-purpose I/O port (P32). It also functions as the serial data input
pin (SI) of the 8-bit serial I/O or as the serial data input pin (UI) of the UART.
When using the P32/SI pin as the SI pin, set the P32/UI/SI pin to "input port" with the port direction
register (DDR3: bit2 = 0).
● P31/UO/SO pin
The P31/UO/SO pin functions as the general-purpose I/O port (P31). It also functions as the serial data
output pin (SO) function of the 8-bit serial I/O or as the serial data output pin (UO) function of the UART.
When the serial data output is allowed (SMR: SOE = 1), the P31/UO/SO pin automatically becomes an
output pin irrespective of the values in the port direction register (bit1 of DDR3) and functions as the SO
pin.
● P30/UCK/SCK pin
The P30/UCK/SCK pin functions as the general-purpose I/O port (P30). It also functions as the shift clock
I/O pin (SCK) of the 8-bit serial I/O or as the shift clock I/O pin (UCK) of the UART.
When using the P30/UCK/SCK pin as the shift clock input pin
When using the SCK pin as the shift clock input pin, set it to "input port" with the port direction register
(DDR3: bit3 = 0) and prohibit shift clock output (SMR: SCKE = 0). In this case, be sure to select the
external shift clock (SMR: CKS1, CKS0 = 11 ).
B
When using the P30/UCK/SCK pin as the shift clock output pin
When the shift clock output is allowed (SMR: SCKE = 1), the P30/UCK/SCK pin automatically becomes
an output pin irrespective of the values in the port direction register (DDR3: bit0) and functions as the
SCK output pin. In this case, be sure to select an internal shift clock (when SMR: CKS1, CKS0 are not
11 ).
B
317
CHAPTER 14 8-BIT SERIAL I/O
■ Block Diagram for 8-bit Serial I/O Pins
Figure 14.3-1 Block Diagram for 8-bit Serial I/O Pins
SCK
P30/UCK/SCK
PDR
SI
P32/UI/SI
Stop mode (SPL = 1)
PDR read
Resource output
Pull-up resistor
Resource
output
enable
Resource
output
available
PDR read
(At read-modify-write)
Pch
Nch
Output latch
PDR write
DDR write
Pin
P30/UCK/SCK
P31/UO/SO
P32/UI/SI
DDR
PUL
Stop mode
(SPL=1)
PUL read
PUL write
Note:
When "pull-up resistor available" is selected in the pull-up setting register, the pin state in stop mode
(SPL = 1) becomes high (pull-up state), not Hi-Z. During the reset, however, pull-up becomes invalid
and the pin state becomes Hi-Z.
318
CHAPTER 14 8-BIT SERIAL I/O
14.4
Registers of 8-Bit Serial I/O
Figure 14.4-1 shows 8-bit serial I/O registers.
■ Registers of 8-bit Serial I/O
Figure 14.4-1 8-bit Serial I/O Registers
SMR (serial mode register)
Address
0039H
Initial value
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SIOF
R/W
SIOE
R/W
SCKE
R/W
SOE
R/W
CKS1
R/W
CKS0
R/W
BDS
R/W
SST
R/W
SDR (serial data register)
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
003AH
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and Writable
: Undefined
X
Note:
When using a bit manipulation instruction, make sure that the SST bit is "0".
319
CHAPTER 14 8-BIT SERIAL I/O
14.4.1
Serial Mode Register (SMR)
The serial mode register (SMR) is used to allow and prohibit 8-bit serial I/O operation,
select a shift clock, set a transfer direction, control interrupts, and check interrupt
states.
■ Serial Mode Register (SMR)
Figure 14.4-2 Serial Mode Register (SMR)
Address bit7 bit6
0039H SIOF SIOE
bit5
bit4
bit3
CKS1
bit2 bit1
bit0
SST
Initial value
00000000B
SCKE SOE
CKS0 BDS
R/W R/W R/W R/W R/W R/W R/W R/W
Serial I/O transfer start bit
SST
At read
At write
Serial I/O transfer is stopped or
prohibited.
Serial I/O transfer is stopped.
Serial I/O transfer is in progress.
0
1
Serial I/O transfer is started or allowed.
Transfer direction selection bit
BDS
0
LSB first (serial I/O transfer starts at the lowest bit.)
MSB first (serial I/O transfer starts at the highest bit.)
1
SCK pin
Output
Output
Output
Input
CKS1 CKS0
Shift clock selection bits
Internal shift clock
External shift clock
2 tINST
8 tINST
0
0
1
1
0
1
0
1
32 tINST
tINST: Instruction cycle
SOE
0
Serial data output allowance bit
P31/UO/SO is used as a general-purpose port (P31).
1
P31/UO/SO is used as a serial data output pin.
SCKE
Shift clock output allowance bit
P30/UCK/SCK is used as a general-purpose port (P30) or the shift
clock input pin (SCK).
0
1
P30/UCK/SCK is used as the shift clock output pin.
SIOE
Interrupt request allowance bit
Interrupt request output is prohibited.
Interrupt request output is allowed.
0
1
Interrupt request flag bit
SIOF
At read
At write
This bit is cleared.
Remains unchanged. This bit does not
Serial transfer has not
terminated.
0
1
Serial transfer has already
terminated.
affect other bits.
R/W : Readable and Writable
: Initial value
320
CHAPTER 14 8-BIT SERIAL I/O
Table 14.4-1 Explanation of Functions of Each Bit in Serial Mode Register (SMR) (1/2)
Bit name Function
•
When 8-bit serial data is input or output during serial I/O operation, this
bit is set to "1". When this bit and the interrupt request allowance bit
(SIOE) are "1", an interrupt request is output.
SIOF:
Interrupt request flag bit
bit7
bit6
•
Setting this bit to "0" clears it, while setting it to "1" does not affect this
bit or implement any changes.
SIOE:
Interrupt request
allowance bit
This bit is used to allow and prohibit interrupt request output to the CPU.
When this bit and the interrupt request allowance bit (SIOF) are "1", an
interrupt request is output.
•
•
This bit is used to control shift clock I/O.
When this bit is "0", the P30/UCK/SCK pin functions as the shift clock
input pin. When "1", it functions as the shift clock output pin.
Notes:
• To use the P30/UCK/SCK pin as the shift clock input pin, it must be set
as an input port. Also select the external shift clock with the shift clock
selection bits (Set the CKS1 and CKS0 bits to 11 ).
SCKE:
B
bit5
Shift clock output
allowance bit
• For shift clock output (SCKE bit = 1), select an internal shift clock (do
not set the CKS1 and CKS0 bits to 11 ).
B
Notes:
• When shift clock output is allowed (when this bit is "1"), the P30/UCK/
SCK pin functions as the UCK/SCK output pin irrespective of the
general-purpose port (P30) state.
• When using the P30/UCK/SCK pin as a general-purpose port (P30), set
its pin as the shift clock input pin (set this bit to "0").
When this bit is "0" the P31/UO/SO pin functions as a general-purpose port
(P31). When "1", the P31/UO/SO pin functions as the serial data output pin
(UO/SO).
SOE:
bit4
Serial data output
allowance bit
Note:
When serial data output is allowed (when this bit is set to "1"), the P31/
UO/SO pin functions as the UO/SO pin irrespective of the general-
purpose port (P31) state.
•
•
These bits are used to select three internal shift clocks or one external
shift clock.
When these bits are not 11 , an internal shift clock is selected. When the
B
shift clock output allowance bit (SCKE) is "1", a shift clock is output
from the UCK/SCK pin.
bit3,
bit2
CKS1, CKS0:
Shift clock selection bits
•
When these bits are 11 , the external clock is selected. When the P30/
B
UCK/SCK pin is set as the shift clock input pin, a shift clock is input
from the UCK/SCK pin (when the SCKE bit and bit0 of the DDR3 are
"0").
321
CHAPTER 14 8-BIT SERIAL I/O
Table 14.4-1 Explanation of Functions of Each Bit in Serial Mode Register (SMR) (2/2)
Bit name
Function
This bit is used to select whether to transfer serial data, starting at the lowest
bit (LSB first, BDS = 0) or the highest bit (MSB first, BDS = 1). When this
bit is set to "0", serial data is transferred, starting at the lowest bit. When it is
set to "1", serial data is transferred, starting at the highest bit.
Note:
BDS:
Transfer direction
selection bit
bit1
If this bit is rewritten after serial data has been written to the SDR to
replace higher data with lower data, the data in the SDR becomes invalid.
•
•
This bit is used to control serial I/O transfer start and allowance. It can
also be used to judge whether serial I/O transfer terminated.
If this bit is set to "1" when the internal shift clock is selected (when the
CKS1 and CKS0 bits are not 11 ), the shift clock counter is cleared and
B
serial I/O transfer is started.
•
If this bit is set to "1" when the external shift clock is selected (when the
CKS1 and CKS0 bits are 11 ), serial I/O transfer is allowed and the shift
B
SST:
clock counter is cleared. The transfer side enters the external shift clock
input wait state.
bit0
Serial I/O transfer start bit
•
•
When serial I/O transfer terminates, this bit is set (cleared) to "0" and the
SIOF bit is set to "1".
If this bit is set to "0" during serial I/O transfer (SST = 1), serial I/O
transfer is suspended.
When serial I/O transfer is suspended, it is necessary to reset the SDR of
the data output side and restart data input side transfer (clear the shift
clock counter).
322
CHAPTER 14 8-BIT SERIAL I/O
14.4.2
Serial Data Register (SDR)
The serial data register (SDR) retains 8-bit serial I/O transfer data. The SDR functions as
a transmission data register at serial output operation. It functions as a reception data
register at serial input operation.
■ Serial Data Register (SDR)
Figure 14.4-3 shows the bit structure of the SDR.
Figure 14.4-3 Serial Data Register (SDR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
003AH
Initial value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and Writable
: Undefined
X
● At serial output operation
The SDR functions as a transmission data register at serial output operation. When serial I/O transfer is
started (SMR: SST = 1), the 8-bit serial data written to the SDR is transferred. Transmission data does not
remain in the SDR because it is shifted out via serial I/O transfer.
● At serial input operation
The SDR functions as a reception data register. When serial I/O transfer is started (SMR: SST = 1), the
serially transferred reception data is stored in the SDR.
● When the serial I/O is in transfer operation
When the serial I/O is in transfer operation, do not write data to the SDR. Moreover, note that the read
values have no significance.
When serial output and serial input are allowed at the same time, serial I/O operation is performed.
323
CHAPTER 14 8-BIT SERIAL I/O
14.5
Interrupt of 8-Bit Serial I/O
An 8-bit serial I/O interrupt is caused by completion of 8-bit serial data I/O.
■ Interrupt at Serial I/O Operation
In the 8-bit serial I/O, serial output operation and serial input operation are performed at the same time.
When serial I/O transfer is started, the values in the serial data register (SDR) are input and output on a per
bit basis in synchronization with the set shift clock cycle. When the shift clock of the 8th bit rises, the
interrupt request flag bit (SMR: SIOF) is set to "1".
In this case, when the interrupt request output allowance bit is allowed (SMR: SIOE = 1), the interrupt
request (IRQC) for CPU interrupt occurs.
Write "0" to the SIOF bit with the interrupt processing routine and clear the interrupt request. When 8-bit
serial output is completed, the SIOF bit is set irrespective of the SIOE bit value.
If serial I/O transfer stop (SMR: SST = 0) and serial data transfer termination take place at the same time
during serial I/O operation, the interrupt request flag bit (SMR: SIOF = 1). If the SIOE bit is allowed (0 →
1), however, the interrupt request occurs immediately.
■ 8-bit Serial I/O Interrupt Register and Vector Table
Table 14.5-1 8-bit Serial I/O Interrupt Register and Vector Table
Interrupt level setting register
Register Setting bit
ILR4 (007E )
Vector table address
Higher Lower
FFE2 FFE3
H
Interrupt name
IRQC
LC1 (bit1) LC0 (bit0)
H
H
324
CHAPTER 14 8-BIT SERIAL I/O
14.6
Operations of Serial Output Functions
In the 8-bit serial I/O, 8-bit serial output operation synchronized with a shift clock is
possible.
■ Serial Output Operation
Serial output operation is divided into serial output operation using an internal shift clock and serial output
operation by using the external shift clock. When serial I/O operation is allowed, serial data is input in the
SDR and, at the same time, the contents of the SDR are output to the serial data output pin (SO).
● Serial output operation via internal shift clock
Serial output operation using the internal shift clock requires the settings shown in Figure 14.6-1 .
Figure 14.6-1 Settings Required for Serial Output Operation using Internal Shift Clock
bit7
bit6
bit5
bit4
bit3
bit2
bit1
BDS
bit0
SST
1
SMR
SIOF
SIOE
SCKE
1
SOE
1
CKS1
CKS0
Other than 11
Transmission data setting
SDR
SSEL
SSEL
1
: Used bit
: Set "1"
1
When serial output operation is started, the contents of the SDR are output to the SO pin in synchronization
with the falling edge of the selected internal shift clock. In this case, the transfer destination (serial input
side) must be in the external shift clock input wait state.
325
CHAPTER 14 8-BIT SERIAL I/O
● Serial output operation using external shift clock
Serial output operation with the external shift clock requires the settings shown in Figure 14.6-2 .
Figure 14.6-2 Settings Required for Serial Output Operation using External Shift Clock
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SMR
SDR
SIOF
SIOE
SCKE
0
SOE
1
CKS1
1
CKS0
1
BDS
SST
1
Transmission data setting
DDR3
0
SSEL
SSEL
1
: Used bit
: Unused bit
: Set "0"
0
1
: Set "1"
When serial output operation is allowed, the contents of the SDR are output to the SO pin in synchronization
with the falling edge of the external shift clock. When serial operation is completed, immediately reset the SDR,
set it again, then allow serial output operation (SMR: SST = 1) to prepare for the output of the next data.
When the remote serial input operation (rising edge) is completed and the 8-bit serial I/O enters the idle
state (state in which it waits for the output of the next data), set the external shift clock to a high level.
Figure 14.6-3 shows 8-bit serial output operation.
Figure 14.6-3 8-bit Serial Output Operation
For LSB first
bit7
#7
bit6
#6
bit5
#5
bit4
#4
bit3
#3
bit2
#2
bit1
#1
bit0
#0
SO pin
SDR
Serial output data
#0
#1
#2
#3
#4
#5
#6
#7
Clear via program
Shift clock
SIOF bit
0
1
2
3
4
5
6
7
Transfer start
Interrupt request
SST bit
Automatic clear at transfer end
■ Operation at Serial Output Completion
At the rising edge of the shift clock for serial data of the 8th bit, the interrupt request flag bit (SMR: SIOF)
is set to "1" and the serial I/O start bit (SMR: SST) is set (cleared) to "0".
326
CHAPTER 14 8-BIT SERIAL I/O
14.7
Operations of Serial Input Functions
In the 8-bit serial I/O, 8-bit serial input operation synchronized with a shift clock is
possible.
■ Serial Input Operation
Serial input operation is divided into serial input operation with an internal shift clock and serial input
operation with an external shift clock. When serial I/O operation is allowed, serial data is input in the SDR
and, at the same time, the contents of the SDR are output to the serial data output pin (SO).
● Serial input operation using internal shift clock
Figure 14.7-1 Settings Required for Serial Input Operation using Internal Shift Clock
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SMR
SIOF
SIOE
SCKE
SOE
CKS1
CKS0
BDS
SST
1
1
Other than 11
Reception data storage
SDR
DDR3
0
SSEL
SSEL
1
0 : Set "0"
: Set "1"
: Used bit
: Unused bit
1
When serial input operation is started, the value of the serial data input pin (SI) is captured and held in the
SDR in synchronization with the rising edge of the selected internal shift clock. In this case, the SDR of the
transfer destination (serial output side) must already be set and the transfer destination must be in the
external shift clock input wait state.
327
CHAPTER 14 8-BIT SERIAL I/O
● Serial input operation using external shift clock
Serial input operation with the external shift clock requires the settings shown in Figure 14.7-2 .
Figure 14.7-2 Settings Required for Serial Input Operation using External Shift Clock
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SMR
SDR
SIOF
SIOE
SCKE
SOE
CKS1
CKS0
BDS
SST
0
1
1
1
Reception data storage
DDR3
0
0
SSEL
1
SSEL
: Used bit
0
1
: Set "0"
: Set "1"
: Unused bit
When serial input operation is allowed, the value of the SI pin is captured and held in the SDR in
synchronization with the rising edge of the external shift clock. When serial input is completed,
immediately read the SDR and allow serial input operation (SMR: SST = 1) to prepare for the input of the
next data. In this case, when the 8-bit serial I/O is idle (state in which it is waiting for the output of the next
data), keep the external shift clock at a "H" level.
Figure 14.7-3 shows 8-bit serial input operation.
Figure 14.7-3 8-bit Serial Input Operation
For MSB first
bit7
#7
bit6
#6
bit5
#5
bit4
#4
bit3
#3
bit2
#2
bit1
#1
bit0
#0
SI pin
SDR
Serial input data
Shift clock
#7
#6
#5
#4
#3
#2
#1
#0
Clear via program
0
1
2
3
4
5
6
7
SIOF bit
Transfer start
Interrupt request
SST bit
Automatic clear at transfer end
■ Operation at Serial Input Completion
At the rising edge of the shift clock for the serial data of the 8th bit, the interrupt request flag bit (SMR:
SIOF) is set to "1" and the serial I/O start bit (SMR: SST) is set (cleared) to "0".
328
CHAPTER 14 8-BIT SERIAL I/O
14.8
8-Bit Serial I/O Operation in Each Mode
This section describes the operation of the 8-bit serial I/O if the 8-bit serial I/O switches
to sleep or stop mode or a stop request is issued when it is in operation.
■ When the Internal Shift Clock is Used
● 8-bit serial I/O operation in sleep mode
In sleep mode, as shown in Figure 14.8-1 , the 8-bit serial I/O continues data transfer without stopping the
serial I/O operation.
Figure 14.8-1 8-bit Serial I/O Operation in Sleep Mode (Internal Shift Clock)
SCK output
SST bit
Clear via program
SIOF bit
Interrupt request
#0
#1
#2
#3
#4
#5
#6
#7
SO pin output
Sleep mode
SLP bit
(STBC register)
Sleep mode release via IRQC
● 8-bit serial I/O operation in stop mode
In stop mode, as shown in Figure 14.8-2 , the 8-bit serial I/O stops the serial I/O operation and suspends
data transfer. After stop mode has been released, reinitialize the 8-bit serial I/O because operation is
resumed halfway.
329
CHAPTER 14 8-BIT SERIAL I/O
Figure 14.8-2 8-bit Serial I/O Operation in Stop Mode (Internal Shift Clock)
SCK output
Oscillation stabilization
wait time
SST bit
Clear via program
Stop mode request
SIOF bit
Interrupt request
#7
#0
#1
#2
#3
#4
#5
#6
SO pin output
Stop mode
STP bit
(STBC register)
Stop mode release via external interrupt
● 8-bit serial I/O operation at issuance of stop request during operation
As shown in Figure 14.8-3 , if operation is stopped (SMR: SST = 0) during data transfer, the 8-bit serial I/O
stops data transfer and clears the shift clock counter. For this reason, the transfer destination must also be
initialized. If serial output is in operation, set the SDR again before restarting the 8-bit serial I/O.
Figure 14.8-3 8-bit Serial I/O Operation at Issuance of Stop Request during Operation(Internal Shift Clock)
SCK output
SST bit
Operation stop
Restart
SDR register resetting
SIOF bit
#0
#1
#2
#3
#4
#5
#0
#1
SO pin output
330
CHAPTER 14 8-BIT SERIAL I/O
■ When the External Shift Clock is Used
● 8-bit serial I/O operation in sleep mode
In sleep mode, as shown in Figure 14.8-4 , the 8-bit serial I/O continues data transfer without stopping the
serial I/O operation.
Figure 14.8-4 8-bit Serial I/O Operation in Sleep Mode (External Shift Clock)
Clock for the next data
SCK input
Transfer stop state
SST bit
Clear via program
SIOF bit
Interrupt request
#0
#1
#2
#3
#4
#5
#7
#6
SO pin output
Sleep mode
STP bit
(STBC register)
Sleep mode release via IRQC
● 8-bit serial I/O operation in stop mode
In stop mode, as shown in Figure 14.8-5 , the 8-bit serial I/O stops the serial I/O operation and suspends
data transfer. After stop mode has been released, a transfer destination error occurs because operation is
resumed halfway. In this case, initialize the 8-bit serial I/O.
Figure 14.8-5 8-bit Serial I/O Operation in Stop Mode (External Shift Clock)
Clock for the next data
SCK input
#6
#7
Oscillation stabilization
wait time
SST bit
Clear via
program
Stop mode request
SIOF bit
Interrupt
request
#0
#1
#2
#3
#4
#5
#6
#7
SO pin output
Stop mode
Transfer error occurrence
STP bit
(STBC register)
Stop mode release via external interrupt
331
CHAPTER 14 8-BIT SERIAL I/O
● 8-bit serial I/O operation at issuance of stop request during operation
As shown in Figure 14.8-6 , if operation is stopped (SMR: SST = 0) during data transfer, the 8-bit serial I/O
stops data transfer and clears the shift clock counter. For this reason, the transfer destination must also be
initialized. If serial output is in operation, set the SDR again before restarting the 8-bit serial I/O. In this
case, when the external clock is input, the SO pin output changes.
Figure 14.8-6 8-bit Serial I/O Operation at Issuance of Stop Request during Operation
(External Shift Clock)
Clock for the next data
SCK input
#6
Operation stop
SDR register resetting
#7
SST bit
Restart
SIOF bit
#0
#1
#2
#3
#4
#5
#0
#1
SO pin output
332
CHAPTER 14 8-BIT SERIAL I/O
14.9
Notes on Using 8-Bit Serial I/O
This section provides notes on using the 8-bit serial I/O.
■ Notes on Using 8-bit Serial I/O
● Error at serial transfer start
The time at which serial I/O transfer is started with a serial transfer program (SMR: SST = 1) is
asynchronous with the time when the falling edge (output) or rising (input) edge of a shift clock occurs. For
this reason, the time that lasts until the first serial data is input or output is delayed by a maximum of one
cycle of the set shift clock.
● Malfunction due to noise
If external noise causes an extra pulse (pulse exceeding the hysteresis width) to be placed on a shift clock
during serial data transfer, the 8-bit serial I/O may malfunction.
● Notes on setting via program
Write data to the serial mode register (SMR) and serial data register (SDR) only when the 8-bit serial I/
•
O is stopped (SMR: SST = 0).
•
•
When starting or allowing serial I/O transfer (SMR: SST=1), do not change other bits of the SMR.
If MSB first is set when a shift clock is used in external shift clock input, the highest bit level is output
as the SO pin output level. If LSB first is set, the lowest bit level is output as the SO pin output level.
MSB first and LSB first are set when the external shift clock is input. In this case, however, serial data
output must be allowed (SMR: SOE = 1) even if serial I/O transfer is stopped (SMR: SST = 0).
•
•
If serial I/O transfer stop (SMR: SST = 0) and serial data transfer termination take place at the same
time during serial I/O operation, the interrupt request flag bit (SMR: SIOF) is not set to "1".
If the SIOF bit is set to "1" and the interrupt request output allowance bit is enabled (SMR: SIOE = 1),
control cannot return from interrupt processing. Be sure to clear the SIOF bit.
● Shift clock idle state
The external shift clock must maintain the "H" level during the wait time between one 8-bit data transfer
and another (idle state). When the internal shift clock is selected (SMR: CKS1, CKS0 = not 11 ) and the
B
P30/UCK/SCK pin is used as the shift clock output pin (SMR: SCKE = 1), data is output at the "H" level in
the idle state.
Figure 14.9-1 shows the shift clock idle state.
Figure 14.9-1 Shift Clock Idle State
External
shift
clock
8-bit data transfer
Idle state
8-bit data transfer
Idle state
Idle state
333
CHAPTER 14 8-BIT SERIAL I/O
14.10 Example of 8-Bit Serial I/O Connection
This section provides an example of mutual connection between 8-bit serial I/Os of
MB89202/F202RA series for bidirectional serial I/O operation.
■ When Bidirectional Serial I/O Operation is Performed
Figure 14.10-1 Example of 8-bit Serial I/O Connection (Interface between MB89202/F202RA Series)
SO
SI
SI
SO
SIO-A
SIO-B
Input
Output
SCK
SCK
Internal shift clock
External shift clock
334
CHAPTER 14 8-BIT SERIAL I/O
Figure 14.10-2 Bidirectional Serial I/O Operation
SIO-A
SIO-B
START
START
Stop SIO-B operation
Stop SIO-A operation
(SST=0)
(SST=0)
Set SI pin to serial data
input (input port)
Set SI pin to serial data
input (input port)
-
-
Set SCK pin to shift clock
-
-
Set SCK pin to shift clock
input
output
Set SO pin to serial data
output
Set SO pin to serial data
output
- Select internal shift clock
-
-
Select external shift clock
-
Set data transfer (shift
Select same data transfer
clock) direction
(shift) direction as SIO-A
Set output data
Is SIO-B in
serial transfer allowance
state?(*1)
NO
Allow serial data transfer
Transfer allowance state
YES
(SST=1)
Set output data
Start serial I/O transfer(*2)
(SST=1)
SIO-A
SIO-B
Serial data output via SIO-A
Serial data transfer
Serial data transfer
Simultaneous data input via SIO-B
NO
NO
End of 8-bit transfer?
End of 8-bit transfer?
(*3)
(*3)
YES(SST=0)
YES(SST=0)
Read input data
Read input data
YES
Is next data available?
SST: The SST bit is the serial I/O transfer start bit of the serial mode
register (SMR).
NO
END
*1
If only the SO, SI, and SCK pins are connected, there is no method for directly checking
whether SIO-B is in the serial transfer allowance state. For this reason, a timer, etc., must be
used to monitor the wait time period that lasts until SIO-B is allowed for transfer via software.
*2
If SIO-B is not allowed for serial I/O transfer, data cannot be transferred correctly even if
SIO-A starts serial I/O transfer.
*3
When 8-bit data transfer terminates, a interrupt request occurs.
335
CHAPTER 14 8-BIT SERIAL I/O
14.11 Program Example for 8-Bit Serial I/O
This section provides program example for 8-bit serial I/O.
■ Program Example for 8-bit Serial Output
● Processing Specifications
•
The 8-bit serial output program outputs 8-bit serial data (55 ) from the SO pin of the 8-bit serial I/O.
H
When serial I/O transfer terminates, an interrupt occurs.
•
•
The program resets transfer data with the interrupt processing routine and outputs it continuously.
The program operates in accordance with the internal shift clock. This clock is output from the SCK
pin.
•
If the shift clock is 32t
when the maximum gear speed (1 instruction cycle = 4/F ) at the 12.5-
INST CH
MHz oscillation (F ), the transfer rate and interrupt cycle are as follows:
CH
Transfer rate = 12.5 MHz/4/32 = 97.7 kbps, interrupt cycle = 8 × 32 × 4/10 MHz = 81.92 µs
● Coding example
SMR
SDR
SSEL
SIOF
SST
EQU
EQU
EQU
EQU
EQU
EQU
0039H
003AH
003BH
SMR:7
SMR:0
007EH
ABS
; Address of serial mode register
; Address of serial data register
; Address of serial/UART selection register
; Defines the interrupt request flag bit.
; Defines the serial I/O transfer start bit.
; Address of interrupt request setting register 4
; [DATA SEGMENT]
ILR4
INT_V DSEG
ORG
0FFE2H
WARI
IRQC
INT_V ENDS
;--------------------Main program--------------------------------------------------------------------------
DW
; Sets an interrupt vector.
CSEG
; [CODE SEGMENT]
; The stack pointer (SP), etc., are already initialized.
:
CLRI
CLRB
MOV
MOV
MOV
; Disables interrupts.
SST
; Stops serial I/O transfer.
ILR4,#11111101B ; Sets the interrupt level to 1.
SDR,#55H ; Sets transfer data (55H).
SMR,#01111000B ; Clears the interrupt request flag, allows the interrupt
request output, shift clock output (SCK), and serial data
output (SO), selects 32tINST, and sets LSB first.
MOV
SETB
SETI
:
SSEL,#00000001B ; Selects the 8-bit serial I/O.
SST
; Starts serial I/O transfer.
; Enables interrupts.
336
CHAPTER 14 8-BIT SERIAL I/O
;--------------------Interrupt processing routine----------------------------------------------------------
WARI
CLRB
SIOF
; Clears the interrupt request flag.
PUSHW
XCHW
PUSHW
MOV
A
A,T
; Saves A and T.
A
SDR,#55H
; Resets transfer data (55 ).
H
SETB
:
SST
; Starts serial I/O transfer.
User processing
:
POPW
XCHW
POPW
RETI
A
A,T
A
; Returns A and T.
ENDS
; -------------------------------------------------------------------------------------------------------------------
END
■ Program Example for 8-bit Serial Input
● Processing specifications
•
The 8-bit serial input program inputs 8-bit serial data from the SI pin of the 8-bit serial I/O. When serial
I/O transfer terminates, an interrupt occurs.
•
•
The program reads transfer data with the interrupt processing routine and inputs it continuously.
The program uses the external shift clock to be input from the SCK pin.
● Coding example
DDR3
SMR
SDR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000DH
0039H
003AH
003BH
SMR:7
SMR:0
007EH
ABS
; Address of data direction register 3
; Address of serial mode register
; Address of serial data register
SSEL
SIOF
SST
; Address of serial/UART selection register
; Defines the interrupt request flag bit.
; Defines the serial I/O transfer start bit.
; Address of interrupt request setting register 4
; [DATA SEGMENT]
ILR4
INT_V DSEG
ORG
0FFE2H
WARI
IRQC
INT_V ENDS
;--------------------Main program---------------------------------------------------------------------------
DW
; Sets an interrupt vector.
CSEG
; [CODE SEGMENT]
; The stack pointer (SP), etc., is already initialized.
:
MOV
CLRI
CLRB
MOV
DDR3,#00000000B ; Sets the P30/SCK and P32/SI pins to input.
; Disables interrupts.
SST
; Stops serial I/O transfer.
ILR4,#11111101B ; Sets the interrupt level to 1.
337
CHAPTER 14 8-BIT SERIAL I/O
MOV
SMR,#01001100B ; Clears the interrupt request flag, allows the interrupt
request output, sets shift clock input (SCK), prohibits
serial data output (SO), selects the external shift clock,
and sets LSB first.
MOV
SETB
SETI
:
SSEL,#00000001B ; Selects the 8-bit serial I/O.
SST
; Allows serial I/O transfer.
; Enables interrupts.
;--------------------Interrupt processing routine-----------------------------------------------------------
WARI
CLRB
PUSHW
XCHW
PUSHW
MOV
SETB
:
SIOF
A
; Clears the interrupt request flag.
A,T
A
A,SDR
SST
; Reads transfer data.
; Allows serial I/O transfer.
User processing
:
POPW
XCHW
POPW
RETI
A
A,T
A
ENDS
; --------------------------------------------------------------------------------------------------------------------
END
338
CHAPTER 15 BUZZER OUTPUT
15.1
Overview of the Buzzer Output
For the buzzer output, four kinds of output frequencies (square waves) can be selected.
The buzzer output may be used for the confirmation tone of key input and other tones.
■ Buzzer Output Function
The buzzer output function is a function for outputting a signal (square wave) used for tones such as a
confirmation tone.
For the buzzer output, it is selectable whether to output one of four output frequencies or to disable the
output.
As the buzzer output, four kinds of divided-frequency outputs are supplied from the time-base timer.
Note:
The time-base timer supplies clock for the buzzer output. Therefore, buzzer output will be affected
when time-base timer is cleared.
Table 15.1-1 lists the four kinds of output frequencies (square waves) specifiable for the buzzer output.
Table 15.1-1 Output Frequencies
Clock supplier
Buzzer output
Square wave output (at 12.5 MHz)
13
13
2 /F
F
F
F
F
/2 (1.526 kHz)
CH
CH
CH
CH
CH
CH
CH
CH
12
12
2 /F
/2 (3.052 kHz)
time-base timer
11
11
2 /F
/2 (6.104 kHz)
10
10
2 /F
/2 (12.21 kHz)
F
: Oscillation frequency
CH
Note:
Calculation example of an output frequency
10
If time-base timer output F /2 is selected in the buzzer register (BZCR) (BZ2=1, BZ1=0, and
CH
BZ0=0) and the oscillation (F ) is 12.5 MHz, the output frequency being output from the BZ pin is
CH
calculated as follows:
10
Output frequency = FCH/2
= 12.5 MHz/1024
12.21 kHz
340
CHAPTER 15 BUZZER OUTPUT
15.2
Configuration of the Buzzer Output
The buzzer output consists of the following two blocks:
• Buzzer output selector
• Buzzer register (BZCR)
■ Block Diagram of the Buzzer Output
Figure 15.2-1 Block Diagram of Buzzer Output
Internal data bus
BZCR
BZ2
BZ1
BZ0
Buzzer enable signal
13
12
11
10
2
2
2
2
/FCH
/FCH
/FCH
/FCH
Selector
output
Buzzer output
selector
Pin
From time-base timer
P37/BZ/PPG
FCH
: Oscillation frequency
● Buzzer output selector
The buzzer output selector is a circuit for selecting one of the four frequencies (square waves) output from
the time-base timer. The buzzer register (BZCR) sets it.
● Buzzer register (BZCR)
The buzzer register (BZCR) is a register for setting the buzzer output frequency and enable the buzzer
output. When the BZCR register sets an output frequency (other than 000 ), the buzzer output is enabled so
B
that the P37/BZ/PPG pin automatically becomes the buzzer output (BZ) pin. Even if the PPG pin has been
enabled, the BZ pin has higher priority.
341
CHAPTER 15 BUZZER OUTPUT
15.3
Pin of the Buzzer Output
The pin related to the buzzer output is P37/BZ/PPG.
■ P37/BZ/PPG Pin
The P37/BZ/PPG pin works as a general-purpose I/O (P37) pin, output pin for the buzzer output (BZ), or
output pin for the 12-bit PPG (PPG).
● BZ pin
The BZ pin outputs the square wave for the buzzer of the frequency having been specified for the BZ pin.
When a buzzer output frequency is specified (other than BZCR:BZ2,BZ1,BZ0=000 ), the P37/BZ/PPG pin
B
automatically works as the BZ pin regardless of the value of output latch. Even if the PPG output has been
enabled, it works as the BZ pin that has higher priority.
■ Block Diagram of the Pin Related to the Buzzer Output
Figure 15.3-1 Block Diagram of Pin Related to Buzzer Output
PDR
Stop mode (SPL=1)
Pull-up resistor
PDR read
Peripheral output
Peripheral
output
enable
PDR read
(At read-modify-write)
Pch
Nch
Output latch
PDR write
DDR write
Pin
P37/BZ/PPG
DDR
Stop mode
(SPL=1)
PUL read
PUL
PUL write
Note:
If pull-up resistor supported is specified by the pull-up setting register, the state of the pin in stop mode
(SPL=1) is not Hi-Z but "H" level (pull-up state). During a reset, however, the pull-up is disabled and
the state is Hi-Z.
342
CHAPTER 15 BUZZER OUTPUT
15.4
Buzzer Register (BZCR)
The buzzer register (BZCR) is used to select an output frequency of the buzzer and also
serves as the buzzer output enable.
■ Buzzer Register (BZCR)
Figure 15.4-1 Buzzer Register (BZCR)
Address bit7
bit6
bit5
bit4 bit3 bit2 bit1
bit0 Initial value
0018
BZ2 BZ1 BZ0 ----- 000
R/W R/W R/W
H
B
Buzzer selection bits (FCH: 12.5 MHz)
Works as a general-purpose output port (P37)
or the 12-bit PPG output (PPG).
BZ2
0
BZ1
0
BZ0
0
1
Outputs FCH/213 (1.526 kHz) to the BZ pin.
0
0
0
1
1
1
1
0
1
12
Outputs FCH/2 (3.052 kHz) to the BZ pin.
0
1
Outputs FCH/211 (6.104 kHz) to the BZ pin.
Outputs FCH/210 (12.21 kHz) to the BZ pin.
1
0
0
1
1
0
1
R/W
FCH
: Readable/Writable
: Unused
: Initial value
0
1
: Oscillation frequency
343
CHAPTER 15 BUZZER OUTPUT
Table 15.4-1 Functions of Each Bit in Buzzer Register (BZCR)
Bit name
Function
bit7
to
bit3
•
•
Undefined at read
No effect on the operation at write
Unused bits
•
•
Select a buzzer output and enable the output.
If 000 is set to these bits, the buzzer output is
B
disabled and the pin works as a general-purpose port
(P37) or as the 12-bit PPG output (PPG). With the
exception of 000 , the pin becomes the buzzer pin
bit2
to
bit0
B
BZ2, BZ1, and BZ0:
Buzzer selection bits
and outputs a square wave. Even if the pin has been
functioning as the 12-bit PPG output, setting a value
other than 000 causes the pin to work as the BZ pin
B
prior to its operation as the PPG pin.
For the buzzer output, four kinds of time-base timer
divided cycle outputs are supplied.
344
CHAPTER 15 BUZZER OUTPUT
15.5
Program Example for Buzzer Output
This section shows an program example for buzzer output.
■ Program Example for Buzzer Output
● Processing specification
Suppose that the buzzer output of 3.052 kHz is output to the BZ pin and then the buzzer output is cut off.
12
If 2 /F is selected when the oscillation (F ) is 12.5 MHz, the buzzer output frequency is calculated as
CH
CH
follows:
Buzzer output frequency: 12.5 MHz/2 = 12.5 MHz/4096 = 3.052 kHz
12
● Coding example
BZCR EQU
;-------------------Main program-----------------------------------------------------------------
0018H
; Address of the buzzer register
CSEG
; [CODE SEGMENT]
:
MOV
BZCR,#00000010 ; Buzzer output on (3.052 kHz / Oscillation of 12.5 MHz)
:
:
:
MOV
BZCR,#00000000 ; Buzzer output off (I/O port or PPG output)
:
:
ENDS
; ----------------------------------------------------------------------------------------------------------
END
345
CHAPTER 15 BUZZER OUTPUT
346
CHAPTER 16 WILD REGISTER FUNCTION
16.1
Overview of the Wild Register Function
The wild register function is a function for patching the faulty part of a program by
setting the address and the correct data in the incorporated registers. Up to two bytes
of data correction is possible.
■ Wild Register Function
The wild register function assigns an address in the ROM area of the microcontroller and replaces the
existing data corresponding to the address, with new data. For example, if an error exists in a program,
setting the address of the faulty part and correction data to the register can correct the faulty data.
■ Wild Register Applicable Addresses
The address area where the wild register function can apply varies slightly with the models. Table 16.1-1
shows the wild register applicable addresses for each model.
Table 16.1-1 Wild Register Applicable Addresses
Model name
MB89V201
ROM area
8000 to FFFF
H
H
C000 to FFFF
MB89202/F202
H
H
Note:
The wild register function cannot be debugged with a tool. Perform the operation check of the wild
register on the actual microcontroller, MB89202/F202/F202RA.
348
CHAPTER 16 WILD REGISTER FUNCTION
16.2
Configuration of the Wild Register Function
The wild register function consists of the following two blocks:
Memory area part
• Data setting register (WRDR)
• Higher address set register (WRARH)
• Lower address set register (WRARL)
Control circuit part
■ Block Diagram of the Wild Register Function
Figure 16.2-1 Block Diagram of Wild Register Function
Incorporated ROM/RAM
Wild register function
Memory area part
Control circuit part
Data setting register
(WRDR)
Access control circuit
Address comparison
EN register (WREN)
Higher address set
register (WRARH)
Matching signal
Address comparison
Lower address set
register (WRARL)
Access control
● Memory area part
This part consists of the data setting register, higher address set register ("H" address), and lower address
set register ("L" address). Set the address and data to be replaced by the wild register. The MB89202/
F202RA series incorporates two bytes for each register.
● Control circuit part
This part compares the data held in the address set registers and the actual data on the address bus. If it
detects a match, it sets the data in the data setting register to the data bus. The control circuit part can
control the operation by the address comparison EN register.
349
CHAPTER 16 WILD REGISTER FUNCTION
16.3
Registers of the Wild Register Function
Figure 16.3-1 shows the registers related to the wild register function.
■ Registers Related to the Wild Register Function
Figure 16.3-1 Registers Related to Wild Register Function
(Data setting register)
WRDR0,WRDR1
Address
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0042
0045
RD07
R/W
RD06
R/W
RD05
R/W
RD04
R/W
RD03
R/W
RD02
R/W
RD01
R/W
RD00 XXXXXXXX
R/W
H
H
B
(Higher address set register)
WRARH0,WRARH1
Initial value
XXXXXXXX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
0040
H
RA15
R/W
RA14
R/W
RA13
R/W
RA12
R/W
RA11
R/W
RA10
R/W
RA09
R/W
RA08
R/W
B
0043
H
(Lower address set register)
WRARL0,WRARL1
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
0041
0044
RA07
R/W
RA06
R/W
RA05
R/W
RA04
R/W
RA03
R/W
RA02
R/W
RA01
R/W
RA00 XXXXXXXX
R/W
H
H
B
WREN (Address comparison EN register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
Initial value
------00
0046
EN01
R/W
EN00
R/W
H
B
(Data test set register)
WROR
Address
0047
Initial value
------00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RESV1
R/W
RESV0
R/W
H
B
R/W : Readable and Writable
: Unused
X
: Undefined
350
CHAPTER 16 WILD REGISTER FUNCTION
16.3.1
Data Setting Registers (WRDR0 and WRDR1)
The data setting registers (WRDR0 and WRDR1) are registers where the correct data
used by the wild register function is set.
■ Data Setting Register (WRDR)
Figure 16.3-2 Data Setting Register (WRDR)
bit7
bit6
bit5
bit4
bit3
bit2
RD02
bit1
bit0
Address
Initial value
XXXXXXXX
WRDR0
WRDR1
0042
H
RD07
R/W
RD06
R/W
RD05
R/W
RD04
R/W
RD03
R/W
RD01
R/W
RD00
R/W
B
B
R/W
0045
H
RD07
R/W
RD06
R/W
RD05
R/W
RD04
R/W
RD03
R/W
RD02
R/W
RD01
R/W
RD00 XXXXXXXX
R/W
: Readable and Writable
: Undefined
R/W
X
Table 16.3-1 Functions of Data Setting Register (WRDR)
Wild register number
Register name
WRDR0
Function
0
1
1-byte registers that store the data at the address assigned by WRARL
and WRARH. The data will be effective at the addresses (WRARL and
WRARH) corresponding to the individual wild register numbers.
WRDR1
Note:
The WRDR register is readable, only when the WREN register (address comparison EN register) is set.
351
CHAPTER 16 WILD REGISTER FUNCTION
16.3.2
Higher Address Set Registers (WRARH0 and WRARH1)
The higher address set registers (WRARH0 and WRARH1) are registers where the
higher byte of addresses to be corrected by the wild register function are set.
■ Higher Address Set Register (WRARH)
Figure 16.3-3 Higher Address Set Register (WRARH)
Address
bit7
Initial value
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WRARH0 0040
RA15
R/W
RA14
R/W
RA13
R/W
RA12
R/W
RA11
R/W
RA10
R/W
RA09
R/W
RA08 XXXXXXXX
R/W
H
B
B
WRARH1 0043
RA15
R/W
RA14
R/W
RA13
R/W
RA12
R/W
RA11
R/W
RA10
R/W
RA09
R/W
RA08 XXXXXXXX
R/W
H
: Readable and Writable
: Undefined
R/W
X
Table 16.3-2 Functions of Higher Address Set Register (WRARH)
Wild register number
Register name
WRARH0
Function
1-byte registers that specify the higher addresses of memory being
assigned. They specify the addresses corresponding to the individual
wild register numbers.
0
1
WRARH1
352
CHAPTER 16 WILD REGISTER FUNCTION
16.3.3
Lower Address Set Registers (WRARL0 and WRARL1)
The lower address set registers (WRARL0 and WRARL1) are registers where the lower
byte of addresses to be corrected by the wild register function are set.
■ Lower Address Set Register (WRARL)
Figure 16.3-4 Lower Address Set Register (WRARL)
Initial value
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WRARL0 0041
RA07
R/W
RA06
R/W
RA05
R/W
RA04
R/W
RA03
R/W
RA02
R/W
RA01
R/W
RA00 XXXXXXXX
R/W
B
B
H
WRARL1 0044
RA07
R/W
RA06
R/W
RA05
R/W
RA04
R/W
RA03
R/W
RA02
R/W
RA01
R/W
RA00 XXXXXXXX
R/W
H
R/W : Readable and Writable
: Undefined
X
Table 16.3-3 Functions of Lower Address Set Register (WRARL)
Wild register number
Register name
WRARL0
Function
1-byte registers that specify the lower addresses of memory being
assigned. They specify the addresses corresponding to the individual
wild register numbers.
0
1
WRARL1
353
CHAPTER 16 WILD REGISTER FUNCTION
16.3.4
Address Comparison EN Register (WREN)
The address comparison EN register (WREN) is a register that enables the operation of
wild register function for the individual wild register numbers.
■ Address Comparison EN Register (WREN)
Figure 16.3-5 Address Comparison EN Register (WREN)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address
Initial value
0046
H
EN01
R/W
EN00
R/W
------00
B
WREN
R/W : Readable and Writable
: Unused
Table 16.3-4 Explanation of Functions of Each Bit in Address Comparison EN Register (WREN)
Bit name Function
bit7
to
bit2
Undefined at read
No effect to the operation at write
Unused bits
When this bit is "0", the corresponding wild register function does not work.
When this bit is "1", the wild register function is enabled. If there is a match with the
address held in WRARH1 and WRARL1, the value of WRDR1, instead of ROM, is
output to the internal bus.
bit1
bit0
EN01
EN00
When this bit is "0", the corresponding wild register function does not work.
When this bit is "1", the wild register function is enabled. If there is a match with the
address held in WRARH0 and WRARL0, the value of WRDR0, instead of ROM, is
output to the internal bus.
354
CHAPTER 16 WILD REGISTER FUNCTION
16.4
Operations of the Wild Register Functions
This section describes the operation order of the wild register.
■ Operation Order of the Wild Register Function
Table 16.4-1 describes the operation order of the wild register. In the operation example column, it corrects
data at address FC36 , from FF to B5 .
H
H
H
Table 16.4-1 Operation Order of Wild Register
Operation
Operation example
Address: FC36 /data: FF
H
H
Set an address of the wild register correspondence area to
the address set register.
WRARL0=36
1
H
WRARH0=FC
H
WRDR0=B5
2
3
Set the correction data to the data setting register.
Set "1" to the address comparison EN00 bit.
H
WREN=01
H
When address = FC36 is accessed
H
4
The wild register works at the time of address matching.
Data = B5
H
■ Wild Register Addresses List
Table 16.4-2 lists the addresses corresponding to the wild register numbers.
Table 16.4-2 Wild Register Addresses List
Higher address
Lower address
Data
Register name
Register name
WRARH0
Address
Register name
WRARL0
Address
Address
1
2
040
041
044
042
WRDR0
WRDR1
H
H
H
H
043
045
WRARH1
WRARL1
H
H
356
CHAPTER 17
FLASH MEMORY
This chapter describes the functions and operation of
the 128K-bit flash memory. The following three methods
are available for writing data to and erasing data from
the flash memory:
1. Parallel programmer
2. Writing/erasing data using a serial programmer
3. Executing programs to write/erase data
This chapter explains "Executing programs to write/
erase data".
Note: A user must create a serial programmer for
writing.
357
CHAPTER 17 FLASH MEMORY
17.1
Overview of Flash Memory
The 128K-bit flash memory is mapped to the C000 to FFFF bank in the CPU memory
H
H
map. The functions of the flash memory interface circuit enable read-access and
program-access from the CPU in the same way as mask ROM. Instructions from the
CPU can be used via the flash memory interface circuit to write data to and erase data
from the flash memory. Internal CPU control therefore enables rewriting of the flash
memory while it is mounted. As a result, improvements in programs and data can be
performed efficiently.
■ Flash Memory Features
•
•
•
•
•
•
16 Kbyte × 8-bit configuration
Use of automatic program algorithm (Embedded Algorthm)
Detection of completion of writing/erasing using data polling or toggle bit functions
Detection of completion of writing/erasing using CPU interrupts
Compatible with JEDEC standard commands
Minimum of 10000 write / erase operations (MB89F202/F202RA)
■ High voltage supply on RST pin (applicable to MB89F202RA only)
During writing data to or erasing all data in flash memory, a typical +10V D.C. voltage should be applied at
the RST pin. After applying the high voltage, wait for 10ms before writing data or erasing all data in flash
memory. And this applied voltage should be kept at the RST pin until data writing or erasing has been
completed.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written to or erased
data from the flash memory, the program in the flash memory must first be copied to RAM. The entire
process is then executed in RAM so that data is simply written to the flash memory. This eliminates the
need for the program to access the flash memory from the flash memory itself.
■ Flash Memory Register
Compatible with JEDEC standard commands
Bit No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0079
INTE
RDYINT
WE
RDY
-
-
-
-
H
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R)
(X)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
358
CHAPTER 17 FLASH MEMORY
17.2
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 17.2-1 Flash Memory Control Status Register (FMCS)
Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
0079H
INTE RDYINT WE RDY
000X----B
R/W R/W R/W
R
Unused bit
Reading / Writing has no effect.
ReaDY bit
RDY
(for enabling data to be written into/erased from flash memory)
Data is being written or erased.
0
1
Data writing/erasing has been completed.
(Subsequent data can be written/erased.)
WE
Write enable bit
0
1
Disables data to be written into/erased from flash memory.
Enables data to be written into/erased from flash memory.
Flash memory operation state indication bit
RDYINT
0
Data is being written/erased.
Data writing/erasing has been completed.
1
(An interrupt request is generated.)
INTE
Causing an interrupt to the CPU to be generated bit
Enables an interrupt when data writing/erasing is completed.
Disables an interrupt when data writing/erasing is completed.
0
1
tINST : Instruction cycle
R/W : Readable/Writable
R
: Read only
: Initial value
359
CHAPTER 17 FLASH MEMORY
Table 17.2-1 Explanation of Functions of Each Bit in the Flash Memory Control Status Register (FMCS)
Bit name
Description
INTE:
Bit causing an interrupt (IRQB) to the CPU to be generated when writing into or erasing
from flash memory is completed.
An interrupt (IRQB) to the CPU is generated when both the INTE bit and RDYINT bit
are "1". If the INTE bit is "0", no interrupt is generated.
Causing an
interrupt to the
CPU to be
generated bit
bit7
bit6
Bit for indicating operation status of flash memory.
This bit is set to "1" when writing into or erasing from flash memory is completed. After
data has been written into or erased from flash memory and this bit has been set to "1",
subsequent data can be written into or erased from flash memory.
Writing "0" clears this bit with "0", while if "1" is written into this bit, it is ignored. This
bit is set to "1" upon the termination of the flash memory automatic algorithm (see
write (RMW) command always reads "1" from this bit.
RDYINT:
Flash memory
operation state
indication bit
Bit for write-enabling flash memory areas.
When this bit is set to "1", a write instruction performed after a command sequence for a
H
H
WE:
Write enable bit
write/erase signals are generated. This bit is used to start a command for writing data into
or erasing data from flash memory.
It is recommended that this bit be set to "0" to prevent data from being incorrectly written
into flash memory, whenever there is no data to be written or erased.
bit5
bit4
Bit for status checking for writing data into or erasing data from flash memory.
No data can be written into or erased from flash memory while this bit is "0". However, a
read command, reset command, and suspend commands such as the sector erase suspend
command can be accepted while this bit is "0".
RDY:
ReaDY bit
bit3
to
Reading / Writing for these bits have no effect.
Unused bits
bit0
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are
made using one or the other of these bits.
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
360
CHAPTER 17 FLASH MEMORY
17.3
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, and Chip Erase.
■ Command Sequence Table
Table 17.3-1 lists the commands used for flash memory write/erase.
Table 17.3-1 Command Sequence Table
Command
sequence
Bus
write
1st bus write
cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus read/
write cycle
5th bus write
cycle
6th bus write
cycle
access
Address Data Address Data Address Data Address Data Address Data Address Data
1
4
XXXX
FAAA
F0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Read/Reset
(*)
AA
F554
55
FAAA
F0
RA
RD
Write
program
4
6
FAAA
FAAA
AA
AA
F554
F554
55
55
FAAA
FAAA
A0
80
PA
PD
-
-
-
-
Chip Erase
FAAA
AA
F554
55
FAAA
10
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
Notes:
•
The addresses shown in the table are those on the CPU memory map. All addresses and data are represented in
hexadecimal notation. The letter X indicates an appropriate value.
RA: Read address
PA: Write address.
RD: Read data
PD: Write data.
•
The flash memory can only accept the command sequences mentioned on the above table (Read/Reset, Write
program, Chip Erase), other command sequences are strictly prohibited to be sent to the flash memory or else the
flash memory may become malfunction.
361
CHAPTER 17 FLASH MEMORY
17.4
Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequence
flags.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, and DQ2. The
functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded
flag (DQ5), and toggle bit2 flag (DQ2). The hardware sequence flags can therefore be used to confirm that
writing or chip sector erase has been completed or that erase code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 17.3-1 in Section "17.3 Starting the Flash
Memory Automatic Algorithm "). Table 17.4-1 lists the bit assignments of the hardware sequence flags.
Table 17.4-1 Bit Assignments of Hardware Sequence Flags
bit7
bit6
bit5
bit4
-
bit3
-
bit2
bit1
-
bit0
-
Hardware sequence flag
DQ7
DQ6
DQ5
DQ2
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control status
register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated,
the state returns to the read/reset state. When creating a program, use one of the flags to confirm that
automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read.
In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector
erase code write is valid. The following sections describe each hardware sequence flag separately. Table
17.4-2 lists the functions of the hardware sequence flags.
Table 17.4-2 Hardware Sequence Flag Functions
State
DQ7
DQ6
DQ5
DQ2
Executing
Automatic writing operation
Automatic erasing operation
Automatic writing operation
Automatic erasing operation
DQ7
0
Toggle
Toggle
Toggle
Toggle
0
0
1
1
1
Toggle
1
Exceeding
the time limit
DQ7
0
Toggle
362
CHAPTER 17 FLASH MEMORY
17.4.1
Data Polling Flag (DQ7)
The data polling flag uses the data polling function to post that the automatic algorithm
is being executed or has terminated
■ Write
Read-access during execution of the automatic write algorithm causes the flash memory to output the
opposite data of bit7 last written, regardless of the value at the address specified by the address signal.
Read-access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read
value of the address specified by the address signal.
■ Automatic Erasing
Read-access during execution of the automatic erasing algorithm causes the flash memory to output "0",
regardless of the value at the address specified by the address signal. After the automatic erasing algorithm
is executed, "1" is output.
Note:
When the automatic algorithm comes to the end of its operation, bit7 (data polling) changes its state
asynchronously during a read operation. This means that flash memory sends data about the operation
state to bit7 and will then send out fixed data. When flash memory ends the automatic algorithm or even
if bit7 is outputting fixed data, the values of the other bits are still undetermined. Fixed data in the other
bits can be read by successively executing read operations.
363
CHAPTER 17 FLASH MEMORY
17.4.2
Toggle Bit Flag (DQ6)
Like the data polling flag, the toggle bit flag uses the toggle bit function to post that the
automatic algorithm is being executed or has terminated.
■ Automatic Write/Erase
Making successive read accesses while the automatic writing/erasing algorithm is being performed toggles
flash memory and makes it output 1 and then 0, in turn, regardless of the specified address. Making
successive read accesses when the automatic writing/erasing algorithm ends makes flash memory to stop
bit6 toggle and outputs the value of bit6 (DATA:6) corresponding to the value read from the specified
address. The toggle bit becomes effective after the last write cycle in each command sequence.
364
CHAPTER 17 FLASH MEMORY
17.4.3
Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag is used to post that execution of the automatic algorithm
has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Automatic Write/Erase
Bit5 indicates that execution of the automatic algorithm exceeded the time (internal pulse count) specified
in flash memory. For an excess, bit5 outputs 1. Thus, if this bit outputs 1 while the automatic algorithm is
operating, data writing or data erasing failed.
Bit5 indicates a failure when an attempt is made to write data into a non-blank area without erasing any
data. In the case of such a failure, fixed data cannot be read from bit7 (data polling) and bit6 (toggle bit)
remains unchanged (toggled). If the time limit is exceeded while there is a failure, "1" is set in bit5. In this
case, note that the setting of bit5 to "1" does not indicate a flash memory failure but the incorrect use of
flash memory. If bit5 is set to "1" as described above, execute a reset command.
365
CHAPTER 17 FLASH MEMORY
17.4.4
Toggle Bit-2 Flag (DQ2)
The toggle bit-2 flag (DQ2) is used to detect that flash memory is performing an
automatic erase operation, together with the toggle bit.
■ Automatic Write/Erase
Making successive read accesses while the automatic erasing algorithm is being performed toggles flash
memory and makes it output 1 and then 0, in turn, regardless of the specified address. Making successive
read accesses while the automatic writing algorithm is being performed toggles flash memory and makes it
output 1 regardless of the specified address.
Making successive read accesses when the automatic writing/erasing algorithm ends makes flash memory
to stop bit2 toggle and outputs the value of bit2 (DATA:6) corresponding to the value read from the
specified address. The toggle bit becomes effective after the last write cycle in each command sequence.
366
CHAPTER 17 FLASH MEMORY
17.5
Detailed Explanation of Writing to Erasing Flash Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, when a command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see Table 17.3-1 in
Section "17.3 Starting the Flash Memory Automatic Algorithm "for a write cycle to the bus to perform
Read/Reset, Write, Chip Erase operations. Each bus write cycle must be performed continuously. In
addition, whether the automatic algorithm has terminated can be determined using the data polling or other
function. At normal termination, the flash memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
367
CHAPTER 17 FLASH MEMORY
17.5.1
Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in the command
continuously to the target sector in the flash memory.
The Read/Reset command has two types of command sequences that execute the first and third bus
operations. However, there are no essential differences between these command sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and when a
command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other
commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the
CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset
command is mainly used to initialize the automatic algorithm in such cases as when a command does not
terminate normally.
368
CHAPTER 17 FLASH MEMORY
17.5.2
Writing Data
This section describes the procedure for issuing the Write command to write data to the
■ Writing Data
The data write automatic algorithm of the flash memory can be started by sending the Write command in
Algorithm ") continuously to the flash memory. When data write to the target address is completed in the
fourth cycle, the automatic algorithm and automatic write are started.
■ Specifying Addresses
Writing can be done in any order of addresses. However, the Write command writes only data of one byte
for each execution.
■ Notes on Writing Data
Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or
toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If
the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be
an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in
the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started
during writing, the data of the written addresses will be unpredictable.
■ Writing to the Flash Memory
Figure 17.5-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags
(see Section "17.4 Confirming the Automatic Algorithm Execution State ") can be used to determine the
state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm
that writing has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes.
For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit (DQ7) must be
rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit
exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked.
369
CHAPTER 17 FLASH MEMORY
Figure 17.5-1 Example of the Flash Memory Write Procedure
Start writing*
* Make sure +10V DC voltage
is applied at the RST pin before
start writing
FMCS: WE (bit5)
Enable flash memory write
Write command sequence
(1) FAAA <-- AA
(2) F554 <-- 55
(3) FAAA <-- A0
(4) Write address <-- Write data
Read internal address
Next address
Data
Data polling (DQ7)
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
NO
Final address
Write error
YES
FMCS: WE (bit5)
Write-disable flash memory.
Confirm with the hardware
Complete writing
sequence flags.
370
CHAPTER 17 FLASH MEMORY
17.5.3
Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing All Data (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the command
continuously to the target sector in the flash memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed,
the chip erase operation is started. For chip erase, the user need not write to the flash memory before
erasing. During execution of the automatic erase algorithm, the flash memory writes "0" for verification
before all of the cells are erased automatically.
371
CHAPTER 17 FLASH MEMORY
17.6
Flash Security Feature
Flash security feature provides possibilities to protect the content of the flash memory
from being read from external.
■ Abstract
By writing the protection code of "01 " to the predefined flash security address of the flash memory,
H
access to the flash memory is restricted. Once the flash memory is protected, unlock the security function
can only be done by performing the chip erase operation. Otherwise, read/write access of the flash memory
from the external pins is not possible. This function is suitable for applications requiring security of self-
containing data stored in the flash memory.
Table 17.6-1 Flash Security Address
Product
Flash Memory Size
Flash Security Address
FFFC
MB89F202/F202RA
16 Kbyte
H
■ How to enable the Flash Security Feature
After writing the code "01 " to the flash security address, the subsequent external reset or power on
H
enables the flash security feature.
■ How to disable the Flash Security Feature
Perform the chip erase operation.
■ Behavior under the Flash Security Feature
Read operation: invalid data read
Write operation: ignored
■ Others
•
•
For the configuration of the standard parallel programmer, please follow the specification of parallel
programmer.
In order to prevent the device form enabling the flash security feature accidentally, writing the
protection code at the last of flash memory programming is recommended.
Note:
The security byte is allocated inside the flash memory. After writing the code "01 " to the flash security
H
address, the subsequent external reset or power on enables the flash security feature. Therefore, if the
flash security feature is not required, do not write "01 " to the security byte address.
H
Once the flash security feature is enabled, all the flash memory failure analysis cannot be performed.
372
CHAPTER 17 FLASH MEMORY
17.7
Notes on using Flash Memory
This section provides notes on using the MB89F202, especially for flash memory.
■ Input of a Hardware Reset (RST)
To input a hardware reset when reading is in progress, i.e., when the automatic algorithm has not been
started, secure a minimum low-level width of 1650 ns.
To input a hardware reset while a write or erase is in progress, i.e., while the automatic algorithm is being
started, secure a minimum low-level width of 1650 ns. In this case, 20 µs are required until the data
becomes readable after the operation being performed terminates and the flash memory is fully initialized.
Performing a hardware reset during a write operation makes the data being written undetermined. Also note
that performing a hardware reset or shut-down during an erase operation may make the sector from which
data is being erased unusable.
■ Software Reset, Watchdog Timer Reset
When write/erase of flash memory is set up for normal mode and CPU memory access mode is internal
ROM mode, and if a reset cause occurs while the automatic algorithm of flash memory is being activated,
the CPU may run out of control.
The cause of a reset does not initialize the flash memory and keeps the automatic algorithm operating.
Thus, when the CPU starts a sequence after the reset is cancelled, the flash memory may not have been in a
read state. Prevent a cause of a reset from occurring while the flash memory is writing or erasing.
■ Program Access to Flash Memory
While the automatic algorithm is being activated, any read access to the flash memory is disabled. When
CPU memory access mode is set to internal ROM mode, move program areas into another area such as
RAM, and then start a write or erase.
In this case, when the flash containing interrupt vectors are erased, the writing or erasing of interrupt
processing cannot be executed.
For the same reason, other interrupt processing shall be disabled while the automatic algorithm is being
activated.
■ Flash Content Protection
Flash content can be read using parallel / serial programmer if the flash content protection mechanism is
not activated.
One predefined area of the flash (FFFC ) is assigned to be used for preventing the read access of flash
H
content. If the protection code "01 " is written in this address (FFFC ), the flash content cannot be read by
H
H
any parallel / serial programmer.
Note : The program written into the flash cannot be verified once the flash protection code is written ("01 "
H
in FFFC ). It is advised to write the flash protection code at last.
H
373
CHAPTER 17 FLASH MEMORY
374
APPENDIX A I/O Map
APPENDIX A I/O Map
For the registers of peripheral functions incorporated in the MB89202/F202RA series,
the addresses shown in Table A-1 are assigned.
■ I/O Map
Table A-1 I/O Map (1 / 4)
Register
abbreviation
Address
Register name
Port 0 data register
Port 0 data direction register
Read/write
Initial value
0000
PDR0
R/W
W
XXXXXXXX
00000000
H
0001
DDR0
H
0002
H
to
Vacancy
0006
H
H
H
H
0007
0008
0009
SYCC
STBC
WDTC
TBTC
System clock control register
Standby control register
R/W
R/W
R/W
R/W
1--11100
00010---
Watchdog control register
Time-base timer control register
0---XXXX
00---000
000A
000B
000C
000D
000E
H
H
H
H
Vacancy
PDR3
DDR3
RSFR
Port 3 data register
R/W
W
XXXXXXXX
00000000
XXXX----
----XXXX
----0000
Port 3 data direction register
Reset flag register
R
H
H
H
H
H
H
H
H
H
H
000F
0010
0011
0012
0013
0014
0015
0016
0017
PDR4
Port 4 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DDR4
OUT4
PDR5
Port 4 data direction register
Port 4 output format register
Port 5 data register
----0000
-------X
DDR5
RCR21
RCR22
RCR23
RCR24
Port 5 data direction register
12-bit PPG control register 1
12-bit PPG control register 2
12-bit PPG control register 3
12-bit PPG control register 4
-------0
00000000
--000000
0-000000
--000000
376
Table A-1 I/O Map (2 / 4)
Register
Address
Register name
Read/write
Initial value
abbreviation
0018
0019
BZCR
TCCR
TCR1
TCR0
TDR1
TDR0
TCPH
TCPL
TCR2
Buzzer register
R/W
R/W
R/W
R/W
R/W
R/W
R
-----000
00000000
H
H
Capture control register
Timer 1 control register
Timer 0 control register
Timer 1 data register
001A
001B
001C
001D
001E
000-0000
H
H
H
H
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
------00
Timer 0 data register
Capture data register H
Capture data register L
Timer output control register
H
H
H
H
H
H
H
H
H
H
H
H
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
R
R/W
Vacancy
CNTR
COMR
EIC1
PWM control register
R/W
W
0-000000
XXXXXXXX
00000000
PWM compare register
External interrupt 1 control register 1
External interrupt 1 control register 2
R/W
R/W
EIC2
----0000
Vacancy
SMC
SRC
Serial mode control register
Serial rate control register
R/W
R/W
00000-00
--011000
002A
SSD
SIDR
SODR
UPC
Serial status and data register
Serial input data register
R/W
R
00100-1X
XXXXXXXX
XXXXXXXX
----0010
H
002B
002C
H
Serial output data register
W
Clock divided cycle selection register
R/W
H
H
002D
to
Vacancy
002F
0030
0031
0032
0033
H
H
H
H
H
ADC1
ADC2
ADDH
ADDL
A/D control register 1
A/D control register 2
A/D data register H
A/D data register L
R/W
R/W
R
-0000000
-0000001
------XX
R
XXXXXXXX
377
APPENDIX A I/O Map
Table A-1 I/O Map (3 / 4)
Register
Address
Register name
A/D enable register
Read/write
Initial value
abbreviation
0034
0035
0036
0037
0038
0039
ADEN
R/W
00000000
H
H
H
H
H
H
Vacancy
EIE2
EIF2
External interrupt 2 control register 1
External interrupt 2 control register 2
Vacancy
R/W
R/W
00000000
-------0
SMR
SDR
Serial mode register
R/W
R/W
R/W
00000000
XXXXXXXX
-------0
003A
003B
Serial data register
H
H
H
SSEL
Serial function switching register
003C
to
Vacancy
003F
0040
0041
0042
0043
0044
0045
0046
0047
0048
H
H
H
H
H
H
H
H
H
H
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WREN
Higher address set register 0
Lower address set register 0
Data setting register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
------00
Higher address set register 1
Lower address set register 1
Data setting register 1
Address comparison EN register
Wild register data test register
WROR
------00
to
Vacancy
005F
H
H
H
H
H
H
H
0060
0061
0062
0063
0064
0065
PDR6
DDR6
PUL6
PDR7
DDR7
PUL7
Port 6 data register
R/W
R/W
R/W
R/W
R/W
R/W
------XX
------00
Port 6 data direction register*
Port 6 pull-up set register
Port 7 data register
------00
-----XXX
-----000
-----000
Port 7 data direction register
Port 7 pull-up set register
378
Table A-1 I/O Map (4 / 4)
Register
Address
Register name
Read/write
Initial value
abbreviation
0066
H
to
Vacancy
006F
H
H
H
H
H
0070
0071
0072
0073
PUL0
PUL3
PUL5
Port 0 pull-up set register
R/W
R/W
R/W
00000000
00000000
-------0
Port 3 pull-up set register
Port 5 pull-up set register
to
Prohibited area
0078
H
H
0079
FMCS
Flash memory control status register
Prohibited area
R/W, R
000X----
007A
007B
007C
007D
007E
H
H
H
H
ILR1
ILR2
ILR3
ILR4
ITR
Interrupt level set register 1
Interrupt level set register 2
Interrupt level set register 3
Interrupt level set register 4
Interrupt test register
W
W
11111111
11111111
11111111
11111111
------00
W
W
H
H
007F
Inhibited
● Explanation on read/write
R/W: Readable and Writable
R: Read only
W: Write only
● Explanation on initial value
0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
*: No used in MB89F202/F202RA.
Note:
Do not use the prohibited areas.
379
APPENDIX B Overview of the Instructions
APPENDIX B Overview of the Instructions
2
This section describes the instructions used for the F MC-8L.
2
■ Overview of the Instructions of the F MC-8L
2
The F MC-8L has 140 kinds of 1-byte machine instructions (actually, the map is 256 bytes). An instruction
and succeeding operands make an instruction code.
Figure B-1 shows the correspondence between the instruction codes and instruction map.
Figure B-1 Correspondence between Instruction Codes and Instruction Map
0 to 2 bytes are provided depending
on the instruction.
1 byte
Machine
Operand
Operand
Instruction code
instruction
Higher 4 bits
[Instruction map]
•
•
The instructions are classified into four groups including transfer instructions and branch instructions.
Various methods for addressing are supported. Depending on the selection of an instruction and
specification of operands, 10 kinds of addressing can be selected.
•
•
Bit manipulation instructions are supported, so read-modify-write operation is possible.
Instructions directing special operations are supported.
380
■ Explanation on the Codes Representing Instructions
Table B-1 describes the codes used to explain the instruction codes in Appendix B.
Table B-1 Explanation on Codes on Instructions’ List
Code
Meaning
dir
off
Direct address (8 bits)
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir:b
rel
@
Register indirect (Example: @A, @IX, and @EP)
Accumulator (8 bits or 16 bits, determined on basis of instruction to be used)
Higher 8 bits of the accumulator (8 bits)
A
AH
AL
Lower 8 bits of the accumulator (8 bits)
Temporary accumulator
(8 bits or 16 bits, determined on basis of instruction to be used)
T
TH
TL
IX
Higher 8 bits of the temporary accumulator (8 bits)
Lower 8 bits of the temporary accumulator (8 bits)
Index register (16 bits)
EP
PC
SP
Extra pointer (16 bits)
Program counter (16 bits)
Stack pointer (16 bits)
PS
Program status (16 bits)
dr
Either accumulator or index register (16 bits)
Condition code register (8 bits)
Register bank pointer (5 bits)
CCR
RP
Ri
General-purpose register (8 bits, i = 0 to 7)
Indicates that X itself is the immediate data.
(8 bits or 16 bits, determined on basis of instruction to be used)
X
Indicates that the contents of X is the accessing subject.
(8 bits or 16 bits, determined on basis of instruction to be used)
(X)
Indicates that the address specified in X is the accessing subject.
(8 bits or 16 bits, determined on basis of instruction to be used)
((X))
381
APPENDIX B Overview of the Instructions
■ Explanation on the Items of Instructions’ List
Table B-2 Explanation on Items of Instructions’ List
Item
Description
MNEMONIC Represents the instruction coded in the assembler.
~
#
Indicates the number of cycles of the instruction (number of instruction cycles).
Indicates the number of bytes of the instruction.
Indicates the operation of the instruction.
Operation
Indicates how the contents of TL, TH, and AH change (automatic transfer from A to
T) when the instruction is executed.
The codes in this column indicate the following:
•
•
•
- indicates no change.
TL,TH,AH
dH indicates the higher 8 bits of the data coded for the operation.
AL and AH indicate the contents of AL and AH just before the execution of the
instruction.
•
00 indicates that it becomes 00.
Indicates whether the instruction changes the corresponding flags.
If ( is shown in this column, the instruction changes the corresponding flags.
N,Z,V,C
Indicates the instruction code. If the appropriate instruction occupies multiple codes,
they are listed under the following rule:
Example:
OP CODE
48 to 4F means the serial numbers from 48 to 4F.
382
B.1 Addressing
2
For the F MC-8L, the following 10 kinds of addressing modes are supported:
• Direct addressing
• Extended addressing
• Bit direct addressing
• Index addressing
• Pointer addressing
• General-purpose register addressing
• Immediate addressing
• Vector addressing
• Relative addressing
• Inherent addressing
■ Explanation on Addressing
● Direct addressing
The addressing, which is indicated by dir in the instructions list, is used for accessing the area from 0000
H
to 00FF . In this addressing, the higher one byte of the address is 00 . Specify the lower one byte with the
H
H
operand.
Figure B.1-1 shows an example.
Figure B.1-1 Example of Direct Addressing
MOV12H, A
H
A
45H
001 2H 45
● Extended Addressing
The addressing, which is indicated by ext in the instructions list, is used for accessing the entire area of 64
KB. In this addressing, specify the higher one byte of the address with the first operand and the lower one
byte with the second operand.
Figure B.1-2 shows an example.
Figure B.1-2 Example of Extended Addressing
MOVW A, 1 2 3 4H
1 2 3 4 H
1 2 3 5 H
5 6
7 8
H
H
A 5 6 7 8H
383
APPENDIX B Overview of the Instructions
● Bit Direct Addressing
The addressing, which is indicated by dir:b in the instructions list, is used for accessing the area from
0000 to 00FF on a per bit basis. In this addressing, the higher one byte of the address is 00 . Specify the
H
H
H
lower one byte with the operand; and the bit position in the specified address with the lower three bits of
the operation code.
Figure B.1-3 shows an example.
Figure B.1-3 Example of Bit Direct Addressing
SETB 34H : 2
7 6 5 4 3 2 1 0
0 0 3 4H
X X X X X 1 X XB
● Index addressing
The addressing, which is indicated by @IX(off in the instructions list, is used for accessing the entire area
of 64 KB. In this addressing, the contents of the first operand are signed and added to IX (index register).
Then the results are used as the address.
Figure B.1-4 shows an example.
Figure B.1-4 Example of Index Addressing
MOVW A, @IX+5 AH
1 2H
3 4H
2 7 A 5H
2 7 F FH
2 8 0 0H
IX
1 2 3 4H
A
● Pointer Addressing
The addressing, which is indicated by @EP in the instructions list, is used for accessing the entire area of
64 KB. In this addressing, the contents of EP (extra pointer) are used as the address.
Figure B.1-5 Example of Pointer Addressing
MOVW A,
@EP
H
H
H
EP 2 7 A 5
2 7 A5
2 7 A6
1 2 H
3 4 H
H
A
1 2 3 4
384
● General-purpose Register Addressing
The addressing, which is indicated by Ri in the instructions list, is used for accessing the register bank of
the general-purpose register area. In this addressing, the higher one byte of the address is fixed to 01. The
lower one byte is generated from the contents of RP (register bank pointer) and the lower three bits of the
operation code. The address is then accessed.
Figure B.1-6 shows an example.
Figure B.1-6 Example of General-purpose Register Addressing
A
MOV , R 6
H
A B
B
H
A
RP 0 1 0 1 0
0 1 5 6 H A B
● Immediate Addressing
The addressing, which is indicated by #d8 in the instructions list, is used when immediate data is required.
In this addressing, the operand directly becomes the immediate data. The specification of byte/word is
determined using the operation code.
Figure B.1-7 shows an example.
Figure B.1-7 Example of Immediate Addressing
H
MOV A, #56
56H
A
● Vector Addressing
The addressing, which is indicated by vct in the instructions list, is used for branching to a subroutine
registered in the table. In this addressing, the operation code includes the vct information, with the
Table B.1-1 Vector Table Address Corresponding to vct
#vct
Vector table address (Jump destination, higher address:lower address)
0
1
2
3
4
5
6
7
FFCO : FFC1
H
H
H
H
H
H
FFC2 : FFC3
H
FFC4 : FFC5
H
FFC6 : FFC7
H
FFC8 : FFC9
H
FFCA : FFCB
H
H
H
H
FFCC : FFCD
H
FFCE : FFCF
H
385
APPENDIX B Overview of the Instructions
Figure B.1-8 shows an example.
Figure B.1-8 Example of Vector Addressing
CALL #5
V
(Conversion)
H
H
F F C
A
H
H
F E
H
PC F E D C
F F C B D C
● Relative Addressing
The addressing, which is indicated by rel in the instructions list, is used for branching to the area of 128
bytes before or after the PC (program counter). In this addressing, the contents of the operand with a sign
are added to the PC. The results are then stored in the PC.
Figure B.1-9 shows an example.
Figure B.1-9 Example of Relative Addressing
NE FEH
B
9ABCH
+ FFFEH
New PC
9 A B AH
Old PC
9 A B CH
In this example, the control jumps to the address holding the operation code of BNE, causing an endless
loop.
● Inherent addressing
This addressing, which has no operand in the instructions list, is used for performing an operation
determined on the basis of the operation code. In this addressing, the operations differ depending on the
instructions.
Figure B.1-10 shows an example.
Figure B.1-10 Example of Inherent Addressing
NOP
New PC
Old PC
H
9 A B DH
9 A B C
386
B.2 Special Instructions
This section describes the special instructions other than addressing.
■ Special Instructions
● JMP @A
By this instruction, the control branches to PC (program counter) using the contents of A (accumulator) as
the address. N items of jump destinations have been listed on the table, one of which is selected and
transferred to A. Executing this instruction can achieve N kinds of branch processing.
Figure B.2-1 JMP @A
(After execution)
(Before execution)
1234H
A
1234H
A
Old PC
New PC
1234H
XXXXH
● MOVW A, PC
This instruction performs the opposite operation of JMP @A. In other words, the contents of the PC are
stored in A. When this instruction has been executed in the main routine and a specific subroutine is to be
called, it is possible to verify that the contents of A are the predetermined value in the subroutine. It is also
possible to verify that the branch was not from an unexpected part, so it is useful in judging that a runaway
has occurred.
Figure B.2-2 shows an overview.
Figure B.2-2 MOVW A, PC
(After execution)
(Before execution)
1234H
A
XXXXH
A
Old PC
1233H
1234H
New PC
When this instruction is executed, the contents of A are not the address holding the operation code of this
instruction but the same value as the address holding the next instruction. In Figure B.2-2 , therefore, the
value stored in A, 1234 , is the same as the address holding the operation code next to the MOVW A, PC.
H
387
APPENDIX B Overview of the Instructions
● MULU A
This instruction multiplies AL (the lower eight bits of accumulator) by TL (the lower eight bits of the
temporary accumulator) without a sign and stores the results in 16 bits length to A. The contents of T
(temporary accumulator) remain as they are. For the operation, the contents of AH (the higher eight bits of
accumulator) and TH (the higher eight bits of temporary accumulator) before the execution are not used.
Take care when using a branch based on the result of multiplication because the flags were not changed.
Figure B.2-3 shows an overview.
Figure B.2-3 MULU A
(After execution)
(Before execution)
1860H
A
5678H
A
1234H
T
1234H
T
● DIVU A
This instruction divides T of 16 bits by AL of 8 bits without a sign, stores the results in 8 bits to AL, and
stores the remainder of 8 bits to TL. Both AH and TH become 0. For the operation, the contents of AH
before execution are not used. If the results exceed 8 bits, they are not guaranteed. Also, the fact that the
results exceeded 8 bits is not indicated. So when using data units that may cause this type of situation,
judge them in advance.
Take care when using a branch based on the result of division, because the flags were not changed.
Figure B.2-4 shows an overview.
Figure B.2-4 DIVU A
(After execution)
(Before execution)
0034H
A
5678H
A
0002H
T
1862H
T
388
● XCHW A, PC
This instruction replaces the contents of A and the contents of PC, resulting in a branch to the address
indicated by the contents of A before execution. The contents of A after execution become the value of the
address next to the address holding the operation code, XCHW A, PC. This instruction is useful especially
when a table is specified in the main routine and a subroutine uses it.
Figure B.2-5 shows an overview.
Figure B.2-5 XCHW A, PC
(Before execution)
(After execution)
5678H
A
1235H
5678H
A
1234H
PC
PC
After execution of this instruction, the contents of A do not become the address holding the operation code
of this instruction. Instead, they are the same as the address holding the next instruction. In Figure B.2-5 ,
therefore, the value stored in A is 1235 , agreeing with the address holding the operation code next to
H
XCHW A, PC. Note that it is not 1234 but 1235 .
H
H
Figure B.2-6 shows an example of assembler coding.
Figure B.2-6 Usage Example of XCHW A, PC
(Main routine)
(Subroutine)
.
.
.
MOVW A, #PUTSUB
XCHW A, PC
PUTSUB
PTS1
XCHW A, EP
PUSHW A
MOV A, @EP
INCW EP
DB
'PUT OUT DATA', EOL
MOVW A, 1234H
Outputs a
table data
unit.
.
.
.
MOV IO, A
CMP A, #EOL
BNE PTS1
POPW A
XCHW A, EP
JMP @A
389
APPENDIX B Overview of the Instructions
● CALLV #vct
This addressing is used for branching to one of the subroutine addresses registered in the table. After the
return address (the contents of PC) is saved to the address indexed by SP (stack pointer), the control is
branched to the address listed in the vector table via the vector addressing. This instruction is one byte, so
using it for the frequently used subroutines enables the entire program size to be smaller.
Figure B.2-7 shows the overview.
Figure B.2-7 Executing Example of CALLV #3
(Before execution)
(After execution)
5678H
PC
FEDCH
1232H
PC
SP
(- 2)
1234H
SP
1232H
1233H
1232H
1233H
X
XH
56 H
H
H
XX
79
FFC6H
FFC7H
FFC6H
FFC7H
H
H
H
FE
FE
D C
DCH
When this instruction is executed, the contents of the PC to be saved in the stack area are not the address
holding the operation code of this instruction. Instead, they comprise the address holding the next
instruction. In Figure B.2-7 , therefore, the value saved in the stack (1232 and 1233 ) is the same as the
H
H
address holding the operation code next to CALLV #vct (return address), i.e. 5679 .
H
390
B.3 Bit Manipulation Instructions (SETB and CLRB)
Some registers of peripheral functions have bits that perform a read operation different
from ordinary read for a bit manipulation instruction.
■ Read-modify-write Operation
The bit manipulation instructions can set "1" (SETB) to the specified bit in a register or RAM or clear it to
"0" (CLRB). Because the CPU handles the data in 8 bits, however, it actually reads the 8-bit data, modifies
the specified bit, and then writes it back to the original address. This series of operations is called read-
modify-write operation.
Table B.3-1 shows the bus operation at bit manipulation instructions.
Table B.3-1 Bus Operation at Bit Manipulation Instructions
CODE
MNEMONIC
~
Cycle
Address bus
N+1
Data bus
Dir
RD
WR
RMW
A0 to A7
CLRB dir:b
4
1
2
3
4
0
0
1
0
1
1
0
1
0
1
0
0
dir address
dir address
N+2
Data
A8 to AF
SETB dir:b
Data
Next operation
■ Read Destination at Execution of a Bit Manipulation Instruction
For some I/O ports and interrupt request flag bits, the read destination for read-modify-write is different
from that for ordinary read.
● I/O port (at bit manipulation)
For some I/O ports, the value of the I/O pin is read at ordinary read; meanwhile, the value of output latch is
read at bit manipulation. This is to prevent the other bits of the output latch from being accidentally
changed regardless of the I/O direction and pin state.
● Interrupt request flag bit (at bit manipulation)
The interrupt request flag bits work as flag bits for confirming an interrupt request at ordinary read;
meanwhile, "1" is always read at bit manipulation. This is to prevent the interrupt request flag bits from
being written as "0", and accidentally clearing the flags at bit manipulation for another bit.
391
APPENDIX B Overview of the Instructions
2
B.4 F MC-8L Instructions List
2
■ Transfer Instructions
Table B.4-1 List of Transfer Instructions (1 / 2)
No.
MNEMONIC
MOV dir, A
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
45
1
2
3
4
5
3
4
4
3
3
2
2
3
1
1
(dir) ←(A)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MOV @IX+off, A
MOV ext, A
((IX) +off) ←(A)
(ext) ←(A)
46
61
MOV @EP, A
MOV Ri, A
( (EP) ) ←(A)
(Ri) ←(A)
47
48 to 4F
6
7
MOV A, #d8
MOV A, dir
2
3
4
4
3
2
2
2
3
1
A) ←d8
AL
AL
AL
AL
AL
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
04
05
06
60
92
(A) ←(dir)
8
MOV A, @IX +off
MOV A, ext
(A) ←( (IX) +off)
(A) ←(ext)
(A) ←( (A) )
9
10
MOV A, @A
11
12
13
14
15
MOV A, @EP
MOV A, Ri
3
3
4
5
4
1
1
3
3
2
(A) ←( (EP) )
(A) ←(Ri)
AL
-
-
-
-
-
-
-
-
-
-
+
+
-
+
+
-
-
-
-
-
-
-
-
-
-
-
07
08 to 0F
85
AL
MOV dir, #d8
MOV @IX+off, #d8
MOV @EP, #d8
(dir) ←d8
-
-
-
( (IX) +off) ←d8
( (EP) ) ←d8
-
-
86
-
-
87
16
17
MOV Ri, #d8
MOVW dir, A
4
4
2
2
(Ri) ←d8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88 to 8F
D5
(dir) ←(AH),
(dir+1) ←(AL)
18
19
20
MOVW @IX+off , A
MOVW ext, A
5
5
4
2
3
1
( (IX)+off ) ←(AH),
((IX)+off+1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D6
D4
D7
(ext) ←(AH),
(ext+1) ←(AL)
MOVW @EP, A
( (EP) ) ←(AH),
( (EP)+1) ←(AL)
21
22
MOVW EP, A
2
3
1
3
(EP) ←(A)
-
-
-
-
-
-
-
-
-
E3
E4
MOVW A, #d16
(A) ←d16
AL
AH
dH
+
+
392
Table B.4-1 List of Transfer Instructions (2 / 2)
No.
MNEMONIC
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
C5
23
MOVW A, dir
4
2
(AH) ←(dir),
AL
AH
dH
+
+
-
-
(AL) ←(dir+1)
24
25
MOVW A, @IX+off
MOVW A, ext
5
5
2
3
(AH) ←( (IX) +off),
(AL) ←( (IX)
AL
AL
AH
AH
dH
dH
+
+
+
+
-
-
-
-
C6
C4
(AH) ←(ext),
(AL) ←(ext+1)
26
27
MOVW A, @A
MOVW A, @EP
4
4
1
1
(AH) ←( (A) ),
(AL) ←( (A)+1)
AL
AL
AH
AH
dH
dH
+
+
+
+
-
-
-
-
93
(AH) ←( (EP) ),
C7
(AL) ←( (EP)+1)
28
29
30
MOVW A, EP
MOVW EP, #d16
MOVW IX, A
2
3
2
1
3
1
(A) ←(EP)
(EP) ←d16
(IX) ←(A)
-
-
-
-
-
-
dH
-
-
-
-
-
-
-
-
-
-
-
-
F3
E7
E2
-
-
31
32
33
34
35
MOVW A, IX
MOVW SP, A
MOVW A, SP
MOV @A, T
MOVW @A, T
2
2
2
3
4
1
1
1
1
1
(A) ←(IX)
(SP) ←(A)
(A) ←(SP)
( (A) ) ←(T)
-
-
-
-
-
-
-
-
-
-
dH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F2
E1
F1
82
83
dH
-
( (A) ) ←(TH), )
-
( (A)+1) ←(TL)
36
37
38
39
40
MOVW IX, #d16
MOVW A, PS
MOVW PS, A
MOVW SP, #d16
SWAP
3
2
2
3
2
3
1
1
3
1
(IX) ←d16
(A) ←(PS)
(PS) ←(A)
(SP) ←d16
(AH) ←→(AL)
-
-
-
-
-
-
-
-
-
-
-
dH
-
-
-
-
-
-
-
-
-
E6
70
71
E5
10
+
-
+
-
+
-
+
-
-
AL
-
-
-
-
41
42
43
44
45
SETB dir:b
CLRB dir:b
XCH A, T
4
4
2
3
3
2
2
1
1
1
(dir):b ←1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A8 to AF
A0 to A7
42
(dir):b ←0
-
-
(AL) ←→(TL)
(A) ←→(T)
(A) ←→(EP)
AL
AL
-
-
XCHW A, T
XCHW A, EP
AH
-
dH
dH
43
F7
46
47
48
XCHW A, IX
XCHW A, SP
MOVW A, PC
3
3
2
1
1
1
(A) ←→(IX)
(A) ←→(SP)
(A) ←(PC)
-
-
-
-
-
-
dH
dH
dH
-
-
-
-
-
-
-
-
-
-
-
-
F6
F5
F0
393
APPENDIX B Overview of the Instructions
Note:
At byte transfer operation to A, the automatic transfer to T is represented by TL ←AL.
The operands in a multiple-operand instruction are stored in the order in which they are indicated in
MNEMONIC.
■ Operation Instructions
Table B.4-2 List of Operation Instructions (1 / 4)
No.
MNEMONIC
ADDC A, Ri
~
#
Operation
(A) ←(A)+(Ri)+C
TL
TH
AH
N
Z
V
C
OP CODE
1
2
3
4
5
3
2
3
4
3
1
2
2
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
28 to 2F
24
ADDC A, #d8
ADDC A, dir
(A) ←(A)+d8+C
(A) ←(A)+(dir)+C
25
ADDC A, @IX+off
ADDC A, @EP
(A) ←(A)+( (IX)+off)+C
(A) ←(A)+( (EP) )+C
26
27
6
7
ADDCW A
ADDC A
3
2
3
2
3
1
1
1
2
2
(A) ←(A)+(T)+C
(AL) ←(AL)+(TL)+C
(A) ←(A)-(Ri)-C
(A) ←(A)-d8-C
-
-
-
-
-
-
-
-
-
-
dH
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
23
22
-
-
-
-
8
SUBC A, Ri
SUBC A, #d8
SUBC A, dir
38 to 3F
34
9
10
(A) ←(A)-(dir)-C
35
11
12
13
14
15
SUBC A, @IX+off
SUBC A, @EP
SUBCW A
SUBC A
4
3
3
2
4
2
1
1
1
1
(A) ←(A)-( (IX)+off)-C
(A) ←(A)-( (EP) )-C
(A) ←(T)-(A)-C
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
36
37
dH
-
33
(AL) ←(TL)-(AL)-C
(Ri) ←(Ri)+1
32
INC Ri
-
C8 to CF
16
17
18
19
20
INCW EP
INCW IX
INCW A
DEC Ri
3
3
3
4
3
1
1
1
1
1
(EP) ←(EP)+1
(IX) ←(IX)+1
(A) ←(A)+1
(Ri) ←(Ri)-1
(EP) ←(EP)-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C3
C2
dH
-
+
+
-
+
+
-
-
C0
+
-
D8 to DF
D3
DECW EP
-
21
22
23
24
DECW IX
DECW A
MULU A
DIVU A
3
3
1
1
1
1
(IX) ←(IX)-1
-
-
-
-
-
-
+
+
-
-
+
+
-
-
-
-
-
D2
D0
01
(A) ←(A)-1
dH
dH
00
19
21
(A) ←(AL) x (TL)
(A) ←(T)/(AL), MOD →(T)
-
-
+
-
+
-
dL
00
11
394
Table B.4-2 List of Operation Instructions (2 / 4)
No.
MNEMONIC
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
25
ANDW A
3
1
-
-
dH
+
+
R
-
63
(A) (A)
(T)
26
27
ORW A
3
3
1
1
-
-
-
-
dH
dH
+
+
+
+
R
R
-
-
73
53
(A) (A)
(A) (A)
(T)
(T)
XORW A
28
29
CMP A
2
3
1
1
(TL) - (AL)
(T)- (A)
-
-
-
-
-
-
+
+
+
+
+
+
+
+
12
13
CMPW A
30
RORC A
ROLC A
2
1
-
-
-
+
+
-
+
03
C
A
31
2
1
-
-
-
+
+
-
+
02
C
A
32
33
34
35
CMP A, #d8
2
3
3
4
2
2
1
2
(A) - d8
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
14
15
17
16
CMP A, dir
(A) - (dir)
CMP A, @EP
CMP A, @IX+off
(A) - ( (EP) )
(A)-( (IX)+off)
36
37
38
CMP A, Ri
DAA
3
2
2
1
1
1
(A) - (Ri)
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
18 to 1F
84
decimal adjust for addition
decimal adjust for subtraction
DAS
94
39
40
XOR A
2
2
1
2
-
-
-
-
-
-
+
+
+
+
R
R
-
-
52
54
(A) (AL) (TL)
XOR A, #d8
(A)
(AL) d8
41
42
XOR A, dir
3
3
2
1
-
-
-
-
-
-
+
+
+
+
R
R
-
-
55
57
(A)
(A)
(AL) (dir)
XOR A, @EP
(AL) ( (EP) )
395
APPENDIX B Overview of the Instructions
Table B.4-2 List of Operation Instructions (3 / 4)
No.
MNEMONIC
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
43
XOR A, @IX+off
4
2
-
-
-
+
+
R
-
56
(A)
(A)
(A)
(AL) ( (IX) +off)
44
45
XOR A, Ri
AND A
3
2
1
1
-
-
-
-
-
-
+
+
+
+
R
R
-
-
58 to 5F
62
(AL) (Ri)
(AL) (TL)
2
3
3
4
3
2
2
1
2
1
46
47
48
49
50
AND A, #d8
AND A, dir
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
R
R
R
R
R
-
-
-
-
-
64
65
(A)
(A)
(A)
(A)
(A)
(AL) d8
(AL) (dir)
AND A, @EP
AND A, @IX+off
AND A, Ri
67
(AL)
(AL)
(AL)
( (EP) )
( (IX)+off)
(Ri)
66
68 to 6F
51
52
53
54
55
OR A
2
2
3
3
4
1
2
2
1
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
R
R
R
R
R
-
-
-
-
-
72
74
75
77
76
(A)
(A)
(A)
(A)
(AL)
(AL)
(AL)
(AL)
(Ri)
OR A, #d8
OR A, dir
d8
(dir)
OR A, @EP
OR A, @IX+off
( (EP) )
( (IX)+off)
(Ri)
(A)
(AL)
56
57
OR A, Ri
3
5
1
3
-
-
-
-
-
-
+
+
+
+
R
+
-
78 to 7F
95
(A)
(AL)
(dir)-d8
CMP dir , #d8
+
396
Table B.4-2 List of Operation Instructions (4 / 4)
No.
MNEMONIC
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
97
58
59
60
CMP @EP, #d8
CMP @IX+off, #d8
CMP Ri, #d8
4
5
4
2
3
2
( (EP) )-d8
( (IX)+off)-d8
(Ri)-d8
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
96
98 to 9F
61
62
INCW SP
DECW SP
3
3
1
1
(SP) ←(SP)+1
(SP) ←(SP)-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C1
D1
■ Branch Instructions
Table B.4-3 List of Branch Instructions
No.
MNEMONIC
BZ/BEQ rel
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
1
2
3
4
5
3
3
3
3
3
2
2
2
2
2
if Z=1 then PC ←PC+rel
if Z=0 then PC ←PC+rel
if C=1 then PC ←PC+rel
if C=0 then PC ←PC+rel
if N=1 then PC ←PC+rel
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FD
FC
F9
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
F8
FB
6
7
BP rel
3
3
2
2
if N=0 then PC ←PC+rel
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FA
FF
BLT rel
if
N=1 then PC PC+rel
8
BGE rel
3
2
-
-
-
-
-
-
-
FE
if
N=0 then PC PC+rel
9
BBC dir:b, rel
BBS dir:b, rel
5
5
3
3
if(dir:b)=0 then PC ←PC+rel
-
-
-
-
-
-
-
-
+
+
-
-
-
-
B0 to B7
B8 to BF
10
if(dir:b)=1 then PC ←PC+rel
11
12
13
14
15
16
17
JMP @A
JMP ext
2
3
6
6
3
4
6
1
3
1
3
1
1
1
(PC) ←(A)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E0
(PC) ←ext
21
E8 to EF
31
CALLV #vct
CALL ext
XCHW A, PC
RET
vector call
-
subroutine call
-
(PC) ←(A), (A) ←(PC)+1
return from subroutine
return from interrupt
dH
-
F4
20
RETI
-
restore
30
397
APPENDIX B Overview of the Instructions
■ Other Instructions
Table B.4-4 List of Other Instructions
No.
MNEMONIC
PUSHW A
~
#
Operation
TL
TH
AH
N
Z
V
C
OP CODE
40
1
2
3
4
5
4
4
4
4
1
1
1
1
1
1
( (SP) ) ←(A), (SP) ←(SP)-2
(A) ←((SP)), (SP) ←(SP)+2
( (SP) ) ←(IX), (SP) ←(SP)-2
(IX) ←((SP)), (SP) ←(SP)+2
No operation
-
-
-
-
-
-
-
-
-
-
-
dH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
POPW A
PUSHW IX
POPW IX
NOP
50
41
51
00
-
-
6
7
8
9
CLRC
SETC
CLRI
SETI
1
1
1
1
1
1
1
1
(C) ←0
(C) ←1
(I) ←0
(I) ←1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
S
-
81
91
80
90
-
398
APPENDIX C Mask Options
APPENDIX C Mask Options
Table C-1 lists the mask options of the MB89202/F202RA series.
■ Mask Options
Table C-1 Mask Options
No.
Part number
MB89202
MB89F202/F202RA
MB89V201
Specifying procedure
Specify when ordering
masking
Specify by part number
Fixed to 218/FCH
Fixed to 218/FCH
Selection of initial value of main clock Selectable
oscillation settling time*
1
(with FCH = 12.5 MHz)
01 : 214/FCH (Approx.1.31 ms)
10 : 217/FCH (Approx.10.5 ms)
11 : 218/FCH (Approx.21.0 ms)
Reset pin output
With reset output
Without reset output
Selectable
Selectable
With reset output
With reset output
2
3
Power on reset selection
With power-on reset
With power-on reset
With power-on reset
Without power-on reset
F
: Main clock scillation frequency
CH
* : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set
400
APPENDIX D Programming EPROM with Evaluation Chip
This section describes how to program EPROM with evaluation chip.
■ Programming EPROM with Evaluation Chip
● EPROM for use
32 Kbyte EPROM (equivalent to MBM27C256A DIP-28)
Figure D-1 Memory Map of the Evaluation Chip
In normal operation
mode
(Corresponding address on
the ROM programmer)
0000H
I/O
0080H
RAM 512bytes
0280H
Unavailable
8000H
0000H
Program area
Program area
(PROM 32Kbytes)
(PROM 32Kbytes)
FFFFH
7FFFH
● Programming EPROM
1. Make the MBM27C256-equivalent setting for the EPROM programmer
2. Load the program data to the area from 0000 to 7FFF of the EPROM programmer.
H
H
3. Program the area from 0000 to 7FFF with the EPROM programmer.
H
H
401
APPENDIX E Pin State of the MB89202/F202RA Series
APPENDIX E Pin State of the MB89202/F202RA Series
Table E-1 describes the pin states in each operation mode of the MB89202/F202RA
series.
■ Pin States in Each Operation Mode
Table E-1 Pin States in Each Operation Mode
In normal operation
mode
In sleep
mode
In stop mode
(SPL = 0)
In stop mode
(SPL = 1)
Pin name
During a reset
Oscillation
input
Oscillation
input
X0
X1
Oscillation input
Oscillation output
Hi-Z
Hi-Z
Oscillation
output
Oscillation
output
"H" output
"H" output
P00/INT20/AN4
to
Port I/O or resource
I/O
*1,*2
Hold
Hold
Hold
Hold
Hi-Z
Hi-Z
Hi-Z
P07/INT27
P30/UCK/SCK
to
P37/BZ/PPG
Port I/O or resource
I/O
*1,*2
Hi-Z
P40/AN0
to
P43/AN3
Port I/O or resource
I/O
*2
Hold
Hold
Hold
Hold
Hi-Z
Hi-Z
Hi-Z
Port I/O or resource
I/O
*2
P50/PWM
Hi-Z
*2
P60, P61
Port I/O
Port I/O
Hold
Hold
Hold
Hold
Hi-Z
Hi-Z
Hi-Z
*2
P70 to P72
Hi-Z
*1:
*2:
For port input and peripheral input, the internal input level is fixed to prevent them from generating a leak via the
input open. However, if external interrupts are allowed for P00 to P07 and P34 to P36, only the external interrupts
are available as their inputs.
The pins, for which pull-up is selected by the option setting, enter the pull-up state.
Hi-Z: Indicates high impedance.
Hold: The pins, for which output is set, maintain the pin state (level) just before the mode transition.
SPL: Pin state spacification bit of the standby control register (STBC)
402
INDEX
Index
Numerics
Notes on Using the 8/16-bit Capture
Timer/Counter .................................... 198
Pins of 8/16-bit Capture Timer/Counter ............. 168
Register and Vector Table Related to 8/16-bit Capture
Timer/Counter of Interrupts ................. 184
Registers of 8/16-bit Capture Timer/Counter
12-bit PPG
12-bit PPG Control Register
8-bit PWM Timer
Block Diagram of an 8-bit PWM Timer ............. 139
Block Diagram of the Pin Related to the 8-bit PWM
Notes on Using 8-bit PWM Timer ..................... 155
Operations of the 8-bit PWM Timer Functions
Register and Vector Table Related to the Interrupts
of an 8-bit PWM Timer ....................... 147
Registers Related to the 8-bit PWM Timer ......... 142
12-bit PPG Timer
Block Diagram of Circuitry Terminating at the Pin
Associated with the 12-bit PPG Timer
Example of Operations of 12-bit PPG Timer Functions
8-bit Serial I/O
Block Diagram for 8-bit Serial I/O Pins ............. 318
Block Diagram of 8-bit Serial I/O...................... 315
Notes on Using 8-bit Serial I/O ......................... 333
Pins of 8-bit Serial I/O...................................... 317
Registers of 8-bit Serial I/O .............................. 319
16-bit Data Storage State
16-bit Operand Storage State
8-bit Serial I/O Interrupt Register
8-bit Serial I/O Interrupt Register and Vector Table
8/16-bit Capture Timer/Counter
8/16-bit Capture Timer/Counter of Interrupts
Block Diagram for 8/16-bit Capture
Block Diagram of 8/16-bit Capture
8-bit Serial Input
Program Example for 8-bit Serial Input.............. 337
8-bit Serial Output
Program Example for 8-bit Serial Output ........... 336
404
INDEX
A
B
A/D Control Register
Behavior
A/D Control Register 1 (ADC1) ........................ 266
A/D Control Register 2 (ADC2) ........................ 268
Behavior under the Flash Security Feature ..........372
Bidirectional Serial I/O Operation
A/D Conversion
When Bidirectional Serial I/O Operation is Performed
A/D Conversion Functions................................ 260
Interrupt when A/D Conversion Functions are Enabled
Operations of A/D Conversion Functions ........... 274
Program Example of the A/D Conversion Functions
Bit Manipulation
Read Destination at Execution of a Bit Manipulation
Bits
Bits for Controlling Acceptance of Interrupts
Bits for Indicating Arithmetic Operation Results
A/D Converter
Activating the A/D Converter Functions............. 273
Block Diagram of the Pins Related to the A/D
Notes on Using the A/D Converter .................... 275
Pins Related to the A/D Converter ..................... 263
Register and Vector Table Related to the Interrupt
Block Diagram
Block Diagram for 8/16-bit Capture Timer/Counter
Block Diagram for 8-bit Serial I/O Pins ..............318
Block Diagram of 12-bit PPG Timer ..................209
Block Diagram of 8/16-bit Capture Timer/Counter
Block Diagram of 8-bit Serial I/O ......................315
Block Diagram of Circuitry Terminating at the Pin
Associated with the 12-bit PPG Timer
A/D Data Register
A/D Data Register (ADDH and ADDL) ............. 270
A/D Enable Register
A/D Enable Register (ADEN) ........................... 271
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt
Abstract
Activating
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 2
Block Diagram of External Interrupt Circuit 1
Block Diagram of External Interrupt Circuit 2
Block Diagram of External Reset Pin ...................47
Block Diagram of MB89202/F202RA Series...........7
Block Diagram of Port 0......................................79
Block Diagram of Port 3......................................85
Block Diagram of Port 4......................................91
Block Diagram of Port 5......................................95
Block Diagram of Port 6....................................101
Block Diagram of Port 7....................................108
Block Diagram of the A/D Converter .................261
Block Diagram of the Pin Related to the 8-bit PWM
Block Diagram of the Pin Related to the Buzzer
Block Diagram of the Pins Related to the A/D
Block Diagram of the UART-relating Pins
Activating the A/D Converter Functions............. 273
Active Mode
Operations in Active Mode ................................. 59
ADC
A/D Control Register 1 (ADC1) ........................ 266
A/D Control Register 2 (ADC2) ........................ 268
ADDH and ADDL
A/D Data Register (ADDH and ADDL) ............. 270
Address Comparison EN Register
Address Comparison EN Register (WREN)........ 354
Addressing
Explanation on Addressing ............................... 383
ADEN
A/D Enable Register (ADEN) ........................... 271
Association
Association between the Interrupt Enable Bits for
External Interrupt Circuit 2 and the External
Automatic Erasing
Automatic Erasing ........................................... 363
Automatic Write/Erase
405
INDEX
Block Diagram of the Wild Register Function
External Interrupt Circuit 1 Programming Example
Functions of External Interrupt Circuit 1 ............ 226
Functions of External Interrupt Circuit 2
I/O Circuit Types ............................................... 14
Interrupt during the Operation of External Interrupt
Interrupt during the Operation of External Interrupt
Pins Associated with External Interrupt Circuit 1
Pins Associated with External Interrupt Circuit 2
Program Example for External Interrupt Circuit 2
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector
Branch
Buzzer Output
Block Diagram of the Pin Related to the Buzzer
Buzzer Register
BZCR
C
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
Registers Associated with External Interrupt Circuit 1
Registers Associated with External Interrupt Circuit 2
Cancellation
Cancellation of Standby Mode by an Interrupt
Capture
Capture Control Register
Capture Data Registers
Circuitry Terminating
Capture Data Registers H and L (TCPH and TCPL)
Block Diagram of Circuitry Terminating at the Pin
Associated with the 12-bit PPG Timer
Capture Timer/Counter
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 1
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 2
CCR
Configuration of the Condition Code Register (CCR)
Changing Edge Polarity Selection
Exercise Caution when Changing Edge Polarity
Clock Controller
Block Diagram of Clock Controller ..................... 54
Choice
Clock Divider Selection Register
Clock Divider Selection Register (UPC) ............ 299
Circuit
Association between the Interrupt Enable Bits for
External Interrupt Circuit 2 and the External
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 1
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 2
Block Diagram of External Interrupt Circuit 1
Block Diagram of External Interrupt Circuit 2
Clock Generator
Clock Generator................................................. 53
Clock Mode
Operations in Each Clock Mode .......................... 58
Clock Speed Switching
Gears (Clock Speed Switching Function) ............. 58
Clock Supply
Clock Supply Function ..................................... 116
Clock Supply Map ............................................. 51
Operations of Clock Supply Function ................ 122
CNTR
PWM Control Register (CNTR) ........................ 143
406
INDEX
Command Sequence
E
Command Sequence Table................................ 361
EIC
COMR
External Interrupt Control Register 1 (EIC1)
PWM Compare Register (COMR) ..................... 145
External Interrupt Control Register 2 (EIC2)
Condition Code Register
Configuration of the Condition Code Register (CCR)
EIE
EIF
Configuration
External Interrupt Circuit 2 Control Register (EIE2)
Configuration of Memory Space.......................... 22
Configuration of the Condition Code Register (CCR)
Configuration of the General-purpose Registers
Configuration of the Interrupt Level Setting Registers
(ILR1 to ILR4) ..................................... 36
Configuration of the Register Bank Pointer (RP)
Configuration of the Reset Flag Register (RSFR)
Configuration of the System Clock Control Register
External Interrupt 2 Flag Register (EIF2) ............252
Erase
Detailed Explanation of Flash Memory Write/Erase
Erasing
Automatic Erasing ............................................363
Erasing All Data (Erasing Chips) .......................371
Writing to/Erasing Flash Memory ......................358
Erasing All Data
Erasing All Data (Erasing Chips) .......................371
Erasing Chips
Erasing All Data (Erasing Chips) .......................371
Evaluation Chip
Controlling Acceptance
Bits for Controlling Acceptance of Interrupts
Programming EPROM with Evaluation Chip
Counter
Counter Function ............................................. 165
Program Example of Counter Function .............. 202
Example
Example of Operations of 12-bit PPG Timer Functions
CPU Reads
States of Pins after the CPU Reads the Mode Data
Exercise Caution
Exercise Caution when Changing Edge Polarity
D
Explanation
Explanation on the Codes Representing Instructions
Explanation on the Items of Instructions’List
Data Setting Register
Data Setting Register (WRDR).......................... 351
DDR
Registers of Port 4.............................................. 91
Registers of Port 5.............................................. 95
Registers PDR0, DDR0, and PUL0 of Port 0 ........ 79
Registers PDR3, DDR3, and PUL3 of Port 3 ........ 85
Registers PDR6, DDR6, and PUL6 of Port 6 ...... 102
Registers PDR7, DDR7, and PUL7 of Port 7 ...... 108
External Interrupt
Association between the Interrupt Enable Bits for
External Interrupt Circuit 2 and the External
Interrupt Pins.......................................248
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 1
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 2
Block Diagram of External Interrupt Circuit 1
Block Diagram of External Interrupt Circuit 2
Detailed Explanation
Detailed Explanation of Flash Memory Write/Erase
Diagram
Diagram for State Transition in Standby Mode
DIP-32P-M06
Package Dimension of DIP-32P-M06 .................. 10
Pin Assignment of DIP-32P-M06 .......................... 8
407
INDEX
Functions of External Interrupt Circuit 2
Program Access to Flash Memory ..................... 373
Writing to the Flash Memory ............................ 369
Writing to/Erasing Flash Memory...................... 358
Interrupt during the Operation of External Interrupt
Interrupt during the Operation of External Interrupt
Pins Associated with External Interrupt Circuit 1
Pins Associated with External Interrupt Circuit 2
Program Example for External Interrupt Circuit 2
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector
Flash Memory Control Status Register
Flash Memory Control Status Register (FMCS)
Flash Memory Register
Flash Memory Register .................................... 358
Flash Security
Behavior under the Flash Security Feature.......... 372
How to disable the Flash Security Feature .......... 372
FMCS
Flash Memory Control Status Register (FMCS)
FPT-34P-M03
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
Pin Assignment of FPT-34P-M03.......................... 9
Registers Associated with External Interrupt Circuit 1
Registers Associated with External Interrupt Circuit 2
Function
Function of the External Reset Pin....................... 47
Functions of 12-bit PPG Timer.......................... 206
Functions of External Interrupt Circuit 1 ............ 226
Functions of External Interrupt Circuit 2
Functions of I/O Ports ........................................ 76
Functions of Port 0 Registers .............................. 80
Functions of Port 3 Registers .............................. 86
Functions of Port 5 Registers .............................. 96
Functions of Port 6 Registers ............................ 103
Functions of Port 7 Registers ............................ 109
Functions of the Dedicated Register..................... 27
Functions of UART.......................................... 280
External Interrupt 2 Flag Register
External Interrupt Circuit
External Interrupt Circuit 1 Programming Example
External Interrupt Circuit 2 Control Register
External Interrupt Circuit 2 Control Register (EIE2)
External Interrupt Control Register
External Interrupt Control Register 1 (EIC1)
External Interrupt Control Register 2 (EIC2)
G
Gears
Gears (Clock Speed Switching Function) ............. 58
External Reset
General-purpose Register
Configuration of the General-purpose Registers
External Shift Clock
General-purpose Register Area
General-purpose Register Area
F
H
H
2
F MC-8L
H
2
Overview of the Instructions of the F MC-8L
Halfway Stop
Operation in Standby Mode and at Halfway Stop
Features
Hardware Reset
Flash Content Protection
Input of a Hardware Reset (RST)....................... 373
Hardware Sequence
Flash Memory
Detailed Explanation of Flash Memory Write/Erase
408
INDEX
High voltage
High voltage supply on RST pin
(applicable to MB89F202RA only)
Internal Shift Clock
When the Internal Shift Clock is Used ................329
Interrupt
8/16-bit Capture Timer/Counter of Interrupts
Association between the Interrupt Enable Bits for
External Interrupt Circuit 2 and the External
Interrupt Pins.......................................248
Bits for Controlling Acceptance of Interrupts ........30
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 1
Block Diagram of Circuitry Terminating at the Pins
Associated with External Interrupt Circuit 2
Block Diagram of External Interrupt Circuit 1
Block Diagram of External Interrupt Circuit 2
Cancellation of Standby Mode by an Interrupt
Configuration of the Interrupt Level Setting Registers
External Interrupt 2 Flag Register (EIF2) ............252
External Interrupt Circuit 1 Programming Example
External Interrupt Circuit 2 Control Register (EIE2)
External Interrupt Control Register 1 (EIC1)
External Interrupt Control Register 2 (EIC2)
Functions of External Interrupt Circuit 2
Higher Address Set Register
Higher Address Set Register (WRARH)............. 352
How to
How to disable the Flash Security Feature .......... 372
I
I/O
8-bit Serial I/O Interrupt Register and Vector Table
Block Diagram for 8-bit Serial I/O Pins.............. 318
Functions of I/O Ports ........................................ 76
I/O Circuit Types ............................................... 14
I/O Port Programming Example ........................ 113
Interrupt at Serial I/O Operation ........................ 324
Notes on Using 8-bit Serial I/O ......................... 333
Pins of 8-bit Serial I/O...................................... 317
Registers of 8-bit Serial I/O............................... 319
Serial I/O Function........................................... 314
When Bidirectional Serial I/O Operation is Performed
ILR
Configuration of the Interrupt Level Setting Registers
(ILR1 to ILR4) ..................................... 36
Indicating Arithmetic Operation Results
Bits for Indicating Arithmetic Operation Results
(Level Detection).................................244
Interrupt at Serial I/O Operation.........................324
Interrupt during the Operation of External Interrupt
Interrupt during the Operation of External Interrupt
Interrupt Processing Time....................................40
Interrupt when A/D Conversion Functions are Enabled
Interrupts when the Interval Timer Function is
Interrupts while Interval Timer Functions are Enabled
Operation of External Interrupt Circuit 1.............239
Operation of External Interrupt Circuit 2.............254
Oscillation Stabilization Time and Time-base Timer
Pins Associated with External Interrupt Circuit 1
Pins Associated with External Interrupt Circuit 2
Influence
Influence from a Reset of Contents in RAM ......... 49
Input
Input of a Hardware Reset (RST)....................... 373
Instruction
Branch Instructions .......................................... 397
Explanation on the Codes Representing Instructions
Explanation on the Items of Instructions’List
Instruction Map ............................................... 399
Operation Instructions ...................................... 394
Other Instructions ............................................ 398
2
Overview of the Instructions of the F MC-8L
Read Destination at Execution of a Bit Manipulation
Transfer Instructions ........................................ 392
Instruction Cycle
Instruction Cycle (t
INST
409
INDEX
Program Example for External Interrupt Circuit 2
L
Register and Vector Table Related to 8/16-bit Capture
Register and Vector Table Related to Interrupts from
Register and Vector Table Related to the Interrupt of
Register and Vector Table Related to the Interrupts of
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector
Level Detection
Functions of External Interrupt Circuit 2
Lower Address Set Register
Lower Address Set Register (WRARL).............. 353
M
Mask
MB89202/F202RA
Features of MB89202/F202RA Series.................... 2
MB89202/F202RA Series Models ......................... 4
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
Memory Access
Registers Associated with External Interrupt Circuit 1
Registers Associated with External Interrupt Circuit 2
Stack Operation at the Beginning of Interrupt
Stack Operation at the End of Interrupt Processing
UART Interrupt Related Registers and Vector Table
Operations for Selecting Memory Access Mode
Memory Map
Memory Space
Configuration of Memory Space.......................... 22
Mode
Cancellation of Standby Mode by an Interrupt
Diagram for State Transition in Standby Mode
Notes on Setting Standby Mode .......................... 70
Operation in Standby Mode and at Halfway Stop
Operations for Selecting Memory Access Mode
Operations in Active Mode ................................. 59
Operations in Each Clock Mode .......................... 58
Operations in the Standby Mode and at a Suspension
Operations Related to Stop Mode ........................ 65
Pin States in Each Operation Mode.................... 402
Reception Operations (Operating Mode 0,1,or 3)
Reception Operations (Operating Mode 2 Only)
Single-chip Mode............................................... 72
States of Pins after the CPU Reads the Mode Data
Theory of Operation for Operating Mode 0,1,2, and 3
Transition to Standby Mode and Interrupt ............ 70
Transmission Operations in Operating Mode is
Interrupt Enable Bits
Association between the Interrupt Enable Bits for
External Interrupt Circuit 2 and the External
Interrupt Level Setting Registers
Configuration of the Interrupt Level Setting Registers
Interrupt Requests
Interval Timer
Interrupts when the Interval Timer Function is
Interrupts while Interval Timer Functions are Enabled
Interval Timer Functions (Functions to Output
Operations of Interval Timer Function
Program Example of Interval Timer Function
Program Example of Interval Timer Functions
410
INDEX
Multiple Interrupts
Operations in Standby Mode................................63
Operations in the Standby Mode and at a Suspension
Multiple Interrupts ............................................. 39
Operations of A/D Conversion Functions............274
Operations of Clock Supply Function .................122
Operations of Interval Timer Function
Operations of the 8-bit PWM Timer Functions
N
Notes
Notes on Setting Standby Mode........................... 70
Notes on Using 12-bit PPG Timer ..................... 221
Notes on Using 8-bit PWM Timer ..................... 155
Notes on Using 8-bit Serial I/O ......................... 333
Notes on Using the 8/16-bit Capture Timer/Counter
Notes on Using the A/D Converter .................... 275
Notes on Using Time-base Timer ...................... 124
Notes on Using Watchdog Timer....................... 132
Operations of the Interval Timer Functions .........148
Operations of Time-base Timer..........................122
Operations of Watchdog Timer ..........................131
Operations Related to Sleep Mode........................64
Overview of the Reset Operation..........................48
Pin States in Each Operation Mode ....................402
Read-modify-write Operation ............................391
Reception Operations (Operating Mode 0,1,or 3)
Reception Operations (Operating Mode 2 Only)
Serial Output Operation.....................................325
Stack Operation at the Beginning of Interrupt
Stack Operation at the End of Interrupt Processing
Steps in the Interrupt Operation............................37
Theory of Operation for Operating Mode 0,1,2, and 3
Transmission Operations in Operating Mode is
When Bidirectional Serial I/O Operation is Performed
O
Operating Mode
Reception Operations (Operating Mode 0,1,or 3)
Reception Operations (Operating Mode 2 Only)
Theory of Operation for Operating Mode 0,1,2, and 3
Transmission Operations in Operating Mode is
Operation
Bits for Indicating Arithmetic Operation Results
Capture Function Operation .............................. 193
Example of Operations of 12-bit PPG Timer Functions
Interrupt at Serial I/O Operation ........................ 324
Interrupt during the Operation of External Interrupt
Interrupt during the Operation of External Interrupt
Interval Timer Function Operation..................... 185
Operation at Serial Output Completion............... 326
Operation in Standby Mode and at Halfway Stop
Operation Order
Operation Order of the Wild Register Function
Oscillation Stabilization Wait Time
Oscillation Stabilization Time and Time-base Timer
Reset Sources and Oscillation Stabilization Wait Time
Operation Instructions ...................................... 394
Operation of External Interrupt Circuit 1 ............ 239
Operation of External Interrupt Circuit 2 ............ 254
Operation of Port 0............................................. 82
Operation of Port 3............................................. 88
Operation of Port 4............................................. 93
Operation of Port 5............................................. 98
Operation of Port 6........................................... 105
Operation of Port 7........................................... 111
Operations for Selecting Memory Access Mode
Other
Other Instructions .............................................398
OUT
Registers of Port 4 ..............................................91
Overview
2
Overview of the Instructions of the F MC-8L
Overview of the Reset Operation..........................48
Operations in Active Mode ................................. 59
Operations in Each Clock Mode .......................... 58
411
INDEX
P
Structure of Port 3.............................................. 84
Port 4
P37/BZ/PPG
Operation of Port 4............................................. 93
Pins of Port 4..................................................... 90
Registers of Port 4.............................................. 91
Structure of Port 4.............................................. 90
Package Dimension
PDR
Port 5
Functions of Port 5 Registers .............................. 96
Operation of Port 5............................................. 98
Pins of Port 5..................................................... 94
Registers of Port 5.............................................. 95
Structure of Port 5.............................................. 94
Peripheral Function
Port 6
Interrupt Requests from Peripheral Functions
Functions of Port 6 Registers ............................ 103
Operation of Port 6........................................... 105
Pins of Port 6................................................... 100
Registers PDR6, DDR6, and PUL6 of Port 6
Pin
Pins Associated with External Interrupt Circuit 1
Pins Associated with External Interrupt Circuit 2
Structure of Port 6............................................ 100
Port 7
Functions of Port 7 Registers ............................ 109
Operation of Port 7........................................... 111
Pins of Port 7................................................... 107
Registers PDR7, DDR7, and PUL7 of Port 7
Structure of Port 7............................................ 107
PPG Timer
Block Diagram of Circuitry Terminating at the Pin
Associated with the 12-bit PPG Timer
Pin Assignment
Precautions
Precautions on Handling Devices ........................ 18
Pin Function
Program Access
Pin States
Program Access to Flash Memory ..................... 373
Program Example
Port
Program Example for 12-bit PPG Timer............. 223
Program Example for 8-bit Serial Input.............. 337
Program Example for 8-bit Serial Output ........... 336
Program Example for Buzzer Output ................. 345
Program Example for External Interrupt Circuit 2
Program Example for UART............................. 311
Program Example of Counter Function .............. 202
Program Example of Interval Timer Functions
Program Example of PWM Timer Functions
Program Example of the A/D Conversion Functions
Port 0
Port 3
412
INDEX
Programming EPROM
12-bit PPG Control Register 2 (RCR22) .............215
12-bit PPG Control Register 3 (RCR23) .............216
12-bit PPG Control Register 4 (RCR24) .............218
8-bit Serial I/O Interrupt Register and Vector Table
A/D Control Register 1 (ADC1).........................266
A/D Control Register 2 (ADC2).........................268
A/D Data Register (ADDH and ADDL)..............270
Address Comparison EN Register (WREN) ........354
Block Diagram of the Wild Register Function
Buzzer Register (BZCR) ...................................343
Capture Control Register (TCCR) ......................171
Capture Data Registers H and L (TCPH and TCPL)
Clock Divider Selection Register (UPC) .............299
Configuration of the Condition Code Register (CCR)
Programming EPROM with Evaluation Chip
Programming Example
External Interrupt Circuit 1 Programming Example
Programming Examples for Time-base Timer
Programming Examples of Watchdog Timer
PUL
Registers of Port 5.............................................. 95
Registers PDR0, DDR0, and PUL0 of Port 0 ........ 79
Registers PDR3, DDR3, and PUL3 of Port 3 ........ 85
Registers PDR6, DDR6, and PUL6 of Port 6 ...... 102
Registers PDR7, DDR7, and PUL7 of Port 7 ...... 108
PWM Compare Register
PWM Compare Register (COMR) ..................... 145
PWM Control Register
Configuration of the General-purpose Registers
Configuration of the Interrupt Level Setting Registers
Configuration of the Register Bank Pointer (RP)
PWM Control Register (CNTR) ........................ 143
PWM Timer
Program Example of PWM Timer Functions
PWM Timer Functions ..................................... 137
Configuration of the Reset Flag Register (RSFR)
R
Configuration of the System Clock Control Register
RAM
16-bit Data Storage State on RAM....................... 26
Influence from a Reset of Contents in RAM ......... 49
Data Setting Register (WRDR) ..........................351
Dedicated Register Configuration.........................27
External Interrupt 2 Flag Register (EIF2) ............252
External Interrupt Circuit 2 Control Register (EIE2)
External Interrupt Control Register 1 (EIC1)
External Interrupt Control Register 2 (EIC2)
RCR
Read
Setting the Read/Reset State.............................. 368
States of Pins after the CPU Reads the Mode Data
Features of the General-purpose Registers.............33
Flash Memory Control Status Register (FMCS)
Read Destination
Read Destination at Execution of a Bit Manipulation
Flash Memory Register .....................................358
Functions of Port 0 Registers ...............................80
Functions of Port 3 Registers ...............................86
Functions of Port 5 Registers ...............................96
Functions of Port 6 Registers .............................103
Functions of Port 7 Registers .............................109
Functions of the Dedicated Register .....................27
General-purpose Register Area
Read-modify-write
Read-modify-write Operation............................ 391
Receiving Status
Receiving Status .............................................. 296
Reception
Reception Interrupt .......................................... 303
H
H
Reception Operations
Higher Address Set Register (WRARH) .............352
Lower Address Set Register (WRARL) ..............353
Operation Order of the Wild Register Function
PWM Compare Register (COMR)......................145
Reception Operations
(Operating Mode 0,1,or 3)................... 307
Reception Operations
(Operating Mode 2 Only).................... 309
Register
413
INDEX
Register and Vector Table Related to 8/16-bit Capture
Register Bank Pointer
Register and Vector Table Related to Interrupts from
Configuration of the Register Bank Pointer (RP)
Reset
Register and Vector Table Related to the Interrupt of
Register and Vector Table Related to the Interrupts of
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector Table
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
Registers Associated with 12-bit PPG Timer
Registers Associated with External Interrupt Circuit 1
Registers Associated with External Interrupt Circuit 2
Registers of 8/16-bit Capture Timer/Counter
Block Diagram of External Reset Pin................... 47
Function of the External Reset Pin....................... 47
Influence from a Reset of Contents in RAM ......... 49
Input of a Hardware Reset (RST)....................... 373
Setting the Read/Reset State.............................. 368
Software Reset,Watchdog Timer Reset .............. 373
State of Reset Waiting for Stabilization of Oscillation
States of Pins during Reset.................................. 50
Reset Flag Register
Configuration of the Reset Flag Register (RSFR)
Reset Sources
Reset Sources .................................................... 43
Reset Sources and Oscillation Stabilization Wait
Reset Waiting
Registers Related to the Wild Register Function
State of Reset Waiting for Stabilization of Oscillation
RP
Configuration of the Register Bank Pointer (RP)
RSFR
Configuration of the Reset Flag Register (RSFR)
RST
Input of a Hardware Reset (RST)....................... 373
UART Interrupt Related Registers and Vector Table
RST pin
High voltage supply on RST pin
(applicable to MB89F202RA only)
S
SDR
Serial Data Register (SDR) ............................... 323
Serial Data Register
Serial Data Register (SDR) ............................... 323
Serial Function Switching
Serial I/O
8-bit Serial I/O Interrupt Register and Vector Table
Block Diagram for 8-bit Serial I/O Pins ............. 318
Block Diagram of 8-bit Serial I/O...................... 315
Interrupt at Serial I/O Operation ........................ 324
Notes on Using 8-bit Serial I/O ......................... 333
Pins of 8-bit Serial I/O...................................... 317
Registers of 8-bit Serial I/O .............................. 319
Serial I/O Function........................................... 314
414
INDEX
When Bidirectional Serial I/O Operation is Performed
Stabilization of Oscillation
State of Reset Waiting for Stabilization of Oscillation
Serial Input
Serial Input Operation ...................................... 327
Stack
16-bit Data Storage State in Stack ........................26
Stack Area
Stack Area for Interrupt Processing ......................42
Stack Operation
Serial Input Data Register
Serial Input Data Register (SIDR)...................... 297
Serial Mode Control Register
Stack Operation at the Beginning of Interrupt
Stack Operation at the End of Interrupt Processing
Serial Mode Control Register (SMC) ................. 290
Serial Mode Register
Serial Mode Register (SMR) ............................. 320
Standby Control Register
Serial Output
Standby Control Register (STBC) ........................66
Operation at Serial Output Completion............... 326
Program Example for 8-bit Serial Output ........... 336
Standby Mode
Cancellation of Standby Mode by an Interrupt
Diagram for State Transition in Standby Mode
Notes on Setting Standby Mode ...........................70
Operation in Standby Mode and at Halfway Stop
Operations in Standby Mode................................63
Operations in the Standby Mode and at a Suspension
Transition to Standby Mode and Interrupt .............70
Serial Output Data Register
Serial Output Data Register (SODR).................. 298
Serial Rate Control Register
Serial Rate Control Register (SRC).................... 292
Serial Status and Data Register
Serial Switch
Serial Switch ................................................... 281
Serial Switch Register
Serial Switch Register (SSEL)........................... 301
Setting
State
Setting the Read/Reset State.............................. 368
State of Reset Waiting for Stabilization of Oscillation
States of Pins after the CPU Reads the Mode Data
States of Pins during Reset ..................................50
SIDR
Serial Input Data Register (SIDR)...................... 297
Single-chip Mode
Single-chip Mode............................................... 72
STBC
Sleep Mode
Standby Control Register (STBC) ........................66
Steps
SMC
Steps in the Interrupt Operation............................37
Serial Mode Control Register (SMC) ................. 290
Stop Mode
SMR
Serial Mode Register (SMR) ............................. 320
Structure
SODR
Structure of Port 0 ..............................................78
Structure of Port 3 ..............................................84
Structure of Port 4 ..............................................90
Structure of Port 5 ..............................................94
Structure of Port 6 ............................................100
Structure of Port 7 ............................................107
Serial Output Data Register (SODR).................. 298
Software Reset
Software Reset,Watchdog Timer Reset .............. 373
Special Instructions
Square Wave
Suspension
Interval Timer Functions (Functions to Output
Operations in the Standby Mode and at a Suspension
SRC
SYCC
Serial Rate Control Register (SRC).................... 292
Configuration of the System Clock Control Register
SSD
System Clock Control Register
SSEL
Configuration of the System Clock Control Register
Serial Switch Register (SSEL)........................... 301
415
INDEX
T
Transition to Standby Mode and Interrupt ............ 70
Transmission
TBTC
Transmission Interrupt...................................... 303
TCCR
Transmission Operations
Transmission Operations in Operating Mode is
TCPH and TCPL
Capture Data Registers H and L (TCPH and TCPL)
U
TCR
UART
Block Diagram of the UART-relating Pins
Block Diagram of UART.................................. 284
Functions of UART.......................................... 280
Program Example for UART............................. 311
UART Relating Pins ........................................ 287
UART-relating Registers .................................. 289
TDR
Theory
UART Interrupt Related Registers
Theory of Operation for Operating Mode 0,1,2, and 3
UART Interrupt Related Registers and Vector Table
Time-base Timer
UART-relating Registers
Operations of Interval Timer Function
UART-relating Registers .................................. 289
UPC
Oscillation Stabilization Time and Time-base Timer
Programming Examples for Time-base Timer
Register and Vector Table Related to Interrupts from
Clock Divider Selection Register (UPC) ............ 299
V
Vector Table
8-bit Serial I/O Interrupt Register and Vector
Register and Vector Table Related to 8/16-bit Capture
Timer/Counter of Interrupts ................. 184
Register and Vector Table Related to Interrupts from
Time-base Timer................................. 121
Register and Vector Table Related to the Interrupt of
the A/D Converter............................... 272
Register and Vector Table Related to the Interrupts of
an 8-bit PWM Timer ........................... 147
Register Associated with Interrupt Generation by
External Interrupt Circuit 1 and Vector
Time-base Timer Control Register
Timer 0 Control Register
Timer 0 Data Register
Timer 1 Control Register
Register Associated with Interrupt Generation by
External Interrupt Circuit 2 and Vector
UART Interrupt Related Registers and Vector Table
Timer 1 Data Register
Timer Output Control Register
t
INST
Instruction Cycle (t
INST
Vector Table Area
Transfer
Vector Table Area
H
H
Transfer Clock Rate
W
Transferred Data Format
Watchdog Control Register
Transition
Watchdog Timer
Diagram for State Transition in Standby Mode
Block Diagram of Watchdog Timer ................... 129
Notes on Using Watchdog Timer....................... 132
416
INDEX
Operations of Watchdog Timer ......................... 131
Programming Examples of Watchdog Timer
Software Reset,Watchdog Timer Reset .............. 373
Watchdog Timer Function ................................ 128
WRARL
Lower Address Set Register (WRARL) ..............353
WRDR
Data Setting Register (WRDR) ..........................351
WREN
Address Comparison EN Register (WREN) ........354
Write
WDTC
Watchdog Control Register (WDTC) ................. 130
Wild Register
Detailed Explanation of Flash Memory Write/Erase
Block Diagram of the Wild Register Function
Operation Order of the Wild Register Function
Registers Related to the Wild Register Function
Wild Register Addresses List ............................ 356
Wild Register Applicable Addresses .................. 348
Wild Register Function..................................... 348
Writing
Notes on Writing Data ......................................369
Writing to/Erasing Flash Memory ......................358
Writing Data
WRARH
Higher Address Set Register (WRARH)............. 352
417
INDEX
418
CM25-10153-2E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
2
F MC-8L
8-BIT MICROCONTROLLER
MB89202/F202RA Series
HARDWARE MANUAL
February 2008 the second edition
Published FUJITSU LIMITED Electronic Devices
Edited
Strategic Business Development Dept.
|
