Cypress STK12C68 5 User Manual

STK12C68-5 (SMD5962-94599)  
64 Kbit (8K x 8) AutoStore nvSRAM  
Features  
Functional Description  
35 ns and 55 ns access times  
The Cypress STK12C68-5 is a fast static RAM with a nonvol-  
atile element in each memory cell. The embedded nonvolatile  
Hands off automatic STORE on power down with external  
68 µF capacitor  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down.  
On power up, data is restored to the SRAM (the RECALL  
operation) from the nonvolatile memory. Both the STORE and  
RECALL operations are also available under software control.  
A hardware STORE is initiated with the HSB pin.  
STORE to QuantumTrap™ nonvolatile elements is initiated  
by software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited Read, Write, and Recall cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Military temperature  
28-pin (300mil) CDIP and 28-pad LCC packages  
Logic Block Diagram  
V
V
CC  
CAP  
Quantum Trap  
128 X 512  
A5  
POWER  
STORE  
CONTROL  
A6  
A7  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
128 X 512  
A8  
HSB  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0 -A12  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
A0  
A4  
A10  
A1  
A3  
A2  
DQ6  
DQ7  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51026 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2009  
STK12C68-5 (SMD5962-94599)  
During normal operation, the device draws current from V to  
Device Operation  
CC  
charge a capacitor connected to the V  
pin. This stored  
CAP  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the V pin drops below V , the part  
The STK12C68-5 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM Read and Write operations are inhibited. The  
STK12C68-5 supports unlimited reads and writes similar to a  
typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
CC  
SWITCH  
automatically disconnects the V  
operation is initiated with power provided by the V  
pin from V . A STORE  
CAP  
CC  
capacitor.  
CAP  
Figure 3 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. A charge storage capacitor  
CAP  
between 68 µF and 220 µF (+20%) rated at 6V must be provided.  
The voltage on the V pin is driven to 5V by a charge pump  
CAP  
internal to the chip. A pull up is placed on WE to hold it inactive  
during power up.  
Figure 3. AutoStore Mode  
SRAM Read  
The STK12C68-5 performs a Read cycle whenever CE and OE  
are LOW while WE and HSB are HIGH. The address specified  
9&$3  
9FF  
on pins A  
determines the 8,192 data bytes accessed. When  
0–12  
the Read is initiated by an address transition, the outputs are  
valid after a delay of t (Read cycle 1). If the Read is initiated  
:(  
AA  
+6%  
by CE or OE, the outputs are valid at t  
or at t  
, whichever  
ACE  
DOE  
is later (Read cycle 2). The data outputs repeatedly respond to  
address changes within the t access time without the need for  
AA  
transitions on any control input pins, and remains valid until  
another address change or until CE or OE is brought HIGH, or  
WE or HSB is brought LOW.  
SRAM Write  
A Write cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the Write cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
pins DQ  
are written into the memory if it has valid t , before  
0–7  
SD  
9VV  
the end of a WE controlled Write or before the end of an CE  
controlled Write. Keep OE HIGH during the entire Write cycle to  
avoid data bus contention on common IO lines. If OE is left LOW,  
internal circuitry turns off the output buffers t  
LOW.  
after WE goes  
In system power mode, both V and V  
are connected to the  
CAP  
CC  
HZWE  
+5V power supply without the 68 μF capacitor. In this mode, the  
AutoStore function of the STK12C68-5 operates on the stored  
system charge as power goes down. The user must, however,  
AutoStore Operation  
guarantee that V does not drop below 3.6V during the 10 ms  
CC  
The STK12C68-5 stores data to nvSRAM using one of three  
storage operations:  
STORE cycle.  
To reduce unnecessary nonvolatile stores, AutoStore, and  
Hardware Store operations are ignored, unless at least one Write  
operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a Write operation has taken place. An  
optional pull up resistor is shown connected to HSB. The HSB  
signal is monitored by the system to detect if an AutoStore cycle  
is in progress.  
1. Hardware store activated by HSB  
2. Software store activated by an address sequence  
3. AutoStore on device power down  
AutoStore operation is a unique feature of QuantumTrap  
technology and is enabled by default on the STK12C68-5.  
Document Number: 001-51026 Rev. **  
Page 3 of 18  
 
STK12C68-5 (SMD5962-94599)  
Figure 4. AutoStore Inhibit Mode  
During any STORE operation, regardless of how it is initiated,  
the STK12C68-5 continues to drive the HSB pin LOW,  
releasing it only when the STORE is complete. After  
completing the STORE operation, the STK12C68-5 remains  
disabled until the HSB pin returns HIGH.  
9&$3  
9FF  
:(  
If HSB is not used, it is left unconnected.  
Hardware RECALL (Power Up)  
+6%  
During power up or after any low power condition (V  
<
CC  
V
), an internal RECALL request is latched. When V  
RESET  
CC  
once again exceeds the sense voltage of V  
, a RECALL  
SWITCH  
cycle is automatically initiated and takes t  
to complete.  
HRECALL  
If the STK12C68-5 is in a Write state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
and system V or between CE and system V  
.
CC  
CC  
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory  
by a software address sequence. The STK12C68-5 software  
STORE cycle is initiated by executing sequential CE controlled  
Read cycles from six specific address locations in exact order.  
During the STORE cycle, an erase of the previous nonvolatile  
data is first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output  
are disabled until the cycle is completed.  
9VV  
If the power supply drops faster than 20 us/volt before Vcc  
reaches V  
between V  
, then a 2.2 ohm resistor must be connected  
and the system supply to avoid momentary  
SWITCH  
CC  
Because a sequence of Reads from specific addresses is  
used for STORE initiation, it is important that no other Read or  
Write accesses intervene in the sequence. If they intervene,  
the sequence is aborted and no STORE or RECALL takes  
place.  
excess of current between V and V  
.
CC  
CAP  
AutoStore Inhibit Mode  
If an automatic STOREon power loss is not required, then V  
CC  
is tied to ground and +5V is applied to V  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the STK12C68-5 is operated in this configuration,  
(Figure 4). This is  
CAP  
To initiate the software STORE cycle, the following Read  
sequence is performed:  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
3. Read address 0x0AAA, Valid READ  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0F, Initiate STORE cycle  
references to V are changed to V  
throughout this data  
CAP  
CC  
sheet. In this mode, STORE operations are triggered through  
software control or the HSB pin. To enable or disable Autostore  
using an IO port pin see Preventing Store on page 5. It is not  
permissible to change between these three options “on the  
fly”.  
Hardware STORE (HSB) Operation  
The software sequence is clocked with CE controlled Reads  
or OE controlled Reads. When the sixth address in the  
sequence is entered, the STORE cycle commences and the  
chip is disabled. It is important that Read cycles and not Write  
cycles are used in the sequence. It is not necessary that OE  
The STK12C68-5 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used  
to request a hardware STORE cycle. When the HSB pin is  
driven LOW, the STK12C68-5 conditionally initiates a STORE  
is LOW for a valid sequence. After the t  
cycle time is  
STORE  
operation after t  
. An actual STORE cycle only begins if a  
DELAY  
fulfilled, the SRAM is again activated for Read and Write  
operation.  
Write to the SRAM takes place since the last STORE or  
RECALL cycle. The HSB pin also acts as an open drain driver  
that is internally driven LOW to indicate a busy condition, while  
the STORE (initiated by any means) is in progress.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM  
by a software address sequence. A software RECALL cycle is  
initiated with a sequence of Read operations in a manner  
similar to the software STORE initiation. To initiate the  
RECALL cycle, the following sequence of CE controlled Read  
operations is performed:  
SRAM Read and Write operations, that are in progress when  
HSB is driven LOW by any means, are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the STK12C68-5 continues SRAM operations for t  
.
DELAY  
During t  
, multiple SRAM Read operations take place. If  
DELAY  
a Write is in progress when HSB is pulled LOW, it allows a  
time, t to complete. However, any SRAM Write cycles  
requested after HSB goes LOW are inhibited until HSB returns  
HIGH.  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
3. Read address 0x0AAA, Valid READ  
DELAY  
Document Number: 001-51026 Rev. **  
Page 4 of 18  
 
STK12C68-5 (SMD5962-94599)  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0E, Initiate RECALL cycle  
Figure 5. Current Versus Cycle Time (Read)  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared; then, the nonvolatile information is transferred into the  
SRAM cells. After the t  
cycle time, the SRAM is again  
RECALL  
ready for Read and Write operations. The RECALL operation  
does not alter the data in the nonvolatile elements. The nonvol-  
atile data can be recalled an unlimited number of times.  
Data Protection  
The STK12C68-5 protects data from corruption during low  
voltage conditions by inhibiting all externally initiated STORE  
and Write operations. The low voltage condition is detected  
when V is less than V  
. If the STK12C68-5 is in a Write  
CC  
SWITCH  
mode (both CE and WE are low) at power up after a RECALL or  
after a STORE, the Write is inhibited until a negative transition  
on CE or WE is detected. This protects against inadvertent writes  
during power up or brown out conditions.  
Figure 6. Current Versus Cycle Time (Write)  
Noise Considerations  
The STK12C68-5 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between V and V  
using leads and traces that are as short  
CC  
SS,  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Hardware Protect  
The STK12C68-5 offers hardware protection against inadvertent  
STORE operation and SRAM Writes during low voltage condi-  
tions. When V  
<V  
, all externally initiated STORE  
CAP  
SWITCH  
operations and SRAM Writes are inhibited. AutoStore can be  
completely disabled by tying VCC to ground and applying +5V to  
Preventing Store  
V
. This is the AutoStore Inhibit mode; in this mode, STOREs  
are only initiated by explicit request using either the software  
sequence or the HSB pin.  
CAP  
The STORE function is disabled by holding HSB high with a  
driver capable of sourcing 30 mA at a V  
of at least 2.2V,  
OH  
because it must overpower the internal pull down device. This  
device drives HSB LOW for 20 μs at the onset of a STORE.  
When the STK12C68-5 is connected for AutoStore operation  
Low Average Active Power  
CMOS technology provides the STK12C68-5 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 5 and Figure 6 shows the relationship  
(system V connected to V and a 68 μF capacitor on V )  
CC  
crosses V  
CC  
CAP  
and V  
on the way down, the STK12C68-5  
CC  
SWITCH  
attempts to pull HSB LOW. If HSB does not actually get below  
between I and Read or Write cycle time. Worst case current  
CC  
V , the part stops trying to pull HSB LOW and abort the STORE  
consumption is shown for both CMOS and TTL input levels  
(commercial temperature range, VCC = 5.5V, 100% duty cycle  
on chip enable). Only standby current is drawn when the chip is  
disabled. The overall average current drawn by the STK12C68-5  
depends on the following items:  
IL  
attempt.  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of Reads to Writes  
CMOS versus TTL input levels  
The operating temperature  
The V level  
CC  
Document Number: 001-51026 Rev. **  
Page 5 of 18  
     
STK12C68-5 (SMD5962-94599)  
Power up boot firmware routines must rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a  
preset state, best practice is to again rewrite the nvSRAM  
into the desired state as a safeguard against events that  
might flip the bit inadvertently (program bugs, incoming  
inspection routines, and so on).  
Best Practices  
nvSRAM products have been used effectively for over 15  
years. While ease-of-use is one of the product’s main system  
values, experience gained working with hundreds of applica-  
tions has resulted in the following suggestions as best  
practices:  
The Vcap value specified in this data sheet includes a  
minimum and a maximum value size. The best practice is to  
meet this requirement and not exceed the maximum Vcap  
value because the higher inrush currents may reduce the  
reliability of the internal pass transistor. Customers who want  
to use a larger Vcap value to make sure there is extra store  
charge must discuss their Vcap size selection with Cypress.  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites sometimes reprograms these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
The end product’s firmware must not assume that an NV  
array is in a set programmed state. Routines that check  
memory content values to determine first time system config-  
uration, cold or warm boot status, and so on must always  
program a unique NV pattern (for example, complex 4-byte  
pattern of 46 E6 49 53 hex or more random bytes) as part of  
the final system manufacturing test to ensure these system  
routines work consistently.  
Table 1. Hardware Mode Selection  
CE  
H
L
WE  
X
HSB  
H
A12–A0  
Mode  
IO  
Power  
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
Standby  
H
H
Active  
L
L
H
Active  
[1]  
X
X
L
Nonvolatile STORE Output High Z  
I
CC2  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active I  
CC2  
Nonvolatile STORE Output High Z  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0E  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Nonvolatile RECALL Output High Z  
Notes  
1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby  
mode, inhibiting all operations until HSB rises.  
2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
3. IO state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
Document Number: 001-51026 Rev. **  
Page 6 of 18  
       
STK12C68-5 (SMD5962-94599)  
Voltage on DQ or HSB .......................–0.5V to Vcc + 0.5V  
Maximum Ratings  
0-7  
Power Dissipation.......................................................... 1.0W  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Temperature under Bias ............................. –55°C to +125°C  
Voltage on Input Relative to GND.....................–0.5V to 7.0V  
Operating Range  
Range  
Military  
Ambient Temperature  
V
CC  
-55°C to +125°C  
4.5V to 5.5V  
Voltage on Input Relative to Vss............0.6V to V + 0.5V  
CC  
DC Electrical Characteristics  
Over the operating range (V = 4.5V to 5.5V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
= 35 ns  
= 55 ns  
75  
55  
mA  
mA  
CC1  
CC  
RC  
RC  
Dependent on output loading and cycle rate. Values  
obtained without output loads.  
I
= 0 mA.  
OUT  
I
I
Average V Current All Inputs Do Not Care, V = Max  
3
mA  
mA  
CC2  
CC  
CC  
during STORE  
Average current for duration t  
STORE  
AverageV Currentat WE > (V – 0.2V). All other inputs cycling.  
10  
CC3  
CC  
CC  
t
= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values  
RC  
Typical  
obtained without output loads.  
I
I
Average V  
Current All Inputs Do Not Care, V = Max  
2
mA  
CC4  
CAP  
CC  
during AutoStore Cycle Average current for duration t  
STORE  
V
Standby Current  
t
t
= 35 ns, CE > V  
= 55 ns, CE > V  
24  
19  
mA  
mA  
CC  
RC  
RC  
IH  
IH  
SB1  
(Standby, Cycling TTL  
Input Levels)  
V
Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V).  
2.5  
mA  
I
CC  
CC  
IN  
CC  
SB2  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
I
I
Input Leakage Current V = Max, V < V < V  
-1  
-5  
+1  
+5  
μA  
IX  
CC  
CC  
SS  
IN  
CC  
Off State Output  
Leakage Current  
V
= Max, V < V < V , CE or OE > V or WE < V  
IL  
μA  
OZ  
SS  
IN  
CC  
IH  
V
V
V
V
V
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
2.2  
V
+ 0.5  
CC  
V
V
V
V
V
IH  
V
– 0.5  
SS  
0.8  
IL  
I
I
I
= –4 mA  
= 8 mA  
= 3 mA  
2.4  
OH  
OL  
BL  
OUT  
OUT  
OUT  
0.4  
0.4  
Logic ‘0’ Voltage on  
HSB Output  
V
Storage Capacitor  
Between Vcap pin and Vss, 6V rated. 68 µF +20% nom.  
54  
260  
µF  
CAP  
Notes  
4.  
V
reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V  
if VCC is connected to ground.  
CC  
CAP  
5. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-51026 Rev. **  
Page 7 of 18  
   
STK12C68-5 (SMD5962-94599)  
Data Retention and Endurance  
Parameter  
DATA  
Description  
Data Retention  
Nonvolatile STORE Operations  
Min  
100  
Unit  
Years  
K
R
NV  
1,000  
C
Capacitance  
In the following table, the capacitance parameters are listed.  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
8
Unit  
pF  
C
C
T = 25°C, f = 1 MHz,  
CC  
IN  
A
V
= 0 to 3.0 V  
7
pF  
OUT  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.  
Parameter  
Description  
Test Conditions  
28-CDIP 28-LCC  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, per  
EIA / JESD51.  
TBD  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
TBD  
°C/W  
Figure 7. AC Test Loads  
R1 963Ω  
R1 963Ω  
For Tri-state Specs  
5.0V  
5.0V  
Output  
Output  
R2  
R2  
512  
30 pF  
5 pF  
512Ω  
Ω
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times (10% to 90%)...................... <5 ns  
Input and Output Timing Reference Levels.......................1.5  
Note  
6. These parameters are guaranteed by design and are not tested.  
Document Number: 001-51026 Rev. **  
Page 8 of 18  
 
STK12C68-5 (SMD5962-94599)  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
35 ns  
55 ns  
Description  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
35  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
ELQV  
t
35  
55  
RC  
AA  
AVAV, ELEH  
[8]  
Address Access Time  
35  
15  
55  
35  
AVQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
DOE  
OHA  
GLQV  
5
5
5
5
AXQX  
[9]  
[9]  
LZCE  
HZCE  
LZOE  
HZOE  
ELQX  
10  
10  
35  
12  
12  
55  
EHQZ  
0
0
0
0
GLQX  
GHQZ  
PU  
ELICCH  
EHICCL  
PD  
Switching Waveforms  
[7, 8]  
Figure 8. SRAM Read Cycle 1: Address Controlled  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
[7]  
Figure 9. SRAM Read Cycle 2: CE and OE Controlled  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
7. WE and HSB must be High during SRAM Read cycles.  
8. Device is continuously selected with CE and OE both Low.  
9. Measured ±200 mV from steady state output voltage.  
Document Number: 001-51026 Rev. **  
Page 9 of 18  
     
STK12C68-5 (SMD5962-94599)  
SRAM Write Cycle  
Parameter  
35 ns  
55 ns  
Description  
Write Cycle Time  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
35  
25  
25  
12  
0
25  
0
0
55  
45  
45  
25  
0
45  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
AVAV  
t
Write Pulse Width  
PWE  
SCE  
SD  
WLWH, WLEH  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
ELWH, ELEH  
t
DVWH, DVEH  
t
HD  
WHDX, EHDX  
t
AW  
AVWH, AVEH  
t
SA  
AVWL, AVEL  
t
HA  
WHAX, EHAX  
[9]  
13  
15  
HZWE  
LZWE  
WLQZ  
WHQX  
5
5
Switching Waveforms  
Figure 10. SRAM Write Cycle 1: WE Controlled  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 11. SRAM Write Cycle 2: CE Controlled  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
11. HSB must be high during SRAM Write cycles.  
12.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-51026 Rev. **  
Page 10 of 18  
     
STK12C68-5 (SMD5962-94599)  
AutoStore or Power Up RECALL  
STK12C68-5  
Unit  
Parameter  
Alt  
Description  
Min  
Max  
t
t
t
Power up RECALL Duration  
STORE Cycle Duration  
550  
μs  
ms  
μs  
t
t
t
RESTORE  
HLHZ  
HRECALL  
10  
STORE  
DELAY  
[9, 15]  
t
Time Allowed to Complete SRAM Cycle  
1
HLQZ , BLQZ  
V
V
t
Low Voltage Trigger Level  
Low Voltage Reset Level  
4.0  
4.5  
3.9  
V
V
SWITCH  
RESET  
V
Rise Time  
150  
μs  
ns  
VCCRISE  
CC  
Low Voltage Trigger (V  
) to HSB Low  
300  
t
SWITCH  
VSBL  
Switching Waveform  
Figure 12. AutoStore/Power Up RECALL  
WE  
Notes  
13. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
14. CE and OE low for output behavior.  
15. CE and OE low and WE high for output behavior.  
16. HSB is asserted low for 1us when V  
takes place.  
drops through V  
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store  
CAP  
SWITCH  
Document Number: 001-51026 Rev. **  
Page 11 of 18  
       
STK12C68-5 (SMD5962-94599)  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows.  
35 ns  
55 ns  
Max  
Parameter  
Alt  
Description  
Unit  
Min  
35  
0
Max  
Min  
55  
0
t
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
ns  
ns  
ns  
ns  
μs  
RC  
AVAV  
AVEL  
ELEH  
ELAX  
SA  
Clock Pulse Width  
25  
20  
30  
20  
CW  
Address Hold Time  
HACE  
RECALL Duration  
20  
20  
RECALL  
Switching Waveform  
Figure 13. CE Controlled Software STORE/RECALL Cycle  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
tSA  
tSCE  
CE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).  
18. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-51026 Rev. **  
Page 12 of 18  
   
STK12C68-5 (SMD5962-94599)  
Hardware STORE Cycle  
STK12C68-5  
Unit  
Parameter  
Alt  
Description  
STORE Cycle Duration  
Min  
Max  
t
t
t
10  
ms  
ns  
t
HLHZ  
STORE  
t
Hardware STORE High to Inhibit Off  
700  
t
t
t
RECOVER, HHQX  
HLHX  
DHSB  
PHSB  
HLBL  
Hardware STORE Pulse Width  
15  
ns  
ns  
Hardware STORE Low to STORE Busy  
300  
Switching Waveform  
Figure 14. Hardware STORE Cycle  
Note  
19. t  
is only applicable after t  
is complete.  
STORE  
DHSB  
Document Number: 001-51026 Rev. **  
Page 13 of 18  
 
STK12C68-5 (SMD5962-94599)  
Part Numbering Nomenclature  
STK12C68 - 5 C 35 M  
Temperature Range:  
M - Military (-55 to 125°C)  
Speed:  
35 - 35 ns  
55 - 55 ns  
Package:  
C = Ceramic 28-pin 300 mil DIP (gold lead finish)  
K = Ceramic 28-pin 300 mil DIP (Solder dip finish)  
L = Ceramic 28-pin LLC  
Retention / Endurance  
5 = Military (10 years or 105 cycles)  
SMD5962 - 94599 01 MX X  
Lead Finish  
A = Solder DIP lead finish  
C = Gold lead DIP finish  
X = Lead finish “A” or “C” is acceptable  
Case Outline  
X = Ceramic 28-pin 300 mil DIP  
Y = Ceramic 28-pin LLC  
Device Class Indicator - Class M  
Device Type:  
01 = 55 ns  
03 = 35 ns  
Document Number: 001-51026 Rev. **  
Page 14 of 18  
STK12C68-5 (SMD5962-94599)  
Ordering Information  
Speed (ns)  
Ordering Code  
Package Diagram  
001-51695  
Package Type  
28-pin CDIP (300 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
28-pin CDIP (300 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
Operating Range  
Military  
35  
STK12C68-5C35M  
STK12C68-5K35M  
STK12C68-5L35M  
STK12C68-5C55M  
STK12C68-5K55M  
STK12C68-5L55M  
001-51695  
001-51696  
55  
001-51695  
001-51695  
001-51696  
The above table contains Final information. Contact your local Cypress sales representative for availability of these parts  
Document Number: 001-51026 Rev. **  
Page 15 of 18  
STK12C68-5 (SMD5962-94599)  
Package Diagrams  
Figure 15. 28-Pin (300-Mil) Side Braze DIL (001-51695)  
001-51695 **  
Document Number: 001-51026 Rev. **  
Page 16 of 18  
STK12C68-5 (SMD5962-94599)  
Package Diagrams (continued)  
Figure 16. 28-Pad (350-Mil) LCC (001-51696)  
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX]  
2. JEDEC 95 OUTLINE# MO-041  
3. PACKAGE WEIGHT : TBD  
001-51696 **  
Document Number: 001-51026 Rev. **  
Page 17 of 18  
STK12C68-5 (SMD5962-94599)  
Document History Page  
Document Title: STK12C68-5 (SMD5962-94599), 64 Kbit (8K x 8) AutoStore nvSRAM  
Document Number: 001-51026  
Orig. of  
Change  
Submission  
Date  
Rev  
ECN No.  
Description of Change  
**  
2666844  
GVCH/PYRS  
03/02/09  
New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-51026 Rev. **  
Revised March 02, 2009  
Page 18 of 18  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  

Gigabyte GA VM800PMC User Manual
GE InfoLink 00018937 User Manual
Fisher Paykel Cooktop CG451D User Manual
DeLonghi Cooktop DE302GB User Manual
Dell UltraSharp 2000FP User Manual
Cuisinart Convection Oven TOB 135 User Manual
Asus P5N E SLI User Manual
Asus Motherboard 90MB0DR0M0AAY0 User Manual
Asus Computer Monitor VH162 User Manual
ASRock Computer Hardware 775i65GV User Manual