STK11C68-5 (SMD5962-92324)
64 Kbit (8K x 8) SoftStore nvSRAM
Features
Functional Description
■ 35 ns, 45 ns, and 55 ns access times
■ Pin compatible with industry standard SRAMs
■ Software initiated nonvolatile STORE
■ Unlimited Read and Write endurance
■ Automatic RECALL to SRAM on power up
■ Unlimited RECALL cycles
The Cypress STK11C68-5 is a 64 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap technology to
produce the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
■ 1,000,000 STORE cycles
■ 100 year data retention
■ Single 5V ± 10% operation
■ Military temperature
■ 28-pin (300 mil) CDIP and 28-pad LCC packages
Logic Block Diagram
V
V
CC
CAP
Quantum Trap
128 X 512
A5
POWER
STORE
CONTROL
A6
A7
RECALL
STORE/
RECALL
STATIC RAM
A8
HSB
ARRAY
128 X 512
CONTROL
A9
A11
A12
SOFTWARE
DETECT
A0
-A12
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
A0
A4
A10
A1
A3
A2
DQ6
DQ7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51001 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 07, 2009
STK11C68-5 (SMD5962-92324)
The software sequence is clocked with CE controlled Reads.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
Read cycles and not Write cycles are used in the sequence. It is
not necessary that OE is LOW for a valid sequence. After the
Device Operation
The STK11C68-5 is a versatile memory chip that provides
several modes of operation. The STK11C68-5 can operate as a
standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements
shadow to which the SRAM information can be copied or from
which the SRAM can be updated in nonvolatile mode.
t
cycle time is fulfilled, the SRAM is again activated for
Read and Write operation.
STORE
Software RECALL
SRAM Read
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
The STK11C68-5 performs a Read cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A
0–12
determines the 8,192 data bytes accessed. When the Read is
initiated by an address transition, the outputs are valid after a
delay of t (Read cycle 1). If the Read is initiated by CE or OE,
AA
the outputs are valid at t
or at t
, whichever is later (Read
ACE
DOE
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
cycle 2). The data outputs repeatedly respond to address
changes within the t access time without the need for
transitions on any control input pins. They remain valid until
another address change or until CE or OE is brought HIGH, or
WE is brought LOW.
AA
SRAM Write
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
A Write cycle is performed whenever CE and WE are LOW. The
address inputs must be stable before entering the Write cycle
and must remain stable until either CE or WE goes HIGH at the
SRAM cells. After the t
cycle time, the SRAM is again
RECALL
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
end of the cycle. The data on the common I/O pins DQ
are
0–7
written into the memory if it has valid t . This is done before the
SD
end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
Hardware RECALL (Power Up)
internal circuitry turns off the output buffers t
LOW.
after WE goes
During power up or after any low power condition (V
<
HZWE
CC
V
), an internal RECALL request is latched. When V
RESET
CC
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
, a RECALL
to complete.
SWITCH
Software STORE
HRECALL
If the STK11C68-5 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C68-5 software
STORE cycle is initiated by executing sequential CE controlled
Read cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
and system V or between CE and system V
.
CC
CC
Hardware Protect
The STK11C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
conditions. When V
operations and SRAM Writes are inhibited.
< V
, all externally initiated STORE
CAP
SWITCH
Noise Considerations
To initiate the software STORE cycle, the following Read
sequence is performed:
The STK11C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
between V and V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
using leads and traces that are as short
CC
SS,
Document Number: 001-51001 Rev. *A
Page 3 of 15
STK11C68-5 (SMD5962-92324)
Figure 4. Current Versus Cycle Time (Write)
Low Average Active Power
CMOS technology provides the STK11C68-5 the benefit of
drawing significantly less current when it is cycled at times longer
between I and Read or Write cycle time. Worst case current
CC
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK11C68-5
depends on the following items:
■ Duty cycle of chip enable
■ Overall cycle rate for accesses
■ Ratio of Reads to Writes
■ CMOS versus TTL input levels
■ Operating temperature
Best Practices
Cypress nvSRAM products have been used effectively for over
15 years. While ease of use is one of the product’s main system
values, the experience gained from working with hundreds of
applications has resulted in the following suggestions as best
practices:
■ V
CC
level
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware must not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration.
■ I/O loading
Figure 3. Current Versus Cycle Time (Read)
■ Cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test. This is to ensure these system routines
work consistently.
Table 1. Hardware Mode Selection
CE
WE
A12–A0
Mode
I/O
Notes
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Nonvolatile STORE
L
H
0x0000
0x1555
0x0AAA
0x1FFF
0x10F0
0x0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Nonvolatile RECALL
Note
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
Document Number: 001-51001 Rev. *A
Page 4 of 15
STK11C68-5 (SMD5962-92324)
Voltage on DQ
...................................–0.5V to Vcc + 0.5V
Maximum Ratings
0-7
Power Dissipation ......................................................... 1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Operating Range
Temperature under bias.............................. –55°C to +125°C
Ambient
Supply Voltage on V Relative to GND ..........–0.5V to 7.0V
Range
Military
V
CC
CC
Temperature
Voltage on Input Relative to Vss............–0.6V to V + 0.5V
CC
-55°C to +125°C
4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (V = 4.5V to 5.5V)
CC
Parameter
Description
Average V Current
Test Conditions
Min
Max
Unit
I
t
t
t
= 35 ns
= 45 ns
= 55 ns
75
65
55
mA
mA
mA
CC1
CC
RC
RC
RC
Dependent on output loading and cycle rate. Values obtained
without output loads. I = 0 mA
OUT
I
I
Average V Current
during STORE
All Inputs Do Not Care, V = Max
3
mA
mA
CC2
CC
CC
Average current for duration t
STORE
Average V Current at
10
WE > (V – 0.2V). All other inputs cycling.
CC3
CC
CC
t
= 200 ns, 5V, 25°C
Dependent on output loading and cycle rate. Values obtained
without output loads.
RC
Typical
V
Standby Current
24
21
20
mA
mA
mA
I
I
t
t
t
= 35 ns, CE > V
= 45 ns, CE > V
= 55 ns, CE > V
CC
SB1
RC
RC
RC
IH
IH
IH
(Standby, Cycling TTL
Input Levels)
V
Standby Current
1500
μA
CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V).
CC
SB2
CC
IN
CC
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz
I
I
Input Leakage Current
V
V
= Max, V < V < V
CC
-1
-5
+1
+5
μA
IX
CC
SS
IN
Off State Output
Leakage Current
μA
= Max, V < V < V , CE or OE > V or WE < V
IL
OZ
CC
SS
IN
CC
IH
V
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
2.2
V
+ 0.5
CC
V
V
V
V
IH
V
– 0.5
SS
0.8
IL
I
I
= –4 mA
= 8 mA
2.4
OH
OL
OUT
0.4
OUT
Data Retention and Endurance
Parameter
Description
Min
Unit
Years
K
DATA
Data Retention
100
R
NV
Nonvolatile STORE Operations
1,000
C
Capacitance
In this table, the capacitance parameters are listed.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
8
Unit
pF
C
T = 25°C, f = 1 MHz,
CC
IN
A
V
= 0 to 3.0V
C
7
pF
OUT
Note
2. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.
IH
3. These parameters are guaranteed by design and are not tested.
Document Number: 001-51001 Rev. *A
Page 5 of 15
STK11C68-5 (SMD5962-92324)
Thermal Resistance
In this table, the thermal resistance parameters are listed.
Parameter
Description
Test Conditions
28-CDIP 28-LCC
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, per EIA /
JESD51.
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Figure 5. AC Test Loads
R1 480Ω
5.0V
Output
R2
30 pF
255Ω
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <5 ns
Input and Output Timing Reference Levels.................... 1.5V
Document Number: 001-51001 Rev. *A
Page 6 of 15
STK11C68-5 (SMD5962-92324)
AC Switching Characteristics
SRAM Read Cycle
Parameter
35 ns
45 ns
55 ns
Description
Unit
Cypress
Parameter
Alt
Min
Max
Min
Max
Min
Max
t
t
Chip Enable Access Time
Read Cycle Time
35
45
55
ns
ns
ACE
ELQV
t
t
35
45
55
t
AVAV,
ELEH
RC
[5]
t
Address Access Time
35
15
45
20
55
35
ns
t
t
AVQV
AA
t
t
Output Enable to Data Valid
ns
ns
DOE
OHA
GLQV
AXQX
Output Hold After Address Change
5
5
5
5
5
5
t
t
t
t
t
t
t
[6]
[6]
t
t
t
t
t
t
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
ns
ns
ns
ns
ns
ns
ELQX
LZCE
HZCE
LZOE
HZOE
13
13
35
15
15
45
25
25
55
EHQZ
0
0
0
0
0
0
GLQX
GHQZ
ELICCH
EHICCL
PU
PD
Switching Waveforms
Figure 6. SRAM Read Cycle 1: Address Controlled
W5&
$''5(66
W$$
W2+$
'4ꢌꢊ'$7$ꢌ287ꢋ
'$7$ꢌ9$/,'
[4]
Figure 7. SRAM Read Cycle 2: CE and OE Controlled
W5&
$''5(66
&(
W$&(
W3'
W+=&(
W/=&(
2(
W+=2(
W'2(
W/=2(
'4ꢌꢊ'$7$ꢌ287ꢋ
'$7$ꢌ9$/,'
$&7,9(
W38
67$1'%<
,&&
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < V and WE > V ; device is continuously selected.
IL
IH
6. Measured ± 200 mV from steady state output voltage.
Document Number: 001-51001 Rev. *A
Page 7 of 15
STK11C68-5 (SMD5962-92324)
SRAM Write Cycle
Parameter
35 ns
45 ns
55 ns
Description
Write Cycle Time
Unit
Cypress
Alt
Min
Max
Min
Max
Min
Max
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
35
25
25
12
0
45
30
30
15
0
55
45
45
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
PWE
SCE
SD
AVAV
t
Write Pulse Width
WLWH, WLEH
t
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
ELWH, ELEH
t
DVWH, DVEH
t
HD
WHDX, EHDX
t
25
0
30
0
45
0
AW
SA
AVWH, AVEH
t
AVWL, AVEL
t
0
0
0
HA
WHAX, EHAX
[6]
13
15
35
t
t
WLQZ
WHQX
HZWE
LZWE
t
Output Active After End of Write
5
5
5
ns
Switching Waveforms
Figure 8. SRAM Write Cycle 1: WE Controlled
tWC
ADDRESS
CE
tHA
tSCE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
Figure 9. SRAM Write Cycle 2: CE and OE Controlled
tWC
ADDRESS
tHA
tSCE
tSA
CE
WE
tAW
tPWE
tSD
tHD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8.
CE or WE must be greater than V during address transitions.
IH
Document Number: 001-51001 Rev. *A
Page 8 of 15
STK11C68-5 (SMD5962-92324)
AutoStore INHIBIT or Power Up RECALL
STK11C68-5
Unit
Parameter
Alt
Description
Power up RECALL Duration
Min
Max
t
t
550
μs
t
t
RESTORE
HRECALL
STORE Cycle Duration
Low Voltage Trigger Level
Low Voltage Reset Level
10
4.5
3.6
ms
V
STORE
HLHZ
V
V
4.0
SWITCH
V
RESET
Figure 10. AutoStore INHIBIT/Power Up RECALL
VCC
5V
VSWITCH
VRESET
STORE INHIBIT
POWER-UP RECALL
t
HRECALL
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
RESET
RESET
SWITCH
Notes
9.
t
starts from the time V rises above V
.
SWITCH
HRECALL
CC
Document Number: 001-51001 Rev. *A
Page 9 of 15
STK11C68-5 (SMD5962-92324)
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
35 ns
45 ns
Max
55 ns
Max
Parameter
Alt
Description
Unit
Min
Max
Min
45
0
Min
55
0
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Setup Time
35
0
ns
ns
RC
AVAV
AVEL
SA
CW
t
t
Clock Pulse Width
Address Hold Time
RECALL Duration
25
20
30
20
35
20
ns
ns
μs
ELEH
ELAX
HACE
20
20
20
RECALL
Switching Waveform
Figure 11. CE Controlled Software STORE/RECALL Cycle
tRC
tRC
ADDRESS # 1
ADDRESS # 6
ADDRESS
tSA
tSCE
CE
tHACE
OE
t
STORE / tRECALL
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA)
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51001 Rev. *A
Page 10 of 15
STK11C68-5 (SMD5962-92324)
Part Numbering Nomenclature
STK11C68 - 5 C 45 M
Temperature Range:
M - Military (-55 to 125°C)
Speed:
35 - 35 ns
45 - 45 ns
55 - 55 ns
Package:
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (Solder dip finish)
L = Ceramic 28-pin LLC
Retention / Endurance
5 = Military (10 years or 105 cycles)
SMD5962-92324 04 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Case Outline
X = Ceramic 28-pin 300 mil DIP
Y = Ceramic 28-pin LLC
Device Class Indicator - Class M
Device Type:
04 = 55 ns
05 = 45 ns
06 = 35 ns
Document Number: 001-51001 Rev. *A
Page 11 of 15
STK11C68-5 (SMD5962-92324)
Ordering Information
Speed (ns)
Ordering Code
Package Diagram
001-51695
001-51695
001-51696
001-51695
001-51695
001-51696
001-51695
001-51695
001-51696
Package Type
28-Pin CDIP (300 mil)
28-Pin CDIP (300 mil)
28-Pin LCC (350 mil)
28-Pin CDIP (300 mil)
28-Pin CDIP (300 mil)
28-Pin LCC (350 mil)
28-Pin CDIP (300 mil)
28-Pin CDIP (300 mil)
28-Pin LCC (350 mil)
Operating Range
35
STK11C68-5C35M
STK11C68-5K35M
STK11C68-5L35M
STK11C68-5C45M
STK11C68-5K45M
STK11C68-5L45M
STK11C68-5C55M
STK11C68-5K55M
STK11C68-5L55M
Military
45
55
This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Document Number: 001-51001 Rev. *A
Page 12 of 15
STK11C68-5 (SMD5962-92324)
Package Diagrams
Figure 12. 28-Pin (300-Mil) Side Braze DIL (001-51695)
001-51695 **
Document Number: 001-51001 Rev. *A
Page 13 of 15
STK11C68-5 (SMD5962-92324)
Package Diagrams (continued)
Figure 13. 28-Pad (350-Mil) LCC (001-51696)
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX]
2. JEDEC 95 OUTLINE# MO-041
3. PACKAGE WEIGHT : TBD
001-51696 **
Document Number: 001-51001 Rev. *A
Page 14 of 15
STK11C68-5 (SMD5962-92324)
Document History Page
Document Title: STK11C68-5 (SMD5962-92324) 64 Kbit (8K x 8) SoftStore nvSRAM
Document Number: 001-51001
Submission
Rev.
ECN No. Orig. of Change
Description of Change
Date
**
2666844
2685053
GVCH/PYRS
GVCH
03/02/09
New data sheet
*A
04/07/2009 Added part numbers: STK11C68-5K45M and STK11C68-5K55M
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51001 Rev. *A
Revised April 07, 2009
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AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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