Cypress Perform STK14D88 User Manual

STK14D88  
32Kx8 AutoStore™ nvSRAM  
Features  
Description  
25, 35, 45 ns Read Access and R/W Cycle Time  
Unlimited Read/Write Endurance  
The Cypress STK14D88 is a 256Kb fast static RAM with a  
nonvolatile Quantum Trap™ storage element included with each  
memory cell.  
Automatic Nonvolatile STORE on Power Loss  
Nonvolatile STORE Under Hardware or Software Control  
Automatic RECALL to SRAM on Power Up  
Unlimited RECALL Cycles  
The SRAM provides fast access and cycle times, ease of use,  
and unlimited read and write endurance of a normal SRAM.  
Data transfers automatically to the nonvolatile storage cells  
when power loss is detected (the STORE operation). On power  
up, data is automatically restored to the SRAM (the RECALL  
operation). Both STORE and RECALL operations are also  
available under software control.  
200K STORE Cycles  
20-Year Nonvolatile Data Retention  
The Cypress nvSRAM is the first monolithic nonvolatile memory  
to offer unlimited writes and reads. It is the highest performance,  
most reliable nonvolatile memory available.  
Single 3.0V +20%, -10% Power Supply  
Commercial, Industrial Temperatures  
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)  
Logic Block Diagram  
V
V
CAP  
CCX  
Quantum Trap  
512 x 512  
POWER  
CONTROL  
A
A
A
A
A
A
A
A
A
5
STORE  
6
7
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 x 512  
8
HSB  
RECALL  
9
11  
12  
13  
14  
SOFTWARE  
DETECT  
A - A  
0
13  
DQ  
DQ  
DQ  
0
1
2
COLUMN I/O  
COLUMN DEC  
DQ  
DQ  
3
4
DQ  
DQ  
DQ  
5
6
7
A A A A A A  
10  
0
1
2
3
4
G
E
W
Cypress Semiconductor Corporation  
Document Number: 001-52037 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2009  
STK14D88  
Absolute Maximum Ratings  
Voltage on Input Relative to Ground.................–0.5V to 4.1V  
Note: Stresses greater than those listed under “Absolute  
Maximum Ratings” may cause permanent damage to the device.  
This is a stress rating only, and functional operation of the device  
at conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
reliability.  
Voltage on Input Relative to VSS...........–0.6V to (V + 0.5V)  
CC  
Voltage on DQ0-7 or HSB......................–0.5V to (V + 0.5V)  
CC  
Temperature under Bias ............................... –55°C to 125°C  
Storage Temperature.................................... –65°C to 140°C  
Power Dissipation............................................................. 1W  
DC Output Current (1 output at a time, 1s duration)..... 15mA  
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS  
θ 5.4 C/W; θ 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].  
jc  
ja  
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS  
θ 6.2 C/W; θ 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].  
jc  
ja  
DC Characteristics  
(V = 2.7V-3.6V)  
CC  
Commercial  
Min Max  
Industrial  
Symbol  
Parameter  
Average V Current  
Unit  
Notes  
Min  
Max  
I
65  
55  
50  
70  
60  
55  
mA  
mA  
mA  
t
t
t
= 25ns  
= 35ns  
= 45ns  
CC  
CC  
AVAV  
AVAV  
AVAV  
1
Dependent on output loading and  
cycle rate. Values obtained without  
output loads.  
I
I
Average V Current during  
STORE  
3
3
mA All Inputs Don’t Care, V = max  
CC  
CC  
CC  
2
3
Average current for duration of  
STORE cycle (t  
)
STORE  
Average V Current at t  
=
10  
10  
mA W (V – 0.2V)  
CC  
CC  
CC  
AVAV  
200ns  
3V, 25°C, Typical  
All Others Cycling, CMOS Levels  
Dependent on output loading and  
cycle rate. Values obtained without  
output loads.  
I
I
Average V  
AutoStore Cycle  
Current during  
3
3
3
3
mA All Inputs Don’t Care  
CC  
CAP  
4
Average current for duration of  
STORE cycle (t  
)
STORE  
V
Standby Current  
mA E (V – 0.2V)  
CC  
SB  
CC  
(Standby, Stable CMOS Input  
Levels)  
All Others V 0.2V or (V  
IN  
CC  
0.2V)  
Standby current level after nonvol-  
atile cycle complete  
I
I
Input Leakage Current  
±1  
±1  
μA  
V
= max  
CC  
ILK  
V
= V to V  
IN  
SS  
CC  
Off-State Output Leakage Current  
±1  
±1  
μA  
V = max  
CC  
OLK  
V
= V to V , E or G V  
IN  
SS  
CC  
IH  
V
V
V
Input Logic “1” Voltage  
Input Logic “0” Voltage  
Output Logic “1” Voltage  
2.0  
– .5  
V
+ .5  
2.0  
V + .5  
CC  
V
V
V
All Inputs  
All Inputs  
IH  
CC  
V
0.8  
V – .5  
SS  
0.8  
IL  
SS  
2.4  
2.4  
I
=– 2mA  
OUT  
OH  
Note:  
2. The HSB pin has I  
=-10uA for V of 2.4V, this parameter is characterized but not tested  
OH  
OUT  
Document Number: 001-52037 Rev. **  
Page 3 of 17  
 
STK14D88  
DC Characteristics (continued)  
(V = 2.7V-3.6V)  
CC  
Commercial  
Min Max  
Industrial  
[2]  
Symbol  
Parameter  
Unit  
Notes  
Min  
Max  
V
T
Output Logic “0” Voltage  
Operating Temperature  
Operating Voltage  
0.4  
70  
0.4  
85  
V
°C  
V
I
= 4mA  
OUT  
OL  
0
-40  
2.7  
17  
A
V
2.7  
17  
3.6  
120  
3.6  
120  
3.3V +20%, -10%  
CC  
V
Storage Capacitance  
μF Between V  
pin and V , 5V  
CAP  
CAP SS  
Rated  
DATA  
Data Retention  
20  
20  
K
R
NV  
Nonvolatile STORE Operations  
200  
200  
Years @ 55°C  
C
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times ............................................ <5 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Output Load..................................See Figure 2 and Figure 3  
Figure 2. AC Output Loading  
3.0V  
577Ω  
OUTPUT  
30 pF  
789Ω  
INCLUDING  
SCOPE AND  
FIXTURE  
Figure 3. AC Output Loading for Tri-state Specs (t , t , t  
, t  
, t  
, t  
HZ LZ WLQZ WHQZ GLQX GHQZ  
3.0V  
577  
Ω
OUTPUT  
5 pF  
789  
Ω
INCLUDING  
SCOPE AND  
FIXTURE  
Capacitance  
[3]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
7
Unit  
pF  
Conditions  
ΔV = 0 to 3V  
ΔV = 0 to 3V  
C
IN  
A
C
7
pF  
OUT  
Note  
3. These parameters are guaranteed but not tested.  
Document Number: 001-52037 Rev. **  
Page 4 of 17  
     
STK14D88  
SRAM READ Cycles #1 and #2  
Symbols  
NO.  
STK14D88-25 STK14D88-35 STK14D88-45  
Parameter  
Unit  
#1  
#2  
Alt.  
Min  
Max  
Min  
Max  
Min  
Max  
1
2
3
4
5
6
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
t
t
t
25  
35  
45  
AVAV  
ELEH  
[5]  
AVQV  
RC  
AA  
OE  
OH  
LZ  
t
Address Access Time  
25  
12  
35  
15  
45  
20  
AVQV  
t
t
t
Output Enable to Data Valid  
Output Hold after Address Change  
GLQV  
AXQX  
ELQX  
[5]  
[6]  
t
3
3
3
3
3
3
AXQX  
Address Change or Chip Enable to  
Output Active  
7
t
t
Address Change or Chip Disable to  
Output Inactive  
10  
13  
15  
ns  
EHQZ  
HZ  
8
9
t
t
t
t
t
t
t
t
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
0
0
0
0
0
0
ns  
ns  
ns  
ns  
GLQX  
OLZ  
OHZ  
PA  
10  
25  
13  
35  
15  
45  
GHQZ  
10  
11  
ELICCH  
EHICCL  
PS  
Figure 4. SRAM READ Cycle 1: Address Controlled  
AVAV  
t
ADDRESS  
AVQV  
t
AXQX  
t
DQ (DATA OUT)  
DATA VALID  
Figure 5. SRAM READ Cycle 2: E Controlled  
Notes  
4. W must be high during SRAM READ cycles.  
5. Device is continuously selected with E and G both low.  
6. Measured ± 200mV from steady state output voltage.  
7. HSB must remain high during READ and WRITE cycles.  
Document Number: 001-52037 Rev. **  
Page 5 of 17  
                             
STK14D88  
SRAM WRITE Cycle #1 and #2  
Symbols  
NO.  
STK14D88-25 STK14D88-35 STK14D88-45  
Parameter  
Write Cycle Time  
Unit  
#1  
#2  
Alt.  
Min  
25  
20  
20  
10  
0
Max  
Min  
35  
25  
25  
12  
0
Max  
Min  
45  
30  
30  
15  
0
Max  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
t
t
t
WC  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVAV  
AVAV  
t
t
t
Write Pulse Width  
WLWH  
WLEH  
WP  
CW  
DW  
t
t
t
t
Chip Enable to End of Write  
Data Set-up to End of Write  
Data Hold after End of Write  
Address Set-up to End of Write  
Address Set-up to Start of Write  
Address Hold after End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
ELWH  
DVWH  
WHDX  
ELEH  
DVEH  
EHDX  
t
t
t
t
t
DH  
AW  
t
t
t
20  
0
25  
0
30  
0
AVWH  
AVEH  
t
t
t
AS  
AVWL  
AVEL  
t
t
t
0
0
0
WHAX  
WLQZ  
EHAX  
WR  
t
t
10  
13  
15  
WZ  
t
t
3
3
3
WHQX  
OW  
Figure 6. SRAM WRITE Cycle 1: W Controlled  
AVAV  
t
ADDRESS  
WHAX  
ELWH  
t
t
E
AVWH  
t
AVWL  
t
WLWH  
t
W
DVWH  
WHDX  
t
t
DATA IN  
DATA VALID  
WLQZ  
t
WHQX  
t
HIGH IMPEDANCE  
DATA OUT  
PREVIOUS DATA  
Figure 7. SRAM WRITE Cycle 2: E Controlled  
AVAV  
t
ADDRESS  
E
AVEL  
ELEH  
EHAX  
t
t
t
AVEH  
t
WLEH  
t
W
DVEH  
EHDX  
t
t
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
8. If W is low when E goes low, the outputs remain in the high-impedance state.  
9. E or W must be V during address transitions.  
IH  
Document Number: 001-52037 Rev. **  
Page 6 of 17  
                       
STK14D88  
AutoStore/POWER UP RECALL  
STK14D88  
No. Symbols  
Alt.  
Parameter  
Unit  
Notes  
Min  
Max  
20  
22  
23  
24  
25  
t
t
Power up RECALL Duration  
STORE Cycle Duration  
Low Voltage Trigger Level  
Vcc Rise Time  
ms  
ms  
V
RECALL  
STORE  
t
12.5  
2.65  
HLHZ  
V
V
SWITCH  
CCRISE  
150  
μs  
Figure 8. AutoStore /POWER UP RECALL  
Note: Read and Write cycles are ignored during STORE, RECALL, and while V is below V  
CC  
SWITCH  
Notes  
10. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.  
12. Industrial Grade Devices require 15 ms Max.  
Document Number: 001-52037 Rev. **  
Page 7 of 17  
         
STK14D88  
Software-Controlled STORE/RECALL Cycle  
Symbols  
No.  
STK14D88-25 STK14D88-35 STK14D88-45  
Parameter  
Alternate  
Unit Notes  
E Cont  
Min  
Max  
Min  
Max  
Min  
Max  
26 t  
t
t
STORE/RECALL Initiation Cycle Time  
25  
0
35  
0
45  
0
ns  
ns  
AVAV  
RC  
27  
28  
29  
30  
Address Setup Time  
Clock Pulse Width  
Address Hold Time  
RECALL Duration  
t
t
t
t
AS  
AVEL  
t
20  
1
25  
1
30  
1
ns  
ns  
μs  
CW  
ELEH  
EHAX  
RECALL  
50  
50  
50  
Figure 9. E and G Controlled Software STORE/RECALL Cycle  
AVAV  
t
AVAV  
t
ADDRESS #1  
ADDRESS #6  
ADDRESS  
AVEL  
t
ELEH  
t
E
ELAX  
t
RECALL  
tSTORE / t  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA  
Notes  
13. The software sequence is clocked on the falling edge of E controlled READs.  
14. The six consecutive addresses must be read in the order listed in the software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.  
Document Number: 001-52037 Rev. **  
Page 8 of 17  
             
STK14D88  
Hardware STORE Cycle  
Symbols  
NO.  
STK14D88  
Parameter  
Unit  
Notes  
Standard Alternate  
Min  
Max  
31  
32  
t
t
t
Hardware STORE to SRAM Disabled  
Hardware STORE Pulse Width  
1
70  
µs  
ns  
DELAY  
HLHX  
HLQZ  
15  
Figure 10. Hardware STORE Cycle  
Soft Sequence Commands  
Symbols  
STK14D88  
NO.  
Parameter  
Min  
Unit  
µs  
Notes  
Standard  
Max  
33  
t
Soft Sequence Processing Time  
70  
SS  
Figure 11. Software Sequence Commands  
Notes  
15. Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete.  
16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.  
17. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.  
Document Number: 001-52037 Rev. **  
Page 9 of 17  
           
STK14D88  
Notes  
Mode Selection  
E
H
L
W
X
H
L
G
X
L
A
–A  
Mode  
IO  
Power  
Standby  
Active  
14  
0
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
X
X
L
X
L
Active  
L
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x03F8  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
AutoStore Disable  
L
L
H
H
L
L
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x07F0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
AutoStore Enable  
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
0x0FC0  
Nonvolatile Store  
Output High Z  
I
CC2  
L
H
L
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
Nonvolatile Recall  
Notes  
18. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.  
19. While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes  
20. I/O state depends on the state of G. The I/O table shown assumes G low.  
Document Number: 001-52037 Rev. **  
Page 10 of 17  
     
STK14D88  
V
pin is driven to 5V by a charge pump internal to the chip. A  
nvSRAM Operation  
CAP  
pull up should be placed on W to hold it inactive during power up.  
nvSRAM  
To reduce unneeded nonvolatile stores, AutoStore and  
Hardware Store operations will be ignored unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. The HSB signal can be monitored by the system to detect  
an AutoStore cycle is in progress.  
The STK14D88 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are the SRAM  
memory cell and a nonvolatile QuantumTrap™ cell. The SRAM  
memory cell operates like a standard fast static RAM. Data in the  
SRAM can be transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture allows all cells to be stored  
and recalled in parallel. During the STORE and RECALL opera-  
tions SRAM READ and WRITE operations are inhibited. The  
STK14D88 supports unlimited read and writes like a typical  
SRAM. In addition, it provides unlimited RECALL operations  
from the nonvolatile cells and up to 200K STORE operations.  
Figure 12. AutoStore Mode  
VCC  
VCAP  
VCC  
SRAM READ  
W
The STK14D88 performs a READ cycle whenever E and G are  
low while W and HSB are high. The address specified on pins  
A
determine which of the 32,768 data bytes will be accessed.  
0-16  
When the READ is initiated by an address transition, the outputs  
will be valid after a delay of t (READ cycle #1). If the READ  
AVQV  
is initiated by E and G, the outputs will be valid at t  
or at  
ELQV  
t
, whichever is later (READ cycle #2). The data outputs will  
GLQV  
repeatedly respond to address changes within the t  
access  
AVQV  
time without the need for transitions on any control input pins,  
and will remain valid until another address change or until either  
E or G is brought high, or W or HSB is brought low.  
Hardware STORE (HSB) Operation  
SRAM WRITE  
The STK14D88 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin can be  
used to request a hardware STORE cycle. When the HSB pin is  
driven low, the STK14D88 will conditionally initiate a STORE  
A WRITE cycle is performed whenever E and W are low and HSB  
is high. The address inputs must be stable prior to entering the  
WRITE cycle and must remain stable until either E or W goes  
high at the end of the cycle. The data on the common I/O pins  
operation after t  
. An actual STORE cycle will only begin if  
DELAY  
DQ will be written into memory if it is valid t  
before the  
0-7  
DVWH  
a WRITE to the SRAM took place since the last STORE or  
RECALL cycle. The HSB pin has a very resistive pull up and is  
internally driven low to indicate a busy condition while the  
STORE (initiated by any means) is in progress. This pin should  
be externally pulled up if it is used to drive other inputs.  
end of a W controlled WRITE or t  
controlled WRITE.  
before the end of an E  
DVEH  
It is recommended that G be kept high during the entire WRITE  
cycle to avoid data bus contention on common I/O lines. If G is  
left low, internal circuitry will turn off the output buffers t  
after  
WLQZ  
SRAM READ and WRITE operations that are in progress when  
HSB is driven low by any means are given time to complete  
before the STORE operation is initiated. After HSB goes low, the  
goes low.  
W
AutoStore Operation  
STK14D88 will continue SRAM operations for t  
. During  
DELAY  
The STK14D88 stores data to nvSRAM using one of three  
storage operations. These three operations are Hardware Store  
(activated by HSB), Software Store (activated by an address  
sequence), and AutoStore (on power down).  
t
, multiple SRAM READ operations may take place. If a  
DELAY  
WRITE is in progress when HSB is pulled low, it will be allowed  
a time, t , to complete. However, any SRAM WRITE cycles  
DELAY  
requested after HSB goes low will be inhibited until HSB returns  
high.  
AutoStore operation is a unique feature of Cypress Quantum  
Trap technology is enabled by default on the STK14D88.  
If HSB is not used, it should be left unconnected.  
CC  
Software STORE  
charge will be used by the chip to perform a single STORE  
operation. If the voltage on the V pin drops below VSWITCH,  
Data can be transferred from the SRAM to the nonvolatile  
memory by a software address sequence. The STK14D88  
software STORE cycle is initiated by executing sequential E  
controlled READ cycles from six specific address locations in  
exact order. During the STORE cycle, previous data is erased  
and then the new data is programmed into the nonvolatile  
elements. Once a STORE cycle is initiated, further memory  
inputs and outputs are disabled until the cycle is completed.  
CC  
the part will automatically disconnect the V  
pin from V . A  
CAP  
CC  
STORE operation will be initiated with power provided by the  
capacitor.  
V
CAP  
Figure 12 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. Refer to the DC CHARAC-  
CAP  
TERISTICS table for the size of the capacitor. The voltage on the  
Document Number: 001-52037 Rev. **  
Page 11 of 17  
 
STK14D88  
To initiate the software STORE cycle, the following READ  
sequence must be performed:  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites willsometimes reprogram these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
End product’s firmware should not assume an NV array is in a  
set programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, etc. should always program a unique NV  
pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or  
more random bytes) as part of the final system manufacturing  
test to ensure these system routines work consistently.  
1. Read Address 0x0E38, Valid READ  
2. Read Address 0x31C7, Valid READ  
3. Read Address 0x03E0, Valid READ  
4. Read Address 0x3C1F, Valid READ  
5. Read Address 0x303F, Valid READ  
6. Read Address 0x0FC0, Initiate STORE Cycle  
Once the sixth address in the sequence has been entered, the  
STORE cycle will commence and the chip will be disabled. It is  
important that READ cycles and not WRITE cycles be used in  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state (autostore enabled, etc.). While the  
nvSRAM is shipped in a preset state, best practice is to again  
rewrite the nvSRAM into the desired state as a safeguard  
against events that might flip the bit inadvertently (program  
bugs, incoming inspection routines, etc.).  
the sequence. After the t  
cycle time has been fulfilled, the  
STORE  
SRAM will again be activated for READ and WRITE operation.  
Software RECALL  
Data can be transferred from the nonvolatile memory to the  
SRAM by a software address sequence. A software RECALL  
cycle is initiated with a sequence of READ operations in a  
manner similar to the software STORE initiation. To initiate the  
RECALL cycle, the following sequence of E controlled READ  
operations must be performed:  
If AutoStore has been firmware disabled, it will not reset to  
“autostore enabled” on every power down event captured by  
the nvSRAM. The application firmware should re-enable or  
re-disable autostore on each reset sequence based on the  
behavior desired.  
1. Read Address 0x0E38, Valid READ  
2. Read Address 0x31C7, Valid READ  
3. Read Address 0x03E0, Valid READ  
4. Read Address 0x3C1F, Valid READ  
5. Read Address 0x303F, Valid READ  
6. Read Address 0x0C63, Initiate RECALL Cycle  
TheV  
valuespecifiedinthisdatasheetincludesaminimum  
CAP  
and a maximum value size. Best practice is to meet this  
requirement and not exceed the max V  
nvSRAM internal algorithm calculates V  
value because the  
charge time based  
CAP  
CAP  
on this max V  
value. Customers that want to use a larger  
CAP  
V
value to make sure there is extra store charge and store  
CAP  
time should discuss their V  
size selection with Cypress to  
CAP  
Internally, RECALL is a two-step procedure. First, the SRAM  
data is cleared, and second, the nonvolatile information is trans-  
understand any impact on the V  
voltage level at the end of  
CAP  
a t  
period.  
RECALL  
ferred into the SRAM cells. After the t  
cycle time, the  
RECALL  
Low Average Active Power  
SRAM will once again be ready for READ or WRITE operations.  
The RECALL operation in no way alters the data in the nonvol-  
atile storage elements.  
CMOS technology provides the STK14D88 with the benefit of  
power supply current that scales with cycle time. Less current will  
be drawn as the memory cycle time becomes longer than 50 ns.  
Data Protection  
Figure 13 shows the relationship between  
I
and  
CC  
The STK14D88 protects data from corruption during low-voltage  
conditions by inhibiting all externally initiated STORE and  
WRITE operations. The low-voltage condition is detected when  
READ/WRITE cycle time. Worst-case current consumption is  
shown for commercial temperature range, V = 3.6V, and chip  
CC  
enable at maximum frequency. Only standby current is drawn  
when the chip is disabled. The overall average current drawn by  
the STK14D88 depends on the following items:  
V
<V  
.
CC  
SWITCH  
If the STK14D88 is in a WRITE mode (both E and W low) at  
power-up, after a RECALL, or after a STORE, the WRITE will be  
inhibited until a negative transition on E or W is detected. This  
protects against inadvertent writes during power up or brown out  
conditions.  
The duty cycle of chip enable  
The overall cycle rate for operations  
The ratio of READs to WRITEs  
The operating temperature  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease-of-use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
The V level  
CC  
I/O loading  
Document Number: 001-52037 Rev. **  
Page 12 of 17  
STK14D88  
Figure 13. Current versus Cycle Time  
Preventing AutoStore  
The AutoStore function can be disabled by initiating an  
AutoStore Disable sequence. A sequence of READ operations  
is performed in a manner similar to the software STORE initi-  
ation. To initiate the AutoStore Disable sequence, the following  
sequence of E controlled or G controlled READ operations must  
be performed:  
50  
40  
30  
20  
10  
0
1. Read Address 0x0E38, Valid READ  
2. Read Address 0x31C7, Valid READ  
3. Read Address 0x03E0, Valid READ  
4. Read Address 0x3C1F, Valid READ  
5. Read Address 0x303F, Valid READ  
6. Read Address 0x03F8, AutoStore Disable  
Writes  
Reads  
The AutoStore can be re-enabled by initiating an AutoStore  
Enable sequence. A sequence of READ operations is performed  
in a manner similar to the software RECALL initiation. To initiate  
the AutoStore Enable sequence, the following sequence of E  
controlled or G controlled READ operations must be performed:  
50 100 150 200 300  
Cycle Time (ns)  
1. Read Address 0x0E38, Valid READ  
2. Read Address 0x31C7, Valid READ  
3. Read Address 0x03E0, Valid READ  
4. Read Address 0x3C1F, Valid READ  
5. Read Address 0x303F, Valid READ  
6. Read Address 0x07F0, AutoStore Enable  
Noise Considerations  
The STK14D88 is a high-speed memory and so must have a  
high-frequency bypass capacitor of 0.1 µF connected between  
both V pins and V ground plane with no plane break to chip  
CC  
SS  
V
. Use leads and traces that are as short as possible. As with  
SS  
all high-speed CMOS ICs, careful routing of power, ground, and  
signals will reduce circuit noise.  
If the AutoStore function is disabled or re-enabled, a manual  
STORE operation (Hardware or Software) needs to be issued to  
save the AutoStore state through subsequent power down  
cycles. The part comes from the factory with AutoStore enabled.  
In all cases, make sure the READ sequence is uninterrupted. For  
example, an interrupt that occurs in the sequence that reads the  
nvSRAM would abort this sequence, resulting in an error.  
Document Number: 001-52037 Rev. **  
Page 13 of 17  
 
STK14D88  
Part Numbering Nomenclature  
STK14D88 - R F 45 I TR  
Packaging Option:  
TR = Tape and Reel  
Blank = Tube  
Temperature Range:  
Blank - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
25 - 25 ns  
35 - 35 ns  
45 - 45 ns  
Lead Finish  
F = 100% Sn (Matte Tin) ROHS Compliant  
Package:  
N = Plastic 32-pin 300 mil SOIC (50 mil pitch)  
R = Plastic 48-pin 300 mil SSOP(25 mil pitch)  
Ordering Codes  
Part Number  
Description  
Access Times Temperature  
STK14D88-NF25  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SOP32-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
3V 32Kx8 AutoStore nvSRAM SSOP48-300  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
25 ns  
35 ns  
45 ns  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
STK14D88-NF35  
STK14D88-NF45  
STK14D88-NF25TR  
STK14D88-NF35TR  
STK14D88-NF45TR  
STK14D88-RF25  
STK14D88-RF35  
STK14D88-RF45  
STK14D88-RF25TR  
STK14D88-RF35TR  
STK14D88-RF45TR  
STK14D88-NF25I  
STK14D88-NF35I  
STK14D88-NF45I  
STK14D88-NF25ITR  
STK14D88-NF35ITR  
STK14D88-NF45ITR  
STK14D88-RF25I  
STK14D88-RF35I  
STK14D88-RF45I  
STK14D88-RF25ITR  
STK14D88-RF35ITR  
STK14D88-RF45ITR  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Document Number: 001-52037 Rev. **  
Page 14 of 17  
STK14D88  
Package Diagrams  
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)  
PIN 1 ID  
16  
1
MIN.  
MAX.  
DIMENSIONS IN INCHES[MM]  
REFERENCE JEDEC MO-119  
0.292[7.416]  
0.299[7.594]  
0.405[10.287]  
0.419[10.642]  
PART #  
17  
32  
S32.3 STANDARD PKG.  
SZ32.3 LEAD FREE PKG.  
SEATING PLANE  
0.810[20.574]  
0.822[20.878]  
0.090[2.286]  
0.100[2.540]  
0.004[0.101]  
0.050[1.270]  
TYP.  
0.006[0.152]  
0.012[0.304]  
0.026[0.660]  
0.032[0.812]  
0.021[0.533]  
0.041[1.041]  
0.004[0.101]  
0.0100[0.254]  
0.014[0.355]  
0.020[0.508]  
51-85127 *A  
Document Number: 001-52037 Rev. **  
Page 15 of 17  
 
STK14D88  
Package Diagrams (continued)  
Figure 15. 48-Pin (300 Mil) SSOP (51-85061)  
51-85061-*C  
Document Number: 001-52037 Rev. **  
Page 16 of 17  
STK14D88  
Document History Page  
Document Title: STK14D88 32Kx8 AutoStore™ nvSRAM  
Document Number: 001-52037  
Orig. of Submission  
Revision  
ECN  
Description of Change  
Change  
Date  
**  
2668632  
GVCH  
03/04/2009 New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
psoc.cypress.com/solutions  
psoc.cypress.com/low-power  
psoc.cypress.com/precision-analog  
psoc.cypress.com/lcd-drive  
psoc.cypress.com/can  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
psoc.cypress.com/usb  
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-52037 Rev. **  
Revised March 02, 2009  
Page 17 of 17  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  

Gigabyte GA M61PME S2P User Manual
GE 17 Feb User Manual
Fujitsu Computer Hardware C122 E177 01EN User Manual
Dell 1708FP BLK User Manual
Dell 66M2N User Manual
DCS CT 304SS User Manual
COBY electronic CT P8800 User Manual
BenQ Computer Monitor G920WL User Manual
AT T Corded Phone 210WH User Manual
Asus LCD Monitor PQ321Q User Manual