Cypress Perform CY7C1372D User Manual

CY7C1370D  
CY7C1372D  
18-Mbit (512K x 36/1M x 18) Pipelined  
SRAM with NoBL™ Architecture  
Features  
Functional Description  
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200 and 167 MHz  
1M x 18 Synchronous pipelined burst SRAMs with No Bus  
Latency™ (NoBL™) logic, respectively. They are designed to  
support unlimited true back-to-back Read/Write operations  
with no wait states. The CY7C1370D and CY7C1372D are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
Write/Read transitions. The CY7C1370D and CY7C1372D are  
pin compatible and functionally equivalent to ZBT devices.  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• 3.3V core power supply (V  
)
DD  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• 3.3V/2.5V I/O power supply(V  
• Fast clock-to-output times  
)
DDQ  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
(BW –BW for CY7C1370D and BW –BW for CY7C1372D)  
and a Write Enable (WE) input. All writes are conducted with  
on-chip synchronous self-timed write circuitry.  
a
d
a
b
• Available in JEDEC-standard lead-free 100-pin TQFP,  
lead-free and non-lead-free 119-Ball BGA and 165-Ball  
FBGA package  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram-CY7C1370D (512K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
BWa  
BWb  
BWc  
BWd  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
WRITE  
DRIVERS  
DQPa  
DQPb  
DQPc  
DQPd  
A
M
P
S
T
E
R
S
F
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05555 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 28, 2006  
CY7C1370D  
CY7C1372D  
Pin Configurations  
100-pin TQFP Pinout  
DQPc  
DQc  
DQc  
1
2
3
4
5
6
7
8
NC  
NC  
NC  
DDQ  
1
2
3
4
5
6
7
8
A
NC  
NC  
78  
DQPb  
DQb  
DQb  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
80  
79  
V
V
DDQ  
V
V
V
NC  
DQPa  
DQa  
DQa  
DDQ  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DDQ  
SS  
V
V
V
SS  
SS  
SS  
DQc  
DQc  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQc  
DQc  
9
9
V
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
SS  
V
V
DDQ  
DDQ  
V
V
DQa  
DQa  
V
NC  
V
ZZ  
DDQ  
DDQ  
DQc  
DQc  
NC  
DQb  
DQb  
DQb  
DQb  
NC  
V
SS  
CY7C1370D  
(512K × 36)  
SS  
V
V
DD  
NC  
DD  
CY7C1372D  
(1M × 18)  
NC  
NC  
V
DD  
DD  
V
V
SS  
SS  
ZZ  
DQa  
DQa  
DQd  
DQb  
DQb  
DQa  
DQa  
DQd  
V
V
DDQ  
DDQ  
V
V
V
DQa  
DQa  
NC  
NC  
V
V
DDQ  
DDQ  
V
V
SS  
V
SS  
SS  
SS  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQb  
DQb  
DQa DQPb  
DQa  
NC  
V
SS  
V
V
SS  
SS  
SS  
V
V
DDQ  
V
DDQ  
DDQ  
DDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
DQPa  
NC  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05555 Rev. *F  
Page 3 of 28  
CY7C1370D  
CY7C1372D  
Pin Configurations (continued)  
119-Ball BGA  
Pinout  
CY7C1370D (512K x 36)  
1
2
3
4
5
6
7
V
A
A
A
A
A
V
DDQ  
A
DDQ  
NC/576M  
NC/1G  
CE  
A
A
A
ADV/LD  
A
A
CE  
A
NC  
NC  
DQ  
B
C
D
2
3
V
DD  
DQ  
DQP  
DQ  
V
NC  
V
DQP  
DQ  
c
c
SS  
SS  
SS  
SS  
SS  
SS  
b
b
DQ  
V
V
CE  
V
V
DQ  
b
E
F
c
c
c
c
c
1
b
b
b
b
V
DQ  
DQ  
DQ  
V
DQ  
DQ  
DQ  
V
V
DDQ  
OE  
A
DDQ  
DQ  
DQ  
G
H
J
BW  
V
BW  
V
c
b
c
b
DQ  
DQ  
WE  
c
SS  
b
SS  
V
NC  
V
NC  
V
DDQ  
DDQ  
DD  
DD  
DD  
DQ  
DQ  
V
CLK  
NC  
V
DQ  
DQ  
K
L
d
d
d
SS  
SS  
a
a
a
a
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
BW  
BW  
d
d
a
V
V
V
V
V
V
V
V
DDQ  
M
N
P
CEN  
A1  
DDQ  
d
SS  
SS  
SS  
SS  
SS  
SS  
a
a
DQ  
DQ  
DQ  
d
d
a
a
DQ  
DQP  
A
A0  
DQP  
A
DQ  
d
d
a
NC/144M  
NC  
MODE  
A
V
NC/288M  
ZZ  
R
T
NC  
A
DD  
NC/72M  
TMS  
A
NC/36M  
NC  
V
TDI  
TCK  
TDO  
V
U
DDQ  
DDQ  
CY7C1372D (1M x 18)  
1
2
3
4
5
6
7
V
A
A
A
A
A
V
A
B
C
D
E
F
DDQ  
DDQ  
NC/576M  
NC/1G  
CE  
A
A
A
A
A
NC  
NC  
NC  
CE  
ADV/LD  
2
3
V
A
DD  
DQ  
NC  
DQ  
V
NC  
V
DQP  
b
SS  
SS  
SS  
SS  
SS  
SS  
a
NC  
V
V
V
V
NC  
DQ  
CE  
b
a
1
V
NC  
DQ  
DQ  
V
OE  
A
DDQ  
a
DDQ  
NC  
NC  
NC  
DQ  
G
H
J
BW  
V
b
a
b
DQ  
V
NC  
V
DQ  
NC  
V
WE  
b
SS  
SS  
a
V
NC  
V
NC  
V
DDQ  
DD  
DD  
DD  
DDQ  
NC  
DQ  
V
CLK  
NC  
V
NC  
DQ  
K
L
b
SS  
SS  
a
DQ  
NC  
DQ  
NC  
DQ  
NC  
BW  
b
a
a
V
V
V
V
V
NC  
V
M
N
P
R
T
CEN  
A1  
DDQ  
b
SS  
SS  
SS  
SS  
DDQ  
DQ  
NC  
DQP  
A
V
DQ  
NC  
b
SS  
a
NC  
V
A0  
NC  
A
DQ  
b
SS  
a
NC/144M  
NC/72M  
MODE  
A
V
NC  
A
NC/288M  
ZZ  
DD  
A
NC/36M  
TCK  
A
V
TMS  
TDI  
TDO  
NC  
V
U
DDQ  
DDQ  
Document #: 38-05555 Rev. *F  
Page 4 of 28  
CY7C1370D  
CY7C1372D  
Pin Configurations (continued)  
165-Ball FBGA Pinout  
CY7C1370D (512K x 36)  
1
2
A
3
4
5
6
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPc  
ADV/LD  
A
B
C
D
CE1  
BWc  
BWb  
CE  
CEN  
WE  
VSS  
VSS  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
BWd  
VSS  
VDD  
BWa  
VSS  
VSS  
NC  
DQc  
VDDQ  
VDDQ  
NC  
DQb  
DQPb  
DQb  
DQc  
DQc  
DQc  
DQc  
DQc  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQb  
DQb  
DQb  
NC  
DQb  
E
F
DQc  
DQc  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQb  
DQb  
ZZ  
G
H
J
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
K
L
DQd  
DQd  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
DQa  
DQPa  
M
N
P
DQPd  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
MODE  
NC/36M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
CY7C1372D (1M x 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
4
5
NC  
6
CE  
7
8
9
A
10  
A
11  
A
A
B
C
D
CE1  
BWb  
NC  
CEN  
ADV/LD  
3
A
CE2  
VDDQ  
VDDQ  
BWa  
VSS  
VSS  
CLK  
VSS  
VSS  
A
A
NC  
WE  
VSS  
VSS  
OE  
VSS  
VDD  
NC  
DQb  
VSS  
VDD  
VDDQ  
VDDQ  
NC  
NC  
DQPa  
DQa  
NC  
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQa  
DQa  
DQa  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
NC  
NC  
NC  
K
L
NC  
NC  
DQb  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
NC  
NC  
M
N
P
DQPb  
NC/144M NC/72M  
MODE NC/36M  
TDI  
TDO  
NC/288M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05555 Rev. *F  
Page 5 of 28  
CY7C1370D  
CY7C1372D  
Pin Definitions  
Pin Name  
I/O Type  
Pin Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge of  
A0  
Input-  
A1  
A
Synchronous the CLK.  
BW  
Input-  
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.  
a
BW  
BW  
BW  
Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP ,  
b
c
d
a
a
a
b
b
b
BW controls DQ and DQP , BW controls DQ and DQP .  
c
c
c
d
d
d
WE  
Input-  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This  
Synchronous signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input- Advance/Load Input used to advance the on-chip address counter or load a new address.  
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a  
new address can be loaded into the device for an access. After being deselected, ADV/LD should  
be driven LOW in order to load a new address.  
CLK  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.  
CLK is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
1
2
3
Synchronous CE and CE to select/deselect the device.  
2
3
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device.  
1
3
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device.  
1
2
OE  
Input-  
Output Enable, active LOW. Combined with the synchronous logic block inside the device to  
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.  
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during  
the data portion of a write sequence, during the first clock when emerging from a deselected  
state and when the device has been deselected.  
CEN  
Input-  
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the  
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not  
deselect the device, CEN can be used to extend the previous cycle when required.  
DQ  
I/O-  
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location  
specified by A during the previous clock rise of the read cycle. The direction of the pins is  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered  
S
[17:0]  
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave  
as outputs. When HIGH, DQ –DQ are placed in a tri-state condition. The outputs are automat-  
a
d
ically tri-stated during the data portion of a write sequence, during the first clock when emerging  
from a deselected state, and when the device is deselected, regardless of the state of OE.  
DQP  
I/O-  
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ . During write  
X
s
Synchronous sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by BW ,  
a
a
b
b
c
c
and DQP is controlled by BW .  
d
d
MODE  
TDO  
TDI  
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.  
Pulled LOW selects the linear burst order. MODE should not change states during operation.  
When left floating MODE will default HIGH, to an interleaved burst order.  
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.  
output  
Synchronous  
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.  
input  
Synchronous  
TMS  
TCK  
Test Mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.  
Select  
Synchronous  
JTAG-Clock Clock input to the JTAG circuitry.  
V
Power Supply Power supply inputs to the core of the device.  
DD  
Document #: 38-05555 Rev. *F  
Page 6 of 28  
CY7C1370D  
CY7C1372D  
Pin Definitions (continued)  
Pin Name  
I/O Type  
Pin Description  
V
V
I/O Power Power supply for the I/O circuitry.  
Supply  
DDQ  
Ground  
Ground for the device. Should be connected to ground of the system.  
SS  
NC  
No connects. This pin is not connected to the die.  
NC/(36M,72M,  
144M, 288M,  
576M, 1G)  
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,  
576M and 1G densities.  
ZZ  
Input-  
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition  
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to V or left  
SS  
floating. ZZ pin has an internal pull-down.  
second clock, a subsequent operation (Read/Write/Deselect)  
can be initiated. Deselecting the device is also pipelined.  
Therefore, when the SRAM is deselected at clock rise by one  
of the chip enable signals, its output will tri-state following the  
next clock rise.  
Introduction  
Functional Overview  
The CY7C1370D and CY7C1372D are synchronous-pipelined  
Burst NoBL SRAMs designed specifically to eliminate wait  
states during Write/Read transitions. All synchronous inputs  
pass through input registers controlled by the rising edge of  
the clock. The clock signal is qualified with the Clock Enable  
input signal (CEN). If CEN is HIGH, the clock signal is not  
recognized and all internal states are maintained. All  
synchronous operations are qualified with CEN. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise  
Burst Read Accesses  
The CY7C1370D and CY7C1372D have an on-chip burst  
counter that allows the user the ability to supply a single  
address and conduct up to four Reads without reasserting the  
address inputs. ADV/LD must be driven LOW in order to load  
a new address into the SRAM, as described in the Single Read  
Access section above. The sequence of the burst counter is  
determined by the MODE input signal. A LOW input on MODE  
selects a linear burst mode, a HIGH selects an interleaved  
burst sequence. Both burst counters use A0 and A1 in the  
burst sequence, and will wrap-around when incremented suffi-  
ciently. A HIGH input on ADV/LD will increment the internal  
burst counter regardless of the state of chip enables inputs or  
WE. WE is latched at the beginning of a burst cycle. Therefore,  
the type of access (Read or Write) is maintained throughout  
the burst sequence.  
(t ) is 2.6 ns (250-MHz device).  
CO  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device will be latched. The  
access can either be a read or write operation, depending on  
the status of the Write Enable (WE). BW can be used to  
conduct byte write operations.  
X
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
Single Write Accesses  
Write access are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
1
2
3
and CE are ALL asserted active, and (3) the write signal WE  
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been  
deselected in order to load a new address for the next  
operation.  
3
is asserted LOW. The address presented is loaded into the  
Address Register. The write signals are latched into the  
Control Logic block.  
On the subsequent clock rise the data lines are automatically  
tri-stated regardless of the state of the OE input signal. This  
allows the external logic to present the data on DQ and DQP  
Single Read Accesses  
A read access is initiated when the following conditions are  
(DQ  
/DQP  
for CY7C1370D and DQ /DQP  
for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
CY7C1372D). In addition, the address for the subsequent  
access (Read/Write/Deselect) is latched into the Address  
Register (provided the appropriate control signals are  
asserted).  
1
2
and CE are ALL asserted active, (3) the Write Enable input  
3
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory core  
and control logic. The control logic determines that a read  
access is in progress and allows the requested data to  
propagate to the input of the output register. At the rising edge  
of the next clock the requested data is allowed to propagate  
through the output register and onto the data bus within 2.6 ns  
(250-MHz device) provided OE is active LOW. After the first  
clock of the read access the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW in  
order for the device to drive out the requested data. During the  
On the next clock rise the data presented to DQ and DQP  
(DQ  
/DQP  
for CY7C1370D & DQ /DQP  
for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
CY7C1372D) (or a subset for byte write operations, see Write  
Cycle Description table for details) inputs is latched into the  
device and the write is complete.  
The data written during the write operation is controlled by BW  
(BW  
signals. The CY7C1370D/CY7C1372D provides byte write  
capability that is described in the Write Cycle Description table.  
for CY7C1370D and BW  
for CY7C1372D)  
a,b,c,d  
a,b  
Document #: 38-05555 Rev. *F  
Page 7 of 28  
CY7C1370D  
CY7C1372D  
Asserting the Write Enable input (WE) with the selected Byte  
Write Select (BW) input will selectively write to only the desired  
bytes. Bytes not selected during a byte write operation will  
remain unaltered. A synchronous self-timed write mechanism  
has been provided to simplify the write operations. Byte write  
capability has been included in order to greatly simplify  
Read/Modify/Write sequences, which can be reduced to  
simple byte write operations.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
Because the CY7C1370D and CY7C1372D are common I/O  
devices, data should not be driven into the device while the  
outputs are active. The Output Enable (OE) can be deasserted  
HIGH before presenting data to the DQ and DQP  
the “sleep” mode. CE , CE , and CE , must remain inactive  
1
2
3
for the duration of t  
after the ZZ input returns LOW.  
ZZREC  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
(DQ  
/DQP  
for CY7C1370D and DQ /DQP  
for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
CY7C1372D) inputs. Doing so will tri-state the output drivers.  
As a safety precaution, DQ and DQP (DQ /DQP for  
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
a,b,c,d  
a,b,c,d  
CY7C1370D and DQ /DQP  
for CY7C1372D) are  
a,b  
a,b  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
automatically tri-stated during the data portion of a write cycle,  
regardless of the state of OE.  
01  
00  
11  
10  
Burst Write Accesses  
10  
11  
00  
01  
The CY7C1370D/CY7C1372D has an on-chip burst counter  
that allows the user the ability to supply a single address and  
conduct up to four write operations without reasserting the  
address inputs. ADV/LD must be driven LOW in order to load  
the initial address, as described in the Single Write Access  
section above. When ADV/LD is driven HIGH on the subse-  
11  
10  
01  
00  
Linear Burst Address Table (MODE = GND)  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
quent clock rise, the chip enables (CE , CE , and CE ) and  
1
2
3
WE inputs are ignored and the burst counter is incremented.  
The correct BW (BW for CY7C1370D and BW for  
CY7C1372D) inputs must be driven in each cycle of the burst  
write in order to write the correct bytes of data.  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
a,b,c,d  
a,b  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min.  
Max.  
80  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
DDZZ  
ZZ > V 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Document #: 38-05555 Rev. *F  
Page 8 of 28  
CY7C1370D  
CY7C1372D  
Truth Table[1, 2, 3, 4, 5, 6, 7]  
Address  
Used  
Operation  
Deselect Cycle  
CE  
H
X
L
ZZ  
L
ADV/LD WE BW  
OE  
CEN CLK  
DQ  
Tri-State  
Tri-State  
Data Out (Q)  
Data Out (Q)  
Tri-State  
Tri-State  
Data In (D)  
Data In (D)  
Tri-State  
Tri-State  
x
None  
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
H
X
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
X
Continue Deselect Cycle  
Read Cycle (Begin Burst)  
Read Cycle (Continue Burst)  
NOP/Dummy Read (Begin Burst)  
Dummy Read (Continue Burst)  
Write Cycle (Begin Burst)  
Write Cycle (Continue Burst)  
NOP/Write Abort (Begin Burst)  
Write Abort (Continue Burst)  
Ignore Clock Edge (Stall)  
Sleep Mode  
None  
L
X
L
External  
Next  
L
X
L
L
H
L
L
External  
Next  
L
H
H
X
X
X
X
X
X
X
L
L
H
L
External  
Next  
L
X
L
L
H
L
X
L
L
None  
L
H
H
X
X
Next  
X
X
X
L
H
X
X
X
X
X
Current  
None  
L
H
Tri-State  
Notes:  
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid  
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.  
2. Write is defined by WE and BW . See Write Cycle Description table for details.  
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.  
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.  
5. CEN = H inserts wait states.  
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when OE  
s
X
is inactive or when the device is deselected, and DQ = data when OE is active.  
s
Document #: 38-05555 Rev. *F  
Page 9 of 28  
CY7C1370D  
CY7C1372D  
Partial Write Cycle Description[1, 2, 3, 8]  
Function (CY7C1370D)  
Read  
WE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
X
H
H
H
H
L
BW  
X
H
H
L
BW  
a
d
c
b
X
H
L
Write – No bytes written  
Write Byte a – (DQ and DQP )  
L
a
a
Write Byte b – (DQ and DQP )  
L
H
L
b
b
Write Bytes b, a  
Write Byte c – (DQ and DQP )  
L
L
L
H
H
L
H
L
c
c
Write Bytes c, a  
Write Bytes c, b  
Write Bytes c, b, a  
L
L
L
L
H
L
L
L
L
Write Byte d – (DQ and DQP )  
L
H
H
H
H
L
H
H
L
H
L
d
d
Write Bytes d, a  
Write Bytes d, b  
Write Bytes d, b, a  
Write Bytes d, c  
Write Bytes d, c, a  
Write Bytes d, c, b  
Write All Bytes  
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Function (CY7C1372D)  
WE  
BW  
x
BW  
x
b
a
Read  
H
L
L
L
L
Write – No Bytes Written  
Write Byte a – (DQ and DQP )  
H
H
L
H
L
a
a
Write Byte b – (DQ and DQP )  
H
L
b
b
Write Both Bytes  
L
Note:  
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.  
X
Document #: 38-05555 Rev. *F  
Page 10 of 28  
CY7C1370D  
CY7C1372D  
Test Data-In (TDI)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. TDI  
is internally pulled up and can be unconnected if the TAP is  
unused in an application. TDI is connected to the most signif-  
icant bit (MSB) of any register. (See Tap Controller Block  
Diagram.)  
The CY7C1370D/CY7C1372D incorporates a serial boundary  
scan test access port (TAP). This part is fully compliant with  
1149.1. The TAP operates using JEDEC-standard 3.3V or  
2.5V I/O logic levels.  
The CY7C1370D/CY7C1372D contains a TAP controller,  
instruction register, boundary scan register, bypass register,  
and ID register.  
Disabling the JTAG Feature  
Test Data-Out (TDO)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull-up resistor. TDO should be  
DD  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.  
TAP Controller Block Diagram  
0
Bypass Register  
TAP Controller State Diagram  
2
1
0
0
0
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
Selection  
Circuitry  
TEST-LOGIC  
1
TDI  
TDO  
RESET  
0
.
.
.
2
1
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
x
.
.
.
.
.
2
1
0
0
1
1
Boundary Scan Register  
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
TCK  
TMS  
1
1
1
1
TAP CONTROLLER  
EXIT1-DR  
EXIT1-IR  
0
0
PAUSE-DR  
0
PAUSE-IR  
0
1
1
Performing a TAP Reset  
0
0
EXIT2-DR  
1
EXIT2-IR  
1
A Reset is performed by forcing TMS HIGH (V ) for five rising  
edges of TCK. This Reset does not affect the operation of the  
SRAM and may be performed while the SRAM is operating.  
DD  
UPDATE-DR  
UPDATE-IR  
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
1
0
1
0
TAP Registers  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Instruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
Test Mode Select (TMS)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Document #: 38-05555 Rev. *F  
Page 11 of 28  
CY7C1370D  
CY7C1372D  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
SAMPLE/PRELOAD  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the in-  
struction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is cap-  
tured in the boundary scan register.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is possi-  
ble that during the Capture-DR state, an input or output will  
undergo a transition. The TAP may then try to capture a signal  
while in transition (metastable state). This will not harm the  
device, but there is no guarantee as to the value that will be  
captured. Repeatable results may not be possible.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
TAP Instruction Set  
Overview  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
Eight different instructions are possible with the three bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells pri-  
or to the selection of another boundary scan test operation.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
access between the TDI and TDO in the shift-DR controller  
state.  
EXTEST Output Bus Tri-State  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
The boundary scan register has a special bit located at bit #85  
(for 119-BGA package) or bit #89 (for 165-FBGA package).  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the “Update-DR” state  
Document #: 38-05555 Rev. *F  
Page 12 of 28  
CY7C1370D  
CY7C1372D  
in the TAP controller, it will directly control the state of the  
output (Q-bus) pins, when the EXTEST is entered as the  
current instruction. When HIGH, it will enable the output  
buffers to drive the output bus. When LOW, this bit will place  
the output bus into a High-Z condition.  
register. When the EXTEST instruction is entered, this bit will  
directly control the output Q-bus pins. Note that this bit is  
preset HIGH to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR,” the value  
loaded into that shift-register cell will latch into the preload  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
[9, 10]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes:  
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05555 Rev. *F  
Page 13 of 28  
CY7C1370D  
CY7C1372D  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ................................................ V to 3.3V  
Input pulse levels.................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.5V  
1.25V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
[11]  
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)  
Parameter  
Description  
Test Conditions  
Min.  
2.4  
2.0  
2.9  
2.1  
Max.  
Unit  
V
V
V
V
V
V
V
I
Output HIGH Voltage  
I
I
I
= –4.0 mA, V  
= –1.0 mA, V  
= –100 µA  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
V
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
V
V
= 3.3V  
= 2.5V  
V
OH2  
OL1  
OL2  
IH  
DDQ  
DDQ  
V
I
I
I
= 8.0 mA, V  
= 8.0 mA, V  
= 100 µA  
= 3.3V  
= 2.5V  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
OL  
DDQ  
V
DDQ  
V
V
= 3.3V  
= 2.5V  
V
DDQ  
DDQ  
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
2.0  
1.7  
V
V
+ 0.3  
V
DDQ  
DDQ  
DDQ  
DDQ  
DD  
DD  
+ 0.3  
V
–0.5  
–0.3  
–5  
0.7  
V
IL  
0.7  
5
V
µA  
GND < V < V  
X
IN  
DDQ  
Note:  
11.All voltages referenced to V (GND).  
SS  
Document #: 38-05555 Rev. *F  
Page 14 of 28  
CY7C1370D  
CY7C1372D  
Identification Register Definitions  
Instruction Field  
Revision Number (31:29)  
Cypress Device ID (28:12)  
Cypress JEDEC ID (11:1)  
ID Register Presence (0)  
CY7C1372D  
000  
CY7C1370D  
Description  
Reserved for version number.  
000  
[12]  
01011001000100101 01011001000010101 Reserved for future use.  
00000110100  
1
00000110100  
1
Allows unique identification of SRAM vendor.  
Indicate the presence of an ID register.  
Scan Register Sizes  
Register Name  
Bit Size (x18)  
Bit Size (x36)  
Instruction  
Bypass  
ID  
3
3
1
1
32  
85  
89  
32  
85  
89  
Boundary Scan Order (119-ball BGA package)  
Boundary Scan Order (165-ball FBGA package)  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state.  
IDCODE  
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This  
operation does not affect SRAM operations.  
SAMPLE Z  
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011 Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101 Do Not Use: This instruction is reserved for future use.  
110 Do Not Use: This instruction is reserved for future use.  
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-  
tions.  
Note:  
12. Bit #24 is “1” in the Register Definitions for both 2.5Vand 3.3V versions of this device.  
Document #: 38-05555 Rev. *F  
Page 15 of 28  
CY7C1370D  
CY7C1372D  
119-Ball BGA Boundary Scan Order [13, 14]  
Bit #  
1
Ball ID  
Bit #  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Ball ID  
F6  
Bit #  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
Ball ID  
G4  
A4  
G3  
C3  
B2  
B3  
A3  
C2  
A2  
B1  
C1  
D2  
E1  
F2  
Bit #  
Ball ID  
L1  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
H4  
T4  
T5  
T6  
R5  
L5  
2
E7  
D7  
H7  
G6  
E6  
D6  
C7  
B7  
C6  
A6  
C5  
B5  
G5  
B6  
D4  
B4  
F4  
M2  
N1  
3
4
P1  
5
K1  
6
L2  
7
R6  
U6  
R7  
T7  
P6  
N7  
M6  
L7  
N2  
P2  
8
9
R3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
T1  
R1  
T2  
L3  
R2  
K6  
P7  
N6  
L6  
G1  
H2  
D1  
E2  
G2  
H1  
J3  
T3  
L4  
N4  
P4  
K7  
J5  
M4  
A5  
K4  
E4  
Internal  
H6  
G7  
2K  
Notes:  
13. Balls which are NC (No Connect) are pre-set LOW.  
14. Bit# 85 is pre-set HIGH.  
Document #: 38-05555 Rev. *F  
Page 16 of 28  
CY7C1370D  
CY7C1372D  
165-Ball BGA Boundary Scan Order [13, 15]  
Bit #  
1
Ball ID  
N6  
Bit #  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
Ball ID  
D10  
C11  
A11  
B11  
A10  
B10  
A9  
Bit #  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Ball ID  
G1  
D2  
E2  
2
N7  
3
N10  
P11  
P8  
4
F2  
5
G2  
H1  
H3  
J1  
6
R8  
7
R9  
8
P9  
B9  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
C10  
A8  
K1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
L1  
B8  
M1  
J2  
A7  
B7  
K2  
B6  
L2  
A6  
M2  
N1  
N2  
P1  
B5  
A5  
A4  
B4  
R1  
R2  
P3  
B3  
A3  
A2  
R3  
P2  
H10  
G11  
F11  
E11  
D11  
G10  
F10  
E10  
B2  
C2  
R4  
P4  
B1  
A1  
N5  
P6  
C1  
D1  
R6  
Internal  
E1  
F1  
Note:  
15. Bit# 89 is pre-set HIGH.  
Document #: 38-05555 Rev. *F  
Page 17 of 28  
CY7C1370D  
CY7C1372D  
Maximum Ratings  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
Range  
Temperature  
V
V
DDQ  
DDQ  
DD  
DD  
DC to Outputs in Tri-State................... –0.5V to V  
+ 0.5V  
Commercial 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to  
DDQ  
V
DD  
DC Input Voltage....................................–0.5V to V + 0.5V  
Industrial  
–40°C to +85°C  
DD  
[16, 17]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
3.6  
V
V
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
DD  
DDQ  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = –4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
V
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
[16]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
+ 0.3V  
0.8  
V
DD  
DD  
V
[16]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
V
IL  
0.7  
V
Input Leakage Current GND V V  
except ZZ and MODE  
5
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 167 MHz  
350  
300  
275  
160  
150  
140  
70  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
CYC  
MAX  
I
Automatic CE  
Power-down  
Current—TTL Inputs  
Max. V , Device Deselected, 4-ns cycle, 250 MHz  
DD  
SB1  
V
V or V V , f = f  
=
IN  
IH  
IN  
IL  
MAX  
5-ns cycle, 200 MHz  
6-ns cycle, 167 MHz  
1/t  
CYC  
I
I
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0  
Max. V , Device Deselected, All speed grades  
DD  
SB2  
V
0.3V or V > V  
0.3V,  
IN  
IN  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
Max. V , Device Deselected, 4-ns cycle, 250 MHz  
135  
130  
125  
80  
mA  
mA  
mA  
mA  
SB3  
DD  
V
0.3V or V > V  
0.3V,  
IN  
IN  
CYC  
DDQ  
5-ns cycle, 200 MHz  
6-ns cycle, 167 MHz  
= 1/t  
MAX  
I
Automatic CE  
Max. V , Device Deselected, All speed grades  
DD  
SB4  
Power-down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH  
IN  
IL  
Notes:  
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
17. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05555 Rev. *F  
Page 18 of 28  
CY7C1370D  
CY7C1372D  
Capacitance[18]  
100 TQFP  
Max.  
119 BGA  
Max.  
165 FBGA  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
C
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
5
5
8
8
8
9
9
9
IN  
A
V
= 3.3V.  
DD  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
= 2.5V  
DDQ  
pF  
Thermal Resistance[18]  
100 TQFP  
Package  
119 BGA  
Package  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures  
for measuring thermal  
28.66  
23.8  
20.7  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
4.08  
6.2  
4.0  
°C/W  
JC  
impedance, per EIA/JESD51.  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
1 ns  
1 ns  
V = 1.25V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Note:  
18. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05555 Rev. *F  
Page 19 of 28  
CY7C1370D  
CY7C1372D  
[23, 24]  
Switching Characteristics Over the Operating Range  
–250  
–200  
–167  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
[19]  
t
V
(typical) to the first access read or write  
1
1
1
ms  
Power  
CC  
Clock  
t
Clock Cycle Time  
Maximum Operating Frequency  
Clock HIGH  
4.0  
5
6
ns  
MHz  
ns  
CYC  
F
250  
200  
167  
MAX  
t
t
1.7  
1.7  
2.0  
2.0  
2.2  
2.2  
CH  
CL  
Clock LOW  
ns  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
OE LOW to Output Valid  
2.6  
2.6  
3.0  
3.0  
3.4  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
EOV  
DOH  
CHZ  
CLZ  
Data Output Hold After CLK Rise  
1.0  
1.0  
0
1.3  
1.3  
0
1.3  
1.3  
0
[20, 21, 22]  
Clock to High-Z  
2.6  
2.6  
3.0  
3.0  
3.4  
3.4  
[20, 21, 22]  
Clock to Low-Z  
[20, 21, 22]  
OE HIGH to Output High-Z  
EOHZ  
EOLZ  
[20, 21, 22]  
OE LOW to Output Low-Z  
Set-up Times  
t
t
t
t
t
t
Address Set-up Before CLK Rise  
Data Input Set-up Before CLK Rise  
CEN Set-up Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
DS  
CENS  
WES  
ALS  
CES  
WE, BW Set-up Before CLK Rise  
x
ADV/LD Set-up Before CLK Rise  
Chip Select Set-up  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
Data Input Hold After CLK Rise  
CEN Hold After CLK Rise  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
DH  
CENH  
WEH  
ALH  
CEH  
WE, BW Hold After CLK Rise  
x
ADV/LD Hold after CLK Rise  
Chip Select Hold After CLK Rise  
Notes:  
19. This part has a voltage regulator internally; t  
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be  
DD  
Power  
initiated.  
20. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ EOLZ  
EOHZ  
21. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
EOHZ  
EOLZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
22. This parameter is sampled and not 100% tested.  
23. Timing reference is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05555 Rev. *F  
Page 20 of 28  
CY7C1370D  
CY7C1372D  
Switching Waveforms  
[25, 26, 27]  
Read/Write/Timing  
1
2
3
4
5
6
7
8
9
10  
t
CYC  
t
CLK  
t
t
t
CENS CENH  
CL  
CH  
CEN  
t
t
CES  
CEH  
CE  
ADV/LD  
WE  
BWx  
A1  
A2  
A4  
CO  
A3  
A5  
A6  
A7  
ADDRESS  
t
t
t
t
DS  
DH  
t
t
t
DOH  
OEV  
CLZ  
CHZ  
t
t
AS  
AH  
Data  
D(A1)  
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
In-Out (DQ)  
t
OEHZ  
t
DOH  
t
OELZ  
OE  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
25. For this waveform ZZ is tied LOW.  
26. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.  
Document #: 38-05555 Rev. *F  
Page 21 of 28  
CY7C1370D  
CY7C1372D  
Switching Waveforms (continued)  
[25, 26, 28]  
NOP,STALL and DESELECT Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BWx  
A1  
A2  
A3  
A4  
A5  
ADDRESS  
t
CHZ  
D(A4)  
D(A1)  
Q(A2)  
Q(A3)  
Q(A5)  
Data  
In-Out (DQ)  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
[29, 30]  
ZZ Mode Timing  
CLK  
ZZ  
t
t
ZZ  
ZZREC  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
28. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
29. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.  
30. I/Os are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05555 Rev. *F  
Page 22 of 28  
CY7C1370D  
CY7C1372D  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1370D-167AXC  
CY7C1372D-167AXC  
CY7C1370D-167BGC  
CY7C1372D-167BGC  
Part and Package Type  
167  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1370D-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-167BGXC  
CY7C1370D-167BZC  
CY7C1372D-167BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1370D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1372D-167BZXC  
CY7C1370D-167AXI  
CY7C1372D-167AXI  
CY7C1370D-167BGI  
CY7C1372D-167BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1370D-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-167BGXI  
CY7C1370D-167BZI  
CY7C1372D-167BZI  
CY7C1370D-167BZXI  
CY7C1372D-167BZXI  
CY7C1370D-200AXC  
CY7C1372D-200AXC  
CY7C1370D-200BGC  
CY7C1372D-200BGC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
200  
Commercial  
CY7C1370D-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-200BGXC  
CY7C1370D-200BZC  
CY7C1372D-200BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1370D-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1372D-200BZXC  
CY7C1370D-200AXI  
CY7C1372D-200AXI  
CY7C1370D-200BGI  
CY7C1372D-200BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1370D-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-200BGXI  
CY7C1370D-200BZI  
CY7C1372D-200BZI  
CY7C1370D-200BZXI  
CY7C1372D-200BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05555 Rev. *F  
Page 23 of 28  
CY7C1370D  
CY7C1372D  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
250  
CY7C1370D-250AXC  
CY7C1372D-250AXC  
CY7C1370D-250BGC  
CY7C1372D-250BGC  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1370D-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-250BGXC  
CY7C1370D-250BZC  
CY7C1372D-250BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1370D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1372D-250BZXC  
CY7C1370D-250AXI  
CY7C1372D-250AXI  
CY7C1370D-250BGI  
CY7C1372D-250BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1370D-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1372D-250BGXI  
CY7C1370D-250BZI  
CY7C1372D-250BZI  
CY7C1370D-250BZXI  
CY7C1372D-250BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05555 Rev. *F  
Page 24 of 28  
CY7C1370D  
CY7C1372D  
Package Diagrams  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Document #: 38-05555 Rev. *F  
Page 25 of 28  
CY7C1370D  
CY7C1372D  
Package Diagrams (continued)  
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.75 0.15(119X)  
Ø1.00(3X) REF.  
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27  
0.70 REF.  
A
3.81  
12.00  
7.62  
B
14.00 0.20  
0.15(4X)  
30° TYP.  
51-85115-*B  
SEATING PLANE  
C
Document #: 38-05555 Rev. *F  
Page 26 of 28  
CY7C1370D  
CY7C1372D  
Package Diagrams (continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
Ø0.25 M C A B  
-0.06  
Ø0.50
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
B
13.00 0.10  
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDECREFERENCE: MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor  
Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05555 Rev. *F  
Page 27 of 28  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1370D  
CY7C1372D  
Document History Page  
Document Title: CY7C1372D/CY7C1370D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture  
Document Number: 38-05555  
Orig. of  
REV.  
**  
ECN No. Issue Date Change  
Description of Change  
254509  
276690  
See ECN  
See ECN  
RKF  
VBL  
New data sheet  
*A  
Changed TQFP pkg to Lead-free TQFP in Ordering Information section  
Added comment of Lead-free BG and BZ packages availability  
*B  
*C  
288531  
See ECN  
SYT  
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for  
non-compliance with 1149.1  
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA  
Packages  
326078  
See ECN  
PCI  
Address expansion pins/balls in the pinouts for all packages are modified as  
per JEDEC standard  
Added description on EXTEST Output Bus Tri-State  
Changed description on the Tap Instruction Set Overview and Extest  
Changed Θ and Θ for TQFP Package from 31 and 6 °C/W to 28.66 and  
JA  
JC  
4.08 °C/W respectively  
Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2  
JA  
JC  
°C/W respectively  
Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and  
JA  
JC  
4.0 °C/W respectively  
Modified V test conditions  
V
OL, OH  
Removed shading from AC/DC Table and Selection Guide  
Removed comment of ‘Lead-free BG packages availability’ below the  
Ordering Information  
Updated Ordering Information Table  
Changed from Preliminary to final  
*D  
*E  
370734  
416321  
See ECN  
See ECN  
PCI  
Modified test condition in note# 17 from V  
Converted from preliminary to final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table  
< V to V  
V  
DDQ  
DD  
DDQ DD  
NXR  
Changed three-state to tri-state  
Changed the I current values of MODE on page # 18 from –5 µA and 30 µA  
X
to –30 µA and 5 µA  
Changed the I current values of ZZ on page # 18 from –30 µA and 5 µA  
X
to –5 µA and 30 µA  
Changed V < V to V < V on page # 18  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Updated Ordering Information Table  
*F  
475677  
See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table.  
Updated the Ordering Information table.  
Document #: 38-05555 Rev. *F  
Page 28 of 28  

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