Cypress Perform CY7C1356C User Manual

CY7C1354C  
CY7C1356C  
9-Mbit (256K x 36/512K x 18)  
Pipelined SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200, and 166 MHz  
The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and  
512K x 18 Synchronous pipelined burst SRAMs with No Bus  
Latency™ (NoBL™) logic, respectively. They are designed to  
support unlimited true back-to-back Read/Write operations  
with no wait states. The CY7C1354C and CY7C1356C are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
Write/Read transitions. The CY7C1354C and CY7C1356C are  
pin compatible and functionally equivalent to ZBT devices.  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 3.3V power supply (V  
)
DD  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• 3.3V or 2.5V I/O power supply (V  
• Fast clock-to-output times  
— 2.8 ns (for 250-MHz device)  
)
DDQ  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non lead-free 119-Ball BGA package and 165-Ball  
FBGA package  
(BW –BW for CY7C1354C and BW –BW for CY7C1356C)  
and a Write Enable (WE) input. All writes are conducted with  
on-chip synchronous self-timed write circuitry.  
a
d
a
b
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
Burst capabilitylinear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram–CY7C1354C (256K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
BWa  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
WRITE  
DRIVERS  
DQPa  
DQPb  
DQPc  
DQPd  
A
M
P
BWb  
BWc  
BWd  
S
T
E
R
S
F
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05538 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 14, 2006  
CY7C1354C  
CY7C1356C  
Pin Configurations  
100-Pin TQFP Pinout  
DQPc  
DQc  
DQc  
1
2
3
4
5
6
7
8
NC  
NC  
NC  
DDQ  
1
2
3
4
5
6
7
8
A
NC  
NC  
78  
DQPb  
DQb  
DQb  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
80  
79  
V
V
DDQ  
V
V
V
NC  
DQPa  
DQa  
DQa  
DDQ  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DDQ  
SS  
V
V
V
SS  
SS  
SS  
DQc  
DQc  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQc  
DQc  
9
9
V
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
SS  
V
V
DDQ  
DDQ  
V
V
DQa  
DQa  
V
NC  
V
ZZ  
DDQ  
DDQ  
DQc  
DQc  
NC  
DQb  
DQb  
DQb  
DQb  
NC  
V
SS  
CY7C1354C  
(256K × 36)  
SS  
CY7C1356C  
(512K × 18)  
V
V
DD  
NC  
DD  
NC  
V
NC  
DD  
DD  
V
V
SS  
SS  
ZZ  
DQa  
DQa  
DQd  
DQb  
DQb  
DQa  
DQa  
DQd  
V
V
DDQ  
DDQ  
V
V
V
DQa  
DQa  
NC  
NC  
V
V
DDQ  
DDQ  
V
V
SS  
V
SS  
SS  
SS  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQb  
DQb  
DQa DQPb  
DQa  
NC  
V
SS  
V
V
SS  
SS  
SS  
V
V
DDQ  
V
DDQ  
DDQ  
DDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
DQPa  
NC  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05538 Rev. *G  
Page 3 of 28  
CY7C1354C  
CY7C1356C  
Pin Configurations (continued)  
119-Ball BGA Pinout  
CY7C1354C (256K × 36)  
1
2
3
4
5
6
7
V
A
A
NC/18M  
A
A
V
DDQ  
A
DDQ  
NC/576M  
NC/1G  
CE  
A
A
A
ADV/LD  
A
A
CE  
A
NC  
NC  
DQ  
B
C
D
2
3
V
DD  
DQ  
DQP  
DQ  
V
NC  
V
DQP  
DQ  
c
c
SS  
SS  
SS  
SS  
SS  
SS  
b
b
DQ  
V
V
CE  
V
V
DQ  
b
E
F
c
c
c
c
c
1
b
b
b
b
V
DQ  
DQ  
DQ  
V
DQ  
DQ  
DQ  
V
V
DDQ  
OE  
A
DDQ  
DQ  
DQ  
G
H
J
BW  
V
BW  
V
c
b
c
b
DQ  
DQ  
WE  
c
SS  
b
SS  
V
NC  
V
NC  
V
DDQ  
DDQ  
DD  
DD  
DD  
DQ  
DQ  
V
CLK  
NC  
V
DQ  
DQ  
K
L
d
d
d
SS  
SS  
a
a
a
a
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
BW  
BW  
d
d
a
V
V
V
V
V
V
V
V
DDQ  
M
N
P
CEN  
A1  
DDQ  
d
SS  
SS  
SS  
SS  
SS  
SS  
a
a
DQ  
DQ  
DQ  
d
d
a
a
DQ  
DQP  
A
A0  
DQP  
A
DQ  
d
d
a
NC/144M  
NC  
MODE  
A
V
NC/288M  
ZZ  
R
T
NC  
A
DD  
NC/72M  
TMS  
A
NC/36M  
NC  
V
TDI  
TCK  
TDO  
V
U
DDQ  
DDQ  
CY7C1356C (512K x 18)  
1
2
3
4
5
6
7
V
A
A
NC/18M  
A
A
V
A
B
C
D
E
F
DDQ  
DDQ  
NC/576M  
NC/1G  
CE  
A
A
A
A
A
NC  
NC  
NC  
CE  
ADV/LD  
2
3
V
A
DD  
DQ  
NC  
DQ  
V
NC  
V
DQP  
b
SS  
SS  
SS  
SS  
SS  
SS  
a
NC  
V
V
V
V
NC  
DQ  
CE  
b
a
1
V
NC  
DQ  
DQ  
V
OE  
A
DDQ  
a
DDQ  
NC  
V
V
NC  
DQ  
G
H
J
BW  
V
b
SS  
SS  
a
b
DQ  
V
NC  
DQ  
NC  
V
WE  
b
SS  
a
V
NC  
V
NC  
V
DDQ  
DD  
DD  
DD  
DDQ  
NC  
DQ  
V
CLK  
NC  
V
NC  
DQ  
K
L
b
SS  
SS  
a
DQ  
NC  
DQ  
V
DQ  
NC  
BW  
b
SS  
a
a
V
V
V
V
V
NC  
V
M
N
P
R
T
CEN  
A1  
DDQ  
b
SS  
SS  
SS  
SS  
DDQ  
DQ  
NC  
DQP  
A
V
DQ  
NC  
b
SS  
a
NC  
V
A0  
NC  
A
DQ  
b
SS  
a
NC/144M  
NC/72M  
MODE  
A
V
NC  
A
NC/288M  
ZZ  
DD  
A
NC/36M  
TCK  
A
V
TMS  
TDI  
TDO  
NC  
V
U
DDQ  
DDQ  
Document #: 38-05538 Rev. *G  
Page 4 of 28  
CY7C1354C  
CY7C1356C  
Pin Configurations (continued)  
165-Ball FBGA Pinout  
CY7C1354C (256K × 36)  
1
2
A
3
4
5
6
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPc  
ADV/LD  
A
B
C
D
CE1  
BWc  
BWd  
VSS  
VDD  
BWb  
BWa  
VSS  
VSS  
CE  
CEN  
WE  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
NC/18M  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
A
NC  
DQc  
VSS  
VSS  
NC  
DQb  
DQPb  
DQb  
DQc  
DQc  
DQc  
DQc  
NC  
DQc  
DQc  
DQc  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
DQb  
DQb  
DQb  
NC  
DQb  
DQb  
DQb  
ZZ  
E
F
G
H
J
NC  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
K
L
DQd  
DQd  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
DQa  
NC  
A
DQa  
DQPa  
M
N
P
DQPd  
NC/144M NC/72M  
MODE NC/36M  
TDI  
TDO  
NC/288M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
CY7C1356C (512K × 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
4
5
NC  
6
CE  
7
8
9
A
10  
A
11  
A
A
B
C
D
CE1  
BWb  
NC  
CEN  
ADV/LD  
3
A
CE2  
VDDQ  
VDDQ  
BWa  
VSS  
VSS  
CLK  
VSS  
VSS  
NC/18M  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
A
WE  
VSS  
VSS  
OE  
VSS  
VDD  
NC  
DQb  
VSS  
VDD  
NC  
NC  
DQPa  
DQa  
NC  
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
NC  
NC  
DQa  
DQa  
DQa  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A
NC  
K
L
NC  
NC  
DQb  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
DQa  
NC  
A
NC  
NC  
M
N
P
DQPb  
NC/144M NC/72M  
MODE NC/36M  
TDI  
TDO  
NC/288M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05538 Rev. *G  
Page 5 of 28  
CY7C1354C  
CY7C1356C  
Pin Definitions  
Pin Name  
I/O Type  
Pin Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge of  
A0, A1  
Input-  
A
Synchronous the CLK.  
Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.  
Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP ,  
BW ,BW ,  
BW ,BW ,  
a
b
c
d
a
a
a
b
b
b
BW controls DQ and DQP , BW controls DQ and DQP .  
c
c
c
d
d
d
WE  
Input-  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.  
Synchronous This signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input- Advance/Load Input used to advance the on-chip address counter or load a new address.  
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a  
new address can be loaded into the device for an access. After being deselected, ADV/LD should  
be driven LOW in order to load a new address.  
CLK  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.  
CLK is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
1
2
3
Synchronous CE and CE to select/deselect the device.  
2
3
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device.  
1
3
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device.  
1
2
OE  
Input-  
Output Enable, active LOW. Combined with the synchronous logic block inside the device to  
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.  
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during  
the data portion of a Write sequence, during the first clock when emerging from a deselected  
state and when the device has been deselected.  
CEN  
Input-  
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the  
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not  
deselect the device, CEN can be used to extend the previous cycle when required.  
DQ  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered  
S
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location  
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins  
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave  
as outputs. When HIGH, DQ –DQ are placed in a tri-state condition. The outputs are automat-  
a
d
ically tri-stated during the data portion of a write sequence, during the first clock when emerging  
from a deselected state, and when the device is deselected, regardless of the state of OE.  
DQP  
I/O-  
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ  
During  
[a:d].  
X
Synchronous write sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by  
a
a
b
b
c
BW , and DQP is controlled by BW .  
c
d
d
MODE  
TDO  
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.  
Pulled LOW selects the linear burst order. MODE should not change states during operation.  
When left floating MODE will default HIGH, to an interleaved burst order.  
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.  
output  
Synchronous  
TDI  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.  
Synchronous  
TMS  
TCK  
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.  
Synchronous  
JTAG-Clock Clock input to the JTAG circuitry.  
Power Supply Power supply inputs to the core of the device.  
I/O Power Supply Power supply for the I/O circuitry.  
V
V
V
DD  
DDQ  
SS  
Ground  
Ground for the device. Should be connected to ground of the system.  
Document #: 38-05538 Rev. *G  
Page 6 of 28  
CY7C1354C  
CY7C1356C  
Pin Definitions (continued)  
Pin Name  
NC  
I/O Type  
Pin Description  
No connects. This pin is not connected to the die.  
NC (18, 36,  
72, 144, 288,  
576, 1G)  
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M  
288M, 576M and 1G densities.  
ZZ  
Input-  
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”  
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left  
floating. ZZ pin has an internal pull-down.  
Burst Read Accesses  
Functional Overview  
The CY7C1354C and CY7C1356C have an on-chip burst  
counter that allows the user the ability to supply a single  
address and conduct up to four Reads without reasserting the  
address inputs. ADV/LD must be driven LOW in order to load  
a new address into the SRAM, as described in the Single Read  
Access section above. The sequence of the burst counter is  
determined by the MODE input signal. A LOW input on MODE  
selects a linear burst mode, a HIGH selects an interleaved  
burst sequence. Both burst counters use A0 and A1 in the  
burst sequence, and will wrap around when incremented suffi-  
ciently. A HIGH input on ADV/LD will increment the internal  
burst counter regardless of the state of chip enables inputs or  
WE. WE is latched at the beginning of a burst cycle. Therefore,  
the type of access (Read or Write) is maintained throughout  
the burst sequence.  
The CY7C1354C and CY7C1356C are synchronous-pipelined  
Burst NoBL SRAMs designed specifically to eliminate wait  
states during Write/Read transitions. All synchronous inputs  
pass through input registers controlled by the rising edge of  
the clock. The clock signal is qualified with the Clock Enable  
input signal (CEN). If CEN is HIGH, the clock signal is not  
recognized and all internal states are maintained. All  
synchronous operations are qualified with CEN. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise  
(t ) is 2.8 ns (250-MHz device).  
CO  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device will be latched. The  
access can either be a Read or Write operation, depending on  
Single Write Accesses  
the status of the Write Enable (WE). BW  
conduct Byte Write operations.  
can be used to  
Write access are initiated when the following conditions are  
[d:a]  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
and CE are ALL asserted active, and (3) the Write signal WE  
Write operations are qualified by the Write Enable (WE). All  
Writes are simplified with on-chip synchronous self-timed  
Write circuitry.  
3
is asserted LOW. The address presented to A –A is loaded  
0
16  
into the Address Register. The write signals are latched into  
the Control Logic block.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
On the subsequent clock rise the data lines are automatically  
tri-stated regardless of the state of the OE input signal. This  
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been  
deselected in order to load a new address for the next  
operation.  
allows the external logic to present the data on DQ  
and DQP  
(DQ  
/DQP  
for CY7C1354C and DQ /DQP  
for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
CY7C1356C). In addition, the address for the subsequent  
access (Read/Write/Deselect) is latched into the address  
register (provided the appropriate control signals are  
asserted).  
Single Read Accesses  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
On the next clock rise the data presented to DQ  
and DQP  
1
2
and CE are ALL asserted active, (3) the Write Enable input  
(DQ  
/DQP  
for CY7C1354C and DQ /DQP  
for  
3
a,b,c,d  
a,b,c,d  
a,b  
a,b  
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the address register and presented to the memory core  
and control logic. The control logic determines that a read  
access is in progress and allows the requested data to  
propagate to the input of the output register. At the rising edge  
of the next clock the requested data is allowed to propagate  
through the output register and onto the data bus within 2.8 ns  
(250-MHz device) provided OE is active LOW. After the first  
clock of the read access the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW in  
order for the device to drive out the requested data. During the  
second clock, a subsequent operation (Read/Write/Deselect)  
can be initiated. Deselecting the device is also pipelined.  
Therefore, when the SRAM is deselected at clock rise by one  
of the chip enable signals, its output will tri-state following the  
next clock rise.  
CY7C1356C) (or a subset for byte write operations, see Write  
Cycle Description table for details) inputs is latched into the  
device and the Write is complete.  
The data written during the Write operation is controlled by BW  
(BW  
for CY7C1354C and BW  
for CY7C1356C)  
a,b,c,d  
a,b  
signals. The CY7C1354C/CY7C1356C provides Byte Write  
capability that is described in the Write Cycle Description table.  
Asserting the Write Enable input (WE) with the selected Byte  
Write Select (BW) input will selectively write to only the desired  
bytes. Bytes not selected during a Byte Write operation will  
remain unaltered. A synchronous self-timed write mechanism  
has been provided to simplify the Write operations. Byte Write  
capability has been included in order to greatly simplify  
Read/Modify/Write sequences, which can be reduced to  
simple Byte Write operations.  
Document #: 38-05538 Rev. *G  
Page 7 of 28  
CY7C1354C  
CY7C1356C  
Because the CY7C1354C and CY7C1356C are common I/O  
devices, data should not be driven into the device while the  
outputs are active. The Output Enable (OE) can be deasserted  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
HIGH before presenting data to the DQ  
and DQP  
(DQ  
/DQP  
for CY7C1354C and DQ /DQP  
for  
the “sleep” mode. CE , CE , and CE must remain inactive for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
1
2
3,  
CY7C1356C) inputs. Doing so will tri-state the output drivers.  
As a safety precaution, DQ (DQ /DQP for  
CY7C1354C and DQ /DQP  
automatically tri-stated during the data portion of a write cycle,  
regardless of the state of OE.  
the duration of t  
after the ZZ input returns LOW.  
ZZREC  
and DQP  
a,b,c,d  
a,b,c,d  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
for CY7C1356C) are  
a,b  
a,b  
)
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
Burst Write Accesses  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
The CY7C1354C/CY7C1356C has an on-chip burst counter  
that allows the user the ability to supply a single address and  
conduct up to four WRITE operations without reasserting the  
address inputs. ADV/LD must be driven LOW in order to load  
the initial address, as described in the Single Write Access  
section above. When ADV/LD is driven HIGH on the subse-  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Linear Burst Address Table (MODE = GND)  
quent clock rise, the chip enables (CE , CE , and CE ) and  
1
2
3
WE inputs are ignored and the burst counter is incremented.  
The correct BW (BW for CY7C1354C and BW for  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
a,b,c,d  
a,b  
CY7C1356C) inputs must be driven in each cycle of the burst  
write in order to write the correct bytes of data.  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
01  
10  
11  
00  
Sleep Mode  
10  
11  
11  
00  
00  
01  
01  
10  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min.  
Max.  
50  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
ZZ > V 0.2V  
DDZZ  
2t  
ZZS  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
ZZ Inactive to exit sleep current  
0
ns  
RZZI  
Truth Table[2, 3, 4, 5, 6, 7, 8]  
Address  
Used  
Operation  
Deselect Cycle  
CE ZZ ADV/LD WE BWx OE CEN CLK  
DQ  
None  
None  
H
X
L
L
L
L
L
L
L
L
L
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L-H  
L-H  
Tri-State  
Tri-State  
Continue Deselect Cycle  
Read Cycle (Begin Burst)  
Read Cycle (Continue Burst)  
NOP/Dummy Read (Begin Burst)  
Dummy Read (Continue Burst)  
Write Cycle (Begin Burst)  
Write Cycle (Continue Burst)  
External  
Next  
L-H Data Out (Q)  
L-H Data Out (Q)  
X
L
H
L
L
External  
Next  
H
H
X
X
L-H  
L-H  
L-H  
L-H  
Tri-State  
Tri-State  
X
L
H
L
External  
Next  
Data In (D)  
Data In (D)  
X
H
X
L
Notes:  
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =  
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.  
3. Write is defined by WE and BW . See Write Cycle Description table for details.  
X
4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.  
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.  
6. CEN = H inserts wait states.  
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE  
X
is inactive or when the device is deselected, and DQs = data when OE is active.  
Document #: 38-05538 Rev. *G  
Page 8 of 28  
CY7C1354C  
CY7C1356C  
Truth Table[2, 3, 4, 5, 6, 7, 8]  
Address  
Used  
Operation  
NOP/WRITE ABORT (Begin Burst)  
WRITE ABORT (Continue Burst)  
IGNORE CLOCK EDGE (Stall)  
SLEEP MODE  
CE ZZ ADV/LD WE BWx OE CEN CLK  
DQ  
Tri-State  
Tri-State  
-
None  
Next  
L
X
X
X
L
L
L
H
X
X
L
X
X
X
H
H
X
X
X
X
X
X
L
L
L-H  
L-H  
L-H  
X
Current  
None  
L
H
X
H
Tri-State  
Partial Write Cycle Description[2, 3, 4, 9]  
Function (CY7C1354C)  
Read  
WE  
BW  
BW  
BW  
BW  
a
d
c
b
H
X
X
H
H
H
H
L
X
H
H
L
X
H
L
Write –No bytes written  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
Write Byte a – (DQ and DQP )  
a
a
Write Byte b – (DQ and DQP )  
H
L
b
b
Write Bytes b, a  
Write Byte c – (DQ and DQP )  
L
H
H
L
H
L
c
c
Write Bytes c, a  
Write Bytes c, b  
Write Bytes c, b, a  
L
L
H
L
L
L
Write Byte d – (DQ and DQP )  
H
H
H
H
L
H
H
L
H
L
d
d
Write Bytes d, a  
Write Bytes d, b  
Write Bytes d, b, a  
Write Bytes d, c  
Write Bytes d, c, a  
Write Bytes d, c, b  
Write All Bytes  
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]  
Function (CY7C1356C)  
Read  
WE  
H
L
BW  
BW  
x
b
a
x
H
H
L
Write – No Bytes Written  
Write Byte a (DQ and DQP  
H
L
L
a
a)  
Write Byte b – (DQ and DQP  
L
H
L
b
b)  
Write Both Bytes  
L
L
Note:  
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.  
X
Document #: 38-05538 Rev. *G  
Page 9 of 28  
CY7C1354C  
CY7C1356C  
Test MODE SELECT (TMS)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
The CY7C1354C/CY7C1356C incorporates a serial boundary  
scan test access port (TAP) in the BGA package only. The  
TQFP package does not offer this functionality. This part  
operates in accordance with IEEE Standard 1149.1-1900, but  
doesn’t have the set of functions required for full 1149.1  
compliance. These functions from the IEEE specification are  
excluded because their inclusion places an added delay in the  
critical speed path of the SRAM. Note the TAP controller  
functions in a manner that does not conflict with the operation  
of other devices using 1149.1 fully compliant TAPs. The TAP  
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.  
Test Data-In (TDI)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. TDI  
is internally pulled up and can be unconnected if the TAP is  
unused in an application. TDI is connected to the most signif-  
icant bit (MSB) of any register. (See Tap Controller Block  
Diagram.)  
The CY7C1354C/CY7C1356C contains a TAP controller,  
instruction register, boundary scan register, bypass register,  
and ID register.  
Test Data-Out (TDO)  
Disabling the JTAG Feature  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull-up resistor. TDO should be  
DD  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.  
TAP Controller Block Diagram  
0
Bypass Register  
TAP Controller State Diagram  
2
1
0
0
0
TEST-LOGIC  
1
Selection  
Circuitry  
RESET  
0
Instruction Register  
31 30 29  
Identification Register  
Selection  
Circuitry  
TDI  
TDO  
.
.
.
2
1
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
x
.
.
.
.
.
2
1
1
1
CAPTURE-DR  
CAPTURE-IR  
Boundary Scan Register  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
TCK  
TMS  
1
1
EXIT1-DR  
EXIT1-IR  
TAP CONTROLLER  
0
0
PAUSE-DR  
0
PAUSE-IR  
0
1
1
Performing a TAP Reset  
0
0
EXIT2-DR  
1
EXIT2-IR  
1
A RESET is performed by forcing TMS HIGH (V ) for five  
DD  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
UPDATE-DR  
UPDATE-IR  
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
TAP Registers  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Instruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
Document #: 38-05538 Rev. *G  
Page 10 of 28  
CY7C1354C  
CY7C1356C  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
through the instruction register through the TDI and TDO balls.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
EXTEST  
EXTEST is a mandatory 1149.1 instruction which is to be  
executed whenever the instruction register is loaded with all  
0s. EXTEST is not implemented in this SRAM TAP controller,  
and therefore this device is not compliant to 1149.1. The TAP  
controller does recognize an all-0 instruction.  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
When an EXTEST instruction is loaded into the instruction  
register, the SRAM responds as if a SAMPLE/PRELOAD  
instruction has been loaded. There is one difference between  
the two instructions. Unlike the SAMPLE/PRELOAD  
instruction, EXTEST places the SRAM outputs in a High-Z  
state.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
IDCODE  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
will undergo a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This will not harm  
the device, but there is no guarantee as to the value that will  
be captured. Repeatable results may not be possible.  
TAP Instruction Set  
Overview  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
hold times (t and t ). The SRAM clock input might not be  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK# captured in the  
boundary scan register.  
The TAP controller cannot be used to load address data or  
control signals into the SRAM and cannot preload the I/O  
buffers. The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of  
SAMPLE/PRELOAD; rather, it performs a capture of the I/O  
ring when these instructions are executed.  
CS  
CH  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
Document #: 38-05538 Rev. *G  
Page 11 of 28  
CY7C1354C  
CY7C1356C  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
prior to the selection of another boundary scan test operation.  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
[10, 11]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes:  
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05538 Rev. *G  
Page 12 of 28  
CY7C1354C  
CY7C1356C  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ................................................ V to 3.3V  
Input pulse levels.................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.5V  
1.25V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
[12]  
(0°C < TA < +70°C; V = 3.3V ±0.165V unless otherwise noted)  
DD  
Parameter  
Description  
Test Conditions  
Min.  
2.4  
2.0  
2.9  
2.1  
Max.  
Unit  
V
V
V
V
V
V
V
Output HIGH Voltage  
I
I
I
= –4.0 mA, V  
= –1.0 mA, V  
= –100 µA  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
V
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
V
V
V
V
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
V
OH2  
OL1  
OL2  
IH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
I
= 8.0 mA  
= 100 µA  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
V
I
V
V
2.0  
1.7  
V
V
+ 0.3  
V
DD  
DD  
+ 0.3  
V
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Identification Register Definitions  
Instruction Field  
Revision Number (31:29)  
Cypress Device ID (28:12)  
Cypress JEDEC ID (11:1)  
ID Register Presence (0)  
CY7C1354C  
000  
CY7C1356C  
Description  
Reserved for version number.  
000  
[13]  
01011001000100110 01011001000010110 Reserved for future use.  
00000110100  
1
00000110100  
1
Allows unique identification of SRAM vendor.  
Indicate the presence of an ID register.  
Notes:  
12. All voltages referenced to V (GND).  
SS  
13. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05538 Rev. *G  
Page 13 of 28  
CY7C1354C  
CY7C1356C  
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Instruction  
3
3
Bypass  
1
1
ID  
32  
69  
69  
32  
69  
69  
Boundary Scan Order (119-ball BGA package)  
Boundary Scan Order (165-ball FBGA package)  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and  
TDO. Forces all SRAM outputs to High-Z state.  
IDCODE  
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This  
operation does not affect SRAM operation.  
SAMPLE Z  
010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011 Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scanregister between TDI and TDO.  
Does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101 Do Not Use: This instruction is reserved for future use.  
110 Do Not Use: This instruction is reserved for future use.  
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.  
Document #: 38-05538 Rev. *G  
Page 14 of 28  
CY7C1354C  
CY7C1356C  
Boundary Scan Exit Order (256K × 36)  
Boundary Scan Exit Order (256K × 36) (continued)  
Bit #  
1
119-ball ID  
K4  
H4  
M4  
F4  
165-ball ID  
B6  
Bit #  
44  
119-ball ID  
165-ball ID  
L2  
K1  
N2  
N1  
M2  
L1  
K2  
J2  
2
B7  
45  
3
A7  
46  
M2  
M1  
L1  
K1  
J1  
4
B8  
47  
5
B4  
G4  
C3  
B3  
D6  
H7  
G6  
E6  
D7  
E7  
F6  
A8  
48  
6
A9  
49  
7
B10  
A10  
C11  
E10  
F10  
G10  
D10  
D11  
E11  
F11  
G11  
H11  
J10  
K10  
L10  
M10  
J11  
K11  
L11  
M11  
N11  
R11  
R10  
P10  
R9  
50  
K2  
8
51  
Not Bonded  
(Preset to 1)  
Not Bonded  
(Preset to 1)  
9
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
H1  
G2  
E2  
D1  
H2  
G1  
F2  
E1  
D2  
C2  
A2  
E4  
B2  
L3  
G2  
F2  
E2  
D2  
G1  
F1  
E1  
D1  
C1  
B2  
A2  
A3  
B3  
B4  
A4  
A5  
B5  
A6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
G7  
H6  
T7  
K7  
L6  
N6  
P7  
N7  
M6  
L7  
G3  
G5  
L5  
K6  
P6  
T4  
B6  
A3  
C5  
B5  
A5  
C6  
A6  
P4  
N4  
R6  
T5  
P9  
R8  
P8  
R6  
P6  
R4  
P4  
T3  
R3  
R2  
R3  
P2  
P1  
P3  
R1  
N1  
L2  
Document #: 38-05538 Rev. *G  
Page 15 of 28  
CY7C1354C  
CY7C1356C  
Boundary Scan Exit Order (512K × 18)  
Boundary Scan Exit Order (512K × 18) (continued)  
Bit #  
1
119-ball ID  
165-ball ID  
B6  
Bit #  
39  
119-ball ID  
165-ball ID  
K4  
H4  
M4  
F4  
B4  
G4  
C3  
B3  
T2  
T3  
R2  
R3  
R3  
P3  
R1  
2
B7  
40  
3
A7  
41  
4
B8  
42  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
5
A8  
43  
44  
45  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
6
A9  
7
B10  
A10  
A11  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
8
9
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
10  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
46  
47  
48  
49  
50  
51  
P2  
N1  
M2  
L1  
N1  
M1  
L1  
K1  
J1  
11  
12  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
K2  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
D6  
E7  
F6  
G7  
H6  
T7  
K7  
L6  
C11  
D11  
E11  
F11  
G11  
H11  
J10  
K10  
L10  
M10  
Not Bonded  
(Preset to 1)  
Not Bonded  
(Preset to 1)  
52  
53  
54  
55  
56  
H1  
G2  
E2  
D1  
G2  
F2  
E2  
D2  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
N6  
P7  
57  
58  
59  
60  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
24  
25  
26  
27  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
61  
62  
63  
64  
65  
C2  
A2  
E4  
B2  
B2  
A2  
A3  
B3  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0)  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
T6  
A3  
C5  
B5  
A5  
C6  
A6  
P4  
N4  
R6  
T5  
R11  
R10  
P10  
R9  
P9  
Not Bonded  
(Preset to 0  
Not Bonded  
(Preset to 0)  
66  
67  
G3  
Not Bonded  
(Preset to 0)  
Not Bonded  
(Preset to 0  
A4  
R8  
P8  
68  
69  
L5  
B6  
B5  
A6  
R6  
P6  
R4  
P4  
Document #: 38-05538 Rev. *G  
Page 16 of 28  
CY7C1354C  
CY7C1356C  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
Range  
Temperature  
V
V
DDQ  
DDQ  
DD  
DD  
DC to Outputs in Tri-State................... –0.5V to V  
+ 0.5V  
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%  
to V  
DDQ  
DD  
Industrial  
–40°C to +85°C  
[14, 15]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
V
3.6  
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
V
DDQ  
DD  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
for 3.3V I/O, I = 4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = 1.0 mA  
2.0  
V
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
DD  
+ 0.3V  
0.8  
V
[16]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
V
IL  
0.7  
V
Input Leakage Current GND V V  
except ZZ and MODE  
5
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
250  
220  
180  
130  
120  
110  
40  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
CYC  
MAX  
I
Automatic CE  
Power-down  
Current—TTL Inputs  
Max. V , Device Deselected, 4-ns cycle, 250 MHz  
DD  
SB1  
V
V or V V , f = f  
IN IN IL MAX  
IH  
= 1/t  
CYC  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
I
I
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0  
Max. V , Device Deselected, All speed grades  
DD  
SB2  
V
0.3V or V > V  
0.3V,  
IN  
IN  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
Max. V , Device Deselected, 4-ns cycle, 250 MHz  
120  
110  
100  
40  
mA  
mA  
mA  
mA  
SB3  
DD  
V
0.3V or V > V  
0.3V,  
IN  
IN  
DDQ  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
= 1/t  
MAX  
CYC  
I
Automatic CE  
Max. V , Device Deselected, All speed grades  
DD  
SB4  
Power-down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH  
IN  
IL  
Notes:  
14. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
15. T  
: Assumes a linear ramp from 0V to V  
(min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
IH  
DD  
DDQ  
DD  
DD  
16. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05538 Rev. *G  
Page 17 of 28  
CY7C1354C  
CY7C1356C  
Capacitance[16]  
100 TQFP  
Max.  
119 BGA  
Max.  
165 FBGA  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
C
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
5
5
5
5
7
5
5
7
IN  
A
V
= 3.3V V  
= 2.5V  
DD  
DDQ  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
pF  
Thermal Resistance[16]  
100 TQFP  
119 BGA  
Max.  
165 FBGA  
Max.  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures for  
measuring thermal impedance,  
per EIA/JESD51.  
29.41  
34.1  
16.8  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
6.13  
14.0  
3.0  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
5 pF  
R = 351Ω  
1 ns  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
V = 1.5V  
T
(a)  
(b)  
(c)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
5 pF  
R = 1538Ω  
1 ns  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
V = 1.25V  
T
(a)  
(b)  
(c)  
Document #: 38-05538 Rev. *G  
Page 18 of 28  
CY7C1354C  
CY7C1356C  
[18, 19]  
Switching Characteristics Over the Operating Range  
–250  
–200  
–166  
Parameter  
Description  
(typical) to the First Access Read or Write  
CC  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
[17]  
t
V
1
1
1
ms  
Power  
Clock  
t
Clock Cycle Time  
4.0  
5
6
ns  
MHz  
ns  
CYC  
F
Maximum Operating Frequency  
Clock HIGH  
250  
2.8  
200  
3.2  
166  
3.5  
MAX  
t
t
t
t
1.8  
1.8  
2.0  
2.0  
2.4  
2.4  
CH  
Clock LOW  
ns  
CL  
OE LOW to Output Valid  
ns  
EOV  
CLZ  
[20, 21, 22]  
Clock to Low-Z  
1.25  
1.5  
1.5  
ns  
Output Times  
t
t
t
t
t
t
t
Data Output Valid after CLK Rise  
OE LOW to Output Valid  
2.8  
2.8  
3.2  
3.2  
3.5  
3.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
EOV  
DOH  
CHZ  
CLZ  
Data Output Hold after CLK Rise  
1.25  
1.25  
1.25  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
[20, 21, 22]  
Clock to High-Z  
2.8  
2.8  
3.2  
3.2  
3.5  
3.5  
[20, 21, 22]  
Clock to Low-Z  
[20, 21, 22]  
OE HIGH to Output High-Z  
EOHZ  
EOLZ  
[20, 21, 22]  
0
0
0
OE LOW to Output Low-Z  
Set-up Times  
t
t
t
t
t
t
Address Set-up before CLK Rise  
Data Input Set-up before CLK Rise  
CEN Set-up before CLK Rise  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
DS  
CENS  
WES  
ALS  
CES  
WE, BW Set-up before CLK Rise  
x
ADV/LD Set-up before CLK Rise  
Chip Select Set-up  
Hold Times  
t
t
t
t
t
t
Address Hold after CLK Rise  
Data Input Hold after CLK Rise  
CEN Hold after CLK Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
DH  
CENH  
WEH  
ALH  
CEH  
WE BW Hold after CLK Rise  
,
x
ADV/LD Hold after CLK Rise  
Chip Select Hold after CLK Rise  
Notes:  
17. This part has a voltage regulator internally; t  
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be  
DD  
power  
initiated.  
18. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
20. t , t , t , and t are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ EOLZ  
EOHZ  
21. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
EOHZ  
EOLZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
22. This parameter is sampled and not 100% tested.  
Document #: 38-05538 Rev. *G  
Page 19 of 28  
CY7C1354C  
CY7C1356C  
Switching Waveforms  
[23, 24, 25]  
Read/Write Timing  
1
2
3
4
5
6
7
8
9
10  
t
CYC  
t
CLK  
t
t
t
CENS CENH  
CL  
CH  
CEN  
t
t
CES  
CEH  
CE  
ADV/LD  
WE  
BWX  
A1  
A2  
A4  
CO  
A3  
A5  
A6  
A7  
ADDRESS  
t
t
t
t
DS  
DH  
t
t
t
DOH  
OEV  
CLZ  
CHZ  
t
t
AS  
AH  
Data  
D(A1)  
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6  
-Out (DQ)  
t
OEHZ  
t
DOH  
t
OELZ  
OE  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
23. For this waveform ZZ is tied low.  
24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.  
Document #: 38-05538 Rev. *G  
Page 20 of 28  
CY7C1354C  
CY7C1356C  
Switching Waveforms (continued)  
NOP,STALL and DESELECT Cycles[23, 24, 26]  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BWX  
A1  
A2  
A3  
A4  
A5  
ADDRESS  
t
CHZ  
D(A4)  
D(A1)  
Q(A2)  
Q(A3)  
Q(A5)  
Data  
In-Out (DQ)  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
Note:  
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
Document #: 38-05538 Rev. *G  
Page 21 of 28  
CY7C1354C  
CY7C1356C  
Switching Waveforms (continued)  
ZZ Mode Timing[27, 28]  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.  
28. I/Os are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05538 Rev. *G  
Page 22 of 28  
CY7C1354C  
CY7C1356C  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1354C-166AXC  
CY7C1356C-166AXC  
CY7C1354C-166BGC  
CY7C1356C-166BGC  
Part and Package Type  
166  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1354C-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-166BGXC  
CY7C1354C-166BZC  
CY7C1356C-166BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1354C-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1356C-166BZXC  
CY7C1354C-166AXI  
CY7C1356C-166AXI  
CY7C1354C-166BGI  
CY7C1356C-166BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1354C-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-166BGXI  
CY7C1354C-166BZI  
CY7C1356C-166BZI  
CY7C1354C-166BZXI  
CY7C1356C-166BZXI  
CY7C1354C-200AXC  
CY7C1356C-200AXC  
CY7C1354C-200BGC  
CY7C1356C-200BGC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
200  
Commercial  
CY7C1354C-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-200BGXC  
CY7C1354C-200BZC  
CY7C1356C-200BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1354C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1356C-200BZXC  
CY7C1354C-200AXI  
CY7C1356C-200AXI  
CY7C1354C-200BGI  
CY7C1356C-200BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1354C-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-200BGXI  
CY7C1354C-200BZI  
CY7C1356C-200BZI  
CY7C1354C-200BZXI  
CY7C1356C-200BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05538 Rev. *G  
Page 23 of 28  
CY7C1354C  
CY7C1356C  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
250  
CY7C1354C-250AXC  
CY7C1356C-250AXC  
CY7C1354C-250BGC  
CY7C1356C-250BGC  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1354C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-250BGXC  
CY7C1354C-250BZC  
CY7C1356C-250BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1354C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1356C-250BZXC  
CY7C1354C-250AXI  
CY7C1356C-250AXI  
CY7C1354C-250BGI  
CY7C1356C-250BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1354C-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1356C-250BGXI  
CY7C1354C-250BZI  
CY7C1356C-250BZI  
CY7C1354C-250BZXI  
CY7C1356C-250BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05538 Rev. *G  
Page 24 of 28  
CY7C1354C  
CY7C1356C  
Package Diagrams  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Document #: 38-05538 Rev. *G  
Page 25 of 28  
CY7C1354C  
CY7C1356C  
Package Diagrams (continued)  
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.75 0.15(119X)  
Ø1.00(3X) REF.  
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27  
0.70 REF.  
A
3.81  
12.00  
7.62  
B
14.00 0.20  
0.15(4X)  
30° TYP.  
51-85115-*B  
SEATING PLANE  
C
Document #: 38-05538 Rev. *G  
Page 26 of 28  
CY7C1354C  
CY7C1356C  
Package Diagrams (continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
Ø0.25 M C A B  
-0.06  
Ø0.50
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
B
13.00 0.10  
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDECREFERENCE: MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device  
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders  
Document #: 38-05538 Rev. *G  
Page 27 of 28  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1354C  
CY7C1356C  
Document History Page  
Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture  
Document Number: 38-05538  
Orig. of  
REV.  
**  
ECN No. Issue Date Change  
Description of Change  
242032  
278130  
See ECN  
See ECN  
RKF  
RKF  
New data sheet  
*A  
Changed Boundary Scan order to match the B Rev of these devices  
Changed TQFP pkg to Lead-free TQFP in Ordering Information section  
Added comment of Lead-free BG and BZ packages availability  
*B  
*C  
284431  
320834  
See ECN  
See ECN  
VBL  
PCI  
Changed ISB1 and ISB3 from DC Characteristic table as follows  
ISB1: 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA  
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA  
Add BG and BZ pkg lead-free part numbers to ordering info section  
Changed 225 MHz to 250 MHz  
Address expansion pins/balls in the pinouts for all packages are modified as  
per JEDEC standard  
Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection  
Guide  
Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and  
JA  
JC  
6.13 °C/W respectively  
Changed Θ and Θ for BGA Package from 25 and 6 °C/W to 34.1 and  
JA  
JC  
14.0 °C/W respectively  
Changed Θ and Θ for FBGA Package from 27 and 6 °C/W to 16.8 and  
JA  
JC  
3.0 °C/W respectively  
Modified V test conditions  
V
OL, OH  
Added Lead-Free product information  
Updated Ordering Information Table  
Changed from Preliminary to Final  
*D  
351895  
See ECN  
PCI  
Changed I  
Updated Ordering Information Table  
from 35 to 40 mA  
SB2  
*E  
*F  
377095  
408298  
See ECN  
See ECN  
PCI  
Modified test condition in note# 15 from V  
< V to V  
V  
DDQ  
DD  
DDQ DD  
RXU  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed three-state to tri-state.  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in  
the Electrical Characteristics Table.  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
*G  
501793  
See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table.  
Updated the Ordering Information table.  
Document #: 38-05538 Rev. *G  
Page 28 of 28  

HP Hewlett Packard L1506 PX848AA User Manual
GE 2 9772 User Manual
Electrolux EAA005 User Manual
Dacor ER30G User Manual
Cres Cor CO151XW185B User Manual
Bosch Appliances Cooktop JGP641 User Manual
AT T EP5962 User Manual
Asus PR DLSW User Manual
Asus Computer Hardware H87I PLUS User Manual
AMX Modero MVP 5200i User Manual