Cypress NoBL CY7C1373D User Manual

CY7C1371D  
CY7C1373D  
18-Mbit (512K x 36/1M x 18)  
Flow-ThroughSRAMwithNoBLArchitecture  
Functional Description[1]  
Features  
• No Bus Latency(NoBL) architecture eliminates dead  
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18  
Synchronous flow through Burst SRAM designed specifically  
to support unlimited true back-to-back Read/Write operations  
with no wait state insertion. The CY7C1371D/CY7C1373D is  
equipped with the advanced No Bus Latency (NoBL) logic  
required to enable consecutive Read/Write operations with  
data being transferred on every clock cycle. This feature  
dramatically improves the throughput of data through the  
SRAM, especially in systems that require frequent Write-Read  
transitions.  
cycles between write and read cycles  
• Supports up to 133-MHz bus operations with zero wait  
states  
— Data is transferred on every clock  
• Pin-compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate the  
need to use OE  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• Registered inputs for flow through operation  
• Byte Write capability  
• 3.3V/2.5V IO power supply (V  
• Fast clock-to-output times  
)
DDQ  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the two or four Byte Write  
Select (BW ) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
X
Three synchronous Chip Enables (CE , CE , CE ) and an  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
• Available in JEDEC-standard Pb-free 100-pin TQFP,  
Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA  
package.  
• Three chip enables for simple depth expansion  
• Automatic Power down feature available using ZZ mode or  
CE deselect  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst Capability — linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
210  
175  
mA  
mA  
70  
70  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05556 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 09, 2007  
 
CY7C1371D  
CY7C1373D  
Pin Configurations  
100-Pin TQFP Pinout  
DQPC  
DQC  
DQC  
VDDQ  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
DQPB  
DQB  
DQB  
VDDQ  
VSS  
2
3
4
5
DQC  
6
DQB  
BYTE C  
BYTE B  
DQB  
DQC  
DQC  
DQC  
VSS  
7
8
DQB  
DQB  
VSS  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
DQC  
DQC  
NC  
VDDQ  
DQB  
DQB  
VSS  
CY7C1371D  
VDD  
NC  
NC  
VDD  
ZZ  
VSS  
DQD  
DQD  
VDDQ  
VSS  
DQA  
DQA  
VDDQ  
VSS  
DQD  
DQA  
DQA  
DQD  
BYTE D  
BYTE A  
DQD  
DQD  
VSS  
DQA  
DQA  
VSS  
VDDQ  
DQD  
DQD  
DQPD  
VDDQ  
DQA  
DQA  
DQPA  
Document #: 38-05556 Rev. *F  
Page 3 of 29  
CY7C1371D  
CY7C1373D  
Pin Configurations (continued)  
100-Pin TQFP Pinout  
NC  
1
NC  
2
NC  
3
VDDQ  
4
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A
NC  
NC  
VDDQ  
VSS  
NC  
VSS  
NC  
5
6
NC  
7
DQPA  
DQA  
DQA  
VSS  
VDDQ  
DQA  
DQA  
VSS  
DQB  
DQB  
VSS  
VDDQ  
DQB  
DQB  
NC  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
CY7C1373D  
BYTE A  
NC  
VDD  
NC  
BYTE B  
VDD  
ZZ  
VSS  
DQB  
DQB  
VDDQ  
VSS  
DQB  
DQB  
DQPB  
NC  
DQA  
DQA  
VDDQ  
VSS  
DQA  
DQA  
NC  
NC  
VSS  
VDDQ  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05556 Rev. *F  
Page 4 of 29  
CY7C1371D  
CY7C1373D  
Pin Configurations (continued)  
119-Ball BGA  
Pinout  
CY7C1371D (512K x 36)  
1
2
3
4
5
6
7
A
A
V
A
A
A
A
V
DDQ  
DDQ  
NC/576M  
NC/1G  
CE  
A
A
A
ADV/LD  
A
A
CE  
A
NC  
NC  
B
C
2
3
V
DD  
D
E
F
DQ  
DQ  
DQP  
DQ  
V
NC  
V
DQP  
DQ  
DQ  
DQ  
C
C
SS  
SS  
SS  
SS  
SS  
SS  
B
B
V
V
V
V
CE  
C
C
B
B
1
V
DQ  
DQ  
V
DDQ  
OE  
A
DDQ  
C
B
G
H
J
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
BW  
V
BW  
V
C
C
C
B
B
B
C
B
DQ  
DQ  
WE  
C
SS  
SS  
B
V
V
NC  
V
NC  
V
V
DDQ  
DDQ  
DD  
DD  
DD  
K
DQ  
DQ  
DQ  
DQ  
DQ  
V
CLK  
NC  
V
DQ  
DQ  
DQ  
DQ  
DQ  
D
D
D
SS  
SS  
A
A
A
DQ  
DQ  
L
M
N
BW  
V
BW  
A
D
D
D
A
A
A
D
V
V
V
V
DDQ  
CEN  
A1  
DDQ  
SS  
SS  
SS  
DQ  
V
V
DQ  
D
SS  
A
P
R
DQ  
DQP  
A
A0  
V
DQP  
A
DQ  
D
D
SS  
SS  
A
NC/144M  
NC  
MODE  
V
NC  
A
NC/288M  
ZZ  
DD  
NC/72M  
TMS  
A
A
A
NC/36M  
NC  
T
U
V
TDI  
TCK  
TDO  
V
DDQ  
DDQ  
CY7C1373D (1Mx 18)  
2
1
3
A
A
A
4
5
A
A
A
6
7
V
A
A
A
V
A
B
C
D
E
F
DDQ  
DDQ  
NC/576M  
NC/1G  
CE  
NC  
NC  
NC  
DQ  
ADV/LD  
CE  
A
2
3
A
V
DD  
DQ  
NC  
V
NC  
CE  
V
DQP  
B
SS  
SS  
SS  
SS  
A
NC  
DQ  
V
V
V
NC  
B
SS  
A
1
V
NC  
V
DQ  
V
DDQ  
OE  
A
DDQ  
SS  
A
NC  
DQ  
NC  
NC  
DQ  
G
H
J
BW  
V
B
A
B
DQ  
NC  
V
DQ  
NC  
WE  
B
SS  
SS  
A
V
V
NC  
V
NC  
V
V
DDQ  
DDQ  
DD  
DD  
DD  
K
NC  
DQ  
DQ  
V
CLK  
NC  
V
NC  
DQ  
DQ  
B
SS  
SS  
A
L
M
N
P
NC  
DQ  
NC  
NC  
BW  
B
A
A
V
V
V
V
V
NC  
DQ  
V
DDQ  
CEN  
A1  
DDQ  
B
SS  
SS  
SS  
SS  
DQ  
NC  
V
V
NC  
DQ  
B
SS  
SS  
A
NC  
DQP  
A0  
NC  
B
A
R
T
NC/144M  
NC/72M  
A
A
MODE  
A
V
NC  
A
A
A
NC/288M  
ZZ  
DD  
NC/36M  
TCK  
V
TMS  
TDI  
TDO  
NC  
V
U
DDQ  
DDQ  
Document #: 38-05556 Rev. *F  
Page 5 of 29  
CY7C1371D  
CY7C1373D  
Pin Configurations (continued)  
165-Ball FBGA Pinout  
CY7C1371D (512K x 36)  
1
2
A
3
CE1  
4
BWC  
5
BWB  
6
CE  
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPC  
DQC  
CEN  
WE  
VSS  
VSS  
ADV/LD  
A
B
C
D
3
A
CE2  
VDDQ  
VDDQ  
BWD  
VSS  
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQC  
VDDQ  
VDDQ  
NC  
DQPB  
DQB  
VDD  
DQB  
DQC  
DQC  
DQC  
DQC  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
E
F
DQC  
DQC  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQB  
DQB  
ZZ  
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQD  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
M
N
P
DQPD  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
A0  
MODE  
NC/36M  
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1373D (1M x 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
CE1  
4
BWB  
5
NC  
6
CE  
7
8
9
A
10  
A
11  
A
CEN  
WE  
VSS  
VSS  
ADV/LD  
A
B
C
D
3
A
CE2  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQB  
VDDQ  
VDDQ  
NC  
NC  
DQPA  
DQA  
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
E
F
NC  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQA  
DQA  
ZZ  
NC  
G
H
J
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
NC  
K
L
NC  
NC  
DQB  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
M
N
P
DQPB  
NC/144M NC/72M  
MODE NC/36M  
TDI  
TDO  
NC/288M  
A0  
A
A
TMS  
TCK  
A
A
A
A
R
Document #: 38-05556 Rev. *F  
Page 6 of 29  
CY7C1371D  
CY7C1373D  
Pin Definitions  
Name  
IO  
Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge of the  
A , A , A  
Input-  
0
1
Synchronous CLK. A are fed to the two-bit burst counter.  
[1:0]  
Input-  
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on  
BW , BW  
A
B
Synchronous the rising edge of CLK.  
BW , BW  
C
D
WE  
Input-  
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This  
Synchronous signal must be asserted LOW to initiate a write sequence.  
Input-  
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When  
ADV/LD  
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new  
address can be loaded into the device for an access. After being deselected, ADV/LD must be  
driven LOW to load a new address.  
CLK  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK  
is only recognized if CEN is active LOW.  
Input-  
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
CE  
CE  
1
2
Synchronous CE and CE to select/deselect the device.  
2
3
Input-  
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device.  
1
3
Input-  
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
CE  
3
Synchronous CE and CE to select/deselect the device.  
1
2
Input-  
Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block  
OE  
Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to  
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE  
is masked during the data portion of a write sequence, during the first clock when emerging from  
a deselected state, when the device has been deselected.  
Input-  
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the  
CEN  
ZZ  
Synchronous SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not  
deselect the device, use CEN to extend the previous cycle when required.  
Input-  
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition  
Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin  
has an internal pull down.  
IO-  
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by  
DQ  
s
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified  
by the addresses presented during the previous clock rise of the read cycle. The direction of the  
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,  
DQ and DQP  
are placed in a tri-state condition.The outputs are automatically tri-stated during  
s
[A:D]  
the data portion of a write sequence, during the first clock when emerging from a deselected state,  
and when the device is deselected, regardless of the state of OE.  
IO-  
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ .  
DQP  
s
X
Synchronous  
MODE  
Input Strap Pin Mode Input. Selects the burst order of the device.  
When tied to Gnd selects linear burst sequence. When tied to V or left floating selects interleaved  
DD  
burst sequence.  
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
IO Power  
Supply  
Power supply for the IO circuitry.  
DDQ  
V
Ground  
Ground for the device.  
SS  
Document #: 38-05556 Rev. *F  
Page 7 of 29  
CY7C1371D  
CY7C1373D  
Pin Definitions (continued)  
Name  
TDO  
IO  
Description  
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG  
output feature is not being used, this pin must be left unconnected. This pin is not available on TQFP  
Synchronous packages.  
TDI  
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not  
input  
being used, this pin can be left floating or connected to V through a pull up resistor. This pin is  
DD  
Synchronous not available on TQFP packages.  
TMS  
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not  
input  
being used, this pin can be disconnected or connected to V . This pin is not available on TQFP  
DD  
Synchronous packages.  
TCK  
NC  
JTAG-  
Clock  
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be  
connected to V . This pin is not available on TQFP packages.  
SS  
No Connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288M, 576M, 1G)are  
address expansion pins and are not internally connected to the die.  
is in progress and allows the requested data to propagate to  
the output buffers. The data is available within 6.5 ns  
Functional Overview  
The CY7C1371D/CY7C1373D is a synchronous flow through  
burst SRAM designed specifically to eliminate wait states  
during Write-Read transitions. All synchronous inputs pass  
through input registers controlled by the rising edge of the  
clock. The clock signal is qualified with the Clock Enable input  
signal (CEN). If CEN is HIGH, the clock signal is not recog-  
nized and all internal states are maintained. All synchronous  
operations are qualified with CEN. Maximum access delay  
(133-MHz device) provided OE is active LOW. After the first  
clock of the read access, the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW in  
order for the device to drive out the requested data. On the  
subsequent clock, another operation (Read/Write/Deselect)  
can be initiated. When the SRAM is deselected at clock rise  
by one of the chip enable signals, its output is tri-stated  
immediately.  
from the clock rise (t  
) is 6.5 ns (133-MHz device).  
CDV  
Burst Read Accesses  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
The CY7C1371D/CY7C1373D has an on-chip burst counter  
that allows the user the ability to supply a single address and  
conduct up to four Reads without reasserting the address  
inputs. ADV/LD must be driven LOW to load a new address  
into the SRAM, as described in the Single Read Access  
section above. The sequence of the burst counter is deter-  
mined by the MODE input signal. A LOW input on MODE  
selects a linear burst mode, a HIGH selects an interleaved  
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device is latched. The access  
can either be a read or write operation, depending on the  
status of the Write Enable (WE). BW can be used to conduct  
byte write operations.  
X
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
burst sequence. Both burst counters use A and A in the burst  
0
1
sequence, and wraps around when incremented sufficiently. A  
HIGH input on ADV/LD increments the internal burst counter  
regardless of the state of chip enable inputs or WE. WE is  
latched at the beginning of a burst cycle. Therefore, the type  
of access (Read or Write) is maintained throughout the burst  
sequence.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD must be driven LOW after the device has been  
deselected to load a new address for the next operation.  
Single Read Accesses  
Single Write Accesses  
A read access is initiated when these conditions are satisfied  
at clock rise:  
Write access are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
and CE are ALL asserted active, and (3) the write signal WE  
3
• CEN is asserted LOW  
is asserted LOW. The address presented to the address bus  
is loaded into the Address Register. The write signals are  
latched into the Control Logic block. The data lines are  
automatically tri-stated regardless of the state of the OE input  
signal. This allows the external logic to present the data on  
• CE , CE , and CE are ALL asserted active  
1
2
3
• The Write Enable input signal WE is deasserted HIGH  
• ADV/LD is asserted LOW.  
The address presented to the address inputs is latched into  
the Address Register and presented to the memory array and  
control logic. The control logic determines that a read access  
DQs and DQP .  
X
On the next clock rise the data presented to DQs and DQP  
(or a subset for byte write operations, see truth table for  
X
Document #: 38-05556 Rev. *F  
Page 8 of 29  
CY7C1371D  
CY7C1373D  
details) inputs is latched into the device and the write is  
complete. Additional accesses (Read/Write/Deselect) can be  
initiated on this cycle.  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
The data written during the Write operation is controlled by  
BW signals. The CY7C1371D/CY7C1373D provides byte  
X
the “sleep” mode. CE , CE , and CE , must remain inactive  
1
2
3
write capability that is described in the truth table. Asserting  
the Write Enable input (WE) with the selected Byte Write  
Select input selectively writes to only the desired bytes. Bytes  
not selected during a byte write operation remains unaltered.  
A synchronous self-timed write mechanism has been provided  
to simplify the write operations. Byte write capability has been  
included to greatly simplify Read/Modify/Write sequences,  
which can be reduced to simple byte write operations.  
for the duration of t  
after the ZZ input returns LOW.  
ZZREC  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
First  
Address  
A1: A0  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
Because the CY7C1371D/CY7C1373D is a common IO  
device, data must not be driven into the device while the  
outputs are active. The Output Enable (OE) can be deasserted  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
HIGH before presenting data to the DQs and DQP inputs.  
X
Doing so tri-states the output drivers. As a safety precaution,  
DQs and DQP are automatically tri-stated during the data  
X
portion of a write cycle, regardless of the state of OE.  
Burst Write Accesses  
Linear Burst Address Table (MODE = GND)  
The CY7C1371D/CY7C1373D has an on-chip burst counter  
that allows the user the ability to supply a single address and  
conduct up to four Write operations without reasserting the  
address inputs. ADV/LD must be driven LOW to load the initial  
address, as described in the Single Write Access section  
above. When ADV/LD is driven HIGH on the subsequent clock  
First  
Address  
A1: A0  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
rise, the Chip Enables (CE , CE , and CE ) and WE inputs are  
1
2
3
ignored and the burst counter is incremented. The correct  
BW inputs must be driven in each cycle of the burst write, to  
X
write the correct bytes of data.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min  
Max  
80  
Unit  
mA  
ns  
I
t
t
t
t
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Document #: 38-05556 Rev. *F  
Page 9 of 29  
CY7C1371D  
CY7C1373D  
Address  
Used  
Operation  
Deselect Cycle  
CE CE  
ZZ ADV/LD WE BW  
X
OE CEN CLK  
DQ  
CE  
X
H
X
X
L
1
2
3
None  
None  
H
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H Tri-State  
L->H Tri-State  
L->H Tri-State  
L->H Tri-State  
L->H Data Out (Q)  
L->H Data Out (Q)  
L->H Tri-State  
L->H Tri-State  
L->H Data In (D)  
L->H Data In (D)  
L->H Tri-State  
L->H Tri-State  
Deselect Cycle  
Deselect Cycle  
None  
L
Continue Deselect Cycle  
Read Cycle (Begin Burst)  
Read Cycle (Continue Burst)  
None  
X
H
X
H
X
H
X
H
X
X
X
H
L
External  
Next  
X
L
X
L
H
L
L
NOP/Dummy Read (Begin Burst) External  
H
H
X
X
X
X
X
X
Dummy Read (Continue Burst)  
Write Cycle (Begin Burst)  
Write Cycle (Continue Burst)  
NOP/Write Abort (Begin Burst)  
Write Abort (Continue Burst)  
Ignore Clock Edge (Stall)  
Sleep Mode  
Next  
External  
Next  
X
L
X
L
H
L
X
L
X
L
H
L
X
L
L
None  
H
H
X
X
Next  
X
X
X
X
X
X
H
X
X
X
X
X
Current  
None  
L->H  
X
Tri-State  
Partial Truth Table for Read/Write[2, 3, 9]  
Function (CY7C1371D)  
WE  
BW  
BW  
BW  
BW  
D
A
B
C
Read  
H
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Write No bytes written  
Write Byte A – (DQ and DQP )  
A
A
Write Byte B – (DQ and DQP )  
H
H
H
L
B
B
Write Byte C – (DQ and DQP )  
H
H
L
C
C
Write Byte D – (DQ and DQP )  
H
L
D
D
Write All Bytes  
L
Partial Truth Table for Read/Write[2, 3, 9]  
Function (CY7C1373D)  
WE  
BW  
BW  
A
B
Read  
H
L
L
L
L
X
H
L
X
H
H
L
Write - No bytes written  
Write Byte A – (DQ and DQP )  
A
A
Write Byte B – (DQ and DQP )  
H
L
B
B
Write All Bytes  
L
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = 0 signifies at least one Byte Write Select is active, BW = Valid signifies that the desired byte write  
X
X
selects are asserted, see truth table for details.  
3. Write is defined by BW , and WE. See truth table for Read/Write.  
X
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.  
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
X
6. CEN = H, inserts wait states.  
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE  
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.  
X
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write is based on which byte write is active.  
X
Document #: 38-05556 Rev. *F  
Page 10 of 29  
               
CY7C1371D  
CY7C1373D  
Test Data-In (TDI)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information on loading the instruction register, see TAP  
Controller State Diagram. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) of any register.  
(See Tap Controller Block Diagram.)  
The CY7C1371D/CY7C1373D incorporates a serial boundary  
scan test access port (TAP).This part is fully compliant with  
1149.1. The TAP operates using JEDEC-standard 3.3V or  
2.5V IO logic levels.  
The CY7C1371D/CY7C1373D contains a TAP controller,  
instruction register, boundary scan register, bypass register,  
and ID register.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
Test Data-Out (TDO)  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull up resistor. TDO must be  
DD  
left unconnected. Upon power up, the device is up in a reset  
state which does not interfere with the operation of the device.  
TAP Controller Block Diagram  
TAP Controller State Diagram  
0
TEST-LOGIC  
1
RESET  
0
Bypass Register  
1
1
1
2
1
0
0
0
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
Selection  
Circuitry  
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
0
0
TDI  
TDO  
1
1
.
.
.
2
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
x
.
.
.
.
.
2
1
1
1
Boundary Scan Register  
1
1
EXIT1-DR  
EXIT1-IR  
0
0
TCK  
PAUSE-DR  
1
0
PAUSE-IR  
1
0
TAP CONTROLLER  
TMS  
0
0
EXIT2-DR  
1
EXIT2-IR  
1
Performing a TAP Reset  
UPDATE-DR  
UPDATE-IR  
A RESET is performed by forcing TMS HIGH (V ) for five  
DD  
1
0
1
0
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
At power up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
TAP Registers  
Test Access Port (TAP)  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Test Mode Select (TMS)  
Instruction Register  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
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Page 11 of 29  
CY7C1371D  
CY7C1373D  
instruction if the controller is placed in a reset state as  
described in the previous section.  
access between the TDI and TDO in the shift-DR controller  
state.  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board level serial test data path.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
The IDCODE instruction is loaded into the instruction register  
upon power up or whenever the TAP controller is supplied a  
test logic reset state.  
(V ) when the BYPASS instruction is executed.  
SS  
SAMPLE Z  
Boundary Scan Register  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
The boundary scan register is loaded with the contents of the  
RAM IO ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the IO ring.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
undergoes a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This does not  
harm the device, but there is no guarantee as to the value that  
is captured. Repeatable results may not be possible.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture setup plus  
TAP Instruction Set  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
Overview  
Eight different instructions are possible with the three bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and must not be used. The other five instruc-  
tions are described in detail below.  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction after it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells pri-  
or to the selection of another boundary scan test operation.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
Document #: 38-05556 Rev. *F  
Page 12 of 29  
CY7C1371D  
CY7C1373D  
boundary scan path when multiple devices are connected  
together on a board.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR,” the value  
loaded into that shift-register cell latches into the preload  
register. When the EXTEST instruction is entered, this bit  
directly controls the output Q-bus pins. Note that this bit is  
preset HIGH to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
EXTEST Output Bus Tri-State  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
The boundary scan register has a special bit located at bit #85  
(for 119-BGA package) or bit #89 (for 165-fBGA package).  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the “Update-DR” state  
in the TAP controller, it directly controls the state of the output  
(Q-bus) pins, when the EXTEST is entered as the current  
instruction. When HIGH, it enables the output buffers to drive  
the output bus. When LOW, this bit places the output bus into  
a High-Z condition.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
Document #: 38-05556 Rev. *F  
Page 13 of 29  
CY7C1371D  
CY7C1373D  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min  
Max  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes:  
10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05556 Rev. *F  
Page 14 of 29  
   
CY7C1371D  
CY7C1373D  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ............................................... .V to 3.3V  
Input pulse level...................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels........................................ .1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.25V  
1.5V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
20pF  
ZO= 50Ω  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)  
Parameter  
Description  
Description  
= –4.0 mA  
Conditions  
Min  
2.4  
2.0  
2.9  
2.1  
Max  
Unit  
V
V
V
V
V
V
V
Output HIGH Voltage  
I
I
I
V
V
V
V
V
V
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
= –1.0 mA  
= –100 µA  
V
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
V
OH2  
OL1  
OL2  
IH  
V
I
I
I
= 8.0 mA  
= 1.0 mA  
= 100 µA  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
OL  
V
V
V
2.0  
1.7  
V
V
+ 0.3  
V
DD  
DD  
+ 0.3  
V
–0.5  
–0.3  
–5  
0.7  
V
IL  
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Note:  
12. All voltages referenced to V (GND).  
SS  
Document #: 38-05556 Rev. *F  
Page 15 of 29  
 
CY7C1371D  
CY7C1373D  
Identification Register Definitions  
CY7C1371D  
(512K X 36)  
CY7C1373D  
(1M X 18)  
Instruction Field  
Revision Number (31:29)  
Device Depth (28:24)  
Description  
000  
01011  
000  
Describes the version number  
Reserved for internal use  
01011  
001001  
010101  
Device Width (23:18)  
001001  
100101  
00000110100  
1
Defines memory type and architecture  
Defines width and density  
Cypress Device ID (17:12)  
Cypress JEDEC ID Code (11:1)  
ID Register Presence Indicator (0)  
00000110100 Allows unique identification of SRAM vendor  
Indicates the presence of an ID register  
1
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Instruction  
3
3
Bypass  
1
1
ID  
32  
85  
89  
32  
85  
89  
Boundary Scan Order (119-Ball BGA package)  
Boundary Scan Order (165-Ball FBGA package)  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000  
Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Document #: 38-05556 Rev. *F  
Page 16 of 29  
CY7C1371D  
CY7C1373D  
119-Ball BGA Boundary Scan Order [13, 14]  
Bit #  
1
Ball ID  
Bit #  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Ball ID  
F6  
Bit #  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
Ball ID  
G4  
A4  
G3  
C3  
B2  
B3  
A3  
C2  
A2  
B1  
C1  
D2  
E1  
F2  
Bit #  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
Ball ID  
L1  
H4  
T4  
T5  
T6  
R5  
L5  
2
E7  
D7  
H7  
G6  
E6  
D6  
C7  
B7  
C6  
A6  
C5  
B5  
G5  
B6  
D4  
B4  
F4  
M2  
N1  
3
4
P1  
5
K1  
6
L2  
7
R6  
U6  
R7  
T7  
P6  
N7  
M6  
L7  
N2  
P2  
8
9
R3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
T1  
R1  
T2  
L3  
R2  
K6  
P7  
N6  
L6  
G1  
H2  
D1  
E2  
G2  
H1  
J3  
T3  
L4  
N4  
P4  
K7  
J5  
M4  
A5  
K4  
E4  
Internal  
H6  
G7  
2K  
Notes:  
13. Balls which are NC (No Connect) are pre-set LOW.  
14. Bit# 85 is pre-set HIGH.  
Document #: 38-05556 Rev. *F  
Page 17 of 29  
   
CY7C1371D  
CY7C1373D  
165-Ball BGA Boundary Scan Order [13, 15]  
Bit #  
1
Ball ID  
N6  
Bit #  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
Ball ID  
D10  
C11  
A11  
B11  
A10  
B10  
A9  
Bit #  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Ball ID  
G1  
D2  
E2  
2
N7  
3
N10  
P11  
P8  
4
F2  
5
G2  
H1  
H3  
J1  
6
R8  
7
R9  
8
P9  
B9  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
C10  
A8  
K1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
L1  
B8  
M1  
J2  
A7  
B7  
K2  
B6  
L2  
A6  
M2  
N1  
N2  
P1  
B5  
A5  
A4  
B4  
R1  
R2  
P3  
B3  
A3  
A2  
R3  
P2  
H10  
G11  
F11  
E11  
D11  
G10  
F10  
E10  
B2  
C2  
R4  
P4  
B1  
A1  
N5  
P6  
C1  
D1  
R6  
Internal  
E1  
F1  
Note:  
15. Bit# 89 is pre-set HIGH.  
Document #: 38-05556 Rev. *F  
Page 18 of 29  
 
CY7C1371D  
CY7C1373D  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Range  
Temperature  
V
V
DDQ  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DD  
DDQ  
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
to V  
+ 0.5V  
DD  
Industrial  
–40°C to +85°C  
DDQ  
Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min  
Max  
Unit  
V
Power Supply Voltage  
IO Supply Voltage  
3.135  
3.135  
2.375  
2.4  
3.6  
V
V
DD  
V
V
V
V
V
I
for 3.3V IO  
for 2.5V IO  
for 3.3V IO, I = –4.0 mA  
V
DD  
DDQ  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
V
OH  
OL  
IH  
OH  
for 2.5V IO, I = –1.0 mA  
2.0  
V
OH  
for 3.3V IO, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V IO, I = 1.0 mA  
V
OL  
Input HIGH Voltage  
for 3.3V IO  
for 2.5V IO  
for 3.3V IO  
for 2.5V IO  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
+ 0.3V  
V
DD  
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
Input Leakage Current GND V V  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
µA  
I
I
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
7.5 ns cycle, 133 MHz  
10 ns cycle, 100 MHz  
210  
175  
140  
120  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
Automatic CE  
Power down  
Current—TTL Inputs  
V = Max, Device Deselected, 7.5 ns cycle, 133 MHz  
DD  
SB1  
SB2  
SB3  
SB4  
V
V or V V  
IN  
IH IN IL  
10 ns cycle, 100 MHz  
f = f  
, inputs switching  
MAX  
I
I
I
Automatic CE  
Power down  
Current—CMOS Inputs f = 0, inputs static  
V
V
= Max, Device Deselected, All speeds  
0.3V or V > V – 0.3V,  
70  
mA  
DD  
IN  
IN  
DD  
Automatic CE  
Power down  
Current—CMOS Inputs f = f  
V
V
= Max, Device Deselected, or 7.5 ns cycle, 133 MHz  
130  
110  
mA  
mA  
DD  
0.3V or V > V – 0.3V  
IN  
IN  
DDQ  
10 ns cycle, 100 MHz  
, inputs switching  
MAX  
Automatic CE  
Power down  
Current—TTL Inputs  
V
V
= Max, Device Deselected, All Speeds  
80  
mA  
DD  
V – 0.3V or V  
, f =  
IN  
DD  
IN 0.3V  
0, inputs static  
Notes:  
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
17. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05556 Rev. *F  
Page 19 of 29  
   
CY7C1371D  
CY7C1373D  
Capacitance[18]  
100 TQFP  
Package  
119 BGA  
Package  
165 FBGA  
Parameter  
Description  
Test Conditions  
Package  
Unit  
pF  
C
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
5
5
8
8
8
9
9
9
IN  
A
V
V
= 3.3V  
= 2.5V  
DD  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
IO  
DDQ  
pF  
Thermal Resistance[18]  
100 TQFP  
Package  
119 BGA  
Package  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures  
for measuring thermal  
impedance, according to  
EIA/JESD51.  
28.66  
23.8  
20.7  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
4.08  
6.2  
4.0  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V IO Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
5 pF  
R = 351Ω  
1ns  
1ns  
V = 1.5V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V IO Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
1ns  
1ns  
V = 1.25V  
T
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Note:  
18. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05556 Rev. *F  
Page 20 of 29  
 
CY7C1371D  
CY7C1373D  
Switching Characteristics Over the Operating Range  
133 MHz  
100 MHz  
Parameter  
Description  
Min  
Max  
Min  
Max  
Unit  
t
1
1
ms  
POWER  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
7.5  
2.1  
2.1  
10  
2.5  
2.5  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
6.5  
8.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CDV  
DOH  
CLZ  
2.0  
2.0  
2.0  
2.0  
Clock to Low-Z  
[20, 21, 22]  
Clock to High-Z  
4.0  
3.2  
5.0  
3.8  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
OE LOW to Output Low-Z  
0
0
OE HIGH to Output High-Z  
4.0  
5.0  
Setup Times  
t
t
t
t
t
t
Address Setup Before CLK Rise  
ADV/LD Setup Before CLK Rise  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ALS  
WES  
CENS  
DS  
WE, BW Setup Before CLK Rise  
X
CEN Setup Before CLK Rise  
Data Input Setup Before CLK Rise  
Chip Enable Setup Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADV/LD Hold After CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ALH  
WEH  
CENH  
DH  
WE, BW Hold After CLK Rise  
X
CEN Hold After CLK Rise  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes:  
19. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation  
DD  
POWER  
can be initiated.  
20. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
21. At any voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same data bus.  
CLZ  
OEHZ  
OELZ  
CHZ  
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve  
High-Z prior to Low-Z under the same system conditions.  
22. This parameter is sampled and not 100% tested.  
23. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05556 Rev. *F  
Page 21 of 29  
           
CY7C1371D  
CY7C1373D  
Switching Waveforms  
Read/Write Waveforms  
t
1
2
3
4
5
6
7
8
9
10  
CYC  
t
CLK  
t
t
t
t
t
CENS  
CES  
CENH  
CEH  
CL  
CH  
CEN  
CE  
ADV/LD  
W E  
BW  
X
A1  
A2  
A4  
A3  
A5  
A6  
A7  
ADDRESS  
DQ  
t
CDV  
t
t
AS  
AH  
t
t
t
t
CHZ  
DOH  
OEV  
CLZ  
D(A1)  
t
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
D(A7)  
t
OEHZ  
t
DS  
DH  
t
DOH  
t
OELZ  
OE  
COM M AND  
W RITE  
D(A1)  
W RITE  
D(A2)  
BURST  
W RITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
W RITE  
D(A5)  
READ  
Q(A6)  
W RITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
For this waveform ZZ is tied LOW.  
25.  
26. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.  
Document #: 38-05556 Rev. *F  
Page 22 of 29  
     
CY7C1371D  
CY7C1373D  
Switching Waveforms (continued)  
[25, 26, 28]  
NOP, STALL AND DESELECT Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BW [A:D]  
ADDRESS  
A1  
A2  
A3  
A4  
A5  
t
CHZ  
D(A1)  
Q(A2)  
Q(A3)  
D(A4)  
Q(A5)  
DQ  
t
DOH  
COMMAND  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
Note:  
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.  
Document #: 38-05556 Rev. *F  
Page 23 of 29  
 
CY7C1371D  
CY7C1373D  
Switching Waveforms (continued)  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.  
30. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05556 Rev. *F  
Page 24 of 29  
   
CY7C1371D  
CY7C1373D  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Part and Package Type  
133 CY7C1371D-133AXC  
CY7C1373D-133AXC  
CY7C1371D-133BGC  
CY7C1373D-133BGC  
CY7C1371D-133BGXC  
CY7C1373D-133BGXC  
CY7C1371D-133BZC  
CY7C1373D-133BZC  
CY7C1371D-133BZXC  
CY7C1373D-133BZXC  
CY7C1371D-133AXI  
CY7C1373D-133AXI  
CY7C1371D-133BGI  
CY7C1373D-133BGI  
CY7C1371D-133BGXI  
CY7C1373D-133BGXI  
CY7C1371D-133BZI  
CY7C1373D-133BZI  
CY7C1371D-133BZXI  
CY7C1373D-133BZXI  
100 CY7C1371D-100AXC  
CY7C1373D-100AXC  
CY7C1371D-100BGC  
CY7C1373D-100BGC  
CY7C1371D-100BGXC  
CY7C1373D-100BGXC  
CY7C1371D-100BZC  
CY7C1373D-100BZC  
CY7C1371D-100BZXC  
CY7C1373D-100BZXC  
CY7C1371D-100AXI  
CY7C1373D-100AXI  
CY7C1371D-100BGI  
CY7C1373D-100BGI  
CY7C1371D-100BGXI  
CY7C1373D-100BGXI  
CY7C1371D-100BZI  
CY7C1373D-100BZI  
CY7C1371D-100BZXI  
CY7C1373D-100BZXI  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
Commercial  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)  
lndustrial  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)  
Commercial  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)  
lndustrial  
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Document #: 38-05556 Rev. *F  
Page 25 of 29  
CY7C1371D  
CY7C1373D  
Package Diagrams  
Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
R 0.08 MIN.  
0.20 MAX.  
0°-7°  
3. DIMENSIONS IN MILLIMETERS  
0.60 0.15  
0.20 MIN.  
1.00 REF.  
51-85050-*B  
DETAIL  
A
Document #: 38-05556 Rev. *F  
Page 26 of 29  
CY7C1371D  
CY7C1373D  
Package Diagrams (continued)  
Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.75 0.15(119X)  
Ø1.00(3X) REF.  
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27  
0.70 REF.  
A
3.81  
12.00  
7.62  
B
14.00 0.20  
0.15(4X)  
30° TYP.  
SEATING PLANE  
C
51-85115-*B  
Document #: 38-05556 Rev. *F  
Page 27 of 29  
CY7C1371D  
CY7C1373D  
Package Diagrams (continued)  
Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
PIN 1 CORNER  
-0.06  
Ø0.50 (165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
13.00 0.10  
B
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDEC REFERENCE : MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device  
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05556 Rev. *F  
Page 28 of 29  
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1371D  
CY7C1373D  
Document History Page  
Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Architecture  
Document Number: 38-05556  
Issue  
Date  
Orig. of  
Change  
REV. ECN NO.  
Description of Change  
**  
254513 See ECN  
288531 See ECN  
RKF  
SYT  
New data sheet  
*A  
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for  
non-compliance with 1149.1  
Removed 117 Mhz Speed Bin  
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages  
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-  
mation  
*B  
326078 See ECN  
PCI  
Address expansion pins/balls in the pinouts for all packages are modified  
according to JEDEC standard  
Added description on EXTEST Output Bus Tri-State  
Changed description on the Tap Instruction Set Overview and Extest  
Changed Θ and Θ for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08  
JA  
JC  
°C/W respectively  
Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W  
JA  
JC  
respectively  
Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0  
JA  
JC  
°C/W respectively  
Modified V  
V
test conditions  
OL, OH  
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-  
mation  
Updated Ordering Information Table  
*C  
*D  
345117 See ECN  
416321 See ECN  
PCI  
Updated Ordering Information Table  
Changed from Preliminary to Final  
NXR  
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901  
North First Street” to “198 Champion Court”  
In the Partial Truth Table for Read/Write on page # 10, the BW of Write Byte A –  
A
(DQ and DQP ) and BW of Write Byte B – (DQ and DQP ) has been changed  
A
A
B
B
B
from H to L  
Changed the description of I from Input Load Current to Input Leakage Current  
X
on page# 20  
Changed the Ix current values of MODE on page # 20 from -5 µA and 30 µA  
to -30 µA and 5 µA  
Changed the Ix current values of ZZ on page # 20 from -30 µA and 5 µA  
to -5 µA and 30 µA  
Changed V < V to V < V on page # 20  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Updated Ordering Information Table  
*E  
*F  
475677 See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP AC  
TH TL  
TDOV  
Switching Characteristics table.  
Updated the Ordering Information table.  
1274734 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform  
Document #: 38-05556 Rev. *F  
Page 29 of 29  

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