Cypress CYDC128B08 User Manual

CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
1.8V 4k/8k/16k x 16 and 8k/16k x 8  
ConsuMoBL Dual-Port Static RAM  
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package  
Features  
• Full asynchronous operation  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
• Pin select for Master or Slave  
• Expandable data bus to 32 bits with Master/Slave chip  
select when using more than one device  
• 4/8/16k × 16 and 8/16k × 8 organization  
• High-speed access: 40 ns  
• On-chip arbitration logic  
• Ultra Low operating power  
• On-chip semaphore logic  
— Active: I = 15 mA (typical) at 55 ns  
CC  
• Input Read Registers and Output Drive Registers  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Commercial and industrial temperature ranges  
— Active: I = 25 mA (typical) at 40 ns  
CC  
— Standby: I  
= 2 µA (typical)  
SB3  
• Port-independent 1.8V, 2.5V, and 3.0V I/Os  
Selection Guide for VCC = 1.8V  
CYDC256B16, CYDC128B16,  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
CYDC064B16, CYDC128B08,  
CYDC064B08  
-40  
-55  
Port I/O Voltages (P1-P2)  
Maximum Access Time  
1.8V-1.8V  
1.8V-1.8V  
Unit  
ns  
40  
25  
2
55  
15  
2
Typical Operating Current  
Typical Standby Current for I  
Typical Standby Current for I  
mA  
µA  
SB1  
SB3  
2
2
µA  
Selection Guide for VCC = 2.5V  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
-40  
-55  
Port I/O Voltages (P1-P2)  
Maximum Access Time  
Typical Operating Current  
2.5V-2.5V  
2.5V-2.5V  
Unit  
ns  
40  
39  
6
55  
28  
6
mA  
µA  
Typical Standby Current for I  
SB1  
Typical Standby Current for I  
4
4
µA  
SB3  
Selection Guide for VCC = 3.0V  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
-40  
-55  
Port I/O Voltages (P1-P2)  
Maximum Access Time  
Typical Operating Current  
3.0V-3.0V  
3.0V-3.0V  
Unit  
ns  
40  
49  
7
55  
42  
7
mA  
µA  
Typical Standby Current for I  
SB1  
Typical Standby Current for I  
6
6
µA  
SB3  
Cypress Semiconductor Corporation  
Document #: 001-01638 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 25, 2007  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Pin Configurations [3, 4, 5, 6, 7]  
100-Pin TQFP (Top View)  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
A
A
A
A
A
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A
A
A
A
A
4L  
5L  
6L  
7L  
8L  
4R  
5R  
6R  
7R  
2
3
4
5
8R  
CE  
SEM  
INT  
6
CE  
R
L
7
SEM  
R
L
8
INT  
R
L
BUSY  
9
BUSY  
R
L
CYDC064B16  
CYDC128B16  
CYDC256B16  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
A
A
V
V
A
A
9L  
9R  
A
10L  
10R  
SS  
V
SS  
V
CC  
CC  
11R  
12R  
A
11L  
[3]  
[3]  
[6]  
A
12L  
[5]  
IRR0  
IRR1  
[7]  
M/S  
NC  
V
V
DDIOL  
DDIOR  
I/O  
0L  
I/O  
15R  
14R  
13R  
I/O  
1L  
I/O  
I/O  
V
I/O  
2L  
V
SS  
SS  
I/O  
3L  
I/O  
I/O  
I/O  
12R  
11R  
10R  
I/O  
4L  
24  
25  
I/O  
5L  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Notes:  
3. A12L and A12R are NC pins for CYDC064B16.  
4. IRR functionality is not supported for the CYDC256B16 device.  
5. This pin is A13L for CYDC256B16 device.  
6. This pin is A13R for CYDC256B16 device.  
7. Leave this pin unconnected. No trace or power component can be connected to this pin.  
Document #: 001-01638 Rev. *E  
Page 3 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
[7, 8, 9, 10]  
Pin Configurations (continued)  
100-pin TQFP (Top View)  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
A
A
A
A
A
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A
A
A
A
A
4L  
5L  
6L  
7L  
8L  
4R  
5R  
6R  
7R  
2
3
4
5
8R  
CE  
SEM  
INT  
6
CE  
R
L
7
SEM  
R
L
8
INT  
R
L
BUSY  
9
BUSY  
L
R
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
A
A
V
V
A
A
9L  
9R  
A
10L  
10R  
SS  
CYDC064B08  
CYDC128B08  
V
SS  
CC  
11L  
V
CC  
11R  
12R  
A
A
12L  
[9]  
[10]  
IRR0  
IRR1  
[11]  
M/S  
NC  
V
V
DDIOL  
DDIOR  
I/O  
0L  
V
V
V
V
V
V
V
SS  
SS  
SS  
SS  
SS  
SS  
SS  
I/O  
1L  
I/O  
2L  
V
SS  
I/O  
3L  
I/O  
4L  
24  
25  
I/O  
5L  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Notes:  
8. IRR functionality is not supported for the CYDC128B08 device.  
9. This pin is A13L for CYDC128B08 devices.  
10. This pin is A13R for CYDC128B08 devices.  
Document #: 001-01638 Rev. *E  
Page 4 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Pin Definitions  
Left Port  
Right Port  
Description  
CE  
CE  
Chip Enable  
L
R
R/W  
R/W  
Read/Write Enable  
Output Enable  
L
R
OE  
OE  
R
L
A
–A  
A
–A  
Address (A –A for 4k devices; A –A for 8k devices; A –A for 16k devices).  
11 12 13  
0L  
13L  
0R  
13R  
0
0
0
I/O –I/O  
I/O –I/O  
Data Bus Input/Output for x16 devices; I/O –I/O for x8 devices.  
0L  
15L  
0R  
15R  
0
7
SEM  
SEM  
Semaphore Enable  
Upper Byte Select (I/O –I/O for x16 devices; Not applicable for x8 devices).  
L
R
UB  
UB  
R
L
8
15  
LB  
LB  
Lower Byte Select (I/O –I/O for x16 devices; Not applicable for x8 devices).  
L
R
0
7
INT  
INT  
Interrupt Flag  
Busy Flag  
L
R
BUSY  
BUSY  
L
R
IRR0, IRR1  
Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.  
A13L, A13R for CYDC256B16 and CYDC128B08 devices.  
ODR0-ODR4  
SFEN  
Output Drive Register; These outputs are Open Drain.  
Special Function Enable  
Master or Slave Select  
M/S  
V
Core Power  
CC  
GND  
Ground  
V
Left Port I/O Voltage  
DDIOL  
V
Right Port I/O Voltage  
DDIOR  
NC  
No Connect. Leave this pin Unconnected.  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
Functional Description  
CYDC128B08, CYDC064B08 are available in 100-pin TQFP  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
packages.  
CYDC128B08, CYDC064B08 are low-power CMOS 4k,  
8k,16k x 16, and 8/16k x 8 dual-port static RAMs. Arbitration  
schemes are included on the devices to handle situations  
when multiple processors access the same piece of data. Two  
ports are provided, permitting independent, asynchronous  
access for reads and writes to any location in memory. The  
devices can be utilized as standalone 16-bit dual-port static  
RAMs or multiple devices can be combined in order to function  
as a 32-bit or wider master/slave dual-port static RAM. An M/S  
pin is provided for implementing 32-bit or wider memory appli-  
cations without the need for separate master and slave  
devices or additional discrete logic. Application areas include  
interprocessor/multiprocessor designs, communications  
status buffering, and dual-port video/graphics memory.  
Power Supply  
The core voltage (V ) can be 1.8V, 2.5V or 3.0V, as long as  
it is lower than or equal to the I/O voltage.  
CC  
Each port can operate on independent I/O voltages. This is  
determined by what is connected to the V  
pins. The supported I/O standards are 1.8V/2.5V LVCMOS  
and 3.0V LVTTL.  
and V  
DDIOL  
DDIOR  
Write Operation  
Data must be set up for a duration of t before the rising edge  
SD  
of R/W in order to guarantee a valid write. A write operation is  
controlled by either the R/W pin (see Write Cycle No. 1  
waveform) or the CE pin (see Write Cycle No. 2 waveform).  
Required inputs for non-contention operations are summa-  
rized in Table 1.  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two  
flags are provided on each port (BUSY and INT). BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port. The Interrupt flag  
(INT) permits communication between ports or systems by  
means of a mail box. The semaphores are used to pass a flag,  
or token, from one port to the other to indicate that a shared  
resource is in use. The semaphore logic is comprised of eight  
shared latches. Only one side can control the latch  
(semaphore) at any time. Control of a semaphore indicates  
that a shared resource is in use. An automatic power-down  
feature is controlled independently on each port by a Chip  
Enable (CE) pin.  
If a location is being written to by one port and the opposite  
port attempts to read that location, a port-to-port flowthrough  
delay must occur before the data is read on the output;  
otherwise the data read is not deterministic. Data will be valid  
on the port t  
after the data is presented on the other port.  
DDD  
Read Operation  
When reading the device, the user must assert both the OE  
and CE pins. Data will be available t after CE or t after  
ACE  
DOE  
OE is asserted. If the user wishes to access a semaphore flag,  
Document #: 001-01638 Rev. *E  
Page 5 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
then the SEM pin must be asserted instead of the CE pin, and  
OE must also be asserted.  
The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL,  
depending on the core voltage supply (V ). Refer to Table 3  
CC  
for Input Read Register operation.  
Interrupts  
IRR is not available in the CYDC256B16 and CYDC128B08,  
The upper two memory locations may be used for message  
passing. The highest memory location (FFF for the  
CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08,  
3FFF for the CYDC256B16 and CYDC128B08) is the mailbox  
for the right port and the second-highest memory location (FFE  
for the CYDC064B16, 1FFE for the CYDC128B16 and  
CYDC064B08, 3FFE for the CYDC256B16 and CYDC128B08)  
is the mailbox for the left port. When one port writes to the  
other port’s mailbox, an interrupt is generated to the owner.  
The interrupt is reset when the owner reads the contents of the  
mailbox. The message is user-defined.  
as the IRR pins are used as extra address pins A  
and A  
.
13L  
13R  
Output Drive Register  
The Output Drive Register (ODR) determines the state of up  
to five external binary state devices by providing a path to V  
for the external circuit. These outputs are Open Drain.  
SS  
The five external devices can operate at different voltages  
(1.5V V 3.5V) but the combined current cannot exceed  
DDIO  
40 mA (8 mA max for each external device). The status of the  
ODR bits are set using standard write accesses from either  
port to address x0001 with a “1” corresponding to on and “0”  
corresponding to off.  
Each port can read the other port’s mailbox without resetting  
the interrupt. The active state of the busy signal (to a port)  
prevents the port from setting the interrupt to the winning port.  
Also, an active busy to a port prevents that port from reading  
its own mailbox and, thus, resetting the interrupt to it.  
The status of the ODR bits can be read with a standard read  
access to address x0001. When SFEN = V , the ODR is active  
IL  
and address x0001 is not available for memory accesses.  
When SFEN = V , the ODR is inactive and address x0001 can  
IH  
If an application does not require message passing, do not  
connect the interrupt pin to the processor’s interrupt request  
input pin. On power up, an initialization program should be run  
and the interrupts for both ports must be read to reset them.  
be used for standard accesses.  
During reads and writes to ODR DQ<4:0> are valid and  
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive  
Register operation.  
The operation of the interrupts and their interaction with Busy  
are summarized in Table 2.  
Semaphore Operation  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
Busy  
CYDC128B08, CYDC064B08 provide eight semaphore  
latches, which are separate from the dual-port memory  
locations. Semaphores are used to reserve resources that are  
shared between the two ports. The state of the semaphore  
indicates that a resource is in use. For example, if the left port  
wants to request a given resource, it sets a latch by writing a  
zero to a semaphore location. The left port then verifies its  
success in setting the latch by reading it. After writing to the  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08, CYDC064B08 provide on-chip arbitration to  
resolve simultaneous memory location access (contention). If  
both ports’ CEs are asserted and an address match occurs  
within t of each other, the busy logic will determine which  
port has access. If t is violated, one port will definitely gain  
permission to the location, but it is not predictable which port  
will get that permission. BUSY will be asserted t  
address match or t  
PS  
PS  
after an  
BLA  
semaphore, SEM or OE must be deasserted for t  
before  
SOP  
after CE is taken LOW.  
BLC  
attempting to read the semaphore. The semaphore value will  
be available t + t after the rising edge of the  
SWRD  
DOE  
Master/Slave  
semaphore write. If the left port was successful (reads a zero),  
it assumes control of the shared resource, otherwise (reads a  
one) it assumes the right port has control and continues to poll  
the semaphore. When the right side has relinquished control  
of the semaphore (by writing a one), the left side will succeed  
in gaining control of the semaphore. If the left side no longer  
requires the semaphore, a one is written to cancel its request.  
A M/S pin is provided in order to expand the word width by  
configuring the device as either a master or a slave. The BUSY  
output of the master is connected to the BUSY input of the  
slave. This will allow the device to interface to a master device  
with no external components. Writing to slave devices must be  
delayed until after the BUSY input has settled (t  
or t  
),  
BLC  
BLA  
otherwise, the slave chip may begin a write cycle during a  
contention situation. When tied HIGH, the M/S pin allows the  
device to be used as a master and, therefore, the BUSY line  
is an output. BUSY can then be used to send the arbitration  
outcome to a slave.  
Semaphores are accessed by asserting SEM LOW. The SEM  
pin functions as a chip select for the semaphore latches (CE  
must remain HIGH during SEM LOW). A  
represents the  
0–2  
semaphore address. OE and R/W are used in the same  
manner as a normal memory access. When writing or reading  
a semaphore, the other address pins have no effect.  
Input Read Register  
When writing to the semaphore, only I/O is used. If a zero is  
The Input Read Register (IRR) captures the status of two  
external input devices that are connected to the Input Read  
pins.  
0
written to the left port of an available semaphore, a one will  
appear at the same semaphore address on the right port. That  
semaphore can now only be modified by the side showing zero  
(the left port in this case). If the left port now relinquishes  
control by writing a one to the semaphore, the semaphore will  
be set to one for both sides. However, if the right port had  
requested the semaphore (written a zero) while the left port  
had control, the right port would immediately own the  
semaphore as soon as the left port released it. Table 5 shows  
sample semaphore operations.  
The contents of the IRR read from address x0000 from either  
port. During reads from the IRR, DQ0 and DQ1 are valid bits  
and DQ<15:2> are don’t care. Writes to address x0000 are not  
allowed from either port.  
Address x0000 is not available for standard memory accesses  
when SFEN = V . When SFEN = V , address x0000 is  
IL  
IH  
available for memory accesses.  
Document #: 001-01638 Rev. *E  
Page 6 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
When reading a semaphore, all sixteen/eight data lines output  
the semaphore value. The read value is latched in an output  
register to prevent the semaphore from changing state during  
a write from the other port. If both ports attempt to access the  
CYDC128B08 consist of an array of 8k and 16k words of 8  
each of dual-port RAM cells, I/O and address lines, and control  
signals (CE, OE, R/W).These control pins permit independent  
access for reads or writes to any location in memory. To handle  
simultaneous writes/reads to the same location, a BUSY pin is  
provided on each port. Two Interrupt (INT) pins can be utilized  
for port-to-port communication. Two Semaphore (SEM)  
control pins are used for allocating shared resources. With the  
M/S pin, the devices can function as a master (BUSY pins are  
outputs) or as a slave (BUSY pins are inputs). The devices  
also have an automatic power-down feature controlled by CE.  
Each port is provided with its own output enable control (OE),  
which allows data to be read from the device.  
semaphore within t  
of each other, the semaphore will  
SPS  
definitely be obtained by one side or the other, but there is no  
guarantee which side will control the semaphore. On  
power-up, both ports should write “1” to all eight semaphores.  
Architecture  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08, CYDC064B08 consist of an array of 4k, 8k, or  
16k words of 16 dual-port RAM cells, I/O and address lines,  
and control signals (CE, OE, R/W). The CYDC064B08 and  
Table 1. Non-Contending Read/Write  
Inputs  
Outputs  
[11]  
CE  
H
X
L
R/W  
X
OE  
X
X
X
X
X
L
UB  
X
H
L
LB  
X
H
H
L
SEM I/O I/O  
I/O I/O  
Operation  
Deselected: Power-down  
Deselected: Power-down  
Write to Upper Byte Only  
Write to Lower Byte Only  
Write to Both Bytes  
8
15  
0
7
H
H
H
H
H
H
H
H
X
L
High Z  
High Z  
X
High Z  
High Z  
L
Data In  
High Z  
High Z  
L
L
H
L
Data In  
Data In  
High Z  
L
L
L
Data In  
Data Out  
High Z  
L
H
H
H
X
L
H
L
Read Upper Byte Only  
Read Lower Byte Only  
Read Both Bytes  
L
L
H
L
Data Out  
Data Out  
High Z  
L
L
L
Data Out  
High Z  
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled  
H
H
Data Out  
Data Out  
Data In  
Data Out  
Data Out  
Data In  
Read Data in Semaphore Flag  
Read Data in Semaphore Flag  
L
L
X
L
Write D  
into Semaphore Flag  
into Semaphore Flag  
IN0  
IN0  
X
X
H
H
L
Data In  
Data In  
Write D  
L
L
X
X
X
X
L
X
L
L
L
Not Allowed  
Not Allowed  
X
[12]  
Table 2. Interrupt Operation Example (Assumes BUSY = BUSY = HIGH)  
L
R
Left Port  
Right Port  
Function  
Set Right INT Flag  
R/W  
CE  
L
OE  
X
A
INT  
R/W  
CE  
X
OE  
X
A
INT  
L
L
L
0L–13L  
L
R
R
R
0R–13R  
R
[15]  
[14]  
L
X
X
X
3FFF  
X
X
X
L
X
L
R
[15]  
[13]  
Reset Right INT Flag  
X
X
X
X
X
L
L
3FFF  
3FFE  
X
H
R
[13]  
[14]  
[15]  
Set Left INT Flag  
X
X
L
L
X
X
X
L
[15]  
Reset Left INT Flag  
L
L
3FFE  
H
X
X
X
L
Notes:  
11. This column applies to x16 devices only.  
12. See Interrupts Functional Description for specific highest memory locations by device.  
13. If BUSY = L, then no change.  
R
14. If BUSY = L, then no change.  
L
15. See Functional Description for specific addresses by device.  
Document #: 001-01638 Rev. *E  
Page 7 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
[16, 19]  
Table 3. Input Read Register Operation  
SFEN  
CE  
L
R/W  
H
OE  
L
UB  
L
LB  
L
ADDR  
I/O I/O I/O I/O  
Mode  
Standard Memory Access  
IRR Read  
0
1
2
15  
[17]  
[17]  
H
L
x0000-Max VALID  
VALID  
[18]  
L
H
L
X
L
x0000  
VALID  
X
[20]  
Table 4. Output Drive Register  
SFEN  
CE  
L
R/W  
H
OE  
UB  
LB  
ADDR  
I/O I/O I/O I/O  
Mode  
0
4
5
15  
[21]  
[17]  
[17]  
[17]  
[17]  
H
L
L
X
L
L
x0000-Max VALID  
VALID  
Standard Memory Access  
[18]  
[20, 22]  
L
L
X
L
X
X
L
L
x0001  
x0001  
VALID  
VALID  
X
X
ODR Write  
[18]  
[20]  
L
H
ODR Read  
Table 5. Semaphore Operation Example  
Function I/O I/O Left I/O I/O Right  
Status  
0
15  
0
15  
No action  
1
0
0
1
1
0
1
1
1
0
1
1
Semaphore-free  
Left port writes 0 to semaphore  
Right port writes 0 to semaphore  
Left port writes 1 to semaphore  
Left port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 1 to semaphore  
Right port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 0 to semaphore  
1
1
0
0
1
1
0
1
1
1
Left Port has semaphore token  
No change. Right side has no write access to semaphore  
Right port obtains semaphore token  
No change. Left port has no write access to semaphore  
Left port obtains semaphore token  
Semaphore-free  
Right port has semaphore token  
Semaphore free  
Left port has semaphore token  
Semaphore-free  
Left port writes 1 to semaphore  
Notes:  
16. SFEN = V for IRR reads.  
IL  
17. UB or LB = V . If LB = V , then DQ<7:0> are valid. If UB = V then DQ<15:8> are valid.  
IL  
IL  
IL  
18. LB must be active (LB = V ) for these bits to be valid.  
IL  
19. SFEN active when either CE = V or CE = V . It is inactive when CE = CE = V .  
L
IL  
R
IL  
L
R
IH  
20. SFEN = V for ODR reads and writes.  
IL  
21. Output enable must be low (OE = V ) during reads for valid data to be output.  
IL  
22. During ODR writes data will also be written to the memory.  
Document #: 001-01638 Rev. *E  
Page 8 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Maximum Ratings[23]  
Output Current into Outputs (LOW)............................. 90 mA  
Static Discharge Voltage.......................................... > 2000V  
Latch-up Current.................................................... > 200 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature .................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Range  
Ambient Temperature  
V
CC  
Commercial  
0°C to +70°C  
1.8V ± 100 mV  
2.5V ± 100 mV  
3.0V ± 300 mV  
Supply Voltage to Ground Potential............... –0.5V to +3.3V  
DC Voltage Applied to  
Outputs in High-Z State..........................–0.5V to V + 0.5V  
CC  
Industrial  
–40°C to +85°C  
1.8V ± 100 mV  
2.5V ± 100 mV  
3.0V ± 300 mV  
[24]  
DC Input Voltage ...............................–0.5V to V + 0.5V  
CC  
Electrical Characteristics for VCC = 1.8V Over the Operating Range  
CYDC256B16,  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
P1 I/O  
P2 I/O  
Parameter  
Description  
Voltage Voltage Min.  
Typ. Max. Min.  
Typ. Max. Unit  
V
Output HIGH Voltage (I = –100 µA)  
1.8V (any port)  
V
– 0.2  
V
DDIO  
– 0.2  
V
OH  
OH  
DDIO  
Output HIGH Voltage (I = –2 mA)  
2.5V (any port)  
3.0V (any port)  
1.8V (any port)  
2.5V (any port)  
3.0V (any port)  
2.0  
2.0  
V
V
OH  
Output HIGH Voltage (I = –2 mA)  
2.1  
2.1  
OH  
V
Output LOW Voltage (I = 100 µA)  
0.2  
0.4  
0.4  
0.2  
0.2  
0.2  
0.2  
0.4  
0.4  
0.2  
0.2  
0.2  
V
V
V
V
V
V
V
OL  
OL  
Output HIGH Voltage (I = 2 mA)  
OL  
Output HIGH Voltage (I = 2 mA)  
OL  
V
ODR ODR Output LOW Voltage (I = 8 mA) 1.8V (any port)  
OL  
IH  
OL  
2.5V (any port)  
3.0V (any port)  
V
Input HIGH Voltage  
1.8V (any port)  
2.5V (any port)  
3.0V (any port)  
1.2  
1.7  
2.0  
V
1.2  
1.7  
2.0  
V
DDIO  
+ 0.2  
DDIO  
+ 0.2  
V
V
V
V
DDIO  
DDIO  
+ 0.3  
+ 0.3  
V
V
DDIO  
DDIO  
+ 0.2  
+ 0.2  
V
I
Input LOW Voltage  
1.8V (any port)  
2.5V (any port)  
3.0V (any port)  
–0.2  
–0.3  
–0.2  
–1  
0.4  
0.6  
0.7  
1
–0.2  
–0.3  
–0.2  
–1  
0.4  
0.6  
0.7  
1
V
IL  
V
V
Output Leakage Current  
1.8V  
2.5V  
3.0V  
1.8V  
2.5V  
3.0V  
1.8V  
2.5V  
3.0V  
1.8V  
2.5V  
3.0V  
µA  
µA  
µA  
µA  
µA  
µA  
OZ  
–1  
1
–1  
1
–1  
1
–1  
1
I
ODR ODR Output Leakage Current.  
–1  
1
–1  
1
CEX  
V
= V  
OUT  
DDIO  
–1  
1
–1  
1
–1  
1
–1  
1
Notes:  
23. The voltage on any input or I/O pin can not exceed the power pin during power-up.  
24. Pulse width < 20 ns.  
Document #: 001-01638 Rev. *E  
Page 9 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range  
CYDC256B16,  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
P1 I/O  
P2 I/O  
Parameter  
Description  
Input Leakage Current  
Voltage Voltage Min.  
Typ. Max. Min.  
Typ. Max. Unit  
I
1.8V  
2.5V  
3.0V  
1.8V  
1.8V  
2.5V  
3.0V  
1.8V  
–1  
–1  
–1  
1
1
–1  
1
1
µA  
µA  
µA  
mA  
IX  
–1  
–1  
1
1
I
I
Operating Current (V = Max.,  
Ind.  
25  
2
40  
15  
2
25  
CC  
CC  
I
= 0 mA) Outputs Disabled  
OUT  
Standby Current (Both Ports TTL Ind.  
1.8V  
1.8V  
6
6
µA  
SB1  
Level) CE and CE V – 0.2,  
L
R
CC  
SEM = SEM = V – 0.2, f = f  
L
R
CC  
MAX  
I
I
Standby Current (One Port TTL  
Ind.  
Ind.  
1.8V  
1.8V  
1.8V  
1.8V  
8.5  
2
18  
6
8.5  
2
14  
6
mA  
SB2  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Standby Current (Both Ports  
CMOS Level) CE & CE  
µA  
SB3  
L
R
V
V
0.2V, SEM and SEM >  
CC  
CC  
L
R
– 0.2V, f = 0  
I
Standby Current (One Port CMOS Ind.  
1.8V  
1.8V  
8.5  
18  
8.5  
14  
mA  
SB4  
[25]  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Notes:  
25. f  
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level  
MAX  
RC  
RC  
standby I  
.
SB3  
Document #: 001-01638 Rev. *E  
Page 10 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Electrical Characteristics for VCC = 2.5V Over the Operating Range  
CYDC256B16,  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
P1 I/O  
P2 I/O  
Parameter  
Description  
Output HIGH Voltage (I = –2 mA)  
Voltage Voltage Min.  
Typ. Max. Min.  
Typ. Max. Unit  
V
V
V
V
2.5V (any port)  
3.0V (any port)  
2.5V (any port)  
3.0V (any port)  
2.0  
2.1  
2.0  
2.1  
V
V
OH  
OL  
OL  
IH  
OH  
Output HIGH Voltage (I = –2 mA)  
OH  
Output LOW Voltage (I = 2 mA)  
0.4  
0.4  
0.2  
0.2  
0.4  
0.4  
0.2  
0.2  
V
V
V
V
V
OL  
Output LOW Voltage (I = 2 mA)  
OL  
ODR ODR Output LOW Voltage (I = 8 mA) 2.5V (any port)  
OL  
3.0V (any port)  
Input HIGH Voltage  
2.5V (any port)  
1.7  
2.0  
V
+ 0.3  
1.7  
2.0  
V
DDIO  
DDIO  
+ 0.3  
3.0V (any port)  
V
V
V
DDIO  
DDIO  
+ 0.2  
+ 0.2  
V
I
Input LOW Voltage  
2.5V (any port)  
3.0V (any port)  
–0.3  
–0.2  
–1  
0.6  
0.7  
1
–0.3  
–0.2  
–1  
0.6  
0.7  
1
V
V
IL  
Output Leakage Current  
2.5V  
3.0V  
2.5V  
3.0V  
2.5V  
3.0V  
2.5V  
2.5V  
3.0V  
2.5V  
3.0V  
2.5V  
3.0V  
2.5V  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
OZ  
–1  
1
–1  
1
I
I
ODR ODR Output Leakage Current.  
–1  
1
–1  
1
CEX  
V
= V  
OUT  
CC  
–1  
1
–1  
1
Input Leakage Current  
–1  
1
–1  
1
IX  
–1  
1
–1  
1
I
I
Operating Current (V = Max.,  
Ind.  
39  
6
55  
28  
6
40  
CC  
CC  
I
= 0 mA) Outputs Disabled  
OUT  
Standby Current (Both Ports TTL Ind.  
2.5V  
2.5V  
8
8
µA  
SB1  
Level) CE and CE V – 0.2,  
L
R
CC  
SEM = SEM = V – 0.2, f=f  
L
R
CC  
MAX  
I
I
Standby Current (One Port TTL  
Ind.  
Ind.  
2.5V  
2.5V  
2.5V  
2.5V  
21  
4
30  
6
18  
4
25  
6
mA  
SB2  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Standby Current (Both Ports  
CMOS Level) CE & CE  
µA  
SB3  
L
R
V
V
0.2V, SEM and SEM >  
CC  
CC  
L
R
– 0.2V, f = 0  
I
Standby Current (One Port CMOS Ind.  
2.5V  
2.5V  
21  
30  
18  
25  
mA  
SB4  
[25]  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Document #: 001-01638 Rev. *E  
Page 11 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Electrical Characteristics for 3.0V Over the Operating Range  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
P1 I/O  
P2 I/O  
Parameter  
Description  
Output HIGH Voltage (I = –2 mA)  
Voltage Voltage Min.  
Typ. Max. Min.  
Typ. Max. Unit  
V
V
V
V
3.0V (any port)  
3.0V (any port)  
2.1  
2.0  
2.1  
V
OH  
OL  
OL  
IH  
OH  
Output LOW Voltage (I = 2 mA)  
0.4  
0.2  
0.4  
0.2  
V
V
V
OL  
ODR ODR Output LOW Voltage (I = 8 mA) 3.0V (any port)  
OL  
Input HIGH Voltage  
3.0V (any port)  
V
2.0  
V
DDIO  
DDIO  
+ 0.2  
+ 0.2  
0.7  
1
V
I
Input LOW Voltage  
3.0V (any port)  
–0.2  
–1  
0.7  
1
–0.2  
–1  
V
IL  
Output Leakage Current  
3.0V  
3.0V  
3.0V  
3.0V  
µA  
µA  
OZ  
I
ODR ODR Output Leakage Current.  
–1  
1
–1  
1
CEX  
V
= V  
OUT  
CC  
I
I
Input Leakage Current  
Operating Current (V = Max.,  
3.0V  
3.0V  
3.0V  
3.0V  
–1  
1
–1  
1
µA  
IX  
Ind.  
49  
7
70  
42  
7
60  
mA  
CC  
CC  
I
= 0 mA) Outputs Disabled  
OUT  
I
Standby Current (Both Ports TTL Ind.  
3.0V  
3.0V  
10  
10  
µA  
SB1  
Level) CE and CE V – 0.2,  
L
R
CC  
SEM = SEM = V – 0.2, f = f  
L
R
CC  
MAX  
I
I
Standby Current (One Port TTL  
Ind.  
Ind.  
3.0V  
3.0V  
3.0V  
3.0V  
28  
6
40  
8
25  
6
35  
8
mA  
SB2  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Standby Current (Both Ports  
CMOS Level) CE & CE  
µA  
SB3  
L
R
V
V
0.2V, SEM and SEM >  
CC  
CC  
L
R
– 0.2V, f = 0  
I
Standby Current (One Port CMOS Ind.  
3.0V  
3.0V  
28  
40  
25  
35  
mA  
SB4  
[25]  
Level) CE | CE V , f = f  
L
R
IH  
MAX  
Capacitance[26]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
9
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
IN  
A
V
= 3.0V  
CC  
10  
pF  
OUT  
Note:  
26. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 001-01638 Rev. *E  
Page 12 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
7
AC Test Loads and Waveforms  
3.0V/2.5V/1.8V  
3.0V/2.5V/1.8V  
RTH = 6 kΩ  
R1  
OUTPUT  
C = 30 pF  
OUTPUT  
R1  
OUTPUT  
C = 30 pF  
R2  
C = 5 pF  
R2  
VTH = 0.8V  
(a) Normal Load (Load 1)  
(c) Three-State Delay (Load 2)  
(b) Thévenin Equivalent (Load 1)  
(Used for t , t , t  
, and t  
LZWE  
ALL INPUT PULSES  
LZ HZ HZWE  
3.0V/2.5V  
1022Ω  
1.8V  
including scope and jig)  
1.8V  
GND  
R1  
R2  
13500Ω  
10800Ω  
90%  
90%  
10%  
3 ns  
10%  
792Ω  
3 ns  
[27]  
Switching Characteristics for VCC = 1.8V Over the Operating Range  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
Parameter  
Description  
Min.  
Max.  
Min.  
55  
5
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
40  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
Address to Data Valid  
Output Hold From Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE Low to Low Z  
40  
55  
AA  
OHA  
[28]  
40  
25  
55  
30  
ACE  
DOE  
LZOE  
[29, 30, 31]  
[29, 30, 31]  
5
5
0
5
5
0
OE HIGH to High Z  
15  
15  
25  
25  
HZOE  
[29, 30, 31]  
CE LOW to Low Z  
LZCE  
[29, 30, 31]  
CE HIGH to High Z  
HZCE  
[31]  
[31]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
Byte Enable Access Time  
PU  
PD  
40  
40  
55  
55  
[28]  
ABE  
Write Cycle  
t
t
t
Write Cycle Time  
40  
30  
30  
55  
45  
45  
ns  
ns  
ns  
WC  
[28]  
CE LOW to Write End  
Address Valid to Write End  
SCE  
AW  
Notes:  
27. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V , and output loading of the specified  
CC  
CC  
I
/I and 30-pF load capacitance.  
OI OH  
28. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t  
time.  
SCE  
29. At any given temperature and voltage condition for any given device, t  
30. Test conditions used are Load 3.  
is less than t  
and t  
is less than t  
.
HZCE  
LZCE  
HZOE  
LZOE  
31. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with  
Busy waveform  
Document #: 001-01638 Rev. *E  
Page 13 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
[27]  
Switching Characteristics for VCC = 1.8V Over the Operating Range (continued)  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
Parameter  
Description  
Address Hold From Write End  
Address Set-up to Write Start  
Write Pulse Width  
Min.  
Max.  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
0
0
0
0
HA  
[28]  
SA  
25  
20  
0
40  
30  
0
PWE  
SD  
Data Set-up to Write End  
Data Hold From Write End  
R/W LOW to High Z  
HD  
[30, 31]  
15  
25  
HZWE  
[30, 31]  
R/W HIGH to Low Z  
0
0
LZWE  
[32]  
Write Pulse to Data Delay  
Write Data Valid to Read Data Valid  
55  
55  
80  
80  
WDD  
[32]  
DDD  
[33]  
Busy Timing  
t
t
t
t
t
t
t
t
BUSY LOW from Address Match  
BUSY HIGH from Address Mismatch  
BUSY LOW from CE LOW  
30  
30  
30  
30  
45  
45  
45  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BLA  
BHA  
BLC  
BHC  
BUSY HIGH from CE HIGH  
Port Set-up for Priority  
[34]  
PS  
5
0
5
0
R/W HIGH after BUSY (Slave)  
R/W HIGH after BUSY HIGH (Slave)  
BUSY HIGH to Data Valid  
WB  
WH  
20  
35  
[35]  
30  
40  
BDD  
[33]  
Interrupt Timing  
t
t
INT Set Time  
35  
35  
45  
45  
ns  
ns  
INS  
INR  
INT Reset Time  
Semaphore Timing  
t
t
t
t
SEM Flag Update Pulse (OE or SEM)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
SEM Address Access Time  
10  
10  
10  
15  
10  
10  
ns  
ns  
ns  
ns  
SOP  
SWRD  
SPS  
40  
55  
SAA  
Notes:  
32. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.  
33. Test conditions used are Load 2.  
34. Add 2ns to this value when the I/O ports are operating at different voltages.  
35. t  
is a calculated parameter and is the greater of t  
–t  
(actual) or t  
–t (actual).  
BDD  
WDD PWE  
DDD SD  
Document #: 001-01638 Rev. *E  
Page 14 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Characteristics for VCC = 2.5V Over the Operating Range  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
40  
5
55  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
Address to Data Valid  
Output Hold From Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE Low to Low Z  
40  
55  
AA  
OHA  
[28]  
40  
25  
55  
30  
ACE  
DOE  
LZOE  
[29, 30, 31]  
[29, 30, 31]  
2
2
0
2
2
0
OE HIGH to High Z  
15  
15  
15  
15  
HZOE  
[29, 30, 31]  
CE LOW to Low Z  
LZCE  
[29, 30, 31]  
CE HIGH to High Z  
HZCE  
[31]  
[31]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
Byte Enable Access Time  
PU  
PD  
[28]  
ABE  
40  
40  
55  
55  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
40  
30  
30  
0
55  
45  
45  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
[28]  
CE LOW to Write End  
SCE  
Address Valid to Write End  
Address Hold From Write End  
Address Set-up to Write Start  
Write Pulse Width  
AW  
HA  
[28]  
SA  
0
0
25  
20  
0
40  
30  
0
PWE  
SD  
Data Set-up to Write End  
Data Hold From Write End  
R/W LOW to High Z  
HD  
[30, 31]  
HZWE  
[30, 31]  
LZWE  
15  
25  
R/W HIGH to Low Z  
0
0
[32]  
Write Pulse to Data Delay  
Write Data Valid to Read Data Valid  
55  
55  
80  
80  
WDD  
[32]  
DDD  
[33]  
Busy Timing  
t
t
t
t
t
t
t
t
BUSY LOW from Address Match  
BUSY HIGH from Address Mismatch  
BUSY LOW from CE LOW  
30  
30  
30  
30  
45  
45  
45  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BLA  
BHA  
BLC  
BHC  
BUSY HIGH from CE HIGH  
Port Set-up for Priority  
[34]  
PS  
5
0
5
0
R/W HIGH after BUSY (Slave)  
R/W HIGH after BUSY HIGH (Slave)  
BUSY HIGH to Data Valid  
WB  
WH  
20  
35  
[35]  
30  
40  
BDD  
Document #: 001-01638 Rev. *E  
Page 15 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Characteristics for VCC = 2.5V Over the Operating Range (continued)  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
-40  
-55  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
[33]  
Interrupt Timing  
t
t
INT Set Time  
INT Reset Time  
35  
35  
45  
45  
ns  
ns  
INS  
INR  
Semaphore Timing  
t
t
t
t
SEM Flag Update Pulse (OE or SEM)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
SEM Address Access Time  
10  
10  
10  
15  
10  
10  
ns  
ns  
ns  
ns  
SOP  
SWRD  
SPS  
40  
55  
SAA  
Switching Characteristics for VCC = 3.0V Over the Operating Range  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
Unit  
-40  
-55  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
tRC  
Read Cycle Time  
40  
5
55  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
Address to Data Valid  
Output Hold From Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE Low to Low Z  
40  
55  
AA  
OHA  
[28]  
40  
25  
55  
30  
ACE  
DOE  
LZOE  
[29, 30, 31]  
[29, 30, 31]  
1
1
0
1
1
0
OE HIGH to High Z  
15  
15  
15  
15  
HZOE  
[29, 30, 31]  
CE LOW to Low Z  
LZCE  
[29, 30, 31]  
CE HIGH to High Z  
HZCE  
[31]  
[31]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
Byte Enable Access Time  
PU  
PD  
40  
40  
55  
55  
[28]  
ABE  
Write Cycle  
t
t
t
t
t
t
t
t
Write Cycle Time  
40  
30  
30  
0
55  
45  
45  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
[28]  
CE LOW to Write End  
SCE  
Address Valid to Write End  
Address Hold From Write End  
Address Set-up to Write Start  
Write Pulse Width  
AW  
HA  
[28]  
0
0
SA  
25  
20  
0
40  
30  
0
PWE  
SD  
Data Set-up to Write End  
Data Hold From Write End  
HD  
Document #: 001-01638 Rev. *E  
Page 16 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08,  
CYDC064B08  
Unit  
-40  
-55  
Parameter  
Description  
R/W LOW to High Z  
Min.  
Max.  
Min.  
Max.  
[30, 31]  
t
t
t
t
15  
25  
ns  
ns  
ns  
ns  
HZWE  
[30, 31]  
R/W HIGH to Low Z  
0
0
LZWE  
[32]  
Write Pulse to Data Delay  
Write Data Valid to Read Data Valid  
55  
55  
80  
80  
WDD  
[32]  
DDD  
[33]  
Busy Timing  
t
t
t
t
t
t
t
t
BUSY LOW from Address Match  
BUSY HIGH from Address Mismatch  
BUSY LOW from CE LOW  
30  
30  
30  
30  
45  
45  
45  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BLA  
BHA  
BLC  
BHC  
BUSY HIGH from CE HIGH  
Port Set-up for Priority  
[34]  
PS  
5
0
5
0
R/W HIGH after BUSY (Slave)  
R/W HIGH after BUSY HIGH (Slave)  
BUSY HIGH to Data Valid  
WB  
WH  
20  
35  
[35]  
30  
40  
BDD  
[33]  
Interrupt Timing  
t
t
INT Set Time  
35  
35  
45  
45  
ns  
ns  
INS  
INR  
INT Reset Time  
Semaphore Timing  
t
t
t
t
SEM Flag Update Pulse (OE or SEM)  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
SEM Address Access Time  
10  
10  
10  
15  
10  
10  
ns  
ns  
ns  
ns  
SOP  
SWRD  
SPS  
40  
55  
SAA  
Document #: 001-01638 Rev. *E  
Page 17 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms  
[36, 37, 38]  
Read Cycle No.1 (Either Port Address Access)  
t
RC  
ADDRESS  
t
AA  
t
t
OHA  
OHA  
DATA OUT  
PREVIOUS DATAVALID  
DATA VALID  
[36, 39, 40]  
Read Cycle No.2 (Either Port CE/OE Access)  
t
ACE  
CE and  
LB or UB  
t
HZCE  
t
DOE  
OE  
t
HZOE  
t
LZOE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PU  
t
PD  
ICC  
CURRENT  
ISB  
[36, 38, 41, 42]  
Read Cycle No. 3 (Either Port)  
t
RC  
ADDRESS  
UB or LB  
t
AA  
t
OHA  
t
t
HZCE  
t
t
LZCE  
t
ABE  
CE  
HZCE  
t
ACE  
LZCE  
DATA OUT  
Notes:  
36. R/W is HIGH for read cycles.  
37. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.  
IL  
IL  
38. OE = V  
.
IL  
39. Address valid prior to or coincident with CE transition LOW.  
40. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .  
IL  
IL  
IH  
IH  
IL  
41. R/W must be HIGH during all address transitions.  
42. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.  
SCE  
PWE  
Document #: 001-01638 Rev. *E  
Page 18 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms (continued)  
[41, 42, 43, 44, 45, 46]  
Write Cycle No.1: R/W Controlled Timing  
t
WC  
ADDRESS  
OE  
[47]  
t
HZOE  
t
AW  
[45, 46]  
CE  
[44]  
PWE  
t
t
t
HA  
SA  
R/W  
DATA OUT  
DATA IN  
[47]  
HZWE  
t
t
LZWE  
NOTE 48  
NOTE 48  
t
t
HD  
SD  
[41, 42, 43, 48]  
Write Cycle No. 2: CE Controlled Timing  
t
WC  
ADDRESS  
t
AW  
[45, 46]  
CE  
t
t
t
HA  
SA  
SCE  
R/W  
t
t
HD  
SD  
DATA IN  
Notes:  
43. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.  
HA  
44. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t  
or (t  
+ t ) to allow the I/O drivers to turn off and data to  
HZWE SD  
PWE  
be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short  
SD  
as the specified t  
.
PWE  
45. To access RAM, CE = V , SEM = V  
.
IH  
IL  
46. To access upper byte, CE = V , UB = V , SEM = V .  
IL  
IL  
IL  
IL  
IH  
IH  
To access lower byte, CE = V , LB = V , SEM = V .  
47. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.  
48. During this period, the I/O pins are in the output state, and input signals must not be applied.  
Document #: 001-01638 Rev. *E  
Page 19 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms (continued)  
[49, 50]  
Semaphore Read After Write Timing, Either Side  
t
t
OHA  
SAA  
A0–A2  
VALID ADRESS  
VALID ADRESS  
t
AW  
t
ACE  
t
HA  
SEM  
t
t
SOP  
SCE  
t
SD  
I/O0  
DATAIN VALID  
DATAOUT VALID  
t
HD  
t
t
PWE  
SA  
R/W  
OE  
t
t
DOE  
SWRD  
t
SOP  
WRITE CYCLE  
[51, 52]  
READ CYCLE  
Timing Diagram of Semaphore Contention  
A0L–A2L  
MATCH  
R/WL  
SEML  
t
SPS  
A0R–A2R  
MATCH  
R/WR  
SEMR  
Notes:  
49. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.  
50. CE = HIGH for the duration of the above timing (both write and read cycle).  
51. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.  
0R  
0L  
R
L
52. If t  
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.  
SPS  
Document #: 001-01638 Rev. *E  
Page 20 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms (continued)  
[53]  
Timing Diagram of Read with BUSY (M/S=HIGH)  
t
WC  
ADDRESSR  
R/WR  
MATCH  
t
PWE  
t
t
HD  
SD  
DATA INR  
VALID  
t
PS  
ADDRESSL  
MATCH  
t
BLA  
t
BHA  
BUSYL  
t
BDD  
t
DDD  
DATAOUTL  
VALID  
t
WDD  
Write Timing with Busy Input (M/S = LOW)  
t
PWE  
R/W  
t
t
WH  
WB  
BUSY  
Note:  
53. CE = CE = LOW.  
L
R
Document #: 001-01638 Rev. *E  
Page 21 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms (continued)  
Busy Timing Diagram No.1 (CE Arbitration)  
[54]  
CE Valid First  
L
ADDRESSL,R  
CEL  
ADDRESS MATCH  
t
PS  
CER  
t
t
BHC  
BLC  
BUSYR  
CE Valid First  
R
ADDRESS  
ADDRESS MATCH  
L,R  
CER  
CEL  
t
PS  
t
t
BHC  
BLC  
BUSYL  
[54]  
Busy Timing Diagram No.2 (Address Arbitration)  
Left Address Valid First  
t
or t  
WC  
RC  
ADDRESSL  
ADDRESSR  
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
t
t
BHA  
BLA  
BUSYR  
Right Address Valid First  
t
or t  
WC  
RC  
ADDRESSR  
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
ADDRESSL  
BUSYL  
t
t
BHA  
BLA  
Note:  
54. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.  
PS  
Document #: 001-01638 Rev. *E  
Page 22 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Switching Waveforms (continued)  
Interrupt Timing Diagrams  
Left Side Sets INT :  
R
t
WC  
ADDRESSL  
CEL  
WRITE 1FFF (OR 1/3FFF)  
[55]  
t
HA  
R/WL  
INTR  
[56]  
t
INS  
Right Side Clears INT :  
R
t
RC  
READ 1FFF  
(OR 1/3FFF)  
ADDRESSR  
CER  
[56]  
t
INR  
R/WR  
OER  
INTR  
Right Side Sets INT :  
L
t
WC  
ADDRESSR  
CER  
WRITE 1FFE (OR 1/3FFE)  
[55]  
HA  
t
R/WR  
INTL  
[56]  
INS  
t
Left Side Clears INT :  
L
t
RC  
READ 1FFE  
OR 1/3FFE)  
ADDRESSR  
CEL  
[56]  
INR  
t
R/WL  
OEL  
INTL  
Notes:  
55. t depends on which enable pin (CE or R/W ) is deasserted first.  
HA  
L
L
56. t  
or t  
depends on which enable pin (CE or R/W ) is asserted last.  
INS  
INR  
L
L
Document #: 001-01638 Rev. *E  
Page 23 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Ordering Information  
16k x16 1.8V Asynchronous Dual-Port SRAM  
Speed  
(ns)  
40  
Package  
Name  
Operating  
Ordering Code  
CYDC256B16-40AXC  
CYDC256B16-55AXC  
CYDC256B16-55AXI  
Package Type  
100-pin Lead-free TQFP  
Range  
Commercial  
Commercial  
Industrial  
AZ0AB  
AZ0AB  
AZ0AB  
55  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
55  
8k x16 1.8V Asynchronous Dual-Port SRAM  
Speed  
(ns)  
40  
Package  
Name  
Operating  
Range  
Ordering Code  
CYDC128B16-40AXC  
CYDC128B16-55AXC  
CYDC128B16-55AXI  
Package Type  
AZ0AB  
AZ0AB  
AZ0AB  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
Commercial  
Commercial  
Industrial  
55  
55  
4k x16 1.8V Asynchronous Dual-Port SRAM  
Speed  
(ns)  
40  
Package  
Name  
Operating  
Range  
Ordering Code  
CYDC064B16-40AXC  
CYDC064B16-55AXC  
CYDC064B16-55AXI  
Package Type  
AZ0AB  
AZ0AB  
AZ0AB  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
Commercial  
Commercial  
Industrial  
55  
55  
16k x8 1.8V Asynchronous Dual-Port SRAM  
Speed  
(ns)  
40  
Package  
Name  
Operating  
Range  
Ordering Code  
CYDC128B08-40AXC  
CYDC128B08-55AXC  
CYDC128B08-55AXI  
Package Type  
AZ0AB  
AZ0AB  
AZ0AB  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
Commercial  
Commercial  
Industrial  
55  
55  
8k x8 1.8V Asynchronous Dual-Port SRAM  
Speed  
(ns)  
40  
Package  
Name  
Operating  
Range  
Ordering Code  
CYDC064B08-40AXC  
CYDC064B08-55AXC  
CYDC064B08-55AXI  
Package Type  
AZ0AB  
AZ0AB  
AZ0AB  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
100-pin Lead-free TQFP  
Commercial  
Commercial  
Industrial  
55  
55  
Document #: 001-01638 Rev. *E  
Page 24 of 26  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Package Diagram  
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100  
51-85048-*C  
All products and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 001-01638 Rev. *E  
Page 25 of 26  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Document History Page  
Document Title: CYDC256B16/CYDC128B16/CYDC064B16/CYDC128B08/CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k  
x 8 ConsuMoBL Dual-Port Static RAM  
Document Number: 001-01638  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
385185  
396697  
SEE ECN  
SEE ECN  
YDT  
KGH  
New data sheet  
*A  
Updated ISB2 and ISB4 typo to mA.  
Updated tINS and tINR for -55 to 31ns.  
*B  
404777  
SEE ECN  
KGH  
Updated I and I values for the 1.8V, 2.5V and 3.0V parameters V and  
OH OL OH  
V
OL  
Replaced -35 speed bin with -40  
Updated Switching Characteristics for V = 2.5V and V = 3.0V  
CC  
CC  
Included note 34  
*C  
*D  
*E  
463014  
505803  
735537  
SEE ECN  
SEE ECN  
SEE ECN  
HKH  
HKH  
HKH  
Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port”  
Cypress Internet Release  
Corrected typo in Features and Ordering Info sections.  
Cypress external web release.  
Corrected typo in Pg5 power supply section  
Updated tDDD timing value to be consistent with tWDD  
Document #: 001-01638 Rev. *E  
Page 26 of 26  

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