Cypress CY8CTST200 User Manual

CY8CTMG200, CY8CTST200  
November 7, 2008  
Errata Document for TrueTouch® CY8CTMG200, CY8CTST200  
®
This document describes the errata for the TrueTouch CY8CTMG200 and CY8CTST200. Details include errata  
trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document  
to the device’s data sheet for a complete functional description.  
Contact your local Cypress Sales Representative if you have questions.  
CY8CTMG200 and CY8CTST200 Errata Summary  
The following Errata items apply to the CY8CTMG200 and CY8CTST200 datasheets 001-47603 and 001-47602.  
1. Latch-up susceptibility when maximum I/O sink current exceeded  
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PROBLEM DEFINITION  
P1[3], P1[6], and P1[7] pins are susceptible to latch-up when the I/O sink current exceeds 25 mA per pin on  
these pins.  
PARAMETERS AFFECTED  
LU – Latch-up Current. Per JESD78A, the maximum allowable latch-up current per pin is 100 mA. Cypress  
internal specification is 200 mA latch-up current limit.  
TRIGGER CONDITION(S)  
Latch-up occurs when both of the following two conditions are met:  
A. The offending I/O is externally connected to a voltage higher than the I/O high state, causing a current to  
flow into the pin that exceeds 25 mA  
B. A Port1 I/O adjacent (P1[1], P1[4] and P1[5] respectively) to the offending I/O is connected to a voltage  
lower than the I/O low state, causing a signal that drops below Vss (signal undershoot), causing a current  
greater than 200 mA to flow out of the pin  
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SCOPE OF IMPACT  
The trigger conditions outlined above exceed the maximum ratings specified in the CY8CTMG200 and  
CY8CTST200 datasheets 001-47603 and 001-47602.  
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WORKAROUND  
Add a series resistor >300Ω to P1[3], P1[6], and P1[7] pins to restrict current to within latch-up limits.  
FIX STATUS  
This issue will be corrected in the next new silicon revision.  
The following Errata item applies only to the CY8CTMG200-48LTXI, CY8CTST200-48LTXI, and CY8CTMG200-  
00LTXI, parts on the 001-47603 and 001-47602 Datasheets.  
2. Does not meet USB 2.0 specification for D+ and D- rise/fall matching when supply voltage is under 3.3V  
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PROBLEM DEFINITION  
Rising to falling rate matching of the USB D+ and D- lines has a corner case at lower supply voltages, such  
as those under 3.3V.  
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PARAMETERS AFFECTED  
Rising to falling rate matching of the USB data lines.  
TRIGGER CONDITION(S)  
Operating the VCC supply voltage at the low end of the chip’s specification (under 3.3V) may cause a  
missmatch in the rising to falling rate.  
Cypress Semiconductor Corporation  
November 7, 2008  
198 Champion Court  
Document No. 001-49988 Rev. **  
San Jose, CA 95134  
408.943.2600  
1
Errata Document  
CY8CTMG200, CY8CTST200  
Document History Page  
®
Document Title: Errata Document for: TrueTouch CY8CTMG200, CY8CTST200  
Document Number: 001-49988  
Orig. of  
Change  
REV.  
ECN NO.  
Issue Date  
Description of Change  
**  
2603495  
See ECN  
DTB  
First release.  
Cypress Semiconductor  
198 Champion Court  
San Jose, CA 95134-1709  
Phone: 408-943-2600  
Fax: 408-943-4730  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes  
no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights.  
Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express  
written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or  
failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the  
manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection  
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custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement.  
Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written  
permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED  
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without  
further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.  
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result  
in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and  
in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
November 7, 2008  
Document No. 001-49988 Rev. **  
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