Cypress CY8CNP102B User Manual

CY8CNP102B, CY8CNP102E  
PRELIMINARY  
Nonvolatile Programmable System-on-Chip  
(PSoC® NV)  
Precision, Programmable Clocking  
Overview  
Internal ±2.5% 24 and 48 MHz Oscillator  
The Cypress nonvolatile Programmable System-on-Chip  
24 and 48 MHz with optional 32.768 kHz Crystal  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
®
(PSoC NV) processor combines a versatile Programmable  
System-on-Chip™ (PSoC) core with an infinite endurance  
nvSRAM in a single package. The PSoC NV combines an 8-bit  
MCU core (M8C), configurable analog and digital functions, a  
uniquely flexible IO interface, and a high density nvSRAM. This  
creates versatile data logging solutions that provide value  
through component integration and programmability. The flexible  
core and a powerful development environment work to reduce  
design complexity, component count, and development time.  
Flexible On-Chip Memory  
32K Bytes Flash Program Storage  
2K Bytes SRAM Data Storage  
256K Bytes secure store nvSRAM with data throughput be-  
tween 100 KBPS and 1 MBPS  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Features  
Flexible Protection Modes  
EEPROM Emulation in Flash  
Powerful Harvard Architecture Processor  
M8C processor speeds  
Programmable Pin Configurations  
33 GPIOs  
• Up to 12 MHz for 3.3V operation  
• Up to 24 MHz for 5V operation  
25 mA Sink on all GPIO  
Two 8x8 multiply, 32 bit accumulate  
Pull up, Pull down, High Z, Strong, or Open Drain Drive  
Low power at high speed  
Modes on all GPIO  
Operating Voltage  
3.3V (CY8CNP102B)  
5V (CY8CNP102E)  
Up to 12 Analog Inputs on GPIOs  
Analog Outputs with 40 mA on 4 GPIOs  
Configurable Interrupt on all GPIOs  
Advanced Peripherals  
12 Rail-to-Rail Analog PSoC blocks provide:  
• Up to 14 bit ADCs  
Additional System Resources  
2
I C Slave, Master, and MultiMaster to 100 Kbps  
and 400 Kbps  
• Up to 9 bit DACs  
Watchdog and Sleep Timers  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
• 8 Analog channels for simultaneous sampling  
Complete Development Tools  
• Up to 820 SPS for each channel with 8 channel sampling  
and logging  
16 Digital PSoC Blocks provide:  
• 8 to 32 bit timers, counters, and PWMs  
• CRC and PRS Modules  
Free Development Software (PSoC Designer™)  
Full Featured, In Circuit Emulator and Programmer  
Full Speed Emulation  
C Compilers, Assembler, and Linker  
Temperature and Packaging  
• Up to 4 Full Duplex UARTs  
Industrial Temperature Range: -40°C to +85°C  
Packaging: 100-pin TQFP  
• Multiple SPIMasters and Slaves  
Complex Peripherals by Combining Blocks  
Cypress Semiconductor Corporation  
Document #: 001-43991 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 20, 2008  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Pinouts  
Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)  
Table 1. Pin Definitions - 100-Pin TQFP  
Type  
Pin Number Pin Name  
Pin Definition  
Digital  
IO  
Analog  
1
2
P0_5  
P0_3  
P0_1  
P2_7  
P2_5  
P2_3  
P2_1  
Vcc  
IO  
IO  
I
Analog Column Mux Input and Column Output  
Analog Column Mux Input and Column Output  
Analog Column Mux Input, GPIO  
GPIO  
IO  
3
IO  
4
IO  
5
IO  
GPIO  
6
IO  
I
I
Direct Switched Capacitor Block Input  
Direct Switched Capacitor Block Input  
Supply Voltage  
7
IO  
8
Power  
9
DNU  
DNU  
DNU  
DNU  
DNU  
NC  
Reserved for test modes - Do Not Use  
Reserved for test modes - Do Not Use  
Reserved for test modes - Do Not Use  
Reserved for test modes - Do Not Use  
Reserved for test modes - Do Not Use  
Not connected on the die  
10  
11  
12  
13  
14  
15  
16  
17  
P3_5  
EN_W  
P3_1  
IO  
IO  
GPIO  
Connect to Pin 26 (EN_W to NV_W)  
GPIO  
Document #: 001-43991 Rev. *D  
Page 3 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Table 1. Pin Definitions - 100-Pin TQFP (continued)  
Type  
Pin Number Pin Name  
Pin Definition  
Digital  
IO  
Analog  
18  
19  
P5_7  
P5_5  
P5_3  
P5_1  
P1_7  
P1_5  
P1_3  
P1_1  
NV_W  
NC  
GPIO  
GPIO  
GPIO  
GPIO  
IO  
20  
IO  
21  
IO  
22  
IO  
I2C Serial Clock (SCL), GPIO  
I2C Serial Data (SDA), GPIO  
GPIO  
23  
IO  
24  
IO  
25  
IO  
Serial Clock (SCL), Crystal (XTALin), GPIO  
Connect to pin 16 (NV_W to EN_W)  
Not connected on the die  
26  
27 - 34  
35 - 39  
40 - 47  
48  
Vss  
Power  
Ground  
NC  
Not connected on the die  
DNU  
NV_A1  
NV_A2  
P1_0  
P1_2  
P1_6  
P5_0  
P5_2  
P5_4  
P5_6  
EN_A1  
EN_A2  
EN_O  
EN_C  
XRES  
VCAP  
Vcc  
Reserved for test modes - Do Not Use  
Connect to pin 58 (NV_A1 to EN_A1)  
Connect to pin 59 (NV_A2 to EN_A2)  
Serial Data (SDA), Crystal (XTALout), GPIO  
GPIO  
49  
50  
51  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
52  
53  
GPIO  
54  
GPIO  
55  
GPIO  
56  
GPIO  
57  
GPIO  
58  
Connect to Pin 49 (EN_A1 to NV_A1)  
Connect to Pin 50 (EN_A2 to NV_A2)  
Connect to Pin 76 (EN_O to NV_O)  
Connect to Pin 99 (EN_C to NV_C)  
Active high external reset (Internal Pull down)  
External Capacitor connection for nvSRAM  
Supply Voltage  
59  
60  
61  
62  
Input  
Power  
Power  
63  
64  
65  
P2_0  
P2_2  
P2_4  
P2_6  
P0_0  
P0_2  
P0_4  
NC  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
I
Direct Switched Capacitor Block Input, GPIO  
Direct Switched Capacitor Block Input, GPIO  
External Analog GND, GPIO  
External Voltage Ref, GPIO  
Analog Column Mux Input, GPIO  
Analog Column Mux Input and Column Output  
Analog Column Mux Input and Column Output  
Not connected on the die  
66  
67  
68  
69  
I
70  
IO  
IO  
71  
72-73  
74  
P0_6  
Vcc  
IO  
I
Analog Column Mux Input, GPIO  
Supply Voltage  
75  
Power  
76  
NV_O  
DNU  
NC  
Connect to Pin 60 (NV_O to EN_O)  
Reserved for test modes - Do Not Use  
Not connected on the die  
77  
78  
Document #: 001-43991 Rev. *D  
Page 4 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Table 1. Pin Definitions - 100-Pin TQFP (continued)  
Type  
Pin Number Pin Name  
Pin Definition  
Digital  
Analog  
79  
HSB#  
Vcc  
Weak Pull up. Connect 10kΩ to Vcc.  
Supply Voltage  
80  
Power  
Power  
81 - 85  
86 - 90  
91 - 98  
99  
NC  
Not connected on the die  
Vss  
Ground  
NC  
Not connected on the die  
NV_C  
P0_7  
Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.  
Analog Column Mux Input, GPIO  
100  
IO  
I
interfacing. Every pin also has the capability to generate a  
system interrupt on high level, low level, and change from last  
read.  
PSoC NV Functional Overview  
The PSoC NV provides a versatile microcontroller core (M8C),  
Flash program memory, nvSRAM data memory, and  
configurable analog and digital peripheral blocks in a single  
package. The flexible digital and analog IOs and routing matrix  
nvSRAM Data Memory  
The nvSRAM memory block is byte addressable fast static RAM  
with a nonvolatile element in each memory cell. The embedded  
create  
a
powerful embedded and flexible mixed signal  
System-on-Chip (SoC).  
®
nonvolatile elements incorporate QuantumTrap technology  
The device incorporates configurable analog and digital blocks,  
interconnect circuitry around an MCU subsystem, and an infinite  
endurance nvSRAM. This enables high level integration in  
consumer, industrial, and automotive applications, where  
preventing data loss under all conditions is vital.  
producing the world’s most reliable nonvolatile memory. The  
SRAM provides infinite read and write cycles, when independent  
nonvolatile data resides in the highly reliable QuantumTrap cell.  
Data transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down, and  
data is restored to the SRAM (the RECALL operation) from the  
nonvolatile memory on power up. All cells store and recall data  
in parallel.  
PSoC NV Core  
The PSoC NV core is a powerful PSoC engine that supports a  
rich feature set. The core includes a M8C CPU, memory, clocks,  
and configurable GPIO (General Purpose IO). The M8C CPU  
core is a powerful processor with speeds up to 24 MHz, providing  
a four MIPS 8-bit Harvard architecture microprocessor. The CPU  
uses an interrupt controller with 25 vectors, to simplify  
programming of real time embedded events. Program execution  
is timed and protected using the included Sleep and Watch Dog  
Timers (WDT).  
Both the STORE and RECALL operations may be initiated under  
software control. The PSoC NV user module embedded in the  
PSoC Designer Tool provides all necessary APIs to initiate  
software STORE and RECALL function from the user program.  
nvSRAM Operation  
The nvSRAM is made up of an SRAM memory cell, and a  
nonvolatile QuantumTrap cell paired in the same physical cell.  
The SRAM memory cell operates as a standard fast static, and  
all READ and WRITE takes place from the SRAM during normal  
operation.  
On-chip memory encompasses 32 KB Flash for program  
storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data  
logging, and up to 2 KB EEPROM emulated using Flash.  
Program Flash uses four protection levels on blocks of 64 bytes,  
allowing customized software IP protection. The nvSRAM  
combines a static RAM cell and a SONOS cell to provide an  
infinite endurance nonvolatile memory block. The memory is  
random access and is accessed using a user module provided  
with the device.  
During the STORE and RECALL operations, SRAM READ and  
WRITE operations are inhibited, and internal operations transfer  
data between the SRAM and nonvolatile cells. The nvSRAM  
provides infinite RECALL operations from the nonvolatile cells  
and up to 200,000 STORE operations.  
®
To reduce unnecessary nonvolatile stores, AutoStore is ignored  
The device incorporates flexible internal clock generators,  
including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5  
percent over temperature and voltage. The 24 MHz IMO can also  
be doubled to 48 MHz for use by the digital system. A low power  
32 kHz Internal Low speed Oscillator (ILO) is provided for the  
Sleep timer and WDT. The clocks, together with programmable  
clock dividers (as a System Resource), provide the flexibility to  
integrate almost any timing requirement into the PSoC NV  
device.  
unless at least one WRITE operation is complete after the most  
recent STORE or RECALL cycle. Software initiated STORE  
cycles are performed regardless of whether a WRITE operation  
has taken place. Embedded APIs provide a seamless interface  
to the nvSRAM.  
During normal operation, the embedded nvSRAM draws current  
from Vcc to charge a capacitor connected to the V  
pin. This  
CAP  
stored charge is used by the chip to perform a STORE operation.  
If the voltage on the Vcc pin drops below V , the part  
GPIOs provide connection to the CPU, and digital and analog  
resources of the device. Each pin’s drive mode may be selected  
from eight options, allowing great flexibility in external  
SWITCH  
automatically disconnects the V  
operation is initiated.  
pin from Vcc and STORE  
Page 5 of 38  
CAP  
Document #: 001-43991 Rev. *D  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Peak Detectors  
Programmable Digital System  
Other possible topologies  
The digital system contains 16 digital PSoC blocks. Each block  
is an 8-bit resource that is used alone or combined with other  
blocks to form 8, 16, 24, and 32-bit peripherals, which are called  
user module references. The digital peripheral configurations  
are:  
Analog blocks are provided in columns of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks.  
Additional System Resources  
PWMs (8 to 32 bit)  
System Resources, some of which are listed in the previous  
sections, provide additional capability useful to complete  
systems. Resources include a multiplier, decimator, switch mode  
pump, low voltage detection, and power on reset. The merits of  
each system resource are:  
PWMs with dead band (8 to 32 bit)  
Counters (8 to 32 bit)  
Timers (8 to 32 bit)  
UART 8 bit with selectable parity (up to 4)  
SPI master and slave (up to 4 each)  
Digital clock dividers provide three customizable clock  
frequencies for use in applications. The clocks may be routed  
to both the digital and analog systems. Additional clocks are  
generated using digital PSoC blocks as clock dividers.  
2
I C slave and multimaster (1 available as a System Resource)  
Cyclical Redundancy Checker and Generator (8 to 32 bit)  
IrDA (up to 4)  
Multiply Accumulate (MAC) provides fast 8-bit multiplier with  
32-bit accumulate, to assist in general math and digital filters.  
The decimator provides a custom hardware filter for digital  
signal, and processing applications including the creation of  
Delta Sigma ADCs.  
Pseudo Random Sequence Generators (8 to 32 bit)  
The digital blocks connect to any GPIO through a series of global  
buses that route any signal to any pin. The buses also enable  
signal multiplexing and performing logic operations. This  
configurability frees your designs from the constraints of a fixed  
peripheral controller.  
2
The I C module provides 100 and 400 kHz communication over  
two wires. Slave, master, and multi master modes are all  
supported.  
Digital blocks are provided in rows of four, where the number of  
blocks varies with PSoC device family. This gives you the  
optimum choice of system resources for your application.  
Low Voltage Detection (LVD) interrupts can signal the  
application of falling voltage levels, while the advanced POR  
(Power On Reset) circuit eliminates the need for a system  
supervisor.  
Programmable Analog System  
The analog system consists 12 configurable blocks, each having  
an opamp circuit enabling the creation of complex analog signal  
flows. Analog peripherals are very flexible and may be  
customized to support specific application requirements. Some  
of the more common analog functions (most available as user  
modules) are:  
Analog-to-digital converters (up to 4, with 6 to 14 bit resolution,  
selectable as Incremental, Delta Sigma, and SAR)  
Filters (2, 4, 6, or 8 pole band pass, low pass, and notch)  
Amplifiers (up to 4, with selectable gain to 48x)  
Instrumentation amplifiers (up to 2, with selectable gain to 93x)  
Comparators (up to 4, with 16 selectable thresholds)  
DACs (up to 4, with 6 to 9 bit resolution)  
Multiplying DACs (up to 4, with 6 to 9 bit resolution)  
High current output drivers (four with 40 mA drive as a Core  
Resource)  
1.3V reference (as a System Resource)  
DTMF Dialer  
Modulators  
Correlators  
Document #: 001-43991 Rev. *D  
Page 6 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Development Tools  
PSoC Designer Software Subsystems  
PSoC Designer is a Microsoft® Windows based, integrated  
development environment for Programmable System-on-Chip  
(PSoC) devices. The PSoC Designer IDE and application run on  
Windows NT 4.0, Windows 2000, Windows Millennium (Me),  
Microsoft Vista, and Windows XP.  
Device Editor  
The Device Editor subsystem enables the user to select different  
onboard analog and digital components called user modules,  
using the PSoC blocks. Examples of user modules are ADCs,  
DACs, nvSRAM, Amplifiers, and Filters.  
PSoC Designer helps the customer to select an operating  
configuration for the PSoC, write application code that uses the  
PSoC, and debug the application. This system provides design  
database management by project, an integrated debugger with  
In-Circuit Emulator, in-system programming support, and the  
CYASM macro assembler for the CPUs.  
The device editor also supports easy development of multiple  
configurations and dynamic reconfiguration. Dynamic  
configuration enables changing configurations at run time.  
PSoC Designer sets up power on initialization tables for selected  
PSoC block configurations and creates source code for an  
application framework. The framework contains software to  
operate the selected components. Also, if the project uses more  
than one operating configuration, the framework contains  
routines to switch between different sets of PSoC block  
configurations at run time. PSoC Designer can print out a  
configuration sheet for a given project configuration, for use  
during application programming in conjunction with the Device  
Data Sheet. After the framework is generated, the user can add  
application specific code to flesh out the framework. It is also  
possible to change the selected components and regenerate the  
framework.  
PSoC Designer also supports a high level C language compiler  
developed specifically for the devices in this family.  
Figure 2. PSoC Designer Subsystem  
Context  
Sensitive  
Help  
Graphical Designer  
PSoC  
Designer  
Interface  
Design Browser  
Importable  
Design  
Database  
The Design Browser enables users to select and import  
preconfigured designs into their project. Users can easily browse  
a catalog of preconfigured designs to facilitate time to design.  
Examples provided in the tools include a 300 baud modem, LIN  
Bus master and slave, fan controller, and magnetic card reader.  
PSoC  
Configuration  
Sheet  
Device  
Database  
PSoC  
Designer  
Core  
Application  
Database  
Application Editor  
In the Application Editor you can edit C language and Assembly  
language source code. You can also assemble, compile, link,  
and build.  
Manufacturing  
Information  
File  
Engine  
Project  
Database  
Assembler. The macro assembler seamlessly merges the  
assembly code with C code. The link libraries automatically use  
absolute addressing or are compiled in relative mode, and linked  
with other software modules to get absolute addressing.  
User  
Modules  
Library  
C Language Compiler. A C language compiler that supports  
Cypress PSoC family devices is available. Even if you have  
never worked in the C language before, the product quickly  
enables you to create complete C programs for the PSoC family  
devices.  
Emulation  
Pod  
In-Circuit  
Emulator  
Device  
Programmer  
The embedded, optimizing C compiler provides all the features  
of C tailored to the PSoC architecture. It is complete with  
embedded libraries providing port and bus operations, standard  
keypad and display support, and extended math functionality.  
Debugger  
The PSoC Designer Debugger subsystem provides hardware  
in-circuit emulation, which enables the designer to test the  
program in a physical system while providing an internal view of  
the PSoC device. Debugger commands enable the designer to  
read and program, read and write data memory, read and write  
IO registers, read and write CPU registers, set and clear  
breakpoints, and provide program run, halt, and step control. The  
debugger also enables the designer to create a trace buffer of  
registers and memory locations of interest.  
Document #: 001-43991 Rev. *D  
Page 7 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Online Help System  
The development process starts when you open a new project  
and bring up the Device Editor, which is a graphical user  
interface (GUI) for configuring the hardware. Pick the user  
modules required for your project and map them onto the PSoC  
blocks with point and click simplicity. Next, build signal chains by  
interconnecting user modules to each other and to the IO pins.  
At this stage, configure the clock source connections and enter  
parameter values directly or by selecting values from drop down  
menus. When you are ready to test the hardware configuration  
or develop code for the project, perform the “Generate  
Application” step. PSoC Designer generates source code that  
automatically configures the device to your specification and  
provides high level user module API functions.  
The online help system displays online, context sensitive help for  
the user. Designed for procedural and quick reference, each  
functional subsystem has its own context sensitive help. This  
system also provides tutorials and links to FAQs and an Online  
Support Forum to aid the designer in getting started.  
Hardware Tools  
In-Circuit Emulator  
A low cost, high functionality ICE (In-Circuit Emulator) is  
available for development support. This hardware has the  
capability to program single devices.  
User Module and Source Code Development Flows  
The emulator consists of a base unit that connects to the PC  
through the USB port. The base unit is universal and operates  
with all PSoC devices. Emulation pods for each device family are  
available separately. The emulation pod takes the place of the  
PSoC device in the target board and performs full speed  
(24 MHz) operation.  
The next step is to write the main program, and any subroutine  
using PSoC Designer’s Application Editor subsystem. The  
Application Editor includes a Project Manager that enables you  
to open the project source code files (including all generated  
code files) from a hierarchal view. The source code editor  
provides syntax coloring and advanced edit features for C and  
assembly language. File search capabilities include simple string  
searches and recursive “grep-style” patterns. A single mouse  
click invokes the Build Manager.  
Designing with User Modules  
The development process for the PSoC device differs from that  
of a traditional fixed function microprocessor. The configurable  
analog and digital hardware blocks give the PSoC architecture a  
unique flexibility that manages specification change during  
development and lowers inventory costs. These configurable  
resources, called PSoC Blocks, implement a wide variety of  
user-selectable functions. Each block has several registers that  
determine its function and connectivity to other blocks,  
multiplexers, buses, and to the IO pins. Iterative development  
cycles permit you to adapt the hardware and the software. This  
substantially lowers the risk of selecting a different part to meet  
the final design requirements.  
It employs a professional strength “makefile” system to  
automatically analyze all file dependencies and run the compiler  
and assembler as necessary. Project level options control  
optimization strategies used by the compiler and linker. Syntax  
errors are displayed in a console window. Double clicking the  
error message takes you directly to the offending line of source  
code. After correction, the linker builds a HEX file image suitable  
for programming.  
Figure 3. User Module and Source Code Development Flows  
To speed the development process, the PSoC Designer IDE  
provides a library of prebuilt, pretested hardware peripheral  
functions, called “User Modules.” User modules simplify  
selecting and implementing peripheral devices, and come in  
analog, digital, and mixed signal varieties. The standard User  
Module library contains over 50 peripherals such as ADCs,  
DACs, Timers, Counters, UARTs, nvSRAM, DTMF Generators,  
and Bi-Quad analog filter sections.  
Device Editor  
Placement  
User  
Module  
Selection  
Source  
Code  
Generator  
and  
Parameter  
-ization  
Generate  
Application  
Each user module establishes the basic register settings that  
implement the selected function. It also provides parameters that  
enable you to tailor its precise configuration to your particular  
application. For example, a Pulse Width Modulator User Module  
configures one or more digital PSoC blocks, one for each 8 bits  
of resolution. The user module parameters permit you to  
establish the pulse width and duty cycle. User modules also  
provide tested software to cut your development time. The user  
module Application Programming Interface (API) provides high  
level functions to control and respond to hardware events at run  
time. The API also provides optional interrupt service routines  
that you can adapt as needed.  
Application Editor  
Source  
Code  
Editor  
Project  
Manager  
Build  
Manager  
Build  
All  
Debugger  
The API functions are documented in user module data sheets  
that are viewed directly in the PSoC Designer IDE. These data  
sheets explain the internal operation of the user module and  
provide performance specifications. Each data sheet describes  
the use of each user module parameter and documents the  
setting of each register controlled by the user module.  
Event &  
Breakpoint  
Manager  
Interface  
to ICE  
Storage  
Inspector  
Document #: 001-43991 Rev. *D  
Page 8 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
The last step in the development process takes place inside the  
Cypress nvSRAM user Module  
PSoC Designer’s Debugger subsystem. The Debugger  
downloads the HEX image to the In-Circuit Emulator (ICE) where  
it runs at full speed. The Debugger capabilities rival those of  
systems costing much more. In addition to traditional single step,  
run to breakpoint, and watch variable features, the Debugger  
provides a large trace buffer enabling you to define complex  
breakpoint events that include monitoring address and data bus  
values, memory locations, and external signals.  
The nvSRAM user module is integrated with the PSoC Designer  
tool and contains APIs that facilitate nvSRAM access and  
control. The user module provides high level access to the  
nvSRAM without user developed code. The user module API  
also provides the ability to read and write arbitrary data struc-  
tures to or from the nvSRAM, and initiate nvSRAM Store or  
Recall operations.  
Electrical Specifications  
This section lists the PSoC NV device DC and AC electrical specifications.  
o
o
o
Specifications are valid for -40 C T 85 C, and T 100 C, except where noted.  
A
J
Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator (IMO) using SLIMO mode.  
Figure 4. Voltage versus CPU Frequency  
Figure 5. IMO Frequency Trim Options  
5.25  
5.25  
4.75  
SLIMO  
SLIMO  
Operating Region  
(CY8CNP102E)  
Mode=1  
Mode=0  
4.75  
3.60  
3.60  
3.00  
SLIMO  
SLIMO  
Operating Region  
(CY8CNP102B)  
Mode=1  
Mode=0  
3.00  
93 kHz  
12 MHz  
24 MHz  
93 kHz  
6 MHz  
12 MHz  
24 MHz  
IMO Frequency  
CPU Frequency  
The following table lists the units of measure that are used in this data sheet.  
Table 2. Units of Measure  
Symbol  
Unit of Measure  
degree Celsius  
Symbol  
Unit of Measure  
microwatts  
o
C
μW  
mA  
ms  
mV  
nA  
ns  
dB  
fF  
decibels  
milli-ampere  
milli-second  
milli-volts  
femto farad  
hertz  
Hz  
KB  
1024 bytes  
1024 bits  
nanoampere  
nanosecond  
nanovolts  
Kbit  
kHz  
kΩ  
kilohertz  
nV  
Ω
kilohm  
ohm  
MHz  
MΩ  
μA  
megahertz  
megaohm  
pA  
pF  
pp  
picoampere  
picofarad  
microampere  
microfarad  
microhenry  
microsecond  
microvolts  
peak-to-peak  
parts per million  
picosecond  
μF  
ppm  
ps  
μH  
μs  
sps  
σ
samples per second  
sigma: one standard deviation  
volts  
μV  
μVrms  
microvolts root-mean-square  
V
Document #: 001-43991 Rev. *D  
Page 9 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
3.3V Operation  
Absolute Maximum Ratings  
Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B)  
Symbol Description  
Storage Temperature  
Min  
Typ  
Max  
Units  
Notes  
o
T
-55  
25  
+100  
C
Higherstoragetemperatures  
reduce data retention time.  
Recommended storage  
STG  
o
temperature is ± 25 C.  
Extended duration storage  
o
temperatures above 65 C  
degrade reliability.  
o
T
Ambient Temperature with Power Applied  
Supply Voltage on Vcc Relative to Vss  
DC Input Voltage  
-40  
-0.5  
+85  
+4.1  
C
A
Vcc  
V
V
V
V
Vss - 0.5  
Vss - 0.5  
-25  
Vcc + 0.5  
Vcc + 0.5  
+50  
IO  
DC Voltage Applied to Tri-state  
Maximum Current into any Port Pin  
V
IOZ  
I
I
mA  
mA  
MIO  
MAIO  
Maximum Current into any Port Pin  
Configured as Analog Driver  
-50  
+50  
ESD  
LU  
Electro Static Discharge Voltage  
Latch-up Current  
2000  
V
Human Body Model ESD.  
200  
mA  
Operating Temperature  
Table 4. 3.3V Operating Temperature (CY8CNP102B)  
Symbol  
Description  
Ambient Temperature  
Junction Temperature  
Min  
-40  
-40  
Typ  
Max  
+85  
Units  
Notes  
o
T
C
A
o
T
+100  
C
J
Document #: 001-43991 Rev. *D  
Page 10 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Electrical Characteristics  
The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature  
range: 3.0V to 3.6V over the Temperature range of -40°C T 85°C. Typical parameters apply to 3.3V at 25°C and are for design  
A
guidance only.  
DC Chip Level Specifications  
Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B)  
Symbol  
Vcc  
Description  
Supply Voltage  
Min  
3.00  
Typ  
Max  
3.6  
40  
Units  
V
Notes  
o
I
I
I
Supply Current  
36  
mA  
T = 25 C, CPU = 3 MHz,  
DD  
A
SYSCLK doubler disabled,  
VC1 = 1.5 MHz, VC2 = 93.75 kHz,  
VC3 = 0.366 kHz, continuous  
nvSRAM access  
o
Supply current when IMO = 6 MHz  
using SLIMO mode.  
27  
28  
5
mA  
mA  
T = 25 C, CPU = 0.75 MHz,  
DDP  
SB  
A
SYSCLK doubler disabled,  
VC1=0.375MHz, VC2=23.44kHz,  
VC3 = 0.09 kHz, continuous  
nvSRAM access  
Sleep (Mode) Current with POR, LVD,  
Sleep Timer, WDT, and internal slow  
oscillator active.  
nvSRAM in standby.  
V
V
Reference Voltage (Bandgap)  
1.28  
61  
1.3  
68  
1.32  
82  
V
Trimmed for appropriate Vcc.  
5V rated (minimum)  
REF  
Storage Capacitor between Vcap and  
Vss  
uF  
cap  
DC General Purpose IO Specifications  
Table 6. 3.3V DC GPIO Specifications (CY8CNP102B)  
Symbol  
Description  
Pull up Resistor  
Min  
Typ  
5.6  
5.6  
Max  
Units  
KΩ  
KΩ  
V
Notes  
R
R
4
4
8
8
PU  
PD  
OH  
Pull down Resistor  
High Output Level  
V
Vcc - 1.0  
IOH = 10 mA, Vcc = 3.0 to 3.6V. 8  
total loads, 4 on even port pins (for  
example, P0[2], P1[4]), 4 on odd  
port pins (for example, P0[3],  
P1[5]). 80mAmaximumcombined  
IOH budget.  
V
Low Output Level  
0.75  
0.8  
V
IOL = 25 mA, Vcc = 3.0 to 3.6V  
8 total loads, 4 on even port pins  
(for example, P0[2], P1[4]), 4 on  
odd port pins (for example, P0[3],  
P1[5]). 150 mA maximum  
OL  
combined IOL budget.  
V
V
V
I
Input Low Level  
1.6  
V
V
Vcc = 3.0 to 3.6  
Vcc = 3.0 to 3.6  
IL  
IH  
H
Input High Level  
Input Hysterisis  
60  
1
mV  
nA  
pF  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
Gross tested to 1 μA.  
IL  
C
3.5  
10  
Pin dependent.  
IN  
o
Temp = 25 C.  
C
Capacitive Load on Pins as Output  
3.5  
10  
pF  
Pin dependent.  
Temp = 25 C.  
OUT  
o
Document #: 001-43991 Rev. *D  
Page 11 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Operational Amplifier Specifications  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.  
Table 7. 3.3V DC Operational Amplifier Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Average Input Offset Voltage Drift  
High Power is 5 Volts Only  
OSOA  
1.65  
1.32  
7.0  
10  
8
mV  
mV  
o
TCV  
I
35.0  
μV/ C  
OSOA  
Input Leakage Current (Port 0 Analog  
Pins)  
200  
pA  
Gross tested to 1 μA.  
EBOA  
o
C
Input Capacitance (Port 0 Analog Pins)  
Common Mode Voltage Range  
Common Mode Rejection Ratio  
Open Loop Gain  
4.5  
9.5  
Vcc  
pF  
V
Pin dependent. Temp = 25 C.  
INOA  
V
0
60  
CMOA  
CMRR  
dB  
dB  
V
OA  
G
80  
OLOA  
V
High Output Voltage Swing (internal  
signals)  
Vcc - 0.01  
OHIGHOA  
OLOWOA  
SOA  
V
Low Output Voltage Swing (internal  
signals)  
0.01  
V
I
Supply Current  
(including associated AGND buffer)  
Power = Low, Opamp Bias = Low  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
Power = High, Opamp Bias = High  
Supply Voltage Rejection Ratio  
150  
300  
600  
1200  
2400  
200  
400  
800  
1600  
3200  
μA  
μA  
μA  
μA  
μA  
μA  
dB  
Not Allowed for 3.3V operation  
PSRR  
54  
80  
Vss VIN (Vcc - 2.25) or  
(Vcc - 1.25V) VIN Vcc  
OA  
DC Low Power Comparator Specifications  
Table 8. 3.3V DC Low Power Comparator Specifications (CY8CNP102B)  
Symbol  
Description  
Low power comparator (LPC) reference voltage range  
LPC supply current  
Min  
0.2  
Typ  
Max  
Vcc - 1.0  
40  
Units  
V
V
I
REFLPC  
10  
2.5  
μA  
SLPC  
V
LPC voltage offset  
30  
mV  
OSLPC  
Document #: 001-43991 Rev. *D  
Page 12 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Analog Output Buffer Specifications  
Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B)  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Output Resistance  
Min  
Typ  
3
Max  
12  
Units  
mV  
V
OSOB  
TCV  
+6  
-
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vcc - 1.0  
R
OUTOB  
Power = Low  
10  
10  
Ω
Ω
Power = High  
V
High Output Voltage Swing  
(Load = 1KΩ to Vcc/2)  
OHIGHOB  
OLOWOB  
SOB  
Power = Low  
Power = High  
0.5 x Vcc + 1.0  
0.5 x Vcc + 1.0  
V
V
V
Low Output Voltage Swing  
(Load = 1KΩ to Vcc/2)  
Power = Low  
Power = High  
0.5 x Vcc - 1.0  
0.5 x Vcc - 1.0  
V
V
I
Supply Current Including Bias Cell  
(No Load)  
Power = Low  
0.8  
2.0  
64  
1
5
mA  
mA  
dB  
Power = High  
PSRR  
Supply Voltage Rejection Ratio  
60  
OB  
Document #: 001-43991 Rev. *D  
Page 13 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Analog Reference Specifications  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Reference control power is high.  
Table 10. 3.3V DC Analog Reference Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
1.28  
Typ  
Max  
1.32  
Units  
V
Bandgap Voltage Reference 3.3V  
1.30  
V
V
BG33  
AGND = Vcc/2  
Vcc/2 - 0.02  
Vcc/2  
Not Allowed  
P2[4]  
Vcc/2 + 0.02  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vcc/2)  
P2[4] - 0.009  
1.27  
P2[4] + 0.009  
1.34  
V
V
[1]  
AGND = BandGap  
1.30  
AGND = 1.6 x BandGap  
2.03  
2.08  
2.13  
V
AGND Block to Block Variation (AGND = Vcc/2)  
RefHi = Vcc/2 + BandGap  
-0.034  
0.000  
0.034  
mV  
Not Allowed  
RefHi = 3 x BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)  
RefHi = P2[4] + BandGap (P2[4] = Vcc/2)  
RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042  
V
V
RefHi = 2 x BandGap  
2.50  
Not Allowed  
2.60  
2.70  
RefHi = 3.2 x BandGap  
RefLo = Vcc/2 - BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefLo = BandGap  
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)  
RefLo = P2[4] – BandGap (P2[4] = Vcc/2)  
RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.036 P2[4] - P2[6] P2[4] - P2[6] + 0.036  
V
DC Analog PSoC NV Block Specifications  
Table 11. 3.3V DC Analog PSoC NV Block Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
12.2  
80  
Max  
Units  
kΩ  
R
C
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switch Cap)  
CT  
SC  
fF  
Note  
1. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.  
Document #: 001-43991 Rev. *D  
Page 14 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC POR, SMP, and LVD Specifications  
Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B)  
Symbol  
Description  
Vdd Value for PPOR Trip (positive ramp)  
PORLEV[1:0] = 00b  
Vdd Value for PPOR Trip (negative ramp)  
PORLEV[1:0] = 00b  
PPOR Hysteresis  
Min  
Typ  
2.91  
2.82  
Max  
Units  
V
V
V
PPOR0R  
V
PPOR0  
V
V
V
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
Vdd Value for LVD Trip  
VM[2:0] = 000b  
92  
0
mV  
mV  
mV  
PH0  
PH1  
PH2  
0
V
V
V
2.86  
2.96  
3.07  
2.92  
3.02  
3.13  
2.98  
3.08  
3.20  
V
V
V
LVD0  
LVD1  
LVD2  
VM[2:0] = 001b  
VM[2:0] = 010b  
Vdd Value for SMP Trip  
VM[2:0] = 000b  
V
V
V
2.96  
3.03  
3.18  
3.02  
3.10  
3.25  
3.08  
3.16  
3.32  
V
V
V
PUMP0  
PUMP1  
PUMP2  
VM[2:0] = 001b  
VM[2:0] = 010b  
Note  
2. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.  
Document #: 001-43991 Rev. *D  
Page 15 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Programming Specifications  
Table 13. 3.3V DC Programming Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
10  
Max  
30  
Units  
mA  
V
Notes  
I
Supply Current During Programming or Verify  
Input Low Voltage During Programming or Verify  
Input High Voltage During Programming or Verify  
DDPV  
V
V
0.8  
ILP  
2.2  
V
IHP  
I
Input Current when Applying Vilp to P1[0] or P1[1]  
During Programming or Verify  
0.2  
mA Driving internal pull  
down resistor.  
ILP  
I
Input Current when Applying Vihp to P1[0] or P1[1]  
During Programming or Verify  
1.5  
mA Driving internal pull  
down resistor.  
IHP  
V
V
Output Low Voltage During Programming or Verify  
Output High Voltage During Programming or Verify  
Flash Endurance (per block)  
Vss + 0.75  
V
V
OLV  
Vcc - 1.0  
50,000  
Vcc  
OHV  
Flash  
Erase/write cycles  
per block.  
ENPB  
[3]  
Flash  
Flash  
Flash Endurance (total)  
1,800,000  
10  
Erase/write cycles.  
ENT  
Flash Data Retention  
Years  
DR  
Note  
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single lock ever sees  
Document #: 001-43991 Rev. *D  
Page 16 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Electrical Characteristics  
The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature  
range: 3.0V to 3.6V over the temperature range of -40°C T 85°C. Typical parameters apply to 3.3V at 25°C and are for design  
A
guidance only.  
AC Chip Level Specifications  
Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
F
Internal Main Oscillator Frequency for  
24 MHz  
23.4  
24  
24.6  
MHz Trimmed for 3.3V operation using  
factory trim values. See the figure  
on page 10. SLIMO Mode = 0.  
IMO24  
F
Internal Main Oscillator Frequency for  
6 MHz  
5.75  
6
6.35  
MHz Trimmed for 3.3V operation using  
factory trim values. See the figure  
on page 10.  
IMO6  
SLIMO Mode = 1.  
F
F
CPU Frequency (3.3V Nominal)  
Digital PSoC Block Frequency  
0.93  
0
12  
48  
12.3  
MHz  
CPU2  
49.2  
MHz Refer to section AC Digital Block  
48M  
F
F
F
Digital PSoC Block Frequency  
Internal Low Speed Oscillator Frequency  
External Crystal Oscillator  
0
15  
24  
32  
24.6  
MHz  
kHz  
24M  
64  
32K1  
32K2  
32.768  
kHz Accuracy is capacitor and crystal  
dependent. 50% duty cycle.  
F
PLL Frequency  
23.986  
MHz A multiple (x732) of crystal  
frequency.  
PLL  
Jitter24M2  
24 MHz Period Jitter (PLL)  
0.5  
0.5  
600  
10  
ps  
ms  
ms  
ms  
T
T
T
T
PLL Lock Time  
PLLSLEW  
PLLSLEWLOW  
OS  
PLL Lock Time for Low Gain Setting  
External Crystal Oscillator Startup to 1%  
50  
250  
300  
500  
600  
External Crystal Oscillator Startup to  
100 ppm  
ms The crystal oscillator frequency is  
within 100 ppm of its final value  
OSACC  
by the end of the T  
period.  
osacc  
Correct operation assumes a  
properly loaded 1 uW maximum  
drive level 32.768 kHz crystal.  
Jitter32k  
32 kHz Period Jitter  
10  
40  
100  
ns  
μs  
T
External Reset Pulse Width  
24 MHz Duty Cycle  
60  
XRST  
DC24M  
50  
%
Step24M  
Fout48M  
24 MHz Trim Step Size  
48 MHz Output Frequency  
50  
kHz  
[4,6]  
46.8  
48.0  
49.2  
MHz Trimmed. Using factory trim  
values.  
Jitter24M1  
24 MHz Period Jitter (IMO)  
600  
ps  
F
Maximum frequency of signal on row input  
or row output.  
12.3  
MHz  
MAX  
T
Supply Ramp Time  
0
μs  
RAMP  
Notes  
4. 4.75V < Vcc < 5.25V.  
5. Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range.  
6. 3.0V < Vcc < 3.6V. See Application Note AN2012 “Adjusting PSoC Micro controller Trims for Dual Voltage-Range Operation” for information on trimming for operation  
at 3.3V.  
7. See individual user module data sheets for information on maximum frequencies for user modules.  
Document #: 001-43991 Rev. *D  
Page 17 of 38  
         
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
In the following table, t  
starts from the time Vcc rises above V  
If an SRAM WRITE has not taken place since the last  
SWITCH.  
HRECALL  
nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum.  
Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B)  
nvSRAM  
Parameter  
Description  
Unit  
Min  
Max  
20  
t
t
Power Up RECALL Duration  
STORE Cycle Duration  
Low Voltage Trigger Level  
VCC Rise Time  
ms  
ms  
V
HRECALL  
12.5  
2.65  
STORE  
V
t
SWITCH  
150  
μs  
VccRISE  
AC General Purpose IO Specifications  
Table 16. 3.3V AC GPIO Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
F
GPIO Operating Frequency  
0
12.3  
MHz Normal Strong Mode  
GPIO  
TRiseS  
Rise Time, Slow Strong Mode, Cload = 50 pF  
10  
27  
ns Vcc = 3V to 3.6V  
10% - 90%  
TFallS  
Fall Time, Slow Strong Mode, Cload = 50 pF  
10  
22  
ns Vcc = 3V to 3.6V  
10% - 90%  
Figure 6. GPIO Timing Diagram  
90%  
GPIO  
Pin  
Output  
Voltage  
10%  
TRiseF  
TRiseS  
TFallF  
TFallS  
Document #: 001-43991 Rev. *D  
Page 18 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Operational Amplifier Specifications  
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
T
Rising Settling Time to 0.1% of a 1V Step  
(10 pF load, Unity Gain)  
Power = High and  
Opamp Bias = High is  
not supported at  
3.3V.  
ROA  
Power = Low, Opamp Bias = Low  
3.92  
0.72  
μs  
Power = Medium, Opamp Bias = High  
μs  
T
Falling Settling Time to 0.1% of a 1V Step  
(10 pF load, Unity Gain)  
SOA  
Power = Low, Opamp Bias = Low  
5.41  
0.72  
μs  
Power = Medium, Opamp Bias = High  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%) of a 1V Step  
(10 pF load, Unity Gain)  
ROA  
FOA  
Power = Low, Opamp Bias = Low  
0.31  
2.7  
V/μs  
Power = Medium, Opamp Bias = High  
V/μs  
Falling Slew Rate (20% to 80%) of a 1V Step  
(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Gain Bandwidth Product  
0.24  
1.8  
V/μs  
V/μs  
BW  
OA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
0.67  
2.8  
MHz  
MHz  
E
Noise at 1 kHz  
100  
nV/rt-Hz  
NOA  
(Power = Medium, Opamp Bias = High)  
AC Digital Block Specifications  
Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B)  
Function  
Description  
Min  
Typ  
Max  
Units  
Notes  
All Functions Maximum Block Clocking Frequency  
24.6  
MHz 3.0V Vcc 3.6V  
Timer  
Capture Pulse Width  
50  
ns  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
24.6  
24.6  
MHz 3.0V Vcc 3.6V.  
MHz 3.0V Vcc 3.6V.  
ns  
Counter  
50  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
24.6  
24.6  
MHz 3.0V Vcc 3.6V.  
MHz 3.0V Vcc 3.6V.  
Dead Band Kill Pulse Width:  
Asynchronous Restart Mode  
20  
ns  
Synchronous Restart Mode  
Disable Mode  
50  
ns  
50  
ns  
Maximum Frequency  
24.6  
MHz 3.0V Vcc 3.6V  
Note  
8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
Document #: 001-43991 Rev. *D  
Page 19 of 38  
   
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued)  
Function  
Description  
Maximum Input Clock Frequency  
Min  
Typ  
Max  
Units  
Notes  
CRCPRS  
(PRS Mode)  
24.6  
MHz 3.0V Vcc 3.6V  
CRCPRS  
(CRC Mode)  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
24.6  
8.2  
MHz 3.0V Vcc 3.6V.  
SPIM  
MHz Maximumdatarateat  
4.1 MHz due to 2 x  
over clocking.  
SPIS  
Maximum Input Clock Frequency  
4.1  
ns  
ns  
Width of SS_ Negated Between Transmissions  
50  
Transmitter Maximum Input Clock Frequency  
24.6  
MHz Maximumdatarateat  
3.08 MHz due to 8 x  
over clocking.  
Vcc 3.0V, 2 Stop Bits  
49.2  
24.6  
49.2  
MHz Maximumdatarateat  
6.15 MHz due to 8 x  
over clocking.  
Receiver  
Maximum Input Clock Frequency  
MHz Maximumdatarateat  
3.08 MHz due to 8 x  
over clocking.  
Vcc 3.0V, 2 Stop Bits  
MHz Maximumdatarateat  
6.15 MHz due to 8 x  
over clocking.  
AC Analog Output Buffer Specifications  
Table 19. 3.3V AC Analog Output Buffer Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100pF Load  
ROB  
Power = Low  
4.7  
4.7  
μs  
Power = High  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100pF Load  
SOB  
Power = Low  
4
4
μs  
Power = High  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load  
ROB  
FOB  
Power = Low  
0.36  
0.36  
V/μs  
Power = High  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load  
Power = Low  
Power = High  
0.4  
0.4  
V/μs  
V/μs  
BW  
Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load  
OB  
OB  
pp  
Power = Low  
Power = High  
0.7  
0.7  
MHz  
MHz  
BW  
Large Signal Bandwidth, 1V , 3dB BW, 100pF Load  
pp  
Power = Low  
Power = High  
200  
200  
kHz  
kHz  
Document #: 001-43991 Rev. *D  
Page 20 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Programming Specifications  
Table 20. 3.3V AC Programming Specifications (CY8CNP102B)  
Symbol  
Description  
Min  
1
Typ  
Max  
20  
20  
Units  
ns  
Notes  
T
T
T
T
F
T
T
T
Rise Time of SCLK  
Fall Time of SCLK  
RSCLK  
FSCLK  
SSCLK  
HSCLK  
SCLK  
1
ns  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
Flash Erase Time (Block)  
10  
10  
ERASEB  
WRITE  
DSCLK3  
2
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
50  
ns 3.0V Vcc 3.6V  
AC I C Specifications  
2
Table 21. 3.3V AC Characteristics of the I C SDA and SCL Pins (CY8CNP102B)  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
Max  
400  
F
T
SCL Clock Frequency  
0
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period, the  
first clock pulse is generated.  
4.0  
0.6  
μs  
HDSTAI2C  
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
LOWI2C  
HIGH Period of the SCL Clock  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
SUSTOI2C  
BUFI2C  
Setup Time for a Repeated START Condition  
Data Hold Time  
Data Setup Time  
250  
4.0  
4.7  
100  
0.6  
1.3  
0
Setup Time for STOP Condition  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
50  
SPI2C  
Note  
9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. This is automatically the  
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit  
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.  
Document #: 001-43991 Rev. *D  
Page 21 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
5V Operation  
Absolute Maximum Ratings  
Table 22. 5V Absolute Maximum Ratings (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
o
T
Storage Temperature  
-55  
25  
+100  
C
Higher storage temperatures  
reduce data retention time.  
Recommended storage  
STG  
o
temperature is ± 25 C. Extended  
duration storage temperatures  
o
above 65 C degrade reliability.  
o
T
Ambient Temperature with  
Power Applied  
-40  
+85  
C
A
Vcc  
Supply Voltage on Vcc  
Relative to Vss  
-0.5  
+6.0  
V
V
V
DC Input Voltage  
Vss - 0.5  
Vss - 0.5  
Vcc + 0.5  
Vcc + 0.5  
V
V
IO  
DC Voltage Applied to  
Tri-state  
IOZ  
I
I
Maximum Current into any  
Port Pin  
-25  
-50  
+50  
+50  
mA  
mA  
MIO  
Maximum Current into any  
Port Pin Configured as  
Analog Driver  
MAIO  
ESD  
LU  
Electro Static Discharge  
Voltage  
2000  
V
Human Body Model ESD.  
Latch-up Current  
200  
mA  
Operating Temperature  
Table 23. 5V Operating Temperature (CY8CNP102E)  
Symbol  
Description  
Ambient Temperature  
Junction Temperature  
Min  
-40  
-40  
Typ  
Max  
+85  
Units  
Notes  
o
T
C
A
o
T
+100  
C
J
Document #: 001-43991 Rev. *D  
Page 22 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Electrical Characteristics  
The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature  
ranges: 4.75V to 5.25V over the Temperature range of -40°C T 85°C. Typical parameters apply to 5V at 25°C and are for design  
A
guidance only.  
DC Chip Level Specifications  
Table 24. 5V DC Chip-Level Specifications (CY8CNP102E)  
Symbol  
Vcc  
Description  
Supply Voltage  
Min  
4.75  
Typ  
Max  
5.25  
45  
Units  
V
Notes  
o
I
I
I
Supply Current  
39  
mA  
T = 25 C, CPU = 3 MHz,  
DD  
A
SYSCLK doubler disabled,  
VC1 = 1.5 MHz, VC2 = 93.75 kHz,  
VC3 = 0.366 kHz, continuous  
nvSRAM access  
o
Supply current when IMO = 6 MHz  
using SLIMO mode.  
27  
28  
5
mA  
mA  
T = 25 C, CPU = 0.75 MHz,  
DDP  
SB  
A
SYSCLK doubler disabled,  
VC1=0.375 MHz, VC2=23.44  
kHz, VC3 = 0.09 kHz, continuous  
nvSRAM access  
Sleep (Mode) Current with POR,  
LVD, Sleep Timer, WDT, and  
internal slow oscillator active.  
nvSRAM in standby.  
V
V
Reference Voltage (Bandgap)  
1.28  
61  
1.3  
68  
1.32  
82  
V
Trimmed for appropriate Vcc.  
5V rated (minimum)  
REF  
Storage Capacitor between Vcap  
and Vss  
uF  
cap  
DC General Purpose IO Specifications  
Table 25. 5V DC GPIO Specifications (CY8CNP102E)  
Symbol  
Description  
Pull up Resistor  
Min  
Typ  
5.6  
5.6  
Max  
Units  
kΩ  
kΩ  
Notes  
R
4
4
8
8
PU  
PD  
OH  
R
Pull down Resistor  
High Output Level  
V
Vcc - 1.0  
V
IOH = 10 mA, Vcc = 4.75 to 5.25V.  
8 total loads, 4 on even port pins  
(for example, P0[2], P1[4]), 4 on  
odd port pins (for example, P0[3],  
P1[5]). 80 mA maximum  
combined IOH budget.  
V
Low Output Level  
0.75  
0.8  
V
IOL = 25 mA, Vcc = 4.75 to 5.25V  
8 total loads, 4 on even port pins  
(for example, P0[2], P1[4]), 4 on  
odd port pins (for example, P0[3],  
P1[5]). 150 mA maximum  
OL  
combined IOL budget.  
V
V
V
I
Input Low Level  
2.1  
V
V
4.75 to 5.25.  
4.75 to 5.25.  
IL  
IH  
H
Input High Level  
Input Hysterisis  
60  
1
mV  
nA  
pF  
pF  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
Capacitive Load on Pins as Output  
Gross tested to 1 μA.  
Pin dependent. Temp = 25 C.  
IL  
o
C
C
3.5  
3.5  
10  
10  
IN  
o
Pin dependent. Temp = 25 C.  
OUT  
Document #: 001-43991 Rev. *D  
Page 23 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Operational Amplifier Specifications  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.  
Table 26. 5V DC Operational Amplifier Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
Average Input Offset Voltage Drift  
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
OSOA  
1.6  
1.3  
1.2  
7.0  
200  
4.5  
10  
8
mV  
mV  
mV  
7.5  
35.0  
o
TCV  
μV/ C  
OSOA  
I
pA Gross tested to 1 μA.  
EBOA  
o
C
9.5  
pF  
Pin dependent. Temp = 25 C.  
INOA  
V
Common Mode Voltage Range.  
All Cases, except highest.  
CMOA  
0.0  
0.5  
60  
Vcc  
V
V
Power = High, Opamp Bias = High  
Common Mode Rejection Ratio  
Open Loop Gain  
Vcc - 0.5  
CMRR  
dB  
dB  
V
OA  
G
80  
OLOA  
V
V
High Output Voltage Swing (internal signals) Vcc - 0.01  
OHIGHOA  
OLOWOA  
SOA  
Low Output Voltage Swing (internal signals)  
0.1  
V
I
Supply Current  
(including associated AGND buffer)  
Power = Low, Opamp Bias = Low  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
Power = High, Opamp Bias = High  
Supply Voltage Rejection Ratio  
150  
300  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
600  
1200  
2400  
4600  
80  
PSRR  
67  
dB Vss VIN (Vcc - 2.25) or  
OA  
(Vcc - 1.25V) VIN Vcc.  
DC Low Power Comparator Specifications  
Table 27. 5V DC Low Power Comparator Specifications (CY8CNP102E)  
Symbol  
Description  
Low power comparator (LPC) reference voltage range  
LPC supply current  
Min  
0.2  
Typ  
Max  
Vcc - 1.0  
40  
Units  
V
V
REFLPC  
SLPC  
I
10  
2.5  
μA  
V
LPC voltage offset  
30  
mV  
OSLPC  
Document #: 001-43991 Rev. *D  
Page 24 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Analog Output Buffer Specifications  
Table 28. 5V DC Analog Output Buffer Specifications (CY8CNP102E)  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Output Resistance  
Min  
Typ  
3
Max  
12  
Units  
mV  
V
OSOB  
TCV  
+6  
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vcc - 1.0  
R
OUTOB  
Power = Low  
1
1
Ω
Ω
Power = High  
V
V
High Output Voltage Swing (Load = 32 ohms to Vcc/2)  
Power = Low  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vcc + 1.3  
0.5 x Vcc + 1.3  
V
V
Power = High  
Low Output Voltage Swing (Load = 32 ohms to Vcc/2)  
Power = Low  
0.5 x Vcc - 1.3  
0.5 x Vcc - 1.3  
V
V
Power = High  
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
1.1  
2.6  
64  
2
5
mA  
mA  
dB  
Power = High  
PSRR  
Supply Voltage Rejection Ratio  
40  
OB  
DC Analog Reference Specifications  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Reference control power is high.  
Table 29. 5V DC Analog Reference Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
1.28  
Typ  
1.30  
Max  
1.32  
Units  
V
V
Bandgap Voltage Reference 5V  
BG5  
[1]  
AGND = Vcc/2  
Vcc/2 - 0.02  
2.52  
Vcc/2  
Vcc/2 + 0.02  
2.72  
V
AGND = 2 x BandGap  
2.60  
V
AGND = P2[4] (P2[4] = Vcc/2)  
P2[4] - 0.013  
1.27  
P2[4]  
P2[4] + 0.013  
1.34  
V
AGND = BandGap  
1.3  
V
AGND = 1.6 x BandGap  
2.03  
2.08  
2.13  
V
AGND Block to Block Variation (AGND = Vcc/2)  
RefHi = Vcc/2 + BandGap  
-0.034  
0.000  
0.034  
V
Vcc/2 + 1.21  
3.75  
Vcc/2 + 1.3  
3.9  
Vcc/2 + 1.382  
4.05  
V
RefHi = 3 x BandGap  
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)  
RefHi = P2[4] + BandGap (P2[4] = Vcc/2)  
P2[6] + 2.478  
P2[4] + 1.218  
P2[6] + 2.6  
P2[4] + 1.3  
P2[6] + 2.722  
P2[4] + 1.382  
V
V
RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058  
V
RefHi = 2 x BandGap  
2.50  
4.02  
2.60  
4.16  
2.70  
4.29  
V
RefHi = 3.2 x BandGap  
V
RefLo = Vcc/2 – BandGap  
Vcc/2 - 1.369  
1.20  
Vcc/2 - 1.30  
1.30  
Vcc/2 - 1.231  
1.40  
V
RefLo = BandGap  
V
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)  
RefLo = P2[4] – BandGap (P2[4] = Vcc/2)  
RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V)  
2.489 - P2[6]  
P2[4] - 1.368  
2.6 - P2[6]  
P2[4] - 1.30  
2.711 - P2[6]  
P2[4] - 1.232  
V
V
P2[4] - P2[6] - 0.042 P2[4] - P2[6] P2[4] - P2[6] + 0.042  
V
Document #: 001-43991 Rev. *D  
Page 25 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Analog PSoC NV Block Specifications  
Table 30. 5V DC Analog PSoC NV Block Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
12.2  
80  
Max  
Units  
kΩ  
R
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switch Cap)  
CT  
SC  
C
fF  
DC POR, SMP, and LVD Specifications  
Table 31. 5V DC POR, SMP, and LVD Specifications (CY8CNP102E)  
Symbol  
Description  
Vdd Value for PPOR Trip (positive ramp)  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
Vdd Value for PPOR Trip (negative ramp)  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
PPOR Hysteresis  
Min  
Typ  
Max  
Units  
V
2.91  
4.39  
4.55  
V
V
V
PPOR0R  
PPOR1R  
PPOR2R  
V
V
V
V
V
2.82  
4.39  
4.55  
V
V
V
PPOR0  
PPOR1  
PPOR2  
V
V
V
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
Vdd Value for LVD Trip  
VM[2:0] = 000b  
92  
0
mV  
mV  
mV  
PH0  
PH1  
PH2  
0
[2]  
V
V
V
V
V
V
V
V
2.86  
2.96  
3.07  
3.92  
4.39  
4.55  
4.63  
4.72  
2.92  
3.02  
3.13  
4.00  
4.48  
4.64  
4.73  
4.81  
2.98  
3.08  
3.20  
4.08  
4.57  
4.74  
4.82  
4.91  
V
V
V
V
V
V
V
V
LVD0  
LVD1  
LVD2  
LVD3  
LVD4  
LVD5  
LVD6  
LVD7  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
Vdd Value for SMP Trip  
VM[2:0] = 000b  
V
V
V
V
V
V
V
V
2.96  
3.03  
3.18  
4.11  
4.55  
4.63  
4.72  
4.90  
3.02  
3.10  
3.25  
4.19  
4.64  
4.73  
4.82  
5.00  
3.08  
3.16  
3.32  
4.28  
4.74  
4.82  
4.91  
5.10  
V
V
V
V
V
V
V
V
PUMP0  
PUMP1  
PUMP2  
PUMP3  
PUMP4  
PUMP5  
PUMP6  
PUMP7  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
Document #: 001-43991 Rev. *D  
Page 26 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
DC Programming Specifications  
Table 32. 5V DC Programming Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
10  
Max  
30  
Units  
mA  
V
Notes  
I
Supply Current During Programming or Verify  
Input Low Voltage During Programming or Verify  
Input High Voltage During Programming or Verify  
DDPV  
V
V
0.8  
ILP  
2.2  
V
IHP  
I
Input Current when Applying Vilp to P1[0] or  
P1[1] During Programming or Verify  
0.2  
mA  
Driving internal pull  
down resistor.  
ILP  
I
Input Current when Applying Vihp to P1[0] or  
P1[1] During Programming or Verify  
1.5  
Vss + 0.75  
Vcc  
mA  
V
Driving internal pull  
down resistor.  
IHP  
V
V
Output Low Voltage During Programming or  
Verify  
OLV  
Output High Voltage During Programming or  
Verify  
Vcc - 1.0  
50,000  
V
OHV  
Flash  
Flash Endurance (per block)  
Erase/writecyclesper  
block.  
ENPB  
[3]  
Flash  
Flash  
Flash Endurance (total)  
1,800,000  
10  
Erase/write cycles.  
ENT  
Flash Data Retention  
Years  
DR  
Document #: 001-43991 Rev. *D  
Page 27 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Electrical Characteristics  
The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature  
range: 4.75V to 5.25V over the Temperature range of -40°C T 85°C. Typical parameters apply to 5V at 25°C and are for design  
A
guidance only.  
AC Chip Level Specifications  
Table 33. 5V AC Chip Level Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
F
Internal Main Oscillator Frequency for 24 MHz  
23.4  
24 24.6  
MHz Trimmed for 5V operation  
using factory trim values.  
SLIMO Mode = 0.  
IMO24  
F
Internal Main Oscillator Frequency for 6 MHz  
5.75  
6
6.35  
MHz Trimmed for 5V operation  
using factory trim values.  
SLIMO Mode = 1.  
IMO6  
F
F
CPU Frequency (5V Nominal)  
Digital PSoC Block Frequency  
0.93  
0
24  
24.6  
MHz  
CPU1  
48 49.2  
MHz Refer to AC Digital Block  
48M  
F
F
F
Digital PSoC Block Frequency  
Internal Low Speed Oscillator Frequency  
External Crystal Oscillator  
0
15  
24  
32  
24.6  
MHz  
kHz  
24M  
64  
32K1  
32K2  
32.768  
kHz Accuracy is capacitor and  
crystal dependent. 50% duty  
cycle.  
F
PLL Frequency  
23.986  
MHz A multiple (x732) of crystal  
frequency.  
PLL  
Jitter24M2  
24 MHz Period Jitter (PLL)  
0.5  
0.5  
600  
10  
ps  
ms  
ms  
ms  
T
T
T
T
PLL Lock Time  
PLLSLEW  
PLLSLEWLOW  
OS  
PLL Lock Time for Low Gain Setting  
External Crystal Oscillator Startup to 1%  
External Crystal Oscillator Startup to 100 ppm  
50  
250  
300  
500  
600  
ms  
The crystal oscillator  
frequency is within 100 ppm  
of its final value by the end of  
OSACC  
the T  
period. Correct  
osacc  
operation assumes a  
properly loaded 1 uW  
maximum drive level 32.768  
kHz crystal.  
Jitter32k  
32 kHz Period Jitter  
10  
40  
100  
ns  
μs  
T
External Reset Pulse Width  
24 MHz Duty Cycle  
60  
XRST  
DC24M  
50  
%
Step24M  
Fout48M  
24 MHz Trim Step Size  
48 MHz Output Frequency  
50  
kHz  
46.8  
48.0  
49.2  
MHz Trimmed. Using factory trim  
values.  
Jitter24M1  
24 MHz Period Jitter (IMO)  
600  
ps  
F
Maximum frequency of signal on row input or  
row output.  
12.3  
MHz  
MAX  
T
Supply Ramp Time  
0
μs  
RAMP  
Document #: 001-43991 Rev. *D  
Page 28 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
In the following table, t  
starts from the time Vcc rises above V  
If an SRAM WRITE has not taken place since the last  
HRECALL  
SWITCH.  
nonvolatile cycle, no STORE takes place. Industrial grade devices require 15 ms maximum.  
Table 34. 5V nvSRAM AutoStore/Power Up RECALL (CY8CNP102E)  
nvSRAM  
Parameter  
Description  
Power Up RECALL Duration  
Unit  
Min  
Max  
20  
t
t
ms  
ms  
V
HRECALL  
STORE Cycle Duration  
Low Voltage Trigger Level  
VCC Rise Time  
12.5  
4.4  
STORE  
V
t
SWITCH  
150  
μs  
VccRISE  
AC General Purpose IO Specifications  
Table 35. 5V AC GPIO Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
0
Typ  
Max  
Units  
Notes  
F
GPIO Operating Frequency  
12.3  
18  
MHz Normal Strong Mode  
GPIO  
TRiseF  
Rise Time, Normal Strong Mode, Cload = 50 pF  
3
ns Vcc = 4.75V to 5.25V  
10% - 90%  
TFallF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
2
18  
ns Vcc = 4.75V to 5.25V  
10% - 90%  
Figure 7. GPIO Timing Diagram  
90%  
GPIO  
Pin  
Output  
Voltage  
10%  
TRiseF  
TRiseS  
TFallF  
TFallS  
Document #: 001-43991 Rev. *D  
Page 29 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Operational Amplifier Specifications  
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Table 36. 5V AC Operational Amplifier Specifications (CY8CNP102E)  
Symbol  
Description  
Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Min  
Typ  
Max  
Units  
T
ROA  
3.9  
μs  
μs  
μs  
Power = Medium, Opamp Bias = High  
0.72  
0.62  
Power = High, Opamp Bias = High  
T
Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
SOA  
5.9  
μs  
μs  
μs  
Power = Medium, Opamp Bias = High  
0.92  
0.72  
Power = High, Opamp Bias = High  
SR  
Rising Slew Rate (20% to 80%) of a 1V Step  
(10 pF load, Unity Gain)  
ROA  
FOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
0.15  
1.7  
V/μs  
V/μs  
V/μs  
6.5  
SR  
Falling Slew Rate (20% to 80%) of a 1V Step  
(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
Gain Bandwidth Product  
0.01  
0.5  
V/μs  
V/μs  
V/μs  
4.0  
BW  
OA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
0.75  
3.1  
5.4  
MHz  
MHz  
MHz  
E
100  
nV/rt-Hz  
NOA  
AC Digital Block Specifications  
Table 37. 5V AC Digital Block Specifications (CY8CNP102E)  
Function  
All  
Functions  
Description  
Min  
Typ  
Max  
Units  
Notes  
Maximum Block Clocking Frequency  
49.2  
MHz 4.75V Vcc 5.25V.  
Timer  
Capture Pulse Width  
50  
ns  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz 4.75V Vcc 5.25V.  
MHz 4.75V Vcc 5.25V.  
ns  
Counter  
50  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
Kill Pulse Width:  
49.2  
24.6  
MHz 4.75V Vcc 5.25V.  
MHz 4.75V Vcc 5.25V.  
Dead Band  
Asynchronous Restart Mode  
Synchronous Restart Mode  
Disable Mode  
20  
ns  
50  
ns  
50  
ns  
Maximum Frequency  
49.2  
49.2  
MHz 4.75V Vcc 5.25V  
MHz 4.75V Vcc 5.25V  
CRCPRS  
(PRS Mode)  
Maximum Input Clock Frequency  
Document #: 001-43991 Rev. *D  
Page 30 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Table 37. 5V AC Digital Block Specifications (CY8CNP102E) (continued)  
Function  
CRCPRS  
(CRC Mode)  
Description  
Min  
Typ  
Max  
Units  
Notes  
Maximum Input Clock Frequency  
24.6  
MHz 4.75V Vcc 5.25V.  
SPIM  
Maximum Input Clock Frequency  
8.2  
MHz Maximumdatarateat  
4.1 MHz due to 2 x  
over clocking.  
SPIS  
Maximum Input Clock Frequency  
4.1  
ns  
ns  
Width of SS_ Negated Between Transmis-  
sions  
50  
Transmitter  
Maximum Input Clock Frequency  
Vcc 4.75V, 2 Stop Bits  
24.6  
49.2  
24.6  
49.2  
MHz Maximumdatarateat  
3.08 MHz due to 8 x  
over clocking.  
MHz Maximumdatarateat  
6.15 MHz due to 8 x  
over clocking.  
Receiver  
Maximum Input Clock Frequency  
Vcc 4.75V, 2 Stop Bits  
MHz Maximumdatarateat  
3.08 MHz due to 8 x  
over clocking.  
MHz Maximumdatarateat  
6.15 MHz due to 8 x  
over clocking.  
AC Analog Output Buffer Specifications  
Table 38. 5V AC Analog Output Buffer Specifications (CY8CNP102E)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
ROB  
Power = Low  
4
4
μs  
Power = High  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
SOB  
Power = Low  
3.4  
3.4  
μs  
Power = High  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
ROB  
FOB  
Power = Low  
0.5  
0.5  
V/μs  
Power = High  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.55  
0.55  
V/μs  
V/μs  
BW  
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load  
OB  
OB  
pp  
Power = Low  
Power = High  
0.8  
0.8  
MHz  
MHz  
BW  
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load  
pp  
Power = Low  
Power = High  
300  
300  
kHz  
kHz  
Document #: 001-43991 Rev. *D  
Page 31 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
AC Programming Specifications  
Table 39. 5V AC Programming Specifications (CY8CNP102E)  
Symbol Description  
Min  
1
Typ  
Max  
20  
20  
Units  
ns  
Notes  
T
T
T
T
F
T
T
T
Rise Time of SCLK  
Fall Time of SCLK  
RSCLK  
1
ns  
FSCLK  
SSCLK  
HSCLK  
SCLK  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
Flash Erase Time (Block)  
10  
10  
ERASEB  
WRITE  
DSCLK  
2
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
45  
ns 4.75V Vcc 5.25V  
AC I C Specifications  
2
Table 40. 5V AC Characteristics of the I C SDA and SCL Pins (CY8CNP102E)  
Standard Mode  
Fast Mode  
Units  
Symbol  
Description  
Min  
0
Max  
100  
Min  
Max  
400  
F
T
SCL Clock Frequency  
0
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this  
period, the first clock pulse is generated.  
4.0  
0.6  
μs  
HDSTAI2C  
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
LOWI2C  
HIGH Period of the SCL Clock  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
SUSTOI2C  
BUFI2C  
Setup Time for a Repeated START Condition  
Data Hold Time  
Data Setup Time  
250  
4.0  
4.7  
100  
0.6  
1.3  
0
Setup Time for STOP Condition  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
50  
SPI2C  
Document #: 001-43991 Rev. *D  
Page 32 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Switching Waveforms  
Figure 8. AutoStore/Power Up RECALL  
No STORE occurs  
without atleast one  
SRAM write  
STORE occurs only  
if a SRAM write  
has happened  
V
CC  
V
SWITCH  
tVCCRISE  
AutoStore  
tSTORE  
tSTORE  
POWER-UP RECALL  
Read & Write Inhibited  
tHRECALL  
tHRECALL  
Figure 9. PLL Lock Timing Diagram  
P L L  
E n a b le  
T
2 4 M H z  
P L L S L E W  
F P L L  
P L L  
0
G a in  
Figure 10. PLL Lock for Low Gain Setting Timing Diagram  
P L L  
E n a b le  
T
2 4 M H z  
P L L S L E W L O W  
F P L L  
P L L  
1
G a in  
Document #: 001-43991 Rev. *D  
Page 33 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Switching Waveforms (continued)  
Figure 11. External Crystal Oscillator Startup Timing Diagram  
3 2 K  
S e le c t  
3 2 k H z  
T
O S  
F 3 2 K 2  
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram  
J itte r 2 4 M 1  
F
2 4 M  
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram  
J itte r 3 2 k  
F
3 2 K 2  
2
Figure 14. Definition of Timing for Fast/Standard Mode on the I C Bus  
SDA  
t
t
t
f
t
f
t
t
t
r
t
SUDATI2C  
t
BUFI2C  
HDSTAI2C  
SPI2C  
r
LOWI2C  
SCL  
t
t
t
SUSTAI2C  
SUSTOI2C  
HDSTAI2C  
t
t
HIGHI2C  
P
S
S
HDDATI2C  
Sr  
Document #: 001-43991 Rev. *D  
Page 34 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Part Numbering Nomenclature  
C
Y
8
C
N
P
1
0
2
B
-
A
X
I
Cypress  
Temp:  
C = Commercial  
I = Industrial  
Microcontroller  
C = CMOS  
X = Pb free  
A = 100TQFP  
B = 3.3V  
E = 5V  
NP = PSoC NV Family  
Density:  
01 = 1Mb  
02 = 2Mb  
12 = 512Kb  
Processor Type:  
1 = M8C (PSoC1 Based)  
Ordering Information  
Ordering Code  
CY8CNP102B-AXI  
CY8CNP102E-AXI  
Package Diagram  
51 - 85048  
Package Type  
100-pin TQFP  
100-pin TQFP  
Operating Range  
Industrial  
51 - 85048  
All the above mentioned parts are of “Pb-free” type and contain preliminary information. Please contact your local Cypress sales representative for  
availability of these parts.  
Document #: 001-43991 Rev. *D  
Page 35 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Packaging Information  
This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package.  
Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation  
tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161.  
Package Diagrams  
Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm  
51-85048 *C  
Thermal Impedance  
Table 41. Thermal Impedance  
Package  
Typical θ  
*
Typical θ  
*
JA  
JC  
100 TQFP  
26.14 oC/W  
5.81 oC/W  
Note  
10. * T = T + POWER x θJA  
J
A
Document #: 001-43991 Rev. *D  
Page 36 of 38  
 
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Document History Page  
Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV)  
Document Number: 001-43991  
Submission  
REV.  
ECN  
Orig. of Change  
Description of Change  
Date  
**  
1941108 vsutmp8/AESA  
See ECN  
See ECN  
New Data Sheet  
*A  
*B  
2378513  
2512803  
PYRS  
Move to external web  
GVCH/PYRS  
06/05/2008 Features: Added total no. of GPIO information in Programmable Pin  
configurations  
Changed Pin no.14 from P3_7 to NC in the Pin diagram  
Table 1: Updated Pin definitions  
Table 5: Changed Typ and max value of IDD from 25 mA and 29mA to 36 mA  
and 40 mA resp.  
Table 5: Changed Typ and max value of IDDP from 15 mA and 16 mA to  
27 mA and 28 mA respectively.  
Table 5: Changed Min and Max value of VCAP from 56 uF and 100 uF to  
61 uF and 82 uF resp.  
Table 6: Changed VIH min value from 2.1 mV to 1.6 mV  
Added Table 12: DC POR,SMP, and LVD specifications  
Table 13: Changed IDDP naming convention to IDDPV  
Table 14: Updated note references  
Table 17: Updated Timer, Counter, deadband and CRCPS (PRS mode)  
values  
Table 23: Changed Typ and max value of IDD from 28 mA and 34 mA to  
39 mA and 45 mA resp.  
Table 23: Changed Typ and max value of IDDP from 15 mA and 16 mA to  
27 mA and 28 mA resp.  
Table 23: Changed Min and Max value of VCAP from 56 uF and 100 uF to  
61 uF and 82 uF resp.  
Added Table 30: DC POR,SMP, and LVD specifications  
Table 31: Changed IDDP naming convention to IDDPV  
table 32: Updated note references  
Updated Figure 14: Definition for Timing for Fast/Standard Mode on the I2C  
bus  
Updated part Numbering Nomenclature  
Updated Thermal Impedance table  
Updated data sheet template  
*C  
*D  
2571208  
2594976  
GVCH/PYRS  
GVCH/PYRS  
09/23/08  
10/22/08  
Changed Title from nvPSoC to PSoC NV  
Updated “Features”  
Added M8C processor speeds for 3.3V and 5V operation in “Features”  
Updated Logic block diagram  
Changed total GPIOs from 27 to 33  
Changed pin number 53 name from P1_4 to P1_6  
Changed pin definition of pin 79 and 99  
Table 5: Changed ISB from 3 mA to 5 mA  
Updated Table 12  
Table 24: Changed ISB from 3 mA to 5 mA  
Document #: 001-43991 Rev. *D  
Page 37 of 38  
PRELIMINARY  
CY8CNP102B, CY8CNP102E  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Clocks & Buffers  
Wireless  
Memories  
CAN 2.0b  
Image Sensors  
USB  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 001-43991 Rev. *D  
Revised October 20, 2008  
Page 38 of 38  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
trademarks referenced herein are property of the respective corporations. AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned  
in this document are the trademarks of their respective holders.  

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