Cypress CY8C24123 User Manual

CY8C24123  
CY8C24223, CY8C24423  
PSoC® Programmable System-on-Chip™  
Additional System Resources  
I CSlave, Master, and Multi-Master to 400 kHz  
Features  
2
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
3.0 to 5.25 V Operating Voltage  
Operating Voltages Down to 1.0V Using On-Chip Switch  
Mode Pump (SMP)  
Complete Development Tools  
Free Development Software (PSoC Designer™)  
Full-Featured, In-Circuit Emulator and Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
Industrial Temperature Range: -40°C to +85°C  
Advanced Peripherals (PSoC Blocks)  
Six Rail-to-Rail Analog PSoC Blocks Provide:  
• Up to 14-Bit ADCs  
• Up to 8-Bit DACs  
Logic Block Diagram  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
Four Digital PSoC Blocks Provide:  
• 8 to 32-Bit Timers, Counters, and PWMs  
• CRC and PRS Modules  
Analog  
Port 2 Port 1 Port 0  
Drivers  
PSoC CORE  
• Full-Duplex UART  
System Bus  
• Multiple SPIMasters or Slaves  
• Connectable to all GPIO Pins  
Complex Peripherals by Combining Blocks  
Global Digital Interconnect  
Global Analog Interconnect  
SRAM  
SROM  
Flash 4K  
Precision, Programmable Clocking  
256 Bytes  
Internal ± 2.5% 24/48 MHz Oscillator  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
Flexible On-Chip Memory  
4K Bytes Flash Program Storage 50,000 Erase/Write Cycles  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Flexible Protection Modes  
EEPROM Emulation in Flash  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Analog  
Block  
Array  
Digital  
Block Array  
(1 Rows,  
4 Blocks)  
(2 Columns,  
6 Blocks)  
Analog  
Input  
Muxing  
Programmable Pin Configurations  
25 mA Sink on all GPIO  
Pull up, Pull down, High Z, Strong, or Open Drain Drive  
Modes on all GPIO  
Up to 10 Analog Inputs on GPIO  
Two 30 mA Analog Outputs on GPIO  
Configurable Interrupt on all GPIO  
POR and LVD Internal  
Voltage  
Switch  
Mode  
Pump  
Digital  
Clocks Accum.  
Multiply  
I2C  
Decimator  
System Resets  
Ref.  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 38-12011 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 11, 2008  
 
CY8C24123  
CY8C24223, CY8C24423  
Figure 2. Analog System Block Diagram  
Analog System  
P0[7]  
P0[6]  
P0[4]  
The Analog System is composed of six configurable blocks, each  
comprised of an opamp circuit allowing the creation of complex  
analog signal flows. Analog peripherals are very flexible and can  
be customized to support specific application requirements.  
Some of the more common PSoC analog functions (most  
available as user modules) are:  
P0[5]  
P0[3]  
P0[1]  
P0[2]  
P0[0]  
Analog-to-digital converters (up to two, with 6 to 14-bit  
resolution, selectable as Incremental, Delta Sigma, and SAR)  
P2[6]  
P2[4]  
Filters (two and four pole band-pass, low-pass, and notch)  
Amplifiers (up to two, with selectable gain to 48x)  
Instrumentation amplifiers (one with selectable gain to 93x)  
Comparators (up to two, with 16 selectable thresholds)  
DACs (up to two, with 6 to 9-bit resolution)  
P2[3]  
P2[1]  
P2[2]  
P2[0]  
Multiplying DACs (up to two, with 6- to 9-bit resolution)  
High current output drivers (two with 30 mA drive as a Core  
Resource)  
Array Input Configuration  
1.3V reference (as a System Resource)  
DTMF dialer  
ACI0[1:0]  
ACI1[1:0]  
Modulators  
Correlators  
Block Array  
Peak detectors  
ACB00  
ASC10  
ASD20  
ACB01  
Many other topologies possible  
Analog blocks are provided in columns of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks. The number of blocks is dependant on the device family  
which is detailed in the table PSoC Device Characteristics on  
ASD11  
ASC21  
Analog Reference  
Interface to  
Digital System  
Reference  
Generators  
RefHi  
RefLo  
AGND  
AGNDIn  
RefIn  
Bandgap  
M8C Interface (Address Bus, Data Bus, Etc.)  
Document Number: 38-12011 Rev. *G  
Page 3 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Additional System Resources  
Getting Started  
System Resources, some of which have been previously listed,  
provide additional capability useful to complete systems.  
Additional resources include a multiplier, decimator, switch mode  
pump, low voltage detection, and power on reset. Brief state-  
ments describing the merits of each system resource follow:  
The quickest path to understanding the PSoC silicon is by  
reading this data sheet and using the PSoC Designer Integrated  
Development Environment (IDE). This data sheet is an overview  
of the PSoC integrated circuit and presents specific pin, register,  
and electrical specifications. For in-depth information, along with  
detailed programming information, refer the PSoC Program-  
mable Sytem-on-Chip Technical Reference Manual.  
Digital clock dividers provide three customizable clock  
frequencies for use in applications. The clocks can be routed  
to both the digital and analog systems. Additional clocks can  
be generated using digital PSoC blocks as clock dividers.  
For up-to-date Ordering, Packaging, and Electrical Specification  
information, refer the latest PSoC device data sheets on the web  
A multiply accumulate (MAC) provides a fast 8-bit multiplier  
with 32-bit accumulate, to assist in both general math and  
digital filters.  
Development Kits  
Development Kits are available from the following distributors:  
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store  
contains development kits, C compilers, and all accessories for  
PSoC development. Go to the Cypress Online Store web site at  
http://www.cypress.com, click the Online Store shopping cart  
icon at the bottom of the web page, and click PSoC (Program-  
mable System-on-Chip) to view a current list of available items.  
The decimator provides a custom hardware filter for digital  
signal processing applications including the creation of Delta  
Sigma ADCs.  
TheI2Cmoduleprovides100and400kHzcommunicationover  
two wires. Slave, master, and multi-master modes are all  
supported.  
Low Voltage Detection (LVD) interrupts can signal the appli-  
cation of falling voltagelevels, while the advanced POR (Power  
On Reset) circuit eliminates the need for a system supervisor.  
Technical Training  
Free PSoC technical training is available for beginners and is  
taught by a marketing or application engineer over the phone.  
PSoC training classes cover designing, debugging, advanced  
analog, and application-specific classes covering topics, such as  
PSoC and the LIN bus. Go to http://www.cypress.com, click on  
Design Support located on the left side of the web page, and  
select Technical Training for more details.  
An internal 1.3V reference provides an absolute reference for  
the analog system, including ADCs and DACs.  
An integrated switch mode pump (SMP) generates normal  
operating voltages from a single 1.2V battery cell, providing a  
low cost boost converter.  
Consultants  
PSoC Device Characteristics  
Certified PSoC Consultants offer everything from technical  
assistance to completed PSoC designs. To contact or become a  
PSoC Consultant go to http://www.cypress.com, click on Design  
Support located on the left side of the web page, and select  
CYPros Consultants.  
Depending on your PSoC device characteristics, the digital and  
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or  
3 analog blocks. The following table lists the resources available  
for specific PSoC device groups.  
Table 1. PSoC Device Characteristics  
Technical Support  
PSoC application engineers take pride in fast and accurate  
response. They can be reached with a 4-hour guaranteed  
PSoC Part  
Number  
Application Notes  
CY8C29x66 up to  
64  
4
2
2
16  
8
12  
12  
12  
12  
8
4
4
4
2
1
4
4
4
2
1
12  
12  
12  
6
A long list of application notes can assist you in every aspect of  
your design effort. To view the PSoC application notes, go to the  
http://www.cypress.com web site and select Application Notes  
under the Design Resources list located in the center of the web  
page. Application notes are listed by date as default.  
CY8C27x66 up to  
44  
CY8C27x43 up to  
44  
8
CY8C24x23 up to 1  
24  
4
CY8C22x13 up to  
16  
1
4
3
Document Number: 38-12011 Rev. *G  
Page 4 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
PSoC Designer Software Subsystems  
Development Tools  
The Cypress MicroSystems PSoC Designer is a Microsoft®  
Windows-based, integrated development environment for the  
Programmable System-on-Chip (PSoC) devices. The PSoC  
Designer IDE and application runs on Windows 98, Windows NT  
4.0, Windows 2000, Windows Millennium (Me), or Windows XP  
(refer Figure 3).  
Device Editor  
The Device Editor subsystem allows the user to select different  
onboard analog and digital components called user modules  
using the PSoC blocks. Examples of user modules are ADCs,  
DACs, Amplifiers, and Filters.  
The device editor also supports easy development of multiple  
configurations and dynamic reconfiguration. Dynamic  
configuration allows for changing configurations at run time.  
PSoC Designer helps the customer to select an operating  
configuration for the PSoC, write application code that uses the  
PSoC, and debug the application. This system provides design  
database management by project, an integrated debugger with  
In-Circuit Emulator, in-system programming support, and the  
CYASM macro assembler for the CPUs.  
PSoC Designer sets up power on initialization tables for selected  
PSoC block configurations and creates source code for an  
application framework. The framework contains software to  
operate the selected components and, if the project uses more  
than one operating configuration, contains routines to switch  
between different sets of PSoC block configurations at run time.  
PSoC Designer can print out a configuration sheet for a given  
project configuration for use during application programming in  
conjunction with the Device Data Sheet. After the framework is  
generated, the user can add application-specific code to flesh  
out the framework. It is also possible to change the selected  
components and regenerate the framework.  
PSoC Designer also supports a high-level C language compiler  
developed specifically for the devices in the family.  
Figure 3. PSoC Designer Subsystems  
Context  
Sensitive  
Help  
PSoCTM  
Designer  
Graphical Designer  
Interface  
Design Browser  
The Design Browser allows users to select and import precon-  
figured designs into the user’s project. Users can easily browse  
a catalog of preconfigured designs to facilitate time-to-design.  
Examples provided in the tools include a 300-baud modem, LIN  
Bus master and slave, fan controller, and magnetic card reader.  
Importable  
Design  
Database  
Application Editor  
PSoC  
Configuration  
Sheet  
Device  
Database  
In the Application Editor you can edit your C language and  
Assembly language source code. You can also assemble,  
compile, link, and build.  
PSoCTM  
Designer  
Core  
Application  
Database  
Assembler. The macro assembler allows the assembly code to  
be merged seamlessly with C code. The link libraries automati-  
cally use absolute addressing or can be compiled in relative  
mode, and linked with other software modules to get absolute  
addressing.  
Manufacturing  
Information  
File  
Engine  
Project  
Database  
User  
Modules  
Library  
C Language Compiler. A C language compiler is available that  
supports Cypress MicroSystems’ PSoC family devices. Even if  
you have never worked in the C language before, the product  
quickly allows you to create complete C programs for the PSoC  
family devices.  
The embedded, optimizing C compiler provides all the features  
of C tailored to the PSoC architecture. It comes complete with  
embedded libraries providing port and bus operations, standard  
keypad and display support, and extended math functionality.  
Emulation  
Pod  
In-Circuit  
Emulator  
Device  
Programmer  
Document Number: 38-12011 Rev. *G  
Page 5 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
Debugger  
User Modules and the PSoC Development  
Process  
The PSoC Designer Debugger subsystem provides hardware  
in-circuit emulation, allowing the designer to test the program in  
a physical system while providing an internal view of the PSoC  
device. Debugger commands allow the designer to read and  
program and read and write data memory, read and write IO  
registers, read and write CPU registers, set and clear break-  
points, and provide program run, halt, and step control. The  
debugger also allows the designer to create a trace buffer of  
registers and memory locations of interest.  
The development process for the PSoC device differs from that  
of a traditional fixed function microprocessor. The configurable  
analog and digital hardware blocks give the PSoC architecture a  
unique flexibility that pays dividends in managing specification  
change during development and by lowering inventory costs.  
These configurable resources, called PSoC Blocks, have the  
ability to implement a wide variety of user-selectable functions.  
Each block has several registers that determine its function and  
connectivity to other blocks, multiplexers, buses and to the IO  
pins. Iterative development cycles permit you to adapt the  
hardware as well as the software. This substantially lowers the  
risk of having to select a different part to meet the final design  
requirements.  
Online Help System  
The online help system displays online, context-sensitive help  
for the user. Designed for procedural and quick reference, each  
functional subsystem has its own context-sensitive help. This  
system also provides tutorials and links to FAQs and an Online  
Support Forum to aid the designer in getting started.  
To speed the development process, the PSoC Designer  
Integrated Development Environment (IDE) provides a library of  
pre-built, pre-tested hardware peripheral functions, called “User  
Modules.” User modules make selecting and implementing  
peripheral devices simple, and come in analog, digital, and  
mixed signal varieties. The standard User Module library  
contains over 50 common peripherals such as ADCs, DACs  
Timers, Counters, UARTs, and other not-so common peripherals  
such as DTMF Generators and Bi-Quad analog filter sections.  
Hardware Tools  
In-Circuit Emulator  
A low cost, high functionality ICE (In-Circuit Emulator) is  
available for development support. This hardware has the  
capability to program single devices.  
The emulator consists of a base unit that connects to the PC by  
way of the parallel or USB port. The base unit is universal and  
operates with all PSoC devices. Emulation pods for each device  
family are available separately. The emulation pod takes the  
place of the PSoC device in the target board and performs full  
speed (24 MHz) operation.  
Each user module establishes the basic register settings that  
implement the selected function. It also provides parameters that  
allow you to tailor its precise configuration to your particular  
application. For example, a Pulse Width Modulator User Module  
configures one or more digital PSoC blocks, one for each 8 bits  
of resolution. The user module parameters permit you to  
establish the pulse width and duty cycle. User modules also  
provide tested software to cut your development time. The user  
module application programming interface (API) provides  
high-level functions to control and respond to hardware events  
at run-time. The API also provides optional interrupt service  
routines that you can adapt as needed.  
Figure 4. PSoC Development Tool Kit  
The API functions are documented in user module data sheets  
that are viewed directly in the PSoC Designer IDE. These data  
sheets explain the internal operation of the user module and  
provide performance specifications. Each data sheet describes  
the use of each user module parameter and documents the  
setting of each register controlled by the user module.  
The development process starts when you open a new project  
and bring up the Device Editor, a pictorial environment (GUI) for  
configuring the hardware. You pick the user modules you need  
for your project and map them onto the PSoC blocks with  
point-and-click simplicity. Next, you build signal chains by inter-  
connecting user modules to each other and the IO pins. At this  
stage, you also configure the clock source connections and enter  
parameter values directly or by selecting values from drop-down  
menus. When you are ready to test the hardware configuration  
or move on to developing code for the project, you perform the  
“Generate Application” step. This causes PSoC Designer to  
generate source code that automatically configures the device to  
your specification and provides the high-level user module API  
functions.  
Document Number: 38-12011 Rev. *G  
Page 6 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 5. User Module and Source Code Development Flows  
Document Conventions  
Acronyms Used  
Device Editor  
The following table lists the acronyms that are used in this  
document.  
Placement  
User  
Module  
Selection  
Source  
Code  
Generator  
and  
Parameter  
-ization  
Table 2. Acronyms  
Acronym  
AC  
Description  
alternating current  
ADC  
API  
analog-to-digital converter  
application programming interface  
central processing unit  
continuous time  
Generate  
Application  
CPU  
CT  
Application Editor  
DAC  
DC  
digital-to-analog converter  
direct current  
Source  
Code  
Editor  
Project  
Manager  
Build  
Manager  
EEPROM electrically erasable programmable read-only  
memory  
FSR  
GPIO  
IO  
full scale range  
Build  
All  
general purpose IO  
input/output  
Debugger  
IPOR  
LSb  
imprecise power on reset  
least-significant bit  
low voltage detect  
most-significant bit  
program counter  
Event &  
Breakpoint  
Manager  
LVD  
MSb  
PC  
Interface  
to ICE  
Storage  
Inspector  
POR  
PPOR  
power on reset  
precision power on reset  
Programmable System-on-Chip  
The next step is to write your main program, and any  
sub-routines using PSoC Designer’s Application Editor  
subsystem. The Application Editor includes a Project Manager  
that allows you to open the project source code files (including  
all generated code files) from a hierarchal view. The source code  
editor provides syntax coloring and advanced edit features for  
both C and assembly language. File search capabilities include  
simple string searches and recursive “grep-style” patterns. A  
single mouse click invokes the Build Manager. It employs a  
professional-strength “makefile” system to automatically analyze  
all file dependencies and run the compiler and assembler as  
necessary. Project-level options control optimization strategies  
used by the compiler and linker. Syntax errors are displayed in a  
console window. Double clicking the error message takes you  
directly to the offending line of source code. When all is correct,  
the linker builds a ROM file image suitable for programming.  
®
PSoC  
PWM  
RAM  
ROM  
SC  
pulse width modulator  
random access memory  
read only memory  
switched capacitor  
switch mode pump  
SMP  
Units of Measure  
A units of measure table is located in the Electrical Specifications  
section. Table 7 on page 11 lists all the abbreviations used to  
measure the PSoC devices.  
Numeric Naming  
The last step in the development process takes place inside the  
PSoC Designer’s Debugger subsystem. The Debugger  
downloads the ROM image to the In-Circuit Emulator (ICE)  
where it runs at full speed. Debugger capabilities rival those of  
systems costing many times more. In addition to traditional  
single-step, run-to-breakpoint and watch-variable features, the  
Debugger provides a large trace buffer and allows you define  
complex breakpoint events that include monitoring address and  
data bus values, memory locations and external signals.  
Hexadecimal numbers are represented with all letters in  
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or  
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’  
prefix, the C coding convention. Binary numbers have an  
appended lowercase ‘b’ (for example, 01010100b’ or  
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.  
Document Number: 38-12011 Rev. *G  
Page 7 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Pinouts  
The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port  
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.  
8-Pin Part Pinout  
Table 3. 8-Pin Part Pinout (PDIP, SOIC)  
Type  
Figure 6. CY8C24123 8-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
AIO, P0[5]  
AIO, P0[3]  
I2C SCL, XTALin, P1[1]  
Vss  
Vdd  
8
7
6
5
1
2
3
4
1
IO  
IO  
IO  
IO  
IO  
P0[5] Analog column mux input and column output  
P0[3] Analog column mux input and column output  
P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)  
PDIP  
SOIC  
P0[4], AI  
P0[2], AI  
2
3
4
5
6
7
8
P1[0], XTALout, I2C SDA  
Power  
Power  
Vss  
Ground connection  
IO  
IO  
IO  
P1[0] Crystal Output (XTALout), I2C Serial Data (SDA)  
P0[2] Analog column mux input  
I
I
P0[4] Analog column mux input  
Vdd  
Supply voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
20-Pin Part Pinout  
Table 4. 20-Pin Part Pinout (PDIP, SSOP, SOIC)  
Type  
Figure 7. CY8C24223 20-Pin PSoC Device  
Pin  
No.  
Pin  
Description  
Name  
Digital Analog  
AI, P0[7]  
AIO, P0[5]  
Vdd  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
1
IO  
IO  
IO  
IO  
I
P0[7] Analog column mux input  
P0[6], AI  
AIO, P0[3]  
P0[4], AI  
P0[2], AI  
3
4
5
6
7
8
9
10  
2
3
4
5
IO  
IO  
I
P0[5] Analog column mux input and column output  
P0[3] Analog column mux input and column output  
P0[1] Analog column mux input  
AI, P0[1]  
PDIP  
SSOP  
SOIC  
SMP  
P0[0], AI  
I2C SCL, P1[7]  
I2C SDA, P1[5]  
P1[3]  
XRES  
P1[6]  
Power  
SMP Switch Mode Pump (SMP) connection to external  
components required  
P1[4], EXTCLK  
P1[2]  
I2C SCL, XTALin, P1[1]  
Vss  
P1[0], XTALout, I2C SDA  
6
IO  
IO  
IO  
IO  
P1[7] I2C Serial Clock (SCL  
P1[5] I2C Serial Data (SDA)  
P1[3]  
7
8
9
P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Power  
Input  
Vss  
Ground connection  
IO  
IO  
IO  
IO  
P1[0] Crystal Output (XTALout), I2C Serial Data (SDA)  
P1[2]  
P1[4] Optional External Clock Input (EXTCLK)  
P1[6]  
XRES Active high external reset with internal pull down  
P0[0] Analog column mux input  
P0[2] Analog column mux input  
P0[4] Analog column mux input  
P0[6] Analog column mux input  
IO  
IO  
IO  
IO  
I
I
I
I
Power  
Vdd  
Supply voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
Document Number: 38-12011 Rev. *G  
Page 8 of 43  
CY8C24123  
CY8C24223, CY8C24423  
28-Pin Part Pinout  
Table 5. 28-Pin Part Pinout (PDIP, SSOP, SOIC)  
Type  
Figure 8. CY8C24423 28-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
AI, P0[7]  
AIO, P0[5]  
AIO, P0[3]  
AI, P0[1]  
Vdd  
1
IO  
IO  
I
P0[7] Analog column mux input  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
P0[6], AI  
2
IO  
P0[5] Analog column mux input and column  
output  
P0[4], AI  
P0[2], AI  
3
IO  
IO  
I
P0[3] Analog column mux input and column  
output  
P2[7]  
P0[0], AI  
P2[5]  
P2[6], External VRef  
P2[4], External AGND  
P2[2], AI  
PDIP  
SSOP  
SOIC  
AI, P2[3]  
4
5
6
7
8
9
IO  
IO  
IO  
IO  
IO  
P0[1] Analog column mux input.  
AI, P2[1]  
P2[7]  
SMP  
P2[0], AI  
P2[5]  
I2C SCL, P1[7]  
I2C SDA, P1[5]  
P1[3]  
XRES  
P1[6]  
I
I
P2[3] Direct switched capacitor block input  
P2[1] Direct switched capacitor block input  
P1[4], EXTCLK  
P1[2]  
I2C SCL, XTALin, P1[1]  
Vss  
Power  
SMP Switch Mode Pump (SMP) connection to  
external components required  
P1[0], XTALout, I2C SDA  
10  
11  
12  
13  
IO  
IO  
IO  
IO  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial Clock  
(SCL)  
14  
15  
Power  
Input  
Vss  
Ground connection  
IO  
P1[0] Crystal Output (XTALout), I2C Serial  
Data (SDA)  
16  
17  
18  
19  
IO  
IO  
IO  
P1[2]  
P1[4] Optional External Clock Input (EXTCLK)  
P1[6]  
XRES Active high external reset with internal  
pull down  
20  
21  
22  
23  
24  
25  
26  
27  
28  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
I
P2[0] Direct switched capacitor block input  
P2[2] Direct switched capacitor block input  
P2[4] External Analog Ground (AGND)  
P2[6] External Voltage Reference (VRef)  
P0[0] Analog column mux input  
I
I
I
I
P0[2] Analog column mux input  
P0[4] Analog column mux input  
P0[6] Analog column mux input  
Power  
Vdd  
Supply voltage  
LEGEND: A = Analog, I = Input, and O = Output.  
Document Number: 38-12011 Rev. *G  
Page 9 of 43  
CY8C24123  
CY8C24223, CY8C24423  
32-Pin Part Pinout  
Table 6. 32-Pin Part Pinout (MLF*)  
Type  
Figure 9. CY8C24423 32-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
IO  
IO  
P2[7]  
P2[5]  
2
3
4
5
6
IO  
IO  
I
I
P2[3] Direct switched capacitor block input  
P2[1] Direct switched capacitor block input  
P2[7]  
P2[5]  
1
2
3
4
5
6
7
8
P0[2], AI  
24  
23  
22  
21  
Power  
Power  
Vss  
Ground connection  
P0[0], AI  
AI, P2[3]  
AI, P2[1]  
P2[6], External VRef  
P2[4], External AGND  
20 P2[2], AI  
SMP Switch Mode Pump (SMP)  
connection to external components  
required  
MLF  
(Top View)  
Vss  
SMP  
P2[0], AI  
XRES  
19  
18  
7
IO  
IO  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
I2C SCL, P1[7]  
I2C SDA, P1[5]  
8
17 P1[6]  
9
NC  
No connection. Do not use.  
10  
11  
IO  
IO  
P1[3]  
P1[1] Crystal Input (XTALin), I2C Serial  
Clock (SCL)  
12  
13  
Power  
Vss  
Ground connection  
IO  
P1[0] Crystal Output (XTALout), I2C Serial  
Data (SDA)  
14  
15  
IO  
IO  
P1[2]  
P1[4] Optional External Clock Input  
(EXTCLK)  
16  
17  
18  
NC  
No connection. Do not use.  
IO  
P1[6]  
Input  
XRES Active high external reset with  
internal pull down  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
IO  
IO  
IO  
IO  
IO  
IO  
I
I
P2[0] Direct switched capacitor block input  
P2[2] Direct switched capacitor block input  
P2[4] External Analog Ground (AGND)  
P2[6] External Voltage Reference (VRef)  
P0[0] Analog column mux input  
I
I
P0[2] Analog column mux input  
NC  
No connection. Do not use.  
IO  
IO  
I
I
P0[4] Analog column mux input  
P0[6] Analog column mux input  
Power  
Vdd  
Supply voltage  
IO  
IO  
I
P0[7] Analog column mux input  
IO  
P0[5] Analog column mux input and  
column output  
31  
32  
IO  
IO  
IO  
I
P0[3] Analog column mux input and  
column output  
P0[1] Analog column mux input  
LEGEND: A = Analog, I = Input, and O = Output.  
* The MLF package has a center pad that must be connected to the same ground as the  
Vss pin.  
Document Number: 38-12011 Rev. *G  
Page 10 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Register Mapping Tables  
Register Reference  
The PSoC device has a total register address space of 512  
bytes. The register space is also referred to as IO space and is  
broken into two parts. The XOI bit in the Flag register determines  
which bank the user is currently in. When the XOI bit is set, the  
user is said to be in the “extended” address space or the “config-  
uration” registers.  
This section lists the registers of the CY8C27xxx PSoC device  
by way of mapping tables, in offset order. For detailed register  
information,  
reference  
the  
PSoC  
Programmable  
System-on-Chip Technical Reference Manual.  
Register Conventions  
Note In the following register mapping tables, blank fields are  
Reserved and must not be accessed.  
Abbreviations Used  
The register conventions specific to this section are listed in the  
following table.  
Table 7. Abbreviations  
Convention  
RW  
Description  
Read and write register or bit(s)  
Read register or bit(s)  
R
W
L
Write register or bit(s)  
Logical register or bit(s)  
Clearable register or bit(s)  
Access is bit specific  
C
#
Document Number: 38-12011 Rev. *G  
Page 11 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
Table 8. Register Map Bank 0 Table: User Space  
PRT0DR  
PRT0IE  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
ASC10CR0  
ASC10CR1  
ASC10CR2  
ASC10CR3  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
PRT0GS  
PRT0DM2  
PRT1DR  
PRT1IE  
PRT1GS  
PRT1DM2  
PRT2DR  
PRT2IE  
PRT2GS  
PRT2DM2  
ASD20CR0  
ASD20CR1  
ASD20CR2  
ASD20CR3  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
I2C_CFG  
I2C_SCR  
I2C_DR  
RW  
#
RW  
#
I2C_MSCR  
INT_CLR0  
INT_CLR1  
RW  
RW  
INT_CLR3  
INT_MSK3  
RW  
RW  
DBB00DR0  
DBB00DR1  
DBB00DR2  
DBB00CR0  
DBB01DR0  
DBB01DR1  
DBB01DR2  
DBB01CR0  
DCB02DR0  
DCB02DR1  
DCB02DR2  
DCB02CR0  
DCB03DR0  
DCB03DR1  
#
AMX_IN  
RW  
INT_MSK0  
INT_MSK1  
INT_VC  
RW  
RW  
RC  
W
W
RW  
#
ARF_CR  
CMP_CR0  
ASY_CR  
CMP_CR1  
RW  
#
RES_WDT  
DEC_DH  
DEC_DL  
DEC_CR0  
DEC_CR1  
MUL_X  
#
RC  
RC  
RW  
RW  
W
W
RW  
#
#
RW  
#
W
RW  
#
MUL_Y  
W
MUL_DH  
MUL_DL  
ACC_DR1  
ACC_DR0  
R
R
#
RW  
RW  
W
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Document Number: 38-12011 Rev. *G  
Page 12 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Table 8. Register Map Bank 0 Table: User Space (continued)  
DCB03DR2  
DCB03CR0  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
RW  
#
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
ACC_DR3  
ACC_DR2  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
RW  
RW  
ACB00CR3  
ACB00CR0  
ACB00CR1  
ACB00CR2  
ACB01CR3  
ACB01CR0  
ACB01CR1  
ACB01CR2  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0RI  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDIOLT1  
RDI0RO0  
RDI0RO1  
CPU_F  
RL  
CPU_SCR1  
CPU_SCR0  
#
#
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Table 9. Register Map Bank 1 Table: Configuration Space  
PRT0DM0  
PRT0DM1  
PRT0IC0  
PRT0IC1  
PRT1DM0  
PRT1DM1  
PRT1IC0  
PRT1IC1  
PRT2DM0  
PRT2DM1  
PRT2IC0  
PRT2IC1  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
ASC10CR0  
ASC10CR1  
ASC10CR2  
ASC10CR3  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
80  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
ASD20CR0  
ASD20CR1  
ASD20CR2  
ASD20CR3  
ASC21CR0  
ASC21CR1  
ASC21CR2  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
GDI_O_IN  
GDI_E_IN  
GDI_O_OU  
GDI_E_OU  
RW  
RW  
RW  
RW  
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Document Number: 38-12011 Rev. *G  
Page 13 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Table 9. Register Map Bank 1 Table: Configuration Space (continued)  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
ASC21CR3  
97  
RW  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
OSC_GO_EN  
OSC_CR4  
OSC_CR3  
OSC_CR0  
OSC_CR1  
OSC_CR2  
VLT_CR  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
R
DBB00FN  
DBB00IN  
DBB00OU  
RW  
RW  
RW  
CLK_CR0  
CLK_CR1  
ABF_CR0  
AMD_CR0  
RW  
RW  
RW  
RW  
DBB01FN  
DBB01IN  
DBB01OU  
RW  
RW  
RW  
VLT_CMP  
AMD_CR1  
ALT_CR0  
RW  
RW  
DCB02FN  
DCB02IN  
DCB02OU  
RW  
RW  
RW  
IMO_TR  
ILO_TR  
BDG_TR  
ECO_TR  
W
W
RW  
W
DCB03FN  
DCB03IN  
DCB03OU  
RW  
RW  
RW  
ACB00CR3  
ACB00CR0  
ACB00CR1  
ACB00CR2  
ACB01CR3  
ACB01CR0  
ACB01CR1  
ACB01CR2  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0RI  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDIOLT1  
RDI0RO0  
RDI0RO1  
CPU_F  
RL  
CPU_SCR1  
CPU_SCR0  
#
#
Blank fields are Reserved and must not be accessed.  
# Access is bit specific.  
Document Number: 38-12011 Rev. *G  
Page 14 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Electrical Specifications  
This section presents the DC and AC electrical specifications of the CY8C24x23 PSoC device. For latest electrical specifications,  
o
o
o
Specifications are valid for -40 C T 85 C and T 100 C, except where noted. Specifications for devices running at greater than  
A
J
o
o
o
12 MHz are valid for -40 C T 70 C and T 82 C.  
A
J
Figure 10. Voltage versus Operating Frequency  
5.25  
4.75  
3.00  
93 kHz  
12 MHz  
24 MHz  
CPU Frequency  
The following table lists the units of measure that are used in this section.  
Table 10. Units of Measure  
Symbol  
°C  
Unit of Measure  
degree Celsius  
Symbol  
μW  
Unit of Measure  
micro watts  
milli-ampere  
milli-second  
milli-volts  
dB  
decibels  
mA  
ms  
mV  
nA  
ns  
fF  
femto farad  
hertz  
Hz  
KB  
Kbit  
kHz  
kΩ  
1024 bytes  
1024 bits  
nano ampere  
nanosecond  
nanovolts  
kilohertz  
nV  
W
kilohm  
ohm  
MHz  
MΩ  
μA  
μF  
μH  
μs  
μV  
μVrms  
megahertz  
megaohm  
pA  
pF  
pp  
ppm  
ps  
pico ampere  
pico farad  
peak-to-peak  
micro ampere  
micro farad  
micro henry  
microsecond  
micro volts  
micro volts root-mean-square  
parts per million  
picosecond  
sps  
s
samples per second  
sigma: one standard deviation  
volts  
V
Document Number: 38-12011 Rev. *G  
Page 15 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Absolute Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.  
Table 11. Absolute Maximum Ratings  
Symbol  
Description  
Storage Temperature  
Min  
Typ  
Max  
Units  
Notes  
o
T
-55  
+100  
C
Higher storage temperatures  
reduce data retention time.  
STG  
o
T
Ambient Temperature with Power Applied  
Supply Voltage on Vdd Relative to Vss  
DC Input Voltage  
-40  
-0.5  
+85  
+6.0  
C
A
Vdd  
V
V
V
Vss - 0.5  
Vss - 0.5  
-25  
Vdd + 0.5  
Vdd + 0.5  
+50  
IO  
DC Voltage Applied to Tri-state  
Maximum Current into any Port Pin  
V
I
I
mA  
mA  
MIO  
Maximum Current into any Port Pin Configured  
as Analog Driver  
-50  
+50  
MAIO  
Static Discharge Voltage  
Latch-up Current  
2000  
V
200  
mA  
Operating Temperature  
Table 12. Operating Temperature  
Symbol  
Description  
Min  
-40  
-40  
Typ  
Max  
+85  
Units  
Notes  
o
T
Ambient Temperature  
Junction Temperature  
C
A
o
T
+100  
C
The temperature rise from ambient  
to junction is package specific. See  
on page 41. The user must limit the  
power consumption to comply with  
this requirement.  
J
Document Number: 38-12011 Rev. *G  
Page 16 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC Electrical Characteristics  
DC Chip-Level Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 13. DC Chip-Level Specifications  
Symbol  
Description  
Supply Voltage  
Min  
3.00  
Typ  
Max  
5.25  
8
Units  
Notes  
Vdd  
V
o
I
Supply Current  
5
mA Conditions are Vdd = 5.0V, 25 C,  
CPU =3MHz, 48 MHz disabled. VC1  
= 1.5 MHz, VC2 = 93.75 kHz,  
VC3 = 93.75 kHz.  
DD  
I
Supply Current  
3.3  
6.0  
mA Conditions are Vdd = 3.3V, T = 25  
DD3  
A
o
C, CPU = 3 MHz, 48 MHz =  
Disabled, VC1 = 1.5 MHz,  
VC2 = 93.75 kHz, VC3 = 93.75 kHz.  
I
I
I
I
Sleep (Mode) Current with POR, LVD,  
Sleep Timer, and WDT.  
3
4
6.5  
25  
μA Conditions are with internal slow  
SB  
a
o
speed oscillator, Vdd = 3.3V, -40 C  
o
<= T <= 55 C.  
A
Sleep (Mode) Current with POR, LVD,  
Sleep Timer, and WDT at high temper-  
μA Conditions are with internal slow  
SBH  
speed oscillator, Vdd = 3.3V,  
a
o
o
ature.  
55 C < T <= 85 C.  
A
Sleep (Mode) Current with POR, LVD,  
Sleep Timer, WDT, and external crystal.  
4
7.5  
μA Conditions are with properly loaded,  
SBXTL  
SBXTLH  
a
1 μW max, 32.768 kHz crystal. Vdd  
o
o
= 3.3V, -40 C <= T <= 55 C.  
A
Sleep (Mode) Current with POR, LVD,  
5
26  
μA Conditions are with properly loaded,  
SleepTimer, WDT, andexternalcrystalat  
1μW max, 32.768 kHz crystal.  
a
o
o
high temperature.  
Vdd = 3.3 V, 55 C < T <= 85 C.  
A
V
Reference Voltage (Bandgap)  
1.275  
1.3  
1.325  
V
Trimmed for appropriate Vdd.  
REF  
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar  
functions enabled.  
Document Number: 38-12011 Rev. *G  
Page 17 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC General Purpose IO Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 14. DC GPIO Specifications  
Symbol  
Description  
Pull up Resistor  
Min  
Typ  
5.6  
5.6  
Max  
Units  
kΩ  
kΩ  
Notes  
R
4
4
8
8
PU  
R
Pull down Resistor  
High Output Level  
PD  
V
Vdd - 1.0  
V
IOH = 10 mA, Vdd = 4.75 to 5.25V  
(80 mA maximum combined IOH  
budget)  
OH  
V
Low Output Level  
0.75  
0.8  
V
IOL = 25 mA, Vdd = 4.75 to 5.25V  
(150 mA maximum combined IOL  
budget)  
OL  
V
V
V
I
Input Low Level  
2.1  
V
V
Vdd = 3.0 to 5.25  
Vdd = 3.0 to 5.25  
IL  
IH  
H
Input High Level  
Input Hysterisis  
60  
1
mV  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
nA Gross tested to 1 μA  
pF  
IL  
C
3.5  
10  
Package and pin dependent.  
IN  
o
Temp = 25 C  
C
Capacitive Load on Pins as Output  
3.5  
10  
pF  
Package and pin dependent.  
Temp = 25 C  
OUT  
o
DC Operational Amplifier Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at  
25°C and are for design guidance only.  
Table 15. 5V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value) Low Power  
Input Offset Voltage (absolute value) Mid Power  
Input Offset Voltage (absolute value) High Power  
Average Input Offset Voltage Drift  
1.6  
10  
mV  
OSOA  
1.3  
8
mV  
mV  
1.2  
7.0  
20  
7.5  
35.0  
o
TCV  
μV/ C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA  
pF  
Gross tested to 1 μA.  
EBOA  
C
4.5  
9.5  
Package and pin  
dependent.  
INOA  
o
Temp = 25 C.  
V
Common Mode Voltage Range  
Common Mode Voltage Range (high power or high  
opamp bias)  
0.0  
0.5  
Vdd  
Vdd - 0.5  
V
Thecommon-modeinput  
voltage range is  
CMOA  
measured through an  
analog output buffer. The  
specificationincludesthe  
limitations imposed by  
the characteristics of the  
analog output buffer.  
Document Number: 38-12011 Rev. *G  
Page 18 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Table 15. 5V DC Operational Amplifier Specifications (continued)  
Symbol Description  
Min  
Typ  
Max  
Units  
Notes  
G
Open Loop Gain  
Power = Low  
Power = Medium  
Power = High  
dB  
Specification is appli-  
cable at high power. For  
all other bias modes  
(except high power, high  
opamp bias), minimum is  
60 dB.  
OLOA  
60  
60  
80  
V
V
High Output Voltage Swing (worst case internal load)  
Power = Low  
Power = Medium  
Power = High  
OHIGHOA  
OLOWOA  
SOA  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.5  
V
V
V
Low Output Voltage Swing (worst case internal load)  
Power = Low  
Power = Medium  
Power = High  
0.2  
0.2  
0.5  
V
V
V
I
Supply Current (including associated AGND buffer)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
Power = High, Opamp Bias = High  
PSRR  
Supply Voltage Rejection Ratio  
60  
dB  
OA  
Document Number: 38-12011 Rev. *G  
Page 19 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Table 16. 3.3V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value) Low Power  
Input Offset Voltage (absolute value) Mid Power  
High Power is 5 Volt Only  
1.65  
1.32  
10  
8
mV  
mV  
OSOA  
o
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/ C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA.  
EBOA  
C
4.5  
9.5  
pF  
Package and pin  
INOA  
o
dependent. Temp = 25 C.  
V
Common Mode Voltage Range  
0.2  
Vdd - 0.2  
V
The common-mode input  
voltage range is  
CMOA  
measured through an  
analog output buffer. The  
specification includes the  
limitationsimposedbythe  
characteristics of the  
analog output buffer.  
G
Open Loop Gain  
Power = Low  
Power = Medium  
Power = High  
dB Specificationisapplicable  
at high power. For all  
OLOA  
60  
60  
80  
other bias modes (except  
high power, high opamp  
bias), minimum is 60 dB.  
V
V
High Output Voltage Swing (worst case internal load)  
Power = Low  
Power = Medium  
OHIGHOA  
OLOWOA  
SOA  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.2  
V
V
V
Power = High is 5V only  
Low Output Voltage Swing (worst case internal load)  
Power = Low  
Power = Medium  
Power = High  
0.2  
0.2  
0.2  
V
V
V
I
Supply Current (including associated AGND buffer)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Power = High, Opamp Bias = High  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
μA  
PSRR  
Supply Voltage Rejection Ratio  
50  
dB  
OA  
Document Number: 38-12011 Rev. *G  
Page 20 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC Analog Output Buffer Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 17. 5V DC Analog Output Buffer Specifications  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Min  
Typ  
3
Max  
12  
Units  
mV  
V
OSOB  
TCV  
+6  
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vdd - 1.0  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
V
High Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd + 1.1  
0.5 x Vdd + 1.1  
V
V
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.3  
0.5 x Vdd - 1.3  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
1.1  
2.6  
5.1  
8.8  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
60  
dB  
OB  
Table 18. 3.3V DC Analog Output Buffer Specifications  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Min  
Typ  
3
Max  
12  
Units  
mV  
V
OSOB  
TCV  
+6  
-
μV/°C  
V
OSOB  
V
0.5  
Vdd - 1.0  
CMOB  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
V
High Output Voltage Swing (Load = 1K ohms to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd + 1.0  
0.5 x Vdd + 1.0  
V
V
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.0  
0.5 x Vdd - 1.0  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
0.8  
2.0  
2.0  
4.3  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
50  
dB  
OB  
Document Number: 38-12011 Rev. *G  
Page 21 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC Switch Mode Pump Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 19. DC Switch Mode Pump (SMP) Specifications  
Symbol  
Description  
5V Output voltage  
Min  
4.75  
3.00  
Typ  
5.0  
Max  
5.25  
3.60  
Units  
Notes  
V
V
5V  
3V  
V
V
Average, neglecting ripple  
Average, neglecting ripple  
PUMP  
PUMP  
PUMP  
3V Output voltage  
3.25  
I
Available Output Current  
For implementation, which  
includes 2 uH inductor, 1 uF cap,  
and Schottky diode  
V
V
= 1.5V, V  
= 1.8V, V  
= 3.25V  
= 5.0V  
8
5
mA  
mA  
BAT  
BAT  
PUMP  
PUMP  
V
V
V
5V  
Input Voltage Range from Battery  
Input Voltage Range from Battery  
1.8  
1.0  
1.1  
5.0  
3.3  
V
V
V
BAT  
3V  
BAT  
Minimum Input Voltage from Battery to  
Start Pump  
BATSTART  
a
ΔV  
ΔV  
ΔV  
Line Regulation (over V  
Load Regulation  
range)  
5
5
%V  
PUMP_Line  
PUMP_Load  
PUMP_Ripple  
BAT  
O
a
%V  
O
Output Voltage Ripple (depends on  
cap/load)  
25  
mVpp Configuration of note 2, load is  
5mA  
Efficiency  
35  
50  
%
Configuration of note 2, load is  
5mA, Vout is 3.25V.  
F
Switching Frequency  
Switching Duty Cycle  
1.3  
50  
MHz  
%
PUMP  
DC  
PUMP  
a. VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 23 on page 25.  
Figure 11. Basic Switch Mode Pump Circuit  
D1  
Vdd  
C1  
SMP  
+
VBAT  
TM  
Battery  
PSoC  
Vss  
Document Number: 38-12011 Rev. *G  
Page 22 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC Analog Reference Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling  
of the digital signal may appear on the AGND.  
Table 20. 5V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2a  
Min  
Typ  
Max  
Units  
BG  
1.274  
1.30  
1.326  
V
CT Block Power = High  
AGND = 2 x BandGapa  
CT Block Power = High  
AGND = P2[4] (P2[4] = Vdd/2)a  
CT Block Power = High  
AGND = BandGapa  
CT Block Power = High  
AGND = 1.6 x BandGapa  
CT Block Power = High  
Vdd/2 - 0.043  
2 x BG - 0.048  
P2[4] - 0.013  
BG - 0.009  
Vdd/2 - 0.025  
2 x BG - 0.030  
P2[4]  
Vdd/2 + 0.003  
2 x BG + 0.024  
P2[4] + 0.014  
BG + 0.016  
V
V
V
V
V
V
BG + 0.008  
1.6 x BG - 0.022  
-0.034  
1.6 x BG - 0.010 1.6 x BG + 0.018  
AGND Column to Column Variation (AGND =  
Vdd/2)a  
0.000  
0.034  
CT Block Power = High  
RefHi = Vdd/2 + BandGap  
Ref Control Power = High  
Vdd/2 + BG - 0.140 Vdd/2 + BG - 0.018  
Vdd/2 + BG +  
0.103  
V
RefHi = 3 x BandGap  
Ref Control Power = High  
3 x BG - 0.112  
3 x BG - 0.018  
3 x BG + 0.076  
V
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)  
Ref Control Power = High  
2 x BG + P2[6] -  
0.113  
2 x BG + P2[6] -  
0.018  
2 x BG + P2[6] +  
0.077  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
Ref Control Power = High  
P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098  
V
V
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)  
Ref Control Power = High  
P2[4] + P2[6] - 0.133  
3.2 x BG - 0.112  
P2[4] + P2[6] -  
0.016  
P2[4] + P2[6]+  
0.100  
RefHi = 3.2 x BandGap  
Ref Control Power = High  
3.2 x BG  
3.2 x BG + 0.076  
V
V
V
V
RefLo = Vdd/2 – BandGap  
Ref Control Power = High  
Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.098  
RefLo = BandGap  
Ref Control Power = High  
BG - 0.082  
BG + 0.023  
BG + 0.129  
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)  
Ref Control Power = High  
2 x BG - P2[6] -  
0.084  
2 x BG - P2[6] +  
0.025  
2 x BG - P2[6] +  
0.134  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
Ref Control Power = High  
P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107  
V
V
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)  
Ref Control Power = High  
P2[4] - P2[6] - 0.057  
P2[4] - P2[6] +  
0.026  
P2[4] - P2[6] +  
0.110  
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%.  
Document Number: 38-12011 Rev. *G  
Page 23 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
Table 21. 3.3V DC Analog Reference Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
BG  
Bandgap Voltage Reference  
1.274  
1.30  
1.326  
V
AGND = Vdd/2a  
CT Block Power = High  
Vdd/2 - 0.037  
Vdd/2 - 0.020  
Vdd/2 + 0.002  
V
AGND = 2 x BandGapa  
CT Block Power = High  
Not Allowed  
AGND = P2[4] (P2[4] = Vdd/2)  
CT Block Power = High  
AGND = BandGapa  
CT Block Power = High  
AGND = 1.6 x BandGapa  
CT Block Power = High  
P2[4] - 0.008  
BG - 0.009  
P2[4] + 0.001  
BG + 0.005  
P2[4] + 0.009  
BG + 0.015  
V
V
1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018  
V
AGND Column to Column Variation (AGND = Vdd/2)a  
CT Block Power = High  
-0.034  
0.000  
0.034  
mV  
RefHi = Vdd/2 + BandGap  
Ref Control Power = High  
Not Allowed  
RefHi = 3 x BandGap  
Ref Control Power = High  
Not Allowed  
Not Allowed  
Not Allowed  
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)  
Ref Control Power = High  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
Ref Control Power = High  
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)  
Ref Control Power = High  
P2[4] + P2[6] -  
0.075  
P2[4] + P2[6] -  
0.009  
P2[4] + P2[6] +  
0.057  
V
RefHi = 3.2 x BandGap  
Ref Control Power = High  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefLo = Vdd/2 - BandGap  
Ref Control Power = High  
RefLo = BandGap  
Ref Control Power = High  
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)  
Ref Control Power = High  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
Ref Control Power = High  
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)  
Ref Control Power = High  
P2[4] - P2[6] -  
0.048  
P2[4]- P2[6] +  
0.022  
P2[4] - P2[6] +  
0.092  
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%  
Document Number: 38-12011 Rev. *G  
Page 24 of 43  
CY8C24123  
CY8C24223, CY8C24423  
DC Analog PSoC Block Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 22. DC Analog PSoC Block Specifications  
Symbol  
RCT  
Description  
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switch Cap)  
Min  
Typ  
12.24  
80  
Max  
Units  
kΩ  
fF  
CSC  
DC POR and LVD Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable  
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.  
Table 23. DC POR and LVD Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Vdd Value for PPOR Trip (positive ramp)  
VPPOR0R PORLEV[1:0] = 00b  
VPPOR1R PORLEV[1:0] = 01b  
VPPOR2R PORLEV[1:0] = 10b  
2.908  
4.394  
4.548  
V
V
V
Vdd Value for PPOR Trip (negative ramp)  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
VPPOR0  
VPPOR1  
VPPOR2  
2.816  
4.394  
4.548  
V
V
V
PPOR Hysteresis  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
VPH0  
VPH1  
VPH2  
92  
0
0
mV  
mV  
mV  
Vdd Value for LVD Trip  
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
VLVD0  
VLVD1  
VLVD2  
VLVD3  
VLVD4  
VLVD5  
VLVD6  
VLVD7  
2.863  
2.963  
3.070  
3.920  
4.393  
4.550  
4.632  
4.718  
2.921  
3.023  
3.133  
4.00  
4.483  
4.643  
4.727  
4.814  
2.979a  
3.083  
3.196  
4.080  
4.573  
4.736b  
4.822  
4.910  
V
V
V
V
V
V
V
V
V
Vdd Value for PUMP Trip  
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
VPUMP0  
VPUMP1  
VPUMP2  
VPUMP3  
VPUMP4  
VPUMP5  
VPUMP6  
VPUMP7  
2.963  
3.033  
3.185  
4.110  
4.550  
4.632  
4.719  
4.900  
3.023  
3.095  
3.250  
4.194  
4.643  
4.727  
4.815  
5.000  
3.083  
3.157  
3.315  
4.278  
4.736  
4.822  
4.911  
5.100  
V
V
V
V
V
V
V
V
V
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.  
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.  
Document Number: 38-12011 Rev. *G  
Page 25 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
DC Programming Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 24. DC Programming Specifications  
Symbol  
IDDP  
Description  
Min  
Typ  
5
Max  
25  
Units  
mA  
V
Notes  
Supply Current During Programming or Verify  
VILP  
VIHP  
IILP  
Input Low Voltage During Programming or  
Verify  
0.8  
Input High Voltage During Programming or  
Verify  
2.2  
0.2  
V
Input Current when Applying Vilp to P1[0] or  
P1[1] During Programming or Verify  
mA Driving internal pull down  
resistor.  
IIHP  
Input Current when Applying Vihp to P1[0] or  
P1[1] During Programming or Verify  
1.5  
mA Driving internal pull down  
resistor.  
VOLV  
VOHV  
Output Low Voltage During Programming or  
Verify  
Vss + 0.75  
Vdd  
V
Output High Voltage During Programming or  
Verify  
Vdd - 1.0  
V
FlashENPB Flash Endurance (per block)  
FlashENT Flash Endurance (total)a  
50,000  
1,800,000  
10  
Erase/write cycles per block.  
Erase/write cycles.  
FlashDR  
Flash Data Retention  
Years  
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2  
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no  
single block ever sees more than 50,000 cycles).  
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.  
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.  
Document Number: 38-12011 Rev. *G  
Page 26 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC Electrical Characteristics  
AC Chip-Level Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 25. AC Chip-Level Specifications  
Symbol  
FIMO  
Description  
Min  
Typ  
Max  
24.6a  
Units  
Notes  
Internal Main Oscillator Frequency  
23.4  
24  
MHz Trimmed. Using factory trim  
values.  
a,b  
FCPU1  
FCPU2  
F48M  
CPU Frequency (5V Nominal)  
CPU Frequency (3.3V Nominal)  
Digital PSoC Block Frequency  
0.93  
0.93  
0
24  
12  
48  
24.6  
MHz  
MHz  
b,c  
12.3  
a,b,d  
49.2  
MHz Refer to the AC Digital Block  
Specifications.  
b,e,d  
F24M  
F32K1  
F32K2  
Digital PSoC Block Frequency  
Internal Low Speed Oscillator Frequency  
External Crystal Oscillator  
0
15  
24  
32  
24.6  
MHz  
kHz  
64  
32.768  
kHz Accuracy is capacitor and  
crystaldependent.50%duty  
cycle.  
FPLL  
PLL Frequency  
23.986  
MHz Is amultiple(x732)of crystal  
frequency.  
Jitter24M2  
TPLLSLEW  
24 MHz Period Jitter (PLL)  
PLL Lock Time  
0.5  
0.5  
600  
10  
ps  
ms  
ms  
ms  
ms  
ns  
TPLLSLEWSLOW PLL Lock Time for Low Gain Setting  
50  
TOS  
External Crystal Oscillator Startup to 1%  
External Crystal Oscillator Startup to 100 ppm  
32 kHz Period Jitter  
1700  
2800  
100  
2620  
3800f  
TOSACC  
Jitter32k  
TXRST  
External Reset Pulse Width  
24 MHz Duty Cycle  
10  
40  
60  
μs  
%
DC24M  
Step24M  
Fout48M  
50  
24 MHz Trim Step Size  
50  
kHz  
48 MHz Output Frequency  
46.8  
48.0  
49.2a,c  
MHz Trimmed. Using factory trim  
values.  
Jitter24M1  
FMAX  
24 MHz Period Jitter (IMO)  
600  
ps  
Maximum frequency of signal on row input or  
row output.  
12.3  
MHz  
TRAMP  
Supply Ramp Time  
0
μs  
a. 4.75V < Vdd < 5.25V.  
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for opera-  
tion at 3.3V.  
d. See the individual user module data sheets for information on maximum frequencies for user modules.  
e. 3.0V < 5.25V.  
f. The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum  
drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC.  
Document Number: 38-12011 Rev. *G  
Page 27 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 12. PLL Lock Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEW  
FPLL  
PLL  
Gain  
0
Figure 13. PLL Lock for Low Gain Setting Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEWLOW  
FPLL  
PLL  
Gain  
1
Figure 14. External Crystal Oscillator Startup Timing Diagram  
32K  
Select  
32 kHz  
T
OS  
F32K2  
Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram  
Jitter24M1  
F24M  
Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram  
Jitter32k  
F32K2  
Document Number: 38-12011 Rev. *G  
Page 28 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC General Purpose IO Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 26. AC GPIO Specifications  
Symbol  
FGPIO  
Description  
GPIO Operating Frequency  
Min  
0
Typ  
Max  
12  
18  
18  
Units  
MHz  
ns  
Notes  
TRiseF  
TFallF  
Rise Time, Normal Strong Mode, Cload = 50 pF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
Rise Time, Slow Strong Mode, Cload = 50 pF  
Fall Time, Slow Strong Mode, Cload = 50 pF  
3
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
2
ns  
TRiseS  
TFallS  
10  
10  
27  
22  
ns  
ns  
Figure 17. GPIO Timing Diagram  
90%  
GPIO  
Pin  
10%  
TRiseF  
TRiseS  
TFallF  
TFallS  
Document Number: 38-12011 Rev. *G  
Page 29 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC Operational Amplifier Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Table 27. 5V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
TROA  
Rising Settling Time from 80% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Specification maximums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
3.9  
μs  
μs  
μs  
μs  
μs  
μs  
0.72  
0.62  
Power = High, Opamp Bias = High  
TSOA  
Falling Settling Time from 20% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Specification maximums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
5.9  
μs  
μs  
μs  
μs  
μs  
μs  
0.92  
0.72  
Power = High, Opamp Bias = High  
SRROA  
SRFOA  
BWOA  
ENOA  
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Power = High, Opamp Bias = High  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.15  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
1.7  
6.5  
Falling Slew Rate(20% to 80%) (10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Power = High, Opamp Bias = High  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.01  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
0.5  
4.0  
Gain Bandwidth Product  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Power = High, Opamp Bias = High  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.75  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
3.1  
5.4  
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
200  
nV/rt-Hz  
Document Number: 38-12011 Rev. *G  
Page 30 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Table 28. 3.3V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
TROA  
Rising Settling Time from 80% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not  
supported)  
Specification maximums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
3.92  
μs  
μs  
μs  
μs  
μs  
0.72  
Power = High, Opamp Bias = High (3.3 Volt High  
Power, High Opamp Bias not supported)  
μs  
TSOA  
Falling Settling Time from 20% of ΔV to 0.1% of ΔV  
(10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not  
supported)  
Specification maximums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
5.41  
μs  
μs  
μs  
μs  
μs  
0.72  
Power = High, Opamp Bias = High (3.3 Volt High  
Power, High Opamp Bias not supported)  
μs  
SRROA  
SRFOA  
BWOA  
ENOA  
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not  
supported)  
Power = High, Opamp Bias = High (3.3 Volt High  
Power, High Opamp Bias not supported)  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.31  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
2.7  
V/μs  
Falling Slew Rate(20% to 80%) (10 pF load, Unity Gain)  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not  
supported)  
Power = High, Opamp Bias = High (3.3 Volt High  
Power, High Opamp Bias not supported)  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.24  
V/μs  
V/μs  
V/μs  
V/μs  
V/μs  
1.8  
V/μs  
Gain Bandwidth Product  
Power = Low  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not  
supported)  
Specification minimums for  
low power and high opamp  
bias, medium power, and  
medium power and high  
opamp bias levels are  
between low and high power  
levels.  
0.67  
MHz  
MHz  
MHz  
MHz  
MHz  
2.8  
Power=High, OpampBias=High(3.3VoltHighPower,  
High Opamp Bias not supported)  
MHz  
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
200  
nV/rt-Hz  
Document Number: 38-12011 Rev. *G  
Page 31 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC Digital Block Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 29. AC Digital Block Specifications  
Function  
Timer  
Description  
Capture Pulse Width  
Min  
50a  
Typ  
Max  
Units  
Notes  
ns  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
50a  
MHz  
Counter  
ns  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
Kill Pulse Width:  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
MHz  
Dead Band  
Asynchronous Restart Mode  
Synchronous Restart Mode  
Disable Mode  
20  
50a  
50a  
ns  
ns  
ns  
Maximum Frequency  
49.2  
49.2  
MHz 4.75V < Vdd < 5.25V  
MHz 4.75V < Vdd < 5.25V  
CRCPRS  
(PRS Mode)  
Maximum Input Clock Frequency  
CRCPRS  
Maximum Input Clock Frequency  
24.6  
MHz  
(CRC Mode)  
SPIM  
SPIS  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
Width of SS_ Negated Between Transmissions  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
50a  
8.2  
4.1  
MHz  
ns  
ns  
Transmitter  
Receiver  
16.4  
49.2  
MHz  
16  
MHz 4.75V < Vdd < 5.25V  
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
Document Number: 38-12011 Rev. *G  
Page 32 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC Analog Output Buffer Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 30. 5V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
TROB  
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
2.5  
2.5  
μs  
μs  
TSOB  
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
2.2  
2.2  
μs  
μs  
SRROB  
SRFOB  
BWOB  
BWOB  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.65  
0.65  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.65  
0.65  
V/μs  
V/μs  
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load  
Power = Low  
Power = High  
0.8  
0.8  
MHz  
MHz  
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load  
Power = Low  
Power = High  
300  
300  
kHz  
kHz  
Table 31. 3.3V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
TROB  
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
3.8  
3.8  
μs  
μs  
TSOB  
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
2.6  
2.6  
μs  
μs  
SRROB  
SRFOB  
BWOB  
BWOB  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.5  
0.5  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.5  
0.5  
V/μs  
V/μs  
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load  
Power = Low  
Power = High  
0.7  
0.7  
MHz  
MHz  
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load  
Power = Low  
Power = High  
200  
200  
kHz  
kHz  
Document Number: 38-12011 Rev. *G  
Page 33 of 43  
CY8C24123  
CY8C24223, CY8C24423  
AC External Clock Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 32. 5V AC External Clock Specifications  
Symbol  
Description  
Min  
0
Typ  
Max  
Units  
MHz  
ns  
FOSCEXT Frequency  
24.24  
High Period  
20.6  
20.6  
150  
Low Period  
ns  
Power Up IMO to Switch  
μs  
Table 33. 3.3V AC External Clock Specifications  
Symbol Description  
FOSCEXT Frequency with CPU Clock divide by 1a  
Min  
0
Typ  
Max  
12.12  
24.24  
Units  
MHz  
MHz  
ns  
FOSCEXT Frequency with CPU Clock divide by 2 or greaterb  
0
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
41.7  
41.7  
150  
ns  
μs  
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle  
requirements.  
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures  
that the fifty percent duty cycle requirement is met.  
AC Programming Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 34. AC Programming Specifications  
Symbol  
TRSCLK  
TFSCLK  
TSSCLK  
THSCLK  
FSCLK  
Description  
Min  
1
Typ  
Max  
20  
20  
Units  
ns  
Rise Time of SCLK  
Fall Time of SCLK  
1
ns  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
ns  
TERASEB Flash Erase Time (Block)  
15  
30  
TWRITE  
TDSCLK  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
45  
Document Number: 38-12011 Rev. *G  
Page 34 of 43  
CY8C24123  
CY8C24223, CY8C24423  
2
AC I C Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
are for design guidance only or unless otherwise specified.  
Table 35. AC Characteristics of the I2C SDA and SCL Pins  
Standard Mode  
Fast Mode  
Min Max  
Symbol  
Description  
Units  
Min  
0
Max  
100  
FSCLI2C  
SCL Clock Frequency  
0
400  
kHz  
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first  
clock pulse is generated.  
4.0  
0.6  
μs  
TLOWI2C  
THIGHI2C  
LOW Period of the SCL Clock  
HIGH Period of the SCL Clock  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
100a  
0.6  
1.3  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
TSUSTAI2C Setup Time for a Repeated START Condition  
THDDATI2C Data Hold Time  
TSUDATI2C Data Setup Time  
250  
4.0  
4.7  
TSUSTOI2C Setup Time for STOP Condition  
TBUFI2C  
TSPI2C  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
50  
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the  
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data  
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.  
Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus  
SDA  
TSPI2C  
TLOWI2C  
TSUDATI2C  
THDSTAI2C  
TBUFI2C  
SCL  
TSUSTOI2C  
TSUSTAI2C  
THDDATI2C  
THDSTAI2C  
THIGHI2C  
S
Sr  
P
S
Document Number: 38-12011 Rev. *G  
Page 35 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Packaging Information  
This section presents the packaging specifications for the CY8C24x23 PSoC device, along with the thermal impedances for each  
package and the typical package capacitance on crystal pins.  
Figure 19. 8-Pin (300-Mil) PDIP  
51-85075 *A  
Document Number: 38-12011 Rev. *G  
Page 36 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 20. 8-Pin (150-Mil) SOIC  
51-85066 *C  
Figure 21. 20-Pin (300-Mil) Molded DIP  
51-85011 *A  
Document Number: 38-12011 Rev. *G  
Page 37 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 22. 20-Pin (210-Mil) SSOP  
51-85077 *C  
Figure 23. 20-Pin (300-Mil) Molded SOIC  
51-85024 *C  
Document Number: 38-12011 Rev. *G  
Page 38 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 24. 28-Pin (300-Mil) Molded DIP  
51-85014 *D  
Document Number: 38-12011 Rev. *G  
Page 39 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 25. 28-Pin (210-Mil) SSOP  
51-85079 *C  
Figure 26. 28-Pin (300-Mil) Molded SOIC  
51-85026 *D  
Document Number: 38-12011 Rev. *G  
Page 40 of 43  
CY8C24123  
CY8C24223, CY8C24423  
Figure 27. 32-Pin (5x5 mm) MLF  
51-85188 *B  
Thermal Impedances  
Capacitance on Crystal Pins  
Table 37. Typical Package Capacitance on Crystal Pins  
Table 36. Thermal Impedances per Package  
Package  
8 PDIP  
Typical θ  
123 oC/W  
*
Package  
8 PDIP  
Package Capacitance  
2.8 pF  
JA  
8 SOIC  
185 oC/W  
109 oC/W  
117 oC/W  
81 oC/W  
69 oC/W  
101 oC/W  
74 oC/W  
22 oC/W  
8 SOIC  
2.0 pF  
20 PDIP  
20 PDIP  
20 SSOP  
20 SOIC  
28 PDIP  
28 SSOP  
28 SOIC  
32 MLF  
3.0 pF  
20 SSOP  
2.6 pF  
20 SOIC  
2.5 pF  
28 PDIP  
3.5 pF  
28 SSOP  
2.8 pF  
28 SOIC  
2.7 pF  
32 MLF  
2.0 pF  
* TJ = TA + POWER x θJA  
Document Number: 38-12011 Rev. *G  
Page 41 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
Ordering Information  
The following table lists the CY8C24x23 PSoC Device family’s key package features and ordering codes.  
Table 38. CY8C24x23 PSoC Device Family Key Features and Ordering Information  
8 Pin (300 Mil) DIP  
8 Pin (150 Mil) SOIC  
CY8C24123-24PI  
CY8C24123-24SI  
4
4
256  
256  
No  
-40°C to +85°C  
4
4
6
6
6
6
4
4
2
2
No  
No  
Yes -40°C to +85°C  
8 Pin (150 Mil) SOIC  
(Tape and Reel)  
CY8C24123-24SIT  
4
256  
Yes -40°C to +85°C  
4
6
6
4
2
No  
20 Pin (300 Mil) DIP  
CY8C24223-24PI  
CY8C24223-24PVI  
4
4
256  
256  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
4
4
6
6
16  
16  
8
8
2
2
Yes  
Yes  
20 Pin (210 Mil) SSOP  
20 Pin (210 Mil) SSOP  
(Tape and Reel)  
CY8C24223-24PVIT  
CY8C24223-24SI  
CY8C24223-24SIT  
4
4
4
256  
256  
256  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
4
4
4
6
6
6
16  
16  
16  
8
8
8
2
2
2
Yes  
Yes  
Yes  
20 Pin (300 Mil) SOIC  
20 Pin (300 Mil) SOIC  
(Tape and Reel)  
28 Pin (300 Mil) DIP  
CY8C24423-24PI  
CY8C24423-24PVI  
4
4
256  
256  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
4
4
6
6
24  
24  
10  
10  
2
2
Yes  
Yes  
28 Pin (210 Mil) SSOP  
28 Pin (210 Mil) SSOP  
(Tape and Reel)  
CY8C24423-24PVIT  
CY8C24423-24SI  
CY8C24423-24SIT  
CY8C24423-24LFI  
4
4
4
4
256  
256  
256  
256  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
Yes -40°C to +85°C  
4
4
4
4
6
6
6
6
24  
24  
24  
24  
10  
10  
10  
10  
2
2
2
2
Yes  
Yes  
Yes  
Yes  
28 Pin (300 Mil) SOIC  
28 Pin (300 Mil) SOIC  
(Tape and Reel)  
32 Pin (5x5 mm) MLF  
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).  
Ordering Code Definitions  
CY 8 C 24 xxx-SPxx  
Package Type:  
P = PDIP  
S = SOIC  
Thermal Rating:  
C = Commercial  
I = Industrial  
PV = SSOP  
LF = MLF  
E = Extended  
A = TQFP  
Speed: 24 MHz  
Part Number  
Family Code  
Technology Code: C = CMOS  
Marketing Code: 8 = Cypress MicroSystems  
Company ID: CY = Cypress  
Document Number: 38-12011 Rev. *G  
Page 42 of 43  
 
CY8C24123  
CY8C24223, CY8C24423  
Document History Page  
Document Title: CY8C24123, CY8C24223, CY8C24423 PSoC® Programmable System-on-Chip™  
Document Number: 38-12011  
Orig. of  
Change  
Submission  
Date  
Revision  
**  
ECN  
Description of Change  
127043  
New Silicon  
and NWJ  
05/15/2003 New document – Advanced Data Sheet (two page product brief).  
*A  
*B  
128779  
129775  
NWJ  
08/13/2003 New document – Preliminary Data Sheet (300 page product detail).  
MWR/NWJ  
09/26/2003 Changes to Electrical Specifications section, Register Details chapter, and  
chapter changes in the Analog System section.  
*C  
*D  
130128  
131678  
NWJ  
NWJ  
10/14/2003 Revised document for Silicon Revision A.  
12/04/2003 Changes to Electrical Specifications section, Miscellaneous changes to I2C,  
GDI, RDI, Registers, and Digital Block chapters.  
*E  
*F  
131802  
229418  
NWJ  
SFV  
12/22/2003 Changes to Electrical Specifications and miscellaneous small changes  
throughout the data sheet.  
06/04/2004 New data sheet format and organization. Reference the PSoC Programmable  
System-on-Chip Technical Reference Manual for additional information. Title  
change.  
*G  
2619935 ONGE/AESA 12/11/2008 Changed title to “CY8C24123, CY8C24223, CY8C24423 PSoC®  
Programmable System-on-Chip™”  
Updated package diagrams 51-85188, 51-85024, 51-85014, and 51-85026.  
Added note on digital signaling in Table on page 23.  
Added Die Sales information note to Ordering Information on page 42.  
Updated data sheet template.  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 38-12011 Rev. *G  
Revised December 11, 2008  
Page 43 of 43  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names  
mentioned in this document may be the trademarks of their respective holders.  

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