Cypress CY8C22113 User Manual

PSoC™ Mixed Signal Array  
Final Data Sheet  
CY8C22113 and CY8C22213  
Features  
Powerful Harvard Architecture Processor  
Precision, Programmable Clocking  
Additional System Resources  
I2CSlave, Master, and Multi-Master to  
400 kHz  
M8C Processor Speeds to 24 MHz  
Low Power at High Speed  
3.0 to 5.25 V Operating Voltage  
Industrial Temperature Range: -40°C to +85°C  
Internal ±2.5% 24/48 MHz Oscillator  
High-Accuracy 24 MHz with Optional 32.768  
kHz Crystal and PLL  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
Advanced Peripherals (PSoC Blocks)  
On-Chip Precision Voltage Reference  
Flexible On-Chip Memory  
3 Rail-to-Rail Analog PSoC Blocks Provide:  
- Up to 14-Bit ADCs  
2K Bytes Flash Program Storage 50,000  
Erase/Write Cycles  
Complete Development Tools  
Free Development Software  
(PSoC™ Designer)  
- Up to 9-Bit DACs  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Flexible Protection Modes  
EEPROM Emulation in Flash  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
4 Digital PSoC Blocks Provide:  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
Full-Featured, In-Circuit Emulator and  
Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
Programmable Pin Configurations  
- Full-Duplex UART  
- SPIMasters or Slaves  
- Connectable to all GPIO Pins  
25 mA Sink on all GPIO  
Pull up, Pull down, High Z, Strong, or Open  
Drain Drive Modes on all GPIO  
Up to 8 Analog Inputs on GPIO  
One 30 mA Analog Outputs on GPIO  
Configurable Interrupt on all GPIO  
Complex Peripherals by Combining Blocks  
Analog  
Port 0  
Drivers  
PSoC™ Functional Overview  
Port 1  
PSoC CORE  
The PSoC™ family consists of many Mixed Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable device. PSoC  
devices include configurable blocks of analog and digital logic,  
as well as programmable interconnects. This architecture  
allows the user to create customized peripheral configurations  
that match the requirements of each individual application.  
Additionally, a fast CPU, Flash program memory, SRAM data  
memory, and configurable IO are included in a range of conve-  
nient pinouts and packages.  
SYSTEM BUS  
Global Digital Interconnect  
Global Analog Interconnect  
SRAM  
256 Bytes  
SROM  
Flash 2K  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources. Configurable global busing allows all  
the device resources to be combined into a complete custom  
system. The PSoC CY8C22x13 family can have up to two IO  
ports that connect to the global digital and analog interconnects,  
providing access to 4 digital blocks and 3 analog blocks.  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Analog  
Block  
Array  
Digital  
Block Array  
(1 Row,  
4 Blocks)  
Analog  
Input  
Muxing  
(1 Column,  
3 Blocks)  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich fea-  
ture set. The core includes a CPU, memory, clocks, and config-  
urable GPIO (General Purpose IO).  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Decimator  
I2C  
The M8C CPU core is a powerful processor with speeds up to  
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-  
SYSTEM RESOURCES  
June 2004  
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12009 Rev. *E  
1
CY8C22x13 Final Data Sheet  
PSoC™ Overview  
Analog blocks are provided in columns of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks. The number of blocks is dependant on the device family  
which is detailed in the table titled “PSoC Device Characteris-  
tics” on page 3.  
Additional System Resources  
System Resources, some of which have been previously listed,  
provide additional capability useful to complete systems. Addi-  
tional resources include a decimator, low voltage detection, and  
power on reset. Brief statements describing the merits of each  
system resource are presented below.  
P0[7]  
P0[5]  
P0[6]  
P0[4]  
Digital clock dividers provide three customizable clock fre-  
quencies for use in applications. The clocks can be routed to  
both the digital and analog systems. Additional clocks can be  
generated using digital PSoC blocks as clock dividers.  
P0[3]  
P0[1]  
P0[2]  
P0[0]  
The decimator provides a custom hardware filter for digital  
signal processing applications including the creation of Delta  
Sigma ADCs.  
The I2C module provides 100 and 400 kHz communication  
over two wires. Slave, master, and multi-master modes are  
all supported.  
Low Voltage Detection (LVD) interrupts can signal the appli-  
cation of falling voltage levels, while the advanced POR  
(Power On Reset) circuit eliminates the need for a system  
supervisor.  
An internal 1.3 voltage reference provides an absolute refer-  
ence for the analog system, including ADCs and DACs.  
Array Input Configuration  
PSoC Device Characteristics  
Depending on your PSoC device characteristics, the digital and  
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or  
3 analog blocks. The following table lists the resources  
available for specific PSoC device groups.  
ACI0[1:0]  
ACI1[1:0]  
Block Array  
PSoC Device Characteristics  
ACB01  
ASD11  
ASC21  
PSoC Part  
Number  
up to  
64  
CY8C29x66  
CY8C27x66  
CY8C27x43  
CY8C24x23  
CY8C22x13  
4
2
2
1
1
16  
8
12  
12  
12  
12  
8
4
4
4
2
1
4
4
4
2
1
12  
12  
12  
6
up to  
44  
up to  
44  
Analog Reference  
8
up to  
24  
Interface to  
Digital System  
Reference  
Generators  
RefHi  
RefLo  
AGND  
AGNDIn  
RefIn  
Bandgap  
4
up to  
16  
4
3
M8C Interface (Address Bus, Data Bus, Etc.)  
Analog System Block Diagram  
June 3, 2004  
Document No. 38-12009 Rev. *E  
3
CY8C22x13 Final Data Sheet  
PSoC™ Overview  
Getting Started  
Development Tools  
The Cypress MicroSystems PSoC Designer is a Microsoft®  
Windows-based, integrated development environment for the  
Programmable System-on-Chip (PSoC) devices. The PSoC  
Designer IDE and application runs on Windows 98, Windows  
NT 4.0, Windows 2000, Windows Millennium (Me), or Windows  
XP. (Reference the PSoC Designer Functional Flow diagram  
below.)  
The quickest path to understanding the PSoC silicon is by read-  
ing this data sheet and using the PSoC Designer Integrated  
Development Environment (IDE). This data sheet is an over-  
view of the PSoC integrated circuit and presents specific pin,  
register, and electrical specifications. For in-depth information,  
along with detailed programming information, reference the  
PSoC™ Mixed Signal Array Technical Reference Manual.  
For up-to-date Ordering, Packaging, and Electrical Specification  
information, reference the latest PSoC device data sheets on  
PSoC Designer helps the customer to select an operating con-  
figuration for the PSoC, write application code that uses the  
PSoC, and debug the application. This system provides design  
database management by project, an integrated debugger with  
In-Circuit Emulator, in-system programming support, and the  
CYASM macro assembler for the CPUs.  
Development Kits  
Development Kits are available from the following distributors:  
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store  
ment kits, C compilers, and all accessories for PSoC develop-  
ment. Click on PSoC (Programmable System-on-Chip) to view  
a current list of available items.  
PSoC Designer also supports a high-level C language compiler  
developed specifically for the devices in the family.  
Context  
Sensitive  
Help  
Graphical Designer  
PSoCTM  
Designer  
Interface  
Tele-Training  
Free PSoC "Tele-training" is available for beginners and taught  
by a live marketing or application engineer over the phone. Five  
training classes are available to accelerate the learning curve  
including introduction, designing, debugging, advanced design,  
advanced analog, as well as application-specific classes cover-  
ing topics like PSoC and the LIN bus. For days and times of the  
Importable  
Design  
Database  
PSoC  
Configuration  
Sheet  
Device  
Database  
Consultants  
PSoCTM  
Designer  
Core  
Certified PSoC Consultants offer everything from technical  
assistance to completed PSoC designs. To contact or become a  
PSoC Consultant, go to the following Cypress support web site:  
Application  
Database  
Manufacturing  
Information  
File  
Engine  
Project  
Database  
Technical Support  
User  
Modules  
Library  
PSoC application engineers take pride in fast and accurate  
response. They can be reached with a 4-hour guaranteed  
Application Notes  
A long list of application notes will assist you in every aspect of  
your design effort. To locate the PSoC application notes, go to  
Emulation  
Pod  
In-Circuit  
Emulator  
Device  
Programmer  
PSoC Designer Subsystems  
June 3, 2004  
Document No. 38-12009 Rev. *E  
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CY8C22x13 Final Data Sheet  
PSoC™ Overview  
Debugger  
PSoC Designer Software Subsystems  
The PSoC Designer Debugger subsystem provides hardware  
in-circuit emulation, allowing the designer to test the program in  
a physical system while providing an internal view of the PSoC  
device. Debugger commands allow the designer to read and  
program and read and write data memory, read and write IO  
registers, read and write CPU registers, set and clear break-  
points, and provide program run, halt, and step control. The  
debugger also allows the designer to create a trace buffer of  
registers and memory locations of interest.  
Device Editor  
The Device Editor subsystem allows the user to select different  
onboard analog and digital components called user modules  
using the PSoC blocks. Examples of user modules are ADCs,  
DACs, Amplifiers, and Filters.  
The device editor also supports easy development of multiple  
configurations and dynamic reconfiguration. Dynamic configu-  
ration allows for changing configurations at run time.  
Online Help System  
PSoC Designer sets up power-on initialization tables for  
selected PSoC block configurations and creates source code  
for an application framework. The framework contains software  
to operate the selected components and, if the project uses  
more than one operating configuration, contains routines to  
switch between different sets of PSoC block configurations at  
run time. PSoC Designer can print out a configuration sheet for  
a given project configuration for use during application pro-  
gramming in conjunction with the Device Data Sheet. Once the  
framework is generated, the user can add application-specific  
code to flesh out the framework. It’s also possible to change the  
selected components and regenerate the framework.  
The online help system displays online, context-sensitive help  
for the user. Designed for procedural and quick reference, each  
functional subsystem has its own context-sensitive help. This  
system also provides tutorials and links to FAQs and an Online  
Support Forum to aid the designer in getting started.  
Hardware Tools  
In-Circuit Emulator  
A low cost, high functionality ICE (In-Circuit Emulator) is avail-  
able for development support. This hardware has the capability  
to program single devices.  
Design Browser  
The Design Browser allows users to select and import precon-  
figured designs into the user’s project. Users can easily browse  
a catalog of preconfigured designs to facilitate time-to-design.  
Examples provided in the tools include a 300-baud modem, LIN  
Bus master and slave, fan controller, and magnetic card reader.  
The emulator consists of a base unit that connects to the PC by  
way of the parallel or USB port. The base unit is universal and  
will operate with all PSoC devices. Emulation pods for each  
device family are available separately. The emulation pod takes  
the place of the PSoC device in the target board and performs  
full speed (24 MHz) operation.  
Application Editor  
In the Application Editor you can edit your C language and  
Assembly language source code. You can also assemble, com-  
pile, link, and build.  
Assembler. The macro assembler allows the assembly code  
to be merged seamlessly with C code. The link libraries auto-  
matically use absolute addressing or can be compiled in relative  
mode, and linked with other software modules to get absolute  
addressing.  
C Language Compiler. A C language compiler is available  
that supports Cypress MicroSystems’ PSoC family devices.  
Even if you have never worked in the C language before, the  
product quickly allows you to create complete C programs for  
the PSoC family devices.  
The embedded, optimizing C compiler provides all the features  
of C tailored to the PSoC architecture. It comes complete with  
embedded libraries providing port and bus operations, standard  
keypad and display support, and extended math functionality.  
PSoC Development Tool Kit  
June 3, 2004  
Document No. 38-12009 Rev. *E  
5
CY8C22x13 Final Data Sheet  
PSoC™ Overview  
the device to your specification and provides the high-level user  
module API functions.  
User Modules and the PSoC  
Development Process  
The development process for the PSoC device differs from that  
of a traditional fixed function microprocessor. The configurable  
analog and digital hardware blocks give the PSoC architecture  
a unique flexibility that pays dividends in managing specification  
change during development and by lowering inventory costs.  
These configurable resources, called PSoC Blocks, have the  
ability to implement a wide variety of user-selectable functions.  
Each block has several registers that determine its function and  
connectivity to other blocks, multiplexers, buses, and to the IO  
pins. Iterative development cycles permit you to adapt the hard-  
ware as well as the software. This substantially lowers the risk  
of having to select a different part to meet the final design  
requirements.  
Device Editor  
Placement  
User  
Module  
Selection  
Source  
Code  
Generator  
and  
Parameter  
-ization  
Generate  
Application  
Application Editor  
Source  
Code  
Editor  
Project  
Manager  
Build  
Manager  
To speed the development process, the PSoC Designer Inte-  
grated Development Environment (IDE) provides a library of  
pre-built, pre-tested hardware peripheral functions, called “User  
Modules.” User modules make selecting and implementing  
peripheral devices simple, and come in analog, digital, and  
mixed signal varieties. The standard User Module library con-  
tains over 50 common peripherals such as ADCs, DACs Tim-  
ers, Counters, UARTs, and other not-so common peripherals  
such as DTMF Generators and Bi-Quad analog filter sections.  
Build  
All  
Debugger  
Each user module establishes the basic register settings that  
implement the selected function. It also provides parameters  
that allow you to tailor its precise configuration to your particular  
application. For example, a Pulse Width Modulator User Mod-  
ule configures one or more digital PSoC blocks, one for each 8  
bits of resolution. The user module parameters permit you to  
establish the pulse width and duty cycle. User modules also  
provide tested software to cut your development time. The user  
module application programming interface (API) provides high-  
level functions to control and respond to hardware events at  
run-time. The API also provides optional interrupt service rou-  
tines that you can adapt as needed.  
Event &  
Breakpoint  
Manager  
Interface  
to ICE  
Storage  
Inspector  
User Modules and Development Process Flow Chart  
The next step is to write your main program, and any sub-rou-  
tines using PSoC Designer’s Application Editor subsystem.  
The Application Editor includes a Project Manager that allows  
you to open the project source code files (including all gener-  
ated code files) from a hierarchal view. The source code editor  
provides syntax coloring and advanced edit features for both C  
and assembly language. File search capabilities include simple  
string searches and recursive “grep-style” patterns. A single  
mouse click invokes the Build Manager. It employs a profes-  
sional-strength “makefile” system to automatically analyze all  
file dependencies and run the compiler and assembler as nec-  
essary. Project-level options control optimization strategies  
used by the compiler and linker. Syntax errors are displayed in  
a console window. Double clicking the error message takes you  
directly to the offending line of source code. When all is correct,  
the linker builds a ROM file image suitable for programming.  
The API functions are documented in user module data sheets  
that are viewed directly in the PSoC Designer IDE. These data  
sheets explain the internal operation of the user module and  
provide performance specifications. Each data sheet describes  
the use of each user module parameter and documents the set-  
ting of each register controlled by the user module.  
The development process starts when you open a new project  
and bring up the Device Editor, a pictorial environment (GUI) for  
configuring the hardware. You pick the user modules you need  
for your project and map them onto the PSoC blocks with point-  
and-click simplicity. Next, you build signal chains by intercon-  
necting user modules to each other and the IO pins. At this  
stage, you also configure the clock source connections and  
enter parameter values directly or by selecting values from  
drop-down menus. When you are ready to test the hardware  
configuration or move on to developing code for the project, you  
perform the “Generate Application” step. This causes PSoC  
Designer to generate source code that automatically configures  
The last step in the development process takes place inside the  
PSoC Designer’s Debugger subsystem. The Debugger down-  
loads the ROM image to the In-Circuit Emulator (ICE) where it  
runs at full speed. Debugger capabilities rival those of systems  
costing many times more. In addition to traditional single-step,  
run-to-breakpoint and watch-variable features, the Debugger  
provides a large trace buffer and allows you define complex  
breakpoint events that include monitoring address and data bus  
values, memory locations and external signals.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
6
CY8C22x13 Final Data Sheet  
PSoC™ Overview  
Document Conventions  
Table of Contents  
For an in depth discussion and more information on your PSoC  
device, obtain the PSoC Mixed Signal Array Technical Refer-  
ence Manual. This document encompasses and is organized  
into the following chapters and sections.  
Acronyms Used  
The following table lists the acronyms that are used in this doc-  
ument.  
Acronym  
AC  
Description  
alternating current  
ADC  
API  
analog-to-digital converter  
application programming interface  
central processing unit  
continuous time  
CPU  
CT  
DAC  
DC  
digital-to-analog converter  
direct current  
EEPROM  
FSR  
GPIO  
IO  
electrically erasable programmable read-only memory  
full scale range  
general purpose IO  
input/output  
IPOR  
LSb  
imprecise power on reset  
least-significant bit  
LVD  
low voltage detect  
MSb  
PC  
most-significant bit  
program counter  
POR  
PPOR  
PSoC™  
PWM  
RAM  
ROM  
SC  
power on reset  
precision power on reset  
Programmable System-on-Chip  
pulse width modulator  
random access memory  
read only memory  
switched capacitor  
SMP  
switch mode pump  
Units of Measure  
A units of measure table is located in the Electrical Specifica-  
tions section. Table 3-1 on page 13 lists all the abbreviations  
used to measure the PSoC devices.  
Numeric Naming  
Hexidecimal numbers are represented with all letters in upper-  
case with an appended lowercase ‘h’ (for example, ‘14h’ or  
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’  
prefix, the C coding convention. Binary numbers have an  
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).  
Numbers not indicated by an ‘h’ or ‘b’ are decimal.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
7
1. Pin Information  
This chapter describes, lists, and illustrates the CY8C22x13 PSoC device pins and pinout configurations.  
1.1  
Pinouts  
The CY8C22x13 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port  
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.  
1.1.1  
8-Pin Part Pinout  
Table 1-1. 8-Pin Part Pinout (PDIP, SOIC)  
Type  
CY8C22113 8-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
2
3
4
5
IO  
IO  
IO  
IO  
I
P0[5]  
Analog column mux input and column output.  
Analog column mux input.  
AIO, P0[5]  
AI, P0[3]  
Vdd  
P0[4], AI  
1
2
3
4
8
7
6
5
P0[3]  
P1[1]  
Vss  
PDIP  
SOIC  
Crystal Input (XTALin), I2C Serial Clock (SCL)  
Ground connection.  
I2C SCL, XTALin, P1[1]  
Vss  
P0[2], AI  
Power  
P1[0], XTALout, I2C SDA  
IO  
P1[0]  
Crystal Output (XTALout), I2C Serial Data  
(SDA)  
6
7
8
IO  
IO  
I
I
P0[2]  
P0[4]  
Vdd  
Analog column mux input.  
Analog column mux input.  
Supply voltage.  
Power  
LEGEND: A = Analog, I = Input, and O = Output.  
1.1.2  
20-Pin Part Pinout  
Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC)  
Type  
CY8C22213 20-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
IO  
IO  
IO  
IO  
I
IO  
I
P0[7]  
P0[5]  
P0[3]  
P0[1]  
Vss  
Analog column mux input.  
Analog column mux input and column output.  
Analog column mux input.  
Analog column mux input.  
Ground connection.  
AI, P0[7]  
AIO, P0[5]  
Vdd  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
7
8
9
2
P0[6], AI  
3
AI, P0[3]  
P0[4], AI  
P0[2], AI  
4
I
AI, P0[1]  
PDIP  
SSOP  
SOIC  
5
Power  
Power  
Vss  
P0[0], AI  
6
IO  
IO  
IO  
IO  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
Vss  
I2C Serial Clock (SCL)  
I2C SCL, P1[7]  
I2C SDA, P1[5]  
P1[3]  
XRES  
P1[6]  
7
I2C Serial Data (SDA)  
P1[4], EXTCLK  
P1[2]  
8
I2C SCL, XTALin, P1[1]  
Vss  
9
Crystal Input (XTALin), I2C Serial Clock (SCL)  
Ground connection.  
P1[0], XTALout, I2C SDA  
10  
10  
11  
IO  
IO  
P1[0]  
Crystal Output (XTALout), I2C Serial Data  
(SDA)  
12  
P1[2]  
13  
14  
15  
IO  
IO  
P1[4]  
P1[6]  
XRES  
Optional External Clock Input (EXTCLK)  
Input  
Active high external reset with internal pull  
down.  
16  
17  
18  
19  
20  
IO  
IO  
IO  
IO  
I
I
I
I
P0[0]  
P0[2]  
P0[4]  
P0[6]  
Vdd  
Analog column mux input.  
Analog column mux input.  
Analog column mux input.  
Analog column mux input.  
Supply voltage.  
Power  
LEGEND: A = Analog, I = Input, and O = Output.  
June 2004  
Document No. 38-12009 Rev. *E  
8
       
CY8C22x13 Final Data Sheet  
1. Pin Information  
1.1.3  
32-Pin Part Pinout  
Table 1-3. 32-Pin Part Pinout (MLF*)  
Type  
CY8C22213 PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
NC  
No connection. Do not use.  
No connection. Do not use.  
No connection. Do not use.  
No connection. Do not use.  
Ground connection.  
2
NC  
3
NC  
4
NC  
5
Power  
Power  
IO  
Vss  
NC  
1
2
3
4
5
6
7
8
P0[2], AI  
P0[0], AI  
NC  
24  
23  
22  
6
Vss  
Ground connection.  
NC  
7
P1[7]  
P1[5]  
NC  
I2C Serial Clock (SCL)  
I2C Serial Data (SDA)  
NC  
NC  
Vss  
8
IO  
21 NC  
20 NC  
MLF  
(Top View)  
9
No connection. Do not use.  
Vss  
NC  
19  
18  
10  
11  
12  
13  
IO  
P1[3]  
P1[1]  
Vss  
I2C SCL, P1[7]  
I2C SDA, P1[5]  
XRES  
IO  
Crystal Input (XTALin), I2C Serial Clock (SCL)  
Ground connection.  
17 P1[6]  
Power  
IO  
P1[0]  
Crystal Output (XTALout), I2C Serial Data  
(SDA)  
14  
15  
16  
17  
18  
IO  
IO  
P1[2]  
P1[4]  
NC  
Optional External Clock Input (EXTCLK)  
No connection. Do not use.  
IO  
P1[6]  
XRES  
Input  
Active high external reset with internal pull  
down.  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
NC  
No connection. Do not use.  
No connection. Do not use.  
No connection. Do not use.  
No connection. Do not use.  
Analog column mux input.  
Analog column mux input.  
No connection. Do not use.  
Analog column mux input.  
Analog column mux input.  
Supply voltage.  
NC  
NC  
NC  
IO  
IO  
I
I
P0[0]  
P0[2]  
NC  
IO  
IO  
I
I
P0[4]  
P0[6]  
Vdd  
Power  
IO  
IO  
IO  
IO  
I
IO  
I
P0[7]  
P0[5]  
P0[3]  
P0[1]  
Analog column mux input.  
Analog column mux input and column output.  
Analog column mux input.  
Analog column mux input.  
I
LEGEND: A = Analog, I = Input, and O = Output.  
* The MLF package has a center pad that must be connected to the same ground  
as the Vss pin.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
9
 
2. Register Reference  
This chapter lists the registers of the CY8C22x13 PSoC device by way of mapping tables, in offset order. For detailed register infor-  
mation, reference the PSoC™ Mixed Signal Array Technical Reference Manual.  
2.1  
Register Conventions  
2.2  
Register Mapping Tables  
The PSoC device has a total register address space of 512  
bytes. The register space is also referred to as IO space and is  
broken into two parts. The XOI bit in the Flag register deter-  
mines which bank the user is currently in. When the XOI bit is  
set, the user is said to be in the “extended” address space or  
the “configuration” registers.  
2.1.1  
Abbreviations Used  
The register conventions specific to this section are listed in the  
following table.  
Convention  
Description  
Read and write register or bit(s)  
Read register or bit(s)  
Note In the following register mapping tables, blank fields are  
Reserved and should not be accessed.  
RW  
R
W
L
Write register or bit(s)  
Logical register or bit(s)  
Clearable register or bit(s)  
Access is bit specific  
C
#
May 2004  
© Cypress MicroSystems, Inc. 2003 — Document No. 38-12009 Rev. *E  
10  
       
CY8C22x13 Final Data Sheet  
2. Register Reference  
Register Map Bank 0 Table: User Space  
PRT0DR  
PRT0IE  
PRT0GS  
PRT0DM2  
PRT1DR  
PRT1IE  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
RW  
RW  
RW  
RW  
PRT1GS  
PRT1DM2  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
I2C_CFG  
I2C_SCR  
I2C_DR  
I2C_MSCR  
INT_CLR0  
INT_CLR1  
RW  
#
RW  
#
RW  
RW  
INT_CLR3  
INT_MSK3  
RW  
RW  
DBB00DR0  
DBB00DR1  
DBB00DR2  
DBB00CR0  
DBB01DR0  
DBB01DR1  
DBB01DR2  
DBB01CR0  
DCB02DR0  
DCB02DR1  
DCB02DR2  
DCB02CR0  
DCB03DR0  
DCB03DR1  
DCB03DR2  
DCB03CR0  
#
AMX_IN  
RW  
INT_MSK0  
INT_MSK1  
INT_VC  
RES_WDT  
DEC_DH  
DEC_DL  
RW  
RW  
RC  
W
RC  
RC  
RW  
RW  
W
RW  
#
ARF_CR  
CMP_CR0  
ASY_CR  
CMP_CR1  
RW  
#
#
#
W
RW  
#
RW  
DEC_CR0  
DEC_CR1  
#
W
RW  
#
#
W
RW  
#
RDI0RI  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDIOLT1  
RDI0RO0  
RDI0RO1  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
ACB01CR3  
ACB01CR0  
ACB01CR1  
ACB01CR2  
RW  
RW  
RW  
RW  
CPU_F  
RL  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
CPU_SCR1  
CPU_SCR0  
#
#
Blank fields are Reserved and should not be accessed.  
# Access is bit specific.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
11  
CY8C22x13 Final Data Sheet  
2. Register Reference  
Register Map Bank 1 Table: Configuration Space  
PRT0DM0  
PRT0DM1  
PRT0IC0  
PRT0IC1  
PRT1DM0  
PRT1DM1  
PRT1IC0  
PRT1IC1  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
RW  
RW  
RW  
RW  
GDI_O_IN  
GDI_E_IN  
GDI_O_OU  
GDI_E_OU  
RW  
RW  
RW  
RW  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
OSC_GO_EN DD  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
R
OSC_CR4  
OSC_CR3  
OSC_CR0  
OSC_CR1  
OSC_CR2  
VLT_CR  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
DBB00FN  
DBB00IN  
DBB00OU  
RW  
RW  
RW  
CLK_CR0  
CLK_CR1  
ABF_CR0  
RW  
RW  
RW  
DBB01FN  
DBB01IN  
DBB01OU  
RW  
RW  
RW  
VLT_CMP  
AMD_CR1  
ALT_CR0  
RW  
RW  
DCB02FN  
DCB02IN  
DCB02OU  
RW  
RW  
RW  
IMO_TR  
ILO_TR  
BDG_TR  
ECO_TR  
W
W
RW  
W
DCB03FN  
DCB03IN  
DCB03OU  
RW  
RW  
RW  
RDI0RI  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDIOLT1  
RDI0RO0  
RDI0RO1  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
ACB01CR3  
ACB01CR0  
ACB01CR1  
ACB01CR2  
RW  
RW  
RW  
RW  
CPU_F  
RL  
CPU_SCR1  
CPU_SCR0  
#
#
Blank fields are Reserved and should not be accessed.  
# Access is bit specific.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
12  
3. Electrical Specifications  
This chapter presents the DC and AC electrical specifications of the CY8C22x13 PSoC device. For the most up to date electrical  
specifications, confirm that you have the most recent data sheet by referencing the web at http://www.cypress.com/psoc.  
o
o
o
Specifications are valid for -40 C T 85 C and T 100 C as specified, except where noted. Specifications for devices running  
A
J
o
o
o
at greater than 12 MHz are valid for -40 C T 70 C and T 82 C.  
A
J
5.25  
4.75  
3.00  
93 kHz  
12 MHz  
24 MHz  
CPU Frequency  
Figure 3-1. Voltage versus Operating Frequency  
The following table lists the units of measure that are used in this chapter.  
Table 3-1: Units of Measure  
Symbol  
Unit of Measure  
Symbol  
Unit of Measure  
oC  
dB  
degree Celsius  
µW  
micro watts  
decibels  
mA  
ms  
mV  
nA  
ns  
milli-ampere  
milli-second  
milli-volts  
fF  
femto farad  
hertz  
Hz  
KB  
1024 bytes  
1024 bits  
nano ampere  
nanosecond  
nanovolts  
Kbit  
kHz  
kΩ  
kilohertz  
nV  
kilohm  
ohm  
MHz  
MΩ  
µA  
megahertz  
megaohm  
micro ampere  
micro farad  
micro henry  
microsecond  
micro volts  
pA  
pF  
pp  
ppm  
ps  
pico ampere  
pico farad  
peak-to-peak  
parts per million  
picosecond  
µF  
µH  
µs  
sps  
σ
samples per second  
sigma: one standard deviation  
volts  
µV  
µVrms  
micro volts root-mean-square  
V
June 2004  
Document No. 38-12009 Rev. *E  
13  
   
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.1  
Absolute Maximum Ratings  
Table 3-2. Absolute Maximum Ratings  
Symbol  
Description  
Min  
-55  
Typ  
Max  
+100  
Units  
oC  
Notes  
TSTG  
Storage Temperature  
Higher storage temperatures will reduce data  
retention time.  
oC  
V
TA  
Ambient Temperature with Power Applied  
-40  
+85  
Vdd  
VIO  
Supply Voltage on Vdd Relative to Vss  
DC Input Voltage  
-0.5  
+6.0  
Vss - 0.5  
Vdd + 0.5  
V
DC Voltage Applied to Tri-state  
Vss - 0.5  
-25  
Vdd + 0.5  
+50  
V
IMIO  
Maximum Current into any Port Pin  
mA  
IMAIO  
Maximum Current into any Port Pin Configured as Analog  
Driver  
-50  
+50  
mA  
Static Discharge Voltage  
Latch-up Current  
2000  
V
200  
mA  
3.2  
Operating Temperature  
Table 3-3. Operating Temperature  
Symbol  
TA  
TJ  
Description  
Min  
Typ  
Max  
Units  
Notes  
oC  
oC  
Ambient Temperature  
Junction Temperature  
-40  
+85  
-40  
+100  
The temperature rise from ambient to junction is  
package specific. See “Thermal Impedances”  
on page 34. The user must limit the power con-  
sumption to comply with this requirement.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
14  
   
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3  
DC Electrical Characteristics  
3.3.1  
DC Chip-Level Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-4. DC Chip-Level Specifications  
Symbol  
Vdd  
Description  
Min  
3.00  
Typ  
Max  
5.25  
Units  
Notes  
Supply Voltage  
Supply Current  
5
V
Conditions are Vdd = 5.0V, 25 oC, CPU = 3  
MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 =  
93.75 kHz, VC3 = 93.75 kHz.  
IDD  
8
mA  
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3  
IDD3  
Supply Current  
3.3  
6.0  
mA  
MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2  
= 93.75 kHz, VC3 = 93.75 kHz.  
ISB  
Sleep (Mode) Current with POR, LVD, Sleep Timer, and  
WDT.a  
3
4
4
6.5  
25  
µA  
µA  
µA  
Conditions are with internal slow speed oscilla-  
tor, Vdd = 3.3V, -40 oC <= TA <= 55 oC.  
ISBH  
Sleep (Mode) Current with POR, LVD, Sleep Timer, and  
WDT at high temperature.a  
Conditions are with internal slow speed oscilla-  
tor, Vdd = 3.3V, 55 oC < TA <= 85 oC.  
ISBXTL  
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,  
and external crystal.a  
7.5  
Conditions are with properly loaded, 1 µW max,  
32.768 kHz crystal. Vdd = 3.3V, -40 oC <= TA <=  
55 oC.  
ISBXTLH  
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,  
and external crystal at high temperature.a  
5
26  
µA  
Conditions are with properly loaded, 1 µW max,  
32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA <=  
85 oC.  
VREF  
Reference Voltage (Bandgap)  
1.275  
1.3  
1.325  
V
Trimmed for appropriate Vdd.  
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions  
enabled.  
3.3.2  
DC General Purpose IO Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-5. DC GPIO Specifications  
Symbol  
Description  
Min  
Typ  
5.6  
Max  
Units  
kΩ  
Notes  
RPU  
Pull up Resistor  
4
4
8
8
RPD  
VOH  
Pull down Resistor  
High Output Level  
5.6  
kΩ  
Vdd - 1.0  
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (80 mA max-  
imum combined IOH budget)  
VOL  
Low Output Level  
0.75  
0.8  
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (150 mA  
maximum combined IOL budget)  
VIL  
Input Low Level  
Input High Level  
Input Hysterisis  
V
Vdd = 3.0 to 5.25  
Vdd = 3.0 to 5.25  
VIH  
VH  
2.1  
V
60  
1
mV  
nA  
pF  
pF  
IIL  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
Capacitive Load on Pins as Output  
Gross tested to 1 µA.  
Package and pin dependent. Temp = 25oC.  
Package and pin dependent. Temp = 25oC.  
CIN  
COUT  
3.5  
3.5  
10  
10  
June 3, 2004  
Document No. 38-12009 Rev. *E  
15  
     
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3.3  
DC Operational Amplifier Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at  
25°C and are for design guidance only.  
Table 3-6. 5V DC Operational Amplifier Specifications  
Symbol  
VOSOA  
Description  
Min  
Typ  
1.6  
Max  
Units  
mV  
Notes  
Input Offset Voltage (absolute value) Low Power  
Input Offset Voltage (absolute value) Mid Power  
Input Offset Voltage (absolute value) High Power  
Average Input Offset Voltage Drift  
10  
8
1.3  
1.2  
7.0  
mV  
mV  
7.5  
µV/oC  
TCVOSOA  
IEBOA  
35.0  
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
Common Mode Voltage Range  
20  
pA  
Gross tested to 1 µA.  
Package and pin dependent. Temp = 25oC.  
CINOA  
4.5  
9.5  
pF  
V
VCMOA  
0.0  
0.5  
Vdd  
The common-mode input voltage range is mea-  
sured through an analog output buffer. The  
specification includes the limitations imposed  
by the characteristics of the analog output  
buffer.  
Common Mode Voltage Range (high power or high  
opamp bias)  
Vdd - 0.5  
GOLOA  
Open Loop Gain  
dB  
Specification is applicable at high power. For all  
other bias modes (except high power, high  
opamp bias), minimum is 60 dB.  
Power = Low  
60  
60  
80  
Power = Medium  
Power = High  
VOHIGHOA  
VOLOWOA  
ISOA  
High Output Voltage Swing (worst case internal load)  
Power = Low  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.5  
V
V
V
Power = Medium  
Power = High  
Low Output Voltage Swing (worst case internal load)  
Power = Low  
0.2  
0.2  
0.5  
V
V
V
Power = Medium  
Power = High  
Supply Current (including associated AGND buffer)  
Power = Low  
150  
300  
600  
1200  
2400  
4600  
200  
400  
800  
1600  
3200  
6400  
µA  
µA  
µA  
µA  
µA  
µA  
dB  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
Power = High, Opamp Bias = High  
Supply Voltage Rejection Ratio  
PSRROA  
60  
June 3, 2004  
Document No. 38-12009 Rev. *E  
16  
 
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
Table 3-7. 3.3V DC Operational Amplifier Specifications  
Symbol  
VOSOA  
Description  
Min  
Typ  
1.65  
Max  
Units  
mV  
Notes  
Input Offset Voltage (absolute value) Low Power  
Input Offset Voltage (absolute value) Mid Power  
High Power is 5 Volt Only  
10  
8
1.32  
mV  
µV/oC  
TCVOSOA  
IEBOA  
Average Input Offset Voltage Drift  
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
Common Mode Voltage Range  
7.0  
20  
4.5  
35.0  
pA  
Gross tested to 1 µA.  
Package and pin dependent. Temp = 25oC.  
CINOA  
9.5  
pF  
V
VCMOA  
0.2  
Vdd - 0.2  
The common-mode input voltage range is  
measured through an analog output buffer.  
The specification includes the limitations  
imposed by the characteristics of the analog  
output buffer.  
GOLOA  
Open Loop Gain  
Power = Low  
dB  
Specification is applicable at high power. For  
all other bias modes (except high power, high  
opamp bias), minimum is 60 dB.  
60  
60  
80  
Power = Medium  
Power = High  
VOHIGHOA  
VOLOWOA  
ISOA  
High Output Voltage Swing (worst case internal load)  
Power = Low  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.2  
V
V
V
Power = Medium  
Power = High is 5V only  
Low Output Voltage Swing (worst case internal load)  
Power = Low  
0.2  
0.2  
0.2  
V
V
V
Power = Medium  
Power = High  
Supply Current (including associated AGND buffer)  
Power = Low  
150  
200  
µA  
µA  
µA  
µA  
µA  
µA  
Power = Low, Opamp Bias = High  
Power = Medium  
300  
400  
600  
800  
Power = Medium, Opamp Bias = High  
Power = High  
1200  
2400  
4600  
1600  
3200  
6400  
Power = High, Opamp Bias = High  
PSRROA  
Supply Voltage Rejection Ratio  
50  
dB  
June 3, 2004  
Document No. 38-12009 Rev. *E  
17  
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3.4  
DC Analog Output Buffer Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-8. 5V DC Analog Output Buffer Specifications  
Symbol  
VOSOB  
Description  
Min  
Typ  
Max  
Units  
mV  
Notes  
Input Offset Voltage (Absolute Value)  
3
12  
TCVOSOB  
VCMOB  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
+6  
µV/°C  
0.5  
Vdd - 1.0  
V
ROUTOB  
Output Resistance  
Power = Low  
1
1
Power = High  
VOHIGHOB  
High Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
0.5 x Vdd + 1.1  
0.5 x Vdd + 1.1  
V
V
Power = High  
VOLOWOB  
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.3  
0.5 x Vdd - 1.3  
V
V
ISOB  
Supply Current Including Bias Cell (No Load)  
Power = Low  
1.1  
2.6  
5.1  
8.8  
mA  
mA  
dB  
Power = High  
PSRROB  
Supply Voltage Rejection Ratio  
60  
Table 3-9. 3.3V DC Analog Output Buffer Specifications  
Symbol  
VOSOB  
Description  
Min  
Typ  
Max  
Units  
Notes  
Input Offset Voltage (Absolute Value)  
3
12  
mV  
µV/°C  
V
TCVOSOB  
VCMOB  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
+6  
-
0.5  
Vdd - 1.0  
ROUTOB  
Output Resistance  
Power = Low  
1
1
Power = High  
VOHIGHOB  
High Output Voltage Swing (Load = 1K ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd + 1.0  
0.5 x Vdd + 1.0  
V
V
VOLOWOB  
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.0  
0.5 x Vdd - 1.0  
V
V
ISOB  
Supply Current Including Bias Cell (No Load)  
Power = Low  
0.8  
2.0  
2.0  
4.3  
mA  
mA  
dB  
Power = High  
PSRROB  
Supply Voltage Rejection Ratio  
50  
June 3, 2004  
Document No. 38-12009 Rev. *E  
18  
 
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3.5  
DC Analog Reference Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Table 3-10. 5V DC Analog Reference Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
AGND = Vdd/2a  
Vdd/2 - 0.043  
Vdd/2 - 0.025  
Vdd/2 + 0.003  
V
CT Block Power = High  
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%.  
Table 3-11. 3.3V DC Analog Reference Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
AGND = Vdd/2a  
Vdd/2 - 0.037  
Vdd/2 - 0.020  
Vdd/2 + 0.002  
V
CT Block Power = High  
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 2%  
3.3.6  
DC Analog PSoC Block Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-12. DC Analog PSoC Block Specifications  
Symbol  
RCT  
CSC  
Description  
Min  
Typ  
12.24  
80  
Max  
Units  
kΩ  
fF  
Notes  
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switch Cap)  
June 3, 2004  
Document No. 38-12009 Rev. *E  
19  
   
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3.7  
DC POR and LVD Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical  
Reference Manual for more information on the VLT_CR register.  
Table 3-13. DC POR and LVD Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
Vdd Value for PPOR Trip (positive ramp)  
PORLEV[1:0] = 00b  
VPPOR0R  
VPPOR1R  
VPPOR2R  
2.908  
V
V
V
PORLEV[1:0] = 01b  
4.394  
4.548  
PORLEV[1:0] = 10b  
Vdd Value for PPOR Trip (negative ramp)  
PORLEV[1:0] = 00b  
VPPOR0  
VPPOR1  
VPPOR2  
2.816  
4.394  
4.548  
V
V
V
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
PPOR Hysteresis  
VPH0  
VPH1  
VPH2  
PORLEV[1:0] = 00b  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
92  
0
mV  
mV  
mV  
0
Vdd Value for LVD Trip  
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
VLVD0  
VLVD1  
VLVD2  
VLVD3  
VLVD4  
VLVD5  
VLVD6  
VLVD7  
V
2.863  
2.963  
3.070  
3.920  
4.393  
4.550  
4.632  
4.718  
2.921  
3.023  
3.133  
4.00  
2.979a  
3.083  
3.196  
4.080  
4.573  
V
V
V
V
V
V
V
V
4.483  
4.643  
4.727  
4.814  
4.736b  
4.822  
4.910  
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.  
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.  
June 3, 2004  
Document No. 38-12009 Rev. *E  
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CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.3.8  
DC Programming Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-14. DC Programming Specifications  
Symbol  
IDDP  
Description  
Min  
Typ  
Max  
Units  
mA  
Notes  
Supply Current During Programming or Verify  
5
25  
0.8  
VILP  
VIHP  
IILP  
Input Low Voltage During Programming or Verify  
Input High Voltage During Programming or Verify  
V
2.2  
V
Input Current when Applying Vilp to P1[0] or P1[1] During  
Programming or Verify  
0.2  
mA  
Driving internal pull-down resistor.  
Driving internal pull-down resistor.  
IIHP  
Input Current when Applying Vihp to P1[0] or P1[1] During  
Programming or Verify  
1.5  
mA  
VOLV  
VOHV  
Output Low Voltage During Programming or Verify  
Output High Voltage During Programming or Verify  
Vss + 0.75  
Vdd  
V
V
Vdd - 1.0  
FlashENPB  
FlashENT  
FlashDR  
Flash Endurance (per block)  
50,000  
1,800,000  
10  
Erase/write cycles per block.  
Erase/write cycles.  
Flash Endurance (total)a  
Flash Data Retention  
Years  
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of  
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever  
sees more than 50,000 cycles).  
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to  
June 3, 2004  
Document No. 38-12009 Rev. *E  
21  
 
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4  
AC Electrical Characteristics  
3.4.1  
AC Chip-Level Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-15. AC Chip-Level Specifications  
Symbol  
FIMO  
Description  
Min  
23.4  
Typ  
Max  
24.6a  
Units  
MHz  
Notes  
Internal Main Oscillator Frequency  
24  
24  
12  
48  
Trimmed. Utilizing factory trim values.  
24.6a,b  
12.3b,c  
49.2a,b,d  
FCPU1  
FCPU2  
F48M  
CPU Frequency (5V Nominal)  
CPU Frequency (3.3V Nominal)  
Digital PSoC Block Frequency  
0.93  
0.93  
0
MHz  
MHz  
MHz  
Refer to the AC Digital Block Specifications  
below.  
24.6b,e,d  
64  
F24M  
F32K1  
F32K2  
Digital PSoC Block Frequency  
Internal Low Speed Oscillator Frequency  
External Crystal Oscillator  
0
24  
32  
MHz  
kHz  
kHz  
15  
32.768  
Accuracy is capacitor and crystal dependent.  
50% duty cycle.  
FPLL  
PLL Frequency  
23.986  
MHz  
Is a multiple (x732) of crystal frequency.  
Jitter24M2  
TPLLSLEW  
24 MHz Period Jitter (PLL)  
PLL Lock Time  
600  
10  
ps  
0.5  
ms  
TPLLSLEWS- PLL Lock Time for Low Gain Setting  
LOW  
0.5  
50  
ms  
TOS  
External Crystal Oscillator Startup to 1%  
1700  
2800  
ms  
ms  
2620  
3800f  
TOSACC  
External Crystal Oscillator Startup to 100 ppm  
Jitter32k  
TXRST  
32 kHz Period Jitter  
100  
ns  
External Reset Pulse Width  
10  
µs  
DC24M  
24 MHz Duty Cycle  
40  
50  
60  
%
Step24M  
Fout48M  
24 MHz Trim Step Size  
48 MHz Output Frequency  
50  
kHz  
MHz  
49.2a,c  
46.8  
48.0  
Trimmed. Utilizing factory trim values.  
Jitter24M1  
FMAX  
24 MHz Period Jitter (IMO)  
600  
ps  
Maximum frequency of signal on row input or row output.  
12.3  
MHz  
TRAMP  
Supply Ramp Time  
0
µs  
a. 4.75V < Vdd < 5.25V.  
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.  
d. See the individual user module data sheets for information on maximum frequencies for user modules.  
e. 3.0V < 5.25V.  
f. The crystal oscillator frequency is within 100 ppm of its final value by the end of the T  
period. Correct operation assumes a properly loaded 1 uW maximum drive level  
osacc  
o
o
32.768 kHz crystal. 3.0V Vdd 5.5V, -40 C T 85 C.  
A
PLL  
Enable  
T
24 MHz  
PLLSLEW  
FPLL  
PLL  
Gain  
0
Figure 3-2. PLL Lock Timing Diagram  
June 3, 2004  
Document No. 38-12009 Rev. *E  
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CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
PLL  
Enable  
T
24 MHz  
PLLSLEWLOW  
FPLL  
PLL  
Gain  
1
Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram  
32K  
Select  
32 kHz  
T
OS  
F32K2  
Figure 3-4. External Crystal Oscillator Startup Timing Diagram  
Jitter24M1  
F24M  
Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram  
Jitter32k  
F32K2  
Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram  
June 3, 2004  
Document No. 38-12009 Rev. *E  
23  
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4.2  
AC General Purpose IO Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-16. AC GPIO Specifications  
Symbol  
FGPIO  
Description  
GPIO Operating Frequency  
Min  
Typ  
Max  
Units  
MHz  
Notes  
0
12  
TRiseF  
TFallF  
TRiseS  
TFallS  
Rise Time, Normal Strong Mode, Cload = 50 pF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
Rise Time, Slow Strong Mode, Cload = 50 pF  
Fall Time, Slow Strong Mode, Cload = 50 pF  
3
18  
18  
ns  
ns  
ns  
ns  
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
2
10  
10  
27  
22  
90%  
10%  
GPIO  
Pin  
TRiseF  
TRiseS  
TFallF  
TFallS  
Figure 3-7. GPIO Timing Diagram  
June 3, 2004  
Document No. 38-12009 Rev. *E  
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CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4.3  
AC Operational Amplifier Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Table 3-17. 5V AC Operational Amplifier Specifications  
Symbol  
TROA  
Description  
Min  
Typ  
Max  
Units  
Notes  
Rising Settling Time from 80% of V to 0.1% of V (10 pF  
Specification maximums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
load, Unity Gain)  
Power = Low  
3.9  
µs  
Power = Low, Opamp Bias = High  
Power = Medium  
µs  
µs  
µs  
µs  
µs  
Power = Medium, Opamp Bias = High  
Power = High  
0.72  
0.62  
Power = High, Opamp Bias = High  
TSOA  
Falling Settling Time from 20% of V to 0.1% of V (10 pF  
Specification maximums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
load, Unity Gain)  
Power = Low  
5.9  
µs  
µs  
µs  
µs  
µs  
µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
0.92  
0.72  
Power = High, Opamp Bias = High  
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low  
SRROA  
SRFOA  
BWOA  
ENOA  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
0.15  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
1.7  
Power = High, Opamp Bias = High  
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low  
6.5  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
0.01  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High  
0.5  
Power = High, Opamp Bias = High  
Gain Bandwidth Product  
4.0  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
Power = Low  
0.75  
MHz  
Power = Low, Opamp Bias = High  
Power = Medium  
MHz  
MHz  
Power = Medium, Opamp Bias = High  
Power = High  
3.1  
MHz  
MHz  
Power = High, Opamp Bias = High  
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
5.4  
MHz  
200  
nV/rt-Hz  
June 3, 2004  
Document No. 38-12009 Rev. *E  
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CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
Table 3-18. 3.3V AC Operational Amplifier Specifications  
Symbol  
TROA  
Description  
Min  
Typ  
Max  
Units  
Notes  
Rising Settling Time from 80% of V to 0.1% of V (10 pF  
Specification maximums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
load, Unity Gain)  
Power = Low  
3.92  
µs  
Power = Low, Opamp Bias = High  
Power = Medium  
µs  
µs  
µs  
µs  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not supported)  
0.72  
Power = High, Opamp Bias = High (3.3 Volt High Power,  
High Opamp Bias not supported)  
µs  
TSOA  
Falling Settling Time from 20% of V to 0.1% of V (10 pF  
load, Unity Gain)  
Specification maximums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
Power = Low  
5.41  
µs  
µs  
µs  
µs  
µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not supported)  
0.72  
Power = High, Opamp Bias = High (3.3 Volt High Power,  
High Opamp Bias not supported)  
µs  
SRROA  
SRFOA  
BWOA  
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
0.31  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not supported)  
2.7  
Power = High, Opamp Bias = High (3.3 Volt High Power,  
High Opamp Bias not supported)  
V/µs  
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
0.24  
V/µs  
V/µs  
V/µs  
V/µs  
V/µs  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not supported)  
1.8  
Power = High, Opamp Bias = High (3.3 Volt High Power,  
High Opamp Bias not supported)  
V/µs  
Gain Bandwidth Product  
Specification minimums for low power and  
high opamp bias, medium power, and  
medium power and high opamp bias levels  
are between low and high power levels.  
Power = Low  
0.67  
MHz  
MHz  
MHz  
MHz  
MHz  
Power = Low, Opamp Bias = High  
Power = Medium  
Power = Medium, Opamp Bias = High  
Power = High (3.3 Volt High Bias Operation not supported)  
2.8  
Power = High, Opamp Bias = High (3.3 Volt High Power,  
High Opamp Bias not supported)  
MHz  
ENOA  
Noise at 1 kHz (Power = Medium, Opamp Bias = High)  
200  
nV/rt-Hz  
June 3, 2004  
Document No. 38-12009 Rev. *E  
26  
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4.4  
AC Digital Block Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-19. AC Digital Block Specifications  
Function  
Timer  
Description  
Min  
50a  
Typ  
Max  
Units  
ns  
Notes  
Capture Pulse Width  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz  
MHz  
ns  
4.75V < Vdd < 5.25V.  
50a  
Counter  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
49.2  
24.6  
MHz  
MHz  
4.75V < Vdd < 5.25V.  
Dead Band Kill Pulse Width:  
Asynchronous Restart Mode  
20  
ns  
ns  
50a  
Synchronous Restart Mode  
Disable Mode  
50a  
ns  
Maximum Frequency  
49.2  
49.2  
MHz  
MHz  
4.75V < Vdd < 5.25V.  
4.75V < Vdd < 5.25V.  
CRCPRS  
Maximum Input Clock Frequency  
(PRS Mode)  
CRCPRS  
Maximum Input Clock Frequency  
24.6  
MHz  
(CRC Mode)  
SPIM  
SPIS  
Maximum Input Clock Frequency  
8.2  
4.1  
MHz  
ns  
Maximum Input Clock Frequency  
50a  
Width of SS_ Negated Between Transmissions  
ns  
Transmitter Maximum Input Clock Frequency  
Receiver Maximum Input Clock Frequency  
16.4  
49.2  
MHz  
MHz  
16  
4.75V < Vdd < 5.25V.  
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
June 3, 2004  
Document No. 38-12009 Rev. *E  
27  
 
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4.5  
AC Analog Output Buffer Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-20. 5V AC Analog Output Buffer Specifications  
Symbol  
Description  
Rising Settling Time to 0.1%, 1V Step, 100pF Load  
Power = Low  
Min  
Typ  
Max  
Units  
Notes  
TROB  
2.5  
µs  
Power = High  
2.5  
µs  
TSOB  
Falling Settling Time to 0.1%, 1V Step, 100pF Load  
Power = Low  
2.2  
2.2  
µs  
Power = High  
µs  
SRROB  
SRFOB  
BWOB  
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load  
Power = Low  
0.65  
0.65  
V/µs  
Power = High  
V/µs  
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load  
Power = Low  
0.65  
0.65  
V/µs  
Power = High  
V/µs  
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load  
0.8  
0.8  
MHz  
MHz  
Power = Low  
Power = High  
BWOB  
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load  
300  
300  
kHz  
kHz  
Power = Low  
Power = High  
Table 3-21. 3.3V AC Analog Output Buffer Specifications  
Symbol  
Description  
Rising Settling Time to 0.1%, 1V Step, 100pF Load  
Power = Low  
Min  
Typ  
Max  
Units  
Notes  
TROB  
3.8  
3.8  
µs  
Power = High  
µs  
TSOB  
Falling Settling Time to 0.1%, 1V Step, 100pF Load  
Power = Low  
2.6  
2.6  
µs  
Power = High  
µs  
SRROB  
SRFOB  
BWOB  
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load  
Power = Low  
0.5  
0.5  
V/µs  
Power = High  
V/µs  
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load  
Power = Low  
0.5  
0.5  
V/µs  
Power = High  
V/µs  
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load  
0.7  
0.7  
MHz  
MHz  
Power = Low  
Power = High  
BWOB  
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load  
200  
200  
kHz  
kHz  
Power = Low  
Power = High  
June 3, 2004  
Document No. 38-12009 Rev. *E  
28  
 
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
3.4.6  
AC External Clock Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-22. 5V AC External Clock Specifications  
Symbol  
Description  
Min  
Typ  
Max  
24.24  
Units  
MHz  
Notes  
FOSCEXT  
Frequency  
0
High Period  
Low Period  
20.6  
20.6  
150  
ns  
ns  
µs  
Power Up IMO to Switch  
Table 3-23. 3.3V AC External Clock Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
Frequency with CPU Clock divide by 1a  
FOSCEXT  
0
0
12.12  
24.24  
MHz  
MHz  
Frequency with CPU Clock divide by 2 or greaterb  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
FOSCEXT  
41.7  
41.7  
150  
ns  
ns  
µs  
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.  
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-  
cent duty cycle requirement is met.  
3.4.7  
AC Programming Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-24. AC Programming Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
ns  
Notes  
TRSCLK  
Rise Time of SCLK  
Fall Time of SCLK  
1
20  
20  
TFSCLK  
TSSCLK  
THSCLK  
FSCLK  
1
ns  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
ns  
TERASEB Flash Erase Time (Block)  
15  
30  
TWRITE  
TDSCLK  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
45  
June 3, 2004  
Document No. 38-12009 Rev. *E  
29  
   
CY8C22x13 Final Data Sheet  
3. Electrical Specifications  
2
3.4.8  
AC I C Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-25. AC Characteristics of the I2C SDA and SCL Pins  
Standard Mode  
Min Max  
100  
Fast Mode  
Min Max  
Symbol  
Description  
SCL Clock Frequency  
Units  
kHz  
Notes  
FSCLI2C  
0
0
400  
THDSTAI2C Hold Time (repeated) START Condition. After this  
period, the first clock pulse is generated.  
4.0  
0.6  
µs  
TLOWI2C  
THIGHI2C  
LOW Period of the SCL Clock  
HIGH Period of the SCL Clock  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
µs  
µs  
µs  
µs  
ns  
µs  
µs  
ns  
TSUSTAI2C Set-up Time for a Repeated START Condition  
THDDATI2C Data Hold Time  
100a  
0.6  
TSUDATI2C Data Set-up Time  
250  
4.0  
TSUSTOI2C Set-up Time for STOP Condition  
TBUFI2C  
TSPI2C  
Bus Free Time Between a STOP and START Condition 4.7  
1.3  
0
Pulse Width of spikes are suppressed by the input fil-  
ter.  
50  
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t  
250 ns must then be met. This will automatically be  
SU;DAT  
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data  
bit to the SDA line t  
+ t  
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.  
rmax SU;DAT  
SDA  
TSPI2C  
TLOWI2C  
TSUDATI2C  
THDSTAI2C  
TBUFI2C  
SCL  
TSUSTOI2C  
TSUSTAI2C  
THDDATI2C  
THDSTAI2C  
THIGHI2C  
S
Sr  
P
S
Figure 3-8. Definition for Timing for Fast/Standard Mode on the I2C Bus  
June 3, 2004  
Document No. 38-12009 Rev. *E  
30  
 
4. Packaging Information  
This chapter illustrates the packaging specifications for the CY8C22x13 PSoC device, along with the thermal impedances for each  
package and the typical package capacitance on crystal pins.  
4.1  
Packaging Dimensions  
51-85075 - *A  
Figure 4-1. 8-Lead (300-Mil) PDIP  
May 2004  
© Cypress MicroSystems, Inc. 2003 — Document No. 38-12009 Rev. *E  
31  
   
CY8C22x13 Final Data Sheet  
4. Packaging Information  
51-85066 - *C  
Figure 4-2. 8-Lead (150-Mil) SOIC  
51-85011 - *A  
Figure 4-3. 20-Lead (300-Mil) Molded DIP  
June 3, 2004  
Document No. 38-12009 Rev. *E  
32  
CY8C22x13 Final Data Sheet  
4. Packaging Information  
51-85077 - *C  
Figure 4-4. 20-Lead (210-Mil) SSOP  
51-85024 - *B  
Figure 4-5. 20-Lead (300-Mil) Molded SOIC  
Document No. 38-12009 Rev. *E  
June 3, 2004  
33  
CY8C22x13 Final Data Sheet  
4. Packaging Information  
X = 138 MIL  
Y = 138 MIL  
32  
51-85188 - **  
Figure 4-6. 32-Lead (5x5 mm) MLF  
4.2  
Thermal Impedances  
Table 4-1. Thermal Impedances per Package  
Package  
Typical θJA  
123 oC/W  
*
8 PDIP  
185 oC/W  
109 oC/W  
117 oC/W  
81 oC/W  
22 oC/W  
8 SOIC  
20 PDIP  
20 SSOP  
20 SOIC  
32 MLF  
* TJ = TA + POWER x θJA  
4.3  
Capacitance on Crystal Pins  
Table 4-2: Typical Package Capacitance on Crystal Pins  
Package  
8 PDIP  
Package Capacitance  
2.8 pF  
2.0 pF  
3.0 pF  
2.6 pF  
2.5 pF  
2.0 pF  
8 SOIC  
20 PDIP  
20 SSOP  
20 SOIC  
32 MLF  
June 3, 2004  
Document No. 38-12009 Rev. *E  
34  
     
5. Ordering Information  
The following table lists the CY8C22x13 PSoC Device family’s key package features and ordering codes.  
Table 5-1. CY8C22x13 PSoC Device Family Key Features and Ordering Information  
8 Pin (300 Mil) DIP  
8 Pin (150 Mil) SOIC  
CY8C22113-24PI  
CY8C22113-24SI  
2
2
256  
256  
No  
No  
-40C to +85C  
-40C to +85C  
4
4
3
3
6
6
4
4
1
1
No  
No  
8 Pin (150 Mil) SOIC  
(Tape and Reel)  
CY8C22113-24SIT  
2
256  
No  
-40C to +85C  
4
3
6
4
1
No  
20 Pin (300 Mil) DIP  
CY8C22213-24PI  
CY8C22213-24PVI  
2
2
256  
256  
No  
No  
-40C to +85C  
-40C to +85C  
4
4
3
3
16  
16  
8
8
1
1
Yes  
Yes  
20 Pin (210 Mil) SSOP  
20 Pin (210 Mil) SSOP  
(Tape and Reel)  
CY8C22213-24PVIT  
CY8C22213-24SI  
CY8C22213-24SIT  
CY8C22213-24LFI  
2
2
2
2
256  
256  
256  
256  
No  
No  
No  
No  
-40C to +85C  
-40C to +85C  
-40C to +85C  
-40C to +85C  
4
4
4
4
3
3
3
3
16  
16  
16  
16  
8
8
8
8
1
1
1
1
Yes  
Yes  
Yes  
Yes  
20 Pin (300 Mil) SOIC  
20 Pin (300 Mil) SOIC  
(Tape and Reel)  
32 Pin (5x5 mm) MLF  
5.1  
Ordering Code Definitions  
CY 8 C 22 xxx-SPxx  
Package Type:  
P = PDIP  
S = SOIC  
Thermal Rating:  
C = Commercial  
I = Industrial  
PV = SSOP  
LF = MLF  
E = Extended  
A = TQFP  
Speed: 24 MHz  
Part Number  
Family Code  
Technology Code: C = CMOS  
Marketing Code: 8 = Cypress MicroSystems  
Company ID: CY = Cypress  
June 3, 2004  
Document No. 38-12009 Rev. *E  
35  
   
6. Sales and Company Information  
To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to  
the section titled “Getting Started” on page 4 in this document.  
Cypress MicroSystems  
2700 162nd Street SW  
Building D  
Lynnwood, WA 98037  
Phone:  
Facsimile:  
800.669.0557  
425.787.4641  
Web Sites: Company Information – http://www.cypress.com  
6.1  
Revision History  
Table 6-1. CY8C22x13 Data Sheet Revision History  
Document Title:  
CY8C22113 and CY8C22213 PSoC Mixed Signal Array Final Data Sheet  
Document Number: 38-12009  
Revision  
**  
ECN #  
128180  
Issue Date  
06/30/2003  
09/16/2003  
10/15/2003  
12/05/2003  
Origin of Change  
New Silicon.  
Description of Change  
New document – Advanced Data Sheet (two page product brief).  
New document – Preliminary Data Sheet (300 page product detail).  
Revised document for Silicon Revision A.  
*A  
*B  
*C  
129202  
130127  
131679  
NWJ  
NWJ  
NWJ  
Changes to Electrical Specifications section, Miscellaneous changes to I2C, GDI, RDI,  
Registers, and Digital Block chapters.  
*D  
*E  
131803  
229421  
12/22/2003  
06/03/2004  
NWJ  
SFV  
Changes to Electrical Specifications and miscellaneous small changes throughout the  
data sheet.  
New data sheet format and organization. Reference the PSoC Mixed Signal Array Tech-  
nical Reference Manual for additional information. Title change.  
Distribution: External/Public  
Posting: None  
6.2  
Copyrights  
© Cypress MicroSystems, Inc. 2004. All rights reserved. PSoC™ (Programmable System-on-Chip™) are trademarks of Cypress MicroSystems, Inc. All other trademarks  
or registered trademarks referenced herein are property of the respective corporations.  
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry  
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products  
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of  
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Micro-  
Systems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety  
applications, unless pursuant to an express written agreement with Cypress MicroSystems.  
June 2004  
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12009 Rev. *E  
36  
     

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