Cypress CY7C144 User Manual

CY7C144 CY7C1458K  
with SEM, INT, BUSY  
x
8/9 Dual-Port Static RAM  
CY7C145, CY7C144  
8K x 8/9 Dual-Port Static RAM  
with SEM, INT, BUSY  
Features  
Functional Description  
True Dual-Ported memory cells that enable simultaneous  
reads of the same memory location  
The CY7C144 and CY7C145 are high speed CMOS 8K x 8  
and 8K x 9 dual-port static RAMs. Various arbitration schemes  
are included on the CY7C144/5 to handle situations when  
multiple processors access the same piece of data. Two ports  
are provided permitting independent, asynchronous access  
for reads and writes to any location in memory. The  
CY7C144/5 can be used as a standalone 64/72-Kbit dual-port  
static RAM or multiple devices can be combined in order to  
function as a 16/18-bit or wider master/slave dual-port static  
RAM. An M/S pin is provided for implementing 16/18-bit or  
wider memory applications without the need for separate  
master and slave devices or additional discrete logic. Appli-  
cation areas include interprocessor/multiprocessor designs,  
8K x 8 organization (CY7C144)  
8K x 9 organization (CY7C145)  
0.65-micron CMOS for optimum speed and power  
High speed access: 15 ns  
Low operating power: I = 160 mA (max.)  
CC  
Fully asynchronous operation  
Automatic power down  
TTL compatible  
communications  
status  
buffering,  
and  
dual-port  
video/graphics memory.  
Master/Slave select pin enables bus width expansion to  
16/18 bits or more  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). Two flags,  
BUSY and INT, are provided on each port. BUSY signals that  
the port is trying to access the same location currently being  
accessed by the other port. The interrupt flag (INT) permits  
communication between ports or systems by means of a mail  
box. The semaphores are used to pass a flag, or token, from  
one port to the other to indicate that a shared resource is in  
use. The semaphore logic is comprised of eight shared  
latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared  
resource is in use. An automatic power down feature is  
controlled independently on each port by a chip enable (CE)  
pin or SEM pin.  
Busy arbitration scheme provided  
Semaphores included to permit software handshaking  
between ports  
INT flag for port-to-port communication  
Available in 68-pin PLCC, 64-pin and 80-pin TQFP  
Pb-free packages available  
R/W  
L
R/W  
R
Logic Block Diagram  
CEL  
OE  
CER  
OE  
R
L
(7C145) I/O  
I/ O (7 C 1 4 5 )  
8R  
I/ O 7R  
8L  
I/O7L  
I/ O  
CONT ROL  
I/O  
CONT ROL  
I/O  
0L  
I/ O  
0R  
[1, 2]  
[1, 2]  
BUS Y  
BUSY  
L
R
A
12L  
0L  
A
12R  
MEM ORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
A
0R  
INT ERRUPT  
SEMAPHORE  
ARB I TRAT IO N  
CE  
L
CE  
OE  
R
R
OE  
L
R/W  
R/W  
L
R
SE M  
SE M  
R
R
L
[2]  
INT  
L
INT [2]  
M/S  
Notes  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
Document #: 38-06034 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 10, 2008  
CY7C145, CY7C144  
Pin Configurations (continued)  
Figure 3. 80-Pin TQFP  
NC  
1
2
3
4
NC  
60  
59  
58  
57  
/O  
A
5L  
2L  
/O  
/O  
/O  
A
4L  
3L  
4L  
5L  
A
3L  
A
2L  
5
6
7
8
56  
55  
54  
53  
A
1L  
GND  
/O  
A
0L  
6L  
/O  
7L  
INT  
L
BUSY  
V
L
9
10  
CC  
52  
51  
GND  
M/S  
CY7C145  
NC  
GND  
/O  
11  
12  
13  
14  
50  
49  
48  
47  
BUSY  
0R  
R
/O  
1R  
INT  
R
/O  
2R  
A
0R  
V
A
1R  
CC  
15  
16  
46  
45  
O
A
2R  
3R  
O
A
3R  
4R  
17  
44  
O
A
5R  
18  
19  
20  
4R  
43  
42  
41  
O
6R  
NC  
NC  
NC  
Table 1. Pin Definitions  
Left Port Right Port  
Description  
I/O  
I/O  
Data bus Input/Output  
Address Lines  
0L7L(8L)  
0R7R(8R)  
A
A
0R12R  
0L12L  
CE  
CE  
Chip Enable  
L
R
OE  
OE  
Output Enable  
L
R
R/W  
R/W  
Read/Write Enable  
L
R
SEM  
SEM  
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-  
L
R
icant bits of the address lines will determine which semaphore to write or read. The I/O pin is used  
0
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.  
INT  
INT  
Interrupt Flag. INT is set when right port writes location 1FFE and is cleared when left port reads  
L
R
L
location 1FFE. INT is set when left port writes location 1FFF and is cleared when right port reads  
R
location 1FFF.  
BUSY  
M/S  
BUSY  
R
Busy Flag  
L
Master or Slave Select  
Power  
V
CC  
GND  
Ground  
Table 2. Selection Guide  
Description  
7C144-15  
7C145-15  
7C144-25  
7C145-25  
7C144-35  
7C145-35  
7C144-55  
7C145-55  
Unit  
Maximum Access Time  
15  
220  
60  
25  
180  
40  
35  
160  
30  
55  
160  
30  
ns  
Maximum Operating Current  
Maximum Standby Current for I  
mA  
mA  
SB1  
Document #: 38-06034 Rev. *D  
Page 3 of 21  
CY7C145, CY7C144  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Latch-Up Current.................................................... >200 mA  
Storage Temperature ..................................... −65°C to +150°C  
Ambient Temperature with  
Power Applied.................................................. −55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage to Ground Potential .................−0.5V to +7.0V  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
40°C to +85°C  
V
CC  
DC Voltage Applied to Outputs  
5V ± 10%  
in High Z State .....................................................−0.5V to +7.0V  
5V ± 10%  
DC Input Voltage ..............................................−0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
7C144-15  
7C145-15  
7C144-25  
7C145-25  
Parameter  
Description  
Test Conditions  
Unit  
Min  
Max  
Min Max  
V
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
Output Leakage Current  
Operating Current  
V
V
= Min., I = 4.0 mA  
2.4  
2.4  
V
V
OH  
OL  
IH  
CC  
OH  
V
V
V
I
= Min., I = 4.0 mA  
0.4  
0.4  
CC  
OL  
2.2  
2.2  
V
0.8  
+10  
+10  
220  
0.8  
+10  
+10  
180  
190  
40  
V
IL  
GND < V < V  
CC  
10  
10  
μA  
μA  
mA  
IX  
I
I
I
Outputs Disabled, GND < V < V  
CC  
10  
10  
OZ  
O
V
= Max., I = 0 mA  
OUT  
Commercial  
Industrial  
CC  
CC  
Outputs Disabled  
I
I
I
Standby Current  
(Both Ports TTL Levels)  
CE and CE > V ,  
Commercial  
Industrial  
60  
130  
15  
mA  
mA  
mA  
SB1  
SB2  
SB3  
L
R
IH  
f = f  
MAX  
50  
Standby Current  
(One Port TTL Level)  
CE or CE > V ,  
Commercial  
Industrial  
110  
120  
15  
L
R
IH  
f = f  
MAX  
Standby Current  
(Both Ports CMOS Levels) CE and CE > V – 0.2V,  
Both Ports  
Commercial  
Industrial  
R
CC  
30  
V
> V – 0.2V  
IN  
CC  
or V < 0.2V, f = 0  
IN  
I
Standby Current  
(One Port CMOS Level)  
One Port  
Commercial  
Industrial  
125  
100  
115  
mA  
SB4  
CE or CE > V – 0.2V,  
L
R
CC  
V
V
> V – 0.2V or  
IN  
IN  
CC  
< 0.2V, Active  
Port Outputs, f = f  
MAX  
Notes  
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.  
6. Pulse width < 20 ns.  
7.  
f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby  
MAX RC RC  
I
.
SB3  
Document #: 38-06034 Rev. *D  
Page 4 of 21  
       
CY7C145, CY7C144  
Electrical Characteristics Over the Operating Range (continued)  
7C144-35  
7C145-35  
7C144-55  
7C145-55  
Parameter  
Description  
Test Conditions  
Unit  
Min  
Max  
Min  
Max  
V
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
Output Leakage Current  
Operating Current  
V
V
= Min., I = 4.0 mA  
2.4  
2.4  
V
V
OH  
OL  
IH  
CC  
OH  
V
V
V
I
= Min., I = 4.0 mA  
0.4  
0.4  
CC  
OL  
2.2  
2.2  
V
0.8  
+10  
+10  
160  
180  
30  
0.8  
+10  
+10  
160  
180  
30  
V
IL  
GND < V < V  
CC  
10  
10  
μA  
μA  
mA  
IX  
I
I
I
Outputs Disabled, GND < V < V  
CC  
10  
10  
OZ  
O
V
= Max., I = 0 mA  
OUT  
Commercial  
Industrial  
CC  
CC  
Outputs Disabled  
I
I
I
Standby Current  
(Both Ports TTL Levels)  
CE and CE > V ,  
Commercial  
Industrial  
mA  
mA  
mA  
SB1  
SB2  
SB3  
L
R
IH  
f = f  
MAX  
40  
40  
Standby Current  
(One Port TTL Level)  
CE or CE > V ,  
Commercial  
Industrial  
100  
110  
15  
100  
110  
15  
L
R
IH  
f = f  
MAX  
Standby Current  
(Both Ports CMOS Levels) CE and CE > V – 0.2V,  
Both Ports  
Commercial  
Industrial  
R
CC  
30  
30  
V
> V – 0.2V  
IN  
CC  
or V < 0.2V, f = 0  
IN  
I
Standby Current  
(One Port CMOS Level)  
One Port  
Commercial  
Industrial  
90  
90  
mA  
SB4  
CE or CE > V – 0.2V,  
L
R
CC  
100  
100  
V
V
> V – 0.2V or  
IN  
IN  
CC  
< 0.2V, Active  
Port Outputs, f = f  
MAX  
Capacitance  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
10  
Unit  
pF  
C
IN  
A
V
= 5.0V  
CC  
C
15  
pF  
OUT  
Note:  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-06034 Rev. *D  
Page 5 of 21  
   
CY7C145, CY7C144  
Figure 4. AC Test Loads and Waveforms  
5V  
5V  
R1 = 893Ω  
R1 = 893Ω  
R
TH  
= 250Ω  
OUTPUT  
C = 30 pF  
OUTPUT  
C = 30pF  
OUTPUT  
C = 5 pF  
R = 347Ω  
R2 = 347Ω  
V
TH  
= 1.4V  
(a) Normal Load (Load1)  
(b) Thévenin Equivalent (Load 1)  
(c) Three-State Delay (Load 3)  
ALL INPUT PULSES  
OUTPUT  
3.0V  
GND  
90%  
90%  
10%  
10%  
C = 30 pF  
3 ns  
3 ns  
Load (Load 2)  
Switching Characteristics Over the Operating Range  
7C144-15  
7C145-15  
7C144-25  
7C145-25  
7C144-35  
7C145-35  
7C144-55  
7C145-55  
Parameter  
Description  
Unit  
Min  
15  
3
Max  
Min  
Max  
Min  
Max  
Min  
Max  
READ CYCLE  
tRC  
Read Cycle Time  
25  
3
35  
3
55  
3
ns  
ns  
ns  
t
t
Address to Data Valid  
15  
25  
35  
55  
AA  
Output Hold From Address  
Change  
OHA  
t
t
t
t
t
t
t
t
CE LOW to Data Valid  
OE LOW to Data Valid  
OE Low to Low Z  
15  
10  
25  
15  
35  
20  
55  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
DOE  
LZOE  
3
3
0
3
3
0
3
3
0
3
3
0
OE HIGH to High Z  
CE LOW to Low Z  
10  
10  
15  
15  
15  
25  
20  
20  
35  
25  
25  
55  
HZOE  
LZCE  
CE HIGH to High Z  
CE LOW to Power-Up  
CE HIGH to Power-Down  
HZCE  
PU  
PD  
WRITE CYCLE  
t
t
t
t
t
t
Write Cycle Time  
15  
12  
12  
2
25  
20  
20  
2
35  
30  
30  
2
55  
45  
45  
2
ns  
ns  
ns  
ns  
ns  
ns  
WC  
SCE  
AW  
HA  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold From Write End  
Address Set-Up to Write Start  
Write Pulse Width  
0
0
0
0
SA  
12  
20  
25  
40  
PWE  
Notes  
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
/I and 30-pF load capacitance.  
I
OI OH  
10. At any given temperature and voltage condition for any given device, t  
11. Test conditions used are Load 3.  
is less than t  
and t  
is less than t  
.
HZCE  
LZCE  
HZOE  
LZOE  
12. This parameter is guaranteed but not tested.  
Document #: 38-06034 Rev. *D  
Page 6 of 21  
           
CY7C145, CY7C144  
[9]  
Switching Characteristics Over the Operating Range (continued)  
7C144-15  
7C145-15  
7C144-25  
7C145-25  
7C144-35  
7C145-35  
7C144-55  
7C145-55  
Parameter  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
25  
0
Max  
t
t
t
t
t
t
Data Set-Up to Write End  
Data Hold From Write End  
R/W LOW to High Z  
10  
0
15  
0
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
SD  
HD  
[11,12]  
10  
15  
20  
25  
HZWE  
[11,12]  
R/W HIGH to Low Z  
3
3
3
3
LZWE  
Write Pulse to Data Delay  
30  
25  
50  
30  
60  
35  
70  
40  
WDD  
Write Data Valid to Read Data  
Valid  
DDD  
BUSY TIMING  
t
BUSY LOW from Address  
Match  
15  
15  
20  
20  
20  
20  
30  
30  
ns  
ns  
BLA  
t
BUSY HIGH from Address  
Mismatch  
BHA  
t
t
t
t
t
t
BUSY LOW from CE LOW  
BUSY HIGH from CE HIGH  
Port Set-Up for Priority  
15  
15  
20  
20  
20  
20  
30  
30  
ns  
ns  
ns  
ns  
ns  
ns  
BLC  
BHC  
PS  
5
0
5
0
5
0
5
0
R/W LOW after BUSY LOW  
R/W HIGH after BUSY HIGH  
WB  
13  
20  
30  
30  
WH  
BDD  
BUSY HIGH to Data Valid  
15  
25  
35  
55  
INTERRUPT TIMING  
t
t
INT Set Time  
15  
15  
25  
25  
25  
25  
35  
35  
ns  
ns  
INS  
INR  
INT Reset Time  
SEMAPHORE TIMING  
t
SEM Flag Update Pulse (OE  
or SEM)  
10  
10  
15  
20  
ns  
SOP  
t
t
SEM Flag Write to Read Time  
5
5
5
5
5
5
5
5
ns  
ns  
SWRD  
SEM Flag Contention  
Window  
SPS  
Notes  
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.  
14. Test conditions used are Load 2.  
Document #: 38-06034 Rev. *D  
Page 7 of 21  
       
CY7C145, CY7C144  
Switching Waveforms  
Figure 5. Read Cycle No. 1 (Either Port Address Access)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)  
SEM or CE  
OE  
t
HZCE  
t
ACE  
t
HZOE  
t
DOE  
t
LZOE  
t
LZCE  
DATA VALID  
DATA OUT  
t
PU  
t
PD  
I
CC  
I
SB  
Figure 7. Read Timing with Port-to-Port Delay (M/S=L)  
t
WC  
ADDRESS  
R
MATCH  
t
PWE  
R/W  
R
t
t
SD  
HD  
DATAIN  
VALID  
R
ADDRESS  
L
MATCH  
t
DDD  
DATA  
VALID  
OUTL  
t
WDD  
Notes  
15. R/W is HIGH for read cycle.  
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.  
17. Address valid prior to or coincident with CE transition LOW.  
18. CE = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.  
L
19. BUSY = HIGH for the writing port.  
20. CE = CE = LOW.  
L
R
Document #: 38-06034 Rev. *D  
Page 8 of 21  
           
CY7C145, CY7C144  
Switching Waveforms (continued)  
Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)  
t
WC  
ADDRESS  
t
SCE  
SEM OR CE  
t
t
HA  
AW  
t
PWE  
R/W  
t
SA  
t
t
HD  
SD  
DATA IN  
DATA VALID  
OE  
t
t
HZOE  
LZOE  
HIGH IMPEDANCE  
DATA OUT  
Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)  
t
WC  
ADDRESS  
t
t
HA  
SCE  
SEM OR CE  
R/W  
t
AW  
t
SA  
t
PWE  
t
t
HD  
SD  
DATAVALID  
DATA IN  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
Notes  
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal  
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t  
or (t  
+ t ) to allow the I/O drivers to turn off and data to  
HZWE SD  
PWE  
be placed on the bus for the required t . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write  
SD  
pulse can be as short as the specified t  
.
PWE  
23. R/W must be HIGH during all address transitions.  
24. Data I/O pins enter high impedance when OE is held LOW during write.  
Document #: 38-06034 Rev. *D  
Page 9 of 21  
         
CY7C145, CY7C144  
Switching Waveforms (continued)  
Figure 10. Semaphore Read After Write Timing, Either Side  
t
AA  
t
OHA  
A A  
0
VALID ADDRESS  
VALID ADDRESS  
2
t
AW  
t
ACE  
t
HA  
SEM  
t
t
SOP  
SCE  
t
SD  
I/O  
0
DATA VALID  
DATA  
VALID  
IN  
OUT  
t
HD  
t
t
PWE  
SA  
R/W  
OE  
t
t
DOE  
SWRD  
t
SOP  
WRITE CYCLE  
READ CYCLE  
Figure 11. Semaphore Contention  
A A  
0L 2L  
MATCH  
R/W  
L
SEM  
L
t
SPS  
A A  
0R 2R  
MATCH  
R/W  
R
SEM  
R
Notes  
25. CE = HIGH for the duration of the above timing (both write and read cycle).  
26. I/O = I/O = LOW (request semaphore); CE = CE = HIGH  
0R  
0L  
R
L
27. Semaphores are reset (available to both ports) at cycle start.  
28. If t is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.  
SPS  
Document #: 38-06034 Rev. *D  
Page 10 of 21  
       
CY7C145, CY7C144  
Switching Waveforms (continued)  
Figure 12. Read with BUSY (M/S=HIGH)  
t
WC  
ADDRESS  
R
MATCH  
t
PWE  
R/W  
R
t
t
HD  
SD  
DATAIN  
VALID  
R
t
PS  
ADDRESS  
L
MATCH  
t
BLA  
t
BHA  
BUSY  
L
t
BDD  
t
DDD  
DATA  
VALID  
OUTL  
t
WDD  
Figure 13. Write Timing with Busy Input (M/S=LOW)  
t
PWE  
R/W  
t
t
WH  
WB  
BUSY  
Document #: 38-06034 Rev. *D  
Page 11 of 21  
CY7C145, CY7C144  
Switching Waveforms (continued)  
Figure 14. Busy Timing Diagram No. 1 (CE Arbitration)  
CE Valid First:  
L
ADDRESSL,R  
ADDRESS MATCH  
CE  
L
t
PS  
CE  
R
t
t
BHC  
BLC  
BUSY  
R
CE Valid First:  
R
ADDRESSL,R  
ADDRESS MATCH  
CE  
R
t
PS  
CE  
L
t
t
BHC  
BLC  
BUSY  
L
Figure 15. Busy Timing Diagram No. 2 (Address Arbitration)  
Left Address Valid First:  
t
or t  
WC  
RC  
ADDRESS  
L
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
ADDRESS  
BUSY  
R
R
t
t
BHA  
BLA  
Right Address Valid First:  
t
or t  
WC  
RC  
ADDRESS  
R
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
ADDRESS  
L
t
t
BHA  
BLA  
BUSY  
L
Note:  
29. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted  
PS  
Document #: 38-06034 Rev. *D  
Page 12 of 21  
 
CY7C145, CY7C144  
Switching Waveforms (continued)  
Figure 16. Interrupt Timing Diagrams  
Left Side Sets INT :  
R
t
WC  
ADDRESS  
WRITE 1FFF  
L
t
HA  
CE  
L
L
R/W  
INT  
R
t
INS  
Right Side Clears INT :  
R
t
RC  
ADDRESS  
READ 1FFF  
R
CE  
R
t
INR  
R/W  
OE  
R
R
INT  
R
Right Side Sets INT :  
L
t
WC  
ADDRESS  
WRITE 1FFE  
R
t
HA  
CE  
R
R
R/W  
INT  
L
t
INS  
Left Side Clears INT :  
L
t
RC  
ADDRESS  
READ 1FFE  
R
CE  
L
t
INR  
R/W  
L
OE  
L
INT  
L
Notes  
30. t depends on which enable pin (CE or R/W ) is deasserted first.  
HA  
L
L
31. t  
or t  
depends on which enable pin (CE or R/W ) is asserted last.  
INS  
INR  
L
L
Document #: 38-06034 Rev. *D  
Page 13 of 21  
   
CY7C145, CY7C144  
Master/Slave  
Architecture  
An M/S pin is provided in order to expand the word width by  
configuring the device as either a master or a slave. The BUSY  
output of the master is connected to the BUSY input of the  
slave. This enables the device to interface to a master device  
with no external components.Writing of slave devices must be  
delayed until after the BUSY input has settled. Otherwise, the  
slave chip may begin a write cycle during a contention  
situation.When presented a HIGH input, the M/S pin allows the  
device to be used as a master and therefore the BUSY line is  
an output. BUSY can then be used to send the arbitration  
outcome to a slave.  
The CY7C144/5 consists of a an array of 8K words of 8/9 bits  
each of dual-port RAM cells, I/O and address lines, and control  
signals (CE, OE, R/W). These control pins permit independent  
access for reads or writes to any location in memory. To handle  
simultaneous writes or reads to the same location, a BUSY pin  
is provided on each port. Two interrupt (INT) pins can be used  
for port-to-port communication. Two semaphore (SEM) control  
pins are used for allocating shared resources. With the M/S  
pin, the CY7C144/5 can function as a Master (BUSY pins are  
outputs) or as a slave (BUSY pins are inputs). The CY7C144/5  
has an automatic power down feature controlled by CE. Each  
port is provided with its own output enable control (OE), which  
allows data to be read from the device.  
Semaphore Operation  
The CY7C144/5 provides eight semaphore latches which are  
separate from the dual-port memory locations. Semaphores  
are used to reserve resources that are shared between the two  
ports.The state of the semaphore indicates that a resource is  
in use. For example, if the left port wants to request a given  
resource, it sets a latch by writing a 0 to a semaphore location.  
The left port then verifies its success in setting the latch by  
reading it. After writing to the semaphore, SEM or OE must be  
Functional Description  
Write Operation  
Data must be set up for a duration of t before the rising edge  
SD  
of R/W to guarantee a valid write. A write operation is  
controlled by either the OE pin (see Figure 8 on page 9) or the  
R/W pin (see Write Cycle No. 2 waveform). Data can be written  
deasserted for t  
The semaphore value is available t  
before attempting to read the semaphore.  
SOP  
to the device t  
after the OE is deasserted or t  
after  
HZOE  
HZWE  
+ t  
after the rising  
SWRD  
DOE  
the falling edge of R/W. Required inputs for non-contention  
operations are summarized in Table 3.  
edge of the semaphore write. If the left port was successful  
(reads a 0), it assumes control over the shared resource,  
otherwise (reads a 1) it assumes the right port has control and  
continues to poll the semaphore.When the right side has relin-  
quished control of the semaphore (by writing a 1), the left side  
will succeed in gaining control of the semaphore. If the left side  
no longer requires the semaphore, a 1 is written to cancel its  
request.  
If a location is being written to by one port and the opposite  
port attempts to read that location, a port-to-port flowthrough  
delay must be met before the data is read on the output;  
otherwise the data read is not deterministic. Data will be valid  
on the port t  
after the data is presented on the other port.  
DDD  
Read Operation  
Semaphores are accessed by asserting SEM LOW. The SEM  
pin functions as a chip enable for the semaphore latches (CE  
When reading the device, the user must assert both the OE  
and CE pins. Data will be available t  
after CE or t  
after  
must remain HIGH during SEM LOW). A  
represents the  
ACE  
DOE  
0–2  
OE are asserted. If the user of the CY7C144/5 wishes to  
access a semaphore flag, then the SEM pin must be asserted  
instead of the CE pin.  
semaphore address. OE and R/W are used in the same  
manner as a normal memory access.When writing or reading  
a semaphore, the other address pins have no effect.  
When writing to the semaphore, only I/O is used. If a 0 is  
0
Interrupts  
written to the left port of an unused semaphore, a 1 appears  
at the same semaphore address on the right port. That  
semaphore can now only be modified by the side showing 0  
(the left port in this case). If the left port now relinquishes  
control by writing a 1 to the semaphore, the semaphore will be  
set to 1 for both sides. However, if the right port had requested  
the semaphore (written a 0) while the left port had control, the  
right port would immediately own the semaphore as soon as  
the left port released it. Table 5 shows sample semaphore  
operations.  
The interrupt flag (INT) permits communications between  
ports.When the left port writes to location 1FFF, the right port’s  
interrupt flag (INT ) is set. This flag is cleared when the right  
R
port reads that same location. Setting the left port’s interrupt  
flag (INT ) is accomplished when the right port writes to  
L
location 1FFE. This flag is cleared when the left port reads  
location 1FFE. The message at 1FFF or 1FFE is user-defined.  
See Table 4 for input requirements for INT. INT and INT are  
push-pull outputs and do not require pull-up resistors to  
operate.  
R
L
When reading a semaphore, all eight/nine data lines output the  
semaphore value. The read value is latched in an output  
register to prevent the semaphore from changing state during  
a write from the other port. If both ports attempt to access the  
Busy  
The CY7C144/5 provides on-chip arbitration to alleviate simul-  
taneous memory location access (contention). If both ports’  
CEs are asserted and an address match occurs within t of  
semaphore within t  
of each other, the semaphore is  
SPS  
definitely obtained by one side or the other, but there is no  
guarantee which side controls the semaphore.  
PS  
each other the Busy logic determines which port has access.  
If t is violated, one port will definitely gain permission to the  
PS  
Initialization of the semaphore is not automatic and must be  
reset during initialization program at power up. All  
Semaphores on both sides should have a one written into  
them at initialization from both sides to assure that they are  
free when needed.  
location, but it is not guaranteed which one. BUSY will be  
asserted t  
after an address match or t  
after CE is taken  
BLA  
BLC  
LOW. BUSY and BUSY in master mode are push-pull  
outputs and do not require pull-up resistors to operate.  
L
R
Document #: 38-06034 Rev. *D  
Page 14 of 21  
CY7C145, CY7C144  
Table 3. Non-Contending Read/Write  
Inputs  
Outputs  
I/O  
CE  
H
R/W  
X
OE  
X
SEM  
Operation  
07/8  
H
L
High Z  
Power-Down  
H
H
L
Data Out  
High Z  
Read Data in Semaphore  
I/O Lines Disabled  
X
X
H
X
L
H
X
Data In  
Write to Semaphore  
L
L
L
H
L
L
X
X
H
H
L
Data Out  
Data In  
Read  
Write  
X
Illegal Condition  
Table 4. Interrupt Operation Example (assumes BUSY = BUSY = HIGH)  
L
R
Function  
Left Port  
Right Port  
R/W  
X
CE  
X
OE  
X
A
INT  
L
R/W  
L
CE  
L
OE  
X
A
INT  
X
012  
012  
Set Left INT  
X
1FFE  
X
Reset Left INT  
Set Right INT  
X
L
L
1FFE  
1FFF  
X
H
X
L
L
X
L
L
X
X
X
X
X
X
L
Reset Right INT  
X
X
X
X
X
L
L
1FFF  
H
Table 5. Semaphore Operation Example  
Function I/O  
Left  
I/O  
Right  
Status  
0-7/8  
0-7/8  
No action  
1
1
Semaphore free  
Left port writes semaphore  
0
0
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
Left port obtains semaphore  
Right side is denied access  
Right port writes 0 to semaphore  
Left port writes 1 to semaphore  
Left port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 1 to semaphore  
Right port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 0 to semaphore  
Left port writes 1 to semaphore  
Right port is granted access to semaphore  
No change. Left port is denied access  
Left port obtains semaphore  
No port accessing semaphore address  
Right port obtains semaphore  
No port accessing semaphore  
Left port obtains semaphore  
No port accessing semaphore  
Document #: 38-06034 Rev. *D  
Page 15 of 21  
     
CY7C145, CY7C144  
Figure 17. Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
200  
1.4  
1.2  
1.0  
0.8  
1.2  
1.0  
ICC  
ICC  
160  
120  
80  
ISB3  
0.8  
0.6  
0.4  
ISB3  
VCC = 5.0V  
TA = 25°C  
VCC = 5.0V  
VIN = 5.0V  
0.6  
0.4  
40  
0
0.2  
0.6  
0.2  
0.0  
5.0  
55  
25  
125  
0
1.0  
2.0  
3.0  
4.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
1.1  
100  
80  
1.2  
1.0  
60  
TA = 25°C  
VCC = 5.0V  
1.0  
40  
0.8  
V
CC = 5.0V  
20  
0
0.9  
0.8  
TA = 25°C  
0.6  
55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
5.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
TYPICAL POWER-ON CURRENT  
vs. SUPPLY VOLTAGE  
TYPICAL ACCESS TIME CHANGE  
vs. OUTPUT LOADING  
NORMALIZED ICC vs. CYCLE TIME  
1.25  
30.0  
25.0  
1.00  
V
CC = 5.0V  
TA = 25°C  
VIN = 5.0V  
0.75  
0.50  
1.0  
20.0  
15.0  
10.0  
0.75  
0.25  
0.0  
VCC = 4.5V  
TA = 25°C  
5.0  
0
0.50  
40  
10  
28  
66  
0
1.0  
2.0  
3.0  
4.0 5.0  
0
200 400 600 800 1000  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
SUPPLY VOLTAGE (V)  
Document #: 38-06034 Rev. *D  
Page 16 of 21  
CY7C145, CY7C144  
Ordering Information  
8K x8 Dual-Port SRAM  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
64-Pin Thin Quad Flat Pack  
15  
CY7C144-15AC  
CY7C144-15AXC  
CY7C144-15JC  
CY7C144-15JXC  
CY7C144-15AI  
CY7C144-15JXI  
CY7C144-15AXI  
CY7C144-25AC  
CY7C144-25AXC  
CY7C144-25JC  
CY7C144-25AI  
CY7C144-25JI  
CY7C144-35AC  
CY7C144-35JC  
CY7C144-35AI  
CY7C144-35JI  
CY7C144-55AC  
CY7C144-55AXC  
CY7C144-55JC  
CY7C144-55JXC  
CY7C144-55AI  
CY7C144-55JI  
A65  
A65  
J81  
J81  
A65  
J81  
A65  
A65  
A65  
J81  
A65  
J81  
A65  
J81  
A65  
J81  
A65  
A65  
J81  
J81  
A65  
J81  
Commercial  
64-Pin Pb-Free Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
68-Pin Pb-Free Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
Industrial  
68-Pin Pb-Free Plastic Leaded Chip Carrier  
64-Pin Pb-Free Thin Quad Flat Pack  
64-Pin Thin Quad Flat Pack  
25  
Commercial  
64-Pin Pb-Free Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
35  
55  
Commercial  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
Commercial  
64-Pin Pb-Free Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
68-Pin Pb-Free Plastic Leaded Chip Carrier  
64-Pin Thin Quad Flat Pack  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
Document #: 38-06034 Rev. *D  
Page 17 of 21  
CY7C145, CY7C144  
8K x9 Dual-Port SRAM  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
80-Pin Thin Quad Flat Pack  
15  
CY7C145-15AC  
CY7C145-15AXC  
CY7C145-15JC  
CY7C145-25AC  
CY7C145-25JC  
CY7C145-25AI  
CY7C145-25JI  
CY7C145-35AC  
CY7C145-35JC  
CY7C145-35JXC  
CY7C145-35AI  
CY7C145-35JI  
CY7C145-55AC  
CY7C145-55JC  
CY7C145-55AI  
CY7C145-55JI  
A80  
A80  
J81  
A80  
J81  
A80  
J81  
A80  
J81  
J81  
A80  
J81  
A80  
J81  
A80  
J81  
Commercial  
80-Pin Pb-Free Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
25  
35  
Commercial  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
Commercial  
68-Pin Plastic Leaded Chip Carrier  
68-Pin Pb-Free Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
55  
Commercial  
Industrial  
68-Pin Plastic Leaded Chip Carrier  
80-Pin Thin Quad Flat Pack  
68-Pin Plastic Leaded Chip Carrier  
Document #: 38-06034 Rev. *D  
Page 18 of 21  
CY7C145, CY7C144  
Package Diagrams  
Figure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 (51-85046)  
51-85046-*C  
Document #: 38-06034 Rev. *D  
Page 19 of 21  
CY7C145, CY7C144  
Figure 19. 80-Pin Thin Plastic Quad Flat Pack A80 (51-85065)  
Figure 20. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005)  
51-85005-*A  
Document #: 38-06034 Rev. *D  
Page 20 of 21  
CY7C145, CY7C144  
Document History Page  
Document Title: CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy  
Document Number: 38-06034  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
110175  
122285  
236752  
SZV  
RBI  
09/29/01 Change from Spec number: 38-00163 to 38-06034  
*A  
*B  
12/27/02 Power up requirements added to Maximum Ratings Information  
YDT  
See ECN Removed cross information from features section, added CY7C144-15AI to  
ordering information section  
*C  
393320  
YIM  
See ECN Added Pb-Free Logo  
Added Pb-Free parts to ordering information:  
CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC,  
CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC  
*D  
2623658  
VKN/PYRS  
12/17/08 Added CY7C144-15JXI in the Ordering information table  
Sales, Solutions and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-06034 Rev. *D  
Revised December 10, 2008  
Page 21 of 21  
All products and company names mentioned in this document may be the trademarks of their respective holders.  

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