Cypress CY7C1344H User Manual

CY7C1344H  
2-Mbit (64K x 36) Flow-Through Sync SRAM  
Features  
Functional Description[1]  
The CY7C1344H is a 64K x 36 synchronous cache RAM  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
• 64K x 36 common I/O  
• 3.3V core power supply  
• 3.3V/2.5V I/O supply  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
— 8.0 ns (100-MHz version)  
• Provide high-performance 2-1-1-1 access rate  
(CE ), depth-expansion Chip Enables (CE and CE ), Burst  
1
2
3
®
Control inputs (ADSC, ADSP,  
ADV), Write Enables  
and BWE , and Global Write (GW). Asynchronous  
and  
• User-selectable burst counter supporting Intel  
®
BW  
(
)
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
[A:D]  
inputs include the Output Enable (OE) and the ZZ pin.  
The CY7C1344H allows either interleaved or linear burst  
sequences, selected by the MODE input pin. A HIGH selects  
an interleaved burst sequence, while a LOW selects a linear  
burst sequence. Burst accesses can be initiated with the  
Processor Address Strobe (ADSP) or the cache Controller  
Address Strobe (ADSC) inputs. Address advancement is  
controlled by the Address Advancement (ADV) input.  
• Asynchronous output enable  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
package  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
The CY7C1344H operates from a +3.3V core power supply  
while all outputs may operate with either a +3.3V/2.5V supply.  
All  
inputs  
and  
outputs  
are  
JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A[1:0]  
MODE  
ADV  
CLK  
Q1  
BURST  
COUNTER  
AND LOGIC  
Q0  
CLR  
ADSC  
ADSP  
DQD DQPD  
,
DQD  
BYTE  
WRITE REGISTER  
,
DQPD  
BYTE  
BWD  
WRITE REGISTER  
DQC DQPC  
,
DQC DQPC  
,
BYTE  
BWC  
BYTE  
WRITE REGISTER  
OUTPUT  
BUFFERS  
DQs  
WRITE REGISTER  
MEMORY  
ARRAY  
SENSE  
AMPS  
DQPA  
DQPB  
DQPC  
DQPD  
DQB DQPB  
,
DQB DQPB  
,
BYTE  
BWB  
BYTE  
WRITE REGISTER  
WRITE REGISTER  
DQA, DQPA  
BYTE  
DQA DQPA  
,
BWA  
BWE  
WRITE REGISTER  
BYTE  
WRITE REGISTER  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
CE1  
CE2  
CE3  
OE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-00211 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 26, 2006  
CY7C1344H  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the  
feed the 2-bit  
A0, A1,  
A
Input-  
Synchronous CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A  
1
2
3
[1:0]  
counter.  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.  
Synchronous Sampled on the rising edge of CLK.  
BW ,  
Input-  
A
BW  
B
BW ,  
C
BW  
D
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global  
Synchronous Write is conducted (ALL bytes are written, regardless of the values on BW  
and BWE).  
[A:D]  
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted  
Synchronous LOW to conduct a Byte Write.  
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst  
counter when ADV is asserted LOW, during a burst operation.  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE  
2
1
Synchronous and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only when a  
3
1
1
new external address is loaded.  
CE  
CE  
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE  
2
1
1
Synchronous and CE to select/deselect the device. CE  
is sampled only when a new external address is loaded.  
3
2
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE  
3
Synchronous and CE to select/deselect the device. CE is sampled only when a new external address is loaded.  
2
3
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,  
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data  
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-  
Synchronous ments the address in a burst cycle.  
ADSP  
Input-  
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted  
Synchronous LOW, addresses presented to the device are captured in the address registers. A  
are also loaded  
[1:0]  
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is  
ignored when CE is deasserted HIGH  
1
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted  
ADSC  
ZZ  
Synchronous LOW, addresses presented to the device are captured in the address registers. A  
are also loaded  
[1:0]  
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”  
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ  
pin has an internal pull-down.  
DQs  
DQP  
DQP  
DQP  
DQP  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the  
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the  
addresses presented during the previous clock rise of the Read cycle. The direction of the pins is  
A,  
B
controlled by  
DQP  
. When  
is asserted LOW, the pins behave as outputs. When HIGH, DQs and  
OE  
OE  
are placed in a tri-state condition.  
C,  
D
[A:D]  
V
Power  
Supply  
Power supply inputs to the core of the device.  
DD  
V
V
Ground  
Ground for the core of the device.  
SS  
I/O Power Power supply for the I/O circuitry.  
Supply  
DDQ  
V
I/O Ground Ground for the I/O circuitry.  
SSQ  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left floating  
DD  
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.  
Mode pin has an internal pull-up.  
NC  
No Connects. Not Internally connected to the die. 4M, 9M,1 8M, 72M, 144M, 288M, 576M, and 1G are  
address expansion pins and are not internally connected to the die.  
Document #: 001-00211 Rev. *B  
Page 3 of 15  
CY7C1344H  
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted  
HIGH, and (4) the Write input signals (GW, BWE, and  
BW[A:D]) indicate a write access. ADSC is ignored if ADSP is  
active LOW.  
Functional Overview  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. Maximum access delay from  
the clock rise (t  
) is 6.5 ns (133-MHz device).  
CDV  
The addresses presented are loaded into the address register  
and the burst counter/control logic and delivered to the  
memory core. The information presented to DQ[D:A] will be  
written into the specified address location. Byte Writes are  
allowed. During byte writes, BWA controls DQA, BWB controls  
DQB, BWC controls DQC, and BWD controls DQD. All I/Os  
are tri-stated when a Write is detected, even a Byte Write.  
Since this is a common I/O device, the asynchronous OE input  
signal must be deasserted and the I/Os must be tri-stated prior  
to the presentation of data to DQs. As a safety precaution, the  
data lines are tri-stated once a Write cycle is detected,  
regardless of the state of OE.  
The CY7C1344H supports secondary cache in systems  
utilizing either a linear or interleaved burst sequence. The  
interleaved burst order supports Pentium and i486™  
processors. The linear burst sequence is suited for processors  
that utilize a linear burst sequence. The burst order is  
user-selectable, and is determined by sampling the MODE  
input. Accesses can be initiated with either the Processor  
Address Strobe (ADSP) or the Controller Address Strobe  
(ADSC). Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
Burst Sequences  
The CY7C1344H provides an on-chip two-bit wraparound  
burst counter inside the SRAM. The burst counter is fed by  
A[1:0], and can follow either a linear or interleaved burst order.  
The burst order is determined by the state of the MODE input.  
A LOW on MODE will select a linear burst sequence. A HIGH  
on MODE will select an interleaved burst order. Leaving  
MODE unconnected will cause the device to default to a inter-  
leaved burst sequence.  
Byte Write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write  
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All Writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE  
1
is HIGH.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CEs, ADSP, and ADSC must remain  
Single Read Accesses  
A single read access is initiated when the following conditions  
are satisfied at clock rise: (1) CE , CE , and CE are all  
1
2
3
asserted active, and (2) ADSP or ADSC is asserted LOW (if  
the access is initiated by ADSC, the write inputs must be  
deasserted during this first cycle). The address presented to  
the address inputs is latched into the address register and the  
burst counter/control logic and presented to the memory core.  
If the OE input is asserted LOW, the requested data will be  
inactive for the duration of t  
LOW.  
after the ZZ input returns  
ZZREC  
available at the data outputs a maximum to t  
after clock  
CDV  
rise. ADSP is ignored if CE is HIGH.  
1
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
Single Write Accesses Initiated by ADSP  
First  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) CE , CE , CE are all asserted  
Address  
A1, A0  
1
2
3
active, and (2) ADSP is asserted LOW. The addresses  
presented are loaded into the address register and the burst  
inputs (GW, BWE, and BW[A:D]) are ignored during this first  
clock cycle. If the write inputs are asserted active (see Write  
Cycle Descriptions table for appropriate states that indicate a  
Write) on the next clock rise, the appropriate data will be  
latched and written into the device. Byte Writes are allowed.  
During Byte Writes, BWA controls DQA and BWB controls  
DQB, BWC controls DQC, and BWD controls DQD. All I/Os  
are tri-stated during a Byte Write. Since this is a common I/O  
device, the asynchronous OE input signal must be deasserted  
and the I/Os must be tri-stated prior to the presentation of data  
to DQs. As a safety precaution, the data lines are tri-stated  
once a Write cycle is detected, regardless of the state of OE.  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Linear Burst Address Table (MODE = GND)  
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
A ,A  
A ,A  
A ,A  
A ,A  
1
0
1
0
1
0
1
0
00  
01  
10  
11  
01  
10  
11  
10  
11  
00  
11  
00  
01  
00  
01  
10  
Single Write Accesses Initiated by ADSC  
This write access is initiated when the following conditions are  
satisfied at clock rise: (1) CE , CE , and CE are all asserted  
1
2
3
Document #: 001-00211 Rev. *B  
Page 4 of 15  
CY7C1344H  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min.  
Max.  
Unit  
mA  
ns  
I
t
t
t
t
40  
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
2t  
ZZS  
DD  
CYC  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
ns  
0
ns  
RZZI  
Truth Table[2, 3, 4, 5, 6]  
Address  
Used  
Cycle Description  
CE CE CE  
3
ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
Deselected Cycle,  
Power-down1  
None  
None  
None  
None  
None  
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H  
L-H  
L-H  
L-H  
L-H  
Tri-State  
Deselected Cycle,  
Power-down  
L
L
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Deselected Cycle,  
Power-down  
X
L
L
Deselected Cycle,  
Power-down  
H
H
Deselected Cycle,  
Power-down  
X
Sleep Mode, Power-down  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
None  
External  
External  
External  
External  
External  
Next  
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
Q
L
L
L
H
X
L
Tri-State  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next  
L
H
L
Tri-State  
Next  
L
Q
Next  
L
H
X
X
L
Tri-State  
Next  
L
D
Next  
L
L
D
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State  
Q
H
X
X
Tri-State  
D
D
Write Cycle, Suspend Burst  
L
Notes:  
2. X = “Don't Care.” H =Logic HIGH, L =Logic LOW.  
3. WRITE = L when any one or more Byte Write Enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals  
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.  
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW  
. Writes may occur only on subsequent clocks  
[A: D]  
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a  
don't care for the remainder of the Write cycle.  
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE  
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 001-00211 Rev. *B  
Page 5 of 15  
CY7C1344H  
Truth Table for Read/Write[2, 3]  
Function  
GW  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
X
H
H
H
H
L
BW  
X
H
H
L
BW  
A
D
C
B
Read  
Read  
X
H
L
Write Byte (A, DQP )  
L
A
Write Byte (B, DQP )  
L
H
L
B
Write Bytes (B, A, DQP , DQP )  
L
L
A
B
Write Byte (C, DQP )  
L
H
H
L
H
L
C
Write Bytes (C, A, DQP , DQP )  
L
L
C
A
Write Bytes (C, B, DQP , DQP )  
L
L
H
L
C
B
Write Bytes (C, B, A, DQP , DQP , DQP )  
L
L
L
C
B
A
Write Byte (D, DQP )  
L
H
H
H
H
L
H
H
L
H
L
D
Write Bytes (D, A, DQP , DQP )  
L
L
D
A
Write Bytes (D, B, DQP , DQP )  
L
L
H
L
D
A
Write Bytes (D, B, A, DQP , DQP , DQP )  
L
L
L
D
B
A
Write Bytes (D, B, DQP , DQP )  
L
L
H
H
L
H
L
D
B
Write Bytes (D, B, A, DQP , DQP , DQP )  
L
L
L
D
C
A
Write Bytes (D, C, A, DQP , DQP , DQP )  
L
L
L
H
L
D
B
A
Write All Bytes  
Write All Bytes  
L
L
L
L
X
X
X
X
X
Document #: 001-00211 Rev. *B  
Page 6 of 15  
CY7C1344H  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
]
Range  
Temperature  
V
V
DDQ  
DD  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DDQ  
Commercial 0°C to +70°C 3.3V 5%/+10% 2.5V –5%  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
to V  
DD  
+ 0.5V  
Industrial  
–40°C to +85°C  
DDQ  
[7, 8]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
V
V
3.6  
DD  
for 3.3V I/O  
for 2.5V I/O  
V
V
DDQ  
DD  
2.625  
V
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = –4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
V
OL  
for 2.5V I/O, I = 1.0 mA  
OL  
[7]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
GND V V  
2.0  
1.7  
V
V
+ 0.3V  
DD  
DD  
+ 0.3V  
[7]  
Input LOW Voltage  
–0.3  
–0.3  
5  
0.8  
V
IL  
0.7  
5
Input Leakage Current  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE  
Input = V  
Input = V  
Input = V  
Input = V  
–30  
–5  
µA  
µA  
SS  
DD  
SS  
DD  
5
Input Current of ZZ  
µA  
30  
5
µA  
I
I
Output Leakage Current  
GND V V  
, Output Disabled  
–5  
µA  
OZ  
I
DDQ  
V
Operating Supply  
V = Max., I  
DD  
= 0 mA,  
7.5-ns cycle, 133 MHz  
10-ns cycle, 100 MHz  
225  
205  
90  
mA  
mA  
mA  
mA  
DD  
DD  
OUT  
Current  
f = f  
= 1/t  
MAX CYC  
I
I
I
I
Automatic CE Power-Down Max. V , Device Deselected, 7.5-ns cycle, 133 MHz  
DD  
Current—TTL Inputs  
SB1  
V
V or V V , f = f  
IN IH IN IL MAX,  
10-ns cycle, 100 MHz  
80  
inputs switching  
Automatic CE Power-Down Max. V , Device Deselected, All speeds  
Current—CMOS Inputs  
40  
mA  
SB2  
SB3  
SB4  
DD  
V
V – 0.3V or V 0.3V,  
IN DD IN  
f = 0, inputs static  
Automatic CE Power-Down Max. V , Device Deselected, 7.5-ns cycle, 133 MHz  
Current—CMOS Inputs  
75  
65  
mA  
mA  
DD  
V
f = f  
V  
– 0.3V or V 0.3V,  
IN  
DDQ IN  
10-ns cycle, 100 MHz  
, inputs switching  
MAX  
Automatic CE Power-Down Max. V , Device Deselected, All speeds  
45  
mA  
DD  
Current—TTL Inputs  
V
V – 0.3V or V 0.3V,  
IN DD IN  
f = 0, inputs static  
Notes:  
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
8. T  
: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 001-00211 Rev. *B  
Page 7 of 15  
CY7C1344H  
Capacitance[9]  
100 TQFP  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max.  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
5
5
5
IN  
A
V
= 3.3V.  
DD  
C
C
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
= 2.5V  
DDQ  
pF  
Thermal Resistance[9]  
100 TQFP  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test  
methods and procedures for measuring  
thermal impedance, per EIA/JESD51  
30.32  
°C/W  
JA  
Thermal Resistance  
(Junction to Case)  
6.85  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
GND  
5 pF  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R =1538Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.25V  
T
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Note:  
9. Tested initially and after any design or process change that may affect these parameters.  
Document #: 001-00211 Rev. *B  
Page 8 of 15  
CY7C1344H  
[10, 11]  
Switching Characteristics Over the Operating Range  
133 MHz  
100 MHz  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
[12]  
t
V
(Typical) to the First Access  
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
7.5  
2.5  
2.5  
10  
4.0  
4.0  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid after CLK Rise  
Data Output Hold after CLK Rise  
6.5  
8.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CDV  
DOH  
CLZ  
2.0  
0
2.0  
0
[13, 14, 15]  
Clock to Low-Z  
[13, 14, 15]  
Clock to High-Z  
3.5  
3.5  
3.5  
3.5  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[13, 14, 15]  
OE LOW to Output Low-Z  
0
0
[13, 14, 15]  
OE HIGH to Output High-Z  
3.5  
3.5  
Set-up Times  
t
t
t
t
t
t
Address Set-up before CLK Rise  
ADSP, ADSC Set-up before CLK Rise  
ADV Set-up before CLK Rise  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW  
Set-up before CLK Rise  
[A:D]  
Data Input Set-up before CLK Rise  
Chip Enable Set-up  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold after CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADSP, ADSC Hold after CLK Rise  
ADH  
WEH  
ADVH  
DH  
GW, BWE, BW  
Hold after CLK Rise  
[A:D]  
ADV Hold after CLK Rise  
Data Input Hold after CLK Rise  
Chip Enable Hold after CLK Rise  
CEH  
Notes:  
10. Timing reference level is 1.5V when V  
= 3.3V and 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
12. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation  
POWER  
DD  
can be initiated.  
13. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
14. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
15. This parameter is sampled and not 100% tested.  
Document #: 001-00211 Rev. *B  
Page 9 of 15  
CY7C1344H  
Timing Diagrams  
[16]  
Read Cycle Timing  
t
CYC  
t
CLK  
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
ADDRESS  
t
t
WES  
WEH  
GW, BWE,BW  
[A:D]  
Deselect Cycle  
t
t
CES  
CEH  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst.  
t
t
t
CDV  
OEV  
OELZ  
t
t
OEHZ  
CHZ  
t
DOH  
t
CLZ  
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A1)  
Data Out (Q)  
High-Z  
t
CDV  
Burst wraps around  
to its initial state  
Single READ  
BURST  
READ  
DON’T CARE  
UNDEFINED  
Note:  
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 001-00211 Rev. *B  
Page 10 of 15  
CY7C1344H  
Timing Diagrams (continued)  
[16, 17]  
Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst.  
t
t
t
ADH  
ADS  
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are ignored for first cycle when  
ADSP initiates burst.  
t
t
WEH  
WES  
BWE,  
BW[A:D]  
t
t
WEH  
WES  
GW  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
ADV suspends burst.  
OE  
t
t
DH  
DS  
Data in (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note:  
17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW  
LOW.  
[A:D]  
Document #: 001-00211 Rev. *B  
Page 11 of 15  
CY7C1344H  
Timing Diagrams (continued)  
[16, 18, 19]  
Read/Write Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
BWE, BW[A:D]  
CE  
t
t
WEH  
WES  
t
t
CEH  
CES  
ADV  
OE  
t
t
DH  
DS  
t
OELZ  
t
High-Z  
D(A3)  
D(A5)  
D(A6)  
Data In (D)  
t
OEHZ  
CDV  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back  
Back-to-Back READs  
Single WRITE  
BURST READ  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes:  
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.  
19. GW is HIGH.  
Document #: 001-00211 Rev. *B  
Page 12 of 15  
CY7C1344H  
Timing Diagrams (continued)  
[20, 21]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
21. DQs are in High-Z when exiting ZZ sleep mode.  
Document #: 001-00211 Rev. *B  
Page 13 of 15  
CY7C1344H  
Ordering Information  
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered”.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
133  
CY7C1344H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1344H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1344H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1344H-100AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
Industrial  
100  
Commercial  
Industrial  
Package Diagram  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
1.40 0.05  
14.00 0.10  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
0.25  
1. JEDEC STD REF MS-026  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 001-00211 Rev. *B  
Page 14 of 15  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1344H  
Document History Page  
Document Title: CY7C1344H 2-Mbit (64K x 36) Flow-Through Sync SRAM  
Document Number: 001-00211  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
347377  
428408  
See ECN  
See ECN  
PCI  
New Data Sheet  
*A  
NXR  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed Three-State to Tri-State.  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table.  
Modified test condition from V < V to V < V  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
Replaced Package Diagram of 51-85050 from *A to *B  
*B  
459347  
See ECN  
NXR  
Converted from Preliminary to Final  
Included 2.5V I/O option  
Updated the Ordering Information table.  
Document #: 001-00211 Rev. *B  
Page 15 of 15  

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