Cypress CY7C1318JV18 User Manual

CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
18-Mbit DDR-II SRAM 2-Word  
Burst Architecture  
Features  
Functional Description  
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)  
300 MHz clock for high bandwidth  
The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and  
CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs  
equipped with DDR-II architecture. The DDR-II consists of an  
SRAM core with advanced synchronous peripheral circuitry and  
a one-bit burst counter. Addresses for read and write are latched  
on alternate rising edges of the input (K) clock. Write data is  
registered on the rising edges of both K and K. Read data is  
driven on the rising edges of C and C if provided, or on the rising  
edge of K and K if C/C are not provided. Each address location  
is associated with two 8-bit words in the case of CY7C1316JV18  
and two 9-bit words in the case of CY7C1916JV18 that burst  
sequentially into or out of the device. The burst counter always  
starts with a ‘0’ internally in the case of CY7C1316JV18 and  
CY7C1916JV18. For CY7C1318JV18 and CY7C1320JV18, the  
burst counter takes in the least significant bit of the external  
address and bursts two 18-bit words (in the case of  
CY7C1318JV18) of two 36-bit words (in the case of  
CY7C1320JV18) sequentially into or out of the device.  
2-word burst for reducing address bus frequency  
Double Data Rate (DDR) interfaces  
(data transferred at 600 MHz) at 300 MHz  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
Echo clocks (CQ and CQ) simplify data capture in high-speed  
systems  
Synchronous internally self-timed writes  
DDR-II operates with 1.5 cycle read latency when the DLL is  
enabled  
Asynchronous inputs include an output impedance matching  
input (ZQ). Synchronous data outputs (Q, sharing the same  
physical pins as the data inputs, D) are tightly matched to the two  
output echo clocks CQ/CQ, eliminating the need to capture data  
separately from each individual DDR SRAM in the system  
design. Output data clocks (C/C) enable maximum system  
clocking and data synchronization flexibility.  
Operates similar to a DDR-I device with 1 cycle read latency in  
DLL off mode  
1.8V core power supply with HSTL inputs and outputs  
Variable drive HSTL output buffers  
Expanded HSTL output voltage (1.4V–V  
)
DD  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1 compatible test access port  
Delay Lock Loop (DLL) for accurate data placement  
Configurations  
CY7C1316JV18 – 2M x 8  
CY7C1916JV18 – 2M x 9  
CY7C1318JV18 – 1M x 18  
CY7C1320JV18 – 512K x 36  
Selection Guide  
Description  
Maximum Operating Frequency  
300 MHz  
300  
Unit  
MHz  
mA  
Maximum Operating Current  
x8  
x9  
610  
615  
x18  
x36  
655  
730  
Cypress Semiconductor Corporation  
Document Number: 001-15271 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 10, 2008  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Logic Block Diagram (CY7C1318JV18)  
Burst  
Logic  
A0  
Write  
Reg  
Write  
Reg  
20 19  
A
A
(19:0)  
Address  
Register  
(19:1)  
18  
LD  
K
K
Output  
R/W  
CLK  
Logic  
Gen.  
Control  
C
C
DOFF  
Read Data Reg.  
CQ  
CQ  
36  
18  
V
REF  
18  
18  
Reg.  
Reg.  
Reg.  
Control  
Logic  
R/W  
18  
18  
BWS  
DQ  
[1:0]  
[17:0]  
Logic Block Diagram (CY7C1320JV18)  
Burst  
Logic  
A0  
Write  
Reg  
Write  
Reg  
19 18  
A
A
(18:0)  
Address  
Register  
(18:1)  
36  
LD  
K
K
Output  
Logic  
Control  
CLK  
R/W  
Gen.  
C
C
DOFF  
Read Data Reg.  
CQ  
CQ  
72  
36  
V
REF  
36  
36  
Reg.  
Reg.  
Reg.  
Control  
Logic  
R/W  
36  
36  
BWS  
DQ  
[3:0]  
[35:0]  
Document Number: 001-15271 Rev. *B  
Page 3 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Pin Configuration  
[1]  
The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow.  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1316JV18 (2M x 8)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/72M  
NC  
3
4
R/W  
A
5
6
K
K
A
7
8
LD  
A
9
10  
NC/36M  
NC  
11  
CQ  
DQ3  
NC  
NC  
DQ2  
NC  
NC  
ZQ  
A
B
C
D
E
F
A
NWS  
NC/144M  
A
1
NC  
NC  
NC  
DQ4  
NC  
DQ5  
NC/288M  
A
NWS  
A
NC  
NC  
NC  
NC  
NC  
NC  
0
NC  
V
V
V
NC  
SS  
SS  
SS  
SS  
NC  
V
V
V
V
V
V
NC  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
NC  
V
V
V
V
V
V
V
V
V
V
NC  
G
H
J
NC  
NC  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
NC  
NC  
DQ1  
NC  
NC  
NC  
DQ0  
NC  
NC  
NC  
TDI  
K
L
NC  
NC  
NC  
NC  
DQ7  
A
NC  
NC  
NC  
NC  
NC  
A
DQ6  
NC  
V
V
V
V
NC  
SS  
SS  
SS  
SS  
M
N
P
R
V
V
NC  
SS  
SS  
SS  
NC  
V
A
A
A
A
C
C
A
A
A
V
NC  
SS  
NC  
A
A
A
A
NC  
TCK  
TMS  
CY7C1916JV18 (2M x 9)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/72M  
NC  
3
4
5
NC  
6
K
K
A
7
8
9
10  
NC/36M  
NC  
11  
CQ  
DQ3  
NC  
A
B
C
D
E
F
A
R/W  
A
NC/144M  
LD  
A
A
NC  
NC  
NC  
DQ4  
NC  
DQ5  
NC/288M  
A
BWS  
A
NC  
NC  
NC  
NC  
NC  
NC  
0
NC  
V
V
V
NC  
SS  
SS  
SS  
SS  
NC  
V
V
V
V
V
V
NC  
NC  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
DQ2  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
NC  
V
V
V
V
V
V
V
V
V
V
NC  
G
H
J
NC  
NC  
NC  
V
V
V
V
REF  
ZQ  
REF  
DDQ  
DDQ  
NC  
NC  
NC  
NC  
DQ1  
NC  
NC  
K
L
NC  
NC  
NC  
NC  
DQ7  
A
NC  
NC  
NC  
NC  
NC  
A
NC  
DQ6  
NC  
V
V
NC  
DQ0  
NC  
SS  
SS  
SS  
SS  
M
N
P
R
V
V
V
V
NC  
SS  
SS  
SS  
NC  
V
A
A
A
A
C
C
A
A
A
V
NC  
NC  
SS  
NC  
A
A
A
A
NC  
DQ8  
TDI  
TCK  
TMS  
Note  
1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.  
Document Number: 001-15271 Rev. *B  
Page 4 of 26  
 
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Pin Configuration  
[1]  
The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow.  
(continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1318JV18 (1M x 18)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
NC/72M  
DQ9  
NC  
3
4
R/W  
A
5
6
K
7
8
9
10  
NC/36M  
NC  
11  
CQ  
A
B
C
D
E
F
A
BWS  
NC/144M  
LD  
A
1
NC  
NC/288M  
A
K
BWS  
A
A
NC  
NC  
NC  
NC  
NC  
NC  
DQ8  
NC  
0
NC  
V
V
A0  
V
DQ7  
NC  
SS  
SS  
SS  
SS  
NC  
DQ10  
DQ11  
NC  
V
V
V
V
V
V
NC  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
DQ6  
DQ5  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQ12  
NC  
V
V
V
V
V
V
V
V
V
V
NC  
G
H
J
DQ13  
NC  
V
V
V
V
REF  
ZQ  
REF  
DDQ  
DDQ  
NC  
NC  
NC  
DQ14  
NC  
NC  
DQ4  
D3  
NC  
K
L
NC  
NC  
NC  
NC  
NC  
A
DQ3  
DQ2  
NC  
DQ15  
NC  
V
V
V
V
NC  
SS  
SS  
SS  
SS  
M
N
P
R
NC  
V
V
DQ1  
NC  
SS  
SS  
SS  
NC  
DQ16  
DQ17  
A
V
A
A
A
A
C
C
A
A
A
V
NC  
SS  
NC  
A
A
A
A
NC  
DQ0  
TDI  
TCK  
TMS  
CY7C1320JV18 (512K x 36)  
1
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
2
3
4
5
BWS  
BWS  
A
6
K
7
BWS  
BWS  
A
8
9
10  
NC/72M  
NC  
11  
A
B
C
D
E
F
NC/144M NC/36M  
R/W  
A
LD  
A
A
CQ  
2
3
1
0
DQ27  
NC  
DQ18  
DQ28  
DQ19  
DQ20  
DQ21  
DQ22  
K
NC  
NC  
NC  
NC  
NC  
NC  
DQ8  
DQ7  
DQ16  
DQ6  
DQ5  
DQ14  
ZQ  
V
V
A0  
V
DQ17  
NC  
SS  
SS  
SS  
SS  
DQ29  
NC  
V
V
V
V
V
V
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ15  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQ30  
DQ31  
V
V
V
V
V
V
V
V
V
V
G
H
J
NC  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
DQ32  
DQ23  
DQ24  
DQ34  
DQ25  
DQ26  
A
NC  
DQ13  
DQ12  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
DQ10  
DQ0  
TDI  
K
L
NC  
NC  
NC  
NC  
NC  
A
DQ33  
NC  
V
V
SS  
SS  
SS  
SS  
M
N
P
R
V
V
V
V
DQ11  
NC  
SS  
SS  
SS  
DQ35  
NC  
V
A
A
A
A
C
C
A
A
A
V
SS  
A
A
A
A
DQ9  
TMS  
TCK  
Document Number: 001-15271 Rev. *B  
Page 5 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Pin Definitions  
Pin Name  
DQ  
IO  
Pin Description  
Input Output- Data Input Output Signals. Sampled on the rising edge of K and K clocks during valid write operations.  
Synchronous These pins drive out the requested data during a read operation. Valid data is driven out on the rising  
edge of both the C and C clocks during read operations or K and K when in single clock mode. When  
[x:0]  
read access is deselected, Q  
are automatically tri-stated.  
[x:0]  
CY7C1316JV18 DQ  
[7:0]  
CY7C1916JV18 DQ  
[8:0]  
CY7C1318JV18 DQ  
[17:0]  
CY7C1320JV18 DQ  
[35:0]  
LD  
NWS ,  
Input-  
Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition  
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.  
Input-  
Nibble Write Select 0, 1 Active LOW (CY7C1316JV18 only). Sampled on the rising edge of the K and  
0
NWS  
Synchronous K clocks during write operations. Used to select which nibble is written into the device during the current  
portion of the write operations. Nibbles not written remain unaltered.  
1
NWS controls D  
and NWS controls D  
.
0
[3:0]  
1
[7:4]  
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select  
ignores the corresponding nibble of data and it is not written into the device.  
BWS ,  
Input-  
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during  
0
BWS ,  
Synchronous write operations. Used to select which byte is written into the device during the current portion of the Write  
operations. Bytes not written remain unaltered.  
1
BWS ,  
2
BWS  
CY7C1916JV18 BWS controls D  
3
0
[8:0]  
[8:0]  
CY7C1318JV18 BWS controls D  
and BWS controls D  
[17:9].  
0
1
CY7C1320JV18 BWS controls D  
[35:27]  
, BWS controls D  
, BWS controls D  
and BWS controls  
0
[8:0]  
1
[17:9]  
2
[26:18]  
3
D
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select  
ignores the corresponding byte of data and it is not written into the device.  
A, A0  
Input-  
Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the  
Synchronous device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316JV18 and 2M x 9 (2 arrays each  
of 1M x 9) for CY7C1916JV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1318JV18, and 512K x 36  
(2 arrays each of 256K x 36) for CY7C1320JV18.  
CY7C1316JV18 – Because the least significant bit of the address internally is a ‘0’, only 20 external  
address inputs are needed to access the entire memory array.  
CY7C1916JV18 – Because the least significant bit of the address internally is a ‘0’, only 20 external  
address inputs are needed to access the entire memory array.  
CY7C1318JV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.  
20 address inputs are needed to access the entire memory array.  
CY7C1320JV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.  
19 address inputs are needed to access the entire memory array. All the address inputs are ignored when  
the appropriate port is deselected.  
R/W  
C
Input-  
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when  
Synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times  
around the edge of K.  
Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from  
the device. C and C can be used together to deskew the flight times of various devices on the board back  
to the controller. See Application Example on page 9 for more information.  
C
Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from  
the device. C and C can be used together to deskew the flight times of various devices on the board back  
to the controller. See Application Example on page 9 for more information.  
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device  
and to drive out data through Q  
edge of K.  
when in single clock mode. All accesses are initiated on the rising  
[x:0]  
K
Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and  
to drive out data through Q when in single clock mode.  
[x:0]  
Document Number: 001-15271 Rev. *B  
Page 6 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Pin Definitions (continued)  
Pin Name  
IO  
Pin Description  
CQ  
Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock  
for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for  
the echo clocks is shown in Switching Characteristics on page 22.  
CQ  
ZQ  
Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock  
for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for  
the echo clocks is shown in Switching Characteristics on page 22.  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus  
impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor connected  
[x:0]  
between ZQ and ground. Alternatively, this pin can be connected directly to V  
, which enables the  
DDQ  
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.  
DOFF  
Input  
DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing  
in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this  
pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I  
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167  
MHz with DDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK Pin for JTAG.  
TDI  
TDI Pin for JTAG.  
TMS  
TMS Pin for JTAG.  
NC  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Not Connected to the Die. Can be tied to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC  
NC/36M  
NC/72M  
NC/144M  
NC/288M  
N/A  
N/A  
N/A  
N/A  
V
Input-  
REF  
Reference measurement points.  
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.  
DD  
Ground  
Ground for the Device.  
SS  
Power Supply Power Supply Inputs for the Outputs of the Device.  
DDQ  
Document Number: 001-15271 Rev. *B  
Page 7 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
mation presented to D  
is also stored into the write data  
are both asserted active. The 36 bits  
Functional Overview  
[17:0]  
register, provided BWS  
[1:0]  
of data are then written into the memory array at the specified  
location. Write accesses can be initiated on every rising edge of  
the positive input clock (K). This pipelines the data flow such that  
18 bits of data can be transferred into the device on every rising  
edge of the input clocks (K and K).  
The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and  
CY7C1320JV18 are synchronous pipelined Burst SRAMs  
equipped with a DDR interface, which operates with a read  
latency of one and half cycles when DOFF pin is tied HIGH.  
When DOFF pin is set LOW or connected to V the device  
SS  
behaves in DDR-I mode with a read latency of one clock cycle.  
When Write access is deselected, the device ignores all inputs  
after the pending write operations are completed.  
Accesses are initiated on the rising edge of the positive input  
clock (K). All synchronous input timing is referenced from the  
rising edge of the input clocks (K and K) and all output timing is  
referenced to the rising edge of the output clocks (C/C, or K/K  
when in single clock mode).  
Byte Write Operations  
Byte write operations are supported by the CY7C1318JV18. A  
write operation is initiated as described in the Write Operations  
section. The bytes that are written are determined by BWS and  
All synchronous data inputs (D  
) pass through input registers  
0
[x:0]  
BWS , which are sampled with each set of 18-bit data words.  
controlled by the rising edge of the input clocks (K and K). All  
synchronous data outputs (Q ) pass through output registers  
1
Asserting the byte write select input during the data portion of a  
write latches the data being presented and writes it into the  
device. Deasserting the Byte Write Select input during the data  
portion of a write enables the data stored in the device for that  
byte to remain unaltered. This feature can be used to simplify  
read/modify/write operations to a byte write operation.  
[x:0]  
controlled by the rising edge of the output clocks (C/C, or K/K  
when in single-clock mode).  
All synchronous control (R/W, LD, BWS  
input registers controlled by the rising edge of the input clock (K).  
) inputs pass through  
[0:X]  
CY7C1318JV18 is described in the following sections. The same  
basic descriptions apply to CY7C1316JV18, CY7C1916JV18,  
and CY7C1320JV18.  
Single Clock Mode  
The CY7C1318JV18 can be used with a single clock that  
controls both the input and output registers. In this mode the  
device recognizes only a single pair of input clocks (K and K) that  
control both the input and output registers. This operation is  
identical to the operation if the device had zero skew between  
the K/K and C/C clocks. All timing parameters remain the same  
in this mode. To use this mode of operation, tie C and C HIGH at  
power on. This function is a strap option and not alterable during  
device operation.  
Read Operations  
The CY7C1318JV18 is organized internally as two arrays of  
512K x 18. Accesses are completed in a burst of two sequential  
18-bit data words. Read operations are initiated by asserting  
R/W HIGH and LD LOW at the rising edge of the positive input  
clock (K). The address presented to address inputs is stored in  
the read address register and the least significant bit of the  
address is presented to the burst counter. The burst counter  
increments the address in a linear fashion. Following the next K  
clock rise, the corresponding 18-bit word of data from this  
DDR Operation  
The CY7C1318JV18 enables high-performance operation  
through high clock frequencies (achieved through pipelining) and  
double data rate mode of operation. The CY7C1318JV18  
requires a single No Operation (NOP) cycle during transition  
from a read to a write cycle. At higher frequencies, some appli-  
cations may require a second NOP cycle to avoid contention.  
address location is driven onto Q  
, using C as the output  
[17:0]  
timing reference. On the subsequent rising edge of C the next  
18-bit data word from the address location generated by the  
burst counter is driven onto Q  
. The requested data is valid  
[17:0]  
0.45 ns from the rising edge of the output clock (C or C, or K and  
K when in single clock mode, 200 MHz and 250 MHz device). To  
maintain the internal logic, each read access must be allowed to  
complete. Read accesses can be initiated on every rising edge  
of the positive input clock (K).  
If a read occurs after a write cycle, address and data for the write  
are stored in registers. The write information must be stored  
because the SRAM cannot perform the last word write to the  
array without conflicting with the read. The data stays in this  
register until the next write cycle occurs. On the first write cycle  
after the read(s), the stored data from the earlier write is written  
into the SRAM array. This is called a posted write.  
The CY7C1318JV18 first completes the pending read transac-  
tions, when read access is deselected. Synchronous internal  
circuitry automatically tri-states the output following the next  
rising edge of the positive output clock (C). This enables a  
seamless transition between devices without the insertion of wait  
states in a depth expanded memory.  
If a read is performed on the same address on which a write is  
performed in the previous cycle, the SRAM reads out the most  
current data. The SRAM does this by bypassing the memory  
array and reading the data from the registers.  
Write Operations  
Write operations are initiated by asserting R/W LOW and LD  
LOW at the rising edge of the positive input clock (K). The  
address presented to address inputs is stored in the write  
address register and the least significant bit of the address is  
presented to the burst counter. The burst counter increments the  
address in a linear fashion. On the following K clock rise the data  
Depth Expansion  
Depth expansion requires replicating the LD control signal for  
each bank. All other control signals can be common between  
banks as appropriate.  
Programmable Impedance  
presented to D  
is latched and stored into the 18-bit write  
[17:0]  
data register, provided BWS  
subsequent rising edge of the negative input clock (K) the infor-  
are both asserted active. On the  
An external resistor, RQ, must be connected between the ZQ pin  
[1:0]  
on the SRAM and V to enable the SRAM to adjust its output  
SS  
Document Number: 001-15271 Rev. *B  
Page 8 of 26  
 
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
driver impedance. The value of RQ must be 5x the value of the  
intended line impedance driven by the SRAM. The allowable  
range of RQ to guarantee impedance matching with a tolerance  
DLL  
These chips use a Delay Lock Loop (DLL) that is designed to  
function between 120 MHz and the specified maximum clock  
frequency. During power up, when the DOFF is tied HIGH, the  
DLL is locked after 1024 cycles of stable clock. The DLL can also  
be reset by slowing or stopping the input clocks K and K for a  
minimum of 30 ns. However, it is not necessary for the to specif-  
ically reset the DLL to lock it to the desired frequency. The DLL  
automatically locks 1024 clock cycles after a stable clock is  
presented. The DLL may be disabled by applying ground to the  
DOFF pin. When the DLL is turned off, the device behaves in  
DDR-I mode (with one cycle latency and a longer access time).  
For information refer to the application note DLL Considerations  
in QDRII™/DDRII.  
of ±15% is between 175Ω and 350Ω, with V  
= 1.5V. The  
DDQ  
output impedance is adjusted every 1024 cycles at power up to  
account for drifts in supply voltage and temperature.  
Echo Clocks  
Echo clocks are provided on the DDR-II to simplify data capture  
on high-speed systems. Two echo clocks are generated by the  
DDR-II. CQ is referenced with respect to C and CQ is referenced  
with respect to C. These are free running clocks and are synchro-  
nized to the output clock of the DDR-II. In the single clock mode,  
CQ is generated with respect to K and CQ is generated with  
Application Example  
Figure 1 shows two DDR-II used in an application.  
Figure 1. Application Example  
R = 250ohms  
R = 250ohms  
SRAM#2  
SRAM#1  
ZQ  
ZQ  
DQ  
A
DQ  
A
CQ/CQ#  
LD# R/W# C C# K K#  
CQ/CQ#  
LD# R/W# C C#  
K
K#  
DQ  
Addresses  
Cycle Start#  
R/W#  
Return CLK  
Source CLK  
Return CLK#  
Source CLK#  
BUS  
MASTER  
(CPU  
or  
Vterm = 0.75V  
R = 50ohms  
Vterm = 0.75V  
ASIC)  
Echo Clock1/Echo Clock#1  
Echo Clock2/Echo Clock#2  
Document Number: 001-15271 Rev. *B  
Page 9 of 26  
   
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Truth Table  
The truth table for the CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 follows.  
Operation  
K
LD  
R/W  
DQ  
DQ  
Write Cycle:  
Load address; wait one cycle;  
L-H  
L
L
D(A1) at K(t + 1) D(A2) at K(t + 1) ↑  
input write data on consecutive K and K rising edges.  
Read Cycle:  
Load address; wait one and a half cycle;  
read data on consecutive C and C rising edges.  
L-H  
L
H
Q(A1) at C(t + 1)Q(A2) at C(t + 2) ↑  
NOP: No Operation  
L-H  
H
X
X
X
High-Z  
High-Z  
Standby: Clock Stopped  
Stopped  
Previous State  
Previous State  
Burst Address Table  
(CY7C1318JV18, CY7C1320JV18)  
First Address (External)  
Second Address (Internal)  
X..X0  
X..X1  
X..X1  
X..X0  
Write Cycle Descriptions  
The write cycle description table for CY7C1316JV18 and CY7C1318JV18 follows.  
BWS / BWS /  
0
1
K
Comments  
K
NWS  
NWS  
1
0
L
L
L–H  
During the data portion of a write sequence:  
CY7C1316JV18 both nibbles (D  
) are written into the device.  
[7:0]  
CY7C1318JV18 both bytes (D  
) are written into the device.  
[17:0]  
L
L
L–H  
L-H During the data portion of a write sequence:  
CY7C1316JV18 both nibbles (D  
) are written into the device.  
[7:0]  
CY7C1318JV18 both bytes (D  
) are written into the device.  
[17:0]  
L
H
H
L
During the data portion of a write sequence:  
CY7C1316JV18 only the lower nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[17:9]  
[3:0]  
[7:4]  
CY7C1318JV18 only the lower byte (D  
[8:0]  
L
L–H During the data portion of a write sequence:  
CY7C1316JV18 only the lower nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1318JV18 only the lower byte (D  
[8:0]  
[17:9]  
H
H
L–H  
During the data portion of a write sequence:  
CY7C1316JV18 only the upper nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1318JV18 only the upper byte (D  
remains unaltered.  
[17:9]  
[8:0]  
L
L–H During the data portion of a write sequence:  
CY7C1316JV18 only the upper nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[7:4]  
[3:0]  
[8:0]  
CY7C1318JV18 only the upper byte (D  
[17:9]  
H
H
H
H
L–H  
No data is written into the devices during this portion of a write operation.  
L–H No data is written into the devices during this portion of a write operation.  
Notes  
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.  
3. Device powers up deselected with the outputs in a tri-state condition.  
4. On CY7C1318JV18 and CY7C1320JV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses  
sequence in the burst. On CY7C1316JV18 and CY7C1916JV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.  
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.  
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging  
symmetrically.  
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on  
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.  
Document Number: 001-15271 Rev. *B  
Page 10 of 26  
               
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Write Cycle Descriptions  
The write cycle description table for CY7C1916JV18 follows.  
BWS  
K
L–H  
K
Comments  
0
L
L
During the Data portion of a write sequence, the single byte (D  
) is written into the device.  
) is written into the device.  
[8:0]  
L–H During the Data portion of a write sequence, the single byte (D  
[8:0]  
H
H
L–H  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
Write Cycle Descriptions  
The write cycle description table for CY7C1320JV18 follows.  
[2, 8]  
BWS  
BWS  
BWS  
BWS  
3
K
K
Comments  
0
1
2
L
L
L
L
L–H  
During the Data portion of a write sequence, all four bytes (D  
the device.  
) are written into  
) are written into  
[35:0]  
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L–H  
L–H During the Data portion of a write sequence, all four bytes (D  
the device.  
[35:0]  
During the Data portion of a write sequence, only the lower byte (D  
) is written  
) is written  
[8:0]  
into the device. D  
remains unaltered.  
[35:9]  
L
L–H During the Data portion of a write sequence, only the lower byte (D  
into the device. D remains unaltered.  
[8:0]  
[35:9]  
H
H
H
H
H
H
L–H  
During the Data portion of a write sequence, only the byte (D  
) is written into  
[17:9]  
the device. D  
and D  
remains unaltered.  
[8:0]  
[35:18]  
L
L–H During the Data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
) is written into  
[17:9]  
[8:0]  
[35:18]  
H
H
H
H
L–H  
During the Data portion of a write sequence, only the byte (D  
) is written into  
) is written into  
) is written into  
) is written into  
[26:18]  
[26:18]  
[35:27]  
[35:27]  
the device. D  
and D  
remains unaltered.  
[17:0]  
[35:27]  
L
L–H During the Data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
[17:0]  
[35:27]  
H
H
L–H  
During the Data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
L
L–H During the Data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
H
H
H
H
H
H
H
H
L–H  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
Document Number: 001-15271 Rev. *B  
Page 11 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Instruction Register  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the TDI  
and TDO pins, as shown in TAP Controller Block Diagram on  
page 15. Upon power up, the instruction register is loaded with  
the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state, as described  
in the previous section.  
These SRAMs incorporate a serial boundary scan Test Access  
Port (TAP) in the FBGA package. This part is fully compliant with  
IEEE Standard #1149.1-2001. The TAP operates using JEDEC  
standard 1.8V IO logic levels.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
When the TAP controller is in the Capture-IR state, the two least  
significant bits are loaded with a binary “01” pattern to allow for  
fault isolation of the board level serial test path.  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternatively  
be connected to V through a pull up resistor. TDO must be left  
unconnected. Upon power up, the device comes up in a reset  
state, which does not interfere with the operation of the device.  
Bypass Register  
DD  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This enables shifting of data through the SRAM  
with minimal delay. The bypass register is set LOW (V ) when  
the BYPASS instruction is executed.  
Test Access Port—Test Clock  
The test clock is used only with the TAP controller. All inputs are  
captured on the rising edge of TCK. All outputs are driven from  
the falling edge of TCK.  
SS  
Boundary Scan Register  
Test Mode Select (TMS)  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several No Connect (NC) pins are also  
included in the scan register to reserve pins for higher density  
devices.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. This pin may be left  
unconnected if the TAP is not used. The pin is pulled up inter-  
nally, resulting in a logic HIGH level.  
The boundary scan register is loaded with the contents of the  
RAM input and output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and TDO  
pins when the controller is moved to the Shift-DR state. The  
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can  
be used to capture the contents of the input and output ring.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the registers  
and can be connected to the input of any of the registers. The  
register between TDI and TDO is chosen by the instruction that  
is loaded into the TAP instruction register. For information on  
loading the instruction register, see the TAP Controller State  
Diagram on page 14. TDI is internally pulled up and can be  
unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) on any register.  
The Boundary Scan Order on page 18 shows the order in which  
the bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected to  
TDI, and the LSB is connected to TDO.  
Identification (ID) Register  
Test Data-Out (TDO)  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired into  
the SRAM and can be shifted out when the TAP controller is in  
the Shift-DR state. The ID register has a vendor code and other  
The TDO output pin is used to serially clock data out from the  
registers. The output is active, depending upon the current state  
of the TAP state machine (see Instruction Codes on page 17).  
The output changes on the falling edge of TCK. TDO is  
connected to the least significant bit (LSB) of any register.  
Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (V ) for five rising  
TAP Instruction Set  
DD  
edges of TCK. This Reset does not affect the operation of the  
SRAM and can be performed while the SRAM is operating. At  
power up, the TAP is reset internally to ensure that TDO comes  
up in a high-Z state.  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in Instruction  
Codes on page 17. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in detail below.  
TAP Registers  
Instructions are loaded into the TAP controller during the Shift-IR  
state when the instruction register is placed between TDI and  
TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO pins. To execute  
the instruction once it is shifted in, the TAP controller must be  
moved into the Update-IR state.  
Registers are connected between the TDI and TDO pins to scan  
the data in and out of the SRAM test circuitry. Only one register  
can be selected at a time through the instruction registers. Data  
is serially loaded into the TDI pin on the rising edge of TCK. Data  
is output on the TDO pin on the falling edge of TCK.  
Document Number: 001-15271 Rev. *B  
Page 12 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
IDCODE  
PRELOAD places an initial data pattern at the latched parallel  
outputs of the boundary scan register cells before the selection  
of another boundary scan test operation.  
The IDCODE instruction loads a vendor-specific, 32-bit code into  
the instruction register. It also places the instruction register  
between the TDI and TDO pins and shifts the IDCODE out of the  
device when the TAP controller enters the Shift-DR state. The  
IDCODE instruction is loaded into the instruction register at  
The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required, that is, while the data  
captured is shifted out, the preloaded data can be shifted in.  
power up or whenever the TAP controller is given  
Test-Logic-Reset state.  
a
BYPASS  
When the BYPASS instruction is loaded in the instruction register  
and the TAP is placed in a Shift-DR state, the bypass register is  
placed between the TDI and TDO pins. The advantage of the  
BYPASS instruction is that it shortens the boundary scan path  
when multiple devices are connected together on a board.  
SAMPLE Z  
The SAMPLE Z instruction connects the boundary scan register  
between the TDI and TDO pins when the TAP controller is in a  
Shift-DR state. The SAMPLE Z command puts the output bus  
into a High-Z state until the next command is given during the  
Update IR state.  
EXTEST  
The EXTEST instruction drives the preloaded data out through  
the system output pins. This instruction also connects the  
boundary scan register for serial access between the TDI and  
TDO in the Shift-DR controller state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the input and output pins is captured  
in the boundary scan register.  
EXTEST OUTPUT BUS TRI-STATE  
IEEE Standard 1149.1 mandates that the TAP controller be able  
to put the output bus into a tri-state mode.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because there  
is a large difference in the clock frequencies, it is possible that  
during the Capture-DR state, an input or output undergoes a  
transition. The TAP may then try to capture a signal while in  
transition (metastable state). This does not harm the device, but  
there is no guarantee as to the value that is captured.  
Repeatable results may not be possible.  
The boundary scan register has a special bit located at bit #47.  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the Update-DR state in  
the TAP controller, it directly controls the state of the output  
(Q-bus) pins, when the EXTEST is entered as the current  
instruction. When HIGH, it enables the output buffers to drive the  
output bus. When LOW, this bit places the output bus into a  
High-Z condition.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture setup plus hold  
times (t and t ). The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock  
during a SAMPLE/PRELOAD instruction. If this is an issue, it is  
still possible to capture all other signals and simply ignore the  
value of the CK and CK captured in the boundary scan register.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that cell,  
during the Shift-DR state. During Update-DR, the value loaded  
into that shift-register cell latches into the preload register. When  
the EXTEST instruction is entered, this bit directly controls the  
output Q-bus pins. Note that this bit is pre-set HIGH to enable  
the output when the device is powered up, and also when the  
TAP controller is in the Test-Logic-Reset state.  
CS  
CH  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the boundary  
scan register between the TDI and TDO pins.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
Document Number: 001-15271 Rev. *B  
Page 13 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
TAP Controller State Diagram  
The state diagram for the TAP controller follows.  
[9]  
TEST-LOGIC  
1
RESET  
0
1
1
1
SELECT  
TEST-LOGIC/  
SELECT  
0
IR-SCAN  
IDLE  
DR-SCAN  
0
0
1
1
CAPTURE-DR  
0
CAPTURE-IR  
0
0
1
0
1
SHIFT-DR  
1
SHIFT-IR  
1
EXIT1-DR  
0
EXIT1-IR  
0
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-IR  
0
UPDATE-DR  
1
1
0
Note  
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document Number: 001-15271 Rev. *B  
Page 14 of 26  
   
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
TAP Controller Block Diagram  
0
Bypass Register  
2
1
1
1
0
0
0
Selection  
TDI  
Selection  
Circuitry  
TDO  
Instruction Register  
Circuitry  
31 30  
29  
.
.
2
Identification Register  
.
106  
.
.
.
2
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
= 2.0 mA  
Min  
1.4  
1.6  
Max  
Unit  
V
V
V
V
V
V
I
I
I
I
I
V
V
OH1  
OH2  
OL1  
OL2  
IH  
OH  
OH  
OL  
OL  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
= 100 μA  
= 2.0 mA  
0.4  
0.2  
V
= 100 μA  
V
0.65V  
V
+ 0.3  
V
DD  
DD  
Input LOW Voltage  
–0.3  
–5  
0.35V  
5
V
IL  
DD  
Input and Output Load Current  
GND V V  
DD  
μA  
X
I
Notes  
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.  
11. Overshoot: V (AC) < V + 0.85V (Pulse width less than t /2).  
/2), Undershoot: V (AC) > 1.5V (Pulse width less than t  
IH  
DDQ  
CYC  
IL  
CYC  
12. All Voltage referenced to Ground.  
Document Number: 001-15271 Rev. *B  
Page 15 of 26  
       
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
TAP AC Switching Characteristics  
Over the Operating Range  
Parameter  
Description  
Min  
Max  
Unit  
ns  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
TCYC  
TF  
20  
MHz  
ns  
20  
20  
TH  
TCK Clock LOW  
ns  
TL  
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
TAP Timing and Test Conditions  
Figure 2 shows the TAP timing and test conditions.  
Figure 2. TAP Timing and Test Conditions  
0.9V  
ALL INPUT PULSES  
1.8V  
50Ω  
0.9V  
TDO  
0V  
Z = 50  
Ω
0
C = 20 pF  
L
t
t
TH  
TL  
GND  
(a)  
Test Clock  
TCK  
t
TCYC  
t
TMSH  
t
TMSS  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data In  
TDI  
Test Data Out  
TDO  
t
TDOV  
t
TDOX  
Notes  
13. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
14. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.  
R
F
Document Number: 001-15271 Rev. *B  
Page 16 of 26  
     
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Identification Register Definitions  
Value  
Instruction Field  
Description  
CY7C1316JV18  
CY7C1916JV18  
001  
CY7C1318JV18  
001  
CY7C1320JV18  
Revision Number  
(31:29)  
001  
001  
Version number.  
Cypress Device ID 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of  
(28:12)  
SRAM.  
Cypress JEDEC ID  
(11:1)  
00000110100  
1
00000110100  
1
00000110100  
1
00000110100  
1
Allows unique  
identification of  
SRAM vendor.  
ID Register  
Presence (0)  
Indicates the  
presence of an ID  
register.  
Scan Register Sizes  
Register Name  
Bit Size  
Instruction  
Bypass  
3
1
ID  
32  
107  
Boundary Scan  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the input and output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI and TDO.  
This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the input and output contents. Places the boundary scan register between TDI and  
TDO. Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the input and output ring contents. Places the boundary scan register between TDI  
and TDO. Does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operation.  
Document Number: 001-15271 Rev. *B  
Page 17 of 26  
   
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
Bump ID  
10G  
9G  
Bit #  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
Bump ID  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
1H  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
84  
Bump ID  
2J  
1
6P  
85  
3K  
2
6N  
11F  
11G  
9F  
86  
3J  
3
7P  
87  
2K  
4
7N  
88  
1K  
5
7R  
10F  
11E  
10E  
10D  
9E  
89  
2L  
6
8R  
90  
3L  
7
8P  
91  
1M  
1L  
8
9R  
92  
9
11P  
10P  
10N  
9P  
93  
3N  
3M  
1N  
2M  
3P  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
10C  
11D  
9C  
94  
95  
96  
10M  
11N  
9M  
9D  
97  
11B  
11C  
9B  
98  
2N  
2P  
99  
9N  
100  
101  
102  
103  
104  
105  
106  
1P  
11L  
11M  
9L  
10B  
11A  
Internal  
9A  
3R  
4R  
4P  
10L  
11K  
10K  
9J  
5P  
8B  
5N  
5R  
7C  
3F  
6C  
1G  
1F  
9K  
8A  
10J  
11J  
11H  
7A  
3G  
2G  
1J  
7B  
6B  
Document Number: 001-15271 Rev. *B  
Page 18 of 26  
 
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
DLL Constraints  
Power Up Sequence in DDR-II SRAM  
DLL uses K clock as its synchronizing input. The input must  
have low phase jitter, which is specified as t  
DDR-II SRAMs must be powered up and initialized in a  
predefined manner to prevent undefined operations. During  
power up, when the DOFF is tied HIGH, the DLL is locked after  
1024 cycles of stable clock.  
.
KC Var  
The DLL functions at frequencies down to 120 MHz.  
If the input clock is unstable and the DLL is enabled, then the  
DLL may lock onto an incorrect frequency, causing unstable  
SRAM behavior. To avoid this, provide 1024 cycles stable clock  
to relock to the desired clock frequency.  
Power Up Sequence  
Apply power and drive DOFF LOW (all other inputs can be  
HIGH or LOW)  
Apply V before V  
DD  
DDQ  
Apply V  
before V  
or at the same time as V  
DDQ  
REF REF  
After the power and clock (K, K) are stable take DOFF HIGH  
The additional 1024 cycles of clocks are required for the DLL  
to lock.  
Power Up Waveforms  
K
K
Unstable Clock  
> 1024 Stable clock  
Stable)  
DDQ  
Start Normal  
Operation  
/
V
Clock Start (Clock Starts after V  
DD  
Stable (< +/- 0.1V DC per 50ns )  
/
/
V
VDDQ  
V
VDD  
DD  
DDQ  
Fix High (or tied to V  
DDQ  
)
DOFF  
Document Number: 001-15271 Rev. *B  
Page 19 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Current into Outputs (LOW) ........................................ 20 mA  
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V  
Latch up Current..................................................... >200 mA  
Maximum Ratings  
Exceeding maximum ratings may shorten the battery life of the  
device. User guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Ambient Temperature with Power Applied.... –10°C to +85°C  
Operating Range  
Ambient  
Range  
Commercial  
Industrial  
Temperature (T )  
V
V
DDQ  
Supply Voltage on V Relative to GND........–0.5V to +2.9V  
A
DD  
DD  
0°C to +70°C  
1.8 ± 0.1V  
1.4V to  
Supply Voltage on V  
Relative to GND.......–0.5V to +V  
DD  
DDQ  
V
DD  
–40°C to +85°C  
DC Applied to Outputs in High-Z .........0.5V to V  
+ 0.3V  
DDQ  
DC Input Voltage  
.............................. –0.5V to V + 0.3V  
DD  
Electrical Characteristics  
DC Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
1.7  
1.4  
Typ  
Max  
Unit  
V
1.8  
1.5  
1.9  
V
V
DD  
V
V
V
V
V
V
V
I
V
DD  
DDQ  
OH  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Note 16  
Note 17  
V
V
/2 – 0.12  
/2 – 0.12  
– 0.2  
V
V
/2 + 0.12  
/2 + 0.12  
V
DDQ  
DDQ  
DDQ  
V
OL  
DDQ  
I
I
= 0.1 mA, Nominal Impedance  
V
V
V
OH(LOW)  
OL(LOW)  
IH  
OH  
OL  
DDQ  
DDQ  
= 0.1 mA, Nominal Impedance  
V
0.2  
V
SS  
V
+ 0.1  
V
+ 0.3  
V
REF  
DDQ  
–0.3  
V
– 0.1  
V
IL  
REF  
Input Leakage Current  
Output Leakage Current  
Input Reference Voltage  
GND V V  
5  
5  
5
μA  
μA  
V
X
I
DDQ  
I
GND V V  
Output Disabled  
5
OZ  
I
DDQ,  
V
Typical Value = 0.75V  
0.68  
0.75  
0.95  
610  
615  
655  
730  
200  
200  
230  
295  
REF  
I
V
Operating Supply  
V
= Max,  
(x8)  
(x9)  
mA  
DD  
DD  
DD  
I
= 0 mA,  
OUT  
f = f  
= 1/t  
MAX  
CYC  
(x18)  
(x36)  
(x8)  
I
Automatic Power down  
Current  
Max V  
,
mA  
SB1  
DD  
Both Ports Deselected,  
(x9)  
V
V or V V  
IN  
IH  
IN  
IL  
(x18)  
(x36)  
f = f  
= 1/t  
, Inputs Static  
MAX  
CYC  
AC Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
V
V
+ 0.2  
IH  
IL  
REF  
V
V
– 0.2  
V
REF  
Notes  
15. Power up: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V  
< V .  
DD  
DD  
IH  
DD  
DDQ  
16. Outputs are impedance controlled. I = –(V  
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.  
OH  
DDQ  
17. Outputs are impedance controlled. I = (V  
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.  
OL  
DDQ  
18. V  
(min) = 0.68V or 0.46V  
, whichever is larger, V  
(max) = 0.95V or 0.54V  
, whichever is smaller.  
REF  
DDQ  
REF  
DDQ  
Document Number: 001-15271 Rev. *B  
Page 20 of 26  
         
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Capacitance  
Tested initially and after any design or process change that may affect these parameters.  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max  
Unit  
pF  
C
T = 25°C, f = 1 MHz, V = 1.8V, V = 1.5V  
DDQ  
5
6
7
IN  
A
DD  
C
C
Clock Input Capacitance  
Output Capacitance  
pF  
CLK  
O
pF  
Thermal Resistance  
Tested initially and after any design or process change that may affect these parameters.  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, in  
accordance with EIA/JESD51.  
28.51  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
5.91  
°C/W  
JC  
AC Test Loads and Waveforms  
V
REF = 0.75V  
0.75V  
VREF  
VREF  
0.75V  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
Z = 50Ω  
0
OUTPUT  
1.25V  
Device  
R = 50Ω  
L
0.75V  
Under  
Device  
Under  
0.25V  
Test  
5 pF  
VREF = 0.75V  
Slew Rate = 2 V/ns  
ZQ  
Test  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Notes  
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V  
= 0.75V, RQ = 250Ω, V  
= 1.5V, input pulse  
DDQ  
REF  
levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.  
OL OH  
Document Number: 001-15271 Rev. *B  
Page 21 of 26  
   
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Switching Characteristics  
Over the Operating Range  
300 MHz  
Unit  
Cypress Consortium  
Parameter Parameter  
Description  
Min Max  
t
t
t
t
t
t
V
(Typical) to the first Access  
1
ms  
ns  
ns  
ns  
ns  
POWER  
CYC  
DD  
t
t
t
t
t
K Clock and C Clock Cycle Time  
Input Clock (K/K and C/C) HIGH  
Input Clock (K/K and C/C) LOW  
3.30 8.4  
KHKH  
KHKL  
KLKH  
KHKH  
KHCH  
1.32  
1.32  
1.49  
KH  
KL  
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge)  
K/K Clock Rise toC/C Clock Rise (rising edge to rising edge)  
KHKH  
KHCH  
0.00 1.45 ns  
Setup Times  
t
t
t
t
t
t
t
t
Address Setup to K Clock Rise  
0.4  
0.4  
0.3  
0.3  
ns  
ns  
ns  
ns  
SA  
AVKH  
IVKH  
IVKH  
DVKH  
Control Setup to Clock (K, K) Rise (LD, R/W)  
SC  
Double Data Rate Control Setup to Clock (K, K) Rise (BWS , BWS , BWS , BWS )  
SCDDR  
SD  
0
1
2
3
D
Setup to Clock (K and K) Rise  
[X:0]  
Hold Times  
t
t
t
t
t
t
t
t
Address Hold after Clock (K and K) Rise  
0.4  
0.4  
ns  
ns  
ns  
ns  
HA  
KHAX  
KHIX  
KHIX  
KHDX  
Control Hold after Clock (K and K) Rise (LD, R/W)  
HC  
Double Data Rate Control Hold after Clock (K and K) Rise (BWS , BWS , BWS , BWS ) 0.3  
HCDDR  
HD  
0
1
2
3
D
Hold after Clock (K and K) Rise  
0.3  
[X:0]  
Output Times  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C/C Clock Rise (or K/K in single clock mode) to Data Valid  
0.45 ns  
ns  
0.45 ns  
ns  
0.27 ns  
CO  
CHQV  
Data Output Hold after Output C/C Clock Rise (Active to Active)  
C/C Clock Rise to Echo Clock Valid  
–0.45  
DOH  
CHQX  
CCQO  
CQOH  
CQD  
CHCQV  
CHCQX  
CQHQV  
CQHQX  
CQHCQL  
CQHCQH  
CHQZ  
Echo Clock Hold after C/C Clock Rise  
Echo Clock High to Data Valid  
–0.45  
Echo Clock High to Data Invalid  
–0.27  
1.24  
1.24  
ns  
ns  
ns  
CQDOH  
CQH  
Output Clock (CQ/CQ) HIGH  
CQ Clock Rise to CQ Clock Rise  
(rising edge to rising edge)  
CQHCQH  
CHZ  
Clock (C and C) Rise to High-Z (Active to High-Z)  
0.45 ns  
ns  
Clock (C and C) Rise to Low-Z  
–0.45  
CLZ  
CHQX1  
DLL Timing  
t
t
t
t
t
t
Clock Phase Jitter  
0.20 ns  
KC Var  
KC Var  
DLL Lock Time (K, C)  
K Static to DLL Reset  
1024  
30  
Cycles  
ns  
KC lock  
KC Reset  
KC lock  
KC Reset  
Notes  
20. This part has an internal voltage regulator; t  
is the time that the power is supplied above V minimum initially before a read or write operation can be initiated.  
POWER  
DD  
21. These parameters are extrapolated from the input timing parameters (t  
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t  
) is already  
KHKH  
KC Var  
included in the t  
). These parameters are only guaranteed by design and are not tested in production.  
KHKH  
22. t  
, t  
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.  
CHZ CLZ  
23. At any voltage and temperature t  
is less than t  
and t  
less than t  
.
CHZ  
CLZ  
CHZ  
CO  
Document Number: 001-15271 Rev. *B  
Page 22 of 26  
         
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Switching Waveforms  
Figure 3. Read/Write/Deselect Sequence  
READ  
2
READ  
3
NOP  
4
NOP  
5
WRITE  
6
WRITE  
7
READ  
8
NOP  
1
9
10  
K
t
t
t
t
KHKH  
KH  
KL  
CYC  
K
LD  
t
t
SC  
HC  
R/W  
A
A0  
A2  
A3  
A4  
A1  
t
HD  
t
t
t
HD  
SA  
HA  
t
t
SD  
SD  
DQ  
Q00 Q01 Q10 Q11  
D21 D30  
Q40 Q41  
D20  
D31  
t
CQDOH  
t
t
KHCH  
CLZ  
t
t
CHZ  
DOH  
t
CO  
t
CQD  
C
t
t
t
t
t
KHKH  
KHCH  
KH  
KL  
CYC  
C#  
t
CCQO  
t
CQOH  
CQ  
CQ#  
t
t
CQH  
t
CQHCQH  
CCQO  
t
CQOH  
DON’T CARE  
UNDEFINED  
Notes  
24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.  
25. Outputs are disabled (High-Z) one clock cycle after a NOP.  
26. In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.  
Document Number: 001-15271 Rev. *B  
Page 23 of 26  
     
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
300 CY7C1316JV18-300BZC  
CY7C1916JV18-300BZC  
CY7C1318JV18-300BZC  
CY7C1320JV18-300BZC  
CY7C1316JV18-300BZXC  
CY7C1916JV18-300BZXC  
CY7C1318JV18-300BZXC  
CY7C1320JV18-300BZXC  
CY7C1316JV18-300BZI  
CY7C1916JV18-300BZI  
CY7C1318JV18-300BZI  
CY7C1320JV18-300BZI  
CY7C1316JV18-300BZXI  
CY7C1916JV18-300BZXI  
CY7C1318JV18-300BZXI  
CY7C1320JV18-300BZXI  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Document Number: 001-15271 Rev. *B  
Page 24 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Package Diagram  
Figure 4. 165-ball FBGA (13 x 15 x 1.40 mm), 51-85180  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
PIN 1 CORNER  
-0.06  
Ø0.50 (165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
13.00 0.10  
B
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDEC REFERENCE : MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
Document Number: 001-15271 Rev. *B  
Page 25 of 26  
CY7C1316JV18, CY7C1916JV18  
CY7C1318JV18, CY7C1320JV18  
Document History Page  
Document Title: CY7C1316JV18/CY7C1916JV18/CY7C1318JV18/CY7C1320JV18, 18-Mbit DDR-II SRAM 2-Word  
Burst Architecture  
Document Number: 001-15271  
ISSUE  
DATE  
ORIG. OF  
CHANGE  
REV. ECN NO.  
DESCRIPTION OF CHANGE  
**  
1103944 See ECN VKN/KKVTMP New data sheet  
*A  
1423243 See ECN VKN/AESA Converted from preliminary to final  
Removed 250MHz and 200MHz  
Updated I /I specs  
DD SB  
Changed DLL minimum operating frequency from 80MHz to 120MHz  
Changed t  
max spec to 8.4ns  
CYC  
*B  
2189567 See ECN VKN/AESA Minor Change-Moved to the external web  
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-15271 Rev. *B  
Revised March 10, 2008  
Page 26 of 26  
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document  
are the trademarks of their respective holders.  

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