Cypress CY7C1292DV18 User Manual

CY7C1292DV18  
CY7C1294DV18  
9-Mbit QDR- II™ SRAM 2-Word  
Burst Architecture  
Features  
Functional Description  
• Separate Independent Read and Write data ports  
The CY7C1292DV18 and CY7C1294DV18 are 1.8V  
Synchronous Pipelined SRAMs, equipped with QDR™-II  
architecture. QDR-II architecture consists of two separate  
ports to access the memory array. The Read port has  
dedicated Data Outputs to support Read operations and the  
Write Port has dedicated Data Inputs to support Write opera-  
tions. QDR-II architecture has separate data inputs and data  
outputs to completely eliminate the need to “turn-around” the  
data bus required with common I/O devices. Access to each  
port is accomplished through a common address bus. The  
Read address is latched on the rising edge of the K clock and  
the Write address is latched on the rising edge of the K clock.  
Accesses to the QDR-II Read and Write ports are completely  
independent of one another. In order to maximize data  
throughput, both Read and Write ports are equipped with  
Double Data Rate (DDR) interfaces. Each address location is  
associated with two 18-bit words (CY7C1292DV18) or 36-bit  
words (CY7C1294DV18) that burst sequentially into or out of  
the device. Since data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K and  
C and C), memory bandwidth is maximized while simplifying  
system design by eliminating bus “turn-arounds.”  
— Supports concurrent transactions  
• 250-MHz clock for high bandwidth  
• 2-Word Burst on all accesses  
• Double Data Rate (DDR) interfaces on both Read and  
Write ports (data transferred at 500 MHz) @ 250 MHz  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Two input clocks for output data (C and C) to minimize  
clock-skew and flight-time mismatches  
• Echo clocks (CQ and CQ) simplify data capture in  
high-speed systems  
• Single multiplexed address input bus latches address  
inputs for both Read and Write ports  
• Separate Port Selects for depth expansion  
• Synchronous internally self-timed writes  
• Available in x 18 and x 36 configurations  
• Full data coherency, providing most current data  
Depth expansion is accomplished with Port Selects for each  
port. Port selects allow each port to operate independently.  
• Core V = 1.8V (±0.1V); I/O V  
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)  
• Offered in both lead-free and non-lead free packages  
= 1.4V to V  
DD  
DD  
DDQ  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
• Variable drive HSTL output buffers  
• JTAG 1149.1 compatible test access port  
• Delay Lock Loop (DLL) for accurate data placement  
Configurations  
CY7C1292DV18 – 512K x 18  
CY7C1294DV18 – 256K x 36  
Selection Guide  
250 MHz  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
250  
600  
550  
500  
Cypress Semiconductor Corporation  
Document #: 001-00350 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 20, 2006  
CY7C1292DV18  
CY7C1294DV18  
Pin Configurations  
165-ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1292DV18 (512K x 18)  
1
2
3
4
5
BWS1  
NC  
6
K
7
NC/288M  
BWS0  
A
8
RPS  
A
9
10  
11  
CQ  
Q8  
D8  
D7  
Q6  
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
NC/144M NC/36M  
WPS  
A
NC/18M NC/72M  
A
B
C
D
Q9  
NC  
D9  
NC  
NC  
NC  
NC  
Q7  
NC  
K
D10  
Q10  
VSS  
VSS  
A
A
VSS  
VSS  
D11  
VSS  
VSS  
VSS  
NC  
Q12  
D13  
VREF  
NC  
Q11  
D12  
Q13  
VDDQ  
D14  
Q14  
D15  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
D6  
NC  
NC  
VREF  
Q4  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
NC  
G
H
J
VDDQ  
NC  
DOFF  
NC  
NC  
NC  
NC  
NC  
D3  
K
L
Q15  
NC  
NC  
NC  
NC  
NC  
NC  
D17  
NC  
D16  
Q16  
Q17  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
NC  
NC  
NC  
Q1  
NC  
D0  
D2  
D1  
Q0  
M
N
P
C
A
A
A
A
A
A
A
A
A
TDO  
TCK  
A
TMS  
TDI  
R
C
CY7C1294DV18 (256K x 36)  
1
2
3
5
6
7
8
9
10  
11  
CQ  
Q8  
D8  
D7  
Q6  
4
WPS  
A
CQ  
Q27  
D27  
D28  
NC/288M NC/72M  
BWS2  
BWS3  
A
K
BWS1  
BWS0  
A
RPS  
A
NC/36M NC/144M  
A
B
C
D
Q18  
Q28  
D20  
D18  
D19  
Q19  
D17  
D16  
Q16  
Q17  
Q7  
K
VSS  
VSS  
NC/18M  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
D15  
Q29  
Q30  
D30  
D29  
Q21  
D22  
VREF  
Q31  
D32  
Q24  
Q20  
D21  
Q22  
VDDQ  
D23  
Q23  
D24  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
Q15  
D14  
D6  
Q14  
D13  
VREF  
Q4  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
Q13  
VDDQ  
D12  
G
H
J
DOFF  
D31  
Q32  
Q33  
Q12  
D11  
D3  
K
L
Q11  
D33  
D34  
Q35  
Q34  
D26  
D35  
D25  
Q25  
Q26  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
D10  
Q10  
Q9  
Q1  
D9  
D0  
D2  
D1  
Q0  
M
N
P
A
C
A
A
A
A
A
A
A
TDO  
TCK  
A
A
TMS  
TDI  
R
C
Document #: 001-00350 Rev. *A  
Page 3 of 23  
CY7C1292DV18  
CY7C1294DV18  
Pin Definitions  
Pin Name  
I/O  
Pin Description  
Data input signals, sampled on the rising edge of K and K clocks during valid write  
D
Input-  
[x:0]  
Synchronous operations.  
CY7C1292DV18 - D  
[17:0]  
[35:0]  
CY7C1294DV18 - D  
WPS  
Input-  
Synchronous active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the  
Write port will cause D to be ignored.  
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted  
[x:0]  
Input-  
Byte Write Select 0, 1, 2 and 3 active LOW. Sampled on the rising edge of the K and K clocks  
BWS , BWS ,  
0
1
3
Synchronous during Write operations. Used to select which byte is written into the device during the current  
portion of the Write operations. Bytes not written remain unaltered.  
BWS , BWS  
2
CY7C1292DV18 BWS controls D  
, BWS controls D  
.
0
[8:0]  
[8:0]  
1
[17:9]  
[17:9]  
CY7C1294DV18 BWS controls D  
, BWS controls D  
,BWS controls D  
and  
[26:18]  
0
1
2
BWS controls D  
3
[35:27].  
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write  
Select will cause the corresponding byte of data to be ignored and not written into the device.  
A
Input-  
Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address)  
Synchronous clocks during active Read and Write operations. These address inputs are multiplexed for both  
Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of  
256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18.  
Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18.  
These inputs are ignored when the appropriate port is deselected.  
Q
Outputs-  
Data Output signals. These pins drive out the requested data during a Read operation. Valid  
[x:0]  
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K  
and K when in single clock mode. When the Read port is deselected, Q  
tri-stated.  
are automatically  
[x:0]  
CY7C1292DV18 Q  
CY7C1294DV18 Q  
[17:0]  
[35:0]  
RPS  
Input-  
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When  
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected.  
When deselected, the pending access is allowed to complete and the output drivers are  
automatically tri-stated following the next rising edge of the C clock. Each read access consists  
of a burst of two sequential transfers.  
C
C
K
Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read  
data from the device. C and C can be used together to deskew the flight times of various devices  
on the board back to the controller. See application example for further details.  
Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read  
data from the device. C and C can be used together to deskew the flight times of various devices  
on the board back to the controller. See application example for further details.  
Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the  
device and to drive out data through Q  
when in single clock mode. All accesses are initiated  
[x:0]  
on the rising edge of K.  
K
Input-Clock Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being  
presented to the device and to drive out data through Q when in single clock mode.  
[x:0]  
CQ  
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the  
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with  
respect to K. The timings for the echo clocks are shown in the AC Timing table.  
CQ  
ZQ  
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the  
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with  
respect to K. The timings for the echo clocks are shown in the AC Timing table.  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the system  
data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a  
[x:0]  
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to  
, which enables the minimum impedance mode. This pin cannot be connected directly to  
V
DDQ  
GND or left unconnected.  
Document #: 001-00350 Rev. *A  
Page 4 of 23  
CY7C1292DV18  
CY7C1294DV18  
Pin Definitions (continued)  
Pin Name  
DOFF  
I/O  
Pin Description  
Input  
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.  
The timings in the DLL turned off operation will be different from those listed in this data sheet.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK pin for JTAG.  
TDI  
TDI pin for JTAG.  
TMS  
TMS pin for JTAG.  
NC  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and  
NC/18M  
NC/36M  
NC/72M  
NC/144M  
NC/288M  
N/A  
N/A  
N/A  
N/A  
N/A  
V
Input-  
REF  
Reference Outputs as well as AC measurement points.  
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
Ground  
Ground for the device.  
SS  
Power Supply Power supply inputs for the outputs of the device.  
DDQ  
Read Operations  
Functional Overview  
The CY7C1292DV18 is organized internally as 2 arrays of  
256K x 18. Accesses are completed in a burst of two  
sequential 18-bit data words. Read operations are initiated by  
asserting RPS active at the rising edge of the Positive Input  
Clock (K). The address is latched on the rising edge of the K  
Clock. The address presented to Address inputs is stored in  
the Read address register. Following the next K clock rise the  
corresponding lowest order 18-bit word of data is driven onto  
The CY7C1292DV18 and CY7C1294DV18 are synchronous  
pipelined Burst SRAMs equipped with both a Read port and a  
Write port. The Read port is dedicated to Read operations and  
the Write port is dedicated to Write operations. Data flows into  
the SRAM through the Write port and out through the Read  
port. These devices multiplex the address inputs in order to  
minimize the number of address pins required. By having  
separate Read and Write ports, the QDR-II completely elimi-  
nates the need to “turn-around” the data bus and avoids any  
possible data contention, thereby simplifying system design.  
Each access consists of two 18-bit data transfers in the case  
of CY7C1292DV18 and two 36-bit data transfers in the case  
of CY7C1294DV18 in one clock cycle.  
the Q  
using C as the output timing reference. On the  
[17:0]  
subsequent rising edge of C, the next 18-bit data word is  
driven onto the Q . The requested data will be valid 0.45  
[17:0]  
ns from the rising edge of the output clock (C and C or K and  
K when in single clock mode).  
Synchronous internal circuitry will automatically tri-state the  
outputs following the next rising edge of the Output Clocks  
(C/C). This will allow for a seamless transition between  
devices without the insertion of wait states in a depth  
expanded memory.  
Accesses for both ports are initiated on the rising edge of the  
positive Input Clock (K). All synchronous input timings are  
referenced from the rising edge of the input clocks (K and K)  
and all output timings are referenced to the rising edge of  
output clocks (C and C or K and K when in single clock mode).  
Write Operations  
All synchronous data inputs (D  
) inputs pass through input  
[x:0]  
registers controlled by the input clocks (K and K). All  
Write operations are initiated by asserting WPS active at the  
rising edge of the Positive Input Clock (K). On the same K  
synchronous data outputs (Q ) outputs pass through output  
[x:0]  
registers controlled by the rising edge of the output clocks (C  
and C or K and K when in single clock mode).  
clock rise, the data presented to D  
is latched and stored  
[17:0]  
into the lower 18-bit Write Data register provided BWS  
are  
[1:0]  
both asserted active. On the subsequent rising edge of the  
Negative Input Clock (K), the address is latched and the infor-  
All synchronous control (RPS, WPS, BWS  
through input registers controlled by the rising edge of the  
input clocks (K and K).  
) inputs pass  
[x:0]  
mation presented to D  
is stored into the Write Data  
are both asserted active. The 36  
[17:0]  
register provided BWS  
[1:0]  
CY7C1292DV18 is described in the following sections. The  
same basic descriptions apply to CY7C1294DV18.  
bits of data are then written into the memory array at the  
specified location. When deselected, the write port will ignore  
all inputs after the pending Write operations have been  
completed.  
Document #: 001-00350 Rev. *A  
Page 5 of 23  
CY7C1292DV18  
CY7C1294DV18  
Byte Write Operations  
Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ  
Byte Write operations are supported by the CY7C1292DV18.  
A Write operation is initiated as described in the Write Opera-  
tions section above. The bytes that are written are determined  
pin on the SRAM and V to allow the SRAM to adjust its  
SS  
output driver impedance. The value of RQ must be 5x the  
value of the intended line impedance driven by the SRAM. The  
allowable range of RQ to guarantee impedance matching with  
a tolerance of ±15% is between 175and 350, with  
by BWS and BWS , which are sampled with each 18-bit data  
0
1
word. Asserting the appropriate Byte Write Select input during  
the data portion of a Write will allow the data being presented  
to be latched and written into the device. Deasserting the Byte  
Write Select input during the data portion of a write will allow  
the data stored in the device for that byte to remain unaltered.  
This feature can be used to simplify Read/Modify/Write opera-  
tions to a Byte Write operation.  
V
= 1.5V.The output impedance is adjusted every 1024  
DDQ  
cycles upon power-up to account for drifts in supply voltage  
and temperature.  
Echo Clocks  
Echo clocks are provided on the QDR-II to simplify data  
capture on high-speed systems. Two echo clocks are  
generated by the QDR-II. CQ is referenced with respect to C  
and CQ is referenced with respect to C. These are  
free-running clocks and are synchronized to the output clock  
(C/C) of the QDR-II. In the single clock mode, CQ is generated  
with respect to K and CQ is generated with respect to K. The  
timings for the echo clocks are shown in the AC Timing table.  
Single Clock Mode  
The CY7C1292DV18 can be used with a single clock that  
controls both the input and output registers. In this mode, the  
device will recognize only a single pair of input clocks (K and  
K) that control both the input and output registers. This  
operation is identical to the operation if the device had zero  
skew between the K/K and C/C clocks. All timing parameters  
remain the same in this mode. To use this mode of operation,  
the user must tie C and C HIGH at power on. This function is  
a strap option and not alterable during device operation.  
DLL  
These chips utilize a Delay Lock Loop (DLL) that is designed  
to function between 80 MHz and the specified maximum clock  
frequency. During power-up, when the DOFF is tied HIGH, the  
DLL gets locked after 1024 cycles of stable clock. The DLL can  
also be reset by slowing or stopping the input clock K and K  
for a minimum of 30 ns. However, it is not necessary for the  
DLL to be specifically reset in order to lock the DLL to the  
desired frequency. The DLL will automatically lock 1024 clock  
cycles after a stable clock is presented.the DLL may be  
disabled by applying ground to the DOFF pin. For information  
refer to the application note “DLL Considerations in  
QDRII/DDRII/QDRII+/DDRII+”.  
Concurrent Transactions  
The Read and Write ports on the CY7C1292DV18 operate  
completely independently of one another. Since each port  
latches the address inputs on different clock edges, the user  
can Read or Write to any location, regardless of the trans-  
action on the other port. Also, reads and writes can be started  
in the same clock cycle. If the ports access the same location  
at the same time, the SRAM will deliver the most recent infor-  
mation associated with the specified address location. This  
includes forwarding data from a Write cycle that was initiated  
on the previous K clock rise.  
Depth Expansion  
The CY7C1292DV18 has a Port Select input for each port.  
This allows for easy depth expansion. Both Port Selects are  
sampled on the rising edge of the Positive Input Clock only (K).  
Each port select input can deselect the specified port.  
Deselecting a port will not affect the other port. All pending  
transactions (Read and Write) will be completed prior to the  
device being deselected.  
Document #: 001-00350 Rev. *A  
Page 6 of 23  
CY7C1292DV18  
CY7C1294DV18  
Application Example[1]  
R = 250οηµσ  
SRAM #1  
SRAM #4  
R = 250οηµσ  
ZQ  
CQ/CQ#  
Q
ZQ  
CQ/CQ#  
Q
R W  
R
P
S
#
B
W
S
W
B
W
S
Vt  
R
P
S
#
P
S
#
P
S
#
D
A
D
A
C
C#  
K
K#  
C
C#  
K
K#  
#
#
DATA IN  
DATA OUT  
Address  
RPS#  
WPS#  
BWS#  
CLKIN/CLKIN#  
Vt  
Vt  
R
BUS  
MASTER  
(CPU  
or  
Source K  
Source K#  
ASIC)  
Delayed K  
Delayed K#  
R
R = 50οηµσ  
Vt = Vddq/2  
Truth Table[2, 3, 4, 5, 6, 7]  
Operation  
K
RPS  
WPS  
DQ  
D(A + 0) at K(t) ↑  
DQ  
D(A + 1) at K(t) ↑  
Write Cycle:  
L-H  
L-H  
L-H  
X
L
Load address on the rising edge of K clock; input write  
data on K and K rising edges.  
Read Cycle:  
L
X
Q(A + 0) at C(t + 1)Q(A + 1) at C(t + 2) ↑  
Load address on the rising edge of K clock; wait one  
and a half cycle; read data on C and C rising edges.  
NOP: No Operation  
H
X
H
X
D = X,  
Q = High-Z  
D = X,  
Q = High-Z  
Standby: Clock Stopped  
Stopped  
Previous State  
Previous State  
[2, 8]  
Write Cycle Descriptions (CY7C1292DV18)  
BWS  
BWS  
K
L-H  
K
Comments  
During the Data portion of a Write sequence: both bytes (D  
0
1
L
L
L
L
L
) are written into the device.  
) are written into the device.  
[17:0]  
L-H During the Data portion of a Write sequence: both bytes (D  
[17:0]  
H
L-H  
During the Data portion of a Write sequence: only the lower byte (D  
) is written into the  
) is written into the  
) is written into the  
[8:0]  
device. D  
will remain unaltered.  
[17:9]  
L
H
H
H
L
L
L-H  
L-H During the Data portion of a Write sequence: only the lower byte (D  
device. D will remain unaltered.  
[8:0]  
[17:9]  
During the Data portion of a Write sequence: only the upper byte (D  
[17:9]  
device. D  
will remain unaltered.  
[8:0]  
L-H During the Data portion of a Write sequence: only the upper byte (D  
device. D will remain unaltered.  
) is written into the  
[17:9]  
[8:0]  
H
H
H
H
L-H  
No data is written into the devices during this portion of a Write operation.  
L-H No data is written into the devices during this portion of a Write operation.  
Notes:  
1. The above application shows four QDR-II being used.  
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, represents rising edge.  
3. Device will power-up deselected and the outputs in a tri-state condition.  
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.  
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.  
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line  
charging symmetrically.  
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS , NWS , BWS , BWS , BWS and BWS can be altered on different  
0
1
0
1
2
3
portions of a Write cycle, as long as the set-up and hold requirements are achieved.  
Document #: 001-00350 Rev. *A  
Page 7 of 23  
CY7C1292DV18  
CY7C1294DV18  
[2, 8]  
Write Cycle Descriptions (CY7C1294DV18)  
BWS BWS BWS BWS  
3
K
K
Comments  
0
1
2
L
L
L
L
L-H  
-
During the Data portion of a Write sequence, all four bytes (D  
into the device.  
) are written  
) are written  
[35:0]  
L
L
L
L
-
L-H  
-
L-H During the Data portion of a Write sequence, all four bytes (D  
into the device.  
[35:0]  
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
-
During the Data portion of a Write sequence, only the lower byte (D  
) is written  
) is written  
[8:0]  
[8:0]  
into the device. D  
will remain unaltered.  
[35:9]  
L
L-H During the Data portion of a Write sequence, only the lower byte (D  
into the device. D will remain unaltered.  
[35:9]  
H
H
H
H
H
H
L-H  
-
-
During the Data portion of a Write sequence, only the byte (D  
) is written into  
) is written into  
) is written into  
) is written into  
) is written into  
) is written into  
[17:9]  
the device. D  
and D  
will remain unaltered.  
[8:0]  
[35:18]  
L
L-H During the Data portion of a Write sequence, only the byte (D  
the device. D and D will remain unaltered.  
[17:9]  
[8:0]  
[35:18]  
H
H
H
H
L-H  
-
-
During the Data portion of a Write sequence, only the byte (D  
[26:18]  
[26:18]  
[35:27]  
[35:27]  
the device. D  
and D  
will remain unaltered.  
[17:0]  
[35:27]  
L
L-H During the Data portion of a Write sequence, only the byte (D  
the device. D and D will remain unaltered.  
[17:0]  
[35:27]  
H
H
L-H  
-
During the Data portion of a Write sequence, only the byte (D  
the device. D will remain unaltered.  
[26:0]  
L
L-H During the Data portion of a Write sequence, only the byte (D  
the device. D will remain unaltered.  
[26:0]  
H
H
H
H
H
H
H
H
L-H  
-
-
No data is written into the device during this portion of a Write operation.  
L-H No data is written into the device during this portion of a Write operation.  
Document #: 001-00350 Rev. *A  
Page 8 of 23  
CY7C1292DV18  
CY7C1294DV18  
Instruction Register  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO pins as shown in TAP Controller Block Diagram.  
Upon power-up, the instruction register is loaded with the  
IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
These SRAMs incorporate a serial boundary scan test access  
port (TAP) in the FBGA package. This part is fully compliant  
with IEEE Standard #1149.1-1900. The TAP operates using  
JEDEC standard 1.8V I/O logic levels.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
When the TAP controller is in the Capture IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board level serial test path.  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V  
through a pull-up resistor. TDO should  
DD  
Bypass Register  
be left unconnected. Upon power-up, the device will come up  
in a reset state which will not interfere with the operation of the  
device.  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
Test Access Port—Test Clock  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
Test Mode Select  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several no connect (NC) pins are  
also included in the scan register to reserve pins for higher  
density devices.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this pin unconnected if the TAP is not used. The pin is  
pulled up internally, resulting in a logic HIGH level.  
The boundary scan register is loaded with the contents of the  
RAM Input and Output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and  
TDO pins when the controller is moved to the Shift-DR state.  
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-  
tions can be used to capture the contents of the Input and  
Output ring.  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information on loading the instruction register, see the TAP  
Controller State Diagram. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) on any register.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
Test Data-Out (TDO)  
Identification (ID) Register  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine (see Instruction codes). The  
output changes on the falling edge of TCK. TDO is connected  
to the least significant bit (LSB) of any register.  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (VDD) for five  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating. At power-up, the TAP is reset internally to ensure  
that TDO comes up in a high-Z state.  
TAP Instruction Set  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the  
Instruction Code table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
TAP Registers  
Registers are connected between the TDI and TDO pins and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction registers. Data is serially loaded into the TDI pin  
on the rising edge of TCK. Data is output on the TDO pin on  
the falling edge of TCK.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO pins.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
Document #: 001-00350 Rev. *A  
Page 9 of 23  
CY7C1292DV18  
CY7C1294DV18  
IDCODE  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state. The IDCODE instruction  
is loaded into the instruction register upon power-up or  
whenever the TAP controller is given a test logic reset state.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
given during the “Update IR” state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
access between the TDI and TDO in the shift-DR controller  
state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
EXTEST OUTPUT BUS TRI-STATE  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
The boundary scan register has a special bit located at bit #47.  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the “Update-DR” state  
in the TAP controller, it will directly control the state of the  
output (Q-bus) pins, when the EXTEST is entered as the  
current instruction. When HIGH, it will enable the output  
buffers to drive the output bus. When LOW, this bit will place  
the output bus into a High-Z condition.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
will undergo a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This will not harm  
the device, but there is no guarantee as to the value that will  
be captured. Repeatable results may not be possible.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR”, the value  
loaded into that shift-register cell will latch into the preload  
register. When the EXTEST instruction is entered, this bit will  
directly control the output Q-bus pins. Note that this bit is  
pre-set LOW to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
Reserved  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins.  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
prior to the selection of another boundary scan test operation.  
Document #: 001-00350 Rev. *A  
Page 10 of 23  
CY7C1292DV18  
CY7C1294DV18  
TAP Controller State Diagram[9]  
TEST-LOGIC  
1
RESET  
0
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
1
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note:  
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document #: 001-00350 Rev. *A  
Page 11 of 23  
CY7C1292DV18  
CY7C1294DV18  
TAP Controller Block Diagram  
0
Bypass Register  
Selection  
Circuitry  
Selection  
Circuitry  
2
1
1
0
TDO  
TDI  
Instruction Register  
29  
31 30  
.
.
2
0
0
Identification Register  
106  
.
.
.
.
2
1
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
[10, 11, 12]  
TAP Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
= 2.0 mA  
= 100 µA  
= 2.0 mA  
Min.  
1.4  
Max.  
Unit  
V
V
V
V
V
V
V
I
I
I
I
I
OH1  
OH2  
OL1  
OL2  
IH  
OH  
OH  
OL  
OL  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
1.6  
V
0.4  
0.2  
V
= 100 µA  
V
0.65V  
V
+ 0.3  
V
DD  
DD  
Input LOW Voltage  
–0.3  
0.35V  
5
V
IL  
DD  
Input and OutputLoad Current  
GND V V  
DD  
5  
µA  
X
I
Notes:  
10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.  
11. Overshoot: V (AC) < V +0.85V (Pulse width less than t /2), Undershoot: V (AC) > –1.5V (Pulse width less than t /2).  
IH  
DDQ  
CYC  
IL  
CYC  
12. All voltage referenced to Ground.  
Document #: 001-00350 Rev. *A  
Page 12 of 23  
CY7C1292DV18  
CY7C1294DV18  
[13, 14]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Description  
Min.  
Max.  
Unit  
ns  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
TCYC  
TF  
20  
MHz  
ns  
20  
20  
TH  
TCK Clock LOW  
ns  
TL  
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
TAP Timing and Test Conditions[13]  
0.9V  
50Ω  
ALL INPUT PULSES  
0.9V  
1.8V  
TDO  
Z = 50Ω  
0
0V  
C = 20 pF  
L
t
t
TL  
TH  
GND  
(a)  
t
TCYC  
Test Clock  
TCK  
t
TMSS  
t
TMSH  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data-In  
TDI  
Test Data-Out  
TDO  
t
TDOV  
t
TDOX  
Notes:  
13. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.  
R
F
14. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
Document #: 001-00350 Rev. *A  
Page 13 of 23  
CY7C1292DV18  
CY7C1294DV18  
Identification Register Definitions  
Value  
Instruction Field  
CY7C1292DV18  
CY7C1294DV18  
Description  
Revision Number (31:29)  
Cypress Device ID (28:12)  
Cypress JEDEC ID (11:1)  
ID Register Presence (0)  
000  
11010011010010110  
00000110100  
1
000  
11010011010100110  
00000110100  
1
Version number.  
Defines the type of SRAM.  
Unique identification of SRAM vendor.  
Indicates the presence of an ID register.  
Scan Register Sizes  
Register Name  
Instruction  
Bit Size  
3
1
Bypass  
ID  
32  
107  
Boundary Scan Cells  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the Input/Output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between  
TDI and TDO. This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the Input/Output contents. Places the boundary scan register  
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the Input/Output ring contents. Places the boundary scan register  
between TDI and TDO. Does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not  
affect SRAM operation.  
Document #: 001-00350 Rev. *A  
Page 14 of 23  
CY7C1292DV18  
CY7C1294DV18  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Bump ID  
11H  
10G  
9G  
Bit #  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Bump ID  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
1H  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
81  
Bump ID  
3G  
2G  
1J  
1
6P  
82  
2
6N  
83  
3
7P  
11F  
11G  
9F  
84  
2J  
4
7N  
85  
3K  
3J  
5
7R  
86  
6
8R  
10F  
11E  
10E  
10D  
9E  
87  
2K  
1K  
2L  
7
8P  
88  
8
9R  
89  
9
11P  
10P  
10N  
9P  
90  
3L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
91  
1M  
1L  
10C  
11D  
9C  
92  
93  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
10M  
11N  
9M  
94  
9D  
95  
11B  
11C  
9B  
96  
9N  
97  
11L  
11M  
9L  
98  
10B  
11A  
Internal  
9A  
99  
100  
101  
102  
103  
104  
105  
106  
10L  
11K  
10K  
9J  
8B  
7C  
9K  
6C  
3F  
10J  
11J  
8A  
1G  
1F  
7A  
Document #: 001-00350 Rev. *A  
Page 15 of 23  
CY7C1292DV18  
CY7C1294DV18  
Power-Up Sequence in QDR-II SRAM[16]  
QDR-II SRAMs must be powered up and initialized in a  
predefined manner to prevent undefined operations.  
DLL Constraints  
• DLL uses K clock as its synchronizing input. The input  
should have low phase jitter, which is specified as t  
.
KC Var  
• The DLL will function at frequencies down to 80 MHz.  
Power-Up Sequence  
• If the input clock is unstable and the DLL is enabled, then  
the DLL may lock onto an incorrect frequency, causing  
unstable SRAM behavior. To avoid this, provide 1024 cycles  
stable clock to relock to the desired clock frequency.  
• Apply power with DOFF tied HIGH (All other inputs can be  
HIGH or LOW)  
— Apply V before V  
DD  
DDQ  
— Apply V  
before V  
or at the same time as V  
REF REF  
DDQ  
• Provide stable power and clock (K, K) for 1024 cycles to  
lock the DLL.  
Power-up Waveforms  
K
K
Unstable Clock  
> 1024 Stable clock  
Start Normal  
Operation  
/
V
Clock Start (Clock Starts after V  
Stable)  
DDQ  
DD  
Stable (< +/- 0.1V DC per 50ns )  
/
/
V
DDQ  
VDDQ  
V
DD  
VDD  
Fix High (or tied to V  
)
DDQ  
DOFF  
Notes:  
15. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1Kohm.  
16. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.  
Document #: 001-00350 Rev. *A  
Page 16 of 23  
CY7C1292DV18  
CY7C1294DV18  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired.)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +2.9V  
Ambient  
DD  
[19]  
[19]  
V
DDQ  
Range Temperature (T )  
V
A
DD  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DDQ  
Com’l  
Ind’l  
0°C to +70°C  
1.8 ± 0.1 V  
1.4V to V  
DD  
DC Voltage Applied to Outputs  
in High-Z State .................................... –0.5V to V  
+ 0.3V  
–40°C to +85°C  
DDQ  
[11]  
DC Input Voltage ...............................–0.5V to V + 0.3V  
DD  
[12, 19]  
Electrical Characteristics Over the Operating Range  
DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
1.7  
Typ.  
1.8  
Max.  
Unit  
V
V
V
V
V
V
V
V
V
I
1.9  
DD  
1.4  
1.5  
V
V
DDQ  
OH  
DD  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Note 17  
Note 18  
V
V
/2 – 0.12  
/2 – 0.12  
– 0.2  
V
V
/2 + 0.12  
/2 + 0.12  
V
DDQ  
DDQ  
V
OL  
DDQ  
DDQ  
I
= 0.1 mA, Nominal Impedance  
V
V
V
OH(LOW)  
OL(LOW)  
IH  
OH  
DDQ  
DDQ  
I
= 0.1 mA, Nominal Impedance  
V
0.2  
+0.3  
DDQ  
V
OL  
SS  
[11]  
Input HIGH Voltage  
V
+ 0.1  
V
V
REF  
[11]  
Input LOW Voltage  
–0.3  
V
– 0.1  
V
IL  
REF  
Input Leakage Current  
Output Leakage Current  
Input Reference Voltage  
GND V V  
5  
5  
5
µA  
µA  
V
X
I
DDQ  
I
GND V V  
Output Disabled  
5
OZ  
I
DDQ,  
[20]  
V
Typical Value = 0.75V  
0.68  
0.75  
0.95  
500  
550  
600  
240  
260  
280  
REF  
I
V
Operating Supply  
V
= Max., I  
= 0 mA, 167 MHz  
200 MHz  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
CYC  
f = f  
= 1/t  
MAX  
250 MHz  
I
Automatic Power-down  
Current  
Max. V , Both Ports  
167 MHz  
200 MHz  
250 MHz  
SB1  
DD  
Deselected, V V or  
IN  
IH  
= 1/t  
V
V f = f  
Inputs Static  
IN  
IL  
MAX CYC,  
AC Input Requirements Over the Operating Range  
Parameter Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min.  
+ 0.2  
REF  
Typ.  
Max.  
Unit  
V
V
V
V
IH  
V
- 0.2  
V
IL  
REF  
Capacitance[21]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
C
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
6
7
pF  
pF  
pF  
IN  
A
V
V
= 1.8V  
DD  
Clock Input Capacitance  
Output Capacitance  
CLK  
= 1.5V  
DDQ  
O
Notes:  
17. Output are impedance controlled. I = –(V  
/2)/(RQ/5) for values of 175<= RQ <= 350s.  
OH  
DDQ  
18. Output are impedance controlled. I = (V  
/2)/(RQ/5) for values of 175<= RQ <= 350.  
OL  
DDQ  
19. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
DD  
DD  
IH  
DD  
DDQ  
20. V  
(Min.) = 0.68V or 0.46V  
, whichever is larger, V  
(Max.) = 0.95V or 0.54V  
, whichever is smaller.  
REF  
DDQ  
REF  
DDQ  
21. Tested initially and after any design or process change that may affect these parameters.  
Document #: 001-00350 Rev. *A  
Page 17 of 23  
CY7C1292DV18  
CY7C1294DV18  
Thermal Resistance[21]  
Parameter  
Description  
Test Conditions  
165 FBGA  
28.51  
Unit  
°C/W  
°C/W  
Θ
Θ
Thermal Resistance (Junction to Ambient) Test conditions follow standard test  
JA  
JC  
methods and procedures for measuring  
thermal impedance, per EIA/JESD51.  
Thermal Resistance (Junction to Case)  
5.91  
AC Test Loads and Waveforms  
V
REF = 0.75V  
0.75V  
VREF  
VREF  
0.75V  
R = 50Ω  
OUTPUT  
[22]  
ALL INPUT PULSES  
1.25V  
Z = 50Ω  
0
OUTPUT  
Device  
R = 50Ω  
L
0.75V  
Under  
Device  
Under  
0.25V  
Test  
5 pF  
VREF = 0.75V  
Slew Rate = 2 V/ns  
ZQ  
Test  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
(a)  
(b)  
Note:  
22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250, V  
= 1.5V, input  
DDQ  
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.  
OL OH  
Document #: 001-00350 Rev. *A  
Page 18 of 23  
CY7C1292DV18  
CY7C1294DV18  
[22, 23]  
Switching Characteristics Over the Operating Range  
250 MHz  
200 MHz  
167 MHz  
Cypress Consortium  
Parameter Parameter  
Description  
Min. Max. Min. Max. Min. Max. Unit  
[24]  
t
t
t
t
t
t
t
t
V (Typical) to the first Access  
DD  
1
1
1
ms  
ns  
ns  
ns  
POWER  
CYC  
KH  
KHKH  
KHKL  
KLKH  
KHKH  
K Clock and C Clock Cycle Time  
Input Clock (K/K and C/C) HIGH  
Input Clock (K/K and C/C) LOW  
4.0  
1.6  
1.6  
6.3  
5.0  
2.0  
2.0  
7.9  
6.0  
2.4  
2.4  
7.9  
KL  
K Clock Rise to K Clock Rise and C to C Rise  
(rising edge to rising edge)  
t
t
t
t
1.8  
0.0  
2.2  
0.0  
2.7  
0.0  
ns  
ns  
KHKH  
KHCH  
K/K Clock Rise to C/C Clock Rise  
(rising edge to rising edge)  
1.8  
2.2  
2.7  
KHCH  
KHKH  
Set-up Times  
t
t
t
t
Address Set-up to Clock (K/K) Rise  
0.35  
0.35  
0.4  
0.4  
0.5  
0.5  
ns  
ns  
SA  
SC  
AVKH  
IVKH  
Control Set-up to K Clock Rise (RPS, WPS)  
Double Data Rate Control Set-up to Clock  
t
t
t
t
(K/K) Rise (BWS , BWS , BWS , BWS )  
0.35  
0.35  
0.4  
0.4  
0.5  
0.5  
ns  
ns  
SCDDR  
IVKH  
0
1
3
4
D
Set-up to Clock (K/K) Rise  
SD  
DVKH  
[X:0]  
Hold Times  
t
t
t
0.35  
0.35  
0.4  
0.4  
0.5  
0.5  
ns  
ns  
Address Hold after Clock (K/K) Rise  
HA  
KHAX  
t
Control Hold after K Clock Rise (RPS, WPS)  
Double Data Rate Control Hold after Clock  
HC  
KHIX  
t
t
t
t
(K/K) Rise (BWS , BWS , BWS , BWS )  
0.35  
0.35  
0.4  
0.4  
0.5  
0.5  
ns  
ns  
HCDDR  
KHIX  
0
1
3
4
D
Hold after Clock (K/K) Rise  
HD  
KHDX  
[X:0]  
Output Times  
C/C Clock Rise (or K/K in Single Clock Mode)  
to Data Valid  
t
t
0.45  
0.45  
0.50  
ns  
CO  
CHQV  
Data Output Hold after Output C/C Clock Rise  
(Active to Active)  
t
t
t
t
t
t
t
t
t
t
–0.45  
0.45  
-0.45  
0.45  
-0.50  
0.50  
ns  
ns  
ns  
ns  
ns  
DOH  
CHQX  
C/C Clock Rise to Echo Clock Valid  
Echo Clock Hold after C/C Clock Rise  
Echo Clock High to Data Valid  
Echo Clock High to Data Invalid  
Clock (C/C) Rise to High-Z  
CCQO  
CQOH  
CQD  
CHCQV  
CHCQX  
CQHQV  
CQHQX  
–0.45  
–0.45  
–0.50  
0.30  
0.35  
0.40  
–0.30  
–0.35  
–0.40  
CQDOH  
[25,26]  
t
t
t
t
0.45  
0.45  
0.50  
ns  
ns  
(Active to High-Z)  
CHZ  
CHQZ  
[25,26]  
–0.45  
–0.45  
–0.50  
Clock (C/C) Rise to Low-Z  
CLZ  
CHQX1  
DLL Timing  
t
t
t
t
t
t
Clock Phase Jitter  
0.20  
0.20  
0.20  
ns  
cycles  
ns  
KC Var  
KC Var  
DLL Lock Time (K, C)  
K Static to DLL Reset  
1024  
30  
1024  
30  
1024  
30  
KC lock  
KC lock  
KC Reset  
KC Reset  
Notes:  
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,  
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.  
24. This part has a voltage regulator internally; t  
can be initiated.  
is the time that the power needs to be supplied above V minimum initially before a read or write operation  
DD  
POWER  
25. t  
, t  
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.  
CHZ CLZ  
26. At any given voltage and temperature t  
is less than t  
and t  
less than t  
.
CO  
CHZ  
CLZ  
CHZ  
Document #: 001-00350 Rev. *A  
Page 19 of 23  
CY7C1292DV18  
CY7C1294DV18  
Switching Waveforms[27, 28, 29]  
Read/Write/Deselect Sequence  
READ  
WRITE  
2
READ  
3
WRITE  
4
WRITE  
6
WRITE  
8
NOP  
READ  
NOP  
7
1
5
9
10  
K
t
t
KHKH  
t
t
CYC  
KH  
KL  
K
RPS  
t
t
SC  
HC  
WPS  
A
A2  
A3  
A4  
A0  
A1  
A5  
A6  
t
t
t
t
SA HA  
SA HA  
D
Q
D31  
t
D10  
D11  
D30  
D50  
D51  
D60  
D61  
t
t
t
SD  
HD  
SD  
HD  
Q20  
CQDOH  
Q00  
Q01  
DOH  
Q21  
Q40  
Q41  
t
t
CLZ  
t
t
CHZ  
t
KHCH  
t
t
KL  
t
CO  
CQD  
t
C
C
KH  
t
t
KHKH  
CYC  
t
KHCH  
t
CCQO  
t
CQOH  
t
CQ  
CQ  
CCQO  
t
CQOH  
DON’T CARE  
UNDEFINED  
Notes:  
27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.  
28. Output are disabled (High-Z) one clock cycle after a NOP.  
29. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole  
diagram.  
Document #: 001-00350 Rev. *A  
Page 20 of 23  
CY7C1292DV18  
CY7C1294DV18  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
167 CY7C1292DV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1294DV18-167BZC  
Commercial  
CY7C1292DV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-167BZXC  
CY7C1292DV18-167BZI  
CY7C1294DV18-167BZI  
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
Industrial  
CY7C1292DV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-167BZXI  
200 CY7C1292DV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1294DV18-200BZC  
Commercial  
Industrial  
CY7C1292DV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-200BZXC  
CY7C1292DV18-200BZI  
CY7C1294DV18-200BZI  
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1292DV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-200BZXI  
250 CY7C1292DV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1294DV18-250BZC  
Commercial  
Industrial  
CY7C1292DV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-250BZXC  
CY7C1292DV18-250BZI  
CY7C1294DV18-250BZI  
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1292DV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1294DV18-250BZXI  
Document #: 001-00350 Rev. *A  
Page 21 of 23  
CY7C1292DV18  
CY7C1294DV18  
Package Diagram  
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
PIN 1 CORNER  
-0.06  
Ø0.50
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
B
13.00 0.10  
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDECREFERENCE: MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and  
Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 001-00350 Rev. *A  
Page 22 of 23  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1292DV18  
CY7C1294DV18  
Document History Page  
Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture  
Document Number: 001-00350  
Orig. of  
REV.  
**  
ECN No. Issue Date Change  
Description of Change  
380737  
485631  
See ECN  
See ECN  
SYT  
NXR  
New data sheet  
*A  
Converted from Preliminary to Final  
Removed 300MHz Speed Bin.  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed C/C Pin Description in the features section and Pin Description.  
Modified the ZQ Definition from Alternately, this pin can be connected directly  
to V to Alternately, this pin can be connected directly to V  
DD  
DDQ.  
Changed t and t from 40 ns to 20 ns, changed t  
, t  
, t , t  
,
TH  
TL  
TMSS TDIS CS TMSH  
t
, t from 10 ns to 5 ns and changed t  
from 20 ns to 10 ns in TAP  
TDIH CH  
TDOV  
AC Switching Characteristics table  
Added power-up sequence details and waveforms.  
Added foot notes #15 and 16 on page# 18.  
Included Maximum Ratings for Supply Voltage on V  
Relative to GND  
DDQ  
Changed the Maximum rating of Ambient Temperature with Power Applied  
from –10°C to +85°C to –55°C to +125°C  
Changed the Maximum Ratings for DC Input Voltage from V  
to V  
DD.  
DDQ  
Changed the description of I from Input Load Current to Input Leakage  
X
Current on page# 13.  
Modified the I and I values  
Modified test condition in Footnote #20 on page# 19 from V  
DD  
SB  
< V to  
DD  
DDQ  
V
< V  
DDQ  
DD.  
Changed the Min. Value of t and t from 0.5ns to 0.35ns for 250 MHz and  
SC  
HC  
0.6ns to 0.4ns for 200 MHz speed bins.  
Changed the description of t from K Clock Rise to Clock (K/K) Rise.  
SA  
Changed the description of t and t from Clock (K and K) Rise to K Clock  
SC  
HC  
Rise.  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
Updated the Ordering Information Table.  
Document #: 001-00350 Rev. *A  
Page 23 of 23  

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