CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Configurations
■ Separate independent read and write data ports
With Read Cycle Latency of 2.0 cycles:
❐ Supports concurrent transactions
CY7C1241V18 – 4M x 8
CY7C1256V18 – 4M x 9
CY7C1243V18 – 2M x 18
CY7C1245V18 – 1M x 36
■ 300 MHz to 375 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 750 MHz) at 375 MHz
Functional Description
■ Read latency of 2.0 clock cycles
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and
CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II+ architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn around” the data bus required with common IO
devices. Each port can be accessed through a common address
bus. Read and write addresses are latched on alternate rising
edges of the input (K) clock. Accesses to the QDR-II+ read and
write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit words
(CY7C1243V18), or 36-bit words (CY7C1245V18), that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate Port Selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core V = 1.8V ± 0.1V; IO V
= 1.4V to V
DD
DD
DDQ
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Delay Lock Loop (DLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
375 MHz
375
333 MHz
333
300 MHz
300
Unit
MHz
mA
1240
1120
1040
Note
1. The QDR consortium specification for V
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
DDQ
V
= 1.4V to V
.
DDQ
DD
Cypress Semiconductor Corporation
Document Number: 001-06365 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 12, 2008
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Logic Block Diagram (CY7C1243V18)
D
[17:0]
18
Write
Reg
Write Write
Write
Reg Reg
Address
Register
A
Reg
(18:0)
19
Address
Register
A
(18:0)
19
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
72
CQ
CQ
36
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
[17:0]
36
[1:0]
18
18
QVLD
Logic Block Diagram (CY7C1245V18)
D
[35:0]
36
Write Write Write Write
Address
Register
A
(17:0)
Reg
Reg Reg
Reg
18
Address
Register
A
(17:0)
18
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
144
CQ
CQ
72
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
72
[35:0]
[3:0]
36
36
QVLD
Document Number: 001-06365 Rev. *D
Page 3 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Configurations
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1241V18 (4M x 8)
1
2
3
6
9
10
11
5
7
8
4
NC/72M
A
NC/144M
A
A
CQ
A
CQ
WPS
NWS1
K
RPS
NC
NC
NC
NC
NC
D4
NC
NC
NC
A
NC/288M
K
NWS0
A
A
NC
NC
NC
NC
NC
NC
Q3
D3
NC
B
C
D
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
D5
Q4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D2
NC
Q2
NC
NC
ZQ
D1
NC
Q0
E
F
Q5
NC
NC
G
VREF
NC
NC
Q6
VDDQ
NC
VDDQ
NC
VREF
Q1
H
J
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D6
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
CY7C1256V18 (4M x 9)
1
2
NC/72M
NC
3
6
K
9
10
A
11
CQ
Q4
D4
NC
Q3
5
NC
7
8
4
WPS
A
CQ
NC
NC
NC
NC
A
NC/144M RPS
A
A
B
C
D
NC
NC
NC
Q5
NC/288M
A
K
BWS0
A
A
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
NC
VSS
VSS
VSS
D5
VSS
VSS
VSS
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D3
NC
E
F
NC
NC
NC
Q6
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
ZQ
D2
NC
Q1
NC
NC
G
H
J
VDDQ
NC
VREF
Q2
DOFF
NC
VREF
NC
NC
Q7
VDDQ
NC
NC
NC
D7
NC
NC
Q8
NC
NC
K
L
NC
NC
NC
NC
NC
NC
NC
D8
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
D0
D1
NC
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
Document Number: 001-06365 Rev. *D
Page 4 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1243V18 (2M x 18)
2
NC/144M
Q9
3
5
6
7
NC/288M
BWS0
A
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
1
4
8
A
A
A
B
C
D
E
F
CQ
NC
NC
NC
WPS
A
BWS1
NC
K
K
RPS
A
D9
NC
NC
NC
NC
D10
Q10
Q11
D12
Q13
VSS
VSS
A
NC
VSS
VSS
VSS
Q7
D11
VSS
VSS
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
D6
Q12
D13
NC
NC
NC
G
VDDQ
NC
VREF
NC
VDDQ
D14
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VREF
Q4
ZQ
D4
H
J
DOFF
NC
NC
NC
NC
NC
NC
NC
Q15
NC
Q14
D15
D16
Q16
Q17
VDDQ
VDDQ
VSS
VDD
VSS
VSS
A
VSS
VSS
VSS
A
VDD
VSS
VSS
A
VDDQ
VDDQ
VSS
NC
D3
NC
Q1
NC
D0
Q3
Q2
D2
D1
Q0
K
L
NC
NC
NC
NC
M
N
P
D17
NC
VSS
VSS
A
QVLD
A
A
A
A
A
A
A
R
TDO
A
A
TMS
TDI
TCK
NC
CY7C1245V18 (1M x 36)
7
1
2
3
8
9
A
10
NC/144M
11
CQ
Q8
D8
D7
4
5
6
K
NC/288M NC/72M
A
B
C
D
CQ
Q27
D27
D28
WPS
A
BWS2
BWS3
A
BWS1
BWS0
A
RPS
A
Q18
Q28
D20
D18
D19
Q19
K
D17
D16
Q16
Q17
Q7
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
D15
Q29
Q30
D30
D29
Q21
D22
VREF
Q31
D32
Q24
Q20
D21
Q22
VDDQ
D23
Q23
D24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q15
D14
Q13
VDDQ
D12
Q12
D11
D6
Q14
D13
VREF
Q4
Q6
Q5
D5
ZQ
D4
Q3
Q2
E
F
G
H
J
DOFF
D31
Q32
Q33
D33
D34
Q35
D3
K
L
Q11
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
Document Number: 001-06365 Rev. *D
Page 5 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Definitions
Pin Name
IO
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
D
Input-
[x:0]
Synchronous CY7C1241V18 − D
[7:0]
CY7C1256V18 − D
[8:0]
CY7C1243V18 − D
CY7C1245V18 − D
[17:0]
[35:0]
WPS
Input-
Synchronous active, a Write operation is initiated. Deasserting deselects the write port. Deselecting the write
port causes D to be ignored.
Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted
[x:0]
NWS ,
Input-
Synchronous the K and K clocks when write operations are active. Used to select which nibble is written into
the device during the current portion of the write operations. NWS controls D and NWS
Nibble Write Select 0, 1, Active LOW (CY7C1241V18 Only). Sampled on the rising edge of
NWS ,
0
1
0
[3:0]
1
controls D
.
[7:4]
All the nibble Write Selects are sampled on the same edge as the data. The corresponding nibble
of data is ignored by deselecting a nibble write select and is not written into the device.
BWS , BWS ,
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Selects which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
Input-
Synchronous
0
1
3
BWS , BWS
2
CY7C1256V18 − BWS controls D
0
[8:0]
[8:0]
CY7C1243V18 − BWS controls D
and BWS controls D
[17:9].
0
1
CY7C1245V18− BWS controls D
, BWS controls D
, BWS controls D
, and BWS
0
[8:0]
1
[17:9]
2
[26:18] 3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select ignores the corresponding byte of data and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
Synchronous tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1241V18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1256V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1243V18
and 1M x 36 (4 arrays each of 256K x 36) for CY7C1245V18. Therefore, only 20 address inputs
are needed to access the entire memoryarrayofCY7C1241V18 and CY7C1256V18, 19 address
inputs for CY7C1243V18, and 18 address inputs for CY7C1245V18. These inputs are ignored
when the appropriate port is deselected.
Q
Outputs-
Data Output Signals. These pins drive out the requested data during a read operation. Valid
[x:0]
Synchronous data is driven out on the rising edge of both the K and K clocks during read operations. When
the read port is deselected, Q
are automatically tri-stated.
[x:0]
CY7C1241V18 − Q
[7:0]
CY7C1256V18 − Q
[8:0]
CY7C1243V18 − Q
CY7C1245V18 − Q
[17:0]
[35:0]
RPS
Input-
Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of
four sequential transfers.
QVLD
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
indicator
and CQ.
Input-
Clock
Positive Input Clock Input. The rising edge of K captures synchronous inputs to the device
and drives out data through Q
rising edge of K.
when in single clock mode. All accesses are initiated on the
[x:0]
K
Input-
Clock
Negative Input Clock Input. K captures synchronous inputs being presented to the device and
drives out data through Q when in single clock mode.
[x:0]
Document Number: 001-06365 Rev. *D
Page 6 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Definitions (continued)
Pin Name
CQ
IO
Pin Description
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
CQ
ZQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
Input
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a
[x:0]
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
, which enables the minimum impedance mode. This pin cannot be connected directly to
V
DDQ
GND or left unconnected.
DOFF
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with QDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs,
NC/72M
NC/144M
NC/288M
N/A
N/A
N/A
V
Input-
REF
Reference and AC measurement points.
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.
DD
Ground
Ground for the Device.
SS
Power Supply Power Supply Inputs for the Outputs of the Device.
DDQ
Document Number: 001-06365 Rev. *D
Page 7 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Write Operations
Functional Overview
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and
CY7C1245V18 are synchronous pipelined Burst SRAMs
equipped with a read and a write port. The read port is dedicated
to read operations and the write port is dedicated to write opera-
tions. Data flows into the SRAM through the write port and out
through the read port. These devices multiplex the address
inputs to minimize the number of address pins required. By
having separate read and write ports, the QDR-II+ completely
eliminates the need to “turn around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1241V18, four 9-bit data transfers in the case of
CY7C1256V18, four 18-bit data transfers in the case of
CY7C1243V18, and four 36-bit data transfers in the case of
CY7C1245V18, in two clock cycles.
clock rise, the data presented to D
the lower 18-bit Write Data register, provided BWS
is latched and stored into
[17:0]
are both
[1:0]
asserted active. On the subsequent rising edge of the Negative
Input Clock (K), the information presented to D is also stored
[17:0]
are both asserted
into the Write Data register, provided BWS
[1:0]
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the Positive Input Clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the input clocks (K/K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
All synchronous data inputs (D
) inputs pass through input
[x:0]
Byte Write Operations
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q ) outputs pass through output
[x:0]
Byte Write operations are supported by the CY7C1243V18. A
Write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS and
registers controlled by the rising edge of the Input clocks (K and
K).
0
BWS , which are sampled with each set of 18-bit data words.
All synchronous control (RPS, WPS, BWS
) inputs pass
1
[x:0]
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and written
into the device. Deasserting the Byte Write Select input during
the data portion of a write allows the data stored in the device for
that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a Byte Write operation.
through input registers controlled by the rising edge of the input
clocks (K/K).
CY7C1243V18 is described in the following sections. The same
basic descriptions apply to CY7C1241V18, CY7C1256V18, and
CY7C1245V18.
Read Operations
Concurrent Transactions
The CY7C1243V18 is organized internally as 4 arrays of 512K x
18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
addresses presented to Address inputs are stored in the Read
address register. Following the next two K clock rising edges, the
corresponding lowest order 18-bit word of data is driven onto the
The read and write ports on the CY7C1243V18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, you can read
or write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Q
using K as the output timing reference. On the subse-
[17:0]
quent rising edge of K the next 18-bit data word is driven onto
the Q . This process continues until all four 18-bit data words
[17:0]
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port assumes priority (because read operations
cannot be initiated on consecutive cycles). If a write was initiated
on the previous cycle, the Read port assumes priority (because
write operations cannot be initiated on consecutive cycles).
Therefore, asserting both port selects active from a deselected
state results in alternating read/write operations being initiated,
with the first access being a read.
have been driven out onto Q
. The requested data is valid
[17:0]
0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
When the read port is deselected, the CY7C1243V18 first
completes the pending Read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the Positive Input Clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Document Number: 001-06365 Rev. *D
Page 8 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Depth Expansion
Valid Data Indicator (QVLD)
The CY7C1243V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
Programmable Impedance
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in QDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V to enable the SRAM to adjust its output
SS
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
the
application
note,
DLL
Considerations
in
of ±15% is between 175Ω and 350Ω, with V
= 1.5V. The
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of 30
ns. However, it is not necessary for the DLL to be reset to lock to
the desired frequency. During power up, when the DOFF is tied
HIGH, the DLL is locked after 2048 cycles of stable clock.
DDQ
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the QDR-II+. The timing for the
Document Number: 001-06365 Rev. *D
Page 9 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Application Example
Figure 1 shows the use of 4 QDR-II+ SRAMs in an application.
Figure 1. Application Example
RQ = 250ohms
RQ = 250ohms
ZQ
CQ/CQ
Q
ZQ
CQ/CQ
Q
Vt
SRAM #1
BWS
SRAM #4
D
A
D
A
R
K
RPS WPS
K
K
K
BWS
RPS WPS
DATA IN
DATA OUT
Address
R
R
Vt
Vt
RPS
BUS MASTER
WPS
BWS
(CPU or ASIC)
CLKIN/CLKIN
Source K
Source K
R = 50ohms, Vt = V
/2
DDQ
Truth Table
The truth table for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows.
Operation RPS WPS DQ DQ DQ
Write Cycle:
K
DQ
L-H
H
L
D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
[9]
Read Cycle:
L-H
L
X
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 3) ↑
(2.0 cycle Latency)
Load address on the
rising edge of K; wait
two cycle; read data
on two consecutive K
and K rising edges.
NOP: No Operation L-H
H
H
X
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock
Stopped
Stopped X
Previous State
Previous State
Previous State
Previous State
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device ignores
the second Read or Write request.
Document Number: 001-06365 Rev. *D
Page 10 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Write Cycle Descriptions
The write cycle description table for CY7C1241V18 and CY7C1243V18 follows.
BWS / BWS /
0
1
K
Comments
K
NWS
NWS
1
0
L
L
L
L
L–H
–
During the data portion of a write sequence:
CY7C1241V18 − both nibbles (D
) are written into the device.
[7:0]
CY7C1243V18 − both bytes (D
) are written into the device.
[17:0]
–
L–H
–
L-H During the data portion of a write sequence:
CY7C1241V18 − both nibbles (D
) are written into the device.
) are written into the device.
[7:0]
CY7C1243V18 − both bytes (D
[17:0]
L
H
H
L
–
During the data portion of a write sequence:
CY7C1241V18 − only the lower nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
[17:9]
CY7C1243V18 − only the lower byte (D
[8:0]
L
L–H During the data portion of a write sequence:
CY7C1241V18 − only the lower nibble (D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
CY7C1243V18 − only the lower byte (D
) is written into the device, D
[8:0]
[17:9]
H
H
L–H
–
–
During the data portion of a write sequence:
CY7C1241V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
remains unaltered.
[7:4]
[3:0]
[8:0]
CY7C1243V18 − only the upper byte (D
[17:9]
L
L–H During the data portion of a write sequence:
CY7C1241V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
remains unaltered.
[7:4]
[3:0]
[8:0]
CY7C1243V18 − only the upper byte (D
[17:9]
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1256V18 follows.
BWS
K
L–H
–
K
Comments
During the data portion of a write sequence, the single byte (D
0
L
L
–
) is written into the device.
) is written into the device.
[8:0]
L–H During the data portion of a write sequence, the single byte (D
[8:0]
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Note
10. Assumes a write cycle was initiated per the Write Cycle Description Table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered in different portions of
0
1
0
1
2
3
a write cycle, as long as the setup and hold requirements are met.
Document Number: 001-06365 Rev. *D
Page 11 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Write Cycle Descriptions
The write cycle description table for CY7C1245V18 follows.
BWS
BWS
BWS
BWS
3
K
K
Comments
0
1
2
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D
into the device.
) are written
) are written
[35:0]
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D
into the device.
[35:0]
–
During the data portion of a write sequence, only the lower byte (D
) is
) is
[8:0]
written into the device. D
remains unaltered.
[35:9]
L
L–H During the data portion of a write sequence, only the lower byte (D
written into the device. D remains unaltered.
[8:0]
[35:9]
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written
) is written
[17:9]
into the device. D
and D
remain unaltered.
[8:0]
[35:18]
L
L–H During the data portion of a write sequence, only the byte (D
into the device. D and D remain unaltered.
[17:9]
[8:0]
[35:18]
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written
) is written
) is written
) is written
[26:18]
[26:18]
[35:27]
[35:27]
into the device. D
and D
remain unaltered.
[17:0]
[35:27]
L
L–H During the data portion of a write sequence, only the byte (D
into the device. D and D remain unaltered.
[17:0]
[35:27]
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
into the device. D remains unaltered.
[26:0]
L
L–H During the data portion of a write sequence, only the byte (D
into the device. D remains unaltered.
[26:0]
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06365 Rev. *D
Page 12 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in “TAP Controller Block Diagram” on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
feature. To disable the TAP controller, tie TCK LOW (V ) to
SS
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to V through a pull up resistor. TDO must be left unconnected.
Upon power up, the device comes up in a reset state which does
not interfere with the operation of the device.
Bypass Register
DD
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This shifts data through the SRAM with minimal
delay. The bypass register is set LOW (V ) when the BYPASS
instruction is executed.
Test Access Port – Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SS
Boundary Scan Register
Test Mode Select
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the “TAP Controller State
Diagram” on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
“Boundary Scan Order” on page 19 shows the order in which the
bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends upon the current
state of the TAP state machine (see “Instruction Codes” on
page 18). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V ) for five rising
TAP Instruction Set
DD
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Document Number: 001-06365 Rev. *D
Page 13 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register upon
power up or whenever the TAP controller is in a Test-Logic-Reset
state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is issued during the
Update-IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, although the SRAM clock operates
more than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
To guarantee that the boundary scan register captures the cor-
rect value of a signal, the SRAM signal must be stabilized long
enough to meet the TAP controller's capture setup plus hold
times (t and t ). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
CS
CH
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-06365 Rev. *D
Page 14 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
TAP Controller State Diagram
The state diagram for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows.
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06365 Rev. *D
Page 15 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
108 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
= −2.0 mA
Min
1.4
1.6
Max
Unit
V
V
V
V
V
V
V
I
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
I
I
I
I
OH1
OH2
OL1
OL2
IH
OH
OH
OL
OL
= −100 μA
= 2.0 mA
V
0.4
0.2
V
= 100 μA
V
0.65V
V
+ 0.3
V
DD
DD
Input LOW Voltage
–0.3
–5
0.35V
5
V
IL
DD
Input and Output Load Current
GND ≤ V ≤ V
DD
μA
X
I
Notes
12. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 21.
13. Overshoot: V (AC) < V + 0.3V (pulse width less than t /2).
/2). Undershoot: V (AC) > − 0.3V (pulse width less than t
IH
DDQ
CYC
IL
CYC
14. All voltage refers to Ground.
Document Number: 001-06365 Rev. *D
Page 16 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Description
Min
Max
Unit
ns
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
TCYC
TF
20
MHz
ns
20
20
TH
TCK Clock LOW
ns
TL
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
TDOV
TDOX
0
TAP Timing and Test Conditions[16]
0.9V
ALL INPUT PULSES
0.9V
50Ω
1.8V
TDO
0V
Z = 50Ω
0
C = 20 pF
L
t
t
TL
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
15. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
16. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 001-06365 Rev. *D
Page 17 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Identification Register Definitions
Value
Instruction
Field
Description
CY7C1241V18
CY7C1256V18
000
CY7C1243V18
000
CY7C1245V18
Revision
000
000
Version number.
Number (31:29)
Cypress Device 11010010101000111 11010010101001111 11010010101010111 11010010101100111 Defines the type
ID (28:12)
of SRAM.
Cypress JEDEC
ID (11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Enables unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an
ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input/output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input/output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input/output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document Number: 001-06365 Rev. *D
Page 18 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-06365 Rev. *D
Page 19 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Power Up Sequence in QDR-II+ SRAM
DLL Constraints
QDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
.
KC Var
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. Toavoid this, provide 2048 cycles stable clock
to relock to the clock frequency you want.
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply V before V
DD
DDQ
❐ Apply V
before V
or at the same time as V
DDQ
REF REF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
Power Up Waveforms
Figure 2. Power Up Waveforms
K
K
Start Normal
Operation
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after V /V
DD DDQ
is Stable)
V
/V
+
V
/V Stable (< 0.1V DC per 50 ns)
DD DDQ
DD DDQ
Fix HIGH (tie to V
DDQ
)
DOFF
Document Number: 001-06365 Rev. *D
Page 20 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch Up Current .................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ........–0.5V to +2.9V
DD
Ambient
Supply Voltage on V
Relative to GND..... –0.5V to + V
DD
DDQ
Range Temperature (T )
V
V
DDQ
A
DD
DC Applied to Outputs in High-Z ........–0.5V to V
+ 0.3V
DDQ
Com’l
Ind’l
0°C to +70°C
1.8 ± 0.1V
1.4V to V
DD
DC Input Voltage ...............................–0.5V to V + 0.3V
DD
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
1.7
1.4
Typ
Max
Unit
V
V
1.8
1.5
1.9
DD
V
V
V
V
V
V
V
I
V
V
DDQ
OH
DD
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
V
V
/2 – 0.12
/2 – 0.12
– 0.2
V
V
/2 + 0.12
/2 + 0.12
V
DDQ
DDQ
V
OL
DDQ
DDQ
I
= −0.1 mA, Nominal Impedance
V
V
V
OH(LOW)
OL(LOW)
IH
OH
OL
DDQ
DDQ
I
= 0.1 mA, Nominal Impedance
V
0.2
V
SS
V
+ 0.1
V
+ 0.15
V
REF
DDQ
–0.15
V
– 0.1
V
IL
REF
Input Leakage Current
Output Leakage Current
Input Reference Voltage
GND ≤ V ≤ V
−2
−2
2
μA
μA
V
X
I
DDQ
I
GND ≤ V ≤ V
Output Disabled
2
OZ
I
DDQ,
V
Typical Value = 0.75V
0.68
0.75
0.95
1040
1120
1240
280
REF
I
V
Operating Supply
V
= Max., I
= 0mA, 300 MHz
333 MHz
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
f = f
= 1/t
MAX
375 MHz
I
Automatic Power down
Current
Max. V , Both Ports
300 MHz
333 MHz
375 MHz
SB1
DD
Deselected, V ≥ V or
IN
IH
300
V
≤ V , f = f
Inputs Static
= 1/t
,
IN
IL
MAX
CYC
310
AC Electrical Characteristics
Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Typ
–
Max
Unit
V
V
V
+ 0.2
V
+ 0.24
DDQ
IH
IL
REF
V
–0.24
–
V
– 0.2
V
REF
Notes
17. Power up: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
DD.
DD
IH
DD
DDQ
18. Outputs are impedance controlled. I = −(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
OH
DDQ
19. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
DDQ
OL
20. V
(min) = 0.68V or 0.46V
, whichever is larger; V
(max) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
21. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-06365 Rev. *D
Page 21 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
Unit
pF
C
5
4
5
IN
A
V
= 1.8V
DD
V
C
C
Clock Input Capacitance
Output Capacitance
pF
CLK
O
= 1.5V
DDQ
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.25
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
2.91
°C/W
JC
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
22. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
REF
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
Document Number: 001-06365 Rev. *D
Page 22 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Switching Characteristics
Over the Operating Range
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max
t
t
t
t
t
V
(Typical) to the First Access
1
–
1
–
1
–
ms
ns
POWER
CYC
KH
DD
t
t
t
t
K Clock Cycle Time
2.66 8.4 3.0 8.4 3.3 8.4
KHKH
KHKL
KLKH
KHKH
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
t
t
CYC
KL
CYC
K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13
1.28
1.40
ns
KHKH
Set-up Times
t
t
t
t
t
t
Address Set-up to K Clock Rise
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
SA
AVKH
IVKH
IVKH
Control Set-up to K Clock Rise (RPS, WPS)
Double Data Rate Control Set-up to Clock (K, K) Rise
SC
0.28
0.28
0.28
SCDDR
(BWS , BWS BWS , BWS )
0
1,
2
3
t
t
D Set-up to Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
ns
SD
DVKH
Hold Times
t
t
t
t
t
t
Address Hold after K Clock Rise
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
HA
KHAX
KHIX
KHIX
Control Hold after K Clock Rise (RPS, WPS)
Double Data Rate Control Hold after Clock (K/K) Rise
HC
0.28
0.28
0.28
HCDDR
(BWS , BWS BWS , BWS )
0
1,
2
3
t
t
D Hold after Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
ns
HD
KHDX
Output Times
t
t
t
t
K/K Clock Rise to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
CO
CHQV
CHQX
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.45
–0.45
–0.45
DOH
t
t
t
t
t
t
t
t
t
t
t
t
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
CCQO
CQOH
CQD
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
–0.45
–0.45
–0.45
0.2
–
0.2
–
0.2
–
Echo Clock High to Data Invalid
–0.2
0.88
0.88
–0.2
1.03
1.03
–0.2
1.15
1.15
CQDOH
CQH
Output Clock (CQ/CQ) HIGH
–
–
–
CQ Clock Rise to CQ Clock Rise
–
–
–
CQHCQH
(rising edge to rising edge)
t
t
t
t
t
t
Clock (K/K) Rise to High-Z (Active to High-Z)
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
CHZ
CLZ
CHQZ
Clock (K/K) Rise to Low-Z
–0.45
–0.45
–0.45
CHQX1
CQHQVLD
Echo Clock High to QVLD Valid
–0.20 0.20 –0.20 0.20 –0.20 0.20
QVLD
DLL Timing
t
t
t
t
t
t
Clock Phase Jitter
DLL Lock Time (K)
–
0.20
–
–
0.20
–
–
0.20
–
ns
KC Var
KC Var
2048
30
2048
30
2048
30
Cycles
ns
KC lock
KC Reset
KC lock
KC Reset
K Static to DLL Reset
–
–
–
Notes
23. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
being operated and outputs data with the output timing of that frequency range.
24. This part has an internal voltage regulator; t
be initiated.
is the time that the power must be supplied above V minimum initially before a read or write operation can
DD
POWER
25. These parameters are extrapolated from the input timing parameters (t
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) is already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production.
KHKH
26. t
, t
are specified with a load capacitance of 5 pF as in part (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ±100 mV from
CHZ CLZ
steady-state voltage.
27. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
28. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
29. Hold to >V or <V .
IH
IL
Document Number: 001-06365 Rev. *D
Page 23 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Switching Waveforms
Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency
NOP
1
READ
2
WRITE
3
READ
4
WRITE
5
NOP
6
7
8
K
t
t
t
t
KH
KL
CYC
KHKH
K
RPS
t
t
SC HC
t
t
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
t
t
HD
SA HA
t
SD
t
SD
D10
D11
D12
D13
D30
D31
D32
D33
D
t
QVLD
t
QVLD
QVLD
t
DOH
t
t
CQDOH
CO
t
t
CHZ
t
CLZ
CQD
Q
Q22
Q01
Q02
Q23
Q00
t
Q03 Q20 Q21
(Read Latency = 2.0 Cycles)
CCQO
CQOH
CQ
CQ
CCQO
t
t
t
CQHCQH
CQH
CQOH
DON’T CARE
UNDEFINED
Notes
30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
31. Outputs are disabled (High-Z) one clock cycle after a NOP.
32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
Document Number: 001-06365 Rev. *D
Page 24 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
375 CY7C1241V18-375BZC
CY7C1256V18-375BZC
CY7C1243V18-375BZC
CY7C1245V18-375BZC
CY7C1241V18-375BZXC
CY7C1256V18-375BZXC
CY7C1243V18-375BZXC
CY7C1245V18-375BZXC
CY7C1241V18-375BZI
CY7C1256V18-375BZI
CY7C1243V18-375BZI
CY7C1245V18-375BZI
CY7C1241V18-375BZXI
CY7C1256V18-375BZXI
CY7C1243V18-375BZXI
CY7C1245V18-375BZXI
333 CY7C1241V18-333BZC
CY7C1256V18-333BZC
CY7C1243V18-333BZC
CY7C1245V18-333BZC
CY7C1241V18-333BZXC
CY7C1256V18-333BZXC
CY7C1243V18-333BZXC
CY7C1245V18-333BZXC
CY7C1241V18-333BZI
CY7C1256V18-333BZI
CY7C1243V18-333BZI
CY7C1245V18-333BZI
CY7C1241V18-333BZXI
CY7C1256V18-333BZXI
CY7C1243V18-333BZXI
CY7C1245V18-333BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06365 Rev. *D
Page 25 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
300 CY7C1241V18-300BZC
CY7C1256V18-300BZC
CY7C1243V18-300BZC
CY7C1245V18-300BZC
CY7C1241V18-300BZXC
CY7C1256V18-300BZXC
CY7C1243V18-300BZXC
CY7C1245V18-300BZXC
CY7C1241V18-300BZI
CY7C1256V18-300BZI
CY7C1243V18-300BZI
CY7C1245V18-300BZI
CY7C1241V18-300BZXI
CY7C1256V18-300BZXI
CY7C1243V18-300BZXI
CY7C1245V18-300BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
Commercial
Industrial
Document Number: 001-06365 Rev. *D
Page 26 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Package Diagram
Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
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Document Number: 001-06365 Rev. *D
Page 27 of 28
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Document History Page
Document Title: CY7C1241V18/CY7C1256V18/CY7C1243V18/CY7C1245V18, 36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Document Number: 001-06365
ISSUE
DATE
ORIG. OF
CHANGE
REV.
ECN NO.
DESCRIPTION OF CHANGE
**
425689
461639
See ECN
See ECN
NXR
NXR
New Data Sheet
*A
Revised the MPNs from
CY7C1256AV18 to CY7C1256V18
CY7C1243AV18 to CY7C1243V18
CY7C1245AV18 to CY7C1245V18
Changed t and t from 40 ns to 20 ns, changed t
, t
, t
,
TH
TL
TMSS TDIS CS
t
, t
, t from 10 ns to 5 ns and changed t
from 20 ns to 10
TMSH TDIH CH
TDOV
ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
*B
497628
See ECN
NXR
Changed the V
operating voltage to 1.4V to V in the Features
DDQ DD
section, in Operating Range table and in the DC Electrical Characteristics
table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power
Applied from –10°C to +85°C to –55°C to +125°C
Changed V
(Max.) spec from 0.85V to 0.95V in the DC Electrical
REF
Characteristics table and in the note below the table
Updated footnote #20 to specify Overshoot and Undershoot Spec
Updated Θ and Θ values
JA
JC
Removed x9 part and its related information
Updated footnote #25
*C
1072841
See ECN VKN/KKVTMP Converted from preliminary to final
Added x8 and x9 parts
Changed I values from 950 mA to 1240 mA for 375 MHz, 850 mA to
DD
1120 mA for 333 MHz, 800 mA to 1040 mA for 300 MHz
Changed I values from 300 mA to 310 mA for 375 MHz, 275 mA to 300
SB
mA for 333 MHz, 250 mA to 280 mA for 300 MHz
Changed t
max spec to 8.4 ns for all speed bins
CYC
Changed Θ value from 12.43 °C/W to 16.25 °C/W
JA
Updated Ordering Information table
*D
2198506
See ECN
VKN/AESA Added footnote# 21related to I
DD
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06365 Rev. *D
Revised March 12, 2008
Page 28 of 28
QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All
product and company names mentioned in this document are the trademarks of their respective holders.
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