CY7C1215H
1-Mbit (32K x 32) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 32K × 32 common I/O architecture
The CY7C1215H SRAM integrates 32K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 3.3V core power supply (V
)
DD
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
)
DDQ
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
1
2
3
— 3.5 ns (for 166-MHz device)
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW , and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
[A:D]
• Provide high-performance 3-1-1-1 access rate
®
• User-selectable burst counter supporting Intel
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode Option
The CY7C1215H operates from a +3.3V core power supply
while all outputs may operate either with a + 2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
Q1
MODE
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQD
BYTE
WRITE REGISTER
DQD
BYTE
WRITE DRIVER
BWD
BWC
DQC
BYTE
WRITE DRIVER
DQC
BYTE
WRITE REGISTER
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
SENSE
AMPS
DQ s
DQB
BYTE
WRITE DRIVER
E
DQB
BYTE
WRITE REGISTER
BWB
DQA
BYTE
WRITE DRIVER
DQA
BYTE
WRITE REGISTER
BWA
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05666 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2006
CY7C1215H
Pin Definitions
Name
I/O
Input-
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A
0
Description
A , A , A
Address Inputs used to select one of the 32K address locations. Sampled at the rising edge
0
1
1
2
3
1
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
BW , BW
Input-
A
B
BW , BW
C
D
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous Write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
BWE
CLK
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE
CE
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
1
2
3
Synchronous CE and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only
2
3
1
1
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device. CE is sampled only when a new external address is
1
3
2
loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Not connected for BGA. Where referenced, CE is
Synchronous CE and CE to select/deselect the device.
1
2
3
CE is sampled only when a new external
assumed active throughout this document for BGA.
address is loaded.
3
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a Read cycle when emerging from a
deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, A is captured in the address registers. A , A are also loaded into the burst counter.
1
0
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
is deasserted HIGH.
1
ADSC
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, A is captured in the address registers. A , A are also loaded into the burst counter.
1
0
When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are
placed in a tri-state condition.
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
Ground
Ground for the core of the device.
SS
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
V
I/O Ground Ground for the I/O circuitry.
SSQ
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left
DD
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M
and 1G are address expansion pins and are not internally connected to the die.
Document #: 38-05666 Rev. *B
Page 3 of 15
CY7C1215H
signals. The CY7C1215H provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Write (BW
) input, will selectively write to only the desired
[A:D]
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
The CY7C1215H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1215H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE , CE , CE are all asserted active, and
1
2
3
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW ) are asserted active to conduct a Write to the
Byte Write operations are qualified with the Byte Write Enable
[A:D]
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQ is written into the corre-
sponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
(BWE) and Byte Write Select (BW
) inputs. A Global Write
[A:D]
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE , CE , CE ) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
1
2
3
1
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
Because the CY7C1215H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
(2) CE , CE , CE are all asserted active, and (3) the Write
1
2
3
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE is HIGH. The address presented to the address inputs (A)
1
is stored into the address advancement logic and the address
register while being presented to the memory array. The corre-
sponding data is allowed to propagate to the input of the output
registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
Burst Sequences
The CY7C1215H provides a two-bit wraparound counter, fed
by A , A , that implements either an interleaved or linear burst
1
0
data bus within t
if OE is active LOW. The only exception
CO
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
Read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output will tri-state immediately.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Single Write Accesses Initiated by ADSP
Sleep Mode
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
(2) CE , CE , CE are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
1
2
3
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
) and
[A:D]
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must
1
2
3
remain inactive for the duration of t
returns LOW.
after the ZZ input
ZZREC
then the Write operation is controlled by BWE and BW
[A:D]
Document #: 38-05666 Rev. *B
Page 4 of 15
CY7C1215H
Linear Burst Address Table
(MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A , A
Second
Address
A , A
Third
Fourth
Address
A , A
First
Address
A , A
Second
Address
A , A
Third
Address
A , A
Fourth
Address
A , A
Address
A , A
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
00
01
10
11
00
01
10
11
01
10
11
10
11
00
11
00
01
00
01
10
01
10
11
00
11
10
11
00
01
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > V – 0.2V
Min.
Max.
40
Unit
mA
ns
I
t
t
t
t
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ recovery time
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Truth Table[2, 3, 4, 5, 6]
Next Cycle
Unselected
Add. Used
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE
H
L
CE
X
X
L
CE
X
H
X
H
X
L
ADSP
X
ADSC
L
ADV
X
OE
X
X
X
X
X
X
X
H
L
DQ
Write
X
1
2
3
None
None
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
DQ
Unselected
L
X
X
X
Unselected
None
L
L
X
X
X
Unselected
None
L
X
L
H
H
L
L
X
X
Unselected
None
L
L
X
X
Begin Read
External
External
Next
L
H
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
Begin Read
L
L
H
H
H
X
L
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
H
H
X
X
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Next
L
Next
L
H
L
Tri-State
DQ
Next
X
L
Current
Current
Current
Current
Current
Current
External
Next
H
H
X
H
H
H
H
H
H
X
H
L
Tri-State
DQ
H
L
Tri-State
DQ
X
H
X
X
X
X
X
Tri-State
Tri-State
Tri-State
Tri-State
Begin Write
Begin Write
H
H
Continue Write
X
X
H
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW ,BW ,BW ,BW ) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
A
B
C
D
(BW ,BW ,BW ,BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05666 Rev. *B
Page 5 of 15
CY7C1215H
Truth Table for Read/Write[2, 3]
Function
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
GW
BWE
L
BW
H
X
H
X
X
H
H
H
H
H
H
H
H
L
BW
X
X
X
X
X
H
H
H
H
L
BW
X
X
X
X
X
H
H
L
BW
A
D
C
B
Next
X
H
X
X
X
H
L
Current
L
Current
L
None
H
H
H
L
Read
Read
H
Write Byte A – DQ
H
L
A
Write Byte B – DQ
Write Bytes B, A
H
L
H
L
B
H
L
L
Write Byte C – DQ
Write Bytes C, A
Write Bytes C, B
H
L
H
H
L
H
L
C
H
L
L
H
L
L
H
L
Write Bytes C, B, A
H
L
L
L
Write Byte D – DQ
Write Bytes D, A
Write Bytes D, B
H
L
H
H
H
H
L
H
H
L
H
L
D
H
L
L
H
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
H
L
L
L
H
L
L
H
H
L
H
L
H
L
L
L
H
L
L
L
H
L
H
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Document #: 38-05666 Rev. *B
Page 6 of 15
CY7C1215H
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage on V Relative to GND....... –0.5V to + 4.6V
DD
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
V
DDQ
Supply Voltage on V
Relative to GND .....–0.5V to + V
DD
DD
DDQ
3.3V
–5%/+10%
2.5V –5%
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
to V
+ 0.5V
DD
DDQ
[7, 8]
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
3.6
Unit
V
Power Supply Voltage
3.135
V
DD
V
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O
for 2.5V I/O
3.135
2.375
2.4
V
V
V
DDQ
DD
2.625
V
V
V
V
I
for 3.3V I/O, I = –4.0 mA
V
OH
OL
IH
OH
for 2.5V I/O, I = –1.0 mA
2.0
V
OH
for 3.3V I/O, I = 8.0 mA
0.4
0.4
V
OL
for 2.5V I/O, I = 1.0 mA
V
OL
[7]
Input HIGH Voltage
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
2.0
1.7
V
V
+ 0.3V
V
DD
DD
+ 0.3V
V
[7]
Input LOW Voltage
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Leakage Current GND ≤ V ≤ V
except ZZ and MODE
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–5
µA
µA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
µA
SS
DD
30
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
–5
µA
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
6-ns cycle,166 MHz
240
225
100
90
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
7.5-ns cycle, 133 MHz
6-ns cycle,166 MHz
7.5-ns cycle, 133 MHz
I
I
I
I
Automatic CS
Power-down
Current—TTL Inputs
V = Max, Device Deselected,
DD
SB1
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
MAX CYC
Automatic CS
Power-down
Current—CMOS Inputs f = 0
V = Max, Device Deselected,
DD
All speeds
40
mA
SB2
SB3
SB4
V
≤ 0.3V or V > V – 0.3V,
IN
IN
DDQ
Automatic CS
Power-down
Current—CMOS Inputs f = f
V
V
= Max, Device Deselected, or 6-ns cycle,166 MHz
85
75
mA
mA
DD
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
7.5-ns cycle, 133 MHz
= 1/t
MAX
CYC
Automatic CS
Power-down
Current—TTL Inputs
V
V
= Max, Device Deselected,
All speeds
45
mA
DD
≥ V or V ≤ V , f = 0
IN
IH IN IL
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
8. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05666 Rev. *B
Page 7 of 15
CY7C1215H
Capacitance[9]
100 TQFP
Max.
Parameter
Description
Input Capacitance
Test Conditions
Unit
pF
C
T = 25°C, f = 1 MHz,
5
5
5
IN
A
V
= 3.3V.
DD
C
C
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
V
= 2.5V
DDQ
pF
Thermal Resistance[9]
100 TQFP
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
6.85
°C/W
JC
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
INCLUDING
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
(a)
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
1 ns
5 pF
R =1538Ω
≤
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05666 Rev. *B
Page 8 of 15
CY7C1215H
[10, 11]
Switching Characteristics Over the Operating Range
166 MHz
133 MHz
Parameter
Description
Min.
Max
Min.
Max
Unit
[12]
t
V
(Typical) to the First Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
CO
1.5
0
1.5
0
DOH
CLZ
[13, 14, 15]
Clock to Low-Z
[13, 14, 15]
Clock to High-Z
3.5
3.5
4.0
4.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[13, 14, 15]
OE LOW to Output Low-Z
0
0
[13, 14, 15]
OE HIGH to Output High-Z
3.5
4.0
Set-up Times
t
t
t
t
t
t
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW
Set-up before CLK Rise
[A:D]
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADH
ADVH
WEH
DH
GW, BWE, BW
Hold after CLK Rise
[A:D]
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CEH
Notes:
10. Timing reference level is 1.5V when V
= 3.3V and is 1.25 when V
= 2.5V.
DDQ
DDQ
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
POWER
DD
can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
14. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 38-05666 Rev. *B
Page 9 of 15
CY7C1215H
Switching Waveforms
[16]
Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05666 Rev. *B
Page 10 of 15
CY7C1215H
Switching Waveforms (continued)
[16, 17]
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
17.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW
.
[A:D]
Document #: 38-05666 Rev. *B
Page 11 of 15
CY7C1215H
Switching Waveforms (continued)
[16, 18, 19]
Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
19. GW is HIGH.
Document #: 38-05666 Rev. *B
Page 12 of 15
CY7C1215H
Switching Waveforms (continued)
[20, 21]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05666 Rev. *B
Page 13 of 15
CY7C1215H
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
100 CY7C1215H-100AXC
CY7C1215H-100AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
133 CY7C1215H-133AXC
CY7C1215H-133AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05666 Rev. *B
Page 14 of 15
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1215H
Document History Page
Document Title: CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM
Document Number: 38-05666
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
343896
430678
See ECN
See ECN
PCI
New Data Sheet
*A
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for V
relative to GND
DDQ
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Modified test condition from V < V to V < V
DD
IH
DD
IH
Replaced Package Name column with Package Diagram in the Ordering
Information table
*B
481916
See ECN
VKN
Converted from Preliminary to Final.
Updated the Ordering Information table.
Document #: 38-05666 Rev. *B
Page 15 of 15
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